XCR3128A [XILINX]
CPLD with Enhanced Clocking; CPLD具有增强的时钟
| 型号： | XCR3128A |
| 厂家： | 
XILINX, INC |
| 描述： | CPLD with Enhanced Clocking |
| 文件： | 总17页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTE
0
XCR3128A: 128 Macrocell
CPLD with Enhanced Clocking
0
14*
DS035 (v1.2) August 10, 2000
Product Specification
Features
Description
•
•
•
Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
3V, In-System Programmable (ISP) using a JTAG
interface
The XCR3128A CPLD (Complex Programmable Logic
Device) is a member of the CoolRunner® family of CPLDs
from Xilinx. These devices combine high speed and zero
power in a 128 macrocell CPLD. With the FZP design tech-
nique, the XCR3128A offers true pin-to-pin speeds of 7.5
ns, while simultaneously delivering power that is less than
100 µA at standby without the need for ‘turbo bits' or other
power-down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any competing
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the pat-
ented full CMOS FZP design technique.
-
-
On-chip supervoltage generation
ISP commands include: Enable, Erase, Program,
Verify
-
-
-
Supported by multiple ISP programming platforms
4-pin JTAG interface (TCK, TMS, TDI, TDO)
JTAG commands include: Bypass, Idcode
•
•
•
•
High-speed pin-to-pin delays of 7.5 ns
Ultra-low static power of less than 100 µA
5V tolerant I/Os to support mixed voltage systems
100% routable with 100% utilization while all pins and
all macrocells are fixed
Deterministic timing model that is extremely simple to
use
Up to 20 clocks available
Support for complex asynchronous clocking
Innovative XPLA™ architecture combines high-speed
with extreme flexibility
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
Advanced 0.35µ E2CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard
and Xilinx CAE tools
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high-speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated effi-
ciently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 1.5 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 9 ns from any pin to any
other pin. In addition, logic that is common to multiple out-
puts can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
•
•
•
•
•
•
•
•
•
•
•
•
Reprogrammable using industry standard device
programmers
Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
-
-
-
Programmable 3-state buffer
Asynchronous macrocell register preset/reset
Up to two, asynchronous clocks
The XCR3128A CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn-
opsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
•
Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
Available in TQFP and VQFP packages
Available in both commercial and industrial grades
Industrial grade operates from 2.7V to 3.6V
•
•
•
DS035 (v1.2) August 10, 2000
www.xilinx.com
1
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
The XCR3128A CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR3128A also includes an industry-standard, IEEE
1149.1, JTAG interface through which In-System Program-
ming (ISP) and reprogramming of the device are sup-
ported.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. The six control terms can individually be
configured as either SUM or PRODUCT terms, and are
used to control the preset/reset and output enables of the
16 macrocells’ flip-flops. In addition, two of the control
terms can be used as clock signals (see Macrocell Archi-
tecture section for details). The PAL array consists of a pro-
grammable AND array with a fixed OR array, while the PLA
array consists of a programmable AND array with a pro-
grammable OR array. The PAL array provides a high speed
path through the array, while the PLA array provides
increased product term density.
XPLA Architecture
Figure 1 shows a high-level block diagram of a 128 macro-
cell device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
by a zero-power Interconnect Array (ZIA). The ZIA is a vir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin tPD of the XCR3128A device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 1.5 ns.
So the total pin-to-pin tPD for the XCR3128A using six to 37
product terms is 9 ns (7.5 ns for the PAL + 1.5 ns for the
PLA).
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
MC0
MC0
MC1
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MC15
MC15
16
16
16
16
MC0
MC1
MC0
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
MC15
MC15
16
16
16
16
ZIA
MC0
MC1
MC0
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
MC15
MC15
16
16
16
16
MC0
MC1
MC0
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
I/O
MC15
MC15
16
16
16
16
SP00464
Figure 1: Xilinx XPLA CPLD Architecture
DS035 (v1.2) August 10, 2000
www.xilinx.com
2
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
36 ZIA INPUTS
6
CONTROL
5
PAL
ARRAY
PLA
ARRAY
(32)
SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
3
www.xilinx.com
DS035 (v1.2) August 10, 2000
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
nous Preset/Reset of the macrocell’s flip-flop. Note that the
Power-on Reset leaves all macrocells in the "zero" state
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in
the CoolRunner XCR3128A. The macrocell can be config-
ured as either a D- or T-type flip-flop or a combinatorial logic
function. A D-type flip-flop is generally more useful for
implementing state machines and data buffering while a
T-type flip-flop is generally more useful in implementing
counters. Each of these flip-flops can be clocked from any
one of six sources. Four of the clock sources (CLK0, CLK1,
CLK2, CLK3) are connected to low-skew, device-wide clock
networks designed to preserve the integrity of the clock sig-
nal by reducing skew between rising and falling edges.
Clock 0 (CLK0) is designated as a "synchronous" clock and
must be driven by an external source. Clock 1 (CLK1),
Clock 2 (CLK2), and Clock 3 (CLK3) can be used as "syn-
chronous" clocks that are driven by an external source, or
as "asynchronous" clocks that are driven by a macrocell
equation. CLK0, CLK1, CLK2, and CLK3 can clock the
macrocell flip-flops on either the rising edge or the falling
edge of the clock signal. The other clock sources are two of
the six control terms (CT2 and CT3) provided in each logic
block. These clocks can be individually configured as either
a PRODUCT term or SUM term equation created from the
36 signals available inside the logic block. The timing for
asynchronous and control term clocks is different in that the
tCO time is extended by the amount of time that it takes for
the signal to propagate through the array and reach the
clock network, and the tSU time is reduced.
when power is properly applied, and that the Preset/Reset
feature for each macrocell can also be disabled. Control
terms CT2 and CT3 can be used as a clock signal to the
flip-flops of the macrocells, and as the Output Enable of the
macrocell’s output buffer. Control terms CT4 and CT5 can
be used to control the Output Enable of the macrocell’s out-
put buffer. Having four dedicated Output Enable control
terms ensures that the CoolRunner devices are PCI com-
pliant. The output buffers can also be always enabled or
always disabled. All CoolRunner devices also provide a
Global 3-state (GTS) pin, which, when enabled and pulled
Low, will 3-state all the outputs of the device. This pin is
provided to support "In-Circuit Testing" or "Bed-of-Nails"
testing.
There are two feedback paths to the ZIA: one from the mac-
rocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin feedback path. When the macrocell is used as an out-
put, the output buffer is enabled, and the macrocell feed-
back path can be used to feedback the logic implemented
in the macrocell. When the I/O pin is used as an input, the
output buffer will be 3-stated and the input signal will be fed
into the ZIA via the I/O feedback path, and the logic imple-
mented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on Terminations in this data sheet and the appli-
cation note Terminating Unused I/O Pins in Xilinx XPLA1
and XPLA2 CoolRunner CPLDs.
The six control terms of each logic block are used to control
the asynchronous Preset/Reset of the flip-flops and the
enable/disable of the output buffers in each macrocell. Con-
trol terms CT0 and CT1 are used to control the asynchro-
TO ZIA
PAL
PLA
D/T
Q
INIT
(P or R)
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
GTS
GND
CT0
CT1
GND
SP00558
Figure 3: XCR3128A Macrocell Architecture
DS035 (v1.2) August 10, 2000
www.xilinx.com
4
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
because the timing models of competing architectures are
very complex and include such things as timing dependen-
cies on the number of parallel expanders borrowed, shar-
able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other competing architec-
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This is
t
= COMBINATORIAL PAL ONLY
= COMBINATORIAL PAL + PLA
PD_PAL
t
PD_PLA
INPUT PIN
OUTPUT PIN
REGISTERED
= PAL ONLY
t
t
REGISTERED
SU_PAL
= PAL + PLA
t
SU_PLA
CO
INPUT PIN
D
Q
OUTPUT PIN
GLOBAL CLOCK PIN
SP00553
Figure 4: CoolRunner Timing Model
5
www.xilinx.com
DS035 (v1.2) August 10, 2000
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
gate implementation allows Xilinx to offer CPLDs which are
TotalCMOS Design Technique for Fast Zero
Power
both high-performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of the XCR3128A TotalCMOS CPLD (data
taken with eight up/down, loadable 16-bit counters at 3.3V,
25°C).
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
70
60
50
40
I
CC
(mA)
30
20
10
0
1
20
40
60
80
100
120
FREQUENCY (MHz)
SP00617
Figure 5: ICC vs. Frequency @ VCC = 3.3V, 25°C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz)
0
1
20
40
60
38.1
80
50.5
100
62.8
120
Typical ICC (mA)
0.03
0.7
12.7
25.5
74.7
DS035 (v1.2) August 10, 2000
www.xilinx.com
6
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
device. The devices come from the factory with these I/O
pins set to perform JTAG functions, but through the soft-
ware, the final function of these pins can be controlled. If
the end application will require the device to be repro-
grammed at some future time with ISP, then the pins can be
left as dedicated JTAG functions, which means they are not
available for use as general purpose I/O pins. However,
unlike competing CPLDs, the Xilinx XCR3128A allow the
macrocells associated with these pins to be used as buried
logic when the JTAG/ISP function is enabled. This is the
default state for the software, and no action is required to
leave these pins enabled for the JTAG/ISP functions. If,
however, JTAG/ISP is not required in the end application,
the software can specify that this function be turned off and
that these pins be used as general purpose I/O. Because
the devices initially have the JTAG/ISP functions enabled,
the JEDEC file can be downloaded into the device once,
after which the JTAG/ISP pins will become general purpose
I/O. This feature is good for manufacturing because the
devices can be programmed during test and assembly of
the end product and yet still use all of the I/O pins after the
programming is done. It eliminates the need for a costly,
separate programming step in the manufacturing process.
Of course, if the JTAG/ISP function is never required, this
feature can be turned off in the software and the device can
be programmed with an industry-standard programmer,
leaving the pins available for I/O functions. Table 4 defines
the dedicated pins used by the four mandatory JTAG sig-
nals for each of the XCR3128A package types.
JTAG Testing Capability
JTAG is the commonly-used acronym for the
Boundary-scan Test (BST) feature defined for integrated
circuits by IEEE Standard 1149.1. This standard defines
input/output pins, logic control functions, and commands
which facilitate both board and device level testing without
the use of specialized test equipment. The Xilinx
XCR3128A devices use the JTAG Interface for In-System
Programming/Reprogramming. Although only a subset of
the full JTAG command set is implemented (see Table 2),
the devices are fully capable of sitting in a JTAG scan chain.
The Xilinx XCR3128A’s JTAG interface includes a TAP Port
defined by the IEEE 1149.1 JTAG Specification. As imple-
mented in the Xilinx XCR3128A, the TAP Port includes four
of the five pins (refer to Table 3) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal
defined by the JTAG specification is TRST* (Test Reset).
TRST* is considered an optional signal, since it is not actu-
ally required to perform BST or ISP. The Xilinx XCR3128A
saves an I/O pin for general purpose use by not implement-
ing the optional TRST* signal in the JTAG interface.
Instead, the Xilinx XCR3128A supports the test reset func-
tionality through the use of its power-up reset circuit, which
is included in all Xilinx CPLDs. The pins associated with the
TAP Port should connect to an external pull-up resistor to
keep the JTAG signals from floating when they are not
being used. In the Xilinx XCR3128A, the four mandatory
JTAG pins each require a unique, dedicated pin on the
Table 2: XCR3128A Low-level JTAG Boundary-scan Commands
Instruction
(Instruction Code)
Register Used
Description
Bypass
(1111)
Bypass Register
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation. The Bypass instruction can be entered by holding TDI at a
constant high value and completing an Instruction-scan cycle.
Idcode
(0001)
Boundary-scan Register
Selects the IDCODE register and places it between TDI and TDO, allowing the
IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind
interrogation of the components assembled onto a printed circuit board. Thus, in
circumstances where the component population may vary, it is possible to determine
what components exist in a product.
7
www.xilinx.com
DS035 (v1.2) August 10, 2000
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Table 3: JTAG Pin Description
Pin
Name
Description
TCK
Test Clock Output
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively.
TMS
TDI
Test Mode Select
Test Data Input
Test Data Output
Serial input pin selects the JTAG instruction mode. TMS should be driven High
during user mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
TDO
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is 3-stated if data is not being shifted out of the device.
Table 4: XCR3128A JTAG Pinout by Package Type
Device
(Pin Number / Macrocell #)
XCR3128A
100-pin VQFP
128-pin TQFP
TCK
TMS
TDI
TDO
62/F15
82/F15
15/C15
21/C15
4/B15
8/B15
73/G15
95/G15
-
Improved quality and reliability
3.3V, In-System Programming (ISP)
•
Field Support
-
-
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
Easy remote upgrades and repair
Support for field configuration, reconfiguration, and
customization
The Xilinx XCR3128A allows for 3.3V in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally provided supervoltages, so that the XCR3128A
may be easily programmed on the circuit board using only
the 3V supply required by the device for normal operation.
A set of low-level ISP basic commands implemented in the
XCR3128A enable this feature. The ISP commands imple-
mented in the Xilinx XCR3128A are specified in Table 5.
Please note that an ENABLE command must precede all
ISP commands unless an ENABLE command has already
been given for a preceding ISP command.
•
Design
-
-
-
-
Faster time-to-market
Debug partitioning and simplified prototyping
Printed circuit board reconfiguration during debug
Better device and board level testing
•
Manufacturing
-
-
-
Multi-functional hardware
Reconfigurability for test
Eliminates handling of "fine lead-pitch" components
for programming
-
Reduced inventory and manufacturing costs
DS035 (v1.2) August 10, 2000
www.xilinx.com
1-800-255-7778
8
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Table 5: Low Level ISP Commands
Instruction
Instruction Code
(Register Used)
Description
Enable
(ISP Shift Register)
1001
1010
1011
1100
Enables the Erase, Program, and Verify commands.
Erases the entire EEPROM array.
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
Programs the data in the ISP Shift Register into the addressed
EEPROM row.
Verify
(ISP Shift Register)
Transfers the data from the addressed row to the ISP Shift
Register. .
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10kΩ
pull-up resistors. These pins can be directly connected to
VCC or GND, but using the external pull-up resistors main-
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
Terminations
The CoolRunner XCR3128A CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR3128A
CPLDs have programmable on-chip pull-down resistors on
each I/O pin. These pull-downs are automatically activated
by the fitter software for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR3128A device be left
unconnected.
When using the JTAG/ISP functions, it is also recom-
mended that 10kΩ pull-up resistors be used on each of the
pins associated with the four mandatory JTAG signals. Let-
ting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the appli-
cation notes JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner CPLDs for more informa-
tion.
9
www.xilinx.com
1-800-255-7778
DS035 (v1.2) August 10, 2000
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
•
•
•
•
Embedded Processor
Automated test equipment
Third party programmers
High-end ISP tools
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD’s and other integrated cir-
cuits. The Xilinx XCR3128A supports the following meth-
ods:
For more details on JTAG and ISP for the XCR3128A, refer
to the related application note: JTAG and ISP Overview for
Xilinx XPLA1 and XPLA2 CPLDs
•
•
PC parallel port
Workstation or PC serial port
Table 6: Programming Specifications
Symbol
Parameter
Min.
Max.
Unit
DC Parameters
VCCP
ICCP
VCC supply program/verify
3.0
3.6
V
ICC limit program/verify
200
mA
VIH
Input voltage (High)
Input voltage (Low)
Output voltage (Low)
Output voltage (High)
Output current (Low)
Output current (High)
2.0
V
V
VIL
0.8
0.5
VSOL
V
VSOH
2.4
8
V
TDO_IOL
TDO_IOH
AC Parameters
fMAX
mA
mA
-8
CLK maximum frequency
Pulse width erase
Pulse width program
Pulse width verify
10
100
10
MHz
ms
ms
µs
PWE
PWP
PWV
10
INIT
Initialization time
100
10
µs
ns
TMS_SU
TDI_SU
TMS_H
TDI_H
TDO_CO
TMS setup time before TCK goes High
TDI setup time before TCK goes High
TMS hold time after TCK goes High
TDI hold time after TCK goes High
TDO valid after TCK goes Low
10
ns
25
ns
25
ns
40
ns
DS035 (v1.2) August 10, 2000
www.xilinx.com
10
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Absolute Maximum Ratings1
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply voltage 2
Input voltage
Output voltage
Input current
-0.5
4.6
V
VI
-1.2
-0.5
-30
-40
-65
5.75
5.5
V
V
VOUT
IIN
30
mA
°C
°C
TJ
Maximum junction temperature
Storage temperature
150
150
Tstr
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Operating Range
Product Grade
Commercial
Industrial
Temperature
0 to +70°C
-40 to +85°C
Voltage
3.0 to 3.6 V
2.7 to 3.6 V
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
VIL
Parameter
Input voltage Low
Test Conditions
Min.
Max.
Unit
V
VCC = 3.0V
VCC = 3.6V
0.8
VIH
VI
Input voltage High
2.0
V
Input clamp voltage
Output voltage Low
Output voltage High
Input leakage current
3-stated output leakage current
Standby current
VCC = 3.0V, IIN = -18 mA
VCC = 3.0V, IOL = 12 mA
VCC = 3.0V, IOH = -12 mA
VIN = 0 to 5.5V
-1.2
0.5
V
VOL
VOH
II
V
2.4
-10
-10
V
10
10
µA
µA
µA
mA
mA
mA
IOZ
ICCQ
ICCD
VIN = 0 to 5.5V
1
VCC = 3.6V, TAMB = 0°C
VCC = 3.6V, TAMB = 0°C @ 1 MHz
VC = 3.6V, TAMB = 0°C @ 50 MHz
100
2
1, 2
Dynamic current
50
IOS
CIN
Short circuit output current 3
One pin at a time for no longer than one
second
-50
5
-200
Input pin capacitance 3
Clock input capacitance 3
I/O pin capacitance3
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
8
pF
pF
pF
CCLK
CI/O
12
10
Notes:
1. See Table 2 on page 7 typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
11
www.xilinx.com
DS035 (v1.2) August 10, 2000
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.0V ≤ VCC ≤ 3.6V
7
10
12
Unit
Symbol
tPD_PAL
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Propagation delay time, input (or
feedback node) to output through PAL
2
7.5
2
10
2
12
ns
ns
tPD_PLA
Propagation delay time, input (or
feedback node) to output through PAL +
PLA
3
9
3
11.5
7
3
13.5
8
tCO
Clock to out (global synchronous clock
from pin)
2
3.5
5
5.5
2
4
2
6
ns
ns
ns
tSU_PAL
tSU_PLA
Setup time (from input or feedback node)
through PAL
Setup time (from input or feedback node)
through PAL + PLA
5.5
7.5
tH
Hold time 2
0
0
0
ns
ns
tCH
tCL
Clock High time 2
Clock Low time 2
Input rise time 2
Input fall time2
2
2
2.5
2.5
3
3
ns
tR
100
100
100
100
100
100
ns
tF
ns
fMAX1
fMAX2
Maximum FF toggle rate2 1/(tCH + tCL
Maximum internal frequency 2
)
250
143
200
118
167
91
MHz
MHz
1/(tSUPAL + tCF
)
fMAX3
Maximum external frequency 2
111
91
71
MHz
1/(tSUPAL + tCO
)
tBUF
Output buffer delay time 2
2
2
2
8
ns
ns
tPDF_PAL
Input (or feedback node) to internal
feedback node delay time through PAL2
2
3
5.5
2
3
7.5
2
3
tPDF_PLA
Input (or feedback node) to internal
feedback node delay time through
PAL+PLA 2
7
9
9.5
5
ns
ns
tCF
Clock to internal feedback node delay
time 2
3.5
4.5
tINIT
tER
Delay from valid VCC to valid reset 2
Input to output disable 2, 3
Input to output valid 2
Input to register preset 2
Input to register reset 2
20
8
20
9.5
9.5
9.5
9.5
20
10
10
10
10
µs
ns
ns
ns
ns
tEA
8
tRP
9
tRR
9
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 7 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
DS035 (v1.2) August 10, 2000
www.xilinx.com
12
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 2.7V ≤ VCC ≤ 3.6V
Symbol
VIL
Parameter
Input voltage Low
Test Conditions
Min.
Max.
Unit
V
VCC = 2.7V
VCC = 3.6V
0.8
VIH
VI
Input voltage High
Input clamp voltage
Output voltage Low
2.0
V
VCC = 2.7V, IIN = -18 mA
VCC = 2.7V, IOL = 8 mA
VCC= 3.0V, IOL = 12 mA
VCC = 2.7V, IOH = -8 mA
VCC = 3.0V, IOH = -12 mA
VIN = 0 to 5.5V
-1.2
0.5
0.5
V
VOL
V
V
VOH
Output voltage High
Input leakage current
2.4
2.4
-10
-10
V
V
II
10
10
100
2
µA
µA
µA
mA
mA
mA
pF
pF
pF
IOZ
ICCQ
ICCD
3-stated output leakage current VIN = 0 to 5.5V
1
Standby current
Dynamic current
VCC = 3.6V, TAMB = -40°C
1 2
VCC = 3.6V, TAMB = -40°C @ 1 MHz
VCC = 3.6V, TAMB = -40°C @ 50 MHz
1 pin at a time for no longer than 1 second
TAMB = 25°C, f = 1 MHz
50
-230
8
IOS
Short circuit output current 3
Input pin capacitance 3
Clock input capacitance 3
I/O pin capacitance 3
-50
5
CIN
CCLK
CI/O
TAMB = 25°C, f = 1 MHz
12
10
TAMB = 25°C, f = 1 MHz
Notes:
1. See Table 1 on page 6 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
13
www.xilinx.com
DS035 (v1.2) August 10, 2000
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 2.7V ≤ VCC ≤ 3.6V
10
15
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
tPD_PAL
Propagation delay time, input (or feedback node) to out-
put through PAL
2
10
2
15
ns
tPD_PLA
Propagation delay time, input (or feedback node) to out-
put through PAL + PLA
3
11.5
7
3
16.5
8
ns
tCO
Clock to out (global synchronous clock from pin)
2
4
2
6
ns
ns
ns
tSU_PAL
tSU_PLA
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through
PAL + PLA
5.5
7.5
tH
Hold time
0
0
ns
ns
tCH
Clock High time
Clock Low time
Input rise time
Input fall time
3
3
4
4
tCL
ns
tR
100
100
100
100
ns
tF
ns
fMAX1
fMAX2
fMAX3
tBUF
tPDF_PAL
Maximum FF toggle rate 2 1/(tCH + tCL
Maximum internal frequency 2 1/(tSUPAL + tCF
Maximum external frequency 2 1/(tSUPAL + tCO
Output buffer delay time 2
)
167
111
91
125
87
MHz
MHz
MHz
ns
)
)
77
2
8
2
9
Input (or feedback node) to internal feedback node delay
time through PAL 2
2
3
2
3
ns
tPDF_PLA
Input (or feedback node) to internal feedback node delay
time through PAL+PLA 2
9.5
10.5
ns
tCF
tINIT
tER
tEA
tRP
tRR
Clock to internal feedback node delay time 2
Delay from valid VCC to valid reset 2
Input to output disable 2, 3
5
5.5
20
12
12
12
12
ns
µs
ns
ns
ns
ns
20
10
10
10
10
Input to output valid 2
Input to register preset 2
Input to register reset 2
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 7 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
DS035 (v1.2) August 10, 2000
www.xilinx.com
14
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
V
DD
Component
Values
390Ω
390Ω
35 pF
S1
R1
R2
C1
R1
R2
V
IN
V
OUT
Measurement
S1
S2
C1
t
Open
Closed
Open
PZH
t
Closed
Closed
PZL
t
P
Closed
S2
NOTE: For t
and t
C = 5 pF, and 3-state levels are
PHZ
PLZ
0.5V from steady state active level.
measured
SP00699
V
= 3.3V, 25°C
DD
6.1
6.0
+3.0V
90%
5.9
5.8
5.7
5.6
5.5
10%
0V
t
R
t
F
t
PD_PAL
(ns)
1.5ns
1.5ns
SP00368
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
5.4
5.3
Input Pulses
Figure 7: Voltage Waveform
5.2
5.1
Table 7: tPD_PAL vs. Number of Outputs Switching
1
2
4
8
12
16
(VCC = 3.3 V, T = 25°C)
NUMBER OF OUTPUTS SWITCHING
SP00698
Number of
Outputs
Figure 6: tPD_PAL vs. Outputs Switching
1
2
4
8
12
16
Typical (ns) 5.3
5.3
5.4
5.6
5.9
6.1
15
www.xilinx.com
1-800-255-7778
DS035 (v1.2) August 10, 2000
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Pin Function and Laynout
XCR3128A: 100-pin VQFP, and 128-pin TQFP Pin Function Table
Function
100-pin
VQFP
I/O-A2
I/O-A0
Function
Function
Function
Pin
#
Pin
#
Pin
#
Pin
#
128-pin
TQFP
I/O-A3
I/O-A2
I/O-A0
NC
100-pin
VQFP
128-pin
TQFP
NC
100-pin
VQFP
128-pin
TQFP
100-pin
VQFP
128-pin
TQFP
NC
1
2
3
4
5
6
7
8
33
34
35
36
I/O-D5
65
66
67
68
69
70
71
72
I/O-G4
I/O-E15
97
98
I/O-A8
V
NC
V
V
CC
I/O-A7
NC
CC
CC
V
I/O-D4
I/O-D2
NC
I/O-G5
I/O-G7
I/O-F0
NC
99
I/O-A5
NC
CC
I/O-B15 (TDI)
I/O-B13
I/O-C0
GND
100
101
102
103
104
I/O-A4
I/O-H0
I/O-H2
I/O-H3
I/O-H4
I/O-H5
NC
37 I/O-D0/CLK2
I/O-G8
NC
-
-
-
-
I/O-B12
NC
38
39
GND
I/O-D15
I/O-D13
I/O-D12
I/O-G10
I/O-G12
I/O-G13
NC
I/O-B10
V
V
I/O-F2
I/O-F3
CC
CC
I/O-E0/
CLK1
I/O-B8
I/O-B15 (TDI) 40
9
I/O-B7
I/O-B13
41
I/O-E2
I/O-D11
73
I/O-G15
(TDO)
I/O-F4
105
-
I/O-H7
10
11
12
13
14
15
I/O-B5
GND
I/O-B12
I/O-B11
I/O-B10
I/O-B8
I/O-B7
I/O-B5
42
43
44
45
46
47
I/O-E4
GND
I/O-D10
I/O-D8
I/O-D7
I/O-D5
74
75
76
77
78
79
GND
I/O-F5
I/O-F7
I/O-F8
I/O-F10
GND
106
107
108
109
110
111
-
-
-
-
-
-
I/O-H8
I/O-H0
I/O-H2
I/O-H4
I/O-H5
I/O-H7
I/O-H10
I/O-B4
I/O-B2
I/O-B0
I/O-E5
I/O-E7
I/O-E8
I/O-E10
V
CC
I/O-H11
I/O-H12
I/O-H13
V
CC
I/O-C15
(TMS)
I/O-D4
I/O-F11
16
17
18
I/O-C13
I/O-C12
GND
I/O-B4
I/O-B3
48
49
50
I/O-E12
I/O-E13
I/O-E15
I/O-D3
I/O-D2
80
81
I/O-H8
I/O-F12
I/O-F13
112
113
114
-
-
-
I/O-H15
GND
I/O-H10
V
I/O-D0/CLK2 82
V
I/O-F15
(TCK)
IN0/CLK0
CC
CC
19
20
21
I/O-C10
I/O-C8
I/O-C7
I/O-B2
I/O-B0
51
52
53
V
GND
83
84
85
I/O-H12
I/O-H13
I/O-H15
I/O-G0
I/O-G2
I/O-G3
115
116
117
-
-
-
IN2/gtsn
IN1
CC
I/O-F0
I/O-F2
V
CC
I/O-C15
(TMS)
I/O-E0/
CLK1
IN3
22
23
I/O-C5
I/O-C4
I/O-C13
I/O-C12
54
55
I/O-F4
I/O-F5
I/O-E2
I/O-E3
86
87
GND
I/O-G4
118
119
-
-
V
CC
IN0/CLK0
V
I/O-A15/
CLK3
CC
24
25
26
27
28
29
30
I/O-C2
I/O-C0
GND
I/O-C11
56
57
58
59
60
61
62
I/O-F7
I/O-F8
I/O-F10
GND
I/O-E4
GND
88
89
90
91
IN2/gtsn
IN1
I/O-G5
I/O-G7
120
121
122
123
124
125
126
-
-
-
-
-
-
-
I/O-A13
I/O-A12
I/O-A12
GND
V
CC
I/O-C10
I/O-C8
I/O-C7
I/O-C5
I/O-C4
I/O-E5
I/O-E7
I/O-E8
I/O-E10
I/O-E11
IN3
I/O-G8
I/O-D15
I/O-D13
I/O-D12
I/O-D10
V
I/O-G10
I/O-G11
I/O-G12
I/O-G13
CC
I/O-F12
I/O-F13
92 I/O-A15/CLK3
I/O-A10
I/O-A8
I/O-A7
93
94
I/O-A13
I/O-A12
I/O-F15
(TCK)
31
32
I/O-D8
I/O-D7
I/O-C3
I/O-C2
63
64
I/O-G0
I/O-E12
I/O-E13
95
96
GND
I/O-G15
(TDO)
127
128
-
-
I/O-A5
I/O-A4
I/O-G2
I/O-A10
GND
DS035 (v1.2) August 10, 2000
www.xilinx.com
16
1-800-255-7778
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
100-pin VQFP
128-pin TQFP
128
103
100
76
1
102
75
1
VQFP
TQFP
25
51
38
65
26
50
39
64
SP00485A
SP00469B
Ordering Information
Example: XCR3128A -7 VQ 100 C
Temperature Range
Number of Pins
Package Type
Device Type
Speed Options
Temperature Range
Speed Options
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +85°C
-15: 15 ns pin-to-pin delay
-12: 12 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
-7: 7.5 ns pin-to-pin delay
Packaging Options
VQ100: 100-pin VQFP
TQ128: 128-pin TQFP
Component Availability
Pins
100
128
Type
Plastic VQFP
Plastic TQFP
Code
VQ100
TQ128
XCR3128A
-15
-12
-10
-7
I
C
I
C
C, I
C
C, I
C
Revision History
Date
Version #
Revision
7/22/99
2/10/00
8/10/00
1.0
1.1
1.2
Initial Xilinx release
Converted to Xilinx format and updated.
Updated pinout table.
17
www.xilinx.com
DS035 (v1.2) August 10, 2000
1-800-255-7778
相关型号：
©2020 ICPDF网 联系我们和版权申明