XCR3256XL-12FTG256I [XILINX]
EE PLD, 12ns, 256-Cell, CMOS, PBGA256, FBGA-256;
| 型号： | XCR3256XL-12FTG256I |
| 厂家： | 
XILINX, INC |
| 描述： | EE PLD, 12ns, 256-Cell, CMOS, PBGA256, FBGA-256 时钟 输入元件 可编程逻辑 |
| 文件： | 总13页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XCR3256XL 256 Macrocell CPLD
0
14
DS013 (v2.7) March 31, 2006
Product Specification
Features
Description
•
•
•
•
•
Low power 3.3V 256 macrocell CPLD
The CoolRunner™ XPLA3 XCR3256XL device is a 3.3V,
256 macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of 16 function blocks provide 6,000 usable gates.
Pin-to-pin propagation delays are as fast as 7.0 ns with a
maximum system frequency of 154 MHz.
7.0 ns pin-to-pin logic delays
System frequencies up to 154 MHz
256 macrocells with 6,000 usable gates
Available in small footprint packages
-
-
-
-
144-pin TQFP (120 user I/O pins)
208-pin PQFP (164 user I/O)
256-ball FBGA (164 user I/O)
280-ball CS BGA (164 user I/O)
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,
both in process technology and design technique. These
CPLDs employ a cascade of CMOS gates to implement
their sum of products, instead of the traditional sense amp
approach. This CMOS gate implementation allows Xilinx
CPLDs to offer devices that are both high performance and
low power, breaking the paradigm that to have low power,
you must have low performance. Refer to Figure 1 and
Table 1 showing the ICC vs. Frequency of our XCR3256XL
TotalCMOS CPLD (data taken with 16 resetable up/down,
16-bit counters at 3.3V, 25°C).
•
Optimized for 3.3V systems
-
-
-
-
Ultra low power operation
Typical Standby Current of 18 μA at 25°C
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power™ (FZP) CMOS design
technology
3.3V PCI electrical specification compatible outputs
(no internal clamp diode on any input or I/O)
-
-
•
Advanced system features
140
120
100
80
-
-
-
-
-
-
-
-
In-system programming
Input registers
Predictable timing model
Up to 23 clocks available per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per function block
60
40
•
•
•
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
20
0
•
•
•
Programmable slew rate control per output
Security bit prevents unauthorized access
20
0
XCR3256XL
40
60
80
100
120
140
160
Refer to the CoolRunner™ XPLA3 family data sheet
Frequency (MHz)
(DS012) for architecture description
Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C
Frequency (MHz)
0
1
10
20
40
60
80
100
120
140
Typical ICC (mA)
0.018
0.98
9.69
19.3
38.1
56.2
73.7
90.8
107.3
123.9
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS013 (v2.7) March 31, 2006
R
XCR3256XL 256 Macrocell CPLD
(1)
DC Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Output High voltage
Test Conditions
Typical
Min.
Max. Unit
(2)
VOH
VCC = 3.0V to 3.6V, IOH = –8 mA
-
2.4
-
-
-
V
CC = 2.7V to 3.0V, IOH = –8 mA
OH = –500 μA
Output Low voltage for 3.3V outputs IOL = 8 mA
-
2.0
(3)
I
-
90% VCC
VOL
IIL
-
-
0.4
10
10
100
2
V
Input leakage current
I/O High-Z leakage current
Standby current
VIN = GND or VCC to 5.5V
-
–10
μA
μA
μA
mA
mA
pF
pF
pF
IIH
VIN = GND or VCC to 5.5V
VCC = 3.6V
f = 1 MHz
-
–10
(7)
ICCSB
30.5
-
-
ICC
Dynamic current(4,5)
-
-
-
-
-
f = 50 MHz
-
60
8
CIN
Input pin capacitance(6)
Clock input capacitance(6)
I/O pin capacitance(6)
f = 1 MHz
-
CCLK
CI/O
f = 1 MHz
5
-
12
10
f = 1 MHz
Notes:
1. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions.
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. This parameter guaranteed by design and characterization, not by testing.
4. See Table 1, Figure 1 for typical values.
5. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
6. Typical values, not tested.
7. Typical value at 70° C.
100
90
I
(3.3V)
OL
80
70
60
50
40
30
I
(3.3V)
OH
I
(2.7V)
OH
20
10
0
0
0.5
1
1.5
2
2.5
Volts
3
3.5
4
4.5
5
DS012_10_040402
Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family. 25°C
2
www.xilinx.com
DS013 (v2.7) March 31, 2006
Product Specification
R
XCR3256XL 256 Macrocell CPLD
(1,2)
AC Electrical Characteristics Over Recommended Operating Conditions
-7
-10
-12
Symbol
TPD1
Parameter
Propagation delay time (single p-term)
Propagation delay time (OR array)(3)
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Min. Max. Min. Max. Min. Max. Unit
-
-
7.0
-
-
9.0
-
-
10.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPD2
TCO
7.5
10.0
12.0
-
4.5
-
5.8
-
6.9
-
TSUF
TSU1
TSU2
2.5
4.3
4.8
0
-
3.0
5.5
6.5
0
-
3.0
6.7
7.9
0
(4)
-
-
-
Setup time (OR array)
-
-
-
-
-
(4)
TH
Hold time
-
(4)
TWLH
Global Clock pulse width (High or Low)
P-term clock pulse width
3.0
4.5
4.5
-
-
4.0
6.0
6.0
-
-
5.0
7.5
7.5
-
-
(4)
TPLH
-
-
-
TAPRPW
Asynchronous preset/reset pulse width (High or Low)
Input rise time
-
-
-
(4)
TR
20
20
154
20
20
105
20
20
88
(4)
TL
Input fall time
-
-
-
(4)
(4)
fSYSTEM
Maximum system frequency
-
-
-
MH
z
TCONFIG
Configuration time(5)
-
-
-
-
-
-
200
200
9.0
9.0
8.0
9.0
-
-
-
-
-
-
200
200
-
-
-
-
-
-
200
200
μs
μs
ns
ns
ns
ns
(4)
TINIT
ISP initialization time
(4)
TPOE
P-term OE to output enabled
P-term OE to output disabled(6)
P-term clock to output
11.0
11.0
10.3
11.0
13.0
13.0
12.4
13.0
(4)
TPOD
(4)
TPCO
(4)
TPAO
P-term set/reset to output valid
Notes:
1. Specifications measured with one output switching.
2. See XPLA3 family data sheet (DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configuration is 10 mA at 3.6V.
6. Output CL = 5 pF.
DS013 (v2.7) March 31, 2006
www.xilinx.com
3
Product Specification
R
XCR3256XL 256 Macrocell CPLD
(1,2)
Internal Timing Parameters
-7
-10
-12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Buffer Delays
TIN
Input buffer delay
Fast input buffer delay
-
-
-
-
-
2.5
2.7
1.0
2.5
4.5
-
-
-
-
-
3.3
3.3
1.3
3.2
5.2
-
-
-
-
-
4.0
3.3
1.5
3.8
6.0
ns
ns
ns
ns
ns
TFIN
TGCK
TOUT
TEN
Global clock buffer delay
Output buffer delay
Output buffer enable/disable delay
Internal Register and Combinatorial Delays
TLDI
Latch transparent delay
-
0.8
0.3
2.0
3.0
-
1.3
-
-
1.0
0.5
2.5
4.5
-
1.6
-
-
1.2
0.7
3.0
5.5
-
2.0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSUI
Register setup time
THI
Register hold time
-
-
-
TECSU
TECHO
TCOI
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
-
-
-
-
-
-
1.0
2.0
5.0
2.0
2.0
2.5
1.3
2.0
7.0
2.5
2.5
3.5
1.6
2.2
8.0
3.0
3.0
4.2
TAOI
-
-
-
TRAI
-
-
-
TPTCK
TLOGI1
TLOGI2
Product term clock delay
-
-
-
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
-
-
-
-
-
Feedback Delays
TF
ZIA delay
-
2.2
-
3.7
-
4.4
ns
Time Adders
TLOGI3
TUDA
Fold-back NAND delay
-
-
-
2.0
2.0
4.0
-
-
-
2.5
2.5
5.0
-
-
-
3.0
3.0
6.0
ns
ns
ns
Universal delay
TSLEW
Slew rate limited delay
Notes:
1. These parameters guaranteed by design and/or characterization, not testing.
2. See the CoolRunner XPLA3 family data sheet (DS012) for the timing model.
4
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DS013 (v2.7) March 31, 2006
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Switching Characteristics
V
CC
S1
Component
Values
R1
R2
C1
390Ω
390Ω
35 pF
R1
V
IN
V
OUT
Measurement
S1
S2
Open
Closed
Closed
Closed
Open
Closed
T
T
(High)
POE
R2
C1
(Low)
POE
T
P
Note: For T
, C1 = 5 pF. Delay measured at
POD
output level of V + 300 mV, V
– 300 mV.
OH
OL
S2
DS013_03_102401
Figure 3: AC Load Circuit
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
+3.0V
0V
90%
10%
T
R
T
L
1.5 ns
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
1
2
4
8
16
DS017_05_042800
Number of Adjacent Outputs Switching
Figure 5: Voltage Waveform
DS013_04_042800
Figure 4: Derating Curve for TPD2
DS013 (v2.7) March 31, 2006
www.xilinx.com
5
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Pin Descriptions
Function Macro-
Table 2: XCR3256XL User I/O Pins
Block
cell
TQ144 PQ208 FT256
CS280
H17
H18
H19
J16
J17
-
TQ144 PQ208 FT256 CS280
3
1
98
97
96
94
93
-
17
18
19
20
21
-
G15
G13
F16
G14
G16
-
Total User I/O Pins
120
164
164
164
3
2
3
3
Table 3: XCR3256XL I/O Pins
3
4
Function Macro-
3
5
Block
cell
TQ144 PQ208 FT256
CS280
E18
E19
F15
F17
F18
-
3
6
1
1
106
6
7
C16
F12
D16
E14
E15
-
3
7
-
-
-
-
1
2
-
3
8
-
-
-
-
1
3
104(1)
8
3
9
-
-
-
-
1
4
103
9
3
10
11
12
13
14
15
16
1
-
-
-
-
1
5
102
10
-
3
-
-
-
-
1
6
-
3
92
-
22
24
25
26
27
197
196
195
194
193
-
H13
H12
H15
H14
H16
D11
A11
E10
B12
C11
-
J18
K16
K17
K18
L16
E14
D14
A14
C13
B13
-
1
7
-
-
-
-
3
1
8
-
-
-
-
3
91
90
-
1
9
-
-
-
-
3
1
10
11
12
13
14
15
16
1
-
-
-
-
3
1
-
-
-
-
4
114
116
117
-
1
101
11
12
13
15
16
4
F13
E16
F14
F15
G12
E13
D15
C13
A14
E11
-
F19
G16
G17
G19
H16
B19
B18
B17
A18
A17
-
4
2
1
100
4
3
1
99
4
4
1
-
4
5
118
-
1
-
4
6
2
107
4
7
-
-
-
-
2
2
108
3
4
8
-
-
-
-
2
3
-
206
205
204
-
4
9
-
-
-
-
2
4
-
4
10
11
12
13
14
15
16
1
-
-
-
-
2
5
109
4
-
-
-
-
2
6
-
4
119
120
121
-
192
190
189(1)
188
187
28
29
30(1)
31
33
B11
A10
C10(1)
A9
A13
A12
C12(1)
B12
D12
L17
L18
L19(1)
M16
M18
2
7
-
-
-
-
4
2
8
-
-
-
-
-
4
2
9
-
-
-
4
2
10
11
12
13
14
15
16
-
-
-
-
4
122
89(1)
-
D9
J14
J15
J13(1)
J16
L14
2
-
-
-
-
5
2
110
111
-
203
202
201
199
198
A13
D12
B13
C12
A12
C16
A16
E15
D15
A15
5
2
2
5
3
88
87
86
2
5
4
2
112
113
5
5
2
6
www.xilinx.com
DS013 (v2.7) March 31, 2006
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Table 3: XCR3256XL I/O Pins (Continued)
Function Macro-
Function Macro-
Block
cell
TQ144 PQ208 FT256
CS280
Block
cell
11
12
13
14
15
16
1
TQ144 PQ208 FT256
CS280
-
5
6
-
-
-
-
-
-
-
-
7
-
-
45
46
47
48
49
65
64
62
61
60
-
-
M16
M14
N16
L12
P15
T12
R12
N11
T13
P12
-
5
7
7
77
R17
R15
T17
T16
U19
T13
W14
T14
R14
W15
-
5
8
-
-
-
-
7
-
5
9
-
-
-
-
7
75
5
10
11
12
13
14
15
16
1
-
-
-
-
7
74
5
-
-
-
-
7
-
5
84
-
34
35
36
37
38
78
77
76
73
71
-
K15
K14
K16
K13
L15
R9
N9
T10
P10
R10
-
M17
N16
N19
N18
N17
U10
T10
W11
U11
T11
-
8
66
5
8
2
67
5
83
82
-
8
3
68
5
8
4
69
5
8
5
-
6
-
8
6
-
6
2
55
56
-
8
7
-
-
-
-
6
3
8
8
-
-
-
-
6
4
8
9
-
-
-
-
6
5
60
-
8
10
11
12
13
14
15
16
1
-
-
-
-
6
6
8
-
-
-
-
6
7
-
-
-
-
8
70
59
58
57
56
55
153
154
159
160
161
-
R13
M11
T14
N12
R14
D3
C1
B4
E6
A4
-
U15
V15
T15
V16
W17
B1
C3
A4
B5
C5
-
6
8
-
-
-
-
8
-
6
9
-
-
-
-
8
71
6
10
11
12
13
14
15
16
1
-
-
-
-
8
-
6
-
-
-
-
8
72
6
61
62
63
-
70
69
68
67
66
39
40
42
43
44
-
T11
N10
P11
M10
R11
K12
L16
M15
N15
L13
-
W12
U12
T12
V13
U13
P16
P18
R19
R16
R18
-
9
2
6
9
2
1
6
9
3
-
6
9
4
-
6
65
81
-
9
5
143
7
9
6
-
7
2
9
7
-
-
-
-
7
3
80
79
78
-
9
8
-
-
-
-
7
4
9
9
-
-
-
-
-
7
5
9
10
11
12
13
14
15
-
-
-
7
6
9
-
-
-
-
7
7
-
-
-
-
9
-
162
163
164
166
C5
B5
D6
A5
A5
E6
D6
B6
7
8
-
-
-
-
9
142
141
140
7
9
-
-
-
-
9
7
10
-
-
-
-
9
DS013 (v2.7) March 31, 2006
www.xilinx.com
7
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Table 3: XCR3256XL I/O Pins (Continued)
Function Macro-
Function Macro-
Block
cell
16
1
TQ144 PQ208 FT256
CS280
A6
D2
D1
E3
E2
E4
-
Block
12
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
14
cell
TQ144 PQ208 FT256
CS280
9
139
167
151
150
149
148
147
-
C6
D1
E4
D2
E3
E1
-
5
15
136
H4
-
H3
-
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
4(1)
6
-
-
-
2
-
7
-
-
-
-
3
5
8
-
-
-
4
6
9
-
-
-
-
5
7
10
11
12
13
14
15
16
1
-
-
-
-
6
-
-
-
-
-
7
-
-
-
-
16
-
135
133
132
131
130
79
80
81
84
86
-
G2
J1
J3
H2
J5
P9
T9
P8
R8
N8
-
H2
J2
J3
K2
K3
W10
T9
U9
T8
T7
-
8
-
-
-
-
9
-
-
-
-
18
19
-
10
11
12
13
14
15
16
1
-
-
-
-
-
-
-
-
8
146
145
144
142
141
168
169
170
171
172
-
F4
F1
G5
E2
F3
B6
E7
A6
D7
B7
-
E1
F5
F3
F4
G3
D7
C7
B7
A7
C8
-
-
-
2
54
53
-
9
10
11
-
3
4
5
49
-
6
2
-
7
-
-
-
-
3
138
-
8
-
-
-
-
4
9
-
-
-
-
5
137
-
10
11
12
13
14
15
16
1
-
-
-
-
6
-
-
-
-
7
-
-
-
-
48
47
46
-
87
88
89
90
91
129
128
127(1)
126
124
-
T8
P7
R7
P6
T7
J2
J4
K1(1)
K3
K2
-
W7
V7
U7
W6
T6
K4
L1
L2(1)
L3
M1
-
8
-
-
-
-
9
-
-
-
-
10
11
12
13
14
15
16
1
-
-
-
-
-
-
-
-
45
20(1)
-
136
134
133
132
131
-
173
175
176(1)
177
178
140
139
138
137
C7
C8
A7(1)
D8
B8
F2
G4
G1
H1
B8
C9
B9(1)
D10
C10
G2
G1
G4
H1
2
3
21
22
23
-
4
5
6
2
-
7
-
-
-
-
3
12
14
8
-
-
-
-
4
9
-
-
-
-
8
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DS013 (v2.7) March 31, 2006
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Table 3: XCR3256XL I/O Pins (Continued)
Function Macro-
Function Macro-
Block
14
14
14
14
14
14
14
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
cell
10
11
12
13
14
15
16
1
TQ144 PQ208 FT256
CS280
-
Block
cell
TQ144 PQ208 FT256
CS280
V1
-
-
-
-
-
-
16
15
35
36
109
108
N3
T1
-
16
16
U2
25
-
123
122
121
120
119
92
93
95
96
97
-
L1
K4
L3
K5
M1
N7
R6
M7
T5
T6
-
M3
M4
N1
N2
N3
V6
U6
R6
W5
T5
-
Notes:
1. JTAG pins.
26
27
28
44
43
42
41
40
-
2
3
4
5
6
7
-
-
-
-
8
-
-
-
-
9
-
-
-
-
10
11
12
13
14
15
16
1
-
-
-
-
-
-
-
-
-
98
99
100
101
102
118
117
115
114
113
-
R5
N6
T4
P5
R4
L2
M2
M3
N2
L5
-
V5
U5
W4
U4
W3
P1
P2
P4
R3
R2
-
39
38
-
37
-
2
-
3
29
30
31
-
4
5
6
7
-
-
-
-
8
-
-
-
-
9
-
-
-
-
10
11
12
13
14
-
-
-
-
-
-
-
-
32
-
112
111
110
P1
M4
R1
R4
T3
U1
34
DS013 (v2.7) March 31, 2006
www.xilinx.com
9
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 4: XCR3256XL Global, JTAG, Port Enable, Power, and No Connect Pins
Pin Type
IN0 / CLK0
IN1 / CLK1
IN2 / CLK2
IN3 / CLK3
TCK
TQ144
128
127
126
125
89
PQ208
181
FT256
B9
CS280
A10
182
A8
D11
183
C9
C11
184
B10
J13
A7
B11
30
L19
TDI
4
176
B9
TDO
104
189
C10
C12
TMS
20
127
K1
L2
P3(1)
PORT_EN
Vcc
13(1)
116(1)
N1(1)
24, 50, 51, 58, 73, 76, 5, 23, 41, 63, 74, 83, 85, E8, E9, F7, F8, F9, F10,
A11, B10, C6, C14,
95, 115, 123, 130, 144
107, 125, 143, 165,
179, 186, 191
G6, G11, H5, H6, H11, D13, D17, F2, J19, L4,
J6, J11, J12, K6, K11, P15, T18, U8, U14, V2,
L7, L8, L9, L10, M8, M9
V9, V11
GND
3, 17, 33, 52, 57, 59, 64, 14, 32, 50, 72, 75, 82,
85, 105, 124, 129, 135 94, 134, 152, 174, 180,
185, 200
E5, F6, F11, G7, G8,
G9, G10, H7, H8, H9,
H10, J7, J8, J9, J10, K7, G15, H5, H15, J5, J15,
E5, E7, E8, E9, E10,
E11, E12, E13, G5,
K8, K9, K10, L6, L11
K5, K15, L5, L15, M5,
M15, N5, N15, R7, R8,
R9, R10, R11, R12, R13
No Connects
-
1, 2, 51, 52, 53, 54, 103, A1, A2, A3, A15, A16,
104, 105, 106, 155, B1, B2, B3, B14, B15,
A1, A2, A3, A8, A9,
A19, B2, B3, B4, B14,
156, 157, 158, 207, 208 B16, C2, C3, C4, C14, B15, B16, C1, C2, C4,
C15, D4, D5, D10, D13,
D14, E12, F5, G3, H3,
L4, M5, M6, M12, M13,
C15, C17, C18, C19,
D3, D4, D5, D8, D9,
D16, D18, D19, E16,
N4, N5, N13, N14, P2, E17, F1, F16, G18, H4,
P3, P4, P13, P14, P16, J1, J4, K1, K19, M2,
R2, R3, R15, R16, T2, M19, N4, P5, P17, P19,
T3, T15, T16
R1, R5, T1, T2, T4, T19,
U3, U16, U17, U18, V3,
V4, V8, V10, V12, V14,
V17, V18, V19, W1,
W2, W8, W9, W13,
W16, W18, W19
Notes:
1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full
explanation.
10
www.xilinx.com
DS013 (v2.7) March 31, 2006
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Device Part Marking and Ordering Combination Information
R
Device Type
Package
XCRxxxxXL
TQ144
This line not
related to device
part number
Speed
7C
Operating Range
1
Sample package with part marking.
Speed
Device Ordering and
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range(1)
Part Marking Number
XCR3256XL-7TQ144C
XCR3256XL-7TQG144C
XCR3256XL-7PQ208C
XCR3256XL-7PQG208C
XCR3256XL-7FT256C
XCR3256XL-7CS280C
XCR3256XL-7CSG280C
XCR3256XL-10TQ144C
XCR3256XL-10TQG144C
XCR3256XL-10PQ208C
XCR3256XL-10PQG208C
XCR3256XL-10FT256C
XCR3256XL-10CS280C
XCR3256XL-10CSG280C
XCR3256XL-10TQ144I
XCR3256XL-10TQG144I
XCR3256XL-10PQ208I
XCR3256XL-10PQG208I
XCR3256XL-10FT256I
XCR3256XL-10CS280I
XCR3256XL-10CSG280I
XCR3256XL-12TQ144C
XCR3256XL-12TQG144C
XCR3256XL-12PQ208C
XCR3256XL-12PQG208C
Package Type
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
12 ns
12 ns
12 ns
12 ns
TQ144 144-pin
TQG144 144-pin
PQ208 208-pin
PQG208 208-pin
FT256 256-ball
CS280 280-ball
CSG280 280-ball
TQ144 144-pin
TQG144 144-pin
PQ208 208-pin
PQG208 208-pin
FT256 256-ball
CS280 280-ball
CSG280 280-ball
TQ144 144-pin
TQG144 144-pin
PQ208 208-pin
PQG208 208-pin
FT256 256-ball
CS280 280-ball
CSG280 280-ball
TQ144 144-pin
TQG144 144-pin
PQ208 208-pin
PQG208 208-pin
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Fine-Pitch BGA (FT)
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
Chip Scale Package (CSP)
Chip Scale Package (CSP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Fine-Pitch BGA (FT)
Chip Scale Package (CSP)
Chip Scale Package (CSP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Fine-Pitch BGA (FT)
I
I
I
I
Chip Scale Package (CSP)
I
Chip Scale Package (CSP); Pb-Free
Thin Quad Flat Pack (TQFP)
I
C
C
C
C
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
DS013 (v2.7) March 31, 2006
www.xilinx.com
11
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Speed
Device Ordering and
Part Marking Number
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range(1)
Package Type
Fine-Pitch BGA (FT)
XCR3256XL-12FT256C
XCR3256XL-12CS280C
XCR3256XL-12CSG280C
XCR3256XL-12TQ144I
XCR3256XL-12TQG144I
XCR3256XL-12PQ208I
XCR3256XL-12PQG208I
XCR3256XL-12FT256I
XCR3256XL-12CS280I
XCR3256XL-12CSG280I
Notes:
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
FT256 256-ball
CS280 280-ball
CSG280 280-ball
TQ144 144-pin
TQG144 144-pin
PQ208 208-pin
PQG208 208-pin
FT256 256-ball
CS280 280-ball
CSG280 280-ball
C
C
C
I
Chip Scale Package (CSP)
Chip Scale Package (CSP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Fine-Pitch BGA (FT)
I
I
I
I
Chip Scale Package (CSP)
I
Chip Scale Package (CSP); Pb-Free
I
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
CoolRunner XPLA3 Data Sheets and Application Notes
Device Packages
Device Package User Guide
Revision History
The following table shows the revision history for this document
Date
Version
1.0
Revision
01/21/00
02/10/00
05/03/00
11/20/00
12/11/00
01/17/01
03/05/01
04/11/01
04/19/01
Initial Xilinx release.
Updated Pinout table.
1.1
1.2
Minor updates and added Boundary Scan to pinout table.
Updated pinout tables; corrected note in Table 4 to read: "port enable pin is brought High".
Updated specifications and pinout tables.
1.3
1.4
1.5
Removed Timing Model.
1.6
Added 256-ball Fine-Pitch Ball Grid Array Package.
1.7
Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec.
Updated Typical I/V curve, Figure 2: added voltage levels.
1.8
12
www.xilinx.com
DS013 (v2.7) March 31, 2006
Product Specification
R
XCR3256XL 256 Macrocell CPLD
Date
Version
Revision
Moved ICC vs Freq. Figure 1 and Table 1 to page 1. Added single p-term setup time (TSU1)
01/08/02
1.9
to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated TSUF spec
to match software timing. Added TINIT spec. Updated TCONFIG spec. Updated THI spec to
correct a typo. Updated AC Load Circuit diagram to more closely resemble true test
conditions, added note for TPOD delay measurement.
11/20/02
2.0
Updated TPCO (added TPTCK), TFIN, and TOUT to match timing model and software.
Updated the following specs based on characterization of product after move to UMC
fabrication: fSYSTEM, VOH,TCONFIG, TINIT, TLOGI3, TF. Updated Typical ICC vs. Freq. and
Derating Curve for TPD2 (improved to 6.5 ns for 16 outputs switching) per new
characterization data. Updated ordering information to new format.
01/27/03
07/15/03
08/21/03
11/5/03
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Moved incorrect note for VOH to line 2 from line 3 in DC table.
Updated test conditions for IIL and IIH.
Updated Package Device Marking Pin 1 orientation.
Updated from Preliminary Product Specification to Product Specification.
Add Tsol specification. Add links to application notes and data sheets.
Added ICCSB Typical and TAPRPW specifications. Removed TSOL specification.
Added Warranty Disclaimer. Added Pb-Free ordering information.
02/13/04
04/08/05
03/31/06
DS013 (v2.7) March 31, 2006
www.xilinx.com
13
Product Specification
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