XCS40-3PQG208I [XILINX]
Field Programmable Gate Array, 784 CLBs, 13000 Gates, 125MHz, CMOS, PQFP208, PLASTIC, QFP-208;型号: | XCS40-3PQG208I |
厂家: | XILINX, INC |
描述: | Field Programmable Gate Array, 784 CLBs, 13000 Gates, 125MHz, CMOS, PQFP208, PLASTIC, QFP-208 时钟 栅 可编程逻辑 |
文件: | 总83页 (文件大小:760K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Spartan and Spartan-XL FPGA
Families Data Sheet
0
0
DS060 (v2.0) March 1, 2013
Product Specification
•
System level features
Introduction
-
-
-
-
Available in both 5V and 3.3V versions
On-chip SelectRAM™ memory
Fully PCI compliant
Full readback capability for program verification
and internal node observability
®
The Spartan and the Spartan-XL FPGA families are a
high-volume production FPGA solution that delivers all the
key requirements for ASIC replacement up to 40,000 gates.
These requirements include high performance, on-chip
RAM, core solutions and prices that, in high volume,
approach and in many cases are equivalent to mask pro-
grammed ASIC devices.
-
-
-
-
-
-
Dedicated high-speed carry logic
Internal 3-state bus capability
Eight global low-skew clock or signal networks
IEEE 1149.1-compatible Boundary Scan logic
Low cost plastic packages available in all densities
Footprint compatibility in common packages
®
By streamlining the Spartan series feature set, leveraging
advanced process technologies and focusing on total cost
management, the Spartan series delivers the key features
required by ASIC and other high-volume logic users while
avoiding the initial cost, long development cycles and inher-
ent risk of conventional ASICs. The Spartan and Spar-
tan-XL families in the Spartan series have ten members, as
shown in Table 1.
•
Fully supported by powerful Xilinx ISE Classics
development system
-
Fully automatic mapping, placement and routing
Additional Spartan-XL Family Features
Spartan/Spartan-XL FPGA Features
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the separate data sheets for more
advanced members for the Spartan Series.
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional MUX or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compliant
•
First ASIC replacement FPGA for high-volume
production with on-chip RAM
•
•
•
•
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCORE and LogiCORE™
predefined solutions available
Enhanced Boundary Scan
Express Mode configuration
•
•
Unlimited reprogrammability
Low cost
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
Max
System
Gates (Logic and RAM)
Typical
Gate Range
Max.
Avail. Distributed
CLBs Flip-flops User I/O RAM Bits
Total
Logic
Cells
238
CLB
Matrix
Total
No. of
(1)
Device
XCS05 and XCS05XL
XCS10 and XCS10XL
XCS20 and XCS20XL
5,000
10,000
20,000
30,000
40,000
2,000-5,000
3,000-10,000
7,000-20,000
10,000-30,000
13,000-40,000
10 x 10
14 x 14
20 x 20
24 x 24
28 x 28
100
196
400
576
784
360
616
77
3,200
6,272
466
112
160
192
950
1,120
1,536
2,016
12,800
18,432
25,088
XCS30 and XCS30XL 1368
XCS40 and XCS40XL 1862
Notes:
(2)
205
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
2. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.
© 1998-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
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Product Specification
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Spartan and Spartan-XL FPGA Families Data Sheet
memory cells determine the logic functions and intercon-
nections implemented in the FPGA. The FPGA can either
actively read its configuration data from an external serial
PROM (Master Serial mode), or the configuration data can
be written into the FPGA from an external device (Slave
Serial mode).
General Overview
Spartan series FPGAs are implemented with a regular, flex-
ible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources (routing channels), and sur-
rounded by a perimeter of programmable Input/Output
Blocks (IOBs), as seen in Figure 1. They have generous
routing resources to accommodate the most complex inter-
connect patterns.
Spartan series FPGAs can be used where hardware must
be adapted to different user applications. FPGAs are ideal
for shortening design and development cycles, and also
offer a cost-effective solution for production rates well
beyond 50,000 systems per month.
The devices are customized by loading configuration data
into internal static memory cells. Re-programming is possi-
ble an unlimited number of times. The values stored in these
B-
SCAN
OSC
IOB
IOB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
IOB
IOB
Routing Channels
IOB
IOB
IOB
IOB
CLB
CLB
IOB
IOB
IOB
IOB
START
-UP
RDBK
VersaRing Routing Channels
DS060_01_081100
Figure 1: Basic FPGA Block Diagram
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan and Spartan-XL devices provide system clock
rates exceeding 80 MHz and internal performance in
excess of 150 MHz. In addition to the conventional benefit
of high volume programmable logic solutions, Spartan
series FPGAs also offer on-chip edge-triggered single-port
and dual-port RAM, clock enables on all flip-flops, fast carry
logic, and many other features.
Configurable Logic Blocks (CLBs)
The CLBs are used to implement most of the logic in an
FPGA. The principal CLB elements are shown in the simpli-
fied block diagram in Figure 2. There are three look-up
tables (LUT) which are used as logic function generators,
two flip-flops and two groups of signal steering multiplexers.
There are also some more advanced features provided by
the CLB which will be covered in the Advanced Features
Description, page 13.
The Spartan/XL families leverage the highly successful
XC4000 architecture with many of that family’s features and
benefits. Technology advancements have been derived
from the XC4000XLA process developments.
Function Generators
Two 16 x 1 memory look-up tables (F-LUT and G-LUT) are
used to implement 4-input function generators, each offer-
ing unrestricted logic implementation of any Boolean func-
tion of up to four independent input signals (F1 to F4 or G1
to G4). Using memory look-up tables the propagation delay
is independent of the function implemented.
Logic Functional Description
The Spartan series uses a standard FPGA structure as
shown in Figure 1, page 2. The FPGA consists of an array
of configurable logic blocks (CLBs) placed in a matrix of
routing channels. The input and output of signals is
achieved through a set of input/output blocks (IOBs) forming
a ring around the CLBs and routing channels.
A third 3-input function generator (H-LUT) can implement
any Boolean function of its three inputs. Two of these inputs
are controlled by programmable multiplexers (see box "A" of
Figure 2). These inputs can come from the F-LUT or G-LUT
outputs or from CLB inputs. The third input always comes
from a CLB input. The CLB can, therefore, implement cer-
tain functions of up to nine inputs, like parity checking. The
three LUTs in the CLB can also be combined to do any arbi-
trarily defined Boolean function of five inputs.
•
•
•
CLBs provide the functional elements for implementing
the user’s logic.
IOBs provide the interface between the package pins
and internal signal lines.
Routing channels provide paths to interconnect the
inputs and outputs of the CLBs and IOBs.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
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Spartan and Spartan-XL FPGA Families Data Sheet
B
G-LUT
G4
G3
G2
G4
SR
Q
D
YQ
Logic
Function
of
G1-G4
G3
G2
G1
G
CK
EC
G1
SR
H-LUT
Y
G
Logic
Function
of
F-G-H1
H1
H
H1
DIN
F4
F
F4
F3
F2
F1
SR
A
Q
D
XQ
Logic
Function
of
F1-F4
F3
G
CK
EC
F2
F1
X
F-LUT
Multiplexer Controlled
by Configuration Program
K
EC
DS060_02_0506 01
Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)
A CLB can implement any of the following functions:
Flip-Flops
•
Any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
Each CLB contains two flip-flops that can be used to regis-
ter (store) the function generator outputs. The flip-flops and
function generators can also be used independently (see
Figure 2). The CLB input DIN can be used as a direct input
to either of the two flip-flops. H1 can also drive either
flip-flop via the H-LUT with a slight additional delay.
Note: When three separate functions are generated, one of
the function outputs must be captured in a flip-flop internal to
the CLB. Only two unregistered function generator outputs
are available from the CLB.
The two flip-flops have common clock (CK), clock enable
(EC) and set/reset (SR) inputs. Internally both flip-flops are
also controlled by a global initialization signal (GSR) which
is described in detail in Global Signals: GSR and GTS,
page 20.
•
•
Any single function of five variables
Any function of four variables together with some
functions of six variables
•
Some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
Latches (Spartan-XL Family Only)
The Spartan-XL family CLB storage elements can also be
configured as latches. The two latches have common clock
(K) and clock enable (EC) inputs. Functionality of the stor-
age element is described in Table 2.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
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Spartan and Spartan-XL FPGA Families Data Sheet
.
Clock Input
Table 2: CLB Storage Element Functionality
Each flip-flop can be triggered on either the rising or falling
clock edge. The CLB clock line is shared by both flip-flops.
However, the clock is individually invertible for each flip-flop
(see CK path in Figure 3). Any inverter placed on the clock
line in the design is automatically absorbed into the CLB.
Mode
CK
EC
SR
D
Q
Power-Up or
GSR
X
X
X
X
SR
Flip-Flop
Operation
X
X
1*
X
1
X
D
X
X
D
SR
D
Clock Enable
0*
0*
0*
0*
The clock enable line (EC) is active High. The EC line is
shared by both flip-flops in a CLB. If either one is left discon-
nected, the clock enable for that flip-flop defaults to the
active state. EC is not invertible within the CLB. The clock
enable is synchronous to the clock and must satisfy the
setup and hold timing specified for the device.
0
1
0
Q
Latch
Operation
(Spartan-XL)
1*
1*
Q
D
Both
Legend:
X
X
0
0*
X
Q
Set/Reset
The set/reset line (SR) is an asynchronous active High con-
trol of the flip-flop. SR can be configured as either set or
reset at each flip-flop. This configuration option determines
the state in which each flip-flop becomes operational after
configuration. It also determines the effect of a GSR pulse
during normal operation, and the effect of a pulse on the SR
line of the CLB. The SR line is shared by both flip-flops. If
SR is not specified for a flip-flop the set/reset for that flip-flop
defaults to the inactive state. SR is not invertible within the
CLB.
Don’t care
Rising edge (clock not inverted).
SR
0*
Set or Reset value. Reset is default.
Input is Low or unconnected (default
value)
1*
Input is High or unconnected (default
value)
CLB Signal Flow Control
SR
In addition to the H-LUT input control multiplexers (shown in
box "A" of Figure 2, page 4) there are signal flow control
multiplexers (shown in box "B" of Figure 2) which select the
signals which drive the flip-flop inputs and the combinatorial
CLB outputs (X and Y).
GND
GSR
Each flip-flop input is driven from a 4:1 multiplexer which
selects among the three LUT outputs and DIN as the data
source.
SD
D
D
Q
Q
Each combinatorial output is driven from a 2:1 multiplexer
which selects between two of the LUT outputs. The X output
can be driven from the F-LUT or H-LUT, the Y output from
G-LUT or H-LUT.
CK
RD
EC
Control Signals
Vcc
There are four signal control multiplexers on the input of the
CLB. These multiplexers allow the internal CLB control sig-
nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be
driven from any of the four general control inputs (C1-C4 in
Figure 4) into the CLB. Any of these inputs can drive any of
the four internal control signals.
Multiplexer Controlled
by Configuration Program
DS060_03_041901
Figure 3: CLB Flip-Flop Functional Block Diagram
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Spartan and Spartan-XL FPGA Families Data Sheet
DIN
H1
GSR
SD
RD
D
D
Q
Q
C1
C2
C3
C4
CK
SR
EC
EC
Vcc
Multiplexer Controlled
by Configuration Program
Multiplexer Controlled
by Configuration Program
DS060_05_041901
DS060_04_081100
Figure 5: IOB Flip-Flop/Latch Functional Block
Diagram
Figure 4: CLB Control Signal Interface
IOB Input Signal Path
The four internal control signals are:
The input signal to the IOB can be configured to either go
directly to the routing channels (via I1 and I2 in Figure 6) or
to the input register. The input register can be programmed
as either an edge-triggered flip-flop or a level-sensitive
latch. The functionality of this register is shown in Table 3,
and a simplified block diagram of the register can be seen in
Figure 5.
•
•
EC: Enable Clock
SR: Asynchronous Set/Reset or H function generator
Input 0
DIN: Direct In or H function generator Input 2
H1: H function generator Input 1.
•
•
Input/Output Blocks (IOBs)
Table 3: Input Register Functionality
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals. Figure 6
shows a simplified functional block diagram of the Spar-
tan/XL FPGA IOB.
Mode
CK
EC
D
Q
Power-Up or
GSR
X
X
X
SR
Flip-Flop
1*
X
D
X
X
D
X
D
Q
Q
D
Q
0
1
0
X
Latch
1*
1*
0
Both
Legend:
X
Don’t care.
Rising edge (clock not inverted).
SR
0*
Set or Reset value. Reset is default.
Input is Low or unconnected (default
value)
1*
Input is High or unconnected (default
value)
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Spartan and Spartan-XL FPGA Families Data Sheet
The register choice is made by placing the appropriate
library symbol. For example, IFD is the basic input flip-flop
(rising edge triggered), and ILD is the basic input latch
(transparent-High). Variations with inverted clocks are also
available. The clock signal inverter is also shown in Figure 5
on the CK line.
using an option in the bitstream generation software. The
Spartan family output levels are also configurable; the two
global adjustments of input threshold and output level are
independent. The inputs of Spartan devices can be driven
by the outputs of any 3.3V device, if the Spartan family
inputs are in TTL mode. Input and output thresholds are
TTL on all configuration pins until the configuration has
been loaded into the device and specifies how they are to
be used. Spartan-XL family inputs are TTL compatible and
3.3V CMOS compatible.
The Spartan family IOB data input path has a one-tap delay
element: either the delay is inserted (default), or it is not.
The Spartan-XL family IOB data input path has a two-tap
delay element, with choices of a full delay, a partial delay, or
no delay. The added delay guarantees a zero hold time with
respect to clocks routed through the global clock buffers.
(See Global Nets and Buffers, page 12 for a description of
the global clock buffers in the Spartan/XL families.) For a
shorter input register setup time, with positive hold-time,
attach a NODELAY attribute or property to the flip-flop.The
output of the input register goes to the routing channels (via
I1 and I2 in Figure 6). The I1 and I2 signals that exit the IOB
can each carry either the direct or registered input signal.
Supported sources for Spartan/XL device inputs are shown
in Table 4.
Spartan-XL family I/Os are fully 5V tolerant even though the
V
is 3.3V. This allows 5V signals to directly connect to the
CC
Spartan-XL family inputs without damage, as shown in
Table 4. In addition, the 3.3V V can be applied before or
CC
after 5V signals are applied to the I/Os. This makes the
Spartan-XL devices immune to power supply sequencing
problems.
The 5V Spartan family input buffers can be globally config-
ured for either TTL (1.2V) or CMOS (VCC/2) thresholds,
GTS
T
D
Q
O
OUTPUT DRIVER
Programmable Slew Rate
Programmable TTL/CMOS Drive
(Spartan only)
CK
EC
OK
Package
Pad
I1
I2
INPUT BUFFER
Delay
D
Q
Programmable
Pull-Up/
Pull-Down
Network
IK
CK
EC
Multiplexer Controlled
by Configuration Program
EC
DS060_06_041901
Figure 6: Simplified Spartan/XL IOB Block Diagram
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family V Clamping
Table 4: Supported Sources for Spartan/XL Inputs
CC
Spartan-XL FPGAs have an optional clamping diode con-
Spartan
Inputs
Spartan-XL
nected from each I/O to V . When enabled they clamp
CC
Inputs
ringing transients back to the 3.3V supply rail. This clamping
3.3V
action is required in 3.3V PCI applications. V clamping is
5V,
5V,
CC
a global option affecting all I/O pins.
Source
TTL CMOS
CMOS
Spartan-XL devices are fully 5V TTL I/O compatible if V
Any device, VCC = 3.3V,
CMOS outputs
CC
√
√
√
√
Unreli-
able
Data
√
√
√
clamping is not enabled. With V
clamping enabled, the
CC
Spartan-XL devices will begin to clamp input voltages to
Spartan family, VCC = 5V,
TTL outputs
one diode voltage drop above V . If enabled, TTL I/O com-
CC
patibility is maintained but full 5V I/O tolerance is sacrificed.
The user may select either 5V tolerance (default) or 3.3V
PCI compatibility. In both cases negative voltage is clamped
to one diode voltage drop below ground.
Any device, VCC = 5V,
TTL outputs (VOH ≤ 3.7V)
Any device, VCC = 5V,
CMOS outputs
√
√ (default
mode)
Spartan-XL devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in Table 5.
Table 5: I/O Standards Supported by Spartan-XL FPGAs
Signaling
Standard
VCC
Clamping
Output
Drive
V
V
V
V
V
OL MAX
IH MAX
IH MIN
IL MAX
OH MIN
TTL
LVTTL
Not allowed
OK
12/24 mA
12/24 mA
24 mA
5.5
2.0
0.8
2.4
2.4
0.4
0.4
3.6
5.5
3.6
3.6
2.0
2.0
0.8
0.8
PCI5V
Not allowed
Required
OK
2.4
0.4
PCI3V
12 mA
50% of V
30% of V
30% of V
90% of V
90% of V
10% of V
10% of V
CC
CC
CC
CC
CC
CC
CC
CC
LVCMOS 3V
12/24 mA
50% of V
Additional Fast Capture Input Latch (Spartan-XL Family
Only)
Table 6: Output Flip-Flop Functionality
Clock
The Spartan-XL family OB has an additional optional latch
on the input. This latch is clocked by the clock used for the
output flip-flop rather than the input clock. Therefore, two
different clocks can be used to clock the two input storage
elements. This additional latch allows the fast capture of
input data, which is then synchronized to the internal clock
by the IOB flip-flop or latch.
Mode
Clock Enable
T
D
Q
Power-Up
or GSR
X
X
0*
X
SR
Flip-Flop
X
0
1*
X
0*
0*
1
X
D
X
X
Q
D
Z
X
0
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active High
input flip-flop. ILFLX is a transparent Low Fast Capture latch
followed by a transparent High input latch. Any of the clock
inputs can be inverted before driving the library element,
and the inverter is absorbed into the IOB.
X
0*
Q
Legend:
X
Don’t care
Rising edge (clock not inverted).
SR
0*
1*
Z
Set or Reset value. Reset is default.
IOB Output Signal Path
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
Output signals can be optionally inverted within the IOB,
and can pass directly to the output buffer or be stored in an
edge-triggered flip-flop and then to the output buffer. The
functionality of this flip-flop is shown in Table 6.
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Spartan and Spartan-XL FPGA Families Data Sheet
Output Multiplexer/2-Input Function Generator
(Spartan-XL Family Only)
By default, a 5V Spartan device output buffer pull-up struc-
ture is configured as a TTL-like totem-pole. The High driver
is an n-channel pull-up transistor, pulling to a voltage one
The output path in the Spartan-XL family IOB contains an
additional multiplexer not available in the Spartan family
IOB. The multiplexer can also be configured as a 2-input
function generator, implementing a pass gate, AND gate,
OR gate, or XOR gate, with 0, 1, or 2 inverted inputs.
transistor threshold below V . Alternatively, the outputs
CC
can be globally configured as CMOS drivers, with additional
p-channel pull-up transistors pulling to V . This option,
CC
applied using the bitstream generation software, applies to
all outputs on the device. It is not individually programma-
ble.
When configured as a multiplexer, this feature allows two
output signals to time-share the same output pad, effec-
tively doubling the number of device outputs without requir-
ing a larger, more expensive package. The select input is
the pin used for the output flip-flop clock, OK.
All Spartan-XL device outputs are configured as CMOS
drivers, therefore driving rail-to-rail. The Spartan-XL family
outputs are individually programmable for 12 mA or 24 mA
output drive.
When the multiplexer is configured as a 2-input function
generator, logic can be implemented within the IOB itself.
Combined with a Global buffer, this arrangement allows
very high-speed gating of a single signal. For example, a
wide decoder can be implemented in CLBs, and its output
gated with a Read or Write Strobe driven by a global buffer.
Any 5V Spartan device with its outputs configured in TTL
mode can drive the inputs of any typical 3.3V device. Sup-
ported destinations for Spartan/XL device outputs are
shown in Table 7.
Three-State Register (Spartan-XL Family Only)
The user can specify that the IOB function generator be
used by placing special library symbols beginning with the
letter "O." For example, a 2-input AND gate in the IOB func-
tion generator is called OAND2. Use the symbol input pin
labeled "F" for the signal on the critical path. This signal is
placed on the OK pin — the IOB input with the shortest
delay to the function generator. Two examples are shown in
Figure 7.
Spartan-XL devices incorporate an optional register control-
ling the three-state enable in the IOBs. The use of the
three-state control register can significantly improve output
enable and disable time.
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-criti-
cal signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
OMUX2
D0
F
O
Spartan/XL devices have a feature called "Soft Start-up,"
designed to reduce ground bounce when all outputs are
turned on simultaneously at the end of configuration.
When the configuration process is finished and the device
starts up, the first activation of the outputs is automatically
slew-rate limited. Immediately following the initial activation
of the I/O, the slew rate of the individual outputs is deter-
mined by the individual configuration option for each IOB.
D1
OAND2
S0
DS060_07_081100
Figure 7: AND and MUX Symbols in Spartan-XL IOB
Output Buffer
An active High 3-state signal can be used to place the out-
put buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control, the
output (O) and output 3-state (T) signals can be inverted.
The polarity of these signals is independently configured for
each IOB (see Figure 6, page 7). An output can be config-
ured as open-drain (open-collector) by tying the 3-state pin
(T) to the output signal, and the input pin (I) to Ground.
Pull-up and Pull-down Network
Programmable pull-up and pull-down resistors are used for
tying unused pins to V or Ground to minimize power con-
CC
sumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to V
The configurable pull-down resistor is an n-channel transis-
tor that pulls to Ground. The value of these resistors is typi-
.
CC
cally 20 KΩ
−
100 KΩ (See "Spartan Family DC
Characteristics Over Operating Conditions" on page 43.).
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This high value makes them unsuitable as wired-AND
pull-up resistors.
falling-edge or rising-edge triggered flip-flops. The clock
inputs for each IOB are independent.
Common Clock Enables
Table 7: Supported Destinations for Spartan/XL
Outputs
The input and output flip-flops in each IOB have a common
clock enable input (see EC signal in Figure 5), which
through configuration, can be activated individually for the
input or output flip-flop, or both. This clock enable operates
exactly like the EC signal on the Spartan/XL FPGA CLB. It
cannot be inverted within the IOB.
Spartan-XL
Outputs
Spartan
Outputs
5V,
5V,
Destination
Any device,
= 3.3V,
3.3V, CMOS
TTL
CMOS
(1)
√
√
Some
Routing Channel Description
V
CC
All internal routing channels are composed of metal seg-
ments with programmable switching points and switching
matrices to implement the desired routing. A structured,
hierarchical matrix of routing channels is provided to
achieve efficient automated routing.
CMOS-threshold
inputs
Any device,
√
√
√
√
V
= 5V,
CC
TTL-thresholdinputs
This section describes the routing channels available in
Spartan/XL devices. Figure 8 shows a general block dia-
gram of the CLB routing channels. The implementation soft-
ware automatically assigns the appropriate resources
based on the density and timing requirements of the design.
The following description of the routing channels is for infor-
mation only and is simplified with some minor details omit-
ted. For an exact interconnect description the designer
should open a design in the FPGA Editor and review the
actual connections in this tool.
Any device,
Unreliable
Data
V
= 5V,
CC
CMOS-threshold
inputs
Notes:
1. Only if destination device has 5V tolerant inputs.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resistor
active. Alternatively, they can be individually configured with
the pull-down resistor, or as a driven output, or to be driven
by an external source. To activate the internal pull-up, attach
the PULLUP library component to the net attached to the
pad. To activate the internal pull-down, attach the PULL-
DOWN library component to the net attached to the pad.
The routing channels will be discussed as follows;
•
CLB routing channels which run along each row and
column of the CLB array.
•
IOB routing channels which form a ring (called a
VersaRing) around the outside of the CLB array. It
connects the I/O with the CLB routing channels.
•
Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
Set/Reset
As with the CLB registers, the GSR signal can be used to
set or clear the input and output registers, depending on the
value of the INIT attribute or property. The two flip-flops can
be individually configured to set or clear on reset and after
configuration. Other than the global GSR net, no user-con-
trolled set/reset signal is available to the I/O flip-flops
(Figure 5). The choice of set or reset applies to both the ini-
tial state of the flip-flop and the response to the GSR pulse.
CLB Routing Channels
The routing channels around the CLB are derived from
three types of interconnects; single-length, double-length,
and longlines. At the intersection of each vertical and hori-
zontal routing channel is a signal steering matrix called a
Programmable Switch Matrix (PSM). Figure 8 shows the
basic routing channel configuration showing single-length
lines, double-length lines and longlines as well as the CLBs
and PSMs. The CLB to routing channel interface is shown
as well as how the PSMs interface at the channel intersec-
tions.
Independent Clocks
Separate clock signals are provided for the input (IK) and
output (OK) flip-flops. The clock can be independently
inverted for each flip-flop within the IOB, generating either
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8 Singles
PSM
PSM
PSM
2 Doubles
3 Longs
CLB
CLB
3 Longs
2 Doubles
PSM
PSM
PSM
2 Doubles
3 Longs 8 Singles 3 Longs
2 Doubles
DS060_09_041901
Figure 8: Spartan/XL CLB Routing Channels and Interface Block Diagram
CLB Interface
Programmable Switch Matrices
A block diagram of the CLB interface signals is shown in
Figure 9. The input signals to the CLB are distributed evenly
on all four sides providing maximum routing flexibility. In
general, the entire architecture is symmetrical and regular.
It is well suited to established placement and routing algo-
rithms. Inputs, outputs, and function generators can freely
swap positions within a CLB to avoid routing congestion
during the placement and routing operation. The exceptions
are the clock (K) input and CIN/COUT signals. The K input
is routed to dedicated global vertical lines as well as four
single-length lines and is on the left side of the CLB. The
CIN/COUT signals are routed through dedicated intercon-
nects which do not interfere with the general routing struc-
ture. The output signals from the CLB are available to drive
both vertical and horizontal channels.
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each PSM consists of programmable pass transis-
tors used to establish connections between the lines (see
Figure 10).
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a dou-
ble-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-Length Lines
Single-length lines provide the greatest interconnect flexibil-
ity and offer fast routing between adjacent blocks. There are
eight vertical and eight horizontal single-length lines associ-
ated with each CLB. These lines connect the switching
matrices that are located in every row and column of CLBs.
Single-length lines are connected by way of the program-
mable switch matrices, as shown in Figure 10. Routing con-
nectivity is shown in Figure 8.
CIN
COUT
G1
Y
G3
C3
F3
Single-length lines incur a delay whenever they go through
a PSM. Therefore, they are not suitable for routing signals
for long distances. They are normally used to conduct sig-
nals within a localized area and to provide the branching for
nets with fanout greater than one.
C1
K
CLB
F1
X
Rev 1.1
DS060_08_081100
Figure 9: CLB Interconnect Signals
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Six Pass Transistors Per
Switch Matrix Interconnect Point
DS060_10_081100
Figure 10: Programmable Switch Matrix
Double-Length Lines
I/O Routing
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a PSM. Double-length lines are
grouped in pairs with the PSMs staggered, so that each line
goes through a PSM at every other row or column of CLBs
(see Figure 8).
Spartan/XL devices have additional routing around the IOB
ring. This routing is called a VersaRing. The VersaRing facil-
itates pin-swapping and redesign without affecting board
layout. Included are eight double-length lines, and four long-
lines.
Global Nets and Buffers
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility.
The Spartan/XL devices have dedicated global networks.
These networks are designed to distribute clocks and other
high fanout control signals throughout the devices with min-
imal skew.
Longlines
Four vertical longlines in each CLB column are driven exclu-
sively by special global buffers. These longlines are in addi-
tion to the vertical longlines used for standard interconnect.
In the 5V Spartan devices, the four global lines can be
driven by either of two types of global buffers; Primary
Global buffers (BUFGP) or Secondary Global buffers
(BUFGS). Each of these lines can be accessed by one par-
ticular Primary Global buffer, or by any of the Secondary
Global buffers, as shown in Figure 11. In the 3V
Spartan-XL devices, the four global lines can be driven by
any of the eight Global Low-Skew Buffers (BUFGLS). The
clock pins of every CLB and IOB can also be sourced from
local interconnect.
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances.
Each Spartan/XL device longline has a programmable split-
ter switch at its center. This switch can separate the line into
two independent routing channels, each running half the
width or height of the array.
Routing connectivity of the longlines is shown in Figure 8.
The longlines also interface to some 3-state buffers which is
described later in 3-State Long Line Drivers, page 19.
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IOB
IOB
IOB
IOB
BUFGS
BUFGP
PGCK1
SGCK4
PGCK4
SGCK1
4
4
BUFGS
BUFGP
4
4
locals
locals
CLB
CLB
CLB
CLB
IOB
IOB
locals
locals
locals
locals
Any BUFGS
Any BUFGS
X4
X4
X4
X4
One BUFGP
per Global Line
One BUFGP
per Global Line
IOB
IOB
locals
locals
BUFGP
BUFGS
SGCK3
PGCK2
SGCK2
PGCK3
BUFGP
BUFGS
IOB
IOB
IOB
IOB
ds060_11_080400
Figure 11: 5V Spartan Family Global Net Distribution
The four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs. The eight Global Low-Skew
buffers in the Spartan-XL devices combine short delay, neg-
ligible skew, and flexibility.
Advanced Features Description
Distributed RAM
Optional modes for each CLB allow the function generators
(F-LUT and G-LUT) to be used as Random Access Memory
(RAM).
Read and write operations are significantly faster for this
on-chip RAM than for off-chip implementations. This speed
advantage is due to the relatively short signal propagation
delays within the FPGA.
The Primary Global buffers must be driven by the semi-ded-
icated pads (PGCK1-4). The Secondary Global buffers can
be sourced by either semi-dedicated pads (SGCK1-4) or
internal nets. Each corner of the device has one Primary
buffer and one Secondary buffer. The Spartan-XL family
has eight global low-skew buffers, two in each corner. All
can be sourced by either semi-dedicated pads (GCK1-8) or
internal nets.
Memory Configuration Overview
There are two available memory configuration modes: sin-
gle-port RAM and dual-port RAM. For both these modes,
write operations are synchronous (edge-triggered), while
read operations are asynchronous. In the single-port mode,
a single CLB can be configured as either a 16 x 1, (16 x 1)
x 2, or 32 x 1 RAM array. In the dual-port mode, a single
CLB can be configured only as one 16 x 1 RAM array. The
different CLB memory configurations are summarized in
Table 8. Any of these possibilities can be individually pro-
grammed into a Spartan/XL FPGA CLB.
Using the library symbol called BUFG results in the software
choosing the appropriate clock buffer, based on the timing
requirements of the design. A global buffer should be spec-
ified for all timing-sensitive global signal distribution. To use
a global buffer, place a BUFGP (primary buffer), BUFGS
(secondary buffer), BUFGLS (Spartan-XL family global
low-skew buffer), or BUFG (any buffer type) element in a
schematic or in HDL code.
Table 8: CLB Memory Configurations
Mode
Single-Port
Dual-Port
16 x 1
(16 x 1) x 2
32 x 1
√
√
√
−
√
−
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•
The 16 x 1 single-port configuration contains a RAM
Table 9: Single-Port RAM Signals
array with 16 locations, each one-bit wide. One 4-bit
address decoder determines the RAM location for write
and read operations. There is one input for writing data
and one output for reading data, all at the selected
address.
RAM Signal
D0 or D1
A[3:0]
Function
Data In
CLB Signal
DIN or H1
Address
Address
Write Enable
Clock
F[4:1] or G[4:1]
A4 (32 x 1 only)
WE
H1
SR
K
•
The (16 x 1) x 2 single-port configuration combines two
16 x 1 single-port configurations (each according to the
preceding description). There is one data input, one
data output and one address decoder for each array.
These arrays can be addressed independently.
The 32 x 1 single-port configuration contains a RAM
array with 32 locations, each one-bit wide. There is one
data input, one data output, and one 5-bit address
decoder.
WCLK
SPO
Single Port Out
(Data Out)
F
or G
OUT OUT
•
•
n
The dual-port mode 16 x 1 configuration contains a
RAM array with 16 locations, each one-bit wide. There
are two 4-bit address decoders, one for each port. One
port consists of an input for writing and an output for
reading, all at a selected address. The other port
consists of one output for reading from an
16 x 1
32 x 1
RAM ARRAY
n
A[n-1:0]
independently selected address.
WE
WRITE
CONTROL
READ
OUT
The appropriate choice of RAM configuration mode for a
given design should be based on timing and resource
requirements, desired functionality, and the simplicity of the
design process. Selection criteria include the following:
Whereas the 32 x 1 single-port, the (16 x 1) x 2 single-port,
and the 16 x 1 dual-port configurations each use one entire
CLB, the 16 x 1 single-port configuration uses only one half
of a CLB. Due to its simultaneous read/write capability, the
dual-port RAM can transfer twice as much data as the sin-
gle-port RAM, which permits only one data operation at any
given time.
SPO
D0 or D1
WCLK
DS060_12_043010
Notes:
1. The (16 x 1) x 2 configuration combines two 16 x 1 single-port
RAMs, each with its own independent address bus and data
input. The same WE and WCLK signals are connected to both
RAMs.
2. n = 4 for the 16 x 1 and (16 x 1) x 2 configurations. n = 5 for the
32 x 1 configuration.
Figure 12: Logic Diagram for the Single-Port RAM
CLB memory configuration options are selected by using
the appropriate library symbol in the design entry.
Writing data to the single-port RAM is essentially the same
as writing to a data register. It is an edge-triggered (syn-
chronous) operation performed by applying an address to
the A inputs and data to the D input during the active edge
of WCLK while WE is High.
Single-Port Mode
There are three CLB memory configurations for the sin-
gle-port RAM: 16 x 1, (16 x 1) x 2, and 32 x 1, the functional
organization of which is shown in Figure 12.
The timing relationships are shown in Figure 13. The High
logic level on WE enables the input data register for writing.
The active edge of WCLK latches the address, input data,
and WE signals. Then, an internal write pulse is generated
that loads the data into the memory cell.
The single-port RAM signals and the CLB signals (Figure 2,
page 4) from which they are originally derived are shown in
Table 9.
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inverted with respect to the sense of the flip-flop clock
inputs. Consequently, within the same CLB, data at the
RAM SPO line can be stored in a flip-flop with either the
same or the inverse clock polarity used to write data to the
RAM.
TWPS
WCLK (K)
WE
TWHS
TDHS
TAHS
TWSS
The WE input is active High and cannot be inverted within
the CLB.
Allowing for settling time, the data on the SPO output
reflects the contents of the RAM location currently
addressed. When the address changes, following the asyn-
TDSS
DATA IN
chronous delay T , the data stored at the new address
ILO
TASS
location will appear on SPO. If the data at a particular RAM
address is overwritten, after the delay T
will appear on SPO.
, the new data
WOS
ADDRESS
Dual-Port Mode
TILO
TILO
In dual-port mode, the function generators (F-LUT and
G-LUT) are used to create a 16 x 1 dual-port memory. Of
the two data ports available, one permits read and write
operations at the address specified by A[3:0] while the sec-
ond provides only for read operations at the address speci-
fied independently by DPRA[3:0]. As a result, simultaneous
read/write operations at different addresses (or even at the
same address) are supported.
TWOS
DATA OUT
OLD
NEW
DS060_13_080400
Figure 13: Data Write and Access Timing for RAM
WCLK can be configured as active on either the rising edge
(default) or the falling edge. While the WCLK input to the
RAM accepts the same signal as the clock input to the asso-
ciated CLB’s flip-flops, the sense of this WCLK input can be
The functional organization of the 16 x 1 dual-port RAM is
shown in Figure 14. The dual-port RAM signals and the
4
16 x 1
RAM
4
4
A[3:0]
WE
D
WRITE
CONTROL
READ
OUT
SPO
WCLK
16 x 1
RAM
4
DPRA[3:0]
DPO
WRITE
CONTROL
READ
OUT
DS060_14_043001
Figure 14: Logic Diagram for the Dual-Port RAM
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CLB signals from which they are originally derived are
shown in Table 10.
attached to the RAM or ROM symbol, as described in the
library guide. If not defined, all RAM contents are initialized
to zeros, by default.
Table 10: Dual-Port RAM Signals
RAM initialization occurs only during device configuration.
The RAM content is not affected by GSR.
RAM Signal
Function
CLB Signal
DIN
D
Data In
More Information on Using RAM Inside CLBs
Three application notes are available from Xilinx that dis-
cuss synchronous (edge-triggered) RAM: "Xilinx Edge-Trig-
gered and Dual-Port RAM Capability," "Implementing FIFOs
in Xilinx RAM," and "Synchronous and Asynchronous FIFO
Designs." All three application notes apply to both the Spar-
tan and the Spartan-XL families.
A[3:0]
Read Address for
Single-Port.
F[4:1]
Write Address for
Single-Port and
Dual-Port.
DPRA[3:0]
Read Address for
Dual-Port
G[4:1]
Fast Carry Logic
Each CLB F-LUT and G-LUT contains dedicated arithmetic
logic for the fast generation of carry and borrow signals.
This extra output is passed on to the function generator in
the adjacent CLB. The carry chain is independent of normal
routing resources. (See Figure 15.)
WE
WCLK
SPO
Write Enable
Clock
SR
K
Single Port Out
(addressed by A[3:0])
F
OUT
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in micro-
processor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
DPO
Dual Port Out
(addressed by
DPRA[3:0])
G
OUT
The RAM16X1D primitive used to instantiate the dual-port
RAM consists of an upper and a lower 16 x 1 memory array.
The address port labeled A[3:0] supplies both the read and
write addresses for the lower memory array, which behaves
the same as the 16 x 1 single-port RAM array described
previously. Single Port Out (SPO) serves as the data output
for the lower memory. Therefore, SPO reflects the data at
address A[3:0].
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry gen-
erate/propagate are meaningless even at the 16-bit level,
and of marginal benefit at the 32-bit level. This fast carry
logic is one of the more significant features of the Spartan
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the upper
memory. The write address for this memory, however,
comes from the address A[3:0]. Dual Port Out (DPO) serves
as the data output for the upper memory. Therefore, DPO
reflects the data at address DPRA[3:0].
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
By using A[3:0] for the write address and DPRA[3:0] for the
read address, and reading only the DPO output, a FIFO that
can read and write simultaneously is easily generated. The
simultaneous read/write capability possible with the
dual-port RAM can provide twice the effective data through-
put of a single-port RAM alternating read and write opera-
tions.
The timing relationships for the dual-port RAM mode are
shown in Figure 13.
Note that write operations to RAM are synchronous
(edge-triggered); however, data access is asynchronous.
CLB
Initializing RAM at FPGA Configuration
DS060_15_081100
Both RAM and ROM implementations in the Spartan/XL
families are initialized during device configuration. The initial
contents are defined via an INIT attribute or property
Figure 15: Available Spartan/XL Carry Propagation
Paths
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Spartan and Spartan-XL FPGA Families Data Sheet
and Spartan-XL families, speeding up arithmetic and count-
ing functions.
and control inputs with the function generators. The carry
outputs connect to the function generators, where they are
combined with the operands to form the sums.
The carry chain in 5V Spartan devices can run either up or
down. At the top and bottom of the columns where there are
no CLBs above and below, the carry is propagated to the
right. The default is always to propagate up the column, as
shown in the figures. The carry chain in Spartan-XL devices
can only run up the column, providing even higher speed.
Figure 17, page 19 shows the details of the Spartan/XL
FPGA carry logic. This diagram shows the contents of the
box labeled "CARRY LOGIC" in Figure 16.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Mac-
ros (RPMs) that already include these symbols.
Figure 16, page 18 shows a Spartan/XL FPGA CLB with
dedicated fast carry logic. The carry logic shares operand
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C
D
IN
OUT
CARRY
LOGIC
G
H
Y
G
CARRY
G4
G3
G2
G
D
IN
S/R
EC
H
G
F
D
Q
YQ
G1
H1
C
OUT0
H
D
IN
S/R
EC
H
G
F
F
D
Q
XQ
CARRY
F4
F3
F2
F1
F
H
F
X
K
S/R
EC
C
IN
DS060_16_080400
Figure 16: Fast Carry Logic in Spartan/XL CLB
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C
OUT
M
G1
G4
M
1
0
1
G2
G3
0
I
C
TO
OUT0
FUNCTION
GENERATORS
M
F2
F1
M
M
1
0
0
1
M
F4
M
M
0
1
3
1
0
F3
M
C
M
IN
DS060_17_080400
Figure 17: Detail of Spartan/XL Dedicated Carry Logic
Three-State Buffer Example
3-State Long Line Drivers
Figure 18 shows how to use the 3-state buffers to imple-
ment a multiplexer. The selection is accomplished by the
buffer 3-state signal.
A pair of 3-state buffers is associated with each CLB in the
array. These 3-state buffers (BUFT) can be used to drive
signals onto the nearest horizontal longlines above and
below the CLB. They can therefore be used to implement
multiplexed or bidirectional buses on the horizontal long-
lines, saving logic resources.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active High 3-state (T) is
identical to an active Low output enable, as shown in
Table 11.
There is a weak keeper at each end of these two horizontal
longlines. This circuit prevents undefined floating levels.
However, it is overridden by any driver.
Table 11: Three-State Buffer Functionality
IN
X
T
1
0
OUT
Z
The buffer enable is an active High 3-state (i.e., an active
Low enable), as shown in Table 11.
IN
IN
Z = (D • A) + (D • B) + (D • C) + (D • N)
A
B
C
N
~100 kΩ
D
D
D
D
N
A
B
C
BUFT
BUFT
BUFT
BUFT
A
B
C
N
"Weak Keeper"
DS060_18_080400
Figure 18: 3-state Buffers Implement a Multiplexer
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Spartan and Spartan-XL FPGA Families Data Sheet
connected to GTS. A specific pin location can be assigned
to this input using a LOC attribute or property, just as with
any other user-programmable pad. An inverter can option-
ally be inserted after the input buffer to invert the sense of
the Global 3-state signal. Alternatively, GTS can be driven
from any internal node.
On-Chip Oscillator
Spartan/XL devices include an internal oscillator. This oscil-
lator is used to clock the power-on time-out, for configura-
tion memory clearing, and as the source of CCLK in Master
configuration mode. The oscillator runs at a nominal 8 MHz
frequency that varies with process, V , and temperature.
CC
The output frequency falls between 4 MHz and 10 MHz.
STARTUP
The oscillator output is optionally available after configura-
tion. Any two of four resynchronized taps of a built-in divider
are also available. These taps are at the fourth, ninth, four-
teenth and nineteenth bits of the divider. Therefore, if the
primary oscillator output is running at the nominal 8 MHz,
the user has access to an 8-MHz clock, plus any two of
500 kHz, 16 kHz, 490 Hz and 15 Hz. These frequencies
can vary by as much as -50% or +25%.
GSR
GTS
PAD
Q2
Q3
IBUF
Q1, Q4
DONEIN
CLK
DS060_19_080400
Figure 19: Symbols for Global Set/Reset
These signals can be accessed by placing the OSC4 library
element in a schematic or in HDL code. The oscillator is
automatically disabled after configuration if the OSC4 sym-
bol is not used in the design.
Boundary Scan
The "bed of nails" has been the traditional method of testing
electronic assemblies. This approach has become less
appropriate, due to closer pin spacing and more sophisti-
cated assembly methods like surface-mount technology
and multi-layer boards. The IEEE Boundary Scan Standard
1149.1 was developed to facilitate board-level testing of
electronic assemblies. Design and test engineers can
embed a standard test logic structure in their device to
achieve high fault coverage for I/O and internal logic. This
structure is easily implemented with a four-pin interface on
any boundary scan compatible device. IEEE 1149.1-com-
patible devices may be serial daisy-chained together, con-
nected in parallel, or a combination of the two.
Global Signals: GSR and GTS
Global Set/Reset
A separate Global Set/Reset line, as shown in Figure 3,
page 5 for the CLB and Figure 5, page 6 for the IOB, sets or
clears each flip-flop during power-up, reconfiguration, or
when a dedicated Reset net is driven active. This global net
(GSR) does not compete with other routing resources; it
uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, if in reset mode, it is reset by both SR and GSR.
The Spartan and Spartan-XL families implement IEEE
1149.1-compatible BYPASS, PRELOAD/SAMPLE and
EXTEST boundary scan instructions. When the boundary
scan configuration option is selected, three normal user I/O
pins become dedicated inputs for these functions. Another
user output pin becomes the dedicated boundary scan out-
put. The details of how to enable this circuitry are covered
later in this section.
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See Figure 19.) A spe-
cific pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-program-
mable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the GSR signal. Alterna-
tively, GSR can be driven from any internal node.
By exercising these input signals, the user can serially load
commands and data into these devices to control the driving
of their outputs and to examine their inputs. This method is
an improvement over bed-of-nails testing. It avoids the need
to over-drive device outputs, and it reduces the user inter-
face to four pins. An optional fifth pin, a reset for the control
logic, is described in the standard but is not implemented in
the Spartan/XL devices.
Global 3-State
A separate Global 3-state line (GTS) as shown in Figure 6,
page 7 forces all FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is executing an
EXTEST instruction. GTS does not compete with other rout-
ing resources; it uses a dedicated distribution network.
The dedicated on-chip logic implementing the IEEE 1149.1
functions includes a 16-state machine, an instruction regis-
ter and a number of data registers. The functional details
can be found in the IEEE 1149.1 specification and are also
discussed in the Xilinx application note: "Boundary Scan in
FPGA Devices."
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. This is similar to what
is shown in Figure 19 for GSR except the IBUF would be
20
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Spartan and Spartan-XL FPGA Families Data Sheet
Figure 20 is a diagram of the Spartan/XL FPGA boundary
scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
Spartan/XL devices can also be configured through the
boundary scan logic. See Configuration Through the
Boundary Scan Pins, page 37.
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2)
allow user scan data to be shifted out on TDO. The data
register clock (BSCAN.DRCK) is available for control of test
logic which the user may wish to implement with CLBs. The
NAND of TCK and RUN-TEST-IDLE is also provided
(BSCAN.IDLE).
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-state Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PRO-
GRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
Instruction Set
The Spartan/XL FPGA boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in Table 12.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
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Spartan and Spartan-XL FPGA Families Data Sheet
DATA IN
IOB.T
0
1
1
0
sd
D
Q
D
Q
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
sd
1
0
D
Q
D
Q
LE
1
0
IOB.I
1
sd
D
Q
D
Q
0
LE
1
0
IOB.Q
IOB.T
BYPASS
REGISTER
0
1
M
U
X
TDO
1
sd
INSTRUCTION REGISTER
TDI
D
Q
D
Q
0
LE
1
sd
D
Q
D
Q
0
LE
1
0
IOB.I
DATAOUT
UPDATE
EXTEST
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
DS060_20_080400
Figure 20: Spartan/XL Boundary Scan Logic
22
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Spartan and Spartan-XL FPGA Families Data Sheet
Table 12: Boundary Scan Instructions
Instruction
Test
TDO.T
TDO.O
I/O Data
Source
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO
Source
I2
0
I1
0
I0
0
Selected
Top-edge IOBs (Right to Left)
EXTEST
DR
DR
0
0
1
SAMPLE/
PRELOAD
DR
Pin/Logic
Left-edge IOBs (Top to Bottom)
0
0
1
1
1
0
0
1
0
USER 1
BSCAN.
TDO1
User Logic
User Logic
Pin/Logic
MODE.I
USER 2
BSCAN.
TDO2
Bottom-edge IOBs (Left to Right)
READBACK
CONFIGURE
Readback
Data
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
1
1
0
1
1
0
DOUT
Disabled
-
(TDI end)
IDCODE
(Spartan-XL
only)
IDCODE
Register
DS060_21_080400
Figure 21: Boundary Scan Bit Sequence
1
1
1
BYPASS
Bypass
-
Register
BSDL (Boundary Scan Description Language) files for
Spartan/XL devices are available on the Xilinx website in
the File Download area. Note that the 5V Spartan devices
and 3V Spartan-XL devices have different BSDL files.
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-state. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
Including Boundary Scan in a Design
If boundary scan is only to be used during configuration, no
special elements need be included in the schematic or HDL
code. In this case, the special boundary scan pins TDI,
TMS, TCK and TDO can be used for user functions after
configuration.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 22.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 21.
The device-specific pinout tables for the Spartan/XL devices
include the boundary scan locations for each IOB pin.
Optional
To User
Logic
IBUF
BSCAN
TDI
TMS
TCK
TDI
TDO
DRCK
IDLE
TDO
TMS
TCK
To User
Logic
TDO1
TDO2
SEL1
SEL2
From
User Logic
DS060_22_080400
Figure 22: Boundary Scan Example
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Spartan and Spartan-XL FPGA Families Data Sheet
Even if the boundary scan symbol is used in a design, the
input pins TMS, TCK, and TDI can still be used as inputs to
be routed to internal logic. Care must be taken not to force
the chip into an undesired boundary scan state by inadver-
tently applying boundary scan input patterns to these pins.
The simplest way to prevent this is to keep TMS High, and
then apply whatever signal is desired to TDI and TCK.
Configuration State: The configuration state is available to
JTAG controllers.
Configuration Disable: The JTAG port can be prevented
from configuring the FPGA.
TCK Startup: TCK can now be used to clock the start-up
block in addition to other user clocks.
CCLK Holdoff: Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the release
of INIT pin and CCLK cycling.
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant during
configuration. In some applications, a situation may occur
where TMS or TCK is driven during configuration. This may
cause the device to go into boundary scan mode and dis-
rupt the configuration process.
Reissue Configure: The Boundary Scan Configure can be
reissued to recover from an unfinished attempt to configure
the device.
Bypass FF: Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop, and
during EXTEST or SAMPLE/PRELOAD for the IOB register.
To prevent activation of boundary scan during configuration,
do either of the following:
•
TMS: Tie High to put the Test Access Port controller
in a benign RESET state.
Power-Down (Spartan-XL Family Only)
All Spartan/XL devices use a combination of efficient seg-
mented routing and advanced process technology to pro-
vide low power consumption under all conditions. The 3.3V
Spartan-XL family adds a dedicated active Low power-down
pin (PWRDWN) to reduce supply current to 100 μA typical.
The PWRDWN pin takes advantage of one of the unused
No Connect locations on the 5V Spartan device. The user
must de-select the "5V Tolerant I/Os" option in the Configu-
ration Options to achieve the specified Power Down current.
The PWRDWN pin has a default internal pull-up resistor,
allowing it to be left unconnected if unused.
•
TCK: Tie High or Low—do not toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note, "Boundary Scan in FPGA Devices. "
Boundary Scan Enhancements (Spartan-XL Family
Only)
Spartan-XL devices have improved boundary scan func-
tionality and performance in the following areas:
IDCODE: The IDCODE register is supported. By using the
IDCODE, the device connected to the JTAG port can be
determined. The use of the IDCODE enables selective con-
figuration dependent on the FPGA found.
V
must continue to be supplied during Power-down, and
CC
configuration data is maintained. When the PWRDWN pin is
pulled Low, the input and output buffers are disabled. The
inputs are internally forced to a logic Low level, including the
MODE pins, DONE, CCLK, and TDO, and all internal
pull-up resistors are turned off. The PROGRAM pin is not
affected by Power Down. The GSR net is asserted during
Power Down, initializing all the flip-flops to their start-up
state.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
c = the company code (49h for Xilinx)
a = the array dimension in CLBs (ranges from 0Ah for
XCS05XL to 1Ch for XCS40XL)
PWRDWN has a minimum pulse width of 50 ns (Figure 23).
On entering the Power-down state, the inputs will be dis-
abled and the flip-flops set/reset, and then the outputs are
disabled about 10 ns later. The user may prefer to assert the
GTS or GSR signals before PWRDWN to affect the order of
events. When the PWRDWN signal is returned High, the
inputs will be enabled first, followed immediately by the
release of the GSR signal initializing the flip-flops. About 10
ns later, the outputs will be enabled. Allow 50 ns after the
release of PWRDWN before using the device.
f = the family code (02h for Spartan-XL family)
v = the die version number
Table 13: IDCODEs Assigned to Spartan-XL FPGAs
FPGA
IDCODE
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
0040A093h
0040E093h
00414093h
00418093h
0041C093h
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T
PWDW
PWRDWN
50 ns
50 ns
Power Down Mode
Outputs
Description
Min
Symbol
T
50 ns
Power Down Time
PWD
T
Power Down Pulse Width
50 ns
PWDW
DS060_23_041901
Figure 23: PWRDWN Pulse Timing
Power-down retains the configuration, but loses all data
stored in the device flip-flops. All inputs are interpreted as
Low, but the internal combinatorial logic is fully functional.
Make sure that the combination of all inputs Low and all
flip-flops set or reset in your design will not generate internal
oscillations, or create permanent bus contention by activat-
ing internal bus drivers with conflicting data onto the same
long line.
that controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The Xilinx develop-
ment system translates the design into a netlist file. It auto-
matically partitions, places and routes the logic and
generates the configuration data in PROM format.
Configuration Mode Control
5V Spartan devices have two configuration modes.
During configuration, the PWRDWN pin must be High. If the
Power Down state is entered before or during configuration,
the device will restart configuration once the PWRDWN sig-
nal is removed. Note that the configuration pins are affected
by Power Down and may not reflect their normal function. If
there is an external pull-up resistor on the DONE pin, it will
be High during Power Down even if the device is not yet
configured. Similarly, if PWRDWN is asserted before config-
uration is completed, the INIT pin will not indicate status
information.
•
•
MODE = 1 sets Slave Serial mode
MODE = 0 sets Master Serial mode
3V Spartan-XL devices have three configuration modes.
•
•
•
M1/M0 = 11 sets Slave Serial mode
M1/M0 = 10 sets Master Serial mode
M1/M0 = 0X sets Express mode
In addition to these modes, the device can be configured
through the Boundary Scan logic (See "Configuration
Through the Boundary Scan Pins" on page 37.).
Note that the PWRDWN pin is not part of the Boundary
Scan chain. Therefore, the Spartan-XL family has a sepa-
rate set of BSDL files than the 5V Spartan family. Boundary
scan logic is not usable during Power Down.
The Mode pins are sampled prior to starting configuration to
determine the configuration mode. After configuration,
these pin are unused. The Mode pins have a weak pull-up
resistor turned on during configuration. With the Mode pins
High, Slave Serial mode is selected, which is the most pop-
ular configuration mode. Therefore, for the most common
configuration mode, the Mode pins can be left unconnected.
If the Master Serial mode is desired, the MODE/M0 pin
should be connected directly to GND, or through a
pull-down resistor of 1 KΩ or less.
Configuration and Test
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional operation of the internal blocks and their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip.
Spartan/XL devices use several hundred bits of configura-
tion data per CLB and its associated interconnects. Each
configuration bit defines the state of a static memory cell
During configuration, some of the I/O pins are used tempo-
rarily for the configuration process. All pins used during con-
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Spartan and Spartan-XL FPGA Families Data Sheet
figuration are shown in Table 14 and Table 15.
Table 15: Pin Functions During Configuration
(Spartan-XL Family Only)
Table 14: Pin Functions During Configuration
(Spartan Family Only)
CONFIGURATION MODE <M1:M0>
Slave
Serial
[1:1]
Master
Serial
[1:0]
Configuration Mode (MODE Pin)
Express
[0:X]
User
Operation
Slave Serial
(High)
Master Serial
(Low)
User
Operation
M1 (High) (I) M1 (High) (I) M1(Low) (I)
M0 (High) (I) M0 (Low) (I) M0 (I)
HDC (High) HDC (High)
M1
M0
MODE (I)
HDC (High)
LDC (Low)
INIT
MODE (I)
HDC (High)
LDC (Low)
INIT
MODE
I/O
HDC (High)
LDC (Low)
INIT
I/O
I/O
LDC (Low)
INIT
LDC (Low)
INIT
I/O
I/O
I/O
DONE
DONE
DONE
DONE
DONE
DONE
DONE
PROGRAM (I)
CCLK (I)
DIN (I)
PROGRAM (I)
CCLK (O)
DIN (I)
PROGRAM
CCLK (I)
I/O
PROGRAM
(I)
PROGRAM PROGRAM PROGRAM
(I)
(I)
CCLK (I)
CCLK (O)
CCLK (I)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
CCLK (I)
I/O
DOUT
DOUT
SGCK4-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
ALL OTHERS
TDI
TDI
I/O
TCK
TCK
I/O
TMS
TMS
I/O
TDO
TDO
I/O
I/O
Notes:
I/O
1. A shaded table cell represents the internal pull-up used
DIN (I)
DOUT
TDI
DIN (I)
DOUT
TDI
I/O
before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
GCK6-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
I/O
TDI
TCK
TCK
TCK
TMS
TDO
TMS
TDO
TMS
TDO
CS1
ALL
OTHERS
Notes:
1. A shaded table cell represents the internal pull-up used
before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
26
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Spartan and Spartan-XL FPGA Families Data Sheet
falling CCLK edge, and the next FPGA in the daisy chain
accepts data on the subsequent rising CCLK edge. See the
timing diagram in Figure 24.
Master Serial Mode
The Master serial mode uses an internal oscillator to gener-
ate a Configuration Clock (CCLK) for driving potential slave
devices and the Xilinx serial-configuration PROM
(SPROM). The CCLK speed is selectable as either 1 MHz
(default) or 8 MHz. Configuration always starts at the default
slow frequency, then can switch to the higher frequency dur-
ing the first frame. Frequency tolerance is –50% to +25%.
In the bitstream generation software, the user can specify
Fast Configuration Rate, which, starting several bits into the
first frame, increases the CCLK frequency by a factor of
eight. For actual timing values please refer to the specifica-
tion section. Be sure that the serial PROM and slaves are
fast enough to support this data rate. Earlier families such
as the XC3000 series do not support the Fast Configuration
Rate option.
In Master Serial mode, the CCLK output of the device drives
a Xilinx SPROM that feeds the FPGA DIN input. Each rising
edge of the CCLK output increments the Serial PROM inter-
nal address counter. The next data bit is put on the SPROM
data output, connected to the FPGA DIN pin. The FPGA
accepts this data on the subsequent rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user I/O, but LDC is then
restricted to be a permanently High user output after config-
uration. Using DONE can also avoid contention on DIN, pro-
vided the Early DONE option is invoked.
When used in a daisy-chain configuration the Master Serial
FPGA is placed as the first device in the chain and is
referred to as the lead FPGA. The lead FPGA presents the
preamble data, and all data that overflows the lead device,
on its DOUT pin. There is an internal pipeline delay of 1.5
CCLK periods, which means that DOUT changes on the
Figure 25 shows a full master/slave system. The leftmost
device is in Master Serial mode, all other devices in the
chain are in Slave Serial mode.
CCLK
(Output)
T
CKDS
T
DSCK
Serial Data In
n
n + 1
n + 2
Serial DOUT
(Output)
n – 3
n – 2
n – 1
n
DS060_24_080400
Symbol
Description
Min
20
0
Units
ns
T
DIN setup
DIN hold
DSCK
CKDS
CCLK
T
ns
Notes:
1. At power-up, VCC must rise from 2.0V to VCC min in less than 25 ms, otherwise
delay configuration by pulling PROGRAM Low until VCC is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 24: Master Serial Mode Programming Switching Characteristics
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin. There
is an internal delay of 0.5 CCLK periods, which means that
DOUT changes on the falling CCLK edge, and the next
FPGA in the daisy chain accepts data on the subsequent
rising CCLK edge.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configura-
tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
In this mode, an external signal drives the CCLK input of the
FPGA (most often from a Master Serial device). The serial
configuration bitstream must be available at the DIN input of
the lead FPGA a short setup time before each rising CCLK
edge.
Figure 25 shows a full master/slave system. A Spartan/XL
device in Slave Serial mode should be connected as shown
in the third device from the left.
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Slave Serial is the default mode if the Mode pins are left
unconnected, as they have weak pull-up resistors during
configuration.
and is captured by each FPGA when it recognizes the 0010
preamble. Following the length-count data, each FPGA out-
puts a High on DOUT until it has received its required num-
ber of data frames.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
After an FPGA has received its configuration data, it passes
on any additional frame start bits and configuration data on
DOUT. When the total number of configuration clocks
applied after memory initialization equals the value of the
24-bit length count, the FPGAs begin the start-up sequence
and become operational together. FPGA I/O are normally
released two CCLK cycles after the last configuration bit is
received.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins of
all devices in parallel, as shown in Figure 25. Connect the
DOUT of each device to the DIN of the next. The lead or
master FPGA and following slaves each passes resynchro-
nized configuration data coming from a single source. The
header data, including the length count, is passed through
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM File Formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.
Note:
M2, M1, M0 can be shorted
to V
if not used as I/O
CC
V
CC
3.3K
3.3K
3.3K
M0 M1
M2
MODE
DOUT
N/C
MODE
DIN
DOUT
DOUT
DIN
CCLK
CCLK
V
CC
Spartan
Master
Serial
Spartan
Slave
Xilinx SPROM
+5V
FPGA
Slave
3.3K
CLK
CCLK
V
PP
DATA
CE
DIN
LDC
INIT
CEO
PROGRAM
DONE
PROGRAM
DONE
RESET
D/P
INIT
INIT
RESET/OE
(Low Reset Option Used)
PROGRAM
DS060_25_061301
Figure 25: Master/Slave Serial Mode Circuit Diagram
28
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Spartan and Spartan-XL FPGA Families Data Sheet
DIN
Bit n
Bit n + 1
T
T
T
CCL
DCC
CCD
CCLK
T
T
CCH
CCO
DOUT
(Output)
Bit n – 1
Bit n
DS060_26_080400
Symbol
Description
Min
20
0
Max
Units
ns
T
T
T
T
DIN setup
-
DCC
CCD
CCO
CCH
DIN hold
-
30
-
ns
DIN to DOUT
High time
Low time
-
ns
CCLK
40
40
-
ns
T
-
ns
CCL
F
Frequency
12.5
MHz
CC
Notes:
1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are
High.
Figure 26: Slave Serial Mode Programming Switching Characteristics
are in Express mode. Concatenated bitstreams are used to
configure the chain of Express mode devices so that each
device receives a separate header. CCLK pins are tied
together and D0-D7 pins are tied together for all devices
along the chain. A status signal is passed from DOUT to
CS1 of successive devices along the chain. Frame data is
accepted only when CS1 is High and the device’s configura-
tion memory is not already full. The lead device in the chain
has its CS1 input tied High (or floating, since there is an
internal pull-up). The status pin DOUT is pulled Low after
the header is received, and remains Low until the device’s
configuration memory is full. DOUT is then pulled High to
signal the next device in the chain to accept the next header
and configuration data on the D0-D7 bus.
Express Mode (Spartan-XL Family Only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers (Figure 27). A CCLK fre-
quency of 1 MHz is equivalent to a 8 MHz serial rate,
because eight bits of configuration data are loaded per
CCLK cycle. Express mode does not support CRC error
checking, but does support constant-field error checking. A
length count is not used in Express mode.
Express mode must be specified as an option to the devel-
opment system. The Express mode bitstream is not com-
patible with the other configuration modes (see Table 16,
page 32.) Express mode is selected by a <0X> on the Mode
pins (M1, M0).
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a large
number of devices are included in the chain, deactivate
some of the internal pull-ups, since the Low-driving DONE
pin of the last device in the chain must sink the current from
all pull-ups in the chain. The DONE pull-up is activated by
default. It can be deactivated using a development system
option.
The first byte of parallel configuration data must be available
at the D inputs of the FPGA a short setup time before the
second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge
(Figure 28).
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All Spartan-XL devices in Express mode are synchronized
Pseudo Daisy Chain
Multiple devices with different configurations can be config-
ured in a pseudo daisy chain provided that all of the devices
DS060 (v2.0) March 1, 2013
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to the DONE pin. User I/Os for each device become active
after the DONE pin for that device goes High. (The exact
timing is determined by development system options.)
Since the DONE pin is open-drain and does not drive a High
value, tying the DONE pins of all devices together prevents
all devices in the chain from going High until the last device
in the chain has completed its configuration cycle. If the
DONE pin of a device is left unconnected, the device
becomes active as soon as that device has been config-
ured. Only devices supporting Express mode can be used
to form an Express mode daisy chain.
V
CC
8
To Additional
Optional
M0
M1
M0
M1
Daisy-Chained
Devices
CS1
CS1
DOUT
DOUT
8
8
D0-D7
D0-D7
DATA BUS
Optional
Daisy-Chained
Spartan-XL
VCC
3.3K
Spartan-XL
PROGRAM
INIT
PROGRAM
PROGRAM
INIT
INIT
CCLK
DONE
DONE
CCLK
To Additional
Optional
Daisy-Chained
Devices
CCLK
DS060_27_080400
Figure 27: Express Mode Circuit Diagram
30
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CCLK
INIT
T
IC
T
CD
T
DC
BYTE
0
BYTE
1
BYTE
6
D0-D7
DOUT
Header Received
FPGA Filled
DS060_28_080400
Symbol
Description
Min
5
Max
Units
μs
T
INIT (High) setup time
D0-D7 setup time
D0-D7 hold time
CCLK High time
CCLK Low time
-
-
IC
T
T
20
0
ns
DC
CD
-
ns
CCLK
T
45
45
-
-
ns
CCH
T
-
ns
CCL
F
CCLK Frequency
10
MHz
CC
Notes:
1. If not driven by the preceding DOUT, CS1 must remain High until the
device is fully configured.
Figure 28: Express Mode Programming Switching Characteristics
Express mode data is shown with D0 at the left and D7 at
the right.
Setting CCLK Frequency
In Master mode, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency ranges
from 0.5 MHz to 1.25 MHz for Spartan/XL devices. In fast
CCLK mode, the frequency ranges from 4 MHz to 10 MHz
for Spartan/XL devices. The frequency is changed to fast by
an option when running the bitstream generation software.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Spartan-XL
family Express mode). This header is followed by the actual
configuration data in frames. The length and number of
frames depends on the device type (see Table 17). Each
frame begins with a start field and ends with an error check.
In serial modes, a postamble code is required to signal the
end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of configuration. Long daisy
chains require additional startup bytes to shift the last data
through the chain. All start-up bytes are "don’t cares".
Data Stream Format
The data stream ("bitstream") format is identical for both
serial configuration modes, but different for the Spartan-XL
family Express mode. In Express mode, the device
becomes active when DONE goes High, therefore no length
count is required. Additionally, CRC error checking is not
supported in Express mode. The data stream format is
shown in Table 16. Bit-serial data is read from left to right.
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A selection of CRC or non-CRC error checking is allowed by
the bitstream generation software. The Spartan-XL family
Express mode only supports non-CRC error checking. The
Table 16: Spartan/XL Data Stream Formats
Express Mode
Serial Modes
(D0...)
(D0-D7)
(Spartan-XL only)
non-CRC error checking tests for
a
designated
Data Type
Fill Byte
end-of-frame field for each frame. For CRC error checking,
the software calculates a running CRC and inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an FPGA includes the last
seven data bits.
11111111b
0010b
FFFFh
Preamble Code
Length Count
Fill Bits
11110010b
(1)
COUNT[23:0]
1111b
COUNT[23:0]
Detection of an error results in the suspension of data load-
ing before DONE goes High, and the pulling down of the
INIT pin. In Master serial mode, CCLK continues to operate
externally. The user must detect INIT and initialize a new
configuration by pulsing the PROGRAM pin Low or cycling
-
Field Check
Code
-
11010010b
(2)
Start Field
0b
11111110b
V
.
CC
Data Frame
DATA[n–1:0]
DATA[n–1:0]
11010010b
Cyclic Redundancy Check (CRC) for Configura-
tion and Readback
CRC or Constant xxxx (CRC)
Field Check
or 0110b
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Extend Write
Cycle
-
FFD2FFFFFFh
Postamble
01111111b
FFh
-
(3)
Start-Up Bytes
FFFFFFFFFFFFFFh
Legend:
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 16. If a frame data
error is detected during the loading of the FPGA, the config-
uration process with a potentially corrupted bitstream is ter-
minated. The FPGA pulls the INIT pin Low and goes into a
Wait state.
Unshaded
Light
Once per bitstream
Once per data frame
Once per device
Dark
Notes:
1. Not used by configuration logic.
2. 11111111b for XCS40XL only.
3. Development system may add more start-up bytes.
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Spartan and Spartan-XL FPGA Families Data Sheet
Table 17: Spartan/XL Program Data
Device
XCS05
XCS10
XCS20
XCS30
XCS40
Max System
Gates
5,000
10,000
20,000
30,000
40,000
CLBs
100
196
400
576
784
(Row x Col.)
(10 x 10)
(14 x 14)
(20 x 20)
(24 x 24)
(28 x 28)
(4)
IOBs
80
112
160
192
205
Part Number
Supply Voltage
Bits per Frame
Frames
XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL XCS30 XCS30XL XCS40 XCS40XL
5V
126
3.3V
127
5V
166
3.3V
167
573
5V
226
788
3.3V
227
789
5V
266
932
3.3V
267
933
5V
306
3.3V
307
428
429
572
1,076
1,077
Program Data
53,936
53,984
54,491
54,544
94,960
95,008
95,699 178,096 179,111 247,920 249,119 329,264 330,647
95,752 178,144 179,160 247,968 249,168 329,312 330,696
PROM Size
(bits)
Express Mode
PROM Size
(bits)
-
79,072
-
128,488
-
221,056
-
298,696
-
387,856
Notes:
1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits (+1 for Spartan-XL
device)
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 (+ 1 for Spartan-XL device)
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8, rounded up to the nearest byte
2. The user can add more "1" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame,
following the four error check bits. However, the Length Count value must be adjusted for all such extra "one" bits, even for extra
leading ones at the beginning of the header.
3. Express mode adds 57 (XCS05XL, XCS10XL), or 53 (XCS20XL, XCS30XL, XCS40XL) bits per frame, + additional start-up bits.
4. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 29. The checksum consists of the 11 most signifi-
cant bits of the 16-bit code. A change in the checksum indi-
cates a change in the Readback bitstream. A comparison to
a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB outputs
should not be included (Readback Capture option not
used), and if RAM is present, the RAM content must be
unchanged.
Statistically, one error out of 2048 might go undetected.
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X2
X15
X16
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
15
SERIAL DATA IN
Polynomial: X16 + X15 + X2 + 1
1
1
1
1
1
0 15 14 13 12 11 10 9
8
7
6
5
LAST DATA FRAME
CRC – CHECKSUM
Readback Data Stream
Figure 29: Circuit for Generating CRC-16
DS060_29_080400
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscil-
lator.
Configuration Sequence
There are four major steps in the Spartan/XL FPGA
power-up configuration sequence.
•
•
•
•
Configuration Memory Clear
Initialization
Configuration
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configuration
frames and then tests the INIT input.
Start-up
The full process is illustrated in Figure 30.
Configuration Memory Clear
Initialization
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
When V
reaches an operational level, and the circuit
CC
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms. The delay is four times as long when in Master
Serial Mode to allow ample time for all slaves to reach a sta-
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber-
ate delay before a Master-mode device recognizes an
inactive INIT. Two internal clocks after the INIT pin is recog-
nized as High, the device samples the MODE pin to deter-
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
ble V . When all INIT pins are tied together, as recom-
CC
mended, the longest delay takes precedence. Therefore,
devices with different time delays can easily be mixed and
matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
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Configuration
The 0010 preamble code indicates that the following 24 bits
represent the length count for serial modes. The length
count is the total number of configuration clocks needed to
load the complete configuration data. (Four additional con-
figuration clocks are required to complete the configuration
process, as discussed below.) After the preamble and the
length count have been passed through to any device in the
daisy chain, its DOUT is held High to prevent frame start
bits from reaching any daisy-chained devices. In Spar-
tan-XL family Express mode, the length count bits are
ignored, and DOUT is held Low, to disable the next device in
the pseudo daisy chain.
V
No
CC
Valid
Boundary Scan
Instructions
Available:
Yes
Test MODE, Generate
One Time-Out Pulse
of 16 or 64 ms
PROGRAM
= Low
Yes
Keep Clearing
Configuration
Memory
EXTEST*
SAMPLE/PRELOAD
BYPASS
CONFIGURE*
(* if PROGRAM = High)
Completely Clear
Configuration Memory
Once More
~1.3 μs per Frame
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configura-
tion clock is selected by the bitstream, the slower clock rate
is used until this configuration bit is detected.
INIT
No
High? if
Master
Master Delays Before
Sampling Mode Line
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error by
pulling the open-drain INIT pin Low. After all configuration
frames have been loaded into an FPGA using a serial
mode, DOUT again follows the input data so that the
remaining data is passed on to the next device. In
Spartan-XL family Express mode, when the first device is
fully programmed, DOUT goes High to enable the next
device in the chain.
Yes
Sample
Mode Line
Master CCLK
Goes Active
Load One
Configuration
Data Frame
Yes
Frame
Error
Pull INIT Low
and Stop
Delaying Configuration After Power-Up
No
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 30.)
SAMPLE/PRELOAD
Config-
uration
memory
Full
No
BYPASS
Yes
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the FPGA keeps clearing its configuration memory.
When PROGRAM goes High, the configuration memory is
cleared one more time, followed by the beginning of config-
uration, provided the INIT input is not externally held Low.
Note that a Low on the PROGRAM input automatically
forces a Low on the INIT output. The Spartan/XL FPGA
PROGRAM pin has a permanent weak pull-up.
Pass
Configuration
Data to DOUT
CCLK
Count Equals
Length
No
Count
Yes
Start-Up
Sequence
F
Avoid holding PROGRAM Low for more than 500 μs. The
500 μs maximum limit is only a recommendation, not a
requirement. The only effect of holding PROGRAM Low for
more than 500 μs is an increase in current, measured at
about 40 mA in the XCS40XL. This increased current can-
not damage the device. This applies only during reconfigu-
ration, not during power-up. The INIT pin can also be held
Low to delay reconfiguration, and the same characteristics
apply as for the PROGRAM pin.
Operational
EXTEST
SAMPLE PRELOAD
BYPASS
If Boundary Scan
is Selected
USER 1
USER 2
CONFIGURE
READBACK
DS060_30_080400
Figure 30: Power-up Configuration Sequence
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the FPGA
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to wait after completing the configuration memory clear
operation. When INIT is no longer held Low externally, the
device determines its configuration mode by capturing the
state of the Mode pins, and is ready to start the configura-
tion process. A master device waits up to an additional
300 μs to make sure that any slaves in the optional daisy
chain have seen that INIT is High.
Figure 31 describes start-up timing in detail. The three
events — DONE going High, the internal GSR being
de-activated, and the user I/O going active — can all occur
in any arbitrary sequence. This relative timing is selected by
options in the bitstream generation software. Heavy lines in
Figure 31 show the default timing. The thin lines indicate all
other possible timing options. The start-up logic must be
clocked until the "F" (Finished) state is reached.
For more details on Configuration, refer to the Xilinx Appli-
cation Note "FPGA Configuration Guidelines" (XAPP090).
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the I/Os become active
one clock later. GSR is then released another clock period
later to make sure that user operation starts from stable
internal conditions. This is the most common sequence,
shown with heavy lines in Figure 31, but the designer can
modify it to meet particular requirements.
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user system. Start-up must make sure that the
user logic ‘wakes up’ gracefully, that the outputs become
active without causing contention with the configuration sig-
nals, and that the internal flip-flops are released from the
Global Set/Reset (GSR) at the right time.
Start-Up Clock
Normally, the start-up sequence is controlled by the internal
device oscillator (CCLK), which is asynchronous to the sys-
tem clock. As a configuration option, they can be triggered
by an on-chip user net called UCLK. This user net can be
accessed by placing the STARTUP library symbol, and the
start-up modes are known as UCLK_NOSYNC or
UCLK_SYNC. This allows the device to wake up in synchro-
nism with the user system.
Start-Up Initiation
Two conditions have to be met in order for the start-up
sequence to begin:
•
•
The chip's internal memory must be full, and
The configuration length count must be met, exactly.
DONE Pin
In all configuration modes except Express mode, Spar-
tan/XL devices read the expected length count from the bit-
stream and store it in an internal register. The length count
varies according to the number of devices and the composi-
tion of the daisy chain. Each device also counts the number
of CCLKs during configuration.
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then be
used as input to the start-up control logic. This is called
“Start-up Timing Synchronous to Done In” and is selected
by either CCLK_SYNC or UCLK_SYNC. When DONE is not
used as an input, the operation is called “Start-up Timing
Not Synchronous to DONE In,” and is selected by either
CCLK_NOSYNC or UCLK_NOSYNC. Express mode con-
figuration always uses either CCLK_SYNC or UCLK_SYNC
timing, while the other configuration modes can use any of
the four timing sequences.
In Express mode, there is no length count. The start-up
sequence for each device begins when the device has
received its quota of configuration data. Wiring the DONE
pins of several devices together delays start-up of all
devices until all are fully configured.
Start-Up Events
The device can be programmed to control three start-up
events.
•
•
The release of the open-drain DONE output
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com-
mon user clock, or to guarantee that all devices are suc-
cessfully configured before any I/Os go active.
The termination of the Global Three-State and the
change of configuration-related pins to the user
function, activating all IOBs.
•
The termination of the Global Set/Reset initialization of
all CLB and IOB storage elements.
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Length Count Match
CCLK Period
CCLK
F
DONE
C1
C2
C2
C3
C3
C4
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
I/O
CCLK_NOSYNC
C4
GSR Active
Heavy lines describe
default timing
C2
C3
C4
DONE IN
F
DONE
I/O
C1, C2 or C3
CCLK_SYNC
Di
Di+1
Di+1
GSR Active
Di
F
DONE
I/O
C1
U2
U2
U3
U3
U4
UCLK_NOSYNC
U4
GSR Active
U2
U3
U4
DONE IN
F
DONE
I/O
C1
U2
UCLK_SYNC
Di
Di+1
Di+2
Di+2
GSR Active
Di Di+1
UCLK Period
Synchronization
Uncertainty
DS060_39_082801
Figure 31: Start-up Timing
•
•
Wait for INIT to go High.
Configuration Through the Boundary Scan
Pins
Spartan/XL devices can be configured through the bound-
ary scan pins. The basic procedure is as follows:
Sequence the boundary scan Test Access Port to the
SHIFT-DR state.
Toggle TCK to clock data into TDI pin.
•
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
•
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
For more detailed information, refer to the Xilinx application
note, "Boundary Scan in FPGA Devices." This application
note applies to Spartan and Spartan-XL devices.
•
Issue the CONFIG command to the TMS input.
DS060 (v2.0) March 1, 2013
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37
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Spartan and Spartan-XL FPGA Families Data Sheet
of the first frame. The first two data bits of the first frame are
always High.
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfering
with the normal operation of the device.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Readback Options
Readback options are: Readback Capture, Readback
Abort, and Clock Select. They are set with the bitstream
generation software.
Although readback can be performed while the device is
operating, for best results and to freeze a known capture
state, it is recommended that the clock inputs be stopped
until readback is complete.
Readback Capture
When the Readback Capture option is selected, the data
stream includes sampled values of CLB and IOB signals.
The rising edge of RDBK.TRIG latches the inverted values
of the four CLB outputs, the IOB output flip-flops and the
input signals I1 and I2. Note that while the bits describing
configuration (interconnect, function generators, and RAM
content) are not inverted, the CLB and IOB output signals
are inverted. RDBK.TRIG is located in the lower-left corner
of the device.
Readback of Spartan-XL family Express mode bitstreams
results in data that does not resemble the original bitstream,
because the bitstream format differs from other modes.
Spartan/XL FPGA Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, instantiate the
READBACK library symbol and attach the appropriate pad
symbols, as shown in Figure 32.
When the Readback Capture option is not selected, the val-
ues of the capture bits reflect the configuration data origi-
nally written to those memory locations. If the RAM
capability of the CLBs is used, RAM data are available in
Readback, since they directly overwrite the F and G func-
tion-table configuration of the CLB.
After Readback has been initiated by a Low-to-High transi-
tion on RDBK.TRIG, the RDBK.RIP (Read In Progress) out-
put goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit (Low)
If Unconnected,
Default is CCLK
DATA
RIP
READ_DATA
CLK
READBACK
OBUF
READ_TRIGGER
TRIG
IBUF
DS060_31_080400
Figure 32: Readback Example
38
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Spartan and Spartan-XL FPGA Families Data Sheet
Readback Abort
met. For example, if a processor is controlling Readback, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
When the Readback Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the Readback opera-
tion and prepares the logic to accept another trigger.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the following
frame. This loading process is dynamic, and is the source of
the maximum High and Low time requirements.
After an aborted Readback, additional clocks (up to one
Readback clock per configuration frame) may be required to
re-initialize the control logic. The status of Readback is indi-
cated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the Readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If Readback
must be inhibited for security reasons, the Readback control
nets are simply not connected. RDBK.CLK is located in the
lower right chip corner.
The user must precisely calculate the location of the Read-
back data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
are listed in Table 16 and Table 17.
Violating the Maximum High and Low Time
Specification for the Readback Clock
The Readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
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Spartan and Spartan-XL FPGA Families Data Sheet
Readback Switching Characteristics Guidelines
The following guidelines reflect worst-case values over the
recommended operating conditions.
Finished
Internal Net
rdbk.TRIG
T
RCRT
T
RCRT
T
RTRC
T
RTRC
rdclk.I
T
RCL
T
RCH
rdbk.RIP
T
RCRR
DUMMY
DUMMY
VALID
VALID
rdbk.DATA
T
RCRD
DS060_32_080400
Figure 33: Spartan and Spartan-XL Readback Timing Diagram
Spartan and Spartan-XL Readback Switching Characteristics
Symbol
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
Min
200
50
-
Max
-
Units
ns
T
T
rdbk.TRIG
rdclk.I
RTRC
RCRT
RCRD
RCRR
-
ns
T
T
250
250
500
500
ns
rdbk.RIP delay
-
ns
T
High time
250
250
ns
RCH
T
Low time
ns
RCL
Notes:
1. Timing parameters apply to all speed grades.
2. If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
40
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Spartan and Spartan-XL FPGA Families Data Sheet
Configuration Switching Characteristics
V
CC
RE-PROGRAM
>300 ns
T
POR
PROGRAM
INIT
T
PI
T
ICCK
T
CCLK
CCLK Output or Input
<300 ns
<300 ns
Mode Pins
(Required)
DONE Response
I/O
DS060_33_080400
Master Mode
Symbol
Description
Min
40
Max
130
200
250
2000
250
Units
T
Power-on reset
ms
POR
T
Program Latency
30
μs per CLB column
PI
T
CCLK (output) delay
40
μs
ns
ns
ICCK
CCLK
CCLK
T
T
CCLK (output) period, slow
CCLK (output) period, fast
640
100
Slave Mode
Symbol
Description
Power-on reset
Min
10
30
4
Max
33
200
-
Units
T
ms
POR
T
Program latency
μs per CLB column
PI
T
CCLK (input) delay (required)
CCLK (input) period (required)
μs
ICCK
T
80
-
ns
CCLK
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family Detailed Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values
are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications.
(1)
Spartan Family Absolute Maximum Ratings
Symbol
Description
Value
Units
V
V
Supply voltage relative to GND
–0.5 to +7.0
CC
(2,3)
V
Input voltage relative to GND
–0.5 to V +0.5
V
IN
CC
(2,3)
V
Voltage applied to 3-state output
Storage temperature (ambient)
Junction temperature
–0.5 to V +0.5
V
TS
CC
T
–65 to +150
+125
°C
°C
STG
T
Plastic packages
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC overshoot (above VCC) or undershoot (below GND) must be limited to either 0.5V or 10 mA, whichever is easier to
achieve.
3. Maximum AC (during transitions) conditions are as follows; the device pins may undershoot to –2.0V or overshoot to +7.0V, provided
this overshoot or undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
4. For soldering guidelines, see the Package Information on the Xilinx website.
Spartan Family Recommended Operating Conditions
Symbol
Description
Min
4.75
4.5
2.0
70%
0
Max
5.25
5.5
Units
V
Supply voltage relative to GND, T = 0°C to +85°C
Commercial
Industrial
V
V
V
CC
J
(1)
Supply voltage relative to GND, T = –40°C to +100°C
J
(2)
V
High-level input voltage
TTL inputs
CMOS inputs
TTL inputs
CMOS inputs
V
CC
IH
100%
0.8
V
CC
(2)
V
Low-level input voltage
V
IL
0
20%
250
V
CC
T
Input signal transition time
-
ns
IN
Notes:
1. At junction temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Input and output measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.
42
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family DC Characteristics Over Operating Conditions
Symbol
Description
High-level output voltage @ I = –4.0 mA, V min
Min
Max
-
Units
V
V
TTL outputs
2.4
OH
OH
CC
High-level output voltage @ I = –1.0 mA, V min
CMOS outputs
TTL outputs
V – 0.5
CC
-
V
OH
CC
(1)
V
Low-level output voltage @ I = 12.0 mA, V min
-
0.4
0.4
-
V
OL
OL
CC
CMOS outputs
-
3.0
-
V
V
Data retention supply voltage (below which configuration data may be lost)
V
DR
(2)
I
Quiescent FPGA supply current
Commercial
Industrial
3.0
6.0
+10
10
0.25
-
mA
mA
μA
pF
mA
mA
CCO
-
I
Input or output leakage current
–10
-
L
C
Input capacitance (sample tested)
IN
I
I
Pad pull-up (when selected) @ V = 0V (sample tested)
0.02
0.02
RPU
RPD
IN
Pad pull-down (when selected) @ V = 5V (sample tested)
IN
Notes:
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2. With no output current loads, no active input pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a Tie
option.
Spartan Family Global Buffer Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values where one
global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB
flip-flops are clocked by the global clock net.
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
Speed Grade
-4
Max
2.0
2.4
2.8
3.2
3.5
2.5
2.9
3.3
3.6
3.9
-3
Max
4.0
4.3
5.4
5.8
6.4
4.4
4.7
5.8
6.2
6.7
Symbol
Description
Device
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
Units
ns
T
From pad through Primary buffer, to any clock K
PG
ns
ns
ns
ns
T
From pad through Secondary buffer, to any clock K
ns
SG
ns
ns
ns
ns
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family CLB Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
expressed in nanoseconds unless otherwise noted.
Speed Grade
-4
-3
Description
Symbol
Min
Max
Min
Max
Units
Clocks
T
Clock High time
Clock Low time
3.0
3.0
-
-
4.0
4.0
-
-
ns
ns
CH
T
CL
Combinatorial Delays
T
F/G inputs to X/Y outputs
-
-
-
1.2
2.0
1.7
-
-
-
1.6
2.7
2.2
ns
ns
ns
ILO
T
F/G inputs via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
IHO
T
HH1O
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
T
-
-
-
-
-
1.7
2.8
1.2
2.0
0.5
-
-
-
-
-
2.1
3.7
1.4
2.6
0.6
ns
ns
ns
ns
ns
OPCY
OUT
T
Add/Subtract input (F3) to C
OUT
ASCY
T
Initialization inputs (F1, F3) to C
OUT
INCY
T
C
C
through function generators to X/Y outputs
SUM
IN
T
to C
, bypass function generators
OUT
BYP
IN
Sequential Delays
Clock K to Flip-Flop outputs Q
Setup Time before Clock K
T
-
2.1
-
2.8
ns
CKO
T
F/G inputs
1.8
2.9
2.3
1.3
2.0
2.5
-
-
-
-
-
-
2.4
3.9
3.3
2.0
2.6
4.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ICK
T
F/G inputs via H
IHCK
T
C inputs via H1 through H
C inputs via DIN
HH1CK
T
DICK
T
C inputs via EC
ECCK
T
C inputs via S/R, going Low (inactive)
RCK
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
0.0
-
0.0
-
ns
T
Width (High)
3.0
-
-
4.0
-
-
ns
ns
RPW
T
Delay from C inputs via S/R, going High to Q
3.0
4.0
RIO
Global Set/Reset
T
Minimum GSR pulse width
11.5
-
13.5
-
ns
MRW
T
Delay from GSR input to any Q
See page 50 for T
values per device.
RRI
MRQ
F
Toggle Frequency (MHz)
-
166
-
125
MHz
TOG
(for export control purposes)
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
are expressed in nanoseconds unless otherwise noted.
Speed Grade
-4
-3
(1)
Symbol
Single Port RAM
Size
Min
Max
Min
Max
Units
Write Operation
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
8.0
8.0
4.0
4.0
1.5
1.5
0.0
0.0
1.5
1.5
0.0
0.0
1.5
1.5
0.0
0.0
-
-
11.6
11.6
5.8
5.8
2.0
2.0
0.0
0.0
2.7
1.7
0.0
0.0
1.6
1.6
0.0
0.0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCS
T
-
-
WCTS
T
-
-
WPS
T
-
-
WPTS
T
-
-
ASS
T
-
-
ASTS
T
-
-
AHS
T
-
-
AHTS
T
-
-
DSS
T
-
-
DSTS
T
-
-
DHS
T
-
-
DHTS
T
WE setup time before clock K
WE hold time after clock K
-
-
-
-
WSS
T
T
T
WSTS
T
-
-
WHS
-
-
WHTS
T
Data valid after clock K
6.5
7.0
7.9
9.3
WOS
-
-
WOTS
Read Operation
T
Address read cycle time
16x2
32x1
16x2
32x1
16x2
32x1
2.6
3.8
-
-
-
2.6
3.8
-
-
-
ns
ns
ns
ns
ns
ns
RC
T
RCT
T
Data valid after address change (no Write
Enable)
1.2
2.0
-
1.6
2.7
-
ILO
T
-
-
IHO
T
Address setup time before clock K
1.8
2.9
2.4
3.9
ICK
T
-
-
IHCK
Notes:
1. Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
(continued)
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
are expressed in nanoseconds unless otherwise noted.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-4
-3
(1)
Symbol
Dual Port RAM
Size
Min Max Min Max Units
Write Operation
T
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
8.0
4.0
1.5
0
-
11.6
5.8
2.1
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCDS
WPDS
-
-
T
-
-
ASDS
T
-
-
AHDS
T
T
1.5
0
-
1.6
0
-
DSDS
DHDS
WSDS
WHDS
WODS
-
-
-
-
T
T
WE setup time before clock K
WE hold time after clock K
1.5
0
1.6
0
-
-
T
Data valid after clock K
-
6.5
-
7.0
Notes:
1. Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Timing
Single Port
Dual Port
TWPS
TWPDS
WCLK (K)
WCLK (K)
TWSS
TWHS
TWSDS
TWHDS
WE
WE
TDHS
TDHDS
TDSS
TDSDS
DATA IN
DATA IN
TAHS
TASS
TAHDS
TASDS
ADDRESS
DATA OUT
ADDRESS
DATA OUT
TILO
TILO
TILO
TILO
TWODS
OLD
TWOS
OLD
NEW
NEW
DS060_34_011300
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading. For more specific, more pre-
cise, and worst-case guaranteed data, reflecting the actual
routing structure, use the values provided by the static tim-
ing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report.
Spartan Family Output Flip-Flop, Clock-to-Out
Speed Grade
-4
-3
Symbol
Description
Device
Max
Max
Units
Global Primary Clock to TTL Output using OFF
T
Fast
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
5.3
5.7
8.7
9.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ICKOF
6.1
9.3
6.5
9.4
6.8
10.2
11.5
12.0
12.2
12.8
12.8
T
Slew-rate limited
9.0
9.4
ICKO
9.8
10.2
10.5
Global Secondary Clock to TTL Output using OFF
T
Fast
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
5.8
6.2
9.2
9.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ICKSOF
6.6
9.8
7.0
9.9
7.3
10.7
12.0
12.5
12.7
13.2
14.3
T
Slew-rate limited
9.5
ICKSO
9.9
10.3
10.7
11.0
Delay Adder for CMOS Outputs Option
T
Fast
All devices
All devices
0.8
1.5
1.0
2.0
ns
ns
CMOSOF
T
Slew-rate limited
CMOSO
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 34.
3. OFF = Output Flip-Flop
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Spartan and Spartan-XL FPGA Families Data Sheet
Capacitive Load Factor
3
2
Figure 34 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2.5 ns to the specified delay. If the load capacitance is 20
pF, subtract 0.8 ns from the specified output delay.
Figure 34 is usable over the specified operating conditions
of voltage and temperature and is independent of the output
slew rate control.
1
0
-1
-2
0
20
40
60
80
100
120
140
Capacitance (pF)
DS060_35_080400
Figure 34: Delay Factor at Various Capacitive Loads
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading.
Spartan Family Primary and Secondary Setup and Hold
Speed Grade
-4
-3
Symbol
Description
Device
Min
Min
Units
Input Setup/Hold Times Using Primary Clock and IFF
T
/T
No Delay
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
1.2 / 1.7
1.0 / 2.3
0.8 / 2.7
0.6 / 3.0
0.4 / 3.5
4.3 / 0.0
4.3 / 0.0
4.3 / 0.0
4.3 / 0.0
5.3 / 0.0
1.8 / 2.5
1.5 / 3.4
1.2 / 4.0
0.9 / 4.5
0.6 / 5.2
6.0 / 0.0
6.0 / 0.0
6.0 / 0.0
6.0 / 0.0
6.8 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PSUF PHF
T
/T
With Delay
PSU PH
Input Setup/Hold Times Using Secondary Clock and IFF
T
/T
No Delay
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
0.9 / 2.2
0.7 / 2.8
0.5 / 3.2
0.3 / 3.5
0.1 / 4.0
4.0 / 0.0
4.0 / 0.0
4.0 / 0.5
4.0 / 0.5
5.0 / 0.0
1.5 / 3.0
1.2 / 3.9
0.9 / 4.5
0.6 / 5.0
0.3 / 5.7
5.7 / 0.0
5.7 / 0.0
5.7 / 0.5
5.7 / 0.5
6.5 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SSUF SHF
T
/T
With Delay
SSU SH
Notes:
1. Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
2. IFF = Input Flip-flop or Latch
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Speed Grade
-4
-3
Symbol
Description
Device
Min
Max
Min
Max Units
Setup Times - TTL Inputs(1)
T
T
Clock Enable (EC) to Clock (IK), no delay
Pad to Clock (IK), no delay
All devices
All devices
1.6
1.5
-
-
2.1
2.0
-
-
ns
ns
ECIK
PICK
Hold Times
T
Clock Enable (EC) to Clock (IK), no delay
All Other Hold Times
All devices
All devices
0.0
0.0
-
-
0.9
0.0
-
-
ns
ns
IKEC
Propagation Delays - TTL Inputs(1)
T
Pad to I1, I2
All devices
All devices
All devices
All devices
-
-
-
-
1.5
2.8
2.7
3.2
-
-
-
-
2.0
3.6
2.8
3.9
ns
ns
ns
ns
PID
T
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
PLI
T
IKRI
T
Clock (IK) to I1, I2 (latch enable, active Low)
IKLI
Delay Adder for Input with Delay Option
T
T
T
T
= T
= T
+ T
+ T
XCS05
XCS10
XCS20
XCS30
XCS40
3.6
3.7
3.8
4.5
5.5
-
-
-
-
-
4.0
4.1
4.2
5.0
5.5
-
-
-
-
-
ns
ns
ns
ns
ns
Delay
ECIKD
PICKD
ECIK
PICK
Delay
Delay
= T + T
Delay
PDLI
PLI
Global Set/Reset
T
Minimum GSR pulse width
All devices 11.5
-
13.5
-
ns
ns
ns
ns
ns
ns
MRW
T
Delay from GSR input to any Q
XCS05
XCS10
XCS20
XCS30
XCS40
-
-
-
-
-
9.0
-
-
-
-
-
11.3
11.9
12.5
13.1
13.8
RRI
9.5
10.0
10.5
11.0
Notes:
1. Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns.
2. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
3. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family IOB Output Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Values are expressed in nanoseconds unless otherwise
noted.
Speed Grade
-4
-3
Symbol
Clocks
Description
Device
Min
Max
Min
Max
Units
T
Clock High
Clock Low
All devices
All devices
3.0
3.0
-
-
4.0
4.0
-
-
ns
ns
CH
T
CL
Propagation Delays - TTL Outputs(1,2)
T
Clock (OK) to Pad, fast
All devices
All devices
All devices
All devices
All devices
All devices
All devices
-
-
-
-
-
-
-
3.3
6.9
3.6
7.2
3.0
6.0
9.6
-
-
-
-
-
-
-
4.5
7.0
4.8
7.3
3.8
7.3
9.8
ns
ns
ns
ns
ns
ns
ns
OKPOF
T
Clock (OK to Pad, slew-rate limited
Output (O) to Pad, fast
OKPOS
T
OPF
T
Output (O) to Pad, slew-rate limited
3-state to Pad High-Z (slew-rate independent)
3-state to Pad active and valid, fast
3-state to Pad active and valid, slew-rate limited
OPS
T
TSHZ
T
T
TSONF
TSONS
Setup and Hold Times
T
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
All devices
All devices
All devices
All devices
2.5
0.0
2.0
0.0
-
-
-
-
3.8
0.0
2.7
0.5
-
-
-
-
ns
ns
ns
ns
OOK
T
OKO
T
T
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
ECOK
OKEC
Global Set/Reset
T
Minimum GSR pulse width
All devices
XCS05
XCS10
XCS20
XCS30
XCS40
11.5
13.5
ns
ns
ns
ns
ns
ns
MRW
T
Delay from GSR input to any Pad
-
-
-
-
-
12.0
12.5
13.0
13.5
14.0
-
-
-
-
-
15.0
15.7
16.2
16.9
17.5
RPO
Notes:
1. Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns.
2. Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns.
3. Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times.
4. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family Detailed Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families.
Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications.
(1)
Spartan-XL Family Absolute Maximum Ratings
Symbol
Description
Value
Units
V
V
Supply voltage relative to GND
Input voltage relative to GND
–0.5 to 4.0
–0.5 to 5.5
CC
(2, 3)
(2, 3)
V
5V Tolerant I/O Checked
V
IN
(4, 5)
Not 5V Tolerant I/Os
–0.5 to V + 0.5
V
CC
V
Voltage applied to 3-state output
5V Tolerant I/O Checked
–0.5 to 5.5
V
TS
(4, 5)
Not 5V Tolerant I/Os
–0.5 to V + 0.5
V
CC
T
Storage temperature (ambient)
Junction temperature
–65 to +150
+125
°C
°C
STG
T
Plastic packages
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. With 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either +5.5V or 10 mA and undershoot (below GND)
must be limited to either 0.5V or 10 mA, whichever is easier to achieve.
3. With 5V Tolerant I/Os selected, the Maximum AC (during transitions) conditions are as follows; the device pins may undershoot to
–2.0V or overshoot to + 7.0V, provided this overshoot or undershoot lasts no more than 11 ns with a forcing current no greater than
100 mA.
4. Without 5V Tolerant I/Os selected, the Maximum DC overshoot or undershoot must be limited to either 0.5V or 10 mA, whichever is
easier to achieve.
5. Without 5V Tolerant I/Os selected, the Maximum AC conditions are as follows; the device pins may undershoot to –2.0V or overshoot
to VCC + 2.0V, provided this overshoot or undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
6. For soldering guidelines, see the Package Information on the Xilinx website.
Spartan-XL Family Recommended Operating Conditions
Symbol
Description
Min
Max
3.6
Units
V
V
Supply voltage relative to GND, T = 0°C to +85°C
Commercial
Industrial
3.0
CC
J
(1)
Supply voltage relative to GND, T = –40°C to +100°C
3.0
3.6
V
J
(2)
V
High-level input voltage
50% of V
5.5
V
IH
CC
(2)
V
Low-level input voltage
0
-
30% of V
250
V
IL
CC
T
Input signal transition time
ns
IN
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Input and output measurement threshold is ~50% of VCC
.
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family DC Characteristics Over Operating Conditions
Symbol
Description
High-level output voltage @ I = –4.0 mA, V min (LVTTL)
Min
Typ.
Max
Units
V
2.4
-
-
-
-
-
-
-
-
V
V
V
V
V
V
OH
OH
CC
High-level output voltage @ I = –500 μA, (LVCMOS)
90% V
OH
CC
(1)
(2)
V
Low-level output voltage @ I = 12.0 mA, V min (LVTTL)
-
-
0.4
OL
OL
CC
Low-level output voltage @ I = 24.0 mA, V min (LVTTL)
0.4
OL
CC
Low-level output voltage @ I = 1500 μA, (LVCMOS)
-
10% V
OL
CC
V
Data retention supply voltage (below which configuration data
may be lost)
2.5
-
DR
(3,4)
I
Quiescent FPGA supply current
Commercial
Industrial
-
0.1
0.1
0.1
0.1
-
2.5
5
mA
mA
mA
mA
μA
CCO
-
(3,5)
I
Power Down FPGA supply current
Commercial
Industrial
-
2.5
5
CCPD
-
–10
-
I
Input or output leakage current
10
10
0.25
-
L
C
Input capacitance (sample tested)
-
pF
IN
I
Pad pull-up (when selected) @ V = 0V (sample tested)
0.02
0.02
-
mA
mA
RPU
RPD
IN
I
Pad pull-down (when selected) @ V = 3.3V (sample tested)
-
IN
Notes:
1. With up to 64 pins simultaneously sinking 12 mA (default mode).
2. With up to 64 pins simultaneously sinking 24 mA (with 24 mA option selected).
3. With 5V tolerance not selected, no internal oscillators, and the FPGA configured with the Tie option.
4. With no output current loads, no active input resistors, and all package pins at VCC or GND.
5. With PWRDWN active.
Supply Current Requirements During Power-On
Spartan-XL FPGAs require that a minimum supply current
be provided to the V lines for a successful power
on. If more current is available, the FPGA can consume
A maximum limit for I
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of I by limiting the supply current
is not specified. Be careful when
CCPO
I
CCPO
CC
CCPO
more than I
reliability.
min., though this cannot adversely affect
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
CCPO
Symbol
Description
Min
100
-
Max
-
Units
mA
I
Total V supply current required during power-on
CCPO
CC
(2,3)
T
V
ramp time
CC
50
ms
CCPO
Notes:
1. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCC ramps from 0 to 3.3V.
2. The ramp time is measured from GND to VCC max on a fully loaded board.
3. VCC must not dip in the negative direction during power on.
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family Global Buffer Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values where one
global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB
flip-flops are clocked by the global clock net.
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
Speed Grade
-5
Max
1.4
1.7
2.0
2.3
2.6
-4
Max
1.5
1.8
2.1
2.5
2.8
Symbol
Description
Device
Units
ns
T
From pad through buffer, to any clock K
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
GLS
ns
ns
ns
ns
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family CLB Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and expressed in nanoseconds unless otherwise noted.
Speed Grade
-5
-4
Symbol
Clocks
Description
Min
Max
Min
Max
Units
T
Clock High time
Clock Low time
2.0
2.0
-
-
2.3
2.3
-
-
ns
ns
CH
T
CL
Combinatorial Delays
T
F/G inputs to X/Y outputs
-
-
-
-
1.0
1.7
1.5
1.5
-
-
-
-
1.1
2.0
1.8
1.8
ns
ns
ns
ns
ILO
T
F/G inputs via H to X/Y outputs
IHO
T
F/G inputs via transparent latch to Q outputs
C inputs via H1 via H to X/Y outputs
ITO
T
HH1O
Sequential Delays
Clock K to Flip-Flop or latch outputs Q
Setup Time before Clock K
T
-
1.2
-
1.4
ns
CKO
T
F/G inputs
0.6
1.3
-
-
0.7
1.6
-
-
ns
ns
ICK
T
F/G inputs via H
IHCK
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
0.0
-
0.0
-
ns
T
Width (High)
2.5
-
-
2.8
-
-
ns
ns
RPW
T
Delay from C inputs via S/R, going High to Q
2.3
2.7
RIO
Global Set/Reset
T
Minimum GSR Pulse Width
10.5
-
11.5
-
ns
MRW
T
Delay from GSR input to any Q
See page 60 for T
values per device.
MRQ
RRI
F
Toggle Frequency (MHz)
-
250
-
217
MHz
TOG
(for export control purposes)
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and are expressed in nanoseconds unless otherwise noted.
Speed Grade
-5
-4
(1)
Symbol
Single Port RAM
Size
Min
Max
Min
Max
Units
Write Operation
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
7.7
7.7
3.1
3.1
1.3
1.5
1.5
1.8
1.4
1.3
0.0
-
-
8.4
8.4
3.6
3.6
1.5
1.7
1.7
2.1
1.6
1.5
0.0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCS
T
-
-
WCTS
T
-
-
WPS
T
-
-
WPTS
T
-
-
ASS
T
-
-
ASTS
T
-
-
DSS
T
-
-
-
-
DSTS
T
WE setup time before clock K
WSS
T
-
-
WSTS
All hold times after clock K
Data valid after clock K
-
-
T
4.5
5.4
5.3
6.3
WOS
T
-
-
WOTS
Read Operation
T
Address read cycle time
16x2
32x1
16x2
32x1
16x2
32x1
2.6
3.8
-
-
-
3.1
5.5
-
-
-
ns
ns
ns
ns
ns
ns
RC
T
RCT
T
Data Valid after address change (no Write
Enable)
1.0
1.7
-
1.1
2.0
-
ILO
T
-
-
IHO
T
Address setup time before clock K
0.6
1.3
0.7
1.6
ICK
T
-
-
IHCK
Notes:
1. Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
56
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and are expressed in nanoseconds unless otherwise noted.
-5
-4
Symbol
Dual Port RAM
Size
Min Max Min Max Units
Write Operation(1)
T
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
WE setup time before clock K
All hold times after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
7.7
3.1
1.3
1.7
1.4
0
-
8.4
3.6
1.5
2.0
1.6
0
-
ns
ns
ns
ns
ns
ns
ns
WCDS
WPDS
-
-
T
-
-
ASDS
DSDS
WSDS
T
-
-
-
-
T
-
-
T
Data valid after clock K
-
5.2
-
6.1
WODS
Notes:
1. Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Timing
Single Port
Dual Port
TWPS
TWPDS
WCLK (K)
WCLK (K)
TWSS
TWHS
TWSDS
TWHDS
WE
WE
TDHS
TDHDS
TDSS
TDSDS
DATA IN
DATA IN
TAHS
TASS
TAHDS
TASDS
ADDRESS
DATA OUT
ADDRESS
DATA OUT
TILO
TILO
TILO
TILO
TWODS
OLD
TWOS
OLD
NEW
NEW
DS060_34_011300
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading.
Spartan-XL Family Output Flip-Flop, Clock-to-Out
Speed Grade
-5
-4
Symbol
Description
Device
Max
Max
Units
Global Clock to Output using OFF
T
Fast
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
4.6
4.9
5.2
5.5
5.8
5.2
5.5
5.8
6.2
6.5
ns
ns
ns
ns
ns
ICKOF
Slew Rate Adjustment
For Output SLOW option add
T
All Devices
1.5
1.7
ns
SLOW
Notes:
1. Output delays are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load.
3. OFF = Output Flip Flop
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading.
Spartan-XL Family Setup and Hold
Speed Grade
-5
-4
Symbol
Description
Device
Max
Max
Units
Input Setup/Hold Times Using Global Clock and IFF
T
/T
No Delay
Full Delay
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
1.1/2.0
1.0/2.2
0.9/2.4
0.8/2.6
0.7/2.8
3.9/0.0
4.1/0.0
4.3/0.0
4.5/0.0
4.7/0.0
1.6/2.6
1.5/2.8
1.4/3.0
1.3/3.2
1.2/3.4
5.1/0.0
5.3/0.0
5.5/0.0
5.7/0.0
5.9/0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUF HF
T
/T
H
SU
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
Capacitive Load Factor
Figure 35 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified
3
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2
2.5 ns to the specified delay. If the load capacitance is 20
pF, subtract 0.8 ns from the specified output delay.
Figure 35 is usable over the specified operating conditions
1
of voltage and temperature and is independent of the output
slew rate control.
0
-1
-2
0
20
40
60
80
100
120
140
Capacitance (pF)
DS060_35_080400
Figure 35: Delay Factor at Various Capacitive Loads
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Speed Grade
-5
-4
Symbol
Description
Device
Min
Max
Min
Max Units
Setup Times
T
T
Clock Enable (EC) to Clock (IK)
All devices
All devices
All devices
0.0
1.0
0.7
-
-
-
0.0
1.2
0.8
-
-
-
ns
ns
ns
ECIK
PICK
Pad to Clock (IK), no delay
T
Pad to Fast Capture Latch Enable (OK), no delay
POCK
Hold Times
All Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays
T
Pad to I1, I2
All devices
All devices
All devices
All devices
-
-
-
-
0.9
2.1
1.0
1.1
-
-
-
-
1.1
2.5
1.1
1.2
ns
ns
ns
ns
PID
T
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
PLI
T
IKRI
T
Clock (IK) to I1, I2 (latch enable, active Low)
IKLI
Delay Adder for Input with Full Delay Option
T
T
T
= T
+ T
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
4.0
4.8
5.0
5.5
6.5
-
-
-
-
-
4.7
5.6
5.9
6.5
7.6
-
-
-
-
-
ns
ns
ns
ns
ns
Delay
PICKD
PICK
Delay
= T + T
PDLI
PLI
Delay
Global Set/Reset
T
Minimum GSR pulse width
All devices 10.5
-
11.5
-
ns
ns
ns
ns
ns
ns
MRW
T
Delay from GSR input to any Q
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
-
-
-
-
-
9.0
-
-
-
-
-
10.5
11.0
11.5
12.5
13.5
RRI
9.5
10.0
11.0
12.0
Notes:
1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family IOB Output Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Values are expressed in nanoseconds unless otherwise
noted.
Speed Grade
-5
-4
Symbol
Description
Device
Min
Max
Min
Max
Units
Propagation Delays
T
Clock (OK) to Pad, fast
All devices
All devices
All devices
All devices
All devices
All devices
All devices
-
-
-
-
-
-
-
3.2
2.5
2.8
2.6
3.7
3.3
1.5
-
-
-
-
-
-
-
3.7
2.9
3.3
3.0
4.4
3.9
1.7
ns
ns
ns
ns
ns
ns
ns
OKPOF
T
Output (O) to Pad, fast
OPF
T
3-state to Pad High-Z (slew-rate independent)
3-state to Pad active and valid, fast
Output (O) to Pad via Output MUX, fast
Select (OK) to Pad via Output MUX, fast
For Output SLOW option add
TSHZ
T
TSONF
T
OFPF
T
OKFPF
T
SLOW
Setup and Hold Times
T
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
All devices
All devices
All devices
All devices
0.5
0.0
0.0
0.1
-
-
-
-
0.5
0.0
0.0
0.2
-
-
-
-
ns
ns
ns
ns
OOK
T
OKO
T
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
ECOK
T
OKEC
Global Set/Reset
T
Minimum GSR pulse width
All devices
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
10.5
-
11.5
-
ns
ns
ns
ns
ns
ns
MRW
T
Delay from GSR input to any Pad
-
-
-
-
-
11.9
12.4
12.9
13.9
14.9
-
-
-
-
-
14.0
14.5
15.0
16.0
17.0
RPO
Notes:
1. Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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Spartan and Spartan-XL FPGA Families Data Sheet
Pin Descriptions
There are three types of pins in the Spartan/XL devices:
Any user I/O can be configured to drive the Global
Set/Reset net GSR or the global three-state net GTS. See
Global Signals: GSR and GTS, page 20 for more informa-
tion.
•
•
•
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
Device pins for Spartan/XL devices are described in
Table 18.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with the I/O pull-up resis-
tor network activated. After configuration, if an IOB is
unused it is configured as an input with the I/O pull-up resis-
tor network remaining activated.
Some Spartan-XL devices are available in Pb-free package
options. The Pb-free package options have the same pin-
outs as the standard package options.
Table 18: Pin Descriptions
I/O
During
Config.
I/O After
Config.
Pin Name
Pin Description
Permanently Dedicated Pins
V
X
X
Eight or more (depending on package) connections to the nominal +5V supply
voltage (+3.3V for Spartan-XL devices). All must be connected, and each must be
decoupled with a 0.01 –0.1 μF capacitor to Ground.
CC
GND
X
X
I
Eight or more (depending on package type) connections to Ground. All must be
connected.
CCLK
I or O
During configuration, Configuration Clock (CCLK) is an output in Master mode and
is an input in Slave mode. After configuration, CCLK has a weak pull-up resistor
and can be selected as the Readback Clock. There is no CCLK High or Low time
restriction on Spartan/XL devices, except during Readback. See Violating the
Maximum High and Low Time Specification for the Readback Clock, page 39
for an explanation of this exception.
DONE
I/O
O
DONE is a bidirectional signal with an optional internal pull-up resistor. As an
open-drain output, it indicates the completion of the configuration process. As an
input, a Low level on DONE can be configured to delay the global logic initialization
and the enabling of outputs.
The optional pull-up resistor is selected as an option in the program that creates
the configuration bitstream. The resistor is included by default.
PROGRAM
I
I
I
PROGRAM is an active Low input that forces the FPGA to clear its configuration
memory. It is used to initiate a configuration cycle. When PROGRAM goes High,
the FPGA finishes the current clear cycle and executes another complete clear
cycle, before it goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally
pulled up to VCC.
MODE
(Spartan)
X
The Mode input(s) are sampled after INIT goes High to determine the
configuration mode to be used.
M0, M1
(Spartan-XL)
During configuration, these pins have a weak pull-up resistor. For the most popular
configuration mode, Slave Serial, the mode pins can be left unconnected. For
Master Serial mode, connect the Mode/M0 pin directly to system ground.
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Table 18: Pin Descriptions (Continued)
I/O
During
Config.
I/O After
Config.
Pin Name
Pin Description
PWRDWN
I
I
PWRDWN is an active Low input that forces the FPGA into the Power Down state
and reduces power consumption. When PWRDWN is Low, the FPGA disables all
I/O and initializes all flip-flops. All inputs are interpreted as Low independent of
their actual level. VCC must be maintained, and the configuration data is
maintained. PWRDWN halts configuration if asserted before or during
configuration, and re-starts configuration when removed. When PWRDWN returns
High, the FPGA becomes operational by first enabling the inputs and flip-flops and
then enabling the outputs. PWRDWN has a default internal pull-up resistor.
User I/O Pins That Can Have Special Functions
TDO
O
O
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not
used, this pin is a 3-state output without a register, after configuration is
completed.
To use this pin, place the library component TDO instead of the usual pad symbol.
An output buffer must still be used.
TDI, TCK,
TMS
I
I/O
or I
(JTAG)
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode
Select inputs respectively. They come directly from the pads, bypassing the IOBs.
These pins can also be used as inputs to the CLB logic after configuration is
completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are
inhibited once configuration is completed, and these pins become
user-programmable I/O. In this case, they must be called out by special library
elements. To use these pins, place the library components TDI, TCK, and TMS
instead of the usual pad symbols. Input or output buffers must still be used.
HDC
LDC
INIT
O
O
I/O
I/O
I/O
High During Configuration (HDC) is driven High until the I/O go active. It is
available as a control output indicating that configuration is not yet completed.
After configuration, HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available
as a control output indicating that configuration is not yet completed. After
configuration, LDC is a user-programmable I/O pin.
I/O
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ to 10 kΩ
external pull-up resistor is recommended.
As an active Low open-drain output, INIT is held Low during the power stabilization
and internal clearing of the configuration memory. As an active Low input, it can
be used to hold the FPGA in the internal WAIT state before the start of
configuration. Master mode devices stay in a WAIT state an additional 30 to
300 μs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error
has occurred. After the I/O go active, INIT is a user-programmable I/O pin.
PGCK1 -
PGCK4
(Spartan)
Weak
Pull-up
I or I/O
Four Primary Global inputs each drive a dedicated internal global net with short
delay and minimal skew. If not used to drive a global buffer, any of these pins is a
user-programmable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad
symbol connected directly to the input of a BUFGP symbol is automatically placed
on one of these pins.
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Table 18: Pin Descriptions (Continued)
I/O
During
Config.
I/O After
Config.
Pin Name
Pin Description
SGCK1 -
SGCK4
(Spartan)
Weak
Pull-up
(except
SGCK4
is DOUT)
I or I/O
Four Secondary Global inputs each drive a dedicated internal global net with short
delay and minimal skew. These internal global nets can also be driven from
internal logic. If not used to drive a global net, any of these pins is a
user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global
Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol
is automatically placed on one of these pins.
GCK1 -
GCK8
(Spartan-XL)
Weak
Pull-up
(except
GCK6 is
DOUT)
I or I/O
Eight Global inputs each drive a dedicated internal global net with short delay and
minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew
Buffers. Any input pad symbol connected directly to the input of a BUFGLS symbol
is automatically placed on one of these pins.
CS1
(Spartan-XL)
I
I
I
I/O
I/O
I/O
During Express configuration, CS1 is used as a serial-enable signal for
daisy-chaining.
D0-D7
(Spartan-XL)
During Express configuration, these eight input pins receive configuration data.
After configuration, they are user-programmable I/O pins.
DIN
During Slave Serial or Master Serial configuration, DIN is the serial configuration
data input receiving data on the rising edge of CCLK. After configuration, DIN is a
user-programmable I/O pin.
DOUT
O
I/O
During Slave Serial or Master Serial configuration, DOUT is the serial
configuration data output that can drive the DIN of daisy-chained slave FPGAs.
DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods
after it was received at the DIN input.
In Spartan-XL family Express mode, DOUT is the status output that can drive the
CS1 of daisy-chained FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
I/O
Weak
Pull-up
I/O
These pins can be configured to be input and/or output after configuration is
completed. Before configuration is completed, these pins have an internal
high-value pull-up resistor network that defines the logic level as High.
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Spartan and Spartan-XL FPGA Families Data Sheet
Device-Specific Pinout Tables
Device-specific tables include all packages for each Spar-
tan and Spartan-XL device. They follow the pad locations
around the die, and include boundary scan register loca-
tions.
XCS05 and XCS05XL Device Pinouts
XCS05/XL
Pad Name
Bndry
Scan
126
(4)
PC84
VQ100
P26
(1)
(1)
Not Connected
,
P34
(2)
Some Spartan-XL devices are available in Pb-free package
options. The Pb-free package options have the same pin-
outs as the standard package options.
PWRDWN
(1)
(2)
(3)
I/O, PGCK2 , GCK3
P35
P36
-
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
127
130
133
136
139
142
145
148
(3)
I/O (HDC)
I/O
(3)
XCS05 and XCS05XL Device Pinouts
(3)
I/O (LDC)
I/O
I/O
I/O
I/O
P37
P38
P39
-
XCS05/XL
Pad Name
Bndry
Scan
(3)
(4)
PC84
P2
P3
P4
-
VQ100
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
(3)
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
(3)
32
35
38
41
44
47
50
53
56
59
-
(3)
-
(3)
I/O
P40
P41
P42
P43
P44
P45
-
151
154
(3)
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
P5
P6
P7
P8
P9
(3)
157
160
163
166
169
172
175
178
(3)
(3)
(3)
-
(1)
(2)
(2)
I/O, SGCK1 , GCK8
VCC
P10
P11
P12
P13
P14
P15
P16
P17
P18
-
P19
P20
P21
P22
P23
P24
-
P25
P26
P27
-
P28
P29
P30
P31
P32
P33
(3)
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
-
(3)
GND
-
(3)
(1)
I/O, PGCK1 , GCK1
62
65
68
71
74
77
83
86
89
-
(3)
I/O
I/O
I/O
(3)
181
184
I/O, TDI
I/O, TCK
I/O, TMS
I/O
(1)
(2)
(2)
(3)
I/O, SGCK3 , GCK4
GND
DONE
VCC
-
-
-
-
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PROGRAM
(2)
(3)
I/O (D7
)
187
190
193
196
199
202
205
208
(1)
(3)
I/O, PGCK3 , GCK5
(2)
(3)
I/O (D6
I/O
)
-
(3)
92
95
98
104
107
110
113
116
119
122
-
(2)
(2)
(2)
(3)
I/O (D5
I/O
I/O
I/O
I/O (D4
I/O
VCC
GND
I/O (D3
I/O
)
P59
P60
-
(3)
(3)
(3)
-
(3)
)
)
P61
P62
P63
P64
P65
P66
-
P67
P68
P69
211
214
(3)
-
-
I/O
(1)
(2)
(2)
I/O, SGCK2 , GCK2
(3)
217
220
223
229
232
235
(1)
Not Connected , M1
(3)
GND
(3)
I/O
I/O (D2
I/O
(1)
(2)
MODE , M0
125
-
(2)
(2)
(3)
)
VCC
(3)
(3)
I/O (D1
)
DS060 (v2.0) March 1, 2013
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65
Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS05 and XCS05XL Device Pinouts
XCS10 and XCS10XL Device Pinouts
XCS05/XL
Pad Name
Bndry
Scan
XCS10/XL
Pad Name PC84
Bndry
TQ144 Scan
(4)
(4)
(2,4)
PC84
P70
VQ100
P71
P72
VQ100 CS144
(3)
I/O
238
241
244
I/O,
SGCK1
GCK8
P10
P99
A2
P143
83
(1)
(2)
(3)
I/O (D0 , DIN)
P71
P72
(2)
(1)
(2)
(3)
I/O, SGCK4 , GCK6
P73
VCC
GND
P11
P12
P13
P100
P1
P2
B2
A1
B1
P144
P1
-
-
(DOUT)
CCLK
VCC
O, TDO
GND
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
-
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
-
-
0
-
2
I/O,
PGCK1
GCK1
P2
86
(1)
(2)
I/O
I/O
I/O
I/O, TDI
I/O, TCK
GND
I/O
I/O
I/O, TMS
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
P14
P3
-
-
P4
P5
-
-
-
P6
P7
-
P8
P9
P10
P11
P12
P13
P14
P15
-
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
G2
G1
G3
G4
H1
H2
H3
H4
J1
P3
P4
89
92
I/O
-
(1)
(2)
I/O, PGCK4 , GCK7
5
8
-
P15
P16
-
P5
95
(2)
I/O (CS1
I/O
)
P6
98
11
14
17
20
23
26
29
-
P7
P8
101
-
I/O
I/O
I/O
I/O
I/O
I/O
GND
Notes:
-
-
P9
104
107
110
113
116
119
122
125
-
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
-
P17
P18
-
P83
P84
P1
-
P19
P20
P21
P22
P23
P24
-
1. 5V Spartan family only
2. 3V Spartan-XL family only
3. The “PWRDWN” on the XCS05XL is not part of the Boundary
Scan chain. For the XCS05XL, subtract 1 from all Boundary
Scan numbers from GCK3 on (127 and higher).
-
4. PC84 package discontinued by PDN2004-01
128
131
134
137
140
143
146
149
-
152
155
158
161
164
167
-
XCS10 and XCS10XL Device Pinouts
P25
P26
-
P16
P17
-
XCS10/XL
Pad Name PC84
Bndry
TQ144 Scan
(4)
(2,4)
VQ100 CS144
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
P2
P3
P4
-
P89
P90
P91
P92
P93
P94
P95
-
D7
A6
B6
C6
D6
A5
B5
C5
D5
A4
B4
C4
A3
B3
C3
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
-
-
-
-
J2
44
47
50
53
56
59
62
65
-
68
71
74
77
80
-
J3
P27
-
P18
P19
-
J4
K1
K2
K3
L1
L2
-
-
-
P5
P6
-
-
-
P7
P8
-
-
P9
I/O
I/O
-
P28
P29
P20
P21
I/O,
SGCK2
GCK2
-
-
(1)
(2)
P96
P97
-
Not
P30
P22
L3
P34
170
Connect-
(1)
ed
(2)
M1
-
GND
P31
P32
P23
P24
M1
M2
P35
P36
-
P98
(1)
MODE
,
173
(2)
M0
66
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DS060 (v2.0) March 1, 2013
Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS10 and XCS10XL Device Pinouts
XCS10 and XCS10XL Device Pinouts
XCS10/XL
Pad Name PC84
VCC
Not
Bndry
TQ144 Scan
XCS10/XL
Pad Name PC84
Bndry
(4)
(2,4)
(4)
(2,4)
VQ100 CS144
VQ100 CS144
P54
TQ144 Scan
(3)
P33
P34
P25
P26
N1
N2
P37
-
I/O,
PGCK3
GCK5
P57
L13
P76 262
(1)
(1)
P38 174
(2)
Connect-
(1)
(3)
ed
I/O
-
-
-
-
K10
K11
K12
K13
J10
J11
J12
J13
P77 265
P78 268
P79 271
P80 274
(3)
(2
I/O
I/O (D6
I/O
PWRDWN
)
(2)
(3)
)
P58
P55
P56
-
-
-
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
-
P68
P69
-
-
-
P70
P71
-
(3)
(3)
-
-
-
I/O,
PGCK2
GCK3
P35
P27
M3
P39 175
(1)
GND
I/O
P81
-
(2)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
P82 277
P83 280
P84 283
P85 286
P86 289
P87 292
P88 295
P89 298
(3)
(3)
(3)
(3)
(3)
I/O (HDC)
I/O
I/O
P36
P28
-
-
N3
K4
L4
P40 178
P41 181
P42 184
P43 187
P44 190
I/O
I/O (D5
I/O
I/O
I/O
I/O (D4
I/O
VCC
GND
I/O (D3
I/O
-
(2)
(2)
(2)
(2)
-
-
-
)
)
)
)
P59
P60
-
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D12
D11
C13
C12
I/O
P29
P30
-
M4
N4
K5
L5
I/O (LDC)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P37
-
-
P45
-
P61
P62
P63
P64
P65
P66
-
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
-
-
-
P46 193
P47 196
P48 199
P49 202
P50 205
P51 208
P52 211
P53 214
-
M5
N5
K6
L6
M6
N6
M7
N7
L7
K7
N8
M8
L8
K8
N9
M9
L9
P90
P91
-
-
P38
P39
-
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
-
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
P92 301
P93 304
P94 307
P95 310
P96 313
P97 316
P98 319
P99 322
-
I/O
I/O
I/O (D2
I/O
P40
P41
P42
P43
P44
P45
-
-
P67
P68
-
P54
P55
-
-
I/O
I/O
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
P56 217
P57 220
P58 223
P59 226
P60 229
P61 232
P62 235
P63 238
-
-
GND
I/O (D1
I/O
I/O
I/O
P100
-
(2)
(2)
(3)
(3)
(3)
(3)
(3)
)
,
P69
P70
-
P101 325
P102 328
P103 331
P104 334
P105 337
-
P46
P47
-
-
-
I/O (D0
DIN)
P71
P72
I/O
GND
I/O
I/O
I/O
-
-
-
(3)
-
K9
P64
-
I/O,
SGCK4
GCK6
P72
P73
C11
P106 340
(1)
(3)
(3)
(3)
(3)
(3)
(3)
P48
P49
-
P45
P46
-
N10
M10
L10
N11
M11
L11
P65 241
P66 244
P67 247
P68 250
P69 253
P70 256
(2)
(DOUT)
CCLK
VCC
O, TDO
GND
I/O
P73
P74
P75
P76
P77
P78
P74
P75
P76
P77
P78
P79
B13
B12
A13
A12
B11
A11
P107
P108
P109
P110
P111
P112
-
-
0
-
2
5
I/O
I/O
-
-
P50
P51
P47
P48
I/O,
SGCK3
GCK4
(1)
(2)
I/O,
PGCK4
GCK7
GND
DONE
VCC
P52
P53
P54
P55
P56
P49
P50
P51
P52
P53
N12
M12
N13
M13
L12
P71
P72
P73
P74
-
-
-
-
(1)
(2)
I/O
-
-
-
-
D10
C10
B10
P113
P114
P115
8
11
14
PROGRAM
(2)
I/O
I/O (CS1
(3)
I/O (D7
)
P75 259
(2)
)
P79
P80
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
Additional XCS10/XL Package Pins
XCS10 and XCS10XL Device Pinouts
XCS10/XL
Pad Name PC84
Bndry
TQ144 Scan
(4)
(2,4)
TQ144
VQ100 CS144
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P80
-
-
P81
-
-
A10
P116
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
17
-
Not Connected Pins
C9
B9
A9
D8
C8
B8
A8
B7
A7
C7
P117
-
-
-
-
-
-
-
-
20
23
26
29
32
35
38
41
-
5/5/97
-
-
P81
P82
-
P82
P83
P84
P85
P86
P87
P88
CS144
Not Connected Pins
-
D9
-
-
P83
P84
P1
4/28/99
GND
Notes:
1. 5V Spartan family only
2. 3V Spartan-XL family only
3. The “PWRDWN” on the XCS10XL is not part of the Boundary
Scan chain. For the XCS10XL, subtract 1 from all Boundary
Scan numbers from GCK3 on (175 and higher).
4. PC84 and CS144 packages discontinued by PDN2004-01
XCS20 and XCS20XL Device Pinouts
XCS20 and XCS20XL Device Pinouts
XCS20/XL
Bndry
Scan
Pad Name VQ100 CS144(2,4) TQ144 PQ208
XCS20/XL
Bndry
Scan
Pad Name VQ100 CS144(2,4) TQ144 PQ208
I/O,
SGCK1(1)
GCK8(2)
P99
A2
P143
P207
119
,
VCC
I/O
P89
D7
A6
B6
C6
D6
-
P128
P129
P130
P131
P132
-
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P204
P205
P206
-
P90
62
65
68
71
74
77
80
83
-
VCC
GND
P100
P1
B2
A1
B1
P144
P1
P208
P1
-
-
I/O
P91
I/O
P92
I/O,
PGCK1(1)
GCK1(2)
P2
P2
P2
122
I/O
P93
,
I/O
-
I/O
-
-
-
I/O
P3
C2
C1
D4
D3
D2
-
P3
P4
P5
P6
P7
-
P3
P4
125
128
131
134
137
140
143
146
149
-
I/O
P94
A5
B5
-
P133
P134
-
I/O
-
I/O
VCC(2)
P95
I/O
-
P5
-
I/O, TDI
I/O, TCK
I/O
P4
P6
I/O
-
C5
D5
A4
-
P135
P136
P137
-
86
89
-
P5
P7
I/O
-
-
P8
GND
I/O
-
I/O
-
-
-
P9
-
92
95
98
101
104
107
110
113
116
I/O
-
-
-
-
P10
P11
P13
P14
P15
P16
P17
P18
P19
P20
I/O
-
-
-
I/O
-
-
I/O
-
-
-
-
GND
I/O
-
D1
E4
E3
E2
E1
-
P8
P9
P10
P11
P12
-
I/O
-
-
-
152
155
158
161
-
I/O
P96
P97
-
B4
C4
A3
B3
C3
P138
P139
P140
P141
P142
I/O
-
I/O
I/O, TMS
I/O
VCC(2)
P6
P7
-
I/O
I/O
-
I/O
P98
I/O
-
-
-
164
167
I/O
-
-
-
68
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS20 and XCS20XL Device Pinouts
XCS20 and XCS20XL Device Pinouts
XCS20/XL
Bndry
Scan
XCS20/XL
Bndry
Scan
Pad Name VQ100 CS144(2,4) TQ144 PQ208
Pad Name VQ100 CS144(2,4) TQ144 PQ208
I/O
-
F4
F3
F2
F1
G2
G1
G3
G4
H1
H2
-
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
-
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
170
173
176
179
-
I/O (LDC)
I/O
P30
N4
-
P44
-
P60
P61
P62
P63
P64
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
262 (3)
265 (3)
268 (3)
271 (3)
274 (3)
-
277 (3)
280 (3)
283 (3)
286 (3)
-
289 (3)
292 (3)
295 (3)
298 (3)
301 (3)
304 (3)
-
I/O
P8
-
I/O
P9
I/O
-
-
-
I/O
P10
I/O
-
-
-
GND
VCC
I/O
P11
I/O
-
-
-
P12
-
GND
I/O
-
K5
L5
M5
N5
K6
-
P45
P46
P47
P48
P49
-
P13
182
185
188
191
194
197
-
-
-
I/O
P14
I/O
I/O
P15
I/O
P31
P32
-
I/O
-
I/O
VCC(2)
I/O
-
I/O
VCC(2)
-
-
-
I/O
-
-
-
-
-
-
I/O
-
-
-
I/O
P16
H3
H4
J1
J2
J3
-
P23
P24
P25
P26
P27
-
200
203
206
209
-
I/O
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
-
L6
M6
N6
M7
N7
L7
K7
N8
M8
L8
-
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
-
I/O
P17
I/O
I/O
-
I/O
I/O
-
I/O (INIT)
VCC
GND
I/O
GND
I/O
-
-
212
215
218
221
224
227
230
233
236
239
-
I/O
-
-
-
-
307 (3)
310 (3)
313 (3)
316 (3)
319 (3)
322 (3)
-
325 (3)
328 (3)
331 (3)
334 (3)
-
337 (3)
340 (3)
343 (3)
346 (3)
349 (3)
352 (3)
355 (3)
358 (3)
361 (3)
364 (3)
I/O
-
-
I/O
I/O
-
-
-
I/O
I/O
P18
P19
-
J4
K1
K2
K3
L1
L2
P28
P29
P30
P31
P32
P33
I/O
I/O
I/O
I/O
I/O
VCC(2)
-
-
-
I/O
-
-
-
-
I/O
P20
P21
I/O
P43
P44
-
K8
N9
M9
L9
K9
-
P60
P61
P62
P63
P64
-
I/O,
SGCK2(1)
GCK2(2)
I/O
,
I/O
I/O
-
Not
Connected(1)
M1(2)
P22
L3
P34
P50
242
GND
I/O
-
-
I/O
-
-
-
GND
MODE(1)
M0(2)
P23
P24
M1
M2
P35
P36
P51
P52
-
I/O
-
-
-
,
245
I/O
-
-
-
VCC
Not
P25
P26
N1
N2
P37
P38
P53
P54
-
I/O
P45
P46
-
N10
M10
L10
N11
M11
L11
P65
P66
P67
P68
P69
P70
246 (1)
I/O
Connected(1)
PWRDWN(2)
I/O,
I/O
I/O
-
P27
M3
P39
P55
247 (3)
I/O
P47
P48
PGCK2(1)
GCK3(2)
,
I/O,
SGCK3(1)
GCK4(2)
,
I/O (HDC)
I/O
P28
N3
K4
L4
P40
P41
P42
P43
P56
P57
P58
P59
250 (3)
253 (3)
256 (3)
259 (3)
-
-
GND
DONE
VCC
P49
P50
P51
N12
M12
N13
P71
P72
P73
P103
P104
P105
-
-
-
I/O
I/O
P29
M4
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Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS20 and XCS20XL Device Pinouts
XCS20 and XCS20XL Device Pinouts
XCS20/XL
Bndry
Scan
XCS20/XL
Bndry
Scan
Pad Name VQ100 CS144(2,4) TQ144 PQ208
Pad Name VQ100 CS144(2,4) TQ144 PQ208
PROGRAM
P52
P53
P54
M13
L12
L13
P74
P75
P76
P106
P107
P108
-
I/O
-
C13
C12
P104
P105
P152
P153
478 (3)
481 (3)
I/O (D7(2)
)
367 (3)
370 (3)
I/O
(D0(2), DIN)
P72
I/O,
PGCK3(1)
GCK5(2)
,
I/O,
P73
C11
P106
P154
484 (3)
SGCK4(1)
GCK6(2)
(DOUT)
,
I/O
-
K10
K11
K12
K13
-
P77
P78
P79
P80
-
P109
P110
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P145
P146
P147
P148
P149
P150
P151
373 (3)
376 (3)
379 (3)
382 (3)
385 (3)
388 (3)
391 (3)
394 (3)
-
I/O
-
CCLK
VCC
P74
P75
P76
P77
P78
P79
B13
B12
A13
A12
B11
A11
P107
P108
P109
P110
P111
P112
P155
P156
P157
P158
P159
P160
-
-
I/O (D6(2)
I/O
)
P55
P56
O, TDO
GND
I/O
0
-
I/O
-
I/O
-
-
-
2
5
I/O
-
-
-
I/O,
PGCK4(1)
GCK7(2)
I/O
-
-
-
,
GND
I/O
-
J10
J11
J12
-
P81
P82
P83
-
-
397 (3)
400 (3)
-
I/O
-
D10
C10
B10
A10
D9
-
P113
P114
P115
P116
P117
-
P161
P162
P163
P164
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
8
I/O
-
I/O
-
11
14
17
20
23
26
29
-
VCC(2)
I/O (D5(2)
I/O
-
I/O (CS1(2)
I/O
)
P80
)
P57
J13
H10
-
P84
P85
-
403 (3)
406 (3)
409 (3)
412 (3)
415 (3)
418 (3)
421 (3)
424 (3)
-
P81
P58
I/O
-
I/O
-
I/O
-
I/O
-
-
-
I/O
-
-
-
I/O
P59
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
-
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
-
I/O
-
-
-
-
I/O
P60
GND
I/O
C9
B9
A9
-
P118
P119
P120
-
I/O (D4(2)
)
)
P61
-
32
35
-
I/O
P62
I/O
VCC(2)
-
VCC
GND
I/O (D3(2)
I/O
P63
-
P64
-
I/O
P82
P83
-
D8
C8
-
P121
P122
-
38
41
44
47
50
53
56
59
-
P65
427 (3)
430 (3)
433 (3)
436 (3)
439 (3)
442 (3)
445 (3)
448 (3)
-
451 (3)
454 (3)
-
457 (3)
460 (3)
463 (3)
466 (3)
469 (3)
472 (3)
475 (3)
I/O
P66
I/O
I/O
P67
I/O
-
-
-
I/O
-
I/O
P84
P85
P86
P87
P88
B8
A8
B7
A7
C7
P123
P124
P125
P126
P127
I/O
-
I/O
I/O
-
-
-
I/O
I/O (D2(2)
)
P68
F10
E13
-
P96
P97
-
I/O
I/O
P69
GND
2/8/00
VCC(2)
I/O
-
-
E12
E11
E10
-
P98
P99
P100
-
I/O
-
GND
I/O
-
-
I/O
-
-
-
I/O
-
-
-
-
I/O
-
-
I/O (D1(2)
)
P70
P71
-
D13
D12
D11
P101
P102
P103
I/O
I/O
70
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
Additional XCS20/XL Package Pins
PQ208
Not Connected Pins
P12
P86 (1)
P18 (1)
P92
P33 (1)
P39
P121(1) P140(1)
P202 P203
P65
P71 (1)
P144
-
P111
P165
9/16/98
P173(1) P192(1)
Notes:
1. 5V Spartan family only
2. 3V Spartan-XL family only
3. The “PWRDWN” on the XCS20XL is not part of the
Boundary Scan chain. For the XCS20XL, subtract 1 from all
Boundary Scan numbers from GCK3 on (247 and higher).
4. CS144 package discontinued by PDN2004-01
XCS30 and XCS30XL Device Pinouts
XCS30/XL
Pad Name
Bndry
Scan
VQ100(5)
TQ144
P128
P129
P130
P131
P132
-
PQ208
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
-
PQ240
P212
P213
P214
P215
P216
P217
P218
P220
P221
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239
P240
P1
BG256(5)
VCC(4)
C10
D10
A9
CS280(2,5)
C10
D10
E10
A9
VCC
P89
-
I/O
P90
74
I/O
P91
77
I/O
P92
80
I/O
P93
B9
B9
83
I/O
-
C9
C9
86
I/O
-
-
D9
D9
89
I/O
P94
P133
P134
-
A8
A8
92
I/O
P95
B8
VCC(4)
B8
95
VCC
-
A7
-
I/O
-
-
A6
B7
98
I/O
-
-
-
C7
C7
101
104
107
-
I/O
-
P135
P136
P137
-
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204
P205
P206
P207
P208
P1
B6
D7
I/O
-
A5
GND(4)
A6
GND(4)
GND
-
I/O
-
C6
B6
110
113
116
119
122
125
128
131
134
137
140
143
-
I/O
-
-
B5
C6
I/O
-
-
-
A4
D6
I/O
-
C5
E6
I/O
P96
P97
-
P138
P139
-
B4
A5
I/O
A3
C5
I/O
D5
B4
I/O
-
-
C4
C4
I/O
-
P140
P141
P142
P143
P144
P1
B3
A3
I/O
-
B2
A2
I/O
P98
P99
P100
P1
P2
P3
-
A2
B3
I/O, SGCK1(1), GCK8(2)
C3
B2
VCC
VCC(4)
GND(4)
B1
A1
GND(4)
GND
-
I/O, PGCK1(1), GCK1(2)
P2
P2
P2
C3
146
149
152
I/O
I/O
P3
P3
P3
C2
C2
P4
P4
P4
D2
B1
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS30 and XCS30XL Device Pinouts (Continued)
XCS30/XL
Pad Name
Bndry
Scan
VQ100(5)
TQ144
PQ208
P5
PQ240
P5
BG256(5)
D3
CS280(2,5)
C1
I/O
-
P5
155
158
161
164
167
170
173
176
179
-
I/O, TDI
I/O, TCK
I/O
P4
P6
P6
P6
E4
D4
P5
P7
P7
P7
C1
D3
-
-
P8
P8
D1
E2
I/O
-
-
P9
P9
E3
E4
I/O
-
-
P10
P11
P12
-
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
E2
E1
I/O
-
-
E1
F5
I/O
-
-
-
F3
F3
I/O
-
F2
GND(4)
F2
GND(4)
GND
I/O
-
P8
P9
P10
P11
P12
-
P13
P14
P15
P16
P17
P18
-
-
G3
F4
182
185
188
191
-
I/O
-
G2
F1
I/O, TMS
I/O
P6
G1
G3
G2
G1
G4
H1
P7
H3
VCC(4)
VCC
I/O
-
-
-
H2
194
197
200
203
206
209
212
215
-
I/O
-
-
-
H1
I/O
-
-
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
-
J2
H4
I/O
-
-
J1
J1
I/O
-
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
-
K2
J2
I/O
P8
K3
J3
I/O
P9
K1
J4
I/O
P10
L1
K1
GND(4)
GND
VCC
I/O
P11
GND(4)
VCC(4)
L2
P12
K2
-
P13
K3
218
221
224
227
230
233
236
239
-
I/O
P14
L3
K4
I/O
P15
L4
K5
I/O
-
M1
L1
I/O
-
M2
L2
I/O
-
-
M3
L3
I/O
-
-
N1
M2
M3
M4
N1
I/O
-
-
-
N2
VCC(4)
VCC
I/O
-
-
P33
P34
P35
P36
P37
P38
-
P16
P23
P24
P25
P26
P27
-
P1
242
245
248
251
-
I/O
P17
P2
N2
I/O
-
-
-
-
-
-
-
-
-
R1
N3
I/O
P3
GND(4)
N4
GND(4)
GND
I/O
T1
P1
254
257
260
263
266
269
I/O
-
P39
P40
P41
P42
P43
R3
P2
I/O
-
T2
P3
I/O
-
U1
P4
I/O
-
T3
P5
I/O
-
U2
R1
72
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS30 and XCS30XL Device Pinouts (Continued)
XCS30/XL
Pad Name
Bndry
VQ100(5)
P18
P19
-
TQ144
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
PQ208
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
PQ240
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
BG256(5)
V1
CS280(2,5)
T1
Scan
272
275
278
281
284
287
290
-
I/O
I/O
T4
T2
I/O
U3
T3
I/O
-
V2
U1
I/O
P20
P21
P22
P23
P24
P25
P26
W1
V1
I/O, SGCK2(1), GCK2(2)
Not Connected(1), M1(2)
GND
V3
U2
W2
GND(4)
V2
GND(4)
MODE(1), M0(2)
Y1
W1
293
-
294 (1)
VCC
VCC(4)
W3
U3
Not Connected (1)
PWRDWN(2)
,
V3
I/O, PGCK2(1), GCK3(2)
P27
P39
P40
P41
P42
P43
P44
-
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
-
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
Y2
W4
W2
W3
T4
295 (3)
298 (3)
301 (3)
304 (3)
307 (3)
310 (3)
313 (3)
316 (3)
319 (3)
322 (3)
325 (3)
328 (3)
-
331 (3)
334 (3)
337 (3)
340 (3)
-
343 (3)
346 (3)
349 (3)
352 (3)
355 (3)
358 (3)
361 (3)
364 (3)
-
I/O (HDC)
I/O
P28
-
V4
I/O
-
U5
U4
I/O
P29
Y3
V4
I/O (LDC)
I/O
P30
Y4
W4
T5
-
V5
I/O
-
-
W5
W5
R6
I/O
-
-
Y5
I/O
-
-
V6
U6
I/O
-
-
-
W6
V6
I/O
-
Y6
GND(4)
T6
GND
I/O
-
P45
P46
P47
P48
P49
-
P66
P67
P68
P69
P70
P71
P72
P73
-
GND(4)
W6
U7
-
W7
I/O
-
Y7
I/O
P31
P32
-
V8
V7
I/O
W8
VCC(4)
W7
T7
VCC
I/O
-
-
Y8
W8
U8
I/O
-
-
U9
I/O
-
-
Y9
W9
V9
I/O
-
-
-
W10
V10
Y10
Y11
W11
VCC(4)
GND(4)
V11
U11
Y12
W12
V12
I/O
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
-
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
-
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
U9
I/O
T9
I/O
W10
V10
U10
GND(4)
T10
R10
W11
V11
U11
I/O (INIT)
VCC
GND
I/O
-
367 (3)
370 (3)
373 (3)
376 (3)
379 (3)
I/O
I/O
I/O
I/O
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS30 and XCS30XL Device Pinouts (Continued)
XCS30/XL
Pad Name
Bndry
Scan
VQ100(5)
TQ144
-
PQ208
P85
-
PQ240
P97
BG256(5)
U12
CS280(2,5)
T11
I/O
-
382 (3)
385 (3)
388 (3)
-
391 (3)
394 (3)
397 (3)
400 (3)
-
403 (3)
406 (3)
409 (3)
412 (3)
415 (3)
418 (3)
421 (3)
424 (3)
427 (3)
430 (3)
433 (3)
436 (3)
-
I/O
-
-
P99
V13
U12
T12
I/O
-
-
-
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
Y14
VCC(4)
VCC
-
-
P86
P87
P88
P89
P90
P91
-
W13
V13
I/O
P43
P60
P61
P62
P63
P64
-
Y15
I/O
P44
V14
U13
T13
I/O
-
W15
I/O
-
Y16
W14
GND(4)
V14
GND
-
GND(4)
V15
I/O
-
I/O
-
-
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
-
W16
Y17
U14
T14
I/O
-
-
I/O
-
-
V16
R14
W15
U15
V16
I/O
-
-
W17
Y18
I/O
-
-
I/O
P45
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
-
U16
I/O
P46
V17
U16
W17
W18
V17
I/O
-
W18
Y19
I/O
-
I/O
I/O, SGCK3(1), GCK4(2)
GND
P47
V18
P48
W19
GND(4)
Y20
V18
P49
GND(4)
W19
U17
U18
V19
DONE
P50
-
VCC
P51
VCC(4)
-
PROGRAM
P52
V19
-
I/O (D7(2)
)
P53
U19
439 (3)
442 (3)
445 (3)
448 (3)
451 (3)
454 (3)
457 (3)
460 (3)
463 (3)
466 (3)
469 (3)
472 (3)
-
I/O, PGCK3(1), GCK5(2)
P54
U18
U19
T16
I/O
I/O
I/O
I/O
-
T17
-
V20
T17
-
U20
T18
-
-
P111
P112
P113
P114
P115
P116
P117
P118
-
T18
T19
I/O (D6(2)
)
P55
P79
P80
-
T19
R16
R19
P15
I/O
P56
T20
I/O
-
R18
I/O
-
-
R19
P17
I/O
-
-
R20
P18
I/O
-
-
P18
GND(4)
P16
GND(4)
GND
I/O
-
P81
-
-
P20
P19
475 (3)
478 (3)
481 (3)
484 (3)
-
I/O
-
-
-
N18
N17
N18
N19
N16
M19
M17
I/O
-
-
P82
P83
-
P119
P120
P121
P122
P123
N19
I/O
N20
VCC
I/O (D5(2)
I/O
-
VCC(4)
M17
M18
)
P57
P58
P84
P85
487 (3)
490 (3)
74
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS30 and XCS30XL Device Pinouts (Continued)
XCS30/XL
Pad Name
Bndry
VQ100(5)
TQ144
-
PQ208
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
-
PQ240
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
BG256(5)
M20
L19
CS280(2,5)
L19
Scan
493 (3)
496 (3)
499 (3)
502 (3)
505 (3)
508 (3)
-
I/O
I/O
I/O
I/O
-
-
-
L18
P59
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
-
L18
L17
P60
L20
L16
I/O (D4(2)
)
)
P61
K20
K19
K18
K17
GND(4)
K16
K15
J19
I/O
P62
K19
VCC
GND
I/O (D3(2)
I/O
P63
VCC(4)
GND(4)
K18
P64
-
P65
511 (3)
514 (3)
517 (3)
520 (3)
523 (3)
526 (3)
529 (3)
532 (3)
-
535 (3)
538 (3)
541 (3)
544 (3)
-
547 (3)
550 (3)
553 (3)
556 (3)
559 (3)
562 (3)
565 (3)
568 (3)
571 (3)
574 (3)
577 (3)
580 (3)
P66
K17
I/O
P67
J20
I/O
-
J19
J18
I/O
-
J18
J17
I/O
-
-
J17
J16
I/O (D2(2)
)
P68
P96
P97
-
H19
H18
VCC(4)
G19
F20
H17
H16
G19
G18
G17
G16
F19
I/O
P69
VCC
I/O
-
-
P98
P99
-
I/O
-
I/O
-
G18
F19
GND(4)
I/O
-
-
-
GND
I/O
-
P100
-
P143
-
GND(4)
-
F18
F18
I/O
-
-
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
E19
F17
I/O
-
-
D20
E18
F16
I/O
-
-
-
F15
I/O
-
D19
C20
E17
E19
E17
E16
D19
C19
B19
C18
B18
I/O
-
-
I/O (D1(2)
)
P70
P71
-
P101
P102
P103
P104
P105
P106
I/O
D18
C19
B20
I/O
I/O
-
I/O (D0(2), DIN)
I/O, SGCK4(1), GCK6(2)
(DOUT)
P72
P73
C18
B19
CCLK
P74
P75
P76
P77
P78
P79
-
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
-
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
A20
VCC(4)
A19
A19
C17
B17
-
-
VCC
O, TDO
0
GND
GND(4)
GND(4)
-
I/O
B18
A18
2
I/O, PGCK4(1), GCK7(2)
B17
A17
5
I/O
C17
D16
C16
B16
8
I/O
-
D16
11
14
17
20
I/O (CS1)(2)
I/O
P80
P81
-
A18
A17
A16
I/O
C16
D15
DS060 (v2.0) March 1, 2013
www.xilinx.com
75
Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS30 and XCS30XL Device Pinouts (Continued)
XCS30/XL
Pad Name
Bndry
Scan
VQ100(5)
TQ144
PQ208
-
PQ240
P190
P191
P192
P193
P194
P196
P197
P198
P199
P200
P201
P202
P203
P205
P206
P207
P208
P209
P210
P211
BG256(5)
B16
CS280(2,5)
A15
I/O
-
-
23
26
29
32
35
-
I/O
-
P117
-
P166
P167
P168
P169
P170
P171
P172
-
A16
E14
I/O
-
C15
C14
I/O
-
-
B15
B14
I/O
-
-
A15
GND(4)
D14
GND(4)
GND
I/O
-
P118
P119
P120
-
-
-
B14
A14
38
41
44
47
-
I/O
A14
C13
I/O
-
C13
B13
I/O
-
-
-
B13
VCC(4)
A13
VCC
I/O
-
-
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
D13
P82
P83
-
P121
P122
-
C12
B12
50
53
56
59
62
65
68
71
-
I/O
B12
D12
I/O
A12
A11
I/O
-
-
B11
B11
I/O
P84
P85
P86
P87
P88
P123
P124
P125
P126
P127
C11
C11
I/O
A11
D11
I/O
A10
A10
I/O
B10
GND(4)
B10
GND(4)
GND
2/8/00
Notes:
1. 5V Spartan family only
2. 3V Spartan-XL family only
3. The “PWRDWN” on the XCS30XL is not part of the Boundary Scan chain. For the XCS30XL, subtract 1 from all Boundary Scan
numbers from GCK3 on (295 and higher).
4. Pads labeled GND(4) or VCC(4) are internally bonded to Ground or VCC planes within the package.
5. CS280 package, and VQ100 and BG256 packages for XCS30 only, discontinued by PDN2004-01
Additional XCS30/XL Package Pins
GND Pins
PQ240
A1
G20
U4
B7
H4
U8
D4
D8
N3
D13
N4
D17
N17
-
GND Pins
H17
U13
P22
P37
P83
-
P98
-
P143
-
P158
-
U17
W14
P204
P219
Not Connected Pins
Not Connected Pins
A7
J4
A13
M4
-
C8
M19
-
D12
V9
-
H20
W9
-
J3
W13
-
P195
-
-
-
-
-
2/12/98
Y13
6/4/97
BG256
CS280
VCC Pins
VCC Pins
C14
E20
K4
D6
F1
D7
F4
D11
F17
P17
U7
-
D14
G4
P19
U10
-
D15
G17
R2
A1
G1
T7
A7
C10
K2
C17
K17
D13
M4
G1
N16
-
L17
R17
V7
P4
G19
U3
R4
U6
U14
-
U10
U17
W13
U15
W20
GND Pins
76
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS40 and XCS40XL Device Pinouts
CS280
XCS40/XL
Bndry
VCC Pins
Pad Name PQ208 PQ240 BG256 CS280(2,5) Scan
E5
E7
G5
L5
R7
-
E8
G15
L15
R8
-
E9
H5
M5
R9
-
E11
H15
M15
R11
-
E12
J5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P200
P201
-
P232
P233
-
B4
A3
-
A5
C5
D5
A4
B4
C4
A3
A2
B3
B2
140
143
146
149
152
155
158
161
164
167
E13
J15
N15
R13
N5
R12
-
-
-
-
P202
P203
P204
P205
P206
P207
P234
P235
P236
P237
P238
P239
D5
C4
B3
B2
A2
C3
Not Connected Pins
A4
D2
A12
D5
C8
D8
H18
R2
T15
-
C12
D17
H19
R4
U5
-
C15
D18
L4
D1
E15
M1
R15
V12
-
I/O,
SGCK1(1)
GCK8(2)
,
,
H2
H3
VCC
GND
P208
P1
P240
P1
VCC(4)
GND(4)
B1
VCC(4)
GND(4)
C3
-
-
M16
R17
W12
M18
T8
R5
V8
-
I/O,
PGCK1(1)
GCK1(2)
P2
P2
170
W16
Not Connected Pins (VCC in XCS40XL)
I/O
P3
P4
P5
P6
P7
-
P3
P4
C2
D2
D3
E4
C1
-
C2
B1
173
176
179
182
185
188
191
194
197
200
203
206
209
-
B5
B15
V15
E3
-
E18
-
R3
-
R18
-
I/O
V5
I/O
P5
C1
D4
D3
D2
D1
E2
5/21/02
I/O, TDI
I/O, TCK
I/O
P6
P7
XCS40 and XCS40XL Device Pinouts
-
I/O
-
-
-
XCS40/XL
Bndry
Pad Name PQ208 PQ240 BG256 CS280(2,5) Scan
I/O
P8
P9
P10
P11
P12
-
P8
D1
E3
E2
E1
F3
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
P183
P184
P185
P186
P187
P188
P189
P190
P191
-
P212
P213
P214
P215
P216
P217
P218
P220
P221
-
VCC(4)
C10
D10
A9
VCC(4)
D10
E10
A9
-
I/O
P9
E4
86
I/O
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
-
E1
89
I/O
F5
92
I/O
F3
B9
B9
95
I/O
F2
F2
GND(4)
GND
I/O
P13
P14
P15
P16
P17
P18
-
GND(4)
G3
G2
G1
H3
VCC(4)
H2
H1
J4
C9
C9
98
D9
D9
101
104
107
110
113
-
F4
212
215
218
221
-
A8
A8
I/O
F1
B8
B8
I/O, TMS
I/O
G3
G2
VCC(4)
G4
H1
H3
H2
H4
J1
C8
C8
-
-
A7
VCC(4)
D8
VCC(4)
VCC
I/O
P192
-
P222
P223
P224
P225
P226
224
227
230
233
236
239
242
245
248
251
A6
B7
116
119
122
125
-
I/O
-
-
C7
C7
I/O
-
P193
P194
P195
P196
P197
P198
P199
B6
D7
I/O
-
-
J3
A5
A6
GND(4)
I/O
P19
P20
P21
P22
P23
P24
P23
P24
P25
P26
P27
P28
J2
P227 GND(4)
I/O
J1
P228
P229
P230
P231
C6
B5
A4
C5
B6
128
131
134
137
I/O
K2
K3
K1
L1
J2
C6
I/O
J3
D6
I/O
J4
E6
I/O
K1
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77
Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
XCS40 and XCS40XL Device Pinouts
XCS40 and XCS40XL Device Pinouts
XCS40/XL
Bndry
XCS40/XL
Bndry
Pad Name PQ208 PQ240 BG256 CS280(2,5) Scan
Pad Name PQ208 PQ240 BG256 CS280(2,5) Scan
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P25
P26
P27
P28
P29
P30
P31
P32
-
P29
P30
P31
P32
P33
P34
P35
P36
-
GND(4)
VCC(4)
L2
GND(4)
VCC(4)
K3
-
I/O (HDC)
I/O
P56
P57
P58
P59
P60
-
P64
P65
P66
P67
P68
-
W4
V4
W3
T4
346 (3)
349 (3)
352 (3)
355 (3)
358 (3)
361 (3)
364 (3)
367 (3)
370 (3)
373 (3)
376 (3)
379 (3)
382 (3)
-
385 (3)
388 (3)
391 (3)
394 (3)
-
397 (3)
400 (3)
403 (3)
406 (3)
409 (3)
412 (3)
415 (3)
418 (3)
421 (3)
424 (3)
VCC(4)
-
-
254
257
260
263
266
269
272
275
278
281
-
I/O
U5
U4
L3
K4
I/O
Y3
V4
L4
K5
I/O (LDC)
I/O
Y4
W4
M1
M2
M3
M4
-
L1
-
R5
L2
I/O
-
-
-
U5
L3
I/O
P61
P62
P63
P64
P65
-
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
-
V5
T5
L4
I/O
W5
W5
-
-
M1
M2
M3
VCC(4)
N1
I/O
Y5
R6
-
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
-
N1
N2
VCC(4)
P1
I/O
V6
U6
-
I/O
W6
V6
P33
P34
P35
P36
P37
P38
-
I/O
Y6
GND(4)
T6
GND(4)
284
287
290
293
-
GND
I/O
P66
P67
P68
P69
P70
P71
P72
P73
-
P2
N2
W7
W6
R1
N3
I/O
Y7
U7
P3
GND(4)
N4
GND(4)
I/O
V8
V7
I/O
W8
VCC(4)
W7
VCC(4)
T1
P1
296
299
302
305
308
311
314
317
320
323
326
329
332
335
VCC
I/O
P39
P40
P41
P42
P43
-
R3
P2
Y8
W8
T2
P3
I/O
U9
U8
U1
P4
I/O
V9
V8
T3
P5
I/O
-
-
W9
T8
U2
R1
I/O
-
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
-
Y9
W9
-
R2
I/O
-
W10
V10
Y10
Y11
W11
VCC(4)
GND(4)
V11
U11
Y12
W12
V12
U12
Y13
W13
V13
Y14
VCC(4)
Y15
V14
W15
V9
-
-
-
R4
I/O
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
-
U9
P44
P45
P46
P47
P48
P49
P52
P53
P54
P55
P56
P57
V1
T1
I/O
T9
T4
T2
I/O
W10
V10
VCC(4)
GND(4)
T10
R10
W11
V11
U11
T11
W12
V12
U12
T12
VCC(4)
V13
U13
T13
U3
T3
I/O (INIT)
VCC
GND
I/O
V2
U1
W1
V3
V1
I/O,
SGCK2(1)
GCK2 (2)
U2
427 (3)
430 (3)
433 (3)
436 (3)
439 (3)
442 (3)
445 (3)
448 (3)
451 (3)
454 (3)
-
,
I/O
I/O
Not
Connected(1)
M1(2)
P50
P58
W2
V2
338
I/O
I/O
GND(4)
Y1
GND(4)
W1
-
I/O
GND
MODE(1)
M0(2)
P51
P52
P59
P60
I/O
,
341
I/O
-
-
VCC
Not
Connected(1)
PWRDWN(2)
P53
P54
P61
P62
VCC(4)
W3
VCC(4)
V3
-
I/O
-
P99
P100
P101
P102
P103
P104
342(1)
I/O
-
VCC
I/O
P86
P87
P88
P89
457 (3)
460 (3)
463 (3)
I/O,
PGCK2(1)
GCK3(2)
P55
P63
Y2
W2
343 (3)
I/O
,
I/O
78
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Spartan and Spartan-XL FPGA Families Data Sheet
XCS40 and XCS40XL Device Pinouts
XCS40 and XCS40XL Device Pinouts
XCS40/XL
Bndry
XCS40/XL
Bndry
Pad Name PQ208 PQ240 BG256 CS280(2,5) Scan
Pad Name PQ208 PQ240 BG256 CS280(2,5) Scan
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P90
P91
-
P105
P106 GND(4)
Y16
W14
GND(4)
V14
466 (3)
I/O
-
-
-
M18
M16
L19
571 (3)
574 (3)
577 (3)
580 (3)
583 (3)
586 (3)
589 (3)
592 (3)
-
-
I/O
-
-
M19
M20
L19
P107
P108
P109
P110
P111
P112
-
V15
W16
Y17
V16
W17
Y18
-
469 (3)
472 (3)
475 (3)
478 (3)
481 (3)
484 (3)
487 (3)
490 (3)
493 (3)
496 (3)
499 (3)
502 (3)
505 (3)
508 (3)
I/O
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
-
P144
P145
P146
P147
P148
P149
P150
P92
P93
P94
P95
P96
-
U14
T14
I/O
L18
I/O
L18
L17
R14
W15
U15
T15
I/O
I/O (D4(2)
L20
L16
)
)
K20
K19
VCC(4)
K19
K18
VCC(4)
GND(4)
K16
K15
J19
I/O
VCC
GND
I/O (D3(2)
I/O
-
-
-
W16
V16
P151 GND(4)
-
P97
P98
P99
P100
P101
P102
P113
P114
P115
P116
P117
P118
U16
V17
W18
Y19
V18
W19
P152
P153
P154
P155
P156
P157
-
K18
K17
J20
595 (3)
598 (3)
601 (3)
604 (3)
607 (3)
610 (3)
613 (3)
616 (3)
619 (3)
622 (3)
-
625 (3)
628 (3)
631 (3)
634 (3)
-
637 (3)
640 (3)
643 (3)
646 (3)
649 (3)
652 (3)
655 (3)
658 (3)
661 (3)
664 (3)
667 (3)
670 (3)
673 (3)
U16
W17
W18
V17
I/O
I/O
J19
J18
I/O
J18
J17
I/O,
SGCK3(1)
GCK4(2)
V18
I/O
J17
J16
,
I/O
H20
-
H19
H18
H17
H16
VCC(4)
G18
G17
G16
F19
I/O
I/O (D2(2)
-
-
GND
DONE
VCC
P103
P104
P105
P106
P107
P108
P119 GND(4)
GND(4)
W19
VCC(4)
-
)
P138
P139
P140
P141
P142
-
P159
P160
P161
P162
P163
P164
P165
H19
H18
VCC(4)
G19
F20
G18
F19
P120
P121
P122
P123
P124
Y20
VCC(4)
V19
-
I/O
-
VCC
I/O
PROGRAM
I/O (D7(2)
U18
-
)
U19
V19
511 (3)
514 (3)
I/O
I/O,
PGCK3(1)
GCK5(2)
U18
U19
I/O
,
I/O
-
517 (3)
520 (3)
523 (3)
526 (3)
529 (3)
523 (3)
535 (3)
538 (3)
541 (3)
544 (3)
547 (3)
550 (3)
-
GND
I/O
P143
-
P166 GND(4)
GND(4)
I/O
I/O
I/O
I/O
I/O
I/O
P109
P110
-
P125
P126
P127
P128
-
T17
V20
U20
T18
-
T16
T17
P167
P168
P169
P170
P171
P172
P173
P174
-
F18
E19
D20
E18
D19
C20
E17
D18
-
F18
I/O
P144
P145
P146
P147
P148
P149
P150
-
F17
T18
I/O
F16
P111
-
T19
I/O
F15
R15
R17
R16
R19
P15
I/O
E19
E17
E16
D19
D18
D17
C19
B19
C18
-
-
-
I/O (D6(2)
)
P112
P113
P114
P115
P116
P117
P118
-
P129
P130
P131
P132
P133
P134
T19
T20
R18
R19
R20
P18
I/O
I/O (D1(2)
)
,
I/O
I/O
I/O
I/O
I/O
P17
I/O
-
-
-
I/O
P18
I/O
P151
P152
P153
P175
P176
P177
C19
B20
C18
I/O
P16
GND(4)
P135 GND(4)
I/O
I/O (D0(2)
DIN)
GND
I/O
P136
P137
P138
P139
P140
P141
P142
P20
N18
P19
553 (3)
556 (3)
559 (3)
562 (3)
-
I/O
-
N17
N18
N19
VCC(4)
M19
M17
I/O,
P154
P178
B19
B18
676 (3)
I/O
P119
P120
P121
P122
P123
N19
SGCK4(1)
GCK6(2)
(DOUT)
,
I/O
N20
VCC
I/O (D5(2)
I/O
VCC(4)
M17
M18
)
565 (3)
568 (3)
CCLK
VCC
P155
P156
P179
P180
A20
VCC(4)
A19
VCC(4)
-
-
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79
Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
Additional XCS40/XL Package Pins
XCS40 and XCS40XL Device Pinouts
XCS40/XL
Bndry
Pad Name PQ208 PQ240 BG256 CS280(2,5) Scan
PQ240
O, TDO
GND
I/O
P157
P158
P159
P160
P181
P182 GND(4)
A19
B17
GND(4)
A18
0
-
GND Pins
P22
P37
P83
-
P98
-
P143
-
P158
-
P183
P184
B18
B17
2
5
P204
P219
I/O,
PGCK4(1)
GCK7(2)
A17
,
Not Connected Pins
P195
-
-
-
-
-
I/O
P161
P162
P163
P164
-
P185
P186
P187
P188
-
C17
D16
A18
A17
-
D16
C16
B16
8
2/12/98
I/O
11
14
17
20
23
26
29
32
35
38
41
-
I/O (CS1(2)
I/O
)
A16
BG256
I/O
E15
VCC Pins
I/O
-
-
-
C15
D15
A15
C14
E20
K4
D6
F1
D7
D11
F17
P17
U7
-
D14
G4
P19
U10
-
D15
G17
R2
I/O
P165
-
P189
P190
P191
P192
P193
P194
C16
B16
A16
C15
B15
A15
F4
P4
I/O
I/O
P166
P167
P168
P169
P170
P171
P172
-
E14
L17
R17
V7
I/O
C14
B14
R4
U6
U14
-
I/O
U15
W20
I/O
D14
GND(4)
A14
GND
I/O
P196 GND(4)
GND Pins
P197
P198
P199
P200
P201
-
B14
A14
C13
B13
VCC(4)
A13
D12
C12
B12
A12
B11
C11
A11
A10
B10
44
47
50
53
-
A1
B7
H4
U8
D4
D8
N3
D13
N4
D17
N17
-
I/O
C13
B13
G20
H17
U13
I/O
U4
U17
W14
I/O
-
A13
VCC(4)
VCC
I/O
P173
-
6/17/97
A12
56
59
62
65
68
71
74
77
80
83
-
I/O
-
-
C12
B12
CS280
I/O
P174
P175
P176
P177
P178
P179
P180
P181
P182
P202
P203
P205
P206
P207
P208
P209
P210
VCC Pins
I/O
D12
A11
A1
D13
K17
U3
A7
E3
B5
B15
G1
R3
V5
C10
G19
R18
V15
C17
K2
I/O
E18
N16
U17
I/O
B11
M4
U10
T7
I/O
C11
D11
A10
I/O
W13
I/O
GND Pins
I/O
B10
GND(4)
E5
E7
G5
L5
R7
-
E8
G15
L15
R8
-
E9
H5
M5
R9
-
E11
H15
M15
R11
-
E12
J5
GND
2/8/00
P211 GND(4)
E13
J15
N15
N5
R12
-
Notes:
1. 5V Spartan family only
2. 3V Spartan-XL family only
3. The “PWRDWN” on the XCS40XL is not part of the Boundary
Scan chain. For the XCS40XL, subtract 1 from all Boundary
Scan numbers from GCK3 on (343 and higher).
4. Pads labeled GND(4) or VCC(4) are internally bonded to
Ground or VCC planes within the package.
R13
5/19/99
5. CS280 package discontinued by PDN2004-01
80
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R
Spartan and Spartan-XL FPGA Families Data Sheet
Product Availability
Table 19 shows the packages and speed grades for Spartan/XL devices. Table 20 shows the number of user I/Os available
for each device/package combination.
Table 19: Component Availability Chart for Spartan/XL FPGAs
Pins
84
100
144
144
208
240
256
280
Plastic
PLCC
Plastic
VQFP
Chip
Scale
Plastic
TQFP
Plastic
PQFP
Plastic
PQFP
Plastic
BGA
Chip
Scale
Type
Code
-3
(3)
(3)
(3)
(3)
(3)
Device
PC84
VQ100
C, I
C
CS144
TQ144
PQ208
PQ240
BG256
CS280
(3)
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
XCS05
(3)
-4
C
(3)
-3
C
C, I
C
C
C
C, I
C
C, I
C
-
-
-
XCS10
XCS20
(3)
-4
C
-
-
-3
-
-
-
-
-
-
C
C, I
C
-
-4
C
-
(3)
(3)
-3
C
C, I
C
C
C
C
C
-
C
XCS30
(3)
(3)
-4
C
C
-3
-
-
C, I
C
C
C
-
XCS40
-4
-
(3)
-4
C
C, I
C
-
-
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
(3)
-5
C
-
-
-
-
(3)
(3)
-4
C
C, I
C
C
C
C
C, I
C
C, I
C
-
-
-
-
(3)
(3)
-5
C
C
-
-
-
(3)
-4
-
-
-
-
-
-
C, I
C
C
C, I
C
-
-
(3)
-5
C
-
-
(3)
-4
C, I
C
-
-
-
-
C, I
C
C
C
C
C
C
C
C, I
C
C
(3)
-5
C
(3)
-4
-
C, I
C
C
(3)
-5
-
-
C
6/25/08
Notes:
1. C = Commercial TJ = 0° to +85°C
2. I = Industrial TJ = –40°C to +100°C
3. PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for XCS30 only, discontinued by PDN2004-01
4. Some Spartan-XL devices are available in Pb-free package options. The Pb-free packages insert a "G" in the package code. Contact
Xilinx for availability.
Package Specifications
Package drawings and material declaration data sheets for
the Spartan/XL devices can be found on the Xilinx website
at:
www.xilinx.com/support/documentation/spartan-xl.htm#19687
Thermal data for the Spartan/XL packages can be found
using the thermal query tool on the Xilinx website at:
www.xilinx.com/cgi-bin/thermal/thermal.pl
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Product Specification
Product Obsolete/Under Obsolescence
R
Spartan and Spartan-XL FPGA Families Data Sheet
Table 20: User I/O Chart for Spartan/XL FPGAs
Package Type
TQ144 PQ208
Max
I/O
(1)
(1)
(1)
(1)
(1)
Device
XCS05
PC84
VQ100
77
CS144
PQ240
BG256
CS280
(1)
80
61
61
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(1)
XCS10
112
160
192
224
80
77
112
113
113
-
-
-
XCS20
-
77
160
169
169
-
-
(1)
(1)
XCS30
-
-
77
192
192
XCS40
-
192
205
(1)
(2)
XCS05XL
XCS10XL
XCS20XL
XCS30XL
61
61
77
-
-
-
-
-
-
(1)
(2)
(1)
(2)
112
160
192
224
77
112
112
113
113
-
-
(2)
(1)
(2)
(2)
(2)
-
77
113
160
169
169
-
(2)
(2)
(2)
(2)
(2)
(2)
(1)
-
-
77
-
-
192
192
205
192
224
(2)
(1)
XCS40XL
6/25/08
-
192
Notes:
1. PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for XCS30 only, discontinued by PDN2004-01
2. These Spartan-XL devices are available in Pb-free package options. The Pb-free packages insert a "G" in the package code. Contact
Xilinx for availability.
Ordering Information
Example:
Device Type
Speed Grade
XCS20XL-4 PQ208C
Temperature Range
C = Commercial (T = 0° to +85°C)
J
I = Industrial (T = –40°C to +100°C)
J
-3
-4
-5
Number of Pins
Package Type
BG = Ball Grid Array
VQ = Very Thin Quad Flat Pack
VQG = Very Thin Quad Flat Pack (Pb-free)
TQ = Thin Quad Flat Pack
BGG = Ball Grid Array (Pb-free)
PC = Plastic Lead Chip Carrier
PQ = Plastic Quad Flat Pack
PQG = Plastic Quad Flat Pack (Pb-free)
TQG = Thin Quad Flat Pack (Pb-free)
CS = Chip Scale
82
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R
Spartan and Spartan-XL FPGA Families Data Sheet
Revision History
The following table shows the revision history for this document.
Date
Version
1.3
Description
Added Spartan-XL specs and Power Down.
11/20/98
01/06/99
03/02/00
09/19/01
1.4
All Spartan-XL -4 specs designated Preliminary with no changes.
Added CS package, updated Spartan-XL specs to Final.
1.5
1.6
Reformatted, updated power specs, clarified configuration information. Removed T
SOL
soldering information from Absolute Maximum Ratings table. Changed Figure 26: Slave
Serial Mode Characteristics: T , T from 45 to 40 ns. Changed Master Mode
CCH CCL
Configuration Switching Characteristics: T
min. from 80 to 100 ns. Added Total Dist.
CCLK
RAM Bits to Table 1; added Start-Up, page 36 characteristics.
06/27/02
06/26/08
1.7
1.8
Clarified Express Mode pseudo daisy chain. Added new Industrial options. Clarified
XCS30XL CS280 V pinout.
CC
Noted that PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for
XCS30 only, are discontinued by PDN2004-01. Extended description of recommended
maximum delay of reconfiguration in Delaying Configuration After Power-Up,
page 35. Added reference to Pb-free package options and provided link to Package
Specifications, page 81. Updated links.
03/01/13
2.0
The products listed in this data sheet are obsolete. See XCN10016 and XCN11010 for
further information.
DS060 (v2.0) March 1, 2013
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83
Product Specification
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