XCV150-4HQ240C_技术文档

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Virtex™ 2.5 V

Field Programmable Gate Arrays

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DS003-2 (v2.5) April 2, 2001

Product Specification

The output buffer and all of the IOB control signals have

independent polarity controls.

Architectural Description

Virtex Array

The Virtex user-programmable gate array, shown in

Figure 1, comprises two major configurable elements: con-

figurable logic blocks (CLBs) and input/output blocks

(IOBs).

DLL

IOBs

DLL

VersaRing

•

CLBs provide the functional elements for constructing

logic

•

IOBs provide the interface between the package pins

and the CLBs

CLBs

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a VersaBlock™ that also provides local

routing resources to connect the CLB to the GRM.

The VersaRing™ I/O interface provides additional routing

resources around the periphery of the device. This routing

improves I/O routability and facilitates pin locking.

VersaRing

IOBs

DLL

The Virtex architecture also includes the following circuits

that connect to the GRM.

vao_b.eps

•

Dedicated block memories of 4096 bits each

Figure 1: Virtex Architecture Overview

Clock DLLs for clock-distribution delay compensation

and clock domain control

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. Two

forms of over-voltage protection are provided, one that per-

mits 5 V compliance, and one that does not. For 5 V compli-

ance, a Zener-like structure connected to ground turns on

when the output rises to approximately 6.5 V. When PCI

3.3 V compliance is required, a conventional clamp diode is

•

3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing

resources

Values stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memory cells on power-up, and can reload if

necessary to change the function of the device.

connected to the output supply voltage, V_CCO

.

Input/Output Block

Optional pull-up and pull-down resistors and an optional

weak-keeper circuit are attached to each pad. Prior to con-

figuration, all pins not involved in configuration are forced

into their high-impedance state. The pull-down resistors and

the weak-keeper circuits are inactive, but inputs can option-

ally be pulled up.

The Virtex IOB, Figure 2, features SelectIO™ inputs and

outputs that support a wide variety of I/O signalling stan-

dards, see Table 1.

The three IOB storage elements function either as edge-trig-

gered D-type flip-flops or as level sensitive latches. Each

IOB has a clock signal (CLK) shared by the three flip-flops

and independent clock enable signals for each flip-flop.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins will float.

Consequently, external pull-up or pull-down resistors must

be provided on pins required to be at a well-defined logic

level prior to configuration.

In addition to the CLK and CE control signals, the three

flip-flops share a Set/Reset (SR). For each flip-flop, this sig-

nal can be independently configured as a synchronous Set,

a synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

All Virtex IOBs support IEEE 1149.1-compatible boundary

scan testing.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS003-2 (v2.5) April 2, 2001

Product Specification

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Module 2 of 4

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Virtex™ 2.5 V Field Programmable Gate Arrays

Q

D

CE

T

TCE

Weak

Keeper

SR

PAD

O

Q

D

CE

OBUFT

OCE

SR

I

Programmable

Delay

IQ

Q

D

CE

IBUF

Vref

SR

CLK

ICE

ds022_02_091300

Figure 2: Virtex Input/Output Block (IOB)

Table 1: Supported Select I/O Standards

Input Reference

Output Source

Board Termination

I/O Standard

Voltage (V_REF

)

Voltage (V_CCO

)

Voltage (V_TT

)

5 V Tolerant

LVTTL 2 – 24 mA

N/A

0.8

3.3

2.5

3.3

N/A

1.5

3.3

2.5

3.3

N/A

1.2

Yes

No

LVCMOS2

PCI, 5 V

PCI, 3.3 V

GTL

GTL+

1.0

1.5

HSTL Class I

HSTL Class III

HSTL Class IV

SSTL3 Class I &II

SSTL2 Class I & II

CTT

0.75

0.9

0.75

1.5

0.9

1.5

1.25

1.5

1.25

1.5

AGP

1.32

N/A

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DS003-2 (v2.5) April 2, 2001

Product Specification

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Virtex™ 2.5 V Field Programmable Gate Arrays

Eight I/O banks result from separating each edge of the

FPGA into two banks, as shown in Figure 3. Each bank has

multiple V_CCOpins, all of which must be connected to the

same voltage. This voltage is determined by the output

standards in use.

Input Path

A buffer In the Virtex IOB input path routes the input signal

either directly to internal logic or through an optional input

flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is zero.

Bank 0

Bank 1

GCLK3 GCLK2

Each input buffer can be configured to conform to any of the

low-voltage signalling standards supported. In some of

these standards the input buffer utilizes a user-supplied

threshold voltage, V_REF. The need to supply V_REFimposes

constraints on which standards can used in close proximity

to each other. See I/O Banking, page 3.

Virtex

Device

GCLK1 GCLK0

There are optional pull-up and pull-down resistors at each

input for use after configuration. Their value is in the range

50 k – 100 k .

Bank 5

Bank 4

X8778_b

Output Path

Figure 3: Virtex I/O Banks

The output path includes a 3-state output buffer that drives

the output signal onto the pad. The output signal can be

routed to the buffer directly from the internal logic or through

an optional IOB output flip-flop.

Within a bank, output standards can be mixed only if they

use the same V_CCO. Compatible standards are shown in

Table 2. GTL and GTL+ appear under all voltages because

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

their open-drain outputs do not depend on V_CCO

.

Table 2: Compatible Output Standards

V_CCOCompatible Standards

Each output driver can be individually programmed for a

wide range of low-voltage signalling standards. Each output

buffer can source up to 24 mA and sink up to 48mA. Drive

strength and slew rate controls minimize bus transients.

3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+

2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+

1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+

In most signalling standards, the output High voltage

depends on an externally supplied V_CCOvoltage. The need

to supply V_CCOimposes constraints on which standards

can be used in close proximity to each other. See I/O Bank-

ing, page 3.

Some input standards require a user-supplied threshold

voltage, V_REF. In this case, certain user-I/O pins are auto-

matically configured as inputs for the V_REFvoltage. Approx-

imately one in six of the I/O pins in the bank assume this

role.

An optional weak-keeper circuit is connected to each out-

put. When selected, the circuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way eliminates bus chatter.

The V_REFpins within a bank are interconnected internally

and consequently only one V_REFvoltage can be used within

each bank. All V_REFpins in the bank, however, must be con-

nected to the external voltage source for correct operation.

Because the weak-keeper circuit uses the IOB input buffer

to monitor the input level, an appropriate V_REFvoltage must

be provided if the signalling standard requires one. The pro-

vision of this voltage must comply with the I/O banking

rules.

Within a bank, inputs that require V_REFcan be mixed with

those that do not. However, only one V_REFvoltage can be

used within a bank. Input buffers that use V_REFare not 5 V

tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V

tolerant.

I/O Banking

The V_CCOand V_REFpins for each bank appear in the device

Pinout tables and diagrams. The diagrams also show the

bank affiliation of each I/O.

Some of the I/O standards described above require V_CCO

and/or V_REFvoltages. These voltages externally and con-

nected to device pins that serve groups of IOBs, called

banks. Consequently, restrictions exist about which I/O

standards can be combined within a given bank.

Within a given package, the number of V_REFand V_CCOpins

can vary depending on the size of device. In larger devices,

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Product Specification

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Module 2 of 4

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Virtex™ 2.5 V Field Programmable Gate Arrays

more I/O pins convert to V_REFpins. Since these are always

a superset of the V_REFpins used for smaller devices, it is

possible to design a PCB that permits migration to a larger

device if necessary. All the V_REFpins for the largest device

anticipated must be connected to the V_REFvoltage, and not

used for I/O.

of five or six inputs. Consequently, when estimating the

number of system gates provided by a given device, each

CLB counts as 4.5 LCs.

Look-Up Tables

Virtex function generators are implemented as 4-input

look-up tables (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16x1-bit dual-port synchronous RAM.

In smaller devices, some V_CCOpins used in larger devices

do not connect within the package. These unconnected pins

can be left unconnected externally, or can be connected to

the V_CCOvoltage to permit migration to a larger device if

necessary.

The Virtex LUT can also provide a 16-bit shift register that is

ideal for capturing high-speed or burst-mode data. This

mode can also be used to store data in applications such as

Digital Signal Processing.

In TQ144 and PQ/HQ240 packages, all V_CCOpins are

bonded together internally, and consequently the same

V_CCOvoltage must be connected to all of them. In the

CS144 package, bank pairs that share a side are intercon-

nected internally, permitting four choices for V_CCO. In both

cases, the V_REFpins remain internally connected as eight

banks, and can be used as described previously.

Storage Elements

The storage elements in the Virtex slice can be configured

either as edge-triggered D-type flip-flops or as level-sensi-

tive latches. The D inputs can be driven either by the func-

tion generators within the slice or directly from slice inputs,

bypassing the function generators.

Configurable Logic Block

The basic building block of the Virtex CLB is the logic cell

(LC). An LC includes a 4-input function generator, carry

logic, and a storage element. The output from the function

generator in each LC drives both the CLB output and the D

input of the flip-flop. Each Virtex CLB contains four LCs,

organized in two similar slices, as shown in Figure 4.

In addition to Clock and Clock Enable signals, each Slice

has synchronous set and reset signals (SR and BY). SR

forces a storage element into the initialization state speci-

fied for it in the configuration. BY forces it into the opposite

state. Alternatively, these signals can be configured to oper-

ate asynchronously. All of the control signals are indepen-

dently invertible, and are shared by the two flip-flops within

the slice.

Figure 5 shows a more detailed view of a single slice.

In addition to the four basic LCs, the Virtex CLB contains

logic that combines function generators to provide functions

COUT

YB

Y

YB

Y

G4

G3

G2

G4

SP

Q

SP

Q

G3

G2

G1

Carry &

Control

Carry &

Control

LUT

D

YQ

D

YQ

EC

G1

RC

BY

F4

BY

XB

X

XB

X

F4

F3

F2

F1

SP

Q

F3

F2

LUT

Carry &

Control

Carry &

Control

D

Q

XQ

D

XQ

EC

F1

RC

Slice 0

RC

Slice 1

BX

slice_b.eps

CIN

Figure 4: 2-Slice Virtex CLB

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DS003-2 (v2.5) April 2, 2001

Product Specification

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Virtex™ 2.5 V Field Programmable Gate Arrays

COUT

YB

CY

G4

G3

G2

G1

I3

I2

I1

I0

Y

O

LUT

INIT

D

Q

YQ

XB

DI

WE

EC

0

1

REV

BY

F5IN

F6

CY

F5

X

F5

BY DG

CK

WE

A4

WSO

WSH

BX

DI

INIT

D

EC

Q

XQ

BX

DI

WE

I3

I2

I1

I0

F4

F3

F2

F1

REV

O

LUT

0

1

SR

CLK

CE

CIN

viewslc4.eps

Figure 5: Detailed View of VIrtex Slice

Additional Logic

Block SelectRAM

The F5 multiplexer in each slice combines the function gen-

erator outputs. This combination provides either a function

generator that can implement any 5-input function, a 4:1

multiplexer, or selected functions of up to nine inputs.

Virtex FPGAs incorporate several large Block SelectRAM

memories. These complement the distributed LUT Selec-

tRAMs that provide shallow RAM structures implemented in

CLBs.

Similarly, the F6 multiplexer combines the outputs of all four

function generators in the CLB by selecting one of the

F5-multiplexer outputs. This permits the implementation of

any 6-input function, an 8:1 multiplexer, or selected func-

tions of up to 19 inputs.

Block SelectRAM memory blocks are organized in columns.

All Virtex devices contain two such columns, one along

each vertical edge. These columns extend the full height of

the chip. Each memory block is four CLBs high, and conse-

quently, a Virtex device 64 CLBs high contains 16 memory

blocks per column, and a total of 32 blocks.

Each CLB has four direct feedthrough paths, one per LC.

These paths provide extra data input lines or additional local

routing that does not consume logic resources.

Table 3 shows the amount of Block SelectRAM memory that

is available in each Virtex device.

Arithmetic Logic

Table 3: Virtex Block SelectRAM Amounts

Dedicated carry logic provides fast arithmetic carry capabil-

ity for high-speed arithmetic functions. The Virtex CLB sup-

ports two separate carry chains, one per Slice. The height

of the carry chains is two bits per CLB.

Device

XCV50

# of Blocks

Total Block SelectRAM Bits

8

32,768

40,960

49,152

57,344

65,536

81,920

98,304

114,688

131,072

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

10

12

14

16

20

24

28

32

The arithmetic logic includes an XOR gate that allows a

1-bit full adder to be implemented within an LC. In addition,

a dedicated AND gate improves the efficiency of multiplier

implementation.

The dedicated carry path can also be used to cascade func-

tion generators for implementing wide logic functions.

BUFTs

Each Virtex CLB contains two 3-state drivers (BUFTs) that

can drive on-chip busses. See Dedicated Routing, page 7.

Each Virtex BUFT has an independent 3-state control pin

and an independent input pin.

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Virtex™ 2.5 V Field Programmable Gate Arrays

Each Block SelectRAM cell, as illustrated in Figure 6, is a

fully synchronous dual-ported 4096-bit RAM with indepen-

dent control signals for each port. The data widths of the

two ports can be configured independently, providing

built-in bus-width conversion.

Table 4: Block SelectRAM Port Aspect Ratios

Width

Depth

4096

2048

1024

512

ADDR Bus

ADDR<11:0>

ADDR<10:0>

ADDR<9:0>

ADDR<8:0>

ADDR<7:0>

Data Bus

DATA<0>

1

2

DATA<1:0>

DATA<3:0>

DATA<7:0>

DATA<15:0>

4

RAMB4_S#_S#

8

WEA

ENA

16

256

DOA[#:0]

RSTA

CLKA

ADDRA[#:0]

DIA[#:0]

The Virtex Block SelectRAM also includes dedicated rout-

ing to provide an efficient interface with both CLBs and

other Block SelectRAMs.

WEB

ENB

RSTB

Programmable Routing Matrix

DOB[#:0]

It is the longest delay path that limits the speed of any

worst-case design. Consequently, the Virtex routing archi-

tecture and its place-and-route software were defined in a

single optimization process. This joint optimization mini-

mizes long-path delays, and consequently, yields the best

system performance.

CLKB

ADDRB[#:0]

DIB[#:0]

xcv_ds_006

Figure 6: Dual-Port Block SelectRAM

The joint optimization also reduces design compilation

times because the architecture is software-friendly. Design

cycles are correspondingly reduced due to shorter design

iteration times.

Table 4 shows the depth and width aspect ratios for the

Block SelectRAM.

To Adjacent

GRM

To Adjacent

GRM

To Adjacent

GRM

Direct Connection

To Adjacent

CLB

Direct Connection

To Adjacent

CLB

X8794b

Figure 7: Virtex Local Routing

•

Internal CLB feedback paths that provide high-speed

connections to LUTs within the same CLB, chaining

them together with minimal routing delay

Local Routing

The VersaBlock provides local routing resources, as shown

in Figure 7, providing the following three types of connec-

tions.

•

Direct paths that provide high-speed connections

between horizontally adjacent CLBs, eliminating the

delay of the GRM.

•

Interconnections among the LUTs, flip-flops, and GRM

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Virtex™ 2.5 V Field Programmable Gate Arrays

•

12 Longlines are buffered, bidirectional wires that

distribute signals across the device quickly and

efficiently. Vertical Longlines span the full height of the

device, and horizontal ones span the full width of the

device.

General Purpose Routing

Most Virtex signals are routed on the general purpose rout-

ing, and consequently, the majority of interconnect

resources are associated with this level of the routing hier-

archy. The general routing resources are located in horizon-

tal and vertical routing channels associated with the rows

and columns CLBs. The general-purpose routing resources

are listed below.

I/O Routing

Virtex devices have additional routing resources around

their periphery that form an interface between the CLB array

and the IOBs. This additional routing, called the VersaRing,

facilitates pin-swapping and pin-locking, such that logic

redesigns can adapt to existing PCB layouts. Time-to-mar-

ket is reduced, since PCBs and other system components

can be manufactured while the logic design is still in

progress.

•

Adjacent to each CLB is a General Routing Matrix

(GRM). The GRM is the switch matrix through which

horizontal and vertical routing resources connect, and

is also the means by which the CLB gains access to

the general purpose routing.

•

24 single-length lines route GRM signals to adjacent

GRMs in each of the four directions.

Dedicated Routing

72 buffered Hex lines route GRM signals to another

GRMs six-blocks away in each one of the four

directions. Organized in a staggered pattern, Hex lines

can be driven only at their endpoints. Hex-line signals

can be accessed either at the endpoints or at the

midpoint (three blocks from the source). One third of

the Hex lines are bidirectional, while the remaining

ones are uni-directional.

Some classes of signal require dedicated routing resources

to maximize performance. In the Virtex architecture, dedi-

cated routing resources are provided for two classes of sig-

nal.

•

Horizontal routing resources are provided for on-chip

3-state busses. Four partitionable bus lines are

provided per CLB row, permitting multiple busses

within a row, as shown in Figure 8.

•

Two dedicated nets per CLB propagate carry signals

vertically to the adjacent CLB.

Tri-State

Lines

CLB

buft_c.eps

Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines

•

The secondary local clock routing resources consist of

Global Routing

24 backbone lines, 12 across the top of the chip and 12

across bottom. From these lines, up to 12 unique

signals per column can be distributed via the 12

longlines in the column. These secondary resources

are more flexible than the primary resources since they

are not restricted to routing only to clock pins.

Global Routing resources distribute clocks and other sig-

nals with very high fanout throughout the device. Virtex

devices include two tiers of global routing resources

referred to as primary global and secondary local clock rout-

ing resources.

•

The primary global routing resources are four

Clock Distribution

dedicated global nets with dedicated input pins that are

designed to distribute high-fanout clock signals with

minimal skew. Each global clock net can drive all CLB,

IOB, and block RAM clock pins. The primary global

nets can only be driven by global buffers. There are

four global buffers, one for each global net.

Virtex provides high-speed, low-skew clock distribution

through the primary global routing resources described

above. A typical clock distribution net is shown in Figure 9.

Four global buffers are provided, two at the top center of the

device and two at the bottom center. These drive the four

primary global nets that in turn drive any clock pin.

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Virtex™ 2.5 V Field Programmable Gate Arrays

Four dedicated clock pads are provided, one adjacent to

each of the global buffers. The input to the global buffer is

selected either from these pads or from signals in the gen-

eral purpose routing.

GCLKPAD2

GCLKPAD3

GCLKBUF2

Global Clock Column

Global Clock Rows

GCLKBUF3

Global Clock Spine

GCLKBUF1

GCLKPAD1

GCLKBUF0

GCLKPAD0

gclkbu_2.eps

Figure 9: Global Clock Distribution Network

Delay-Locked Loop (DLL)

Boundary Scan

Associated with each global clock input buffer is a fully digi-

tal Delay-Locked Loop (DLL) that can eliminate skew

between the clock input pad and internal clock-input pins

throughout the device. Each DLL can drive two global clock

networks.The DLL monitors the input clock and the distrib-

uted clock, and automatically adjusts a clock delay element.

Clock edges reach internal flip-flops one to four clock peri-

ods after they arrive at the input. This closed-loop system

effectively eliminates clock-distribution delay by ensuring

that clock edges arrive at internal flip-flops in synchronism

with clock edges arriving at the input.

Virtex devices support all the mandatory boundary-scan

instructions specified in the IEEE standard 1149.1. A Test

Access Port (TAP) and registers are provided that imple-

ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions. The TAP

also supports two internal scan chains and configura-

tion/readback of the device.The TAP uses dedicated pack-

age pins that always operate using LVTTL. For TDO to

operate using LVTTL, the V_CCOfor Bank 2 should be 3.3 V.

Otherwise, TDO switches rail-to-rail between ground and

V_CCO

.

In addition to eliminating clock-distribution delay, the DLL

provides advanced control of multiple clock domains. The

DLL provides four quadrature phases of the source clock,

can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,

5, 8, or 16.

Boundary-scan operation is independent of individual IOB

configurations, and unaffected by package type. All IOBs,

including un-bonded ones, are treated as independent

3-state bidirectional pins in a single scan chain. Retention of

the bidirectional test capability after configuration facilitates

the testing of external interconnections.

The DLL also operates as a clock mirror. By driving the out-

put from a DLL off-chip and then back on again, the DLL can

be used to de-skew a board level clock among multiple Vir-

tex devices.

Table 5 lists the boundary-scan instructions supported in

Virtex FPGAs. Internal signals can be captured during

EXTEST by connecting them to un-bonded or unused IOBs.

They can also be connected to the unused outputs of IOBs

defined as unidirectional input pins.

In order to guarantee that the system clock is operating cor-

rectly prior to the FPGA starting up after configuration, the

DLL can delay the completion of the configuration process

until after it has achieved lock.

Before the device is configured, all instructions except

USER1 and USER2 are available. After configuration, all

instructions are available. During configuration, it is recom-

mended that those operations using the boundary-scan

register (SAMPLE/PRELOAD, INTEST, EXTEST) not be

performed.

See DLL Timing Parameters, page 21 of Module 3, for fre-

quency range information.

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Virtex™ 2.5 V Field Programmable Gate Arrays

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FPGA, and also to read back the configuration data.

The FPGA supports up to two additional internal scan

chains that can be specified using the BSCAN macro. The

macro provides two user pins (SEL1 and SEL2) which are

decodes of the USER1 and USER2 instructions respec-

tively. For these instructions, two corresponding pins (TDO1

and TDO2) allow user scan data to be shifted out of TDO.

Figure 10 is a diagram of the Virtex Series boundary scan

logic. It includes three bits of Data Register per IOB, the

IEEE 1149.1 Test Access Port controller, and the Instruction

Register with decodes.

Likewise, there are individual clock pins (DRCK1 and

DRCK2) for each user register. There is a common input pin

(TDI) and shared output pins that represent the state of the

TAP controller (RESET, SHIFT, and UPDATE).

Instruction Set

The Virtex Series boundary scan instruction set also

includes instructions to configure the device and read back

configuration data (CFG_IN, CFG_OUT, and JSTART). The

complete instruction set is coded as shown in Table 5.

Bit Sequence

The order within each IOB is: In, Out, 3-State. The

input-only pins contribute only the In bit to the boundary

scan I/O data register, while the output-only pins contributes

all three bits.

Data Registers

The primary data register is the boundary scan register. For

each IOB pin in the FPGA, bonded or not, it includes three

bits for In, Out, and 3-State Control. Non-IOB pins have

appropriate partial bit population if input-only or output-only.

Each EXTEST CAPTURED-OR state captures all In, Out,

and 3-state pins.

From a cavity-up view of the chip (as shown in EPIC), start-

ing in the upper right chip corner, the boundary scan

data-register bits are ordered as shown in Figure 11.

BSDL (Boundary Scan Description Language) files for Vir-

tex Series devices are available on the Xilinx web site in the

File Download area.

The other standard data register is the single flip-flop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

DATA IN

IOB.T

0

1

0

sd

1

D

Q

D

Q

LE

IOB

sd

1

0

D

Q

D

Q

LE

1

0

IOB.I

1

sd

D

Q

D

Q

0

LE

1

0

IOB.Q

IOB.T

BYPASS

REGISTER

0

1

M

U

X

TDO

1

sd

INSTRUCTION REGISTER

TDI

D

Q

D

Q

0

LE

1

sd

D

Q

D

Q

0

LE

1

0

IOB.I

DATAOUT

SHIFT/

CAPTURE

UPDATE

EXTEST

CLOCK DATA

REGISTER

X9016

Figure 10: Virtex Series Boundary Scan Logic

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Virtex™ 2.5 V Field Programmable Gate Arrays

Identification Registers

Right half of Top-edge IOBs (Right-to-Left)

Bit 0 ( TDO end)

Bit 1

Bit 2

The IDCODE register is supported. By using the IDCODE,

the device connected to the JTAG port can be determined.

GCLK2

GCLK3

Left half of Top-edge IOBs (Right-to-Left)

Left-edge IOBs (Top-to-Bottom)

The IDCODE register has the following binary format:

vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1

where

M1

M0

M2

v = the die version number

Left half of Bottom-edge IOBs (Left-to-Right)

f = the family code (03h for Virtex family)

GCLK1

GCLK0

a = the number of CLB rows (ranges from 010h for XCV50

to 040h for XCV1000)

Right half of Bottom-edge IOBs (Left-to-Right)

DONE

PROG

c = the company code (49h for Xilinx)

The USERCODE register is supported. By using the USER-

CODE, a user-programmable identification code can be

loaded and shifted out for examination. The identification

code is embedded in the bitstream during bitstream gener-

ation and is valid only after configuration.

Right-edge IOBs (Bottom -to-Top)

(TDI end)

CCLK

990602001

Figure 11: Boundary Scan Bit Sequence

Table 6: IDCODEs Assigned to Virtex FPGAs

Table 5: Boundary Scan Instructions

FPGA

XCV50

IDCODE

v0610093h

v0614093h

v0618093h

v061C093h

v0620093h

v0628093h

v0630093h

v0638093h

v0640093h

Boundary-Scan

Command

Binary

Code(4:0)

Description

EXTEST

00000

Enables boundary-scan

EXTEST operation

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

SAMPLE/PRELOAD

00001

Enables boundary-scan

SAMPLE/PRELOAD

operation

USER 1

USER 2

00010

00011

00100

00101

00111

01000

01001

01010

Access user-defined

register 1

Access user-defined

register 2

CFG_OUT

CFG_IN

Access the configuration

bus for read operations.

Access the configuration

bus for write operations.

Including Boundary Scan in a Design

Since the boundary scan pins are dedicated, no special ele-

ment needs to be added to the design unless an internal

data register (USER1 or USER2) is desired.

INTEST

Enables boundary-scan

INTEST operation

USERCODE

IDCODE

HIGHZ

Enables shifting out

USER code

If an internal data register is used, insert the boundary scan

symbol and connect the necessary pins as appropriate.

Enables shifting out of ID

Code

Development System

3-statesoutputpinswhile

enabling the Bypass

Register

Virtex FPGAs are supported by the Xilinx Foundation and

Alliance CAE tools. The basic methodology for Virtex design

consists of three interrelated steps: design entry, imple-

mentation, and verification. Industry-standard tools are

used for design entry and simulation (for example, Synop-

sys FPGA Express), while Xilinx provides proprietary archi-

tecture-specific tools for implementation.

JSTART

01100

11111

Clock the start-up

sequence when

StartupClk is TCK

BYPASS

Enables BYPASS

The Xilinx development system is integrated under the Xil-

inx Design Manager (XDM™) software, providing designers

RESERVED

All other

codes

Xilinx reserved

instructions

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Virtex™ 2.5 V Field Programmable Gate Arrays

with a common user interface regardless of their choice of

entry and verification tools. The XDM software simplifies the

selection of implementation options with pull-down menus

and on-line help.

Design Implementation

The place-and-route tools (PAR) automatically provide the

implementation flow described in this section. The parti-

tioner takes the EDIF net list for the design and maps the

logic into the architectural resources of the FPGA (CLBs

and IOBs, for example). The placer then determines the

best locations for these blocks based on their interconnec-

tions and the desired performance. Finally, the router inter-

connects the blocks.

Application programs ranging from schematic capture to

Placement and Routing (PAR) can be accessed through the

XDM software. The program command sequence is gener-

ated prior to execution, and stored for documentation.

Several advanced software features facilitate Virtex design.

RPMs, for example, are schematic-based macros with rela-

tive location constraints to guide their placement. They help

ensure optimal implementation of common functions.

The PAR algorithms support fully automatic implementation

of most designs. For demanding applications, however, the

user can exercise various degrees of control over the pro-

cess. User partitioning, placement, and routing information

is optionally specified during the design-entry process. The

implementation of highly structured designs can benefit

greatly from basic floor planning.

For HDL design entry, the Xilinx FPGA Foundation develop-

ment system provides interfaces to the following synthesis

design environments.

•

Synopsys (FPGA Compiler, FPGA Express)

Exemplar (Spectrum)

The implementation software incorporates Timing Wizard^®

timing-driven placement and routing. Designers specify tim-

ing requirements along entire paths during design entry.

The timing path analysis routines in PAR then recognize

these user-specified requirements and accommodate them.

Synplicity (Synplify)

For schematic design entry, the Xilinx FPGA Foundation

and alliance development system provides interfaces to the

following schematic-capture design environments.

Timing requirements are entered on a schematic in a form

directly relating to the system requirements, such as the tar-

geted clock frequency, or the maximum allowable delay

between two registers. In this way, the overall performance

of the system along entire signal paths is automatically tai-

lored to user-generated specifications. Specific timing infor-

mation for individual nets is unnecessary.

•

Mentor Graphics V8 (Design Architect, QuickSim II)

Viewlogic Systems (Viewdraw)

Third-party vendors support many other environments.

A standard interface-file specification, Electronic Design

Interchange Format (EDIF), simplifies file transfers into and

out of the development system.

Design Verification

Virtex FPGAs supported by a unified library of standard

functions. This library contains over 400 primitives and mac-

ros, ranging from 2-input AND gates to 16-bit accumulators,

and includes arithmetic functions, comparators, counters,

data registers, decoders, encoders, I/O functions, latches,

Boolean functions, multiplexers, shift registers, and barrel

shifters.

In addition to conventional software simulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

devices are infinitely reprogrammable, designs can be veri-

fied in real time without the need for extensive sets of soft-

ware simulation vectors.

The development system supports both software simulation

and in-circuit debugging techniques. For simulation, the

system extracts the post-layout timing information from the

design database, and back-annotates this information into

the net list for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

TRACE^®static timing analyzer.

The “soft macro” portion of the library contains detailed

descriptions of common logic functions, but does not con-

tain any partitioning or placement information. The perfor-

mance of these macros depends, therefore, on the

partitioning and placement obtained during implementation.

RPMs, on the other hand, do contain predetermined parti-

tioning and placement information that permits optimal

implementation of these functions. Users can create their

own library of soft macros or RPMs based on the macros

and primitives in the standard library.

For in-circuit debugging, the development system includes

a download and readback cable. This cable connects the

FPGA in the target system to a PC or workstation. After

downloading the design into the FPGA, the designer can

single-step the logic, readback the contents of the flip-flops,

and so observe the internal logic state. Simple modifica-

tions can be downloaded into the system in a matter of min-

utes.

The design environment supports hierarchical design entry,

with high-level schematics that comprise major functional

blocks, while lower-level schematics define the logic in

these blocks. These hierarchical design elements are auto-

matically combined by the implementation tools. Different

design entry tools can be combined within a hierarchical

design, thus allowing the most convenient entry method to

be used for each portion of the design.

Configuration

Virtex devices are configured by loading configuration data

into the internal configuration memory. Some of the pins

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Virtex™ 2.5 V Field Programmable Gate Arrays

used for this are dedicated configuration pins, while others

can be re-used as general purpose inputs and outputs once

configuration is complete.

Configuration Modes

Virtex supports the following four configuration modes.

•

Slave-serial mode

Master-serial mode

SelectMAP mode

Boundary-scan mode

The dedicated pins are the mode pins (M2, M1, M0), the

configuration clock pin (CCLK), the INIT pin, the DONE pin

and the boundary-scan pins (TDI, TDO, TMS, TCK).

Depending on the configuration mode chosen, CCLK can

be an output generated by the FPGA, or can be generated

externally, and provided to the FPGA as an input.

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Table 7.

Note that some configuration pins can act as outputs. For

correct operation, these pins can require a V_CCOof 3.3 V to

permit LVTTL operation. All the pins affected fall in banks 2

or 3.

Configuration through the boundary-scan port is always

available, independent of the mode selection. Selecting the

boundary-scan mode simply turns off the other modes. The

three mode pins have internal pull-up resistors, and default

to a logic High if left unconnected.

After Virtex devices are configured, unused IOBs function

as 3-state OBUFTs with weak pull downs. For a more

detailed description than that given below, see the

XAPP138, Virtex Configuration and Readback.

Table 7: Configuration Codes

Configuration Mode

Master-serial mode

Boundary-scan mode

SelectMAP mode

M2 M1 M0 CCLK Direction Data Width Serial D_out

Configuration Pull-ups

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Out

N/A

In

1

8

1

8

1

Yes

No

Slave-serial mode

Master-serial mode

Boundary-scan mode

SelectMAP mode

In

Yes

No

Out

N/A

In

Yes

No

Slave-serial mode

In

Yes

The change of DOUT on the rising edge of CCLK differs

from previous families, but will not cause a problem for

mixed configuration chains. This change was made to

improve serial-configuration rates for Virtex only chains.

Slave Serial Mode

In slave serial mode, the FPGA receives configuration data

in bit-serial form from a serial PROM or other source of

serial configuration data. The serial bitstream must be setup

at the DIN input pin a short time before each rising edge of

an externally generated CCLK.

Figure 12 shows a full master/slave system. A Virtex device

in slave serial mode should be connected as shown in the

third device from the left

For more information on serial PROMs, see the PROM data

Slave-serial mode is selected by applying <111> or <011>

to the mode pins (M2, M1, M0). A weak pull-up on the mode

pins makes slave serial the default mode if the pins are left

unconnected. Figure 13 shows slave-serial configuration

timing.

sheet at http://www.xilinx.com/partinfo/ds026.pdf.

Multiple FPGAs can be daisy-chained for configuration from

a single source. After a particular FPGA has been config-

ured, the data for the next device is routed to the DOUT pin.

The data on the DOUT pin changes on the rising edge of

CCLK.

Table 8 provides more detail about the characteristics

shown in Figure 13. Configuration must be delayed until the

INIT pins of all daisy-chained FPGAs are High.

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Virtex™ 2.5 V Field Programmable Gate Arrays

Table 8: Master/Slave Serial Mode Programming Switching

Description

DIN setup/hold, slave mode

DIN setup/hold, master mode

DOUT

Symbol

T_DCC/T_CCD

_DSCK/T_SCKD

T_CCO

Units

ns, min

ns, max

ns, min

MHz, max

1/2

3

5.0 / 0

12.0

5.0

T

High time

CCLK

4

T_CCH

Low time

5

T_CCL

5.0

Maximum Frequency

F_CC

66

Frequency Tolerance, master mode with

respect to nominal

+45%

–30%

V

3.3V

CC

M0 M1

4.7 K

M0 M1

M2

DOUT

DIN

DOUT

CCLK

VIRTEX

MASTER

SERIAL

VIRTEX,

XC4000XL,

XC1701L

CCLK

CLK

SLAVE

DATA

DIN

Optional Pull-up

1

CE

CEO

PROGRAM

DONE

PROGRAM

DONE

Resistor on Done

RESET/OE

INIT

(Low Reset Option Used)

PROGRAM

Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 Ω should be added to the common DONE line.

xcv_12_091499

Figure 12: Master/Slave Serial Mode Circuit Diagram

DIN

1

2

5

T

DCC

CCD

CCL

CCLK

4

T

CCH

3

T

CCO

DOUT

(Output)

X5379_a

Figure 13: Slave Serial Mode Programming Switching Characteristics

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Virtex™ 2.5 V Field Programmable Gate Arrays

At power-up, V_CCmust rise from 1.0 V to V_CCmin in less

than 50 ms, otherwise delay configuration by pulling PRO-

GRAM Low until V_CCis valid.

Master Serial Mode

In master serial mode, the CCLK output of the FPGA drives

a Xilinx Serial PROM that feeds bit-serial data to the DIN

input. The FPGA accepts this data on each rising CCLK

edge. After the FPGA has been loaded, the data for the next

device in a daisy-chain is presented on the DOUT pin after

the rising CCLK edge.

The sequence of operations necessary to configure a Virtex

FPGA serially appears in Figure 14.

SelectMAP Mode

The SelectMAP mode is the fastest configuration option.

Byte-wide data is written into the FPGA with a BUSY flag

controlling the flow of data.

The interface is identical to slave serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK which always starts at a slow default frequency. Con-

figuration bits then switch CCLK to a higher frequency for

the remainder of the configuration. Switching to a lower fre-

quency is prohibited.

An external data source provides a byte stream, CCLK, a

Chip Select (CS) signal and a Write signal (WRITE). If

BUSY is asserted (High) by the FPGA, the data must be

held until BUSY goes Low.

Data can also be read using the SelectMAP mode. If

WRITE is not asserted, configuration data is read out of the

FPGA as part of a readback operation.

The CCLK frequency is set using the ConfigRate option in

the bitstream generation software. The maximum CCLK fre-

quency that can be selected is 60 MHz. When selecting a

CCLK frequency, ensure that the serial PROM and any

daisy-chained FPGAs are fast enough to support the clock

rate.

In the SelectMAP mode, multiple Virtex devices can be

chained in parallel. DATA pins (D7:D0), CCLK, WRITE,

BUSY, PROG, DONE, and INIT can be connected in parallel

between all the FPGAs. Note that the data is organized with

the MSB of each byte on pin DO and the LSB of each byte

on D7. The CS pins are kept separate, insuring that each

FPGA can be selected individually. WRITE should be Low

before loading the first bitstream and returned High after the

last device has been programmed. Use CS to select the

appropriate FPGA for loading the bitstream and sending the

configuration data. at the end of the bitstream, deselect the

loaded device and select the next target FPGA by setting its

CS pin High. A free-running oscillator or other externally

generated signal can be used for CCLK. The BUSY signal

can be ignored for frequencies below 50 MHz. For details

about frequencies above 50 MHz, see XAPP138, Virtex

Configuration and Readback. Once all the devices have

been programmed, the DONE pin goes High.

On power-up, the CCLK frequency is 2.5 MHz. This fre-

quency is used until the ConfigRate bits have been loaded

when the frequency changes to the selected ConfigRate.

Unless a different frequency is specified in the design, the

default ConfigRate is 4 MHz.

Figure 12 shows a full master/slave system. In this system,

the left-most device operates in master-serial mode. The

remaining devices operate in slave-serial mode. The

SPROM RESET pin is driven by INIT, and the CE input is

driven by DONE. There is the potential for contention on the

DONE pin, depending on the start-up sequence options

chosen.

Figure 13 shows the timing of master-serial configuration.

Master serial mode is selected by a <000> or <100> on the

mode pins (M2, M1, M0). Table 8 shows the timing informa-

tion for Figure 13.

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Virtex™ 2.5 V Field Programmable Gate Arrays

Apply Power

FPGA starts to clear

configuration memory.

Set PROGRAM = High

Release INIT

FPGA makes a final

clearing pass and releases

INIT when finished.

If used to delay

configuration

Low

INIT?

High

Load a Configuration Bit

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

No

End of

Bitstream?

If no CRC errors found,

FPGA enters start-up phase

causing DONE to go High.

Yes

Configuration Completed

ds003_154_111799

Figure 14: Serial Configuration Flowchart

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained to permit high-speed 8-bit readback.

Multiple Virtex FPGAs can be configured using the Select-

MAP mode, and be made to start-up simultaneously. To

configure multiple devices in this way, wire the individual

CCLK, Data, WRITE, and BUSY pins of all the devices in

parallel. The individual devices are loaded separately by

asserting the CS pin of each device in turn and writing the

appropriate data. ^See Table 9 for SelectMAP Write Timing

Retention of the SelectMAP port is selectable on a

design-by-design basis when the bitstream is generated. If

retention is selected, PROHIBIT constraints are required to

prevent the SelectMAP-port pins from being used as user

I/O.

Characteristics.

.

Table 9: SelectMAP Write Timing Characteristics

Description

Symbol

T_SMDCC/T_SMCCD

T_SMCSCC/T_SMCCCS

T_SMCCW/T_SMWCC

T_SMCKBY

Units

ns, min

D

_0-7Setup/Hold

1/2

3/4

5/6

7

5.0 / 1.7

7.0 / 1.7

12.0

CS Setup/Hold

ns, min

WRITE Setup/Hold

ns, min

CCLK

BUSY Propagation Delay

Maximum Frequency

ns, max

MHz, max

F_CC

66

Maximum Frequency with no handshake

F_CCNH

50

1. Assert WRITE and CS Low. Note that when CS is

asserted on successive CCLKs, WRITE must remain

either asserted or de-asserted. Otherwise an abort will

be initiated, as described below.

Write

Write operations send packets of configuration data into the

FPGA. The sequence of operations for a multi-cycle write

operation is shown below. Note that a configuration packet

can be split into many such sequences. The packet does

not have to complete within one assertion of CS, illustrated

in Figure 15.

2. Drive data onto D[7:0]. Note that to avoid contention,

the data source should not be enabled while CS is Low

and WRITE is High. Similarly, while WRITE is High, no

more that one CS should be asserted.

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Virtex™ 2.5 V Field Programmable Gate Arrays

3. At the rising edge of CCLK: If BUSY is Low, the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance will instead

occur on the first clock after BUSY goes Low, and the

data must be held until this has happened.

5. De-assert CS and WRITE.

A flowchart for the write operation appears in Figure 16.

Note that if CCLK is slower than f_CCNH, the FPGA will never

assert BUSY, In this case, the above handshake is unnec-

essary, and data can simply be entered into the FPGA every

CCLK cycle.

4. Repeat steps 2 and 3 until all the data has been sent.

CCLK

3

4

6

CS

5

WRITE

1

2

DATA[7:0]

7

BUSY

Write

No Write

Write

ds003_16_102199

Figure 15: Write Operations

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Virtex™ 2.5 V Field Programmable Gate Arrays

Apply Power

FPGA starts to clear

configuration memory.

Set PROGRAM = High

Release INIT

FPGA makes a final

clearing pass and releases

INIT when finished.

If used to delay

configuration

Low

INIT?

High

Set WRITE = Low

Enter Data Source

Set CS = Low

Sequence A

On first FPGA

Apply Configuration Byte

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

High

Busy?

Low

No

End of Data?

Yes

If no errors,

first FPGAs enter start-up phase

releasing DONE.

On first FPGA

Set CS = High

If no errors,

later FPGAs enter start-up phase

releasing DONE.

For any other FPGAs

Repeat Sequence A

Disable Data Source

Set WRITE = High

When all DONE pins

are released, DONE goes High

and start-up sequences complete.

Configuration Completed

ds003_17_111799

Figure 16: SelectMAP Flowchart for Write Operation

aries, and the FPGA requires a new synchronization word

prior to accepting any new packets.

Abort

During a given assertion of CS, the user cannot switch from

a write to a read, or vice-versa. This action causes the cur-

rent packet command to be aborted. The device will remain

BUSY until the aborted operation has completed. Following

an abort, data is assumed to be unaligned to word bound-

To initiate an abort during a write operation, de-assert

WRITE. At the rising edge of CCLK, an abort is initiated, as

shown in Figure 17.

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Virtex™ 2.5 V Field Programmable Gate Arrays

The power-up timing of configuration signals is shown in

Figure 18. The corresponding timing characteristics are

listed in Table 10. .

CCLK

Vcc

PROGRAM

INIT

T

POR

CS

WRITE

T

PI

DATA[7:0]

BUSY

T

ICCK

CCLK OUTPUT or INPUT

Abort

X8797_c

M0, M1, M2

(Required)

VALID

Figure 17: SelectMAP Write Abort Waveforms

98122302

Boundary-Scan Mode

In the boundary-scan mode, no non-dedicated pins are

required, configuration being done entirely through the

IEEE 1149.1 Test Access Port.

Figure 18: Power-Up Timing Configuration Signals

Table 10: Power-up Timing Characteristics

Configuration through the TAP uses the CFG_IN instruc-

tion. This instruction allows data input on TDI to be con-

verted into data packets for the internal configuration bus.

Description

Power-on Reset

Symbol

T_POR

T_PL

Value

2.0

Units

ms, max

s, max

s, min

The following steps are required to configure the FPGA

through the boundary-scan port (when using TCK as a

start-up clock).

Program Latency

CCLK (output) Delay

100.0

0.5

T_ICCK

4.0

s, max

ns, min

1. Load the CFG_IN instruction into the boundary-scan

instruction register (IR)

Program Pulse Width

T_PROGRAM

300

2. Enter the Shift-DR (SDR) state

3. Shift a configuration bitstream into TDI

4. Return to Run-Test-Idle (RTI)

5. Load the JSTART instruction into IR

6. Enter the SDR state

Delaying Configuration

INIT can be held Low using an open-drain driver. An

open-drain is required since INIT is a bidirectional

open-drain pin that is held Low by the FPGA while the con-

figuration memory is being cleared. Extending the time that

the pin is Low causes the configuration sequencer to wait.

Thus, configuration is delayed by preventing entry into the

phase where data is loaded.

7. Clock TCK through the startup sequence

8. Return to RTI

Configuration and readback via the TAP is always available.

The boundary-scan mode is selected by a <101> or 001>

on the mode pins (M2, M1, M0).

Start-Up Sequence

The default Start-up sequence is that one CCLK cycle after

DONE goes High, the global 3-state signal (GTS) is released.

This permits device outputs to turn on as necessary.

Configuration Sequence

The configuration of Virtex devices is a three-phase pro-

cess. First, the configuration memory is cleared. Next, con-

figuration data is loaded into the memory, and finally, the

logic is activated by a start-up process.

One CCLK cycle later, the Global Set/Reset (GSR) and Glo-

bal Write Enable (GWE) signals are released. This permits

the internal storage elements to begin changing state in

response to the logic and the user clock.

Configuration is automatically initiated on power-up unless

it is delayed by the user, as described below. The configura-

tion process can also be initiated by asserting PROGRAM.

The end of the memory-clearing phase is signalled by INIT

going High, and the completion of the entire process is sig-

nalled by DONE going High.

The relative timing of these events can be changed. In addi-

tion, the GTS, GSR, and GWE events can be made depen-

dent on the DONE pins of multiple devices all going High,

forcing the devices to start in synchronism. The sequence

can also be paused at any stage until lock has been

achieved on any or all DLLs.

Module 2 of 4

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Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Data Stream Format

Readback

Virtex devices are configured by sequentially loading

frames of data. Table 11 lists the total number of bits

required to configure each device. For more detailed infor-

mation, see application note XAPP151 “Virtex Configura-

tion Architecture Advanced Users Guide”.

The configuration data stored in the Virtex configuration

memory can be readback for verification. Along with the

configuration data it is possible to readback the contents all

flip-flops/latches, LUTRAMs, and block RAMs. This capabil-

ity is used for real-time debugging.

For more detailed information, see application note

XAPP138, Virtex FPGA Series Configuration and Read-

back.

Table 11: Virtex Bit-Stream Lengths

Device

XCV50

# of Configuration Bits

559,200

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

781,216

1,040,096

1,335,840

1,751,808

2,546,048

3,607,968

4,715,616

6,127,744

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Module 2 of 4

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Virtex™ 2.5 V Field Programmable Gate Arrays

Revision History

Date

11/98

01/99

02/99

05/99

07/99

Version

1.0

Revision

Initial Xilinx release.

1.2

Updated package drawings and specs.

1.3

Update of package drawings, updated specifications.

Addition of package drawings and specifications.

Replaced FG 676 & FG680 package drawings.

1.4

1.5

1.6

Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit

Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O

Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and

new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and

Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.

Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated

IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.

Added IOB Input Switching Characteristics Standard Adjustments.

09/99

1.7

Speed grade update to preliminary status, Power-on specification and Clock-to-Out

Minimums additions, “0” hold time listing explanation, quiescent current listing update, and

Figure 6 ADDRA input label correction. Added T_IJITCCparameter, changed T_OJITto

T_OPHASE

.

01/00

03/00

1.8

1.9

2.0

Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,

117153, 117154, and 117612. Modified notes for Recommended Operating Conditions

(voltage and temperature). Changed Bank information for V_CCOin CS144 package on p.43.

Updated DLL Jitter Parameter table and waveforms, added Delay Measurement

Methodology table for different I/O standards, changed buffered Hex line info and

Input/Output Timing measurement notes.

New TBCKO values; corrected FG680 package connection drawing; new note about status

of CCLK pin after configuration.

05/00

09/00

2.1

2.2

2.3

Modified “Pins not listed ...” statement. Speed grade update to Final status.

Modified Table 18.

•

Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.

Corrected Units column in table under IOB Input Switching Characteristics.

Added values to table under CLB SelectRAM Switching Characteristics.

•

Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in

Table 18.

10/00

04/01

2.4

2.5

•

Corrected BG256 Pin Function Diagram.

Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.

Updated SelectMAP Write Timing Characteristics values in Table 9.

Converted file to modularized format. See the Virtex Data Sheet section.

Virtex Data Sheet

The Virtex Data Sheet contains the following modules:

•

DS003-1, Virtex 2.5V FPGAs:

Introduction and Ordering Information (Module 1)

•

DS003-3, Virtex 2.5V FPGAs:

DC and Switching Characteristics (Module 3)

•

DS003-2, Virtex 2.5V FPGAs:

Functional Description (Module 2)

DS003-4, Virtex 2.5V FPGAs:

Pinout Tables (Module 4)

Module 2 of 4

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Product Specification

0

R

Virtex™ 2.5 V

Field Programmable Gate Arrays

0

3

DS003-3 (v2.5) April 2, 2001

Product Specification

Virtex Electrical Characteristics

Definition of Terms

Data sheets can be designated as Advance or Preliminary. The status of specifications in these data sheets is as follows:

Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values

are subject to change. Use as estimates, not for production.

Preliminary: Based on preliminary characterization. Further changes are not expected.

Unmarked: Data sheets not identified as either Advance or Preliminary are to be considered final.

All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters

included are common to popular designs and typical applications. Contact the factory for design considerations requiring

more detailed information.

All specifications are subject to change without notice.

Virtex DC Characteristics

Absolute Maximum Ratings⁽¹⁾

Symbol

V_CCINT

V_CCO

Description

Supply voltage relative to GND⁽²⁾

Units

V

–0.5 to 3.0

–0.5 to 4.0

–0.5 to 3.6

–0.5 to 5.5

50

Supply voltage relative to GND⁽²⁾

Input Reference Voltage

V

V_REF

V

Input voltage relative to GND⁽³⁾

Using V_REF

V

V_IN

Internal threshold

V

Voltage applied to 3-state output

V_TS

V_CC

T_STG

T_SOL

T_J

V

Longest Supply Voltage Rise Time from 1V-2.375V

Storage temperature (ambient)

ms

C

–65 to +150

+260

Maximum soldering temp. (10s @ 1/16 in. = 1.5 mm)

Junction temperature

C

Plastic Packages

+125

C

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.

2. Power supplies can turn on in any order.

3. For protracted periods (e.g., longer than a day), V_INshould not exceed V_CCOby more than 3.6 V.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Product Specification

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Module 3 of 4

1

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Virtex™ 2.5 V Field Programmable Gate Arrays

Recommended Operating Conditions

Symbol

Description

Input Supply voltage relative to GND, T_J= 0 C to +85 C

Input Supply voltage relative to GND, T_J= –40 C to +100 C Industrial

Min

2.5 – 5%

1.4

Max

2.5 + 5%

3.6

Units

V

Commercial

(1)

V_CCINT

V

Supply voltage relative to GND, T_J= 0 C to +85 C

Supply voltage relative to GND, T_J= –40 C to +100 C

Input signal transition time

Commercial

Industrial

V

(4)

V_CCO

1.4

3.6

V

T_IN

250

ns

Notes:

1. Correct operation is guaranteed with a minimum V_CCINTof 2.375 V (Nominal V_CCINT–5%). Below the minimum value, all delay

parameters increase by 3% for each 50-mV reduction in V_CCINTbelow the specified range.

2. At junction temperatures above those listed as Operating Conditions, delay parameters do increase. Please refer to the TRCE report.

3. Input and output measurement threshold is ~50% of V_CC

4. Min and Max values for V_CCOare I/O Standard dependant.

.

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Virtex™ 2.5 V Field Programmable Gate Arrays

DC Characteristics Over Recommended Operating Conditions

Symbol

Description

Data Retention V_CCINTVoltage

Device

Min

Max

Units

V_DRINT

All

2.0

V

(below which configuration data can be lost)

Data Retention V_CCOVoltage

V_DRIO

All

1.2

V

(below which configuration data can be lost)

I_CCINTQQuiescent V_CCINTsupply current^(1,3)

XCV50

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

XCV50

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

All

50

75

100

2

mA

A

I_CCOQ

Quiescent V_CCOsupply current⁽¹⁾

2

I_REF

I_L

C_IN

I_RPU

V_REFcurrent per V_REFpin

20

+10

8

Input or output leakage current

Input capacitance (sample tested)

All

–10

A

BGA, PQ, HQ, packages

All

pF

Pad pull-up (when selected) @ V_in= 0 V, V_CCO= 3.3 V (sample

tested)

All

Note (2)

0.25

0.15

mA

I_RPD

Pad pull-down (when selected) @ V_in= 3.6 V (sample tested)

Notes:

1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.

2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors

do not guarantee valid logic levels when input pins are connected to other circuits.

3. Multiply I_CCINTQlimit by two for industrial grade.

DS003-3 (v2.5) April 2, 2001

Product Specification

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Module 3 of 4

3

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Virtex™ 2.5 V Field Programmable Gate Arrays

Power-On Power Supply Requirements

Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual

current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal

power supply voltage of the device⁽¹⁾from 0 V. The current is highest at the fastest suggested ramp rate (0 V to nominal

voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 V to nominal voltage in 50 ms).

Product

Virtex Family, Commercial Grade

Virtex Family, Industrial Grade

Notes:

Description⁽²⁾

Current Requirement^(1,3)

Minimum required current supply

500 mA

2 A

1. Ramp rate used for this specification is from 0 - 2.7 VDC. Peak current occurs on or near the internal power-on reset threshold and

lasts for less than 3 ms.

2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.

3. Larger currents can result if ramp rates are forced to be faster.

DC Input and Output levels

Values for V_ILand V_IHare recommended input voltages. Values for I_OLand I_OHare guaranteed output currents over the

recommended operating conditions at the V_OLand V_OHtest points. Only selected standards are tested. These are chosen

to ensure that all standards meet their specifications. The selected standards are tested at minimum V_CCOfor each standard

with the respective V_OLand V_OHvoltage levels shown. Other standards are sample tested.

V_IL

V, max

V_IH

V_OL

V, Max

0.4

V_OH

V, Min

I_OL

mA

24

I_OH

mA

Input/Output

Standard

V, min

– 0.5

V, min

2.0

V, max

5.5

LVTTL⁽¹⁾

LVCMOS2

PCI, 3.3 V

PCI, 5.0 V

GTL

0.8

.7

2.4

–24

1.7

5.5

0.4

1.9

12

–12

Note (2)

40

Note (2)

n/a

44% V_CCINT60% V_CCINTV_CCO+ 0.5 10% V_CCO

90% V_CCO

2.4

0.8

2.0

5.5

3.6

0.55

0.4

V_REF– 0.05 V_REF+ 0.05

n/a

GTL+

V

_REF– 0.1

_REF– 0.2

V_REF+ 0.1

V_REF+ 0.2

0.6

n/a

36

n/a

HSTL I

0.4

V_CCO– 0.4

V_REF+ 0.6

V_REF+ 0.8

8

–8

HSTL III

HSTL IV

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

CTT

0.4

24

–8

0.4

48

–8

V_REF– 0.6

V_REF– 0.8

8

–8

16

–16

V_REF– 0.61 V_REF+ 0.61

V_REF– 0.80 V_REF+ 0.80

7.6

–7.6

–15.2

–8

15.2

8

V_REF– 0.4

10% V_CCO

V_REF+ 0.4

90% V_CCO

Note (2)

AGP

Notes:

1. V_OLand V_OHfor lower drive currents are sample tested.

2. Tested according to the relevant specifications.

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Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Virtex Switching Characteristics

Testing of switching parameters is modeled after testing

methods specified by MIL-M-38510/605. All devices are

100% functionally tested. Internal timing parameters are

derived from measuring internal test patterns. Listed below

are representative values. For more specific, more precise,

and worst-case guaranteed data, use the values reported

by the static timing analyzer (TRCE in the Xilinx Develop-

ment System) and back-annotated to the simulation net list.

All timing parameters assume worst-case operating condi-

tions (supply voltage and junction temperature). Values

apply to all Virtex devices unless otherwise noted.

IOB Input Switching Characteristics

Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values

shown in IOB Input Switching Characteristics Standard Adjustments, page 7.

Speed Grade

Description

Propagation Delays

Device

Symbol

Min

-6

-5

-4

Units

Pad to I output, no delay

Pad to I output, with delay

All

T_IOPI

0.39

0.8

0.9

1.1

0.8

1.5

1.8

2.1

1.6

0.9

1.7

2.0

2.4

1.8

1.0

1.9

2.3

2.7

2.0

ns, max

XCV50

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

All

T_IOPID

Pad to output IQ via transparent

latch, no delay

T_IOPLI

Pad to output IQ via transparent

latch, with delay

XCV50

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

T_IOPLID

1.9

2.0

2.1

2.2

2.3

3.7

3.9

4.0

4.1

4.2

4.4

4.5

4.2

4.3

4.4

4.6

4.7

4.9

5.1

4.8

4.9

5.1

5.3

5.4

5.6

5.8

ns, max

Sequential Delays

Clock CLK to output IQ

All

T_IOCKIQ

0.2

0.7

0.8

ns, max

ns, min

Setup and Hold Times with respect to Clock CLK at IOB input

register⁽¹⁾

Setup Time / Hold Time

Pad, no delay

All

T_IOPICK/T_IOICKP

0.8 / 0

1.6 / 0 1.8 / 0 2.0 / 0

DS003-3 (v2.5) April 2, 2001

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Module 3 of 4

5

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Virtex™ 2.5 V Field Programmable Gate Arrays

Speed Grade

Description

Pad, with delay

Device

XCV50

Symbol

Min

-6

-5

-4

Units

ns, min

ns, max

T_IOPICKD/T_IOICKPD

1.9 / 0

2.0 / 0

2.1 / 0

2.2 / 0

2.3 / 0

0.37/ 0

3.7 / 0

3.8 / 0

3.9 / 0

4.1 / 0

4.2 / 0

4.4 / 0

4.5 / 0

0.8 / 0

4.1 / 0

4.3 / 0

4.4 / 0

4.6 / 0

4.7 / 0

4.9 / 0

5.0 / 0

0.9 / 0

4.7 / 0

4.9 / 0

5.0 / 0

5.3 / 0

5.4 / 0

5.6 / 0

5.8 / 0

1.0 / 0

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

All

ICE input

T

_IOICECK/T_IOCKICE

Set/Reset Delays

SR input (IFF, synchronous)

SR input to IQ (asynchronous)

GSR to output IQ

Notes:

All

T_IOSRCKI

T_IOSRIQ

T_GSRQ

0.49

0.70

4.9

1.0

1.4

9.7

1.1

1.6

1.3

1.8

ns, max

10.9

12.5

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

2. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 2.

Module 3 of 4

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Virtex™ 2.5 V Field Programmable Gate Arrays

IOB Input Switching Characteristics Standard Adjustments

Speed Grade

Description

Symbol

Standard⁽¹⁾

Min

-6

-5

-4

Units

Data Input Delay Adjustments

Standard-specific data input delay

adjustments

T_ILVTTL

T_ILVCMOS2

T_{IPCI33_3}

T_{IPCI33_5}

T_{IPCI66_3}

T_IGTL

LVTTL

LVCMOS2

PCI, 33 MHz, 3.3 V

PCI, 33 MHz, 5.0 V

PCI, 66 MHz, 3.3 V

GTL

0

ns

–0.02

–0.05

0.13

–0.04

–0.11

0.25

–0.04

–0.12

0.28

–0.05

–0.14

0.33

–0.05

0.10

–0.11

0.20

–0.12

0.23

–0.14

0.26

T_IGTLP

GTL+

0.06

0.11

0.12

0.14

T_IHSTL

HSTL

0.02

0.03

0.04

T_ISSTL2

T_ISSTL3

T_ICTT

SSTL2

–0.04

–0.02

0.01

–0.08

–0.04

0.02

–0.09

–0.05

0.02

–0.10

–0.06

0.02

SSTL3

CTT

T_IAGP

AGP

–0.03

–0.06

–0.07

–0.08

Notes:

1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 2.

IOB Output Switching Characteristics

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 9.

Speed Grade

Description

Propagation Delays

Symbol

Min

-6

-5

-4

Units

O input to Pad

T_IOOP

1.2

1.4

2.9

3.4

3.2

3.7

3.5

4.0

ns, max

O input to Pad via transparent latch

3-State Delays

T_IOOLP

T input to Pad high-impedance⁽¹⁾

T input to valid data on Pad

T_IOTHZ

T_IOTON

1.0

1.4

2.0

3.1

2.2

3.3

2.4

3.7

ns, max

T input to Pad high-impedance via

transparent latch⁽¹⁾

T_IOTLPHZ

1.2

2.4

2.6

3.0

ns, max

T input to valid data on Pad via

transparent latch

T_IOTLPON

T_GTS

1.6

2.5

3.5

4.9

3.8

5.5

4.2

6.3

ns, max

GTS to Pad high impedance⁽¹⁾

Sequential Delays

Clock CLK to Pad

T_IOCKP

1.0

1.1

2.9

2.3

3.2

2.5

3.5

2.9

ns, max

Clock CLK to Pad high-impedance

(synchronous)⁽¹⁾

T_IOCKHZ

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Virtex™ 2.5 V Field Programmable Gate Arrays

Speed Grade

Description

Symbol

Min

-6

-5

-4

Units

Clock CLK to valid data on Pad

(synchronous)

T_IOCKON

1.5

3.4

3.7

4.1

ns, max

Setup and Hold Times before/after Clock CLK⁽²⁾

Setup Time / Hold Time

O input

T

_IOOCK/T_IOCKO

0.51 / 0

1.1 / 0

1.2 / 0

0.9 / 0

1.2 / 0

0.8 / 0

0.9 / 0

1.1 / 0

1.3 / 0

ns, min

OCE input

T

_IOOCECK/T_IOCKOCE0.37 / 0

_IOSRCKO/T_IOCKOSR0.52 / 0

0.8 / 0

1.1 / 0

0.7 / 0

0.9 / 0

1.0 / 0

1.4 / 0

0.9 / 0

1.1 / 0

1.3 / 0

SR input (OFF)

T

3-State Setup Times, T input

3-State Setup Times, TCE input

3-State Setup Times, SR input (TFF)

Set/Reset Delays

T

_IOTCK/T_IOCKT

_IOTCECK/T_IOCKTCE

_IOSRCKT/T_IOCKTSR

0.34 / 0

0.41 / 0

0.49 / 0

T

SR input to Pad (asynchronous)

T_IOSRP

1.6

3.8

3.1

4.1

3.4

4.6

3.9

ns, max

SR input to Pad high-impedance

(asynchronous)⁽¹⁾

T_IOSRHZ

SR input to valid data on Pad

(asynchronous)

T_IOSRON

T_IOGSRQ

2.0

4.9

4.2

9.7

4.6

5.1

ns, max

GSR to Pad

10.9

12.5

Notes:

1. 3-state turn-off delays should not be adjusted.

2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

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Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

IOB Output Switching Characteristics Standard Adjustments

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays by the values shown.

Speed Grade

Unit

Description

Symbol

Standard⁽¹⁾

Min

-6

-5

-4

s

Output Delay Adjustments

Standard-specific adjustments for

output delays terminating at pads

(based on standard capacitive load,

Csl)

T_{OLVTTL_S2}

T_{OLVTTL_S4}

T_{OLVTTL_S6}

T_{OLVTTL_S8}

T_{OLVTTL_S12}

T_{OLVTTL_S16}

T_{OLVTTL_S24}

T_{OLVTTL_F2}

T_{OLVTTL_F4}

T_{OLVTTL_F6}

T_{OLVTTL_F8}

T_{OLVTTL_F12}

T_{OLVTTL_F16}

T_{OLVTTL_F24}

T_OLVCMOS2

T_{OPCI33_3}

T_{OPCI33_5}

T_{OPCI66_3}

T_OGTL

LVTTL, Slow, 2 mA

4 mA

4.2

2.5

14.7

7.5

4.8

3.0

1.9

1.7

1.3

13.1

5.3

3.1

1.0

0

15.8

8.0

5.1

3.3

2.1

1.9

1.4

14.0

5.7

3.3

1.1

0

17.0

8.6

ns

6 mA

1.8

5.6

8 mA

1.2

3.5

12 mA

1.0

2.2

16 mA

0.9

2.0

24 mA

0.8

1.6

LVTTL, Fast, 2mA

4 mA

1.9

15.1

6.1

0.7

6 mA

0.2

3.6

8 mA

0.1

1.2

12 mA

0

16 mA

–0.10

0.10

0.50

0.40

0.10

0.6

–0.05 –0.05

–0.20 –0.21

–0.05

–0.23

0.12

2.7

24 mA

LVCMOS2

PCI, 33 MHz, 3.3 V

PCI, 33 MHz, 5.0 V

PCI, 66 MHz, 3.3 V

GTL

0.10

2.3

0.11

2.5

2.8

3.0

3.3

–0.40 –0.42

–0.46

0.6

0.50

0.8

0.54

0.9

T_OGTLP

GTL+

0.7

1.0

T_{OHSTL_I}

HSTL I

0.10

–0.10

–0.20

–0.10

–0.20

–0.30

0

–0.50 –0.53

–0.5

–1.0

–1.1

–0.5

–1.0

–0.5

–1.1

–0.6

–1.0

T_{OHSTL_III}

T_{OHSTL_IV}

T_{OSSTL2_I}

T_{OSSLT2_II}

T_{OSSTL3_I}

T_{OSSTL3_II}

T_OCTT

HSTL III

HSTL IV

SSTL2 I

SSTL2 II

SSTL3 I

SSTL3 II

CTT

–0.9

–1.0

–0.9

–1.0

–0.50 –0.53

–0.9 –0.9

–0.50 –0.53

–1.0

–0.6

–0.9

–1.0

–0.6

–0.9

T_OAGP

AGP

0

Notes:

1. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see

Table 1 and Table 2.

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Module 3 of 4

9

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Virtex™ 2.5 V Field Programmable Gate Arrays

For other capacitive loads, use the formulas below to calcu-

Calculation of T_ioopas a Function of

Capacitance

late the corresponding T_ioop

_ioop= T_ioop+ T_opadjust+ (C_load– C_sl) * fl

Where:

_opadjustis reported above in the Output Delay

.

T

T_ioopis the propagation delay from the O Input of the IOB to

the pad. The values for T_ioopwere based on the standard

capacitive load (Csl) for each I/O standard as listed in

Table 1.

T

Adjustment section.

C_loadis the capacitive load for the design.

Table 1: Constants for Calculating T_ioop

Csl

(pF)

fl

Table 2: Delay Measurement Methodology

Standard

LVTTL Fast Slew Rate, 2mA drive

LVTTL Fast Slew Rate, 4mA drive

LVTTL Fast Slew Rate, 6mA drive

LVTTL Fast Slew Rate, 8mA drive

LVTTL Fast Slew Rate, 12mA drive

LVTTL Fast Slew Rate, 16mA drive

LVTTL Fast Slew Rate, 24mA drive

LVTTL Slow Slew Rate, 2mA drive

LVTTL Slow Slew Rate, 4mA drive

LVTTL Slow Slew Rate, 6mA drive

LVTTL Slow Slew Rate, 8mA drive

LVTTL Slow Slew Rate, 12mA drive

LVTTL Slow Slew Rate, 16mA drive

LVTTL Slow Slew Rate, 24mA drive

LVCMOS2

(ns/pF)

Meas. V_REF

Point Typ⁽²⁾

35

50

10

0

0.41

0.20

(1)

Standard

LVTTL

V_L

V_H

0

3

1.4

-

0.13

0.079

0.044

0.043

0.033

0.41

LVCMOS2

PCI33_5

PCI33_3

PCI66_3

GTL

0

2.5

Per PCI Spec

V_REF+0.2

1.125

-

V

_REF–0.2

V_REF

0.80

1.0

0.75

0.90

1.5

1.25

1.5

0.20

GTL+

V_REF–0.2

V_REF+0.2

0.100

0.086

0.058

0.050

0.048

0.041

0.050

0.033

0.014

0.017

0.022

0.016

0.014

0.028

0.016

0.029

0.016

0.035

0.037

HSTL Class I

HSTL Class III

HSTL Class IV

SSTL3 I & II

SSTL2 I & II

CTT

V

_REF–0.5

V_REF+0.5

V

V_REF+0.5

V_REF–0.5

_REF–1.0

V_REF+0.5

V

V_REF+1.0

V

_REF–0.75 V_REF+0.75

V_REF–0.2 V_REF+0.2

V_REFV_REF

(0.2xV_CCO(0.2xV_CCO

PCI 33MHz 5V

PCI 33MHZ 3.3 V

AGP

–

+

Per

PCI 66 MHz 3.3 V

AGP

Spec

)

GTL

GTL+

0

Notes:

1. Input waveform switches between V_Land V_H.

2. Measurements are made at VREF (Typ), Maximum, and

Minimum. Worst-case values are reported.

3. I/O parameter measurements are made with the capacitance

values shown in Table 1. See Xilinx Application Note

XAPP133 for appropriate terminations.

4. I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

HSTL Class I

20

30

20

10

HSTL Class III

HSTL Class IV

SSTL2 Class I

SSTL2 Class II

SSTL3 Class I

SSTL3 Class II

CTT

AGP

Notes:

1. I/O parameter measurements are made with the capacitance

values shown above. See Xilinx Application Note XAPP133

for appropriate terminations.

2. I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

Module 3 of 4

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Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Clock Distribution Guidelines

Speed Grade

Description

Global Clock Skew⁽¹⁾

Device

Symbol

-6

-5

-4

Units

Global Clock Skew between IOB Flip-flops

XCV50

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

T_GSKEWIOB

0.10

0.12

0.13

0.14

0.13

0.14

0.16

0.20

0.12

0.13

0.14

0.16

0.13

0.15

0.17

0.23

0.14

0.15

0.16

0.18

0.14

0.17

0.20

0.25

ns, max

Notes:

1. These clock-skew delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case

conditions. Precise values for a particular design are provided by the timing analyzer.

Clock Distribution Switching Characteristics

Speed Grade

Description

GCLK IOB and Buffer

Symbol

Min

-6

-5

-4

Units

Global Clock PAD to output.

T_GPIO

T_GIO

0.33

0.34

0.7

0.8

0.9

ns, max

Global Clock Buffer I input to O output

DS003-3 (v2.5) April 2, 2001

Product Specification

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Module 3 of 4

11

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Virtex™ 2.5 V Field Programmable Gate Arrays

I/O Standard Global Clock Input Adjustments

Speed Grade

Description

Symbol

Standard⁽¹⁾

Min

-6

-5

-4

Units

Data Input Delay Adjustments

Standard-specific global clock input

delay adjustments

T_GPLVTTL

LVTTL

0

ns,

max

T_GPLVCMOS

LVCMOS2

–0.02

–0.05

0.13

–0.05

0.7

–0.04

–0.11

0.25

–0.11

0.8

–0.04

–0.12

0.28

–0.12

0.9

–0.05

–0.14

0.33

–0.14

0.9

ns,

max

2

T_{GPPCI33_3}

PCI, 33 MHz, 3.3

V

ns,

max

T_{GPPCI33_5}

T_{GPPCI66_3}

T_GPGTL

PCI, 33 MHz, 5.0

V

ns,

max

PCI, 66 MHz, 3.3

V

ns,

max

GTL

GTL+

HSTL

SSTL2

SSTL3

CTT

ns,

max

T_GPGTLP

T_GPHSTL

T_GPSSTL2

T_GPSSTL3

T_GPCTT

0.7

0.8

ns,

max

0.7

ns,

max

0.6

0.52

0.6

0.51

0.55

0.7

0.50

0.54

0.7

ns,

max

0.6

ns,

max

0.7

ns,

max

T_GPAGP

AGP

0.6

0.54

0.53

0.52

ns,

max

Notes:

1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 2.

Module 3 of 4

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Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

CLB Switching Characteristics

Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise

values are provided by the timing analyzer.

Speed Grade

Description

Combinatorial Delays

Symbol

Min

-6

-5

-4

Units

4-input function: F/G inputs to X/Y outputs

5-input function: F/G inputs to F5 output

5-input function: F/G inputs to X output

6-input function: F/G inputs to Y output via F6 MUX

6-input function: F5IN input to Y output

T_ILO

T_IF5

0.29

0.32

0.36

0.44

0.17

0.31

0.6

0.7

0.8

0.9

0.32

0.7

0.8

1.0

0.36

0.7

0.8

0.9

ns, max

T_IF5X

1.0

T_IF6Y

1.2

T_F5INY

T_IFNCTL

0.42

0.8

Incremental delay routing through transparent latch

to XQ/YQ outputs

BY input to YB output

T_BYYB

0.27

0.53

0.6

0.7

ns, max

Sequential Delays

FF Clock CLK to XQ/YQ outputs

Latch Clock CLK to XQ/YQ outputs

Setup and Hold Times before/after Clock CLK⁽¹⁾

4-input function: F/G Inputs

5-input function: F/G inputs

6-input function: F5IN input

6-input function: F/G inputs via F6 MUX

BX/BY inputs

T_CKO

0.54

0.6

1.1

1.2

1.4

1.6

ns, max

T_CKLO

Setup Time / Hold Time

T

_ICK/T_CKI

0.6 / 0

0.7 / 0

1.2 / 0 1.4 / 0 1.5 / 0 ns, min

1.3 / 0 1.5 / 0 1.7 / 0 ns, min

T

_IF5CK/T_CKIF5

T

_F5INCK/T_CKF5IN0.46 / 0 1.0 / 0 1.1 / 0 1.2 / 0 ns, min

_IF6CK/T_CKIF60.8 / 0 1.5 / 0 1.7 / 0 1.9 / 0 ns, min

T

_DICK/T_CKDI

0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min

0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min

0.33 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min

CE input

T

_CECK/T_CKCE

SR/BY inputs (synchronous)

Clock CLK

T

_RCKT_CKR

Minimum Pulse Width, High

Minimum Pulse Width, Low

Set/Reset

T_CH

T_CL

0.8

1.5

1.7

2.0

ns, min

Minimum Pulse Width, SR/BY inputs

T_RPW

T_RQ

1.3

2.5

1.1

2.8

1.3

3.3

1.4

ns, min

ns, max

Delay from SR/BY inputs to XQ/YQ outputs

(asynchronous)

0.54

Delay from GSR to XQ/YQ outputs

Toggle Frequency (MHz) (for export control)

Notes:

T_IOGSRQ

4.9

9.7

10.9

294

12.5

250

ns, max

MHz

F

_TOG(MHz)

625

333

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

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Module 3 of 4

13

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Virtex™ 2.5 V Field Programmable Gate Arrays

CLB Arithmetic Switching Characteristics

Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment

listed. Precise values are provided by the timing analyzer.

Speed Grade

Description

Combinatorial Delays

Symbol

Min

-6

-5

-4

Units

F operand inputs to X via XOR

F operand input to XB output

F operand input to Y via XOR

F operand input to YB output

F operand input to COUT output

G operand inputs to Y via XOR

G operand input to YB output

G operand input to COUT output

BX initialization input to COUT

CIN input to X output via XOR

CIN input to XB

T_OPX

T_OPXB

T_OPY

0.37

0.54

0.8

1.1

0.9

1.3

1.0

1.4

2.0

1.5

1.2

2.1

1.6

1.1

0.53

0.06

0.6

ns, max

1.5

1.7

T_OPYB

T_OPCYF

T_OPGY

T_OPGYB

T_OPCYG

T_BXCY

T_CINX

0.8

1.5

1.7

0.6

1.2

1.3

0.46

0.8

1.0

1.1

1.6

1.8

0.7

1.3

1.4

0.41

0.21

0.02

0.23

0.05

0.9

1.0

0.41

0.04

0.46

0.45

0.09

0.46

0.05

0.52

0.51

0.10

T_CINXB

T_CINY

T_CINYB

T_BYP

CIN input to Y via XOR

CIN input to YB

0.6

CIN input to COUT output

0.11

Multiplier Operation

F1/2 operand inputs to XB output via AND

F1/2 operand inputs to YB output via AND

F1/2 operand inputs to COUT output via AND

G1/2 operand inputs to YB output via AND

G1/2 operand inputs to COUT output via AND

Setup and Hold Times before/after Clock CLK⁽¹⁾

CIN input to FFX

T_FANDXB

T_FANDYB

T_FANDCY

T_GANDYB

T_GANDCY

0.18

0.40

0.22

0.25

0.07

0.36

0.8

0.40

0.9

0.46

1.1

ns, max

0.43

0.50

0.13

0.48

0.6

0.7

0.15

0.17

Setup Time / Hold Time

T

_CCKX/T_CKCX0.50 / 0

_CCKY/T_CKCY0.53 / 0

1.0 / 0

1.1 / 0

1.2 / 0

1.3 / 0

1.4 / 0

ns, min

CIN input to FFY

Notes:

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

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DS003-3 (v2.5) April 2, 2001

Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

CLB SelectRAM Switching Characteristics

Speed Grade

Description

Sequential Delays

Symbol

Min

-6

-5

-4

Units

Clock CLK to X/Y outputs (WE active) 16 x 1 mode

Clock CLK to X/Y outputs (WE active) 32 x 1 mode

Shift-Register Mode

T_SHCKO16

T_SHCKO32

1.2

2.3

2.7

2.6

3.1

3.0

3.5

ns, max

Clock CLK to X/Y outputs

Setup and Hold Times before/after Clock CLK⁽¹⁾

F/G address inputs

T_REG

1.2

3.7

4.1

4.7

ns, max

Setup Time / Hold Time

T_AS/T_AH

0.25 / 0

0.34 / 0

0.38 / 0

0.5 / 0

0.7 / 0

0.8 / 0

0.6 / 0

0.8 / 0

0.9 / 0

0.7 / 0

0.9 / 0

1.0 / 0

ns, min

BX/BY data inputs (DIN)

CE input (WE)

T_DS/T_DH

T

_WS/T_WH

Shift-Register Mode

BX/BY data inputs (DIN)

CE input (WS)

T_SHDICK

T_SHCECK

0.34

0.38

0.7

0.8

0.9

1.0

ns, min

Clock CLK

Minimum Pulse Width, High

Minimum Pulse Width, Low

T_WPH

T_WPL

T_WC

1.2

2.4

4.8

2.7

5.4

3.1

6.2

ns, min

Minimum clock period to meet address write cycle

time

Shift-Register Mode

Minimum Pulse Width, High

Minimum Pulse Width, Low

Notes:

T_SRPH

T_SRPL

1.2

2.4

2.7

3.1

ns, min

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

DS003-3 (v2.5) April 2, 2001

Product Specification

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Module 3 of 4

15

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Block RAM Switching Characteristics

Speed Grade

Description

Sequential Delays

Symbol

T_BCKO

Min

-6

-5

-4

Units

Clock CLK to DOUT output

Setup and Hold Times before/after Clock CLK⁽¹⁾

ADDR inputs

1.7

3.4

3.8

4.3

ns, max

Setup Time / Hold Time

T

_BACK/T_BCKA

0.6 / 0

1.3 / 0

1.2 / 0

2.6 / 0

2.5 / 0

2.3 / 0

1.3 / 0

3.0 / 0

2.7 / 0

2.6 / 0

1.5 / 0

3.4 / 0

3.2 / 0

3.0 / 0

ns, min

DIN inputs

T

_BDCK/T_BCKD

_BECK/T_BCKE

T_BRCK/T_BCKR

EN input

T

RST input

WEN input

T

_BWCK/T_BCKW

Clock CLK

Minimum Pulse Width, High

Minimum Pulse Width, Low

CLKA -> CLKB setup time for different ports

Notes:

T_BPWH

T_BPWL

T_BCCS

0.8

1.5

3.0

1.7

3.5

2.0

4.0

ns, min

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

TBUF Switching Characteristics

Speed Grade

Description

Symbol

Min

-6

-5

-4

Units

Combinatorial Delays

IN input to OUT output

T_IO

T_OFF

T_ON

0

ns, max

TRI input to OUT output high-impedance

TRI input to valid data on OUT output

0.05

0.09

0.10

0.11

JTAG Test Access Port Switching Characteristics

Speed Grade

Description

Symbol

-6

4.0

2.0

11.0

33

-5

4.0

2.0

11.0

33

-4

Units

ns, min

TMS and TDI Setup times before TCK

TMS and TDI Hold times after TCK

Output delay from clock TCK to output TDO

Maximum TCK clock frequency

T_TAPTCK

T_TCKTAP

T_TCKTDO

F_TCK

4.0

2.0

ns, min

11.0

33

ns, max

MHz, max

Module 3 of 4

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DS003-3 (v2.5) April 2, 2001

Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Virtex Pin-to-Pin Output Parameter Guidelines

Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are

expressed in nanoseconds unless otherwise noted.

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL

Speed Grade

Description

Symbol

Device

XCV50

Min

1.0

-6

-5

-4

Units

LVTTL Global Clock Input to Output Delay using

Output Flip-flop, 12 mA, Fast Slew Rate, with DLL.

For data output with different standards, adjust

delays with the values shown in Output Delay

Adjustments.

T_ICKOFDLL

3.1

3.3

3.6

ns, max

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and

where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.

For other I/O standards and different loads, see Table 1 and Table 2.

3. DLL output jitter is already included in the timing calculation.

Global Clock Input-to-Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL

Speed Grade

Description

Symbol

Device

XCV50

Min

1.5

1.6

1.7

-6

-5

-4

Units

LVTTL Global Clock Input to Output Delay using

Output Flip-flop, 12 mA, Fast Slew Rate, without DLL.

For data output with different standards, adjust

delays with the values shown in Input and Output

Delay Adjustments.

For I/O standards requiring V_REF, such as GTL,

GTL+, SSTL, HSTL, CTT, and AGO, an additional

600 ps must be added.

T_ICKOF

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

6.0

6.2

6.3

ns, max

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and

where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.

For other I/O standards and different loads, see Table 1 and Table 2.

DS003-3 (v2.5) April 2, 2001

Product Specification

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1-800-255-7778

Module 3 of 4

17

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Minimum Clock-to-Out for Virtex Devices

With DLL

Without DLL

V100 V150 V200 V300 V400 V600 V800 V1000

I/O Standard

*LVTTL_S2

*LVTTL_S4

*LVTTL_S6

*LVTTL_S8

*LVTTL_S12

*LVTTL_S16

*LVTTL_S24

*LVTTL_F2

*LVTTL_F4

*LVTTL_F6

*LVTTL_F8

*LVTTL_F12

*LVTTL_F16

*LVTTL_F24

LVCMOS2

PCI33_3

All Devices

5.2

3.5

2.8

2.2

2.0

1.9

1.8

2.9

1.7

1.2

1.1

1.0

0.9

1.1

1.5

1.4

1.1

1.6

1.7

1.1

0.9

0.8

0.9

0.8

0.7

1.0

V50

6.0

4.3

3.6

3.1

2.9

2.8

2.6

3.8

2.6

2.0

1.9

1.8

1.7

1.9

2.4

2.2

1.9

2.5

1.9

1.7

1.6

1.7

1.6

1.5

1.8

Units

ns

6.0

4.3

3.6

3.1

2.9

2.8

2.6

3.8

2.6

2.0

1.9

1.8

1.7

1.9

2.4

2.2

1.9

2.5

1.9

1.7

1.6

1.7

1.6

1.7

1.5

1.8

6.0

4.3

3.6

3.1

2.9

2.8

2.7

3.8

2.6

2.0

1.9

1.8

1.7

1.9

2.4

2.3

2.0

2.5

2.6

1.9

1.8

1.6

1.7

1.6

1.7

1.6

1.8

1.9

6.0

4.3

3.6

3.1

2.9

2.8

2.7

3.8

2.6

2.1

1.9

1.8

2.0

2.4

2.3

2.0

2.5

2.6

1.9

1.8

1.7

1.6

1.7

1.6

1.9

6.1

4.4

3.7

3.1

2.9

2.8

2.7

3.8

2.6

2.1

2.0

1.9

1.8

2.0

2.4

2.3

2.0

2.5

2.6

2.0

1.8

1.7

1.8

1.7

1.6

1.9

6.1

4.4

3.7

3.1

2.9

2.8

2.7

3.8

2.6

2.1

2.0

1.9

1.8

2.0

2.4

2.3

2.0

2.5

2.6

2.0

1.8

1.7

1.8

1.7

1.6

1.9

6.1

4.4

3.7

3.2

3.0

2.9

2.7

3.9

2.7

2.1

2.0

1.9

1.8

2.0

2.5

2.3

2.0

2.6

2.0

1.8

1.7

1.8

1.7

1.6

1.9

6.1

4.4

3.7

3.2

3.0

2.9

2.7

3.9

2.7

2.1

2.0

1.9

1.8

2.0

2.5

2.3

2.1

2.6

2.0

1.8

1.7

1.8

1.7

1.8

1.6

1.9

6.1

4.4

3.7

3.2

3.0

2.9

2.8

3.9

2.7

2.2

2.0

1.9

2.1

2.5

2.4

2.1

2.6

2.7

2.0

1.9

1.8

1.7

1.8

1.7

2.0

PCI33_5

PCI66_3

GTL

GTL+

HSTL I

HSTL III

HSTL IV

SSTL2 I

SSTL2 II

SSTL3 I

SSTL3 II

CTT

AGP

*S = Slow Slew Rate, F = Fast Slew Rate

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and

where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2. Input and output timing is measured at 1.4 V for LVTTL. For other I/O standards, see Table 2. In all cases, an 8 pF external capacitive

load is used.

Module 3 of 4

18

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DS003-3 (v2.5) April 2, 2001

Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Virtex Pin-to-Pin Input Parameter Guidelines

Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are

expressed in nanoseconds unless otherwise noted

Global Clock Set-Up and Hold for LVTTL Standard, with DLL

Speed Grade

Description

Symbol

Device

Min

-6

-5

-4

Units

Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different

standards, adjust the setup time delay by the values shown in Input Delay Adjustments.

No Delay

T

_PSDLL/T_PHDLL

XCV50

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

0.40 / –0.4 1.7 /–0.4 1.8 /–0.4 2.1 /–0.4

0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4

ns,

min

Global Clock and IFF, with DLL

ns,

min

ns,

min

ns,

min

ns,

min

ns,

min

ns,

min

ns,

min

ns,

min

IFF = Input Flip-Flop or Latch

Notes:

1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured

relative to the Global Clock input signal with the slowest route and heaviest load.

2. DLL output jitter is already included in the timing calculation.

3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

DS003-3 (v2.5) April 2, 2001

Product Specification

www.xilinx.com

1-800-255-7778

Module 3 of 4

19

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Global Clock Set-Up and Hold for LVTTL Standard, without DLL

Speed Grade

-6 -5

Description

Symbol

Device

Min

-4

Units

Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard.⁽²⁾For data input with different

standards, adjust the setup time delay by the values shown in Input Delay Adjustments.

Full Delay

T

_PSFD/T_PHFD

XCV50

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

0.6 / 0

0.7 / 0

2.3 / 0

2.4 / 0

2.5 / 0

2.6 / 0

2.7 / 0

2.8 / 0

2.6 / 0

2.7 / 0

2.8 / 0

2.9 / 0

3.1 / 0

2.9 / 0

3.0 / 0

3.1 / 0

3.2 / 0

3.3 / 0

3.5 / 0

3.6 / 0

ns,

min

Global Clock and IFF, without

DLL

ns,

min

ns,

min

ns,

min

ns,

min

ns,

min

ns,

min

ns,

min

ns,

min

IFF = Input Flip-Flop or Latch

Notes: Notes:

1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured

relative to the Global Clock input signal with the slowest route and heaviest load.

2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

Module 3 of 4

20

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1-800-255-7778

DS003-3 (v2.5) April 2, 2001

Product Specification

R

Virtex™ 2.5 V Field Programmable Gate Arrays

DLL Timing Parameters

Switching parameters testing is modeled after testing methods specified by MIL-M-38510/605; all devices are 100 percent

functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are

derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended

operating conditions.

Speed Grade

-6

-5

-4

Description

Input Clock Frequency (CLKDLLHF)

Input Clock Frequency (CLKDLL)

Input Clock Pulse Width (CLKDLLHF)

Input Clock Pulse Width (CLKDLL)

Notes:

Symbol

FCLKINHF

FCLKINLF

T_DLLPWHF

T_DLLPWLF

Min

60

Max

200

100

-

Min

60

Max

180

90

Min

60

Max

180

90

-

Units

MHz

ns

25

2.0

2.5

2.4

3.0

-

2.4

3.0

-

ns

1. All specifications correspond to Commercial Operating Temperatures (0°C to + 85°C).

DLL Clock Tolerance, Jitter, and Phase Information

All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock

mirror configuration and matched drivers.

CLKDLLHF

CLKDLL

Description

Input Clock Period Tolerance

Symbol

T_IPTOL

T_IJITCC

T_LOCK

F_CLKIN

Min

Max Min Max Units

-

1.0

150

20

-

1.0

300

20

ns

ps

s

Input Clock Jitter Tolerance (Cycle to Cycle)

Time Required for DLL to Acquire Lock

> 60 MHz

50 - 60 MHz

40 - 50 MHz

30 - 40 MHz

25 - 30 MHz

25

s

-

50

s

-

90

s

-

120

60

s

Output Jitter (cycle-to-cycle) for any DLL Clock Output⁽¹⁾T_OJITCC

60

100

140

ps

Phase Offset between CLKIN and CLKO⁽²⁾

T_PHIO

100

140

Phase Offset between Clock Outputs on the DLL⁽³⁾

T_PHOO

Maximum Phase Difference between CLKIN and

CLKO⁽⁴⁾

T_PHIOM

160

200

160

200

ps

Maximum Phase Difference between Clock Outputs on

the DLL⁽⁵⁾

T_PHOOM

Notes:

1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.

2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,

excluding Output Jitter and input clock jitter.

3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL

outputs, excluding Output Jitter and input clock jitter.

4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,

or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).

5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL

clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).

6. All specifications correspond to Commercial Operating Temperatures (0°C to +85°C).

DS003-3 (v2.5) April 2, 2001

Product Specification

www.xilinx.com

1-800-255-7778

Module 3 of 4

21

R

Virtex™ 2.5 V Field Programmable Gate Arrays

Period Tolerance: the allowed input clock period change in nanoseconds.

+ T

_

T

IPTOL

CLKIN

Output Jitter: the difference between an ideal Phase Offset and Maximum Phase Difference

reference clock edge and the actual design.

Ideal Period

Actual Period

+/- Jitter

+ Maximum

Phase Difference

+ Phase Offset

ds003_20c_110399

Figure 1: Frequency Tolerance and Clock Jitter

Module 3 of 4

22