XCV3200E-7FGG1156I [XILINX]
Field Programmable Gate Array, 400MHz, 73008-Cell, CMOS, PBGA1156;
| 型号： | XCV3200E-7FGG1156I |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 400MHz, 73008-Cell, CMOS, PBGA1156 时钟 栅 可编程逻辑 |
| 文件： | 总233页 (文件大小：1475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
Virtex™-E 1.8 V
Field Programmable Gate Arrays
0
0
DS022-1 (v2.3) July 17, 2002
Production Product Specification
Features
•
Fast, High-Density 1.8 V FPGA Family
•
High-Performance Built-In Clock Management Circuitry
-
-
-
-
Densities from 58 k to 4 M system gates
130 MHz internal performance (four LUT levels)
Designed for low-power operation
-
-
Eight fully digital Delay-Locked Loops (DLLs)
Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
-
-
Clock Multiply and Divide
Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
•
•
Highly Flexible SelectI/O+™ Technology
-
-
Supports 20 high-performance interface standards
Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
•
Flexible Architecture Balances Speed and Density
-
-
-
-
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input function
Differential Signalling Support
-
-
-
-
LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
Differential I/O signals can be input, output, or I/O
Compatible with standard differential devices
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
-
-
-
LVPECL and LVDS clock inputs for 300+ MHz
clocks
•
•
Proprietary High-Performance SelectLink™
Technology
-
-
•
Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
-
-
Double Data Rate (DDR) to Virtex-E link
Web-based HDL generation methodology
Further compile time reduction of 50%
Internet Team Design (ITD) tool ideal for
million-plus gate density designs
Wide selection of PC and workstation platforms
Sophisticated SelectRAM+™ Memory Hierarchy
-
-
-
-
1 Mb of internal configurable distributed RAM
Up to 832 Kb of synchronous internal block RAM
True Dual-Port BlockRAM capability
Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
-
•
•
SRAM-Based In-System Configuration
Unlimited re-programmability
Advanced Packaging Options
-
-
-
-
-
0.8 mm Chip-scale
1.0 mm BGA
1.27 mm BGA
HQ/PQ
-
Designed for high-performance Interfaces to
External Memories
200 MHz ZBT* SRAMs
-
-
-
200 Mb/s DDR SDRAMs
Supported by free Synthesizable reference design
•
•
0.18 μm 6-Layer Metal Process
100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.
© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-1 (v2.3) July 17, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 1: Virtex-E Field-Programmable Gate Array Family Members
System
Gates
Logic
Gates
CLB
Array
Logic
Cells
Differential
I/O Pairs
User
I/O
BlockRAM Distributed
Device
Bits
RAM Bits
XCV50E
71,693
128,236
20,736
32,400
16 x 24
20 x 30
28 x 42
32 x 48
40 x 60
48 x 72
64 x 96
72 x 108
80 x 120
92 x 138
1,728
2,700
83
176
196
284
316
404
512
660
724
804
804
804
65,536
24,576
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
83
81,920
38,400
306,393
63,504
5,292
119
137
183
247
281
344
344
344
344
114,688
131,072
163,840
294,912
393,216
589,824
655,360
753,664
851,968
75,264
411,955
82,944
6,912
98,304
569,952
129,600
186,624
331,776
419,904
518,400
685,584
876,096
10,800
15,552
27,648
34,992
43,200
57,132
153,600
221,184
393,216
497,664
614,400
812,544
1,038,336
985,882
1,569,178
2,188,742
2,541,952
3,263,755
4,074,387
104 x 156 73,008
The Virtex-E family is not bitstream-compatible with the Vir-
tex family, but Virtex designs can be compiled into equiva-
lent Virtex-E devices.
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions. See the data sheet pinout section for details.
I/O performance is increased to 622 Mb/s using Source
Synchronous data transmission architectures and synchro-
nous system performance up to 240 MHz using sin-
gled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pins can be used
for these new standards.
General Description
The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 6-layer metal 0.18 μm CMOS process. These
advances make Virtex-E FPGAs powerful and flexible alter-
natives to mask-programmed gate arrays. The Virtex-E fam-
ily includes the nine members in Table 1.
Virtex-E devices have up to 640 Kb of faster (250 MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Virtex devices. Each indi-
vidual DLL is slightly improved with easier clock mirroring
and 4x frequency multiplication.
Building on experience gained from Virtex FPGAs, the
Virtex-E family is an evolutionary step forward in program-
mable logic design. Combining a wide variety of program-
mable system features, a rich hierarchy of fast, flexible
interconnect resources, and advanced process technology,
the Virtex-E family delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility
while reducing time-to-market.
V
, the supply voltage for the internal logic and mem-
CCINT
ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
processing and 0.18 μm design rules have resulted in
smaller dice, faster speed, and lower power consumption.
I/O pins are 3 V tolerant, and can be 5 V tolerant with an
external 100 Ω resistor. PCI 5 V is not supported. With the
addition of appropriate external resistors, any pin can toler-
ate any voltage desired.
Banking rules are different. With Virtex devices, all input
Virtex-E Architecture
buffers are powered by V
. With Virtex-E devices, the
CCINT
Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
LVTTL, LVCMOS2, and PCI input buffers are powered by
the I/O supply voltage V
.
CCO
Module 1 of 4
2
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DS022-1 (v2.3) July 17, 2002
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Table 2: Performance for Common Circuit Functions
Function
Register-to-Register
Adder
Bits
Virtex-E (-7)
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP™, slave serial, and JTAG modes).
16
64
4.3 ns
6.3 ns
Pipelined Multiplier
Address Decoder
8 x 8
4.4 ns
5.1 ns
The standard Xilinx Foundation Series™ and Alliance
Series™ Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
16 x 16
16
64
3.8 ns
5.5 ns
16:1 Multiplexer
Parity Tree
4.6 ns
9
18
36
3.5 ns
4.3 ns
5.9 ns
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
LVDS
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz. Table 2 shows performance data for
representative circuits, using worst-case timing parameters.
LVPECL
Virtex-E Device/Package Combinations and Maximum I/O
Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
XCV
50E
XCV
100E
XCV
200E
XCV
300E
XCV
400E
XCV
600E
XCV
1000E
XCV
1600E
XCV
2000E
XCV
2600E
XCV
3200E
CS144
PQ240
HQ240
BG352
BG432
BG560
FG256
FG456
FG676
FG680
FG860
FG900
FG1156
94
94
94
158
158
158
158
158
158
158
404
196
176
260
260
316
316
404
316
404
404
404
176
176
284
176
312
404
444
512
512
660
660
660
512
660
700
724
512
660
512
804
804
804
DS022-1 (v2.3) July 17, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
3
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Ordering Information
Example: XCV300E-6PQ240C
Device Type
Temperature Range
C = Commercial (Tj = 0 C to +85 C)
I = Industrial (Tj = -40 C to +100 C)
Speed Grade
(-6, -7, -8)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
DS022_043_072000
Figure 1: Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T
values, buffered Hex Line info, p. 8, I/O Timing
BYP
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
7/10/00
1.3
1.4
1.5
Updated pinout tables, V page 20, and corrected Figure 20.
CC
Correction to table on p. 22.
•
Numerous minor edits.
•
•
•
•
•
•
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
Min values added to Virtex-E Electrical Characteristics tables.
8/1/00
1.6
1.7
9/20/00
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate V
pins in Table ~ (Module 4).
CCINT
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Module 1 of 4
4
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DS022-1 (v2.3) July 17, 2002
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Revision
Date
Version
•
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
11/20/00
1.8
•
•
•
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for T
, T
, T
, and T
.
SHCKO32 REG BCCS
ICKOF
•
Changed all minimum hold times to –0.4 under Global Clock Setup and Hold for
LVTTL Standard, with DLL.
•
Revised maximum T
in -6 speed grade for DLL Timing Parameters.
DLLPW
•
•
•
Changed GCLK0 to BA22 for FG860 package in Table 46.
Revised footnote for Table 14.
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
2/12/01
1.9
XCV2000E devices.
•
•
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
•
•
•
•
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
Updated numerous values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format. See the Virtex-E Data Sheet section.
4/2/01
2.0
2.1
Updated the Virtex-E Device/Package Combinations and Maximum I/O table to
show XCV3200E in the FG1156 package.
10/25/01
•
•
Minor edits.
11/09/01
07/17/02
2.2
2.3
Data sheet designation upgraded from Preliminary to Production.
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•
DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•
DS022-2, Virtex-E 1.8V FPGAs:
DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
Pinout Tables (Module 4)
DS022-1 (v2.3) July 17, 2002
Production Product Specification
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1-800-255-7778
Module 1 of 4
5
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Module 1 of 4
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DS022-1 (v2.3) July 17, 2002
Production Product Specification
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Virtex™-E 1.8 V
Field Programmable Gate Arrays
0
0
DS022-2 (v2.8) January 16, 2006
Production Product Specification
Architectural Description
Virtex-E Array
The Virtex-E user-programmable gate array, shown in
Figure 1, comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks (IOBs).
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
•
CLBs provide the functional elements for constructing
logic
Input/Output Block
The Virtex-E IOB, Figure 2, features SelectI/O+ inputs and
outputs that support a wide variety of I/O signalling stan-
dards, see Table 1.
•
IOBs provide the interface between the package pins
and the CLBs
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
Q
D
CE
T
TCE
Weak
Keeper
SR
PAD
DLLDLL
DLLDLL
O
Q
D
CE
OCE
OBUFT
VersaRing
SR
I
IQ
Programmable
Delay
Q
D
CE
IBUF
Vref
SR
SR
CLK
ICE
ds022_02_091300
Figure 2: Virtex-E Input/Output Block (IOB)
The three IOB storage elements function either as
edge-triggered D-type flip-flops or as level-sensitive latches.
Each IOB has a clock signal (CLK) shared by the three
flip-flops and independent clock enable signals for each
flip-flop.
VersaRing
DLLDLL
DLLDLL
ds022_01_121099
Figure 1: Virtex-E Architecture Overview
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex-E architecture also includes the following circuits
that connect to the GRM.
•
•
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
•
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
© 2000–2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
www.xilinx.com
Module 2 of 4
1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Input Path
Table 1: Supported I/O Standards
The Virtex-E IOB input path routes the input signal directly
to internal logic and/ or through an optional input flip-flop.
Board
Output Input Input Termination
I/O
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Standard
V
V
V
Voltage (V
N/A
)
TT
CCO
CCO
REF
LVTTL
LVCMOS2
LVCMOS18
SSTL3 I & II
SSTL2 I & II
GTL
3.3
2.5
1.8
3.3
2.5
N/A
N/A
1.5
1.5
3.3
3.3
3.3
3.3
2.5
3.3
3.3
2.5
N/A
N/A
N/A
1.50
1.25
0.80
1.0
N/A
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
1.8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
1.50
1.25
1.20
1.50
0.75
1.50
1.50
N/A
threshold voltage, V . The need to supply V
imposes
REF
REF
constraints on which standards can be used in close prox-
imity to each other. See I/O Banking.
GTL+
There are optional pull-up and pull-down resistors at each
user I/O input for use after configuration. Their value is in
the range 50 – 100 kΩ.
HSTL I
0.75
0.90
1.50
1.32
N/A
N/A
N/A
N/A
HSTL III & IV
CTT
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
AGP-2X
PCI33_3
PCI66_3
BLVDS & LVDS
LVPECL
N/A
3.3
N/A
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
N/A
N/A
N/A
N/A
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
In most signalling standards, the output High voltage
depends on an externally supplied V
voltage. The need
CCO
to supply V
imposes constraints on which standards
CCO
The output buffer and all of the IOB control signals have
independent polarity controls.
can be used in close proximity to each other. See I/O Bank-
ing.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to V
the exception of LVCMOS18, LVCMOS25, GTL, GTL+,
LVDS, and LVPECL.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
with
CCO
Optional pull-up, pull-down and weak-keeper circuits are
attached to each pad. Prior to configuration all outputs not
involved in configuration are forced into their high-imped-
ance state. The pull-down resistors and the weak-keeper
circuits are inactive, but I/Os can optionally be pulled up.
Since the weak-keeper circuit uses the IOB input buffer to
monitor the input level, an appropriate V
voltage must be
REF
provided if the signalling standard requires one. The provi-
sion of this voltage must comply with the I/O banking rules.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins are in a
high-impedance state. Consequently, external pull-up or
pull-down resistors must be provided on pins required to be
at a well-defined logic level prior to configuration.
I/O Banking
Some of the I/O standards described above require V
CCO
and/or V
voltages. These voltages are externally sup-
REF
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
All Virtex-E IOBs support IEEE 1149.1-compatible Bound-
ary Scan testing.
Module 2 of 4
2
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DS022-2 (v2.8) January 16, 2006
Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in Figure 3. Each bank has
In Virtex-E, input buffers with LVTTL, LVCMOS2,
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
multiple V
pins, all of which must be connected to the
V
rather than V
. For these standards, only input
CCO
CCO
CCINT
same voltage. This voltage is determined by the output
standards in use.
and output buffers that have the same V
together.
can be mixed
CCO
The V
and V
pins for each bank appear in the device
REF
CCO
pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Bank 0
Bank 1
GCLK3 GCLK2
Within a given package, the number of V
and V
pins
CCO
REF
can vary depending on the size of device. In larger devices,
more I/O pins convert to V pins. Since these are always
VirtexE
Device
REF
a super set of the V
pins used for smaller devices, it is
REF
possible to design a PCB that permits migration to a larger
device if necessary. All the V pins for the largest device
REF
anticipated must be connected to the V
used for I/O.
voltage, and not
REF
GCLK1 GCLK0
Bank 5
Bank 4
In smaller devices, some V
pins used in larger devices
CCO
do not connect within the package. These unconnected pins
can be left unconnected externally, or can be connected to
ds022_03_121799
Figure 3: Virtex-E I/O Banks
the V
voltage to permit migration to a larger device if
CCO
necessary.
Within a bank, output standards can be mixed only if they
use the same V
Table 2. GTL and GTL+ appear under all voltages because
. Compatible standards are shown in
Configurable Logic Blocks
CCO
The basic building block of the Virtex-E CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex-E CLB contains four LCs,
organized in two similar slices, as shown in Figure 4.
Figure 5 shows a more detailed view of a single slice.
their open-drain outputs do not depend on V
.
CCO
Table 2: Compatible Output Standards
V
Compatible Standards
CCO
3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+, LVPECL
In addition to the four basic LCs, the Virtex-E CLB contains
logic that combines function generators to provide functions
of five or six inputs. Consequently, when estimating the
number of system gates provided by a given device, each
CLB counts as 4.5 LCs.
2.5 V
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,
BLVDS, LVDS
1.8 V
1.5 V
LVCMOS18, GTL, GTL+
HSTL I, HSTL III, HSTL IV, GTL, GTL+
Look-Up Tables
Some input standards require a user-supplied threshold
Virtex-E function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16 x 1-bit dual-port synchronous RAM.
voltage, V . In this case, certain user-I/O pins are auto-
REF
matically configured as inputs for the V
voltage. Approx-
REF
imately one in six of the I/O pins in the bank assume this
role.
The V
pins within a bank are interconnected internally
REF
and consequently only one V
voltage can be used within
The Virtex-E LUT can also provide a 16-bit shift register that
is ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such as
Digital Signal Processing.
REF
each bank. All V
pins in the bank, however, must be con-
REF
nected to the external voltage source for correct operation.
Within a bank, inputs that require V can be mixed with
REF
those that do not. However, only one V
used within a bank.
voltage can be
REF
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
COUT
COUT
YB
Y
YB
Y
G4
G4
G3
G2
SP
SP
Q
G3
G2
G1
Carry &
Control
Carry &
Control
LUT
LUT
D
YQ
D
Q
YQ
CE
CE
G1
BY
F4
RC
RC
BY
XB
X
XB
X
F4
F3
F2
F1
SP
SP
F3
F2
LUT
LUT
Carry &
Control
Carry &
Control
D
Q
D
Q
XQ
XQ
CE
CE
F1
RC
Slice 0
RC
Slice 1
BX
BX
CIN
CIN
ds022_04_121799
Figure 4: 2-Slice Virtex-E CLB
COUT
CY
YB
Y
G4
I3
O
G3
G2
G1
I2
I1
I0
LUT
INIT
D Q
CE
YQ
DI
WE
0
1
REV
BY
XB
F5IN
F6
CY
F5
X
F5
BY DG
CK WSO
WE
BX
WSH
A4
DI
INIT
D Q
CE
XQ
BX
DI
WE
I3
I2
I1
I0
F4
F3
F2
F1
REV
O
LUT
0
1
SR
CLK
CE
ds022_05_092000
CIN
Figure 5: Detailed View of Virtex-E Slice
the function generators within the slice or directly from slice
inputs, bypassing the function generators.
Storage Elements
The storage elements in the Virtex-E slice can be config-
ured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
In addition to Clock and Clock Enable signals, each Slice
has synchronous set and reset signals (SR and BY). SR
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Virtex™-E 1.8 V Field Programmable Gate Arrays
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals can be configured to oper-
ate asynchronously. All of the control signals are indepen-
dently invertible, and are shared by the two flip-flops within
the slice.
Table 3: CLB/Block RAM Column Locations
XCV
Device
/Col. 0 12 24 36 48 60 72 84 96 108 120 138 156
50E
Columns 0, 6, 18, & 24
Columns 0, 12, 18, & 30
Columns 0, 12, 30, & 42
100E
Additional Logic
200E
The F5 multiplexer in each slice combines the function gen-
erator outputs. This combination provides either a function
generator that can implement any 5-input function, a 4:1
multiplexer, or selected functions of up to nine inputs.
300E
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
400E
√
√
600E
√
√
√
√
√
√
√
√
√
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
1000E
1600E
2000E
2600E
3200E
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Each CLB has four direct feedthrough paths, two per slice.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
√
Table 4 shows the amount of block SelectRAM memory that
is available in each Virtex-E device.
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capabil-
ity for high-speed arithmetic functions. The Virtex-E CLB
supports two separate carry chains, one per Slice. The
height of the carry chains is two bits per CLB.
Table 4: Virtex-E Block SelectRAM Amounts
Virtex-E Device # of Blocks Block SelectRAM Bits
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
16
20
65,536
81,920
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation. The dedicated carry path can also be used
to cascade function generators for implementing wide logic
functions.
28
114,688
131,072
163,840
294,912
393,216
589,824
655,360
753,664
851,968
32
40
BUFTs
72
Each Virtex-E CLB contains two 3-state drivers (BUFTs)
that can drive on-chip buses. See Dedicated Routing.
Each Virtex-E BUFT has an independent 3-state control pin
and an independent input pin.
96
144
160
184
208
Block SelectRAM
Virtex-E FPGAs incorporate large block SelectRAM memo-
ries. These complement the Distributed SelectRAM memo-
ries that provide shallow RAM structures implemented in
CLBs.
As illustrated in Figure 6, each block SelectRAM cell is a
fully synchronous dual-ported (True Dual Port) 4096-bit
RAM with independent control signals for each port. The
data widths of the two ports can be configured indepen-
dently, providing built-in bus-width conversion.
Block SelectRAM memory blocks are organized in columns,
starting at the left (column 0) and right outside edges and
inserted every 12 CLB columns (see notes for smaller
devices). Each memory block is four CLBs high, and each
memory column extends the full height of the chip, immedi-
ately adjacent (to the right, except for column 0) of the CLB
column locations indicated in Table 3.
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•
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM.
RAMB4_S#_S#
WEA
ENA
RSTA
DOA[#:0]
To Adjacent
GRM
CLKA
ADDRA[#:0]
DIA[#:0]
To
Adjacent
GRM
To Adjacent
GRM
GRM
WEB
ENB
RSTB
DOB[#:0]
CLKB
ADDRB[#:0]
DIB[#:0]
To Adjacent
GRM
Direct
Direct Connection
To Adjacent
CLB
Connection
To Adjacent
CLB
CLB
ds022_06_121699
Figure 6: Dual-Port Block SelectRAM
XCVE_ds_007
Figure 7: Virtex-E Local Routing
Table 5 shows the depth and width aspect ratios for the
block SelectRAM. The Virtex-E block SelectRAM also
includes dedicated routing to provide an efficient interface
with both CLBs and other block SelectRAMs. Refer to
XAPP130 for block SelectRAM timing waveforms.
General Purpose Routing
Most Virtex-E signals are routed on the general purpose
routing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. General-purpose routing resources are located in
horizontal and vertical routing channels associated with the
CLB rows and columns and are as follows:
Table 5: Block SelectRAM Port Aspect Ratios
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
1
2
•
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
4
8
•
•
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
16
256
72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
are driven only at their endpoints. Hex-line signals can
be accessed either at the endpoints or at the midpoint
(three blocks from the source). One third of the Hex
lines are bidirectional, while the remaining ones are
uni-directional.
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex-E routing
architecture and its place-and-route software were defined
in a joint optimization process. This joint optimization mini-
mizes long-path delays, and consequently, yields the best
system performance.
•
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
Local Routing
I/O Routing
The VersaBlock provides local routing resources (see
Figure 7), providing three types of connections:
Virtex-E devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the
VersaRing, facilitates pin-swapping and pin-locking, such
that logic redesigns can adapt to existing PCB layouts.
Time-to-market is reduced, since PCBs and other system
components can be manufactured while the logic design is
still in progress.
•
•
Interconnections among the LUTs, flip-flops, and GRM
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
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Dedicated Routing
Clock Routing
Clock Routing resources distribute clocks and other signals
with very high fanout throughout the device. Virtex-E
devices include two tiers of clock routing resources referred
to as global and local clock routing resources.
Some classes of signal require dedicated routing resources to
maximize performance. In the Virtex-E architecture, dedi-
cated routing resources are provided for two classes of signal.
•
Horizontal routing resources are provided for on-chip
3-state buses. Four partitionable bus lines are provided
per CLB row, permitting multiple buses within a row, as
shown in Figure 8.
•
The global routing resources are four dedicated global
nets with dedicated input pins that are designed to
distribute high-fanout clock signals with minimal skew.
Each global clock net can drive all CLB, IOB, and block
RAM clock pins. The global nets can be driven only by
global buffers. There are four global buffers, one for
each global net.
•
•
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.Global Clock Distribution
Network
DLL Location
•
The local clock routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These local resources are
more flexible than the global resources since they are
not restricted to routing only to clock pins.
Tri-State
Lines
CLB
CLB
CLB
CLB
buft_c.eps
Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
global nets that in turn drive any clock pin.
Global Clock Distribution
Virtex-E provides high-speed, low-skew clock distribution
through the global routing resources described above. A
typical clock distribution net is shown in Figure 9.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the gen-
eral purpose routing.
GCLKPAD3
GCLKBUF3
GCLKPAD2
GCLKBUF2
Global Clock Column
Global Clock Rows
Digital Delay-Locked Loops
There are eight DLLs (Delay-Locked Loops) per device,
with four located at the top and four at the bottom,
Figure 10. The DLLs can be used to eliminate skew
between the clock input pad and the internal clock input pins
throughout the device. Each DLL can drive two global clock
networks.The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element.
Additional delay is introduced such that clock edges arrive
at internal flip-flops synchronized with clock edges arriving
at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
and can double the clock or divide the clock by 1.5, 2, 2.5, 3,
4, 5, 8, or 16.
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
XCVE_009
Figure 9: Global Clock Distribution Network
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The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to deskew a board level clock among multiple
devices.
also supports two internal scan chains and configura-
tion/readback of the device.
The JTAG input pins (TDI, TMS, TCK) do not have a V
CCO
requirement and operate with either 2.5 V or 3.3 V input sig-
nalling levels. The output pin (TDO) is sourced from the
To guarantee that the system clock is operating correctly
prior to the FPGA starting up after configuration, the DLL
can delay the completion of the configuration process until
after it has achieved lock. For more information about DLL
functionality, see the Design Consideration section of the
data sheet.
V
in bank 2, and for proper operation of LVTTL 3.3 V lev-
CCO
els, the bank should be supplied with 3.3 V.
Boundary Scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including un-bonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections, provided the user
design or application is turned off.
DLLDLL
DLLDLL
Table 6 lists the Boundary Scan instructions supported in
Virtex-E FPGAs. Internal signals can be captured during
EXTEST by connecting them to un-bonded or unused IOBs.
They can also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Primary DLLs
Before the device is configured, all instructions except
USER1 and USER2 are available. After configuration, all
instructions are available. During configuration, it is recom-
mended that those operations using the Boundary Scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.
DLLDLL
DLLDLL
XCVE_0010
Figure 10: DLL Locations
In addition to the test instructions outlined above, the
Boundary Scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
Boundary Scan
Virtex-E devices support all the mandatory Boundary Scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple-
ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions. The TAP
Figure 11 is a diagram of the Virtex-E Series Boundary
Scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
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DATA IN
IOB.T
0
1
0
sd
1
D
Q
D
Q
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
sd
1
0
D
Q
D
Q
LE
1
0
IOB.I
1
sd
D
Q
D
Q
0
LE
1
0
IOB.Q
IOB.T
BYPASS
REGISTER
0
1
M
U
X
TDO
1
sd
INSTRUCTION REGISTER
TDI
D
Q
D
Q
0
LE
1
sd
D
Q
D
Q
0
LE
1
0
IOB.I
DATAOUT
UPDATE
EXTEST
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
X9016
Figure 11: Virtex-E Family Boundary Scan Logic
Table 6: Boundary Scan Instructions (Continued)
Instruction Set
The Virtex-E series Boundary Scan instruction set also
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The
complete instruction set is coded as shown in Table 6..
Boundary Scan
Command
Binary
Code(4:0)
Description
Access the
configuration bus for
write operations.
CFG_IN
00101
Table 6: Boundary Scan Instructions
INTEST
00111
01000
01001
01010
Enables Boundary Scan
INTEST operation
Boundary Scan
Command
Binary
Code(4:0)
Description
USERCODE
IDCODE
HIGHZ
Enables shifting out
USER code
EXTEST
00000
00001
Enables Boundary Scan
EXTEST operation
Enables shifting out of
ID Code
SAMPLE/
PRELOAD
Enables Boundary Scan
SAMPLE/PRELOAD
operation
3-states output pins
while enabling the
Bypass Register
USER1
00010
00011
00100
Access user-defined
register 1
JSTART
01100
11111
Clock the start-up
sequence when
StartupClk is TCK
USER2
Access user-defined
register 2
CFG_OUT
Access the
configuration bus for
read operations.
BYPASS
Enables BYPASS
RESERVED
All other
codes
Xilinx reserved
instructions
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BSDL (Boundary Scan Description Language) files for Vir-
tex-E Series devices are available on the Xilinx web site in
the File Download area.
Data Registers
The primary data register is the Boundary Scan register.
For each IOB pin in the FPGA, bonded or not, it includes
three bits for In, Out, and 3-State Control. Non-IOB pins
have appropriate partial bit population if input-only or out-
put-only. Each EXTEST CAPTURED-OR state captures all
In, Out, and 3-state pins.
Identification Registers
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream Boundary Scan
device.
v = the die version number
The FPGA supports up to two additional internal scan
chains that can be specified using the BSCAN macro. The
macro provides two user pins (SEL1 and SEL2) which are
decodes of the USER1 and USER2 instructions respec-
tively. For these instructions, two corresponding pins (T
DO1 and TDO2) allow user scan data to be shifted out of
TDO.
f = the family code (05 for Virtex-E family)
a = the number of CLB rows (ranges from 16 for
XCV50E to 104 for XCV3200E)
c = the company code (49h for Xilinx)
The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code (see Table 7) is embedded in the bitstream during bit-
stream generation and is valid only after configuration.
Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
(TDI) and shared output pins that represent the state of the
TAP controller (RESET, SHIFT, and UPDATE).
Bit Sequence
Table 7: IDCODEs Assigned to Virtex-E FPGAs
The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the Boundary
Scan I/O data register, while the output-only pins contrib-
utes all three bits.
FPGA
IDCODE
XCV50E
v0A10093h
v0A14093h
v0A1C093h
v0A20093h
v0A28093h
v0A30093h
v0A40093h
v0A48093h
v0A50093h
v0A5C093h
v0A68093h
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
From a cavity-up view of the chip (as shown in EPIC), start-
ing in the upper right chip corner, the Boundary Scan
data-register bits are ordered as shown in Figure 12.
Right half of top-edge IOBs (Right to Left)
Bit 0 ( TDO end)
Bit 1
Bit 2
GCLK2
GCLK3
Left half of top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
M1
M0
M2
Left half of bottom-edge IOBs (Left to Right)
GCLK1
GCLK0
Right half of bottom-edge IOBs (Left to Right)
Note:
DONE
PROG
Attempting to load an incorrect bitstream causes
configuration to fail and can damage the device.
Right-edge IOBs (Bottom to Top)
(TDI end)
CCLK
Including Boundary Scan in a Design
990602001
Since the Boundary Scan pins are dedicated, no special
element needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
Figure 12: Boundary Scan Bit Sequence
If an internal data register is used, insert the Boundary Scan
symbol and connect the necessary pins as appropriate.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
implementation of these functions. Users can create their
own library of soft macros or RPMs based on the macros
and primitives in the standard library.
Development System
Virtex-E FPGAs are supported by the Xilinx Foundation and
Alliance Series CAE tools. The basic methodology for
Virtex-E design consists of three interrelated steps: design
entry, implementation, and verification. Industry-standard
tools are used for design entry and simulation (for example,
Synopsys FPGA Express), while Xilinx provides proprietary
architecture-specific tools for implementation.
The design environment supports hierarchical design entry,
with high-level schematics that comprise major functional
blocks, while lower-level schematics define the logic in
these blocks. These hierarchical design elements are auto-
matically combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
design, thus allowing the most convenient entry method to
be used for each portion of the design.
The Xilinx development system is integrated under the
Xilinx Design Manager (XDM™) software, providing design-
ers with a common user interface regardless of their choice
of entry and verification tools. The XDM software simplifies
the selection of implementation options with pull-down
menus and on-line help.
Design Implementation
The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The parti-
tioner takes the EDIF net list for the design and maps the
logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best locations for these blocks based on their interconnec-
tions and the desired performance. Finally, the router inter-
connects the blocks.
Application programs ranging from schematic capture to
Placement and Routing (PAR) can be accessed through the
XDM software. The program command sequence is gener-
ated prior to execution, and stored for documentation.
Several advanced software features facilitate Virtex-E design.
RPMs, for example, are schematic-based macros with relative
location constraints to guide their placement. They help
ensure optimal implementation of common functions.
The PAR algorithms support fully automatic implementation
of most designs. For demanding applications, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floor planning.
For HDL design entry, the Xilinx FPGA Foundation develop-
ment system provides interfaces to the following synthesis
design environments.
•
•
•
Synopsys (FPGA Compiler, FPGA Express)
Exemplar (Spectrum)
®
The implementation software incorporates Timing Wizard
Synplicity (Synplify)
timing-driven placement and routing. Designers specify tim-
ing requirements along entire paths during design entry.
The timing path analysis routines in PAR then recognize
these user-specified requirements and accommodate them.
For schematic design entry, the Xilinx FPGA Foundation
and Alliance development system provides interfaces to the
following schematic-capture design environments.
•
•
Mentor Graphics V8 (Design Architect, QuickSim II)
Viewlogic Systems (Viewdraw)
Timing requirements are entered on a schematic in a form
directly relating to the system requirements, such as the tar-
geted clock frequency, or the maximum allowable delay
between two registers. In this way, the overall performance
of the system along entire signal paths is automatically tai-
lored to user-generated specifications. Specific timing infor-
mation for individual nets is unnecessary.
Third-party vendors support many other environments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Virtex-E FPGAs are supported by a unified library of stan-
dard functions. This library contains over 400 primitives and
macros, ranging from 2-input AND gates to 16-bit accumu-
lators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.
Design Verification
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be veri-
fied in real time without the need for extensive sets of soft-
ware simulation vectors.
The “soft macro” portion of the library contains detailed
descriptions of common logic functions, but does not con-
tain any partitioning or placement information. The perfor-
mance of these macros depends, therefore, on the
partitioning and placement obtained during implementation.
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the net list for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
RPMs, on the other hand, do contain predetermined parti-
tioning and placement information that permits optimal
®
TRCE static timing analyzer.
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For in-circuit debugging, an optional download and read-
back cable is available. This cable connects the FPGA in the
target system to a PC or workstation. After downloading the
design into the FPGA, the designer can single-step the
logic, readback the contents of the flip-flops, and so observe
the internal logic state. Simple modifications can be down-
loaded into the system in a matter of minutes.
Configuration
Virtex-E devices are configured by loading configuration
data into the internal configuration memory. Note that
attempting to load an incorrect bitstream causes configura-
tion to fail and can damage the device.
operate as LVCMOS. All affected pins fall in banks 2 or 3.
The configuration pins needed for SelectMap (CS, Write)
are located in bank 1.
Configuration Modes
Virtex-E supports the following four configuration modes.
Some of the pins used for configuration are dedicated pins,
while others can be re-used as general purpose inputs and
outputs once configuration is complete.
•
•
•
•
Slave-serial mode
The following are dedicated pins:
Master-serial mode
SelectMAP mode
Boundary Scan mode (JTAG)
•
•
•
•
•
Mode pins (M2, M1, M0)
Configuration clock pin (CCLK)
PROGRAM pin
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
configuration. The selection codes are listed in Table 8.
DONE pin
Boundary Scan pins (TDI, TDO, TMS, TCK)
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or can be generated
externally and provided to the FPGA as an input. The
PROGRAM pin must be pulled High prior to reconfiguration.
Configuration through the Boundary Scan port is always
available, independent of the mode selection. Selecting the
Boundary Scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected. However, it is recom-
mended to drive the configuration mode pins externally.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a V
of 3.3 V or
CCO
2.5 V. At 3.3 V the pins operate as LVTTL, and at 2.5 V they
Table 8: Configuration Codes
Configuration
Configuration Mode M2(1)
M1
0
M0
0
CCLK Direction Data Width Serial D
Pull-ups(1)
out
Master-serial mode
Boundary Scan mode
SelectMAP mode
Slave-serial mode
Master-serial mode
Boundary Scan mode
SelectMAP mode
Slave-serial mode
Notes:
0
1
1
1
1
0
0
0
Out
N/A
In
1
1
8
1
1
1
8
1
Yes
No
No
0
1
No
1
0
No
No
1
1
In
Yes
Yes
No
No
0
0
Out
N/A
In
Yes
0
1
Yes
1
0
No
Yes
1
1
In
Yes
Yes
1. M2 is sampled continuously from power up until the end of the configuration. Toggling M2 while INIT is being held externally Low can
cause the configuration pull-up settings to change.
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Table 9 lists the total number of bits required to configure
each device.
For more detailed information on serial PROMs, see the
PROM data sheet at http://www.xilinx.com/bvdocs/publi-
cations/ds026.pdf.
Table 9: Virtex-E Bitstream Lengths
Multiple FPGAs can be daisy-chained for configuration from a
single source. After a particular FPGA has been configured,
the data for the next device is routed to the DOUT pin. The
maximum capacity for a single LOUT/DOUT write is 2 -1
(1,048,575) 32-bit words, or 33,554,4000 bits. The data on the
DOUT pin changes on the rising edge of CCLK.
Device
# of Configuration Bits
630,048
XCV50E
20
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
863,840
1,442,016
1, 875,648
2,693,440
The change of DOUT on the rising edge of CCLK differs
from previous families, but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
3,961,632
6,587,520
8,308,992
Figure 13 shows a full master/slave system. A Virtex-E
device in slave-serial mode should be connected as shown
in the right-most device.
10,159,648
12,922,336
16,283,712
Slave-serial mode is selected by applying <111> or <011> to
the mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left uncon-
nected. However, it is recommended to drive the configura-
tion mode pins externally. Figure 14 shows slave-serial
mode programming switching characteristics.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
Table 10 provides more detail about the characteristics
shown in Figure 14. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.
Table 10: Master/Slave Serial Mode Programming Switching
Figure
Description
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
References
Symbol
T /T
DCC CCD
Values
5.0 / 0.0
5.0 / 0.0
12.0
Units
ns, min
ns, min
ns, max
ns, min
ns, min
MHz, max
1/2
1/2
3
T
/T
DSCK CKDS
T
T
CCO
CCH
High time
CCLK
4
5.0
Low time
5
T
5.0
CCL
Maximum Frequency
F
66
CC
Frequency Tolerance, master mode with respect to nominal
+45% –30%
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.
N/C
3.3V
330 Ω
M0 M1
M2
M0 M1
M2
N/C
DOUT
DIN
DOUT
CCLK
VIRTEX-E
MASTER
SERIAL
VIRTEX-E,
XC4000XL,
SLAVE
XC1701L
CLK
CCLK
DIN
DATA
CE
Optional Pull-up
Resistor on Done
1
PROGRAM
PROGRAM
DONE
CEO
INIT
DONE
INIT
RESET/OE
(Low Reset Option Used)
PROGRAM
Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor
of 330 Ω should be added to the common DONE line. (For Spartan-XL devices, add a 4.7K Ω
pull-up resistor.) This pull-up is not needed if the DriveDONE attribute is set. If used,
DriveDONE should be selected only for the last device in the configuration chain.
XCVE_ds_013_050103
Figure 13: Master/Slave Serial Mode Circuit Diagram
DIN
1
2
5
T
T
DCC
T
CCD
CCL
CCLK
4
T
CCH
3
T
CCO
DOUT
(Output)
X5379_a
Figure 14: Slave-Serial Mode Programming Switching Characteristics
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge. The maximum capacity for a single
On power-up, the CCLK frequency is approximately
2.5 MHz. This frequency is used until the ConfigRate bits
have been loaded when the frequency changes to the
selected ConfigRate. Unless a different frequency is speci-
fied in the design, the default ConfigRate is 4 MHz.
20
LOUT/DOUT write is 2 -1 (1,048,575) 32-bit words, or
33,554,4000 bits.
In a full master/slave system (Figure 13), the left-most
device operates in master-serial mode. The remaining
devices operate in slave-serial mode. The SPROM RESET
pin is driven by INIT, and the CE input is driven by DONE.
There is the potential for contention on the DONE pin,
depending on the start-up sequence options chosen.
The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK, which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.
The sequence of operations necessary to configure a
Virtex-E FPGA serially appears in Figure 15.
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
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Figure 16 shows the timing of master-serial configuration.
Master-serial mode is selected by a <000> or <100> on the
mode pins (M2, M1, M0). Table 10 shows the timing infor-
mation for Figure 16.
Apply Power
Set PROGRAM = High
Release INIT
FPGA starts to clear
configuration memory.
FPGA makes a final
clearing pass and releases
INIT when finished.
If used to delay
configuration
Low
INIT?
High
Load a Configuration Bit
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
No
End of
Bitstream?
If no CRC errors found,
FPGA enters start-up phase
causing DONE to go High.
Yes
Configuration Completed
ds009_15_111799
Figure 15: Serial Configuration Flowchart
CCLK
(Output)
T
2
CKDS
T
1
DSCK
Serial Data In
Serial DOUT
(Output)
DS022_44_071201
Figure 16: Master-Serial Mode Programming Switching Characteristics
At power-up, V
than 50 ms, otherwise delay configuration by pulling
PROGRAM Low until V is valid.
must rise from 1.0 V to V
Min in less
Multiple Virtex-E FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, WRITE, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
asserting the CS pin of each device in turn and writing the
appropriate data. See Table 11 for SelectMAP Write Timing
Characteristics.
CC
CC
CC
SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the FPGA with a BUSY flag
controlling the flow of data.
An external data source provides a byte stream, CCLK, a
Chip Select (CS) signal and a Write signal (WRITE). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low.
Write
Write operations send packets of configuration data into the
FPGA. The sequence of operations for a multi-cycle write
operation is shown below. Note that a configuration packet
can be split into many such sequences. The packet does
not have to complete within one assertion of CS, illustrated
in Figure 17.
Data can also be read using the SelectMAP mode. If
WRITE is not asserted, configuration data is read out of the
FPGA as part of a readback operation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback.
1. Assert WRITE and CS Low. Note that when CS is
asserted on successive CCLKs, WRITE must remain
either asserted or de-asserted. Otherwise, an abort is
initiated, as described below.
Retention of the SelectMAP port is selectable on a
design-by-design basis when the bitstream is generated. If
retention is selected, PROHIBIT constraints are required to
prevent the SelectMAP-port pins from being used as user
I/O.
2. Drive data onto D[7:0]. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
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3. At the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance instead
occurs on the first clock after BUSY goes Low, and the
data must be held until this has happened.
4. Repeat steps 2 and 3 until all the data has been sent.
5. De-assert CS and WRITE.
Table 11: SelectMAP Write Timing Characteristics
Description
Symbol
/T
SMDCC SMCCD
Units
ns, min
D
Setup/Hold
1/2
3/4
5/6
7
T
5.0 / 1.7
7.0 / 1.7
7.0 / 1.7
12.0
0-7
CS Setup/Hold
T
/T
ns, min
SMCSCC SMCCCS
WRITE Setup/Hold
T
/T
ns, min
SMCCW SMWCC
CCLK
BUSY Propagation Delay
Maximum Frequency
T
ns, max
MHz, max
MHz, max
SMCKBY
F
66
CC
Maximum Frequency with no handshake
F
50
CCNH
CCLK
3
4
CS
5
6
WRITE
1
2
DATA[0:7]
BUSY
7
No Write
Write
No Write
Write
DS022_45_071702
Figure 17: Write Operations
A flowchart for the write operation is shown in Figure 18.
Note that if CCLK is slower than f , the FPGA never
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
CCNH
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in Figure 19.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
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Apply Power
FPGA starts to clear
configuration memory.
PROGRAM
from Low
to High
No
FPGA makes a final
clearing pass and releases
INIT when finished.
Yes
If used to delay
configuration
Release INIT
Low
INIT?
High
Set WRITE = Low
Enter Data Source
Sequence A
On first FPGA
Set CS = Low
Apply Configuration Byte
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
High
Busy?
Low
No
End of Data?
Yes
If no errors,
first FPGAs enter start-up phase
releasing DONE.
On first FPGA
Set CS = High
If no errors,
later FPGAs enter start-up phase
releasing DONE.
For any other FPGAs
Repeat Sequence A
Disable Data Source
Set WRITE = High
When all DONE pins
are released, DONE goes High
and start-up sequences complete.
Configuration Completed
ds003_17_090602
Figure 18: SelectMAP Flowchart for Write Operations
CCLK
CS
WRITE
DATA[0:7]
BUSY
Abort
DS022_46_071702
Figure 19: SelectMAP Write Abort Waveforms
PROGRAM pin must be pulled High prior to reconfiguration.
A Low on the PROGRAM pin resets the TAP controller and
no JTAG operations can be performed.
Boundary Scan Mode
In the Boundary Scan mode, configuration is done through
the IEEE 1149.1 Test Access Port. Note that the
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Configuration through the TAP uses the CFG_IN instruc-
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus.
Configuration and readback via the TAP is always available.
The Boundary Scan mode is selected by a <101> or <001>
on the mode pins (M2, M1, M0). For details on TAP charac-
teristics, refer to XAPP139.
The following steps are required to configure the FPGA
through the Boundary Scan port (when using TCK as a
start-up clock).
Configuration Sequence
The configuration of Virtex-E devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
1. Load the CFG_IN instruction into the Boundary Scan
instruction register (IR).
2. Enter the Shift-DR (SDR) state.
3. Shift a configuration bitstream into TDI.
4. Return to Run-Test-Idle (RTI).
5. Load the JSTART instruction into IR.
6. Enter the SDR state.
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura-
tion process can also be initiated by asserting PROGRAM.
The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is sig-
nalled by DONE going High.
7. Clock TCK through the startup sequence.
8. Return to RTI.
The power-up timing of configuration signals is shown in
Figure 20.
Vcc
TPOR
PROGRAM
TPL
INIT
TICCK
CCLK OUTPUT or INPUT
M0, M1, M2
(Required)
VALI
ds022_020_071201
Figure 20: Power-Up Timing Configuration Signals
The corresponding timing characteristics are listed in
Table 12.
Table 12: Power-up Timing Characteristics
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
Description
Symbol
Value
2.0
Units
ms, max
μs, max
μs, min
μs, max
ns, min
1
Power-on Reset
T
POR
Program Latency
T
100.0
0.5
PL
CCLK (output) Delay
T
Start-Up Sequence
ICCK
4.0
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
Program Pulse Width
T
300
PROGRAM
Notes:
1.
T
POR delay is the initialization time required after VCCINT and
VCCO in Bank 2 reach the recommended operating voltage.
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
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the internal storage elements to begin changing state in
response to the logic and the user clock.
dent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.
The relative timing of these events can be changed. In addi-
tion, the GTS, GSR, and GWE events can be made depen-
Readback
The configuration data stored in the Virtex-E configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUT RAMs, and block RAMs. This capa-
bility is used for real-time debugging. For more detailed
information, see application note XAPP138 “Virtex FPGA
Series Configuration and Readback”.
Design Considerations
This section contains more detailed design information on
the following features.
high-speed signal. A multiplied clock also provides design-
ers the option of time-domain-multiplexing, using one circuit
twice per clock cycle, consuming less area than two copies
of the same circuit. Two DLLs in can be connected in series
to increase the effective clock multiplication factor to four.
•
•
•
Delay-Locked Loop . . . see page 19
BlockRAM . . . see page 24
SelectI/O . . . see page 31
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to deskew a board level clock between multiple devices.
Using DLLs
The Virtex-E FPGA series provides up to eight fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits which improve and
simplify system level design.
In order to guarantee the system clock establishes prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL
achieves lock.
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance clocks.
Introduction
Library DLL Symbols
As FPGAs grow in size, quality on-chip clock distribution
becomes increasingly important. Clock skew and clock
delay impact device performance and the task of managing
clock skew and clock delay with conventional clock trees
becomes more difficult in large devices. The Virtex-E series
of devices resolve this potential problem by providing up to
eight fully digital dedicated on-chip DLL circuits, which pro-
vide zero propagation delay and low clock skew between
output clock signals distributed throughout the device.
Figure 21 shows the simplified Xilinx library DLL macro
symbol, BUFGDLL. This macro delivers a quick and effi-
cient way to provide a system clock with zero propagation
delay throughout the device. Figure 22 and Figure 23 show
the two library DLL primitives. These symbols provide
access to the complete set of DLL features when imple-
menting more complex applications.
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network min-
imizes clock skews due to loading differences. By monitor-
ing a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the indi-
vidual clock loads within the device.
I
O
0ns
ds022_25_121099
Figure 21: Simplified DLL Macro Symbol BUFGDLL
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at 100
MHz. This technique can simplify board design because the
clock path on the board no longer distributes such a
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GDLL requires an external signal source clock. Therefore,
only an external input port can source the signal that drives
the BUFGDLL I pin.
CLKDLL
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
Clock Output — O
The clock output pin O represents a delay-compensated
version of the source clock (I) signal. This signal, sourced by
a global clock buffer BUFG symbol, takes advantage of the
dedicated global clock routing resources of the device.
CLK2X
CLKDV
LOCKED
RST
The output clock has a 50-50 duty cycle unless you deacti-
vate the duty cycle correction property.
ds022_26_121099
Figure 22: Standard DLL Symbol CLKDLL
CLKDLL Primitive Pin Descriptions
The library CLKDLL primitives provide access to the com-
plete set of DLL features needed when implementing more
complex applications with the DLL.
CLKDLLHF
CLKIN
CLKFB
CLK0
CLK180
Source Clock Input — CLKIN
The CLKIN pin provides the user source clock (the clock
signal on which the DLL operates) to the DLL. The CLKIN
frequency must fall in the ranges specified in the data sheet.
A global clock buffer (BUFG) driven from another CLKDLL,
one of the global clock input buffers (IBUFG), or an
IO_LVDS_DLL pin on the same edge of the device (top or
bottom) must source this clock signal. There are four
IO_LVDS_DLL input pins that can be used as inputs to the
DLLs. This makes a total of eight usable input pins for DLLs
in the Virtex-E family.
CLKDV
RST
LOCKED
ds022_027_121099
Figure 23: High Frequency DLL Symbol CLKDLLHF
BUFGDLL Pin Descriptions
Use the BUFGDLL macro as the simplest way to provide
zero propagation delay for a high-fanout on-chip clock from
an external input. This macro uses the IBUFG, CLKDLL and
BUFG primitives to implement the most basic DLL applica-
tion as shown in Figure 24.
Feedback Clock Input — CLKFB
The DLL requires a reference or feedback signal to provide
the delay-compensated output. Connect only the CLK0 or
CLK2X DLL outputs to the feedback clock input (CLKFB)
pin to provide the necessary feedback to the DLL. The feed-
back clock input can also be provided through one of the fol-
lowing pins.
IBUFG
BUFG
CLKDLL
I
O
I
O
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
IBUFG - Global Clock Input Pad
CLK2X
IO_LVDS_DLL - the pin adjacent to IBUFG
CLKDV
LOCKED
If an IBUFG sources the CLKFB pin, the following special
rules apply.
RST
1. An external input port must source the signal that drives
the IBUFG I pin.
ds022_28_121099
Figure 24: BUFGDLL Schematic
2. The CLK2X output must feedback to the device if both
the CLK0 and CLK2X outputs are driving off chip
devices.
This symbol does not provide access to the advanced clock
domain controls or to the clock multiplication or clock divi-
sion features of the DLL. This symbol also does not provide
access to the RST, or LOCKED pins of the DLL. For access
to these features, a designer must use the library DLL prim-
itives described in the following sections.
3. That signal must directly drive only OBUFs and nothing
else.
These rules enable the software determine which DLL clock
output sources the CLKFB pin.
Source Clock Input — I
Reset Input — RST
The I pin provides the user source clock, the clock signal on
which the DLL operates, to the BUFGDLL. For the BUF-
GDLL macro the source clock frequency must fall in the low
frequency range as specified in the data sheet. The BUF-
When the reset pin RST activates the LOCKED signal deac-
tivates within four source clock cycles. The RST pin, active
High, must either connect to a dynamic signal or tied to
Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
ground. As the DLL delay taps reset to zero, glitches can
occur on the DLL clock output pins. Activation of the RST
pin can also severely affect the duty cycle of the clock out-
put pins. Furthermore, the DLL output clocks no longer
deskew with respect to one another. For these reasons,
rarely use the reset pin unless re-configuring the device or
changing the input frequency.
The timing diagrams in Figure 25 illustrate the DLL clock
output characteristics.
0
90 180 270
0
90 180 270
t
CLKIN
CLK2X
2x Clock Output — CLK2X
CLKDV_DIVIDE=2
The output pin CLK2X provides a frequency-doubled clock
with an automatic 50/50 duty-cycle correction. Until the
CLKDLL has achieved lock, the CLK2X output appears as a
1x version of the input clock with a 25/75 duty cycle. This
behavior allows the DLL to lock on the correct edge with
respect to source clock. This pin is not available on the
CLKDLLHF primitive.
CLKDV
DUTY_CYCLE_CORRECTION=FALSE
CLK0
CLK90
CLK180
CLK270
Clock Divide Output — CLKDV
The clock divide output pin CLKDV provides a lower fre-
quency version of the source clock. The CLKDV_DIVIDE
property controls CLKDV such that the source clock is
divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.
DUTY_CYCLE_CORRECTION=TRUE
CLK0
CLK90
CLK180
CLK270
This feature provides automatic duty cycle correction such
that the CLKDV output pin always has a 50/50 duty cycle,
with the exception of noninteger divides in HF mode, where
the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.
ds022_29_121099
1x Clock Outputs — CLK[0|90|180|270]
Figure 25: DLL Output Characteristics
The 1x clock output pin CLK0 represents a delay-compen-
sated version of the source clock (CLKIN) signal. The
CLKDLL primitive provides three phase-shifted versions of
the CLK0 signal while CLKDLLHF provides only the 180
phase-shifted version. The relationship between phase shift
and the corresponding period shift appears in Table 13.
The DLL provides duty cycle correction on all 1x clock out-
puts such that all 1x clock outputs by default have a 50/50
duty cycle. The DUTY_CYCLE_CORRECTION property
(TRUE by default), controls this feature. In order to deacti-
vate the DLL duty cycle correction, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
Table 13: Relationship of Phase-Shifted Output Clock
to Period Shift
Phase (degrees)
Period Shift (percent)
The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).
0
0%
90
25%
50%
75%
180
270
Locked Output — LOCKED
To achieve lock, the DLL might need to sample several thou-
sand clock cycles. After the DLL achieves lock, the
LOCKED signal activates. The DLL timing parameter sec-
tion of the data sheet provides estimates for locking times.
To guarantee that the system clock is established prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL locks.
The STARTUP_WAIT property activates this feature.
Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other spuri-
ous movement. In particular the CLK2X output appears as a
1x clock with a 25/75 duty cycle.
DS022-2 (v2.8) January 16, 2006
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
DLL Properties
Input Clock
Properties provide access to some of the Virtex-E series
DLL features, (for example, clock division and duty cycle
correction).
The output clock signal of a DLL, essentially a delayed ver-
sion of the input clock signal, reflects any instability on the
input clock in the output waveform. For this reason the qual-
ity of the DLL input clock relates directly to the quality of the
output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the data sheet.
Duty Cycle Correction Property
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, exhibiting a 50/50 duty
cycle. The DUTY_CYCLE_CORRECTION property (by
default TRUE) controls this feature. To deactivate the DLL
duty-cycle correction for the 1x clock outputs, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol.
In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially available
quartz crystal oscillator. For example, most crystal oscilla-
tors produce an output waveform with a frequency tolerance
of 100 PPM, meaning 0.01 percent change in the clock
period. The DLL operates reliably on an input waveform with
a frequency drift of up to 1 ns — orders of magnitude in
excess of that needed to support any crystal oscillator in the
industry. However, the cycle-to-cycle jitter must be kept to
less than 300 ps in the low frequencies and 150 ps for the
high frequencies.
Clock Divide Property
The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.
Input Clock Changes
Startup Delay Property
Changing the period of the input clock beyond the maximum
drift amount requires a manual reset of the CLKDLL. Failure
to reset the DLL produces an unreliable lock signal and out-
put clock.
This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the device con-
figuration DONE signal waits until the DLL locks before
going to High.
It is possible to stop the input clock with little impact to the
DLL. Stopping the clock should be limited to less than
100 μs to keep device cooling to a minimum. The clock
should be stopped during a Low phase, and when restored
the full High period should be seen. During this time,
LOCKED stays High and remains High when the clock is
restored.
Virtex-E DLL Location Constraints
As shown in Figure 26, there are four additional DLLs in the
Virtex-E devices, for a total of eight per Virtex-E device.
These DLLs are located in silicon, at the top and bottom of
the two innermost block SelectRAM columns. The location
constraint LOC, attached to the DLL symbol with the identi-
fier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,
or DLL3P, controls the DLL location.
When the clock is stopped, one to four more clocks are still
observed as the delay line is flushed. When the clock is
restarted, the output clocks are not observed for one to four
clocks as the delay line is filled. The most common case is
two or three clocks.
The LOC property uses the following form:
LOC = DLL0P
In a similar manner, a phase shift of the input clock is also
possible. The phase shift propagates to the output one to
four clocks after the original shift, with no disruption to the
CLKDLL control.
DLL-3S DLL-3P
DLL-2P DLL-2S
B
R
A
B
R
A
B
R
A
B
R
A
Output Clocks
M
M
M
M
As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or they can route directly to destination
clock pins. The only BUFGs that the DLL clock outputs can
drive are the two on the same edge of the device (top or bot-
tom). In addition, the CLK2X output of the secondary DLL
can connect directly to the CLKIN of the primary DLL in the
same quadrant.
Bottom Right
Half Edge
DLL-1S DLL-1P
DLL-0P DLL-0S
x132_14_100799
Figure 26: Virtex Series DLLs
Design Factors
Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Useful Application Examples
Virtex-E Device
The Virtex-E DLL can be used in a variety of creative and
useful applications. The following examples show some of
the more common applications. The Verilog and VHDL
example files are available at:
CLKDLL
IBUFG
OBUF
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
IBUFG
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
CLK2X
CLKDV
LOCKED
Standard Usage
RST
The circuit shown in Figure 27 resembles the BUFGDLL
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
CLKDLL
BUFG
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
CLKDLL
IBUFG
BUFG
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLK2X
RST
CLKDV
LOCKED
OBUF
IBUF
RST
ds022_028_121099
Non-Virtex-E Chip
Non-Virtex-E Chip
Figure 27: Standard DLL Implementation
Other Non_Virtex-E Chips
Board Level Deskew of Multiple Non-Virtex-E
Devices
ds022_029_121099
Figure 28: DLL Deskew of Board Level Clock
The circuit shown in Figure 28 can be used to deskew a
system clock between a Virtex-E chip and other non-Vir-
tex-E chips on the same board. This application is com-
monly used when the Virtex-E device is used in conjunction
with other standard products such as SRAM or DRAM
devices. While designing the board level route, ensure that
the return net delay to the source equals the delay to the
other chips involved.
Board-level deskew is not required for low-fanout clock net-
works. It is recommended for systems that have fanout lim-
itations on the clock network, or if the clock distribution chip
cannot handle the load.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
The dll_mirror_1 files in the xapp132.zip file show the
VHDL and Verilog implementation of this circuit.
Deskew of Clock and Its 2x Multiple
The circuit shown in Figure 29 implements a 2x clock multi-
plier and also uses the CLK0 clock output with a zero ns
skew between registers on the same chip. Alternatively, a
clock divider circuit can be implemented using similar con-
nections.
CLKDLL
IBUFG
BUFG
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
BUFG
OBUF
CLK2X
CLKDV
LOCKED
IBUF
RST
ds022_030_121099
Figure 29: DLL Deskew of Clock and 2x Multiple
DS022-2 (v2.8) January 16, 2006
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Because any single DLL can access only two BUFGs at
most, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
new capabilities allowing the FPGA designer to simplify
designs.
Operating Modes
The dll_2x files in the xapp132.zip file show the VHDL and
Verilog implementation of this circuit.
VIrtex-E block SelectRAM+ memory supports two operating
modes:
•
•
Read Through
Write Back
Virtex-E 4x Clock
Two DLLs located in the same half-edge (top-left, top-right,
bottom-right, bottom-left) can be connected together, with-
out using a BUFG between the CLKDLLs, to generate a 4x
clock as shown in Figure 30. Virtex-E devices, like the Virtex
devices, have four clock networks that are available for inter-
nal deskewing of the clock. Each of the eight DLLs have
access to two of the four clock networks. Although all the
DLLs can be used for internal deskewing, the presence of
two GCLKBUFs on the top and two on the bottom indicate
that only two of the four DLLs on the top (and two of the four
DLLs on the bottom) can be used for this purpose.
Read Through (one clock edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the out-
puts, depending on whether a faster clock-to-out versus
set-up time is desired. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the
read pulse clock.
CLKDLL-S
IBUFG
Write Back (one clock edge)
CLKIN
CLKFB
CLK0
CLK90
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.
CLK180
CLK270
CLK2X
CLKDV
INV
Block SelectRAM+ Characteristics
RST
LOCKED
•
All inputs are registered with the port clock and have a
set-up to clock timing specification.
CLKDLL-P
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
•
All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
The block SelectRAMs are true SRAM memories and
do not have a combinatorial path from the address to
the output. The LUT SelectRAM+ cells in the CLBs are
still available with this function.
BUFG
OBUF
CLK2X
CLKDV
•
•
RST
LOCKED
ds022_031_041901
The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
Figure 30: DLL Generation of 4x Clock in Virtex-E
Devices
•
•
A write operation requires only one clock edge.
A read operation requires only one clock edge.
The dll_4xe files in the xapp132.zip file show the DLL imple-
mentation in Verilog for Virtex-E devices. These files can be
found at:
The output ports are latched with a self timed circuit to guar-
antee a glitch free read. The state of the output port does
not change until the port executes another read or write
operation.
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
Using Block SelectRAM+ Features
The Virtex FPGA Series provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block SelectRAM+
memory can be independently configured as a read/write
port, a read port, a write port, and can be configured to a
specific data width. The block SelectRAM+ memory offers
Library Primitives
Figure 31 and Figure 32 show the two generic library block
SelectRAM+ primitives. Table 14 describes all of the avail-
able primitives for synthesis and simulation.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Port Signals
Each block SelectRAM+ port operates independently of the
others while accessing the same set of 4096 memory cells.
RAMB4_S#_S#
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
DOA[#:0]
Table 15 describes the depth and width aspect ratios for the
block SelectRAM+ memory.
Table 15: Block SelectRAM+ Port Aspect Ratios
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
1
2
DOB[#:0]
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
4
ds022_032_121399
8
Figure 31: Dual-Port Block SelectRAM+ Memory
16
256
RAMB4_S#
Clock—CLK[A|B]
WE
EN
Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time refer-
enced to the CLK pin.
RST
CLK
DO[#:0]
ADDR[#:0]
DI[#:0]
ds022_033_121399
Enable—EN[A|B]
Figure 32: Single-Port Block SelectRAM+ Memory
The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the mem-
ory cells.
Table 14: Available Library Primitives
Primitive
RAMB4_S1
Port A Width
Port B Width
N/A
1
Write Enable—WE[A|B]
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
RAMB4_S2
Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the con-
tents of the memory cells referenced by the address bus
reflect on the data out bus.
2
1
4
8
16
N/A
2
Reset—RST[A|B]
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
RAMB4_S4
The reset pin forces the data output bus latches to zero syn-
chronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.
2
4
4
8
16
N/A
4
Address Bus—ADDR[A|B]<#:0>
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
RAMB4_S8
The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in Table 15.
8
16
N/A
8
Data In Bus—DI[A|B]<#:0>
The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width, as
shown in Table 15.
RAMB4_S8_S8
RAMB4_S8_S16
RAMB4_S16
8
16
N/A
16
16
RAMB4_S16_S16
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16 shows low order address mapping for each port
width.
Data Output Bus—DO[A|B]<#:0>
The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in Table 15.
Table 16: Port Address Mapping
Port
Port
Width
Addresses
1
4095...
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Inverting Control Pins
The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration
option.
2
4
2047...
1023...
511...
07
06
05
04
03
02
01
00
03
02
01
00
8
01
00
16
255...
00
Address Mapping
Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port.
Creating Larger RAM Structures
The block SelectRAM+ columns have specialized routing to
allow cascading blocks together with minimal routing delays.
This achieves wider or deeper RAM structures with a smaller
timing penalty than when using normal routing channels.
The physical RAM location addressed for a particular width
are described in the following formula (of interest only when
the two ports use different aspect ratios).
Location Constraints
Start = ((ADDR
+1) * Width ) –1
port
port
Block SelectRAM+ instances can have LOC properties
attached to them to constrain the placement. The block
SelectRAM+ placement locations are separate from the
CLB location naming convention, allowing the LOC proper-
ties to transfer easily from array to array.
End = ADDR
* Width
port
port
The LOC properties use the following form.
LOC = RAMB4_R#C#
RAMB4_R0C0 is the upper left RAMB4 location on the
device.
Conflict Resolution
The block SelectRAM+ memory is a true dual-read/write
port RAM that allows simultaneous access of the same
memory cell from both ports. When one port writes to a
given memory cell, the other port must not address that
memory cell (for a write or a read) within the clock-to-clock
setup window. The following lists specifics of port and mem-
ory cell write conflict resolution.
Single Port Timing
Figure 33 shows a timing diagram for a single port of a block
SelectRAM+ memory. The block SelectRAM+ AC switching
characteristics are specified in the data sheet. The block
SelectRAM+ memory is initially disabled.
At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus con-
tains the contents of the memory location, 0x00, as indi-
cated by the ADDR bus.
•
If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.
•
If one port attempts a read of the same memory cell
the other simultaneously writes, violating the
At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors the
DI bus. The DI bus is written to the memory location 0x0F.
clock-to-clock setup requirement, the following occurs.
-
-
The write succeeds
The data out on the writing port accurately reflects
the data written.
At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
and the WE pin is Low indicating a read operation. The DO
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.
-
The data out on the reading port is invalid.
Conflicts do not cause any physical damage.
At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low
Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
indicating that the block SelectRAM+ memory is now dis-
abled. The DO bus retains the last value.
the contents of the memory are correct, but the read port
has invalid data.
At the first rising edge of the CLKA, memory location 0x00 is
to be written with the value 0xAAAA and is mirrored on the
DOA bus. The last operation of Port B was a read to the
same memory location 0x00. The DOB bus of Port B does
not change with the new value on Port A, and retains the
last read value. A short time later, Port B executes another
read to memory location 0x00, and the DOB bus now
reflects the new memory value written by Port A.
Dual Port Timing
Figure 34 shows a timing diagram for a true dual-port
read/write block SelectRAM+ memory. The clock on port A
has a longer period than the clock on Port B. The timing
parameter T
, (clock-to-clock set-up) is shown on this
BCCS
diagram. The parameter, T
gram. All other timing parameters are identical to the single
port version shown in Figure 33.
is violated once in the dia-
BCCS
At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
T
is only of importance when the address of both ports
BCCS
are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is vio-
lated for a WRITE-WRITE condition, the contents of the
memory at that location are invalid. When the clock-to-clock
set-up parameter is violated for a WRITE-READ condition,
memory location without violating the T
parameter and
BCCS
the DOB reflects the new memory values written by Port A.
T
T
BPWL
BPWH
CLK
T
T
BACK
ADDR
00
0F
7E
8F
BDCK
DDDD
CCCC
BBBB
2222
DIN
DOUT
EN
T
BCKO
MEM (00)
CCCC
MEM (7E)
T
BECK
RST
WE
T
BWCK
DISABLED
READ
WRITE
READ
DISABLED
ds022_0343_121399
Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory
DS022-2 (v2.8) January 16, 2006
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
T
BCCS
VIOLATION
CLK_A
ADDR_A
00
7E
0F
0F
7E
EN_A
WE_A
DI_A
T
BCCS
T
BCCS
AAAA
9999
AAAA
0000
1111
AAAA
9999
AAAA
UNKNOWN
2222
DO_A
CLK_B
ADDR_B
00
00
7E
0F
0F
7E
1A
EN_B
WE_B
DI_B
1111
1111
1111
BBBB
1111
2222
FFFF
DO_B
MEM (00)
AAAA
9999
BBBB
UNKNOWN
2222
FFFF
ds022_035_121399
Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory
At the third rising edge of CLKA, the T
parameter is
presently support generics. The initialization values instead
attach as attributes to the RAM by a built-in Synopsys
dc_script. The translate_off statement stops synthesis
translation of the generic statements. The following code
illustrates a module that employs these techniques.
BCCS
violated with two writes to memory location 0x0F. The DOA
and DOB buses reflect the contents of the DIA and DIB
buses, but the stored value at 0x0F is invalid.
At the fourth rising edge of CLKA, a read operation is per-
formed at memory location 0x0F and invalid data is present
on the DOA bus. Port B also executes a read operation to
memory location 0x0F and also reads invalid data.
Table 17: RAM Initialization Properties
Property
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0a
INIT_0b
INIT_0c
INIT_0d
INIT_0e
INIT_0f
Memory Cells
255 to 0
At the fifth rising edge of CLKA a read operation is per-
511 to 256
formed that does not violate the T
parameter to the
BCCS
767 to 512
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
1023 to 768
1279 to 1024
1535 to 1280
1791 to 2047
2047 to 1792
2303 to 2048
2559 to 2304
2815 to 2560
3071 to 2816
3327 to 3072
3583 to 3328
3839 to 3584
4095 to 3840
Initialization
The block SelectRAM+ memory can initialize during the
device configuration sequence. The 16 initialization properties
of 64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in Table 17. Any initial-
ization properties not explicitly set configure as zeros. Partial
initialization strings pad with zeros. Initialization strings
greater than 64 hex values generate an error. The RAMs can
be simulated with the initialization values using generics in
VHDL simulators and parameters in Verilog simulators.
Initialization in VHDL and Synopsys
The block SelectRAM+ structures can be initialized in VHDL
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization. Synopsys FPGA compiler does not
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Virtex™-E 1.8 V Field Programmable Gate Arrays
address bus of Port B to 0 (GND), allows a 32-bit wide sin-
gle port RAM to be created.
Initialization in Verilog and Synopsys
The block SelectRAM+ structures can be initialized in Verilog
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a def-
param to pass the initialization. The Synopsys FPGA com-
piler does not presently support defparam. The initialization
values instead attach as attributes to the RAM by a built-in
Synopsys dc_script. The translate_off statement stops syn-
thesis translation of the defparam statements. The following
code illustrates a module that employs these techniques.
Creating Two Single-Port RAMs
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single RAM to be split into
two single port memories of 2K bits each as shown in
Figure 36.
RAMB4_S4_S16
WE1
EN1
WEA
ENA
RST1
DOA[3:0]
DO1[3:0]
RSTA
CLK1
, ADDR1[8:0]
DI1[3:0]
CLKA
ADDRA[9:0]
DIA[3:0]
Design Examples
V
CC
Creating a 32-bit Single-Port RAM
WE2
EN2
WEB
ENB
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single port, 128 deep by
32-bit wide RAM to be created using a single block
SelectRAM+ cell as shown in Figure 35.
RST2
CLK2
GND, ADDR2[6:0]
DI2[15:0]
RSTB
CLKB
ADDRB[7:0]
DIB[15:0]
DOB[15:0]
DO2[15:0]
ds022_037_121399
Figure 36: 512 x 4 RAM and 128 x 16 RAM
RAMB4_S16_S16
WE
WEA
ENA
RSTA
CLKA
ADDRA[7:0]
DIA[15:0]
In this example, a 512K x 4 RAM (Port A) and a 128 x 16
RAM (Port B) are created out of a single block SelectRAM+.
The address space for the RAM is split by fixing the MSB of
EN
RST
CLK
DOA[15:0]
DO[31:16]
ADDR[6:0], V
CC
DI[31:16]
Port A to 1 (V ) for the upper 2K bits and the MSB of Port
B to 0 (GND) for the lower 2K bits.
CC
WE
EN
RST
WEB
ENB
RSTB
CLKB
DOB[15:0]
DO[15:0]
CLK
Block Memory Generation
ADDR[6:0], GND
ADDRB[7:0]
DIB[15:0]
DI[15:0]
The CoreGen program generates memory structures using
the block SelectRAM+ features. This program outputs
VHDL or Verilog simulation code templates and an EDIF file
for inclusion in a design.
ds022_036_121399
Figure 35: Single Port 128 x 32 RAM
Interleaving the memory space, setting the LSB of the
address bus of Port A to 1 (V ), and the LSB of the
CC
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Virtex™-E 1.8 V Field Programmable Gate Arrays
VHDL Initialization Example
library IEEE;
use IEEE.std_logic_1164.all;
entity MYMEM is
port (CLK, WE:in std_logic;
ADDR: in std_logic_vector(8 downto 0);
DIN: in std_logic_vector(7 downto 0);
DOUT: out std_logic_vector(7 downto 0));
end MYMEM;
architecture BEHAVE of MYMEM is
signal logic0, logic1: std_logic;
component RAMB4_S8
--synopsys translate_off
generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255
downto 0)
:= X"0000000000000000000000000000000000000000000000000000000000000000");
--synopsys translate_on
port (WE, EN, RST, CLK: in STD_LOGIC;
ADDR: in STD_LOGIC_VECTOR(8 downto 0);
DI: in STD_LOGIC_VECTOR(7 downto 0);
DO: out STD_LOGIC_VECTOR(7 downto 0));
end component;
--synopsys dc_script_begin
--set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
--set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
--synopsys dc_script_end
begin
logic0 <=’0’;
logic1 <=’1’;
ram0: RAMB4_S8
--synopsys translate_off
generic map (
INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")
--synopsys translate_on
port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT);
end BEHAVE;
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Verilog Initialization Example
module MYMEM (CLK, WE, ADDR, DIN, DOUT);
input CLK, WE;
input [8:0] ADDR;
input [7:0] DIN;
output [7:0] DOUT;
wire logic0, logic1;
//synopsys dc_script_begin
//set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
//set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
//synopsys dc_script_end
assign logic0 = 1’b0;
assign logic1 = 1’b1;
RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),
.DO(DOUT));
//synopsys translate_off
defparam ram0.INIT_00 =
256h’0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;
defparam ram0.INIT_01 =
256h’FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;
//synopsys translate_on
endmodule
Using SelectI/O
The Virtex-E FPGA series includes a highly configurable,
high-performance I/O resource, called SelectI/O™ to pro-
vide support for a wide variety of I/O standards. The
SelectI/O resource is a robust set of features including pro-
grammable control of output drive strength, slew rate, and
input delay and hold time. Taking advantage of the flexibility
and SelectI/O features and the design considerations
described in this document can improve and simplify sys-
tem level design.
Each SelectI/O block can support up to 20 I/O standards.
Supporting such a variety of I/O standards allows the sup-
port of a wide variety of applications, from general purpose
standard applications to high-speed low-voltage memory
buses.
SelectI/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL out-
put buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak “keeper” circuit ideal for
use in external bussing applications.
Introduction
Each Input/Output Block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for high perfor-
mance I/O becomes more important.
The input buffer has an optional delay element used to guar-
antee a zero hold time requirement for input signals regis-
tered within the IOB.
While chip-to-chip delays have an increasingly substantial
impact on overall system speed, the task of achieving the
desired system performance becomes more difficult with
the proliferation of low-voltage I/O standards. SelectI/O, the
revolutionary input/output resources of Virtex-E devices,
resolve this potential problem by providing a highly config-
urable, high-performance alternative to the I/O resources of
more conventional programmable devices. Virtex-E SelectI/O
features combine the flexibility and time-to-market advan-
tages of programmable logic with the high performance pre-
viously available only with ASICs and custom ICs.
The Virtex-E SelectI/O features also provide dedicated
resources for input reference voltage (V
) and output
REF
source voltage (V
), along with a convenient banking
CCO
system that simplifies board design.
By taking advantage of the built-in features and wide variety
of I/O standards supported by the SelectI/O features, sys-
tem-level design and board design can be greatly simplified
and improved.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Fundamentals
Overview of Supported I/O Standards
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored spe-
cifically to the needs of that application. The bus I/O stan-
dards provide specifications to other vendors who create
products designed to interface with these applications.
Each standard often has its own specifications for current,
voltage, I/O buffering, and termination techniques.
This section provides a brief overview of the I/O standards
supported by all Virtex-E devices.
While most I/O standards specify a range of allowed volt-
ages, this document records typical voltage values only.
Detailed information on each specification can be found on
the Electronic Industry Alliance Jedec website at:
http://www.jedec.org
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly depen-
dent on the capability of the programmable logic device to
support an ever increasing variety of I/O standards
LVTTL — Low-Voltage TTL
The Low-Voltage TTL, or LVTTL standard is a general pur-
pose EIA/JESDSA standard for 3.3V applications that uses
an LVTTL input buffer and a Push-Pull output buffer. This
The SelectI/O resources feature highly configurable input
and output buffers which provide support for a wide variety
of I/O standards. As shown in Table 18, each buffer type can
support a variety of voltage requirements.
standard requires a 3.3V output source voltage (V
does not require the use of a reference voltage (V
), but
) or a
CCO
REF
termination voltage (V ).
TT
LVCMOS2 — Low-Voltage CMOS for 2.5 Volts
Table 18: Virtex-E Supported I/O Standards
The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2
standard is an extension of the LVCMOS standard
Board
(JESD 8.-5) used for general purpose 2.5V applications.
This standard requires a 2.5V output source voltage
Termination
Output Input Input
Voltage
(V
(V
(V
), but does not require the use of a reference voltage
I/O Standard
LVTTL
V
V
V
)
TT
CCO
CCO
CCO
REF
) or a board termination voltage (V ).
REF
TT
3.3
2.5
1.8
3.3
2.5
N/A
N/A
1.5
1.5
3.3
3.3
3.3
3.3
2.5
3.3
3.3
2.5
N/A
N/A
N/A
1.50
1.25
0.80
1.0
N/A
N/A
N/A
LVCMOS18 — 1.8 V Low Voltage CMOS
LVCMOS2
LVCMOS18
SSTL3 I & II
SSTL2 I & II
GTL
This standard is an extension of the LVCMOS standard. It is
used in general purpose 1.8 V applications. The use of a
1.8
reference voltage (V
) or a board termination voltage
REF
(V ) is not required.
TT
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
1.50
1.25
1.20
1.50
0.75
1.50
1.50
N/A
N/A
N/A
N/A
N/A
PCI — Peripheral Component Interface
The Peripheral Component Interface, or PCI standard spec-
ifies support for both 33 MHz and 66 MHz PCI bus applica-
tions. It uses a LVTTL input buffer and a Push-Pull output
buffer. This standard does not require the use of a reference
GTL+
voltage (V
) or a board termination voltage (V ), how-
REF
TT
HSTL I
0.75
0.90
1.50
1.32
N/A
N/A
N/A
N/A
ever, it does require a 3.3V output source voltage (V
).
CCO
GTL — Gunning Transceiver Logic Terminated
HSTL III & IV
CTT
The Gunning Transceiver Logic, or GTL standard is a
high-speed bus standard (JESD8.3) invented by Xerox. Xil-
inx has implemented the terminated variation for this stan-
dard. This standard requires a differential amplifier input
buffer and a Open Drain output buffer.
AGP-2X
PCI33_3
PCI66_3
BLVDS & LVDS
LVPECL
GTL+ — Gunning Transceiver Logic Plus
3.3
The Gunning Transceiver Logic Plus, or GTL+ standard is a
high-speed bus standard (JESD8.3) first used by the Pen-
tium Pro processor.
N/A
N/A
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic, or HSTL standard is a
general purpose high-speed, 1.5V bus standard sponsored
by IBM (EIA/JESD 8-6). This standard has four variations or
classes. SelectI/O devices support Class I, III, and IV. This
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Virtex™-E 1.8 V Field Programmable Gate Arrays
standard requires a Differential Amplifier input buffer and a
Push-Pull output buffer.
Library Symbols
The Xilinx library includes an extensive list of symbols
designed to provide support for the variety of SelectI/O fea-
tures. Most of these symbols represent variations of the five
generic SelectI/O symbols.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3V, or SSTL3 stan-
dard is a general purpose 3.3V memory bus standard also
sponsored by Hitachi and IBM (JESD8-8). This standard
has two classes, I and II. SelectI/O devices support both
classes for the SSTL3 standard. This standard requires a
Differential Amplifier input buffer and an Push-Pull output
buffer.
•
•
•
•
•
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
SSTL2 — Stub Series Terminated Logic for 2.5V
IBUF
The Stub Series Terminated Logic for 2.5V, or SSTL2 stan-
dard is a general purpose 2.5V memory bus standard spon-
sored by Hitachi and IBM (JESD8-9). This standard has two
classes, I and II. SelectI/O devices support both classes for
the SSTL2 standard. This standard requires a Differential
Amplifier input buffer and an Push-Pull output buffer.
Signals used as inputs to the Virtex-E device must source
an input buffer (IBUF) via an external input port. The generic
Virtex-E IBUF symbol appears in Figure 37. The extension
IBUF
I
O
CTT — Center Tap Terminated
The Center Tap Terminated, or CTT standard is a 3.3V
memory bus standard sponsored by Fujitsu (JESD8-4).
This standard requires a Differential Amplifier input buffer
and a Push-Pull output buffer.
x133_01_111699
Figure 37: Input Buffer (IBUF) Symbols
AGP-2X — Advanced Graphics Port
to the base name defines which I/O standard the IBUF
uses. The assumed standard is LVTTL when the generic
IBUF has no specified extension.
The Intel AGP standard is a 3.3V Advanced Graphics
Port-2X bus standard used with the Pentium II processor for
graphics applications. This standard requires a Push-Pull
output buffer and a Differential Amplifier input buffer.
The following list details the variations of the IBUF symbol:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IBUF
LVDS — Low Voltage Differential Signal
IBUF_LVCMOS2
IBUF_PCI33_3
IBUF_PCI66_3
IBUF_GTL
LVDS is a differential I/O standard. It requires that one data
bit is carried through two signal lines. As with all differential
signaling standards, LVDS has an inherent noise immunity
over single-ended I/O standards. The voltage swing
between two signal lines is approximately 350mV. The use
IBUF_GTLP
IBUF_HSTL_I
IBUF_HSTL_III
IBUF_HSTL_IV
IBUF_SSTL3_I
IBUF_SSTL3_II
IBUF_SSTL2_I
IBUF_SSTL2_II
IBUF_CTT
of a reference voltage (V
) or a board termination voltage
REF
(V ) is not required. LVDS requires the use of two pins per
TT
input or output. LVDS requires external resistor termination.
BLVDS — Bus LVDS
This standard allows for bidirectional LVDS communication
between two or more devices. The external resistor termi-
nation is different than the one for standard LVDS.
LVPECL — Low Voltage Positive Emitter Coupled
Logic
IBUF_AGP
IBUF_LVCMOS18
IBUF_LVDS
IBUF_LVPECL
LVPECL is another differential I/O standard. It requires two
signal lines for transmitting one data bit. This standard
specifies two pins per input or output. The voltage swing
between these two signal lines is approximately 850 mV.
When the IBUF symbol supports an I/O standard that
requires a V , the IBUF automatically configures as a dif-
The use of a reference voltage (V
) or a board termina-
REF
REF
ferential amplifier input buffer. The V
voltage must be
tion voltage (V ) is not required. The LVPECL standard
REF
TT
supplied on the V
pins. In the case of LVDS, LVPECL,
requires external resistor termination.
REF
and BLVDS, V
is not required.
REF
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The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
CLKDLLHF, or BUFG symbol. The generic Virtex-E IBUFG
symbol appears in Figure 39.
are eight independent V
banks internally. See Figure 38
REF
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
IBUFG
I
O
cally configured as a V
input. After placing a differential
REF
amplifier input signal within a given V
bank, the same
REF
external source must drive all I/O pins configured as a V
input.
x133_03_111699
REF
Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)
Symbol
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same stan-
dard. How to specify a specific location for the IBUF via the
LOC property is described below. Table 19 summarizes the
Virtex-E input standards compatibility requirements.
The extension to the base name determines which I/O stan-
dard is used by the IBUFG. With no extension specified for
the generic IBUFG symbol, the assumed standard is
LVTTL.
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.
The following list details variations of the IBUFG symbol.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IBUFG
IBUFG_LVCMOS2
IBUFG_PCI33_3
IBUFG_PCI66_3
IBUFG_GTL
When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher per-
formance. To delay the input signal, activate the delay ele-
ment with the DELAY=TRUE property.
IBUFG_GTLP
IBUFG_HSTL_I
IBUFG_HSTL_III
IBUFG_HSTL_IV
IBUFG_SSTL3_I
IBUFG_SSTL3_II
IBUFG_SSTL2_I
IBUFG_SSTL2_II
IBUFG_CTT
Table 19: Xilinx Input Standards Compatibility
Requirements
Rule 1 Standards with the same input V
, output V
,
CCO
CCO
and V
can be placed within the same bank.
REF
IBUFG_AGP
IBUFG_LVCMOS18
IBUFG_LVDS
Bank 0
Bank 1
GCLK3 GCLK2
IBUFG_LVPECL
When the IBUFG symbol supports an I/O standard that
requires a differential amplifier input, the IBUFG automati-
cally configures as a differential amplifier input buffer. The
low-voltage I/O standards with a differential amplifier input
Virtex-E
Device
require an external reference voltage input V
.
REF
GCLK1 GCLK0
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
Bank 5
Bank 4
are eight independent V
banks internally. See Figure 38
REF
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
ds022_42_012100
Figure 38: Virtex-E I/O Banks
cally configured as a V
input. After placing a differential
REF
amplifier input signal within a given V
external source must drive all I/O pins configured as a V
input.
bank, the same
REF
IBUFG
REF
Signals used as high fanout clock inputs to the Virtex-E
device should drive a global clock input buffer (IBUFG) via
an external input port in order to take advantage of one of
the four dedicated global clock distribution networks. The
output of the IBUFG should only drive a CLKDLL,
IBUFG placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard. The
LOC property can specify a location for the IBUFG.
As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP symbol
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Virtex™-E 1.8 V Field Programmable Gate Arrays
represents a combination of the LVTTL IBUFG and BUFG
symbols, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OBUF_PCI66_3
OBUF_GTL
OBUF_GTLP
Unlike previous architectures, the Virtex-E BUFGP symbol
can only be placed in a global clock pad location. The LOC
property can specify a location for the BUFGP.
OBUF_HSTL_I
OBUF_HSTL_III
OBUF_HSTL_IV
OBUF_SSTL3_I
OBUF_SSTL3_II
OBUF_SSTL2_I
OBUF_SSTL2_II
OBUF_CTT
OBUF
An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) symbol appears in
Figure 40.
The extension to the base name defines which I/O standard
the OBUF uses. With no extension specified for the generic
OBUF symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
OBUF_AGP
OBUF_LVCMOS18
OBUF_LVDS
OBUF_LVPECL
OBUF
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS packages support four V banks.
I
O
CCO
OBUF placement restrictions require that within a given
bank each OBUF share the same output source drive
x133_04_111699
V
CCO
Figure 40: Virtex-E Output Buffer (OBUF) Symbol
voltage. Input buffers of any type and output buffers that do
not require V can be placed within any V bank.
The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
CCO
CCO
Table 20 summarizes the Virtex-E output compatibility
requirements. The LOC property can specify a location for
the OBUF.
LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF symbol names is as follows:
Table 20: Output Standards Compatibility
Requirements
OBUF_<slew_rate>_<drive_strength>
Rule 1 Only outputs with standards that share compatible
V
can be used within the same bank.
CCO
where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
Rule 2 There are no placement restrictions for outputs
with standards that do not require a V
.
CCO
The following list details variations of the OBUF symbol.
V
Compatible Standards
CCO
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OBUF
3.3
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
OBUF_S_2
OBUF_S_4
OBUF_S_6
OBUF_S_8
OBUF_S_12
OBUF_S_16
OBUF_S_24
OBUF_F_2
OBUF_F_4
OBUF_F_6
OBUF_F_8
OBUF_F_12
OBUF_F_16
OBUF_F_24
OBUF_LVCMOS2
OBUF_PCI33_3
2.5
1.5
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
OBUFT
The generic 3-state output buffer OBUFT (see Figure 41)
typically implements 3-state outputs or bidirectional I/O.
The extension to the base name defines which I/O standard
OBUFT uses. With no extension specified for the generic
OBUFT symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUFT additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
LVTTL 3-state output buffers have selectable drive
strengths.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four V
banks.
CCO
The format for LVTTL OBUFT symbol names is as follows:
OBUFT_<slew_rate>_<drive_strength>
The SelectI/O OBUFT placement restrictions require that
within a given V bank each OBUFT share the same out-
CCO
put source drive voltage. Input buffers of any type and out-
put buffers that do not require V can be placed within
where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
CCO
the same V
bank.
CCO
The LOC property can specify a location for the OBUFT.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the OBUFT (PUL-
LUP, PULLDOWN, or KEEPER).
OBUFT
T
O
I
The weak “keeper” circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
x133_05_111699
an I/O standard that requires a V
have automatic place-
REF
Figure 41: 3-State Output Buffer Symbol (OBUFT)
ment of a V
in the bank with an OBUFT configured with
REF
a weak “keeper” circuit. This restriction does not affect most
circuit design as applications using an OBUFT configured
with a weak “keeper” typically implement a bidirectional I/O.
The following list details variations of the OBUFT symbol.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OBUFT
OBUFT_S_2
OBUFT_S_4
OBUFT_S_6
In this case the IBUF (and the corresponding V
explicitly placed.
) are
REF
The LOC property can specify a location for the OBUFT.
OBUFT_S_8
IOBUF
OBUFT_S_12
OBUFT_S_16
OBUFT_S_24
OBUFT_F_2
OBUFT_F_4
OBUFT_F_6
Use the IOBUF symbol for bidirectional signals that require
both an input buffer and a 3-state output buffer with an
active high 3-state pin. The generic input/output buffer
IOBUF appears in Figure 42.
The extension to the base name defines which I/O standard
the IOBUF uses. With no extension specified for the generic
IOBUF symbol, the assumed standard is LVTTL input buffer
and slew rate limited LVTTL with 12 mA drive strength for
the output buffer.
OBUFT_F_8
OBUFT_F_12
OBUFT_F_16
OBUFT_F_24
OBUFT_LVCMOS2
OBUFT_PCI33_3
OBUFT_PCI66_3
OBUFT_GTL
OBUFT_GTLP
OBUFT_HSTL_I
OBUFT_HSTL_III
OBUFT_HSTL_IV
OBUFT_SSTL3_I
OBUFT_SSTL3_II
OBUFT_SSTL2_I
OBUFT_SSTL2_II
OBUFT_CTT
The LVTTL IOBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL bidirectional buffers have selectable output drive
strengths.
The format for LVTTL IOBUF symbol names is as follows:
IOBUF_<slew_rate>_<drive_strength>
where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
OBUFT_AGP
OBUFT_LVCMOS18
OBUFT_LVDS
OBUFT_LVPECL
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Virtex™-E 1.8 V Field Programmable Gate Arrays
The low-voltage I/O standards with a differential amplifier
input require an external reference voltage input V
.
REF
IOBUF
T
I
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
IO
are eight independent V
banks internally. See Figure 38,
REF
page 34 for a representation of the Virtex-E I/O banks.
Within each bank approximately one of every six I/O pins is
O
automatically configured as a V
input. After placing a dif-
REF
ferential amplifier input signal within a given V
bank, the
REF
x133_06_111699
same external source must drive all I/O pins configured as a
input.
Figure 42: Input/Output Buffer Symbol (IOBUF)
V
REF
The following list details variations of the IOBUF symbol.
IOBUF placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IOBUF
The Virtex-E series supports eight banks for the HQ and PQ
IOBUF_S_2
IOBUF_S_4
IOBUF_S_6
packages. The CS package supports four V
banks.
CCO
Additional restrictions on the Virtex-E SelectI/O IOBUF
placement require that within a given V bank each
IOBUF_S_8
CCO
IOBUF must share the same output source drive voltage.
Input buffers of any type and output buffers that do not
IOBUF_S_12
IOBUF_S_16
IOBUF_S_24
IOBUF_F_2
require V
can be placed within the same V
bank.
CCO
CCO
The LOC property can specify a location for the IOBUF.
An optional delay element is associated with the input path
in each IOBUF. When the IOBUF drives an input flip-flop
within the IOB, the delay element activates by default to
ensure a zero hold-time requirement. Override this default
with the NODELAY=TRUE property.
IOBUF_F_4
IOBUF_F_6
IOBUF_F_8
IOBUF_F_12
IOBUF_F_16
IOBUF_F_24
IOBUF_LVCMOS2
IOBUF_PCI33_3
IOBUF_PCI66_3
IOBUF_GTL
In the case when the IOBUF does not drive an input flip-flop
within the IOB, the delay element de-activates by default to
provide higher performance. To delay the input signal, acti-
vate the delay element with the DELAY=TRUE property.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the IOBUF (PUL-
LUP, PULLDOWN, or KEEPER).
IOBUF_GTLP
IOBUF_HSTL_I
IOBUF_HSTL_III
IOBUF_HSTL_IV
IOBUF_SSTL3_I
IOBUF_SSTL3_II
IOBUF_SSTL2_I
IOBUF_SSTL2_II
IOBUF_CTT
SelectI/O Properties
Access to some of the SelectI/O features (for example, loca-
tion constraints, input delay, output drive strength, and slew
rate) is available through properties associated with these
features.
Input Delay Properties
IOBUF_AGP
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element activates by default to ensure a zero hold-time
requirement. Use the NODELAY=TRUE property to over-
ride this default.
IOBUF_LVCMOS18
IOBUF_LVDS
IOBUF_LVPECL
When the IOBUF symbol used supports an I/O standard
that requires a differential amplifier input, the IOBUF auto-
matically configures with a differential amplifier input buffer.
In the case when the IBUF does not drive a flip-flop within
the IOB, the delay element by default de-activates to pro-
vide higher performance. To delay the input signal, activate
the delay element with the DELAY=TRUE property.
DS022-2 (v2.8) January 16, 2006
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Flip-Flop/Latch Property
Design Considerations
The Virtex-E series I/O Block (IOB) includes an optional
register on the input path, an optional register on the output
path, and an optional register on the 3-state control pin. The
design implementation software automatically takes advan-
tage of these registers when the following option for the Map
program is specified.
Reference Voltage (VREF) Pins
Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (V ). Provide the
REF
V
as an external signal to the device.
REF
The voltage reference signal is “banked” within the device on
a half-edge basis such that for all packages there are eight
map –pr b <filename>
independent V
banks internally. See Figure 38 for a rep-
REF
Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.
resentation of the Virtex-E I/O banks. Within each bank
approximately one of every six I/O pins is automatically con-
figured as a V
input signal within a given V
source must drive all I/O pins configured as a V
input. After placing a differential amplifier
REF
Location Constraints
bank, the same external
REF
Specify the location of each SelectI/O symbol with the loca-
tion constraint LOC attached to the SelectI/O symbol. The
external port identifier indicates the value of the location
constrain. The format of the port identifier depends on the
package chosen for the specific design.
input.
REF
Within each V
bank, any input buffers that require a
REF
V
signal must be of the same type. Output buffers of any
REF
type and input buffers can be placed without requiring a ref-
erence voltage within the same V bank.
REF
The LOC properties use the following form:
LOC=A42
Output Drive Source Voltage (VCCO) Pins
Many of the low voltage I/O standards supported by
SelectI/O devices require a different output drive source
LOC=P37
voltage (V
). As a result each device can often have to
CCO
Output Slew Rate Property
support multiple output drive source voltages.
As mentioned above, a variety of symbol names provide the
option of choosing the desired slew rate for the output buff-
ers. In the case of the LVTTL output buffers (OBUF, OBUFT,
and IOBUF), slew rate control can be alternatively pro-
gramed with the SLEW= property. By default, the slew rate
for each output buffer is reduced to minimize power bus
transients when switching non-critical signals. The SLEW=
property has one of the two following values.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four V
banks.
CCO
Output buffers within a given V
bank must share the
CCO
same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the
V
voltage for Input V
voltage.
CCO
CCO
Transmission Line Effects
SLEW=SLOW
The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short dis-
tance. Transmission line delays vary with inductance and
capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.
SLEW=FAST
Output Drive Strength Property
The desired output drive strength can be additionally speci-
fied by choosing the appropriate library symbol. The Xilinx
library also provides an alternative method for specifying
this feature. For the LVTTL output buffers (OBUF, OBUFT,
and IOBUF, the desired drive strength can be specified with
the DRIVE= property. This property could have one of the
following seven values.
Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-
tent) termination or changes in the transmission line imped-
ance cause these reflections and can cause additional
delay in longer traces. As system speeds continue to
increase, the effect of I/O delays can become a limiting fac-
tor and therefore transmission line termination becomes
increasingly more important.
DRIVE=2
DRIVE=4
DRIVE=6
Termination Techniques
DRIVE=8
A variety of termination techniques reduce the impact of
transmission line effects.
DRIVE=12 (Default)
DRIVE=16
DRIVE=24
The following are output termination techniques:
•
•
•
•
None
Series
Parallel (Shunt)
Series and Parallel (Series-Shunt)
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Input termination techniques include the following.
Simultaneous Switching Guidelines
•
•
None
Parallel (Shunt)
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
These termination techniques can be applied in any combi-
nation. A generic example of each combination of termina-
tion methods appears in Figure 43.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Double Parallel Terminated
Unterminated
Z=50
VTT
VTT
Z=50
VREF
Unterminated Output Driving
a Parallel Terminated Input
Series Terminated Output Driving
a Parallel Terminated Input
VTT
VTT
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Z=50
VREF
Z=50
VREF
Series-Parallel Terminated Output
Driving a Parallel Terminated Input
VTT
VTT
Series Terminated Output
Z=50
VREF
Z=50
VREF
x133_07_111699
Table 21 provides guidelines for the maximum number of
simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce. See
Table 22 for the number of effective output power/ground pairs
for each Virtex-E device and package combination.
Figure 43: Overview of Standard Input and Output
Termination Methods
Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair
Package
Standard
LVTTL Slow Slew Rate, 2 mA drive
BGA, CS, FGA
HQ
49
31
22
17
12
10
7
PQ, TQ
68
41
29
22
17
14
9
36
20
15
12
9
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVCMOS
7
5
40
24
17
13
10
8
29
18
13
10
7
21
12
9
7
5
6
4
5
4
3
10
8
7
5
PCI
6
4
GTL
4
4
4
GTL+
4
4
4
DS022-2 (v2.8) January 16, 2006
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair (Continued)
Package
Standard
BGA, CS, FGA
HQ
13
7
PQ, TQ
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
CTT
18
9
9
5
3
8
5
6
4
7
5
5
4
15
10
11
7
11
7
8
5
14
9
10
7
AGP
Note: This analysis assumes a 35 pF load for each output.
Table 22: Virtex-E Equivalent Power/Ground Pairs
Pkg/Part
CS144
PQ240
HQ240
BG352
BG432
BG560
XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E
12
20
12
20
20
20
20
20
56
20
20
32
32
32
40
40
40
40
58
60
(1)
FG256
24
40
24
40
FG456
FG676
54
56
46
(2)
FG680
56
58
58
96
56
60
56
64
FG860
FG900
FG1156
56
60
104
120
Notes:
1. Virtex-E devices in FG256 packages have more VCCO than Virtex series devices.
2. FG680 numbers are preliminary.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
GTL+
Application Examples
A sample circuit illustrating a valid termination technique for
GTL+ appears in Figure 45. DC voltage specifications
appear in Table 24.
Creating a design with the SelectI/O features requires the
instantiation of the desired library symbol within the design
code. At the board level, designers need to know the termi-
nation techniques required for each I/O standard.
GTL+
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the SelectI/O features.
= 1.5V
= 1.5V
VTT
VTT
50Ω
50Ω
V
= N/A
CCO
Z = 50
Termination Examples
VREF = 1.0V
Figure 45: Terminated GTL+
Table 24: GTL+ Voltage Specifications
Circuit examples involving typical termination techniques for
each of the SelectI/O standards follow. For a full range of
accepted values for the DC voltage specifications for each
standard, refer to the table associated with each figure.
x133_09_012400
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
Parameter
Min
Typ
-
Max
V
V
V
V
-
0.88
1.35
0.98
-
-
1.12
1.65
-
CCO
REF
TT
GTL
1
= N × V
1.0
1.5
1.1
0.9
-
TT
A sample circuit illustrating a valid termination technique for
GTL is shown in Figure 44.
= V
+ 0.1
– 0.1
IH
REF
V = V
1.02
-
IL
REF
GTL
V
V
I
-
OH
OL
VTT = 1.2V VTT = 1.2V
0.3
-
0.45
-
0.6
-
50Ω
50Ω
Z = 50
VCCO = N/A
at V (mA)
OH
OH
VREF = 0.8V
I
I
at V (mA) at 0.6V
36
-
-
-
OL
OL
OL
x133_08_111699
at V (mA) at 0.3V
-
48
OL
Figure 44: Terminated GTL
Notes:
1. N must be greater than or equal to 0.653 and less than or
Table 23 lists DC voltage specifications.
equal to 0.68.
Table 23: GTL Voltage Specifications
Parameter
Min
Typ
N/A
0.8
1.2
0.85
0.75
-
Max
V
V
V
V
-
-
0.86
1.26
-
CCO
REF
TT
1
= N × V
0.74
TT
1.14
= V
+ 0.05
– 0.05
0.79
IH
REF
V = V
-
-
0.81
-
IL
REF
V
V
OH
OL
-
0.2
-
0.4
-
I
I
I
at V (mA)
-
OH
OH
at V (mA) at 0.4V
32
-
-
-
OL
OL
OL
at V (mA) at 0.2V
-
40
OL
Notes:
1. N must be greater than or equal to 0.653 and less than or
equal to 0.68.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
HSTL
HSTL Class III
VCCO = 1.5V
A sample circuit illustrating a valid termination technique for
HSTL_I appears in Figure 46. A sample circuit illustrating a
valid termination technique for HSTL_III appears in
Figure 47.
VTT= 1.5V
50Ω
Z = 50
Table 25: HSTL Class I Voltage Specification
VREF = 0.9V
Figure 47: Terminated HSTL Class III
Parameter
Min
1.40
0.68
-
Typ
1.50
0.75
Max
1.60
0.90
-
x133_11_111699
V
V
V
V
V
V
V
CCO
REF
TT
IH
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in Figure 48.
V
× 0.5
CCO
V
V
+ 0.1
-
-
-
-
REF
Table 27: HSTL Class IV Voltage Specification
-
V
– 0.1
REF
IL
Parameter
Min
Typ
1.50
0.90
Max
– 0.4
CCO
-
0.4
-
OH
OL
V
V
V
V
V
V
V
I
1.40
1.60
CCO
-
-
-
-
-
REF
TT
IH
I
I
at V (mA)
−8
-
-
OH
OH
V
CCO
at V (mA)
8
-
OL
OL
V
+ 0.1
-
REF
-
-
-
-
-
-
V
– 0.1
REF
IL
HSTL Class I
= 1.5V
V
– 0.4
CCO
-
0.4
-
OH
OL
-
V
= 0.75V
TT
V
CCO
at V (mA)
−8
50Ω
Z = 50
OH
OH
I
at V (mA)
48
-
OL
OL
V
= 0.75V
REF
Note: Per EIA/JESD8-6, “The value of VREF is to be selected
by the user to provide optimum noise margin in the use
conditions specified by the user.
x133_10_111699
Figure 46: Terminated HSTL Class I
Table 26: HSTL Class III Voltage Specification
HSTL Class IV
Parameter
Min
Typ
1.50
0.90
Max
VTT= 1.5V VTT= 1.5V
V
CCO = 1.5V
V
V
V
V
V
V
V
1.40
1.60
CCO
50Ω
50Ω
(1)
-
-
-
-
-
REF
TT
IH
Z = 50
V
VREF = 0.9V
CCO
x133_12_111699
V
+ 0.1
-
REF
Figure 48: Terminated HSTL Class IV
-
-
-
-
-
-
V
– 0.1
REF
IL
V
– 0.4
CCO
-
0.4
-
OH
OL
-
I
at V (mA)
−8
OH
OH
I
at V (mA)
24
-
OL
OL
Note: Per EIA/JESD8-6, “The value of VREF is to be selected
by the user to provide optimum noise margin in the use
conditions specified by the user.”
Module 2 of 4
42
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DS022-2 (v2.8) January 16, 2006
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
SSTL3_I
Table 29: SSTL3_II Voltage Specifications
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in Figure 49. DC voltage specifications
appear in Table 28.
Parameter
Min
3.0
1.3
1.3
1.5
Typ
3.3
1.5
1.5
1.7
1.3
-
Max
3.6
V
V
V
V
CCO
REF
= 0.45 × V
1.7
CCO
SSTL3 Class I
= V
1.7
TT
IH
REF
REF
VTT= 1.5V
VCCO = 3.3V
(1)
= V
+ 0.2
3.9
50Ω
25Ω
(2)
V = V
– 0.2
REF
−0.3
2.1
-
1.5
Z = 50
IL
VREF = 1.5V
V
V
= V
+ 0.8
REF
-
0.9
-
OH
OL
x133_13_111699
= V
– 0.8
-
REF
Figure 49: Terminated SSTL3 Class I
I
I
at V (mA)
−16
16
-
OH
OH
at V (mA)
-
-
Table 28: SSTL3_I Voltage Specifications
OL
OL
Notes:
1. IH maximum is VCCO + 0.3
2. VIL minimum does not conform to the formula
Parameter
Min
3.0
1.3
1.3
1.5
Typ
3.3
1.5
1.5
1.7
1.3
-
Max
3.6
1.7
1.7
V
V
V
V
V
CCO
REF
= 0.45 × V
CCO
SSTL2_I
= V
TT
IH
REF
REF
REF
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in Figure 51. DC voltage specifications
appear in Table 30.
(1)
= V
+ 0.2
– 0.2
3.9
(2)
V = V
−0.3
1.9
-
1.5
IL
SSTL2 Class I
V
= V
+ 0.6
– 0.6
-
1.1
-
OH
OL
REF
REF
V
= 1.25V
TT
V
= 2.5V
V
= V
-
CCO
50Ω
I
I
at V (mA)
−8
8
-
OH
OH
25Ω
Z = 50
at V (mA)
-
-
OL
OL
V
= 1.25V
REF
Notes:
xap133_15_011000
1. VIH maximum is VCCO + 0.3
2. VIL minimum does not conform to the formula
Figure 51: Terminated SSTL2 Class I
SSTL3_II
Table 30: SSTL2_I Voltage Specifications
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in Figure 50. DC voltage specifications
appear in Table 29.
Parameter
Min
2.3
Typ
2.5
1.25
1.25
1.43
1.07
-
Max
2.7
V
V
V
V
CCO
REF
= 0.5 × V
1.15
1.11
1.33
1.35
1.39
CCO
(1)
= V
+ N
SSTL3 Class II
TT
IH
REF
REF
REF
(2)
VTT= 1.5V VTT= 1.5V
= V
+ 0.18
– 0.18
3.0
VCCO = 3.3V
(3)
V = V
−0.3
1.17
50Ω
50Ω
Z = 50
IL
25Ω
V
V
I
= V
+ 0.61
REF
1.76
-
-
OH
VREF = 1.5V
= V
– 0.61
REF
-
0.74
OL
x133_14_111699
at V (mA)
−7.6
7.6
-
-
-
Figure 50: Terminated SSTL3 Class II
OH
OH
I
at V (mA)
-
OL
OL
Notes:
1. N must be greater than or equal to -0.04 and less than or
equal to 0.04.
2.
VIH maximum is VCCO + 0.3.
3. VIL minimum does not conform to the formula.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
www.xilinx.com
Module 2 of 4
43
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Virtex™-E 1.8 V Field Programmable Gate Arrays
SSTL2_II
Table 32: CTT Voltage Specifications
Parameter Min
A sample circuit illustrating a valid termination technique for
SSTL2_II appears in Figure 52. DC voltage specifications
appear in Table 31.
Typ
3.3
1.5
1.5
1.7
1.3
1.9
1.1
-
Max
3.6
1.65
1.65
-
(1)
V
V
V
V
2.05
1.35
CCO
REF
TT
SSTL2 Class II
1.35
1.55
-
VTT= 1.25V VTT= 1.25V
V
CCO = 2.5V
= V
+ 0.2
– 0.2
IH
REF
50Ω
50Ω
25Ω
V = V
1.45
-
IL
REF
Z = 50
VREF = 1.25V
V
= V
+ 0.4
REF
1.75
-
OH
x133_16_111699
V
= V
– 0.4
REF
1.25
-
OL
Figure 52: Terminated SSTL2 Class II
I
I
at V (mA)
−8
8
OH
OH
Table 31: SSTL2_II Voltage Specifications
at V (mA)
-
-
OL
OL
Parameter
Min
2.3
Typ
2.5
1.25
1.25
1.43
1.07
-
Max
2.7
Notes:
1. Timing delays are calculated based on VCCO min of 3.0V.
V
V
V
V
CCO
REF
= 0.5 × V
1.15
1.11
1.33
1.35
1.39
CCO
(1)
PCI33_3 & PCI66_3
= V
+ N
TT
IH
REF
REF
REF
PCI33_3 or PCI66_3 require no termination. DC voltage
specifications appear in Table 33.
(2)
= V
+ 0.18
– 0.18
3.0
(3)
V = V
−0.3
1.17
IL
Table 33: PCI33_3 and PCI66_3 Voltage Specifications
V
V
= V
+ 0.8
– 0.8
1.95
-
-
OH
OL
REF
REF
Parameter
Min
3.0
Typ
Max
= V
-
0.55
V
V
V
V
3.3
3.6
CCO
REF
TT
I
at V (mA)
−15.2
15.2
-
-
-
OH
OH
-
-
-
-
I
at V (mA)
-
OL
OL
-
-
Notes:
1. N must be greater than or equal to -0.04 and less than or
= 0.5 × V
1.5
1.65
V
+ 0.5
CCO
IH
CCO
equal to 0.04.
2. VIH maximum is VCCO + 0.3.
3. VIL minimum does not conform to the formula.
V = 0.3 × V
−0.5
2.7
0.99
1.08
IL
CCO
V
= 0.9 × V
-
-
-
-
-
OH
CCO
V
= 0.1 × V
-
0.36
CTT
OL
CCO
A sample circuit illustrating a valid termination technique for
CTT appear in Figure 53. DC voltage specifications appear
in Table 32.
I
I
at V (mA)
Note 1
Note 1
-
-
OH
OH
at V (mA)
OL
OL
Notes:
1. Tested according to the relevant specification.
CTT
VTT = 1.5V
VCCO = 3.3V
50Ω
Z = 50
VREF= 1.5V
x133_17_111699
Figure 53: Terminated CTT
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DS022-2 (v2.8) January 16, 2006
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
LVTTL
LVCMOS18
LVTTL requires no termination. DC voltage specifications
appears in Table 34.
LVCMOS18 does not require termination. Table 36 lists DC
voltage specifications.
Table 34: LVTTL Voltage Specifications
Table 36: LVCMOS18 Voltage Specifications
Parameter
Min
3.0
-
Typ
Max
Parameter
Min
Typ
Max
1.90
-
V
V
V
V
V
V
V
3.3
3.6
V
V
V
V
V
V
V
1.70
1.80
CCO
REF
TT
CCO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
REF
TT
IH
-
-
2.0
−0.5
2.4
-
3.6
0.8
-
0.65 x V
1.95
IH
CCO
– 0.5
V – 0.4
CCO
0.2 x V
CCO
IL
IL
-
0.4
-
OH
OL
OH
OL
0.4
-
-
I
at V (mA)
−24
24
I
I
at V (mA)
–8
8
OH
OH
OH
OH
I
at V (mA)
-
at V (mA)
-
OL
OL
OL
OL
Notes:
1. Note: VOLand VOH for lower drive currents sample tested.
AGP-2X
The specification for the AGP-2X standard does not docu-
ment a recommended termination technique. DC voltage
specifications appear in Table 37.
LVCMOS2
LVCMOS2 requires no termination. DC voltage specifica-
tions appear in Table 35.
Table 37: AGP-2X Voltage Specifications
Parameter
Min
3.0
Typ
3.3
1.32
-
Max
Table 35: LVCMOS2 Voltage Specifications
V
V
V
V
3.6
CCO
REF
TT
Parameter
Min
2.3
-
Typ
Max
(1)
= N × V
1.17
-
1.48
CCO
V
V
V
V
V
V
V
2.5
2.7
CCO
REF
TT
-
-
-
-
-
-
-
-
-
-
-
= V
+ 0.2
– 0.2
1.37
-
1.52
1.12
3.0
0.33
-
-
IH
REF
-
V = V
1.28
IL
REF
1.7
−0.5
1.9
-
3.6
0.7
-
IH
V
= 0.9 × V
2.7
-
OH
OL
CCO
CCO
IL
V
= 0.1 × V
-
0.36
OH
OL
I
I
at V (mA)
Note 2
Note 2
-
-
OH
OH
0.4
-
at V (mA)
-
OL
OL
I
at V (mA)
−12
12
OH
OH
Notes:
I
at V (mA)
-
OL
OL
1. N must be greater than or equal to 0.39 and less than or
equal to 0.41.
2. Tested according to the relevant specification.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
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Module 2 of 4
45
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Virtex™-E 1.8 V Field Programmable Gate Arrays
LVDS
LVPECL
Depending on whether the device is transmitting or receiv-
ing an LVPECL signal, two different circuits are used for
LVPECL termination. A sample circuit illustrating a valid ter-
mination technique for transmitting LVPECL signals
appears in Figure 56. A sample circuit illustrating a valid ter-
mination for receiving LVPECL signals appears in
Figure 57. Table 39 lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on Table 40.
Depending on whether the device is transmitting an LVDS
signal or receiving an LVDS signal, there are two different
circuits used for LVDS termination. A sample circuit illustrat-
ing a valid termination technique for transmitting LVDS sig-
nals appears in Figure 54. A sample circuit illustrating a
valid termination for receiving LVDS signals appears in
Figure 55. Table 38 lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on Table 40.
Table 39: LVPECL Voltage Specifications
1/4 of Bourns
Part Number
Parameter
Min
3.0
-
Typ
Max
3.6
-
Virtex-E
CAT16-LV4F12
FPGA
RS
Z
Z
= 50Ω
= 50Ω
0
0
Q
V
V
V
V
V
V
V
3.3
CCO
REF
TT
to LVDS Receiver
to LVDS Receiver
2.5V
165
R
-
-
-
-
-
-
DIV
140
DATA
Transmit
RS
-
-
Q
165
VCCO = 2.5V
LVDS
1.49
0.86
1.8
-
2.72
2.125
-
IH
Output
x133_19_122799
IL
Figure 54: Transmitting LVDS Signal Circuit
OH
OL
1.57
VIRTEX-E
FPGA
Notes:
Z
Z
= 50Ω
= 50Ω
0
0
LVDS_IN
Q
Q
1. For more detailed information, see DS022-3: Virtex-E 1.8V
FPGA DC and Switching Characteristics, Module 3, LVPECL
DC Specifications section.
+
–
from
LVDS
Driver
R
T
100Ω
DATA
Receive
LVDS_IN
1/4 of Bourns
Part Number
Virtex-E
CAT16-PC4F12
FPGA
x133_29_122799
RS
Z
= 50Ω
= 50Ω
0
0
LVPECL_OUT
LVPECL_OUT
Q
to LVPECL Receiver
to LVPECL Receiver
3.3V
Figure 55: Receiving LVDS Signal Circuit
Table 38: LVDS Voltage Specifications
100
R
DIV
187
DATA
Transmit
RS
Z
Q
100
Parameter
Min
2.375
0.2
Typ
2.5
1.25
1.25
0.35
0.35
-
Max
2.625
2.2
x133_20_122799
V
V
V
V
V
V
V
CCO
Figure 56: Transmitting LVPECL Signal Circuit
(2)
ICM
(1)
VIRTEX-E
FPGA
1.125
0.1
1.375
-
OCM
Z
= 50Ω
= 50Ω
0
0
Q
LVPECL_IN
(1)
IDIFF
+
–
from
LVPECL
Driver
R
T
100Ω
DATA
Receive
(1)
0.25
1.25
-
0.45
-
ODIFF
Z
(1)
Q
LVPECL_IN
OH
(1)
x133_21_122799
-
1.25
OL
Figure 57: Receiving LVPECL Signal Circuit
Notes:
1. Measured with a 100 Ω resistor across Q and Q.
2. Measured with a differential input voltage = +/− 350 mV.
Module 2 of 4
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DS022-2 (v2.8) January 16, 2006
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Termination Resistor Packs
Creating LVDS Global Clock Input Buffers
Resistor packs are available with the values and the config-
uration required for LVDS and LVPECL termination from
Bourns, Inc., as listed in Table. For pricing and availability,
please contact Bourns directly at http://www.bourns.com.
Global clock input buffers can be combined with adjacent
IOBs to form LVDS clock input buffers. P-side is the GCLK-
PAD location; N-side is the adjacent IO_LVDS_DLL site.
Table 41: Global Clock Input Buffer Pair Locations
Table 40: Bourns LVDS/LVPECL Resistor Packs
GCLK 3
GCLK 2
GCLK 1
GCLK 0
Term.
for:
Pairs/
Pack Pins
Pkg
P
N
P
N
P
N
P
N
Part Number
CAT16−LV2F6
CAT16−LV4F12
CAT16−PC2F6
CAT16−PC4F12
CAT16−PT2F2
CAT16−PT4F4
I/O Standard
LVDS
CS144
A6
C6
A7
B7
M7
M6
K7
N8
Driver
Driver
Driver
Driver
2
4
2
4
2
4
8
16
8
PQ240 P213 P215 P210 P209 P89
HQ240 P213 P215 P210 P209 P89
P87
P87
P92
P92
P93
P93
LVDS
LVPECL
LVPECL
BG352 D14
BG432 D17
BG560 A17
A15
C17
C18
A7
B14 A13 AF14 AD14 AE13 AC13
A16 B16 AK16 AL17 AL16 AH15
D17 E17 AJ17 AM18 AL17 AM17
16
8
LVDS/LVPECL Receiver
LVDS/LVPECL Receiver
16
FG256
B8
C9
A8
R8
Yll
T8
N8
N9
FG456 C11
FG676 E13
FG680 A20
FG860 C22
FG900 C15
FG1156 E17
B11
B13
C22
A22
A15
C17
A11 D11
AA11
W12
U12
LVDS Design Guide
C13 F14 AB13 AF13 AA14 AC14
D21 A19 AU22 AT22 AW19 AT21
B22 D22 AY22 AW21 BA22 AW20
E15 E16 AK16 AH16 AJ16 AF16
The SelectI/O library elements have been expanded for Vir-
tex-E devices to include new LVDS variants. At this time all
of the cells might not be included in the Synthesis libraries.
The 2.1i-Service Pack 2 update for Alliance and Foundation
software includes these cells in the VHDL and Verilog librar-
ies. It is necessary to combine these cells to create the
P-side (positive) and N-side (negative) as described in the
input, output, 3-state and bidirectional sections.
D17
J18
Al19
AL17 AH18 AM18
HDL Instantiation
IBUF_LVDS
OBUF_LVDS
IOBUF_LVDS
T
Only one global clock input buffer is required to be instanti-
ated in the design and placed on the correct GCLKPAD
location. The N-side of the buffer is reserved and no other
IOB is allowed to be placed on this location.
I
O
I
O
I
IO
IBUFG_LVDS
OBUFT_LVDS
T
O
In the physical device, a configuration option is enabled that
routes the pad wire to the differential input buffer located in
the GCLKIOB. The output of this buffer then drives the out-
put of the GCLKIOB cell. In EPIC it appears that the second
buffer is unused. Any attempt to use this location for another
purpose leads to a DRC error in the software.
I
O
I
O
x133_22_122299
Figure 58: LVDS elements
VHDL Instantiation
gclk0_p : IBUFG_LVDS port map
(I=>clk_external, O=>clk_internal);
Verilog Instantiation
IBUFG_LVDS gclk0_p (.I(clk_external),
.O(clk_internal));
Location constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
NET clk_external LOC = GCLKPAD3;
GCLKPAD3 can also be replaced with the package pin
name such as D17 for the BG432 package.
DS022-2 (v2.8) January 16, 2006
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Verilog Instantiation
Optional N-side
IBUF_LVDS data0_p (.I(data[0]),
.O(data_int[0]));
Some designers might prefer to also instantiate the N-side
buffer for the global clock buffer. This allows the top-level net
list to include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUFG connection has a net connected to it. Since the
N-side IBUFG does not have a connection in the EDIF net
list, it is trimmed from the design in MAP.
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the input buffers this can be done with the following con-
straint in the .ucf or .ncf file.
NET data<0> LOC = D28; # IO_L0P
VHDL Instantiation
Optional N-side
gclk0_p : IBUFG_LVDS port map
(I=>clk_p_external, O=>clk_internal);
Some designers might prefer to also instantiate the N-side
buffer for the input buffer. This allows the top-level net list to
include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUF connection has a net connected to it. Since the N-side
IBUF does not have a connection in the EDIF net list, it is
trimmed from the design in MAP.
gclk0_n : IBUFG_LVDS port map
(I=>clk_n_external, O=>clk_internal);
Verilog Instantiation
IBUFG_LVDS gclk0_p (.I(clk_p_external),
.O(clk_internal));
VHDL Instantiation
IBUFG_LVDS gclk0_n (.I(clk_n_external),
.O(clk_internal));
data0_p : IBUF_LVDS port map
(I=>data_p(0), O=>data_int(0));
Location Constraints
data0_n : IBUF_LVDS port map
(I=>data_n(0), O=>open);
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
Verilog Instantiation
IBUF_LVDS data0_p (.I(data_p[0]),
.O(data_int[0]));
NET clk_p_external LOC = GCLKPAD3;
NET clk_n_external LOC = C17;
IBUF_LVDS data0_n (.I(data_n[0]), .O());
GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
Creating LVDS Input Buffers
An LVDS input buffer can be placed in a wide number of IOB
locations. The exact location is dependent on the package
that is used. The Virtex-E package information lists the pos-
sible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Adding an Input Register
HDL Instantiation
All LVDS buffers can have an input register in the IOB. The
input register is in the P-side IOB only. All the normal IOB
register options are available (FD, FDE, FDC, FDCE, FDP,
FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,
LDP, LDPE). The register elements can be inferred or
explicitly instantiated in the HDL code.
Only one input buffer is required to be instantiated in the
design and placed on the correct IO_L#P location. The
N-side of the buffer is reserved and no other IOB is allowed
to be placed on this location. In the physical device, a con-
figuration option is enabled that routes the pad wire from the
IO_L#N IOB to the differential input buffer located in the
IO_L#P IOB. The output of this buffer then drives the output
of the IO_L#P cell or the input register in the IO_L#P IOB. In
EPIC it appears that the second buffer is unused. Any
attempt to use this location for another purpose leads to a
DRC error in the software.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
To improve design coding times VHDL and Verilog synthesis
macro libraries available to explicitly create these structures.
The input library macros are listed in Table 42. The I and IB
inputs to the macros are the external net connections.
VHDL Instantiation
data0_p : IBUF_LVDS port map (I=>data(0),
O=>data_int(0));
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Verilog Instantiation
OBUF_LVDS data0_p
.O(data_p[0]));
INV data0_inv (.I(data_int[0],
Table 42: Input Library Macros
(.I(data_int[0]),
Name
Inputs
Outputs
IBUFDS_FD_LVDS
IBUFDS_FDE_LVDS
IBUFDS_FDC_LVDS
IBUFDS_FDCE_LVDS
IBUFDS_FDP_LVDS
IBUFDS_FDPE_LVDS
IBUFDS_FDR_LVDS
IBUFDS_FDRE_LVDS
IBUFDS_FDS_LVDS
IBUFDS_FDSE_LVDS
IBUFDS_LD_LVDS
IBUFDS_LDE_LVDS
IBUFDS_LDC_LVDS
IBUFDS_LDCE_LVDS
IBUFDS_LDP_LVDS
IBUFDS_LDPE_LVDS
I, IB, C
I, IB, CE, C
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
.O(data_n_int[0]);
I, IB, C, CLR
I, IB, CE, C, CLR
I, IB, C, PRE
I, IB, CE, C, PRE
I, IB, C, R
OBUF_LVDS data0_n
.O(data_n[0]));
(.I(data_n_int[0]),
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
I, IB, CE, C, R
I, IB, C, S
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Outputs
I, IB, CE, C, S
I, IB, G
If the outputs are synchronous (registered in the IOB) then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or COLUMN in the device.
I, IB, GE, G
I, IB, G, CLR
I, IB, GE, G, CLR
I, IB, G, PRE
I, IB, GE, G, PRE
The LVDS pairs that can be used as asynchronous outputs
are listed in the Virtex-E pinout tables. Some pairs are
marked as asynchronous-capable for all devices in that
package, and others are marked as available only for that
device in the package. If the device size might change at
some point in the product lifetime, then only the common
pairs for all packages should be used.
Creating LVDS Output Buffers
LVDS output buffers can be placed in a wide number of IOB
locations. The exact locations are dependent on the pack-
age used. The Virtex-E package information lists the possi-
ble locations as IO_L#P for the P-side and IO_L#N for the
N-side, where # is the pair number.
Adding an Output Register
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
HDL Instantiation
Both output buffers are required to be instantiated in the
design and placed on the correct IO_L#P and IO_L#N loca-
tions. The IOB must have the same net source the following
pins, clock (C), set/reset (SR), output (O), output clock
enable (OCE). In addition, the output (O) pins must be
inverted with respect to each other, and if output registers
are used, the INIT states must be opposite values (one
HIGH and one LOW). Failure to follow these rules leads to
DRC errors in software.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The clock pin (C), clock enable (CE) and
set/reset (CLR/PRE or S/R) pins must connect to the same
source. Failure to do this leads to a DRC error in the soft-
ware.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
VHDL Instantiation
data0_p : OBUF_LVDS port map
(I=>data_int(0),
O=>data_p(0));
To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The output library macros are listed in
Table 43. The O and OB inputs to the macros are the exter-
nal net connections.
data0_inv: INV
(I=>data_int(0),
port map
O=>data_n_int(0));
data0_n : OBUF_LVDS port map
(I=>data_n_int(0), O=>data_n(0));
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VHDL Instantiation
Table 43: Output Library Macros
data0_p:
OBUFT_LVDS port map
(I=>data_int(0), T=>data_tri,
O=>data_p(0));
Name
Inputs
D, C
Outputs
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
OBUFDS_FD_LVDS
OBUFDS_FDE_LVDS
OBUFDS_FDC_LVDS
OBUFDS_FDCE_LVDS
OBUFDS_FDP_LVDS
OBUFDS_FDPE_LVDS
OBUFDS_FDR_LVDS
OBUFDS_FDRE_LVDS
OBUFDS_FDS_LVDS
OBUFDS_FDSE_LVDS
OBUFDS_LD_LVDS
OBUFDS_LDE_LVDS
OBUFDS_LDC_LVDS
OBUFDS_LDCE_LVDS
OBUFDS_LDP_LVDS
OBUFDS_LDPE_LVDS
data0_inv: INV port map
(I=>data_int(0), O=>data_n_int(0));
DD, CE, C
D, C, CLR
D, CE, C, CLR
D, C, PRE
D, CE, C, PRE
D, C, R
data0_n:
OBUFT_LVDS port map
(I=>data_n_int(0), T=>data_tri,
O=>data_n(0));
Verilog Instantiation
OBUFT_LVDS data0_p
(.I(data_int[0]),
.T(data_tri), .O(data_p[0]));
INV
data0_inv (.I(data_int[0],
D, CE, C, R
D, C, S
.O(data_n_int[0]);
OBUFT_LVDS data0_n
(.I(data_n_int[0]),
.T(data_tri), .O(data_n[0]));
D, CE, C, S
D, G
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
D, GE, G
D, G, CLR
D, GE, G, CLR
D, G, PRE
D, GE, G, PRE
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous 3-State Outputs
If the outputs are synchronous (registered in the IOB), then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or COLUMN in the device. This applies for either the
3-state pin or the data out pin.
Creating LVDS Output 3-State Buffers
LVDS output 3-state buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.
LVDS pairs that can be used as asynchronous outputs are
listed in the Virtex-E pinout tables. Some pairs are marked
as “asynchronous capable” for all devices in that package,
and others are marked as available only for that device in
the package. If the device size might be changed at some
point in the product lifetime, then only the common pairs for
all packages should be used.
HDL Instantiation
Both output 3-state buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the fol-
lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one High and one
Low). If 3-state registers are used, they must be initialized to
the same state. Failure to follow these rules leads to DRC
errors in the software.
Adding Output and 3-State Registers
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The 3-state (T), 3-state clock enable
(CE), clock pin (C), output clock enable (CE) and set/reset
(CLR/PRE or S/R) pins must connect to the same source.
Failure to do this leads to a DRC error in the software.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The input library macros are listed below.
The 3-state is configured to be 3-stated at GSR and when
the PRE,CLR,S or R is asserted and shares it's clock
enable with the output register. If this is not desirable then
the library can be updated by the user for the desired func-
tionality. The O and OB inputs to the macros are the exter-
nal net connections.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Bidirectional
Buffers
If the output side of the bidirectional buffers are synchro-
nous (registered in the IOB), then any IO_L#P|N pair can be
used. If the output side of the bidirectional buffers are asyn-
chronous (no output register), then they must use one of the
pairs that is a part of the asynchronous LVDS IOB group.
This applies for either the 3-state pin or the data out pin.
Creating a LVDS Bidirectional Buffer
LVDS bidirectional buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.
The LVDS pairs that can be used as asynchronous bidirec-
tional buffers are listed in the Virtex-E pinout tables. Some
pairs are marked as asynchronous capable for all devices in
that package, and others are marked as available only for
that device in the package. If the device size might change
at some point in the product’s lifetime, then only the com-
mon pairs for all packages should be used.
HDL Instantiation
Both bidirectional buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the fol-
lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one HIGH and one
LOW). If 3-state registers are used, they must be initialized
to the same state. Failure to follow these rules leads to DRC
errors in the software.
Adding Output and 3-State Registers
All LVDS buffers can have an output and input registers in
the IOB. The output registers must be in both the P-side and
N-side IOBs, the input register is only in the P-side. All the
normal IOB register options are available (FD, FDE, FDC,
FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,
LDC, LDCE, LDP, LDPE). The register elements can be
inferred or explicitly instantiated in the HDL code. Special
care must be taken to insure that the D pins of the registers
are inverted and that the INIT states of the registers are
opposite. The 3-state (T), 3-state clock enable (CE), clock
pin (C), output clock enable (CE), and set/reset (CLR/PRE
or S/R) pins must connect to the same source. Failure to do
this leads to a DRC error in the software.
VHDL Instantiation
data0_p:
IOBUF_LVDS port map
(I=>data_out(0), T=>data_tri,
IO=>data_p(0), O=>data_int(0));
data0_inv: INV
port map
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs. To improve design coding times
VHDL and Verilog synthesis macro libraries have been
developed to explicitly create these structures. The bidirec-
tional I/O library macros are listed in Table 44. The 3-state is
configured to be 3-stated at GSR and when the PRE,CLR,S
or R is asserted and shares its clock enable with the output
and input register. If this is not desirable then the library can
be updated be the user for the desired functionality. The I/O
and IOB inputs to the macros are the external net connec-
tions.
(I=>data_out(0),
O=>data_n_out(0));
data0_n : IOBUF_LVDS port map
(I=>data_n_out(0), T=>data_tri,
IO=>data_n(0), O=>open);
Verilog Instantiation
IOBUF_LVDS data0_p(.I(data_out[0]),
.T(data_tri), .IO(data_p[0]),
.O(data_int[0]);
INV
data0_inv (.I(data_out[0],
.O(data_n_out[0]);
IOBUF_LVDS
data0_n(.I(data_n_out[0]),.T(data_tri),.
IO(data_n[0]).O());
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Table 44: Bidirectional I/O Library Macros
Name
Inputs
D, T, C
Bidirectional
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
Outputs
IOBUFDS_FD_LVDS
IOBUFDS_FDE_LVDS
IOBUFDS_FDC_LVDS
IOBUFDS_FDCE_LVDS
IOBUFDS_FDP_LVDS
IOBUFDS_FDPE_LVDS
IOBUFDS_FDR_LVDS
IOBUFDS_FDRE_LVDS
IOBUFDS_FDS_LVDS
IOBUFDS_FDSE_LVDS
IOBUFDS_LD_LVDS
IOBUFDS_LDE_LVDS
IOBUFDS_LDC_LVDS
IOBUFDS_LDCE_LVDS
IOBUFDS_LDP_LVDS
IOBUFDS_LDPE_LVDS
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
D, T, CE, C
D, T, C, CLR
D, T, CE, C, CLR
D, T, C, PRE
D, T, CE, C, PRE
D, T, C, R
D, T, CE, C, R
D, T, C, S
D, T, CE, C, S
D, T, G
D, T, GE, G
D, T, G, CLR
D, T, GE, G, CLR
D, T, G, PRE
D, T, GE, G, PRE
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T
values, buffered Hex Line info, p. 8, I/O Timing
BYP
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
7/10/00
1.3
1.4
1.5
Updated pinout tables, V page 20, and corrected Figure 20.
CC
Correction to table on p. 22.
•
•
•
Numerous minor edits.
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
8/1/00
1.6
•
•
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Revision
Date
Version
9/20/00
1.7
•
•
Min values added to Virtex-E Electrical Characteristics tables.
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate V
pins in Table ~ (Module 4).
CCINT
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
11/20/00
1.8
•
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
•
•
•
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for T
, T
, T
, and T
.
SHCKO32 REG BCCS
ICKOF
•
Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
•
•
Revised maximum T
in -6 speed grade for DLL Timing Parameters.
DLLPW
Changed GCLK0 to BA22 for FG860 package in Table 46.
2/12/01
4/02/01
1.9
2.0
•
•
Revised footnote for Table 14.
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
•
•
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E
devices in the BG560 package.
•
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
•
•
Updated numerous values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format. See the Virtex-E Data Sheet section.
4/19/01
2.1
2.2
•
Modified Figure 30 "DLL Generation of 4x Clock in Virtex-E Devices."
07/23/01
•
•
Made minor edits to text under Configuration.
Added CLB column locations for XCV2600E anbd XCV3200E devices in Table 3.
11/09/01
2.3
•
Added warning under Configuration section that attempting to load an incorrect
bitstream causes configuration to fail and can damage the device.
07/17/02
09/10/02
2.4
2.5
•
•
Data sheet designation upgraded from Preliminary to Production.
Added clarification to the Input/Output Block, Configuration, Boundary Scan
Mode, and Block SelectRAM sections. Revised Figure 18, Table 11, and Table 36.
11/19/02
2.6
•
•
Added clarification in the Boundary Scan section.
Removed last sentence regarding deactivation of duty-cycle correction in Duty Cycle
Correction Property section.
06/15/04
01/12/06
01/16/06
2.6.1
2.7
•
•
•
Updated clickable web addresses.
Updated the Slave-Serial Mode and the Master-Serial Mode sections.
Made minor updates to Table 8.
2.8
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•
DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•
DS022-2, Virtex-E 1.8V FPGAs:
DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
Pinout Tables (Module 4)
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Field Programmable Gate Arrays
0
0
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
Virtex-E Electrical Characteristics
Definition of Terms
Electrical and switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as
follows:
Table 1 correlates the current status of each Virtex-E device
with a corresponding speed file designation.
Table 1: Virtex-E Device Speed Grade Designations
Speed Grade Designations
Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Device
XCV50E
Advance
Preliminary Production
–8, –7, –6
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
–8, –7, –6
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
–8, –7, –6
–8, –7, –6
–8, –7, –6
–8, –7, –6
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
–8, –7, –6
–8, –7, –6
–8, –7, –6
–8, –7, –6
–8, –7, –6
All specifications are subject to change without notice.
All specifications are representative of worst-case supply
voltage and junction temperature conditions. The parame-
ters included are common to popular designs and typical
applications. Contact the factory for design considerations
requiring more detailed information.
© 2000-2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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DC Characteristics
Absolute Maximum Ratings
(1)
Symbol
Description
Units
V
V
Internal Supply voltage relative to GND
Supply voltage relative to GND
Input Reference Voltage
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
CCINT
V
V
CCO
V
V
REF
(3)
IN
V
Input voltage relative to GND
Voltage applied to 3-state output
–0.5 to V
+0.5
V
CCO
V
–0.5 to 4.0
V
TS
V
Longest Supply Voltage Rise Time from 0 V - 1.71 V
Storage temperature (ambient)
50
ms
°C
°C
CC
T
–65 to +150
+125
STG
(2)
T
Junction temperature
Plastic packages
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.
2. For soldering guidelines and thermal considerations, see the device packaging information on www.xilinx.com.
3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the
device is not PCI compliant.
Recommended Operating Conditions
Symbol
Description
Internal Supply voltage relative to GND, T = 0 °C to +85 °C
Min
Max
Units
V
Commercial 1.8 – 5% 1.8 + 5%
J
V
CCINT
Internal Supply voltage relative to GND, T = –40 °C to +100 °C
Industrial
Commercial
Industrial
1.8 – 5% 1.8 + 5%
V
J
Supply voltage relative to GND, T = 0 °C to +85 °C
1.2
1.2
3.6
3.6
V
J
V
CCO
Supply voltage relative to GND, T = –40 °C to +100 °C
V
J
T
Input signal transition time
250
ns
IN
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Voltage
Device
Min
Max Units
Data Retention V
CCINT
V
All
1.5
V
DRINT
(below which configuration data might be lost)
Data Retention V Voltage
CCO
V
All
1.2
V
DRIO
(below which configuration data might be lost)
Quiescent V supply current (Note 1)
I
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
All
200
200
300
300
300
400
500
500
500
500
500
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
CCINTQ
CCINT
I
Quiescent V
supply current (Note 1)
CCO
CCOQ
2
2
2
2
2
2
2
2
2
2
I
Input or output leakage current
–10
+10
8
L
C
Input capacitance (sample tested)
BGA, PQ, HQ, packages
= 3.3 V (sample tested)
All
pF
IN
I
Pad pull-up (when selected) @ V = 0 V, V
CCO
All
Note 2 0.25
Note 2 0.25
mA
mA
RPU
RPD
in
I
Pad pull-down (when selected) @ V = 3.6 V (sample tested)
in
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
1
power supply voltage of the device from 0V. The fastest ramp rate is 0V to nominal voltage in 2 ms, and the slowest allowed
ramp rate is 0V to nominal voltage in 50 ms. For more details on power supply requirements, see XAPP158 on
www.xilinx.com.
(2)
(3)
Product (Commercial Grade)
XCV50E - XCV600E
Description
Current Requirement
Minimum required current supply
Minimum required current supply
Minimum required current supply
Minimum required current supply
500 mA
1 A
XCV812E - XCV2000E
XCV2600E - XCV3200E
Virtex-E Family, Industrial Grade
1.2 A
2 A
Notes:
1. Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and
lasts for less than 3 ms.
2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3. Larger currents might result if ramp rates are forced to be faster.
DC Input and Output Levels
Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended
OH
IL
IH
OL
operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that
OL
OH
all standards meet their specifications. The selected standards are tested at minimum V
with the respective V and
CCO
OL
V
voltage levels shown. Other standards are sample tested.
OH
V
V
V
V
I
I
OH
IL
IH
OL
OH
OL
Input/Output
Standard
V, Min
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V, Max
V, Min
2.0
V, Max
3.6
V, Max
0.4
V, Min
2.4
mA
24
mA
– 24
– 12
– 8
(1)
LVTTL
0.8
0.7
LVCMOS2
LVCMOS18
PCI, 3.3 V
GTL
1.7
2.7
0.4
1.9
12
35% V
30% V
65% V
1.95
0.4
V – 0.4
CCO
8
CCO
CCO
CCO
50% V
V
+ 0.5 10% V
90% V
CCO
Note 2
40
Note 2
n/a
CCO
CCO
CCO
V
– 0.05
– 0.1
– 0.1
– 0.1
– 0.1
– 0.2
– 0.2
– 0.2
– 0.2
V
+ 0.05
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.2
+ 0.2
+ 0.2
+ 0.2
3.6
0.4
0.6
0.4
0.4
0.4
n/a
n/a
REF
REF
GTL+
V
V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
36
n/a
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
(3)
HSTL I
V
V
V
V
V
– 0.4
8
–8
CCO
CCO
CCO
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
V
V
V
V
V
V
V
V
V
V
V
V
– 0.4
– 0.4
24
–8
48
–8
V
V
– 0.6
V
V
+ 0.6
8
–8
REF
REF
REF
REF
– 0.8
– 0.61
– 0.80
+ 0.8
16
–16
–7.6
–15.2
V
V
V
V
+ 0.61
+ 0.80
7.6
15.2
REF
REF
REF
REF
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
V
V
V
V
I
I
OH
IL
IH
OL
OH
OL
Input/Output
Standard
V, Min
– 0.5
– 0.5
V, Max
V, Min
V, Max
3.6
V, Max
– 0.4
V, Min
V + 0.4
REF
mA
8
mA
–8
CTT
V
– 0.2
V
V
+ 0.2
V
REF
REF
REF
REF
REF
AGP
V
– 0.2
+ 0.2
3.6
10% V
90% V
Note 2
Note 2
CCO
CCO
Notes:
1.
VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
3. DC input and output levels for HSTL18 (HSTL I/O standard with VCCO of 1.8 V) are provided in an HSTL white paper on
www.xilinx.com.
LVDS DC Specifications
DC Parameter
Supply Voltage
Symbol
Conditions
Min
Typ
Max Units
V
2.375
2.5
2.625
1.6
V
V
V
CCO
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
V
R = 100 Ω across Q and Q signals
1.25 1.425
OH
T
V
R = 100 Ω across Q and Q signals
0.9
1.075 1.25
OL
T
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
V
R = 100 Ω across Q and Q signals
250
350 450
mV
V
ODIFF
T
Output Common-Mode Voltage
V
R = 100 Ω across Q and Q signals 1.125 1.25 1.375
T
OCM
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
V
Common-mode input voltage = 1.25 V 100
Differential input voltage = ±350 mV 0.2
350
NA
2.2
mV
V
IDIFF
Input Common-Mode Voltage
V
1.25
ICM
Note: Refer to the Design Consideration section for termination schematics.
LVPECL DC Specifications
These values are valid at the output of the source termination pack shown under LVPECL, with a 100 Ω differential load only.
The V levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
OH
ranges. The following table summarizes the DC output specifications of LVPECL.
DC Parameter
Min
Max
Min
Max
Min
Max
Units
V
3.0
3.3
3.6
V
V
V
V
V
V
CCO
V
1.8
0.96
1.49
0.86
0.3
2.11
1.27
2.72
2.125
-
1.92
1.06
1.49
0.86
0.3
2.28
1.43
2.72
2.125
-
2.13
1.30
1.49
0.86
0.3
2.41
1.57
2.72
2.125
-
OH
V
OL
V
IH
V
IL
Differential Input Voltage
DS022-3 (v2.9.2) March 14, 2003
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Module 3 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All
timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Virtex-E devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels in Table 2. For other standards, adjust the delays with the
values shown in IOB Input Switching Characteristics Standard Adjustments, page 8.
Table 2: IOB Input Switching Characteristics
(1)
Speed Grade
(2)
Description
Propagation Delays
Symbol
Device
Min
-8
-7
-6
Units
Pad to I output, no delay
Pad to I output, with delay
T
All
0.43
0.51
0.51
0.51
0.51
0.51
0.51
0.55
0.55
0.55
0.55
0.55
0.8
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
1.1
0.8
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
1.1
0.8
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
1.1
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
IOPI
T
XCV50E
IOPID
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
Pad to output IQ via transparent
latch, no delay
T
All
0.8
1.4
1.5
1.6
ns, max
IOPLI
Pad to output IQ via transparent
latch, with delay
T
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
1.31
1.31
1.39
1.39
1.43
1.55
1.55
1.59
1.59
1.59
1.59
2.9
2.9
3.1
3.1
3.2
3.5
3.5
3.6
3.6
3.6
3.6
3.0
3.0
3.2
3.2
3.3
3.6
3.6
3.7
3.7
3.7
3.7
3.1
3.1
3.3
3.3
3.4
3.7
3.7
3.8
3.8
3.8
3.8
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
IOPLID
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 2: IOB Input Switching Characteristics (Continued)
(1)
Speed Grade
(2)
Description
Sequential Delays
Symbol
Device
Min
-8
-7
-6
Units
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Clock CLK to output IQ
T
All
0.56
0.56
0.18
1.2
1.2
0.4
1.3
1.3
0.7
1.4
1.4
0.7
ns, min
ns, min
ns, max
CH
T
CL
T
IOCKIQ
Setup and Hold Times with respect to Clock at IOB Input
Register
Pad, no delay
T
T
/
IOPICK
All
0.69 / 0
1.3 / 0
1.4 / 0
1.5 / 0
ns, min
IOICKP
Pad, with delay
T
T
/
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
All
1.25 / 0
1.25 / 0
1.33 / 0
1.33 / 0
1.37 / 0
1.49 / 0
1.49 / 0
1.53 / 0
1.53 / 0
1.53 / 0
1.53 / 0
2.8 / 0
2.8 / 0
3.0 / 0
3.0 / 0
3.1 / 0
3.4 / 0
3.4 / 0
3.5 / 0
3.5 / 0
3.5 / 0
3.5 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
3.5 / 0
3.6 / 0
3.6 / 0
3.6 / 0
3.6 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
3.5 / 0
3.6 / 0
3.6 / 0
3.6 / 0
3.6 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
IOPICKD
IOICKPD
ICE input
T
T
/
0.28 /
0.0
0.55 /
0.01
0.7 /
0.01
0.7 /
0.01
IOICECK
IOCKICE
SR input (IFF, synchronous)
Set/Reset Delays
T
All
0.38
0.8
0.9
1.0
ns, min
IOSRCKI
SR input to IQ (asynchronous)
GSR to output IQ
T
All
All
0.54
3.88
1.1
7.6
1.2
8.5
1.4
9.7
ns, max
ns, max
IOSRIQ
T
GSRQ
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 4.
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
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Module 3 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Input Switching Characteristics Standard Adjustments
(1)
Speed Grade
Description
Symbol
Standard
Min
-8
-7
-6
Units
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
T
LVTTL
LVCMOS2
LVCMOS18
LVDS
0.0
–0.02
0.12
0.00
0.00
0.0
0.0
0.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ILVTTL
T
0.0
0.0
ILVCMOS2
T
+0.20
+0.15
+0.15
+0.08
–0.11
+0.14
+0.14
+0.04
+0.04
+0.04
+0.10
+0.04
+0.20
+0.15
+0.15
+0.08
–0.11
+0.14
+0.14
+0.04
+0.04
+0.04
+0.10
+0.04
+0.20
+0.15
+0.15
+0.08
–0.11
+0.14
+0.14
+0.04
+0.04
+0.04
+0.10
+0.04
ILVCMOS18
T
ILVDS
T
LVPECL
ILVPECL
IPCI33_3
IPCI66_3
T
PCI, 33 MHz, 3.3 V –0.05
PCI, 66 MHz, 3.3 V –0.05
T
T
GTL
GTL+
HSTL
SSTL2
SSTL3
CTT
+0.10
+0.06
+0.02
–0.04
–0.02
+0.01
–0.03
IGTL
IGTLPLUS
T
T
IHSTL
T
T
ISSTL2
ISSTL3
T
ICTT
T
AGP
IAGP
Notes:
1. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 4.
Q
D
CE
T
TCE
Weak
Keeper
SR
PAD
O
Q
D
CE
OCE
OBUFT
SR
I
IQ
Programmable
Delay
Q
D
CE
IBUF
Vref
SR
SR
CLK
ICE
ds022_02_091300
Figure 1: Virtex-E Input/Output Block (IOB)
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Output Switching Characteristics, Figure 1
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 10.
Speed Grade(1)
Description(2)
Propagation Delays
Symbol
Min
-8
-7
-6
Units
O input to Pad
TIOOP
1.04
1.24
2.5
2.9
2.7
3.1
2.9
3.4
ns, max
ns, max
O input to Pad via transparent latch
3-State Delays
TIOOLP
T input to Pad high-impedance (Note 2)
T input to valid data on Pad
TIOTHZ
TIOTON
0.73
1.13
1.5
2.7
1.7
2.9
1.9
3.1
ns, max
ns, max
T input to Pad high-impedance via transparent
latch (Note 2)
TIOTLPHZ
0.86
1.8
2.0
2.2
ns, max
T input to valid data on Pad via transparent latch
GTS to Pad high impedance (Note 2)
Sequential Delays
TIOTLPON
TGTS
1.26
1.94
3.0
4.1
3.2
4.6
3.4
4.9
ns, max
ns, max
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Clock CLK to Pad
TCH
TCL
0.56
0.56
0.97
1.2
1.2
2.4
1.3
1.3
2.8
1.4
1.4
2.9
ns, min
ns, min
ns, max
TIOCKP
Clock CLK to Pad high-impedance (synchronous)
(Note 2)
TIOCKHZ
TIOCKON
0.77
1.17
1.6
2.8
2.0
3.2
2.2
3.4
ns, max
ns, max
Clock CLK to valid data on Pad (synchronous)
Setup and Hold Times before/after Clock CLK
O input
TIOOCK / TIOCKO
TIOOCECK / TIOCKOCE
TIOSRCKO / TIOCKOSR
TIOTCK / TIOCKT
0.43 / 0
0.28 / 0
0.40 / 0
0.26 / 0
0.30 / 0
0.38 / 0
0.9 / 0
0.55 / 0.01
0.8 / 0
1.0 / 0
0.7 / 0
0.9 / 0
0.6 / 0
0.7 / 0
0.9 / 0
1.1 / 0
0.7 / 0
1.0 / 0
0.7 / 0
0.8 / 0
1.0 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
OCE input
SR input (OFF)
0.51 / 0
0.6 / 0
3-State Setup Times, T input
3-State Setup Times, TCE input
3-State Setup Times, SR input (TFF)
Set/Reset Delays
TIOTCECK / TIOCKTCE
T
IOSRCKT / TIOCKTSR
0.8 / 0
SR input to Pad (asynchronous)
TIOSRP
1.30
1.08
3.1
2.2
3.3
2.4
3.5
2.7
ns, max
ns, max
SR input to Pad high-impedance (asynchronous)
(Note 2)
TIOSRHZ
SR input to valid data on Pad (asynchronous)
TIOSRON
TIOGSRQ
1.48
3.88
3.4
7.6
3.7
8.5
3.9
9.7
ns, max
ns, max
GSR to Pad
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. 3-state turn-off delays should not be adjusted.
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
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Module 3 of 4
9
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Speed Grade
Description
Symbol
Standard
Min
-8
-7
-6
Units
Output Delay Adjustments
Standard-specific adjustments for output
delays terminating at pads (based on
standard capacitive load, Csl)
TOLVTTL_S2
TOLVTTL_S4
TOLVTTL_S6
TOLVTTL_S8
TOLVTTL_S12
TOLVTTL_S16
TOLVTTL_S24
TOLVTTL_F2
TOLVTTL_F4
TOLVTTL_F6
TOLVTTL_F8
TOLVTTL_F12
TOLVTTL_F16
TOLVTTL_F24
TOLVCMOS_2
TOLVCMOS_18
TOLVDS
LVTTL, Slow, 2 mA
4 mA
4.2
2.5
+14.7
+7.5
+14.7
+7.5
+14.7
+7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
1.8
+4.8
+4.8
+4.8
8 mA
1.2
+3.0
+3.0
+3.0
12 mA
1.0
+1.9
+1.9
+1.9
16 mA
0.9
+1.7
+1.7
+1.7
24 mA
0.8
+1.3
+1.3
+1.3
LVTTL, Fast, 2 mA
4 mA
1.9
+13.1
+5.3
+13.1
+5.3
+13.1
+5.3
0.7
6 mA
0.20
0.10
0.0
+3.1
+3.1
+3.1
8 mA
+1.0
+1.0
+1.0
12 mA
0.0
0.0
0.0
16 mA
–0.10
–0.10
0.10
0.10
–0.39
–0.20
0.50
0.10
0.6
–0.05
–0.20
+0.09
+0.7
–0.05
–0.20
+0.09
+0.7
–0.05
–0.20
+0.09
+0.7
24 mA
LVCMOS2
LVCMOS18
LVDS
–1.2
–1.2
–1.2
TOLVPECL
TOPCI33_3
TOPCI66_3
TOGTL
LVPECL
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
GTL
–0.41
+2.3
–0.41
+2.3
–0.41
+2.3
–0.41
+0.49
+0.8
–0.41
+0.49
+0.8
–0.41
+0.49
+0.8
TOGTLP
GTL+
0.7
TOHSTL_I
HSTL I
0.10
–0.10
–0.20
–0.10
–0.20
–0.20
–0.30
0.0
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
TOHSTL_III
TOHSTL_IV
TOSSTL2_I
TOSSTL2_II
TOSSTL3_I
TOSSTL3_II
TOCTT
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
TOAGP
AGP
–0.1
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DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Calculation of T
as a Function of Capacitance
ioop
T
is the propagation delay from the O Input of the IOB to
For other capacitive loads, use the formulas below to calcu-
ioop
the pad. The values for T
are based on the standard
late the corresponding T
:
ioop
ioop
capacitive load (C ) for each I/O standard as listed in
Table 3.
sl
T
= T
+ T
+ (C
– C ) * fl
load sl
ioop
ioop
opadjust
where:
Table 3: Constants for Use in Calculation of T
ioop
T
is reported above in the Output Delay
Adjustment section.
opadjust
Standard
LVTTL Fast Slew Rate, 2mA drive
LVTTL Fast Slew Rate, 4mA drive
LVTTL Fast Slew Rate, 6mA drive
LVTTL Fast Slew Rate, 8mA drive
LVTTL Fast Slew Rate, 12mA drive
LVTTL Fast Slew Rate, 16mA drive
LVTTL Fast Slew Rate, 24mA drive
LVTTL Slow Slew Rate, 2mA drive
LVTTL Slow Slew Rate, 4mA drive
LVTTL Slow Slew Rate, 6mA drive
LVTTL Slow Slew Rate, 8mA drive
LVTTL Slow Slew Rate, 12mA drive
LVTTL Slow Slew Rate, 16mA drive
LVTTL Slow Slew Rate, 24mA drive
LVCMOS2
Csl (pF) fl (ns/pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
0
0.41
0.20
C
is the capacitive load for the design.
load
Table 4: Delay Measurement Methodology
0.13
Meas.
Point
VREF
Standard
LVTTL
VL
VH
(Typ)2
1
1
0.079
0.044
0.043
0.033
0.41
0
3
1.4
-
LVCMOS2
PCI33_3
PCI66_3
GTL
0
2.5
Per PCI Spec
Per PCI Spec
VREF +0.2
VREF +0.2
VREF +0.5
VREF +0.5
VREF +0.5
VREF +1.0
1.125
-
-
-
0.20
VREF –0.2
VREF –0.2
VREF –0.5
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0.80
1.0
0.75
0.90
0.90
1.5
1.25
1.5
0.10
GTL+
0.086
0.058
0.050
0.048
0.041
0.050
0.050
0.033
0.014
0.017
0.022
0.016
0.014
0.028
0.016
0.029
0.016
0.035
0.037
HSTL Class I
HSTL Class III VREF –0.5
HSTL Class IV VREF –0.5
SSTL3 I & II
SSTL2 I & II
CTT
VREF –1.0
VREF –0.75 VREF +0.75
VREF –0.2 VREF +0.2
VREF VREF
(0.2xVCCO (0.2xVCCO
LVCMOS18
PCI 33 MHZ 3.3 V
AGP
–
+
Per
AGP
Spec
PCI 66 MHz 3.3 V
)
)
GTL
GTL+
0
LVDS
1.2 –0.125 1.2 + 0.125
1.6 –0.3 1.6 + 0.3
1.2
1.6
HSTL Class I
20
20
20
30
30
30
30
20
10
LVPECL
Notes:
HSTL Class III
HSTL Class IV
1. Input waveform switches between VLand VH.
2. Measurements are made at VREF (Typ), Maximum, and
SSTL2 Class I
Minimum. Worst-case values are reported.
I/O parameter measurements are made with the
capacitance values shown in Table 3. See the application
examples (in Module 2 of this data sheet) for appropriate
terminations.
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
CTT
AGP
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. See the application examples (in
Module 2 of this data sheet) for appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
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Module 3 of 4
11
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Clock Distribution Switching Characteristics
Speed Grade
Description
GCLK IOB and Buffer
Symbol
Min
-8
-7
-6
Units
Global Clock PAD to output.
T
0.38
0.11
0.7
0.7
0.7
ns, max
ns, max
GPIO
Global Clock Buffer I input to O output
T
0.20
0.45
0.50
GIO
I/O Standard Global Clock Input Adjustments
Speed Grade
(1)
Description
Symbol
Standard
Min
-8
-7
-6
Units
Data Input Delay Adjustments
Standard-specific global clock
input delay adjustments
T
LVTTL
LVCMOS2
LVCMOS18
LVDS
0.0
–0.02
0.12
0.23
0.23
–0.05
–0.05
0.20
0.20
0.18
0.21
0.18
0.22
0.21
0.0
0.0
0.0
0.0
0.0
0.0
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
GPLVTTL
T
GPLVCMOS2
T
0.20
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.20
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.20
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
GPLVCMOS18
T
GLVDS
T
LVPECL
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
GTL
GLVPECL
GPPCI33_3
GPPCI66_3
T
T
T
GPGTL
T
GTL+
GPGTLP
GPHSTL
T
HSTL
T
T
SSTL2
GPSSTL2
GPSSTL3
SSTL3
T
CTT
GPCTT
GPAGP
T
AGP
Notes:
1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 4.
Module 3 of 4
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DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used, see Figure 2. The values listed below are
worst-case. Precise values are provided by the timing analyzer.
Speed Grade(1)
Description
Combinatorial Delays
Symbol
Min
-8
-7
-6
Units
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
TILO
TIF5
0.19
0.36
0.35
0.35
0.04
0.40
0.76
0.74
0.74
0.11
0.42
0.8
0.47
0.9
ns, max
ns, max
ns, max
ns, max
ns, max
TIF5X
TIF6Y
TF5INY
0.8
0.9
0.9
1.0
0.20
0.22
Incremental delay routing through transparent latch to
XQ/YQ outputs
TIFNCTL
TBYYB
0.27
0.19
0.63
0.38
0.7
0.8
ns, max
ns, max
BY input to YB output
0.46
0.51
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times before/after Clock CLK
4-input function: F/G Inputs
TCKO
0.34
0.40
0.78
0.77
0.9
0.9
1.0
1.0
ns, max
ns, max
TCKLO
TICK
/
0.39 / 0
0.55 / 0
0.27 / 0
0.58 / 0
0.25 / 0
0.28 / 0
0.24 / 0
0.9 / 0
1.3 / 0
0.6 / 0
1.3 / 0
0.6 / 0
0.55 / 0
0.46 / 0
1.0 / 0
1.4 / 0
0.8 / 0
1.5 / 0
0.7 / 0
0.7 / 0
0.52 / 0
1.1 / 0
1.5 / 0
0.8 / 0
1.6 / 0
0.8 / 0
0.7 / 0
0.6 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
TCKI
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
TIF5CK /
TCKIF5
TF5INCK
TCKF5IN
/
TIF6CK
TCKIF6
/
TDICK
TCKDI
/
CE input
TCECK /
TCKCE
SR/BY inputs (synchronous)
TRCK /
TCKR
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
TCH
TCL
0.56
0.56
1.2
1.2
1.3
1.3
1.4
1.4
ns, min
ns, min
Minimum Pulse Width, SR/BY inputs
TRPW
TRQ
0.94
0.39
-
1.9
0.8
416
2.1
0.9
400
2.4
1.0
357
ns, min
ns, max
MHz
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
Toggle Frequency (MHz) (for export control)
FTOG
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
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Module 3 of 4
13
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
COUT
CY
YB
Y
G4
G3
G2
G1
I3
I2
I1
I0
O
LUT
WE
INIT
D Q
CE
YQ
DI
0
1
REV
BY
XB
F5IN
F6
CY
F5
X
F5
BY DG
CK WSO
WE
BX
WSH
A4
DI
INIT
D Q
CE
XQ
BX
DI
WE
I3
I2
I1
I0
F4
F3
F2
F1
REV
O
LUT
0
1
SR
CLK
CE
ds022_05_092000
CIN
Figure 2: Detailed View of Virtex-E Slice
Module 3 of 4
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Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
(1)
Speed Grade
Description
Combinatorial Delays
Symbol
Min
-8
-7
-6
Units
F operand inputs to X via XOR
F operand input to XB output
F operand input to Y via XOR
F operand input to YB output
F operand input to COUT output
G operand inputs to Y via XOR
G operand input to YB output
G operand input to COUT output
BX initialization input to COUT
CIN input to X output via XOR
CIN input to XB
T
0.32
0.35
0.59
0.48
0.37
0.34
0.47
0.36
0.19
0.27
0.02
0.26
0.16
0.05
0.68
0.65
1.07
0.89
0.71
0.72
0.78
0.60
0.36
0.50
0.04
0.45
0.28
0.10
0.8
0.8
0.8
0.9
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
OPX
T
OPXB
T
1.4
1.5
OPY
T
1.1
1.3
OPYB
T
0.9
1.0
OPCYF
T
0.8
0.9
OPGY
T
1.2
1.3
OPGYB
T
0.9
1.0
OPCYG
T
0.51
0.6
0.57
0.7
BXCY
T
CINX
T
T
0.07
0.7
0.08
0.7
CINXB
CIN input to Y via XOR
T
CINY
CIN input to YB
0.38
0.14
0.43
0.15
CINYB
CIN input to COUT output
T
BYP
Multiplier Operation
F1/2 operand inputs to XB output via AND
F1/2 operand inputs to YB output via AND
F1/2 operand inputs to COUT output via AND
G1/2 operand inputs to YB output via AND
G1/2 operand inputs to COUT output via AND
Setup and Hold Times before/after Clock CLK
CIN input to FFX
T
0.10
0.28
0.17
0.20
0.09
0.30
0.56
0.38
0.46
0.28
0.35
0.7
0.39
0.8
ns, max
ns, max
ns, max
ns, max
ns, max
FANDXB
T
FANDYB
FANDCY
GANDYB
GANDCY
T
0.46
0.55
0.30
0.51
0.7
T
T
0.34
T
T
/T
0.47 / 0
0.49 / 0
1.0 / 0
1.2 / 0
1.2 / 0
1.3 / 0
1.3 / 0
ns, min
ns, min
CCKX CKCX
CIN input to FFY
/T
0.92 / 0
CCKY CKCY
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS022-3 (v2.9.2) March 14, 2003
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Module 3 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
CLB Distributed RAM Switching Characteristics
(1)
Speed Grade
Description
Symbol
Min
-8
-7
-6
Units
Sequential Delays
Clock CLK to X/Y outputs (WE active) 16 x 1 mode
Clock CLK to X/Y outputs (WE active) 32 x 1 mode
Shift-Register Mode
T
T
0.67
0.84
1.38
1.66
1.5
1.9
1.7
2.1
ns, max
ns, max
SHCKO16
SHCKO32
Clock CLK to X/Y outputs
T
1.25
2.39
2.9
3.2
ns, max
REG
Setup and Hold Times before/after Clock CLK
F/G address inputs
T /T
0.19 / 0
0.44 / 0
0.29 / 0
0.38 / 0 0.42 / 0 0.47 / 0 ns, min
0.87 / 0 0.97 / 0 1.09 / 0 ns, min
AS AH
BX/BY data inputs (DIN)
T
/T
DS DH
SR input (WE)
T
/T
0.57 / 0 0.7 / 0
0.8 / 0
ns, min
WS WH
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
Shift-Register Mode
T
0.96
0.96
1.92
1.9
1.9
3.8
2.1
2.1
4.2
2.4
2.4
4.8
ns, min
ns, min
ns, min
WPH
T
WPL
T
WC
Minimum Pulse Width, High
Minimum Pulse Width, Low
Notes:
T
1.0
1.0
1.9
1.9
2.1
2.1
2.4
2.4
ns, min
ns, min
SRPH
T
SRPL
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
RAMB4_S#_S#
WEA
ENA
RSTA
DOA[#:0]
CLKA
ADDRA[#:0]
DIA[#:0]
WEB
ENB
RSTB
DOB[#:0]
CLKB
ADDRB[#:0]
DIB[#:0]
ds022_06_121699
Figure 3: Dual-Port Block SelectRAM
Module 3 of 4
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Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Block RAM Switching Characteristics
(1)
Speed Grade
Description
Sequential Delays
Symbol
Min
-8
-7
-6
Units
Clock CLK to DOUT output
Setup and Hold Times before Clock CLK
ADDR inputs
T
0.63
2.46
3.1
3.5
ns, max
BCKO
T
/T
0.42 / 0
0.42 / 0
0.97 / 0
0.9 / 0
0.9 / 0
0.9 / 0
2.0 / 0
1.8 / 0
1.7 / 0
1.0 / 0
1.0 / 0
2.2 / 0
2.1 / 0
2.0 / 0
1.1 / 0
1.1 / 0
2.5 / 0
2.3 / 0
2.2 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
BACK BCKA
DIN inputs
T
/T
BDCK BCKD
EN input
T
/T
BECK BCKE
RST input
T
/T
BRCK BCKR
WEN input
T
/T
0.86 / 0
BWCK BCKW
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
CLKA -> CLKB setup time for different ports
Notes:
T
0.6
0.6
1.2
1.2
1.2
2.4
1.35
1.35
2.7
1.5
1.5
3.0
ns, min
ns, min
ns, min
BPWH
T
BPWL
BCCS
T
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
TBUF Switching Characteristics
Speed Grade
Description
Combinatorial Delays
Symbol
Min
-8
-7
-6
Units
IN input to OUT output
T
0.0
0.0
0.0
0 .0
0.11
0.11
ns, max
ns, max
ns, max
IO
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
T
0.05
0.05
0.092
0.092
0.10
0.10
OFF
T
ON
JTAG Test Access Port Switching Characteristics
Description
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Symbol
Value
Units
ns, min
T
4.0
2.0
11.0
33
TAPTK
T
ns, min
TCKTAP
TCKTDO
T
ns, max
MHz, max
F
TCK
DS022-3 (v2.9.2) March 14, 2003
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Module 3 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
(2, 3)
Speed Grade
(1)
Description
Symbol
Device
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
-8
-7
-6
Units
ns
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, with
DLL. For data output with different standards,
adjust the delays with the values shown in IOB
Output Switching Characteristics Standard
Adjustments, page 10.
T
XCV50E
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
ICKOFDLL
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 3 and Table 4.
3. DLL output jitter is already included in the timing calculation.
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Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
(2)
Speed Grade
(1)
Description
Symbol
Device
Min
1.5
1.5
1.5
1.5
1.5
1.6
1.7
1.8
1.8
2.0
2.2
-8
-7
-6
Units
ns
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without
DLL. For data output with different standards,
adjust the delays with the values shown in IOB
Output Switching Characteristics Standard
Adjustments, page 10.
T
XCV50E
4.2
4.2
4.3
4.3
4.4
4.5
4.6
4.7
4.8
5.0
5.2
4.4
4.4
4.5
4.5
4.6
4.7
4.8
4.9
5.0
5.2
5.4
4.6
4.6
4.7
4.7
4.8
4.9
5.0
5.1
5.2
5.4
5.6
ICKOF
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 3 and Table 4.
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Virtex-E Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
(2, 3)
Speed Grade
(1)
Description
Symbol
Device
Min
-8
-7
-6
Units
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard. For data input with different standards,
adjust the setup time delay by the values shown in IOB Input
Switching Characteristics Standard Adjustments, page 8.
No Delay
T
/T
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PSDLL PHDLL
Global Clock and IFF, with DLL
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
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Global Clock Set-Up and Hold for LVTTL Standard, without DLL
(2, 3)
Speed Grade
-8
(1)
Description
Symbol
Device
Min
-7
-6
Units
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard. For data input with different standards, adjust
the setup time delay by the values shown in IOB Input Switching
Characteristics Standard Adjustments, page 8.
Full Delay
T
/T
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
1.8 / 0
1.8 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.3 / 0
2.5 / 0
2.5 / 0
2.7 / 0
2.8 / 0
1.8 / 0
1.8 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.3 / 0
2.5 / 0
2.5 / 0
2.7 / 0
2.8 / 0
1.8 / 0
1.8 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.3 / 0
2.5 / 0
2.5 / 0
2.7 / 0
2.8 / 0
1.8 / 0
1.8 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.3 / 0
2.5 / 0
2.5 / 0
2.7 / 0
2.8 / 0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PSFD PHFD
Global Clock and IFF, without DLL
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
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DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
Speed Grade
-8
-7
-6
Description
Symbol
FCLKINHF
FCLKINLF
FCLKIN
Min
60
Max
350
160
Min
60
Max
320
160
Min Max Units
Input Clock Frequency (CLKDLLHF)
Input Clock Frequency (CLKDLL)
Input Clock Low/High Pulse Width
60
25
275
135
MHz
MHz
ns
25
25
T
≥2 5 MHz
≥ 50 MHz
≥100 MHz
5.0
3.0
2.4
2.0
5.0
3.0
2.4
2.0
5.0
3.0
2.4
2.0
DLLPW
ns
ns
≥ 150
ns
MHz
≥ 200
MHz
1.8
1.5
1.3
1.8
1.5
1.3
1.8
1.5
NA
ns
ns
ns
≥ 250
MHz
≥ 300
MHz
Period Tolerance: the allowed input clock period change in nanoseconds.
+ T
_
IPTOL
T
T
CLKIN
CLKIN
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
Phase Offset and Maximum Phase Difference
Ideal Period
Actual Period
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
ds022_24_091200
Figure 4: DLL Timing Waveforms
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DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
CLKDLLHF
CLKDLL
Min Max Units
Description
Input Clock Period Tolerance
Symbol
TIPTOL
TIJITCC
TLOCK
FCLKIN
Min
Max
1.0
-
-
-
-
-
-
-
-
1.0
± 300
20
ns
ps
μs
μs
μs
μs
μs
ps
ps
ps
ps
ps
Input Clock Jitter Tolerance (Cycle to Cycle)
Time Required for DLL to Acquire Lock(6)
± 150
20
-
-
-
-
-
-
> 60 MHz
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
25 - 30 MHz
-
25
-
50
-
90
-
120
Output Jitter (cycle-to-cycle) for any DLL Clock Output(1)
Phase Offset between CLKIN and CLKO(2)
Phase Offset between Clock Outputs on the DLL(3)
Maximum Phase Difference between CLKIN and CLKO(4)
Maximum Phase Difference between Clock Outputs on the DLL(5)
Notes:
TOJITCC
TPHIO
± 60
± 100
± 140
± 160
± 200
± 60
± 100
± 140
± 160
± 200
TPHOO
TPHIOM
TPHOOM
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excluding
input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6. Add 30% to the value for industrial grade parts.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T
values, buffered Hex Line info, p. 8, I/O Timing
BYP
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
7/10/00
1.3
1.4
1.5
Updated pinout tables, V page 20, and corrected Figure 20.
CC
Correction to table on p. 22.
•
Numerous minor edits.
•
•
•
•
•
•
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
8/1/00
1.6
1.7
Min values added to Virtex-E Electrical Characteristics tables.
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
9/20/00
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate V
pins in Table ~ (Module 4).
CCINT
•
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
11/20/00
1.8
•
•
•
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for T
, T
, T
, and T
.
SHCKO32 REG BCCS
ICKOF
•
Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
•
Revised maximum T
in -6 speed grade for DLL Timing Parameters.
DLLPW
•
•
•
Changed GCLK0 to BA22 for FG860 package in Table 46.
Revised footnote for Table 14.
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
2/12/01
1.9
•
•
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
•
•
•
•
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
Updated numerous values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format. See the Virtex-E Data Sheet section.
Updated values in Virtex-E Switching Characteristics tables.
4/02/01
4/19/01
2.0
2.1
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Revision
Date
Version
•
•
Under Absolute Maximum Ratings, changed (T
) to 220 °C.
SOL
07/23/01
2.2
Changes made to SSTL symbol names in IOB Input Switching Characteristics
Standard Adjustments table.
•
•
•
Removed T
parameter and added footnote to Absolute Maximum Ratings table.
SOL
07/26/01
9/18/01
2.3
2.4
2.5
Reworded power supplies footnote to Absolute Maximum Ratings table.
Updated the speed grade designations used in data sheets, and added Table 1, which
shows the current speed grade designation for each device.
10/25/01
•
Added XCV2600E and XCV3200E values to DC Characteristics Over Recommended
Operating Conditions and Power-On Power Supply Requirements tables.
•
•
Updated the Power-On Power Supply Requirements table.
11/09/01
02/01/02
2.6
2.7
Updated footnotes to the DC Input and Output Levels and DLL Clock Tolerance,
Jitter, and Phase Information tables.
•
•
•
•
Data sheet designation upgraded from Preliminary to Production.
Removed mention of MIL-M-38510/605 specification.
Added link to XAPP158 from the Power-On Power Supply Requirements section.
07/17/02
2.8
Revised V in Absolute Maximum Ratings table.
09/10/02
2.9
IN
•
Added Clock CLK switching characteristics to Table 2, “IOB Input Switching
Characteristics,” on page 6 and IOB Output Switching Characteristics, Figure 1.
•
•
•
Added footnote regarding V PCI compliance to Absolute Maximum Ratings table.
12/22/02
03/14/03
2.9.1
2.9.2
IN
The fastest ramp rate is 0V to nominal voltage in 2 ms
Under Power-On Power Supply Requirements, the fastest ramp rate is no longer a
"suggested" rate.
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•
DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•
DS022-2, Virtex-E 1.8V FPGAs:
DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
Pinout Tables (Module 4)
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Field Programmable Gate Arrays
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0
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Virtex-E Pin Definitions
Pin Name
Dedicated Pin
Direction
Description
GCK0, GCK1,
GCK2, GCK3
Yes
Input
Clock input pins that connect to Global Clock Buffers.
Mode pins are used to specify the configuration mode.
M0, M1, M2
CCLK
Yes
Yes
Input
Input or
Output
The configuration Clock I/O pin: it is an input for SelectMAP and
slave-serial modes, and output in master-serial mode. After
configuration, it is input only, logic level = Don’t Care.
PROGRAM
DONE
Yes
Yes
Input
Initiates a configuration sequence when asserted Low.
Bidirectional Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
INIT
No
No
Bidirectional When Low, indicates that the configuration memory is being cleared.
The pin becomes a user I/O after configuration.
(Open-drain)
BUSY/DOUT
Output
In SelectMAP mode, BUSY controls the rate at which configuration
data is loaded. The pin becomes a user I/O after configuration unless
the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data
to downstream devices in a daisy-chain. The pin becomes a user I/O
after configuration.
D0/DIN,
D1, D2,
D3, D4,
D5, D6,
D7
No
Input or
Output
In SelectMAP mode, D0-7 are configuration data pins. These pins
become user I/Os after configuration unless the SelectMAP port is
retained.
In bit-serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.
WRITE
No
No
Input
Input
Mixed
In SelectMAP mode, the active-low Write Enable signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.
CS
In SelectMAP mode, the active-low Chip Select signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.
TDI, TDO,
TMS, TCK
DXN, DXP
Yes
Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.
Yes
Yes
Yes
No
N/A
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
Power-supply pins for the internal core logic.
V
Input
Input
Input
CCINT
V
Power-supply pins for the output drivers (subject to banking rules)
CCO
V
Input threshold voltage pins. Become user I/Os when an external
threshold voltage is not needed (subject to banking rules).
REF
GND
Yes
Input
Ground
© 2000-2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Pinout Differences Between Virtex and Virtex-E Families
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions, listed in Table 1.
All Devices, PQ240 and HQ240 Packages
The Virtex devices in PQ240 and HQ240 packages do not
have V
banking, but Virtex-E devices do. To achieve
CCO
this, eight Virtex I/O pins (P232, P207, P176, P146, P116,
P85, P55, and P25) are now VCCO pins in the Virtex-E fam-
ily. This change also requires one Virtex I/O or VREF pin to
be swapped with a standard I/O pin.
XCV200E Device, FG456 Package
The Virtex-E XCV200E has two I/O pins swapped with the
Virtex XCV200 to accommodate differential clock pairing.
Additionally, accommodating differential clock input pairs in
XCV400E Device, FG676 Package
The Virtex-E XCV400E has two I/O pins swapped with the
Virtex XCV400 to accommodate differential clock pairing.
Virtex-E caused some IO_V
differences in the XCV400E
REF
and XCV600E devices only. Virtex IO_V
pins P215 and
REF
P87 are Virtex-E IO_V
pins P216 and P86, respectively.
REF
Virtex-E pins P215 and P87 are IO_DLL.
Table 1: Pinout Differences Summary
Part
Package
FG456
Pins
Virtex
I/O
Virtex-E
XCV200
E11, U11
B11, AA11
D13, Y13
B13, AF13
No Connect
No Connect
I/O
IO_LVDS_DLL
No Connect
XCV400
FG676
No Connect
IO_LVDS_DLL
IO_LVDS_DLL
XCV400/600 PQ240/HQ240 P215, P87
P216, P86
IO_V
I/O
REF
IO_V
REF
All
PQ240/HQ240 P232, P207, P176, P146, P116, P85, P55, and P25 I/O
P231 I/O
V
CCO
IO_V
REF
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Table 2: LVDS Pin Pairs
Pin Name
Low Voltage Differential Signals
The Virtex-E family incorporates low-voltage signalling
(LVDS and LVPECL). Two pins are utilized for these signals
to be connected to a Virtex-E device. These are known as
differential pin pairs. Each differential pin pair has a Positive
(P) and a Negative (N) pin. These pairs are labeled in the
following manner.
Description
IO_L#[P/N]
Represents a general IO or a
synchronous input/output
differential signal. When used
as a differential signal, N
means Negative I/O and P
means Positive I/O.
Example: IO_L22N
IO_L#[P/N]
where
IO_L#[P/N]_Y
Represents a general IO or a
synchronous input/output
differential signal, or a
part-dependent asynchronous
output differential signal.
L = LVDS or LVPECL pin
# = Pin Pair Number
P = Positive
Example: IO_L22N_Y
N = Negative
IO_L#[P/N]_YY
Represents a general IO or a
synchronous input/output
differential signal, or an
asynchronous output
I/O pins for differential signals can either be synchronous or
asynchronous, input or output. The pin pairs can be used for
synchronous input and output signals as well as asynchro-
nous input signals. However, only some of the low-voltage
pairs can be used for asynchronous output signals.
Example: O_L22N_YY
differential signal.
IO_LVDS_DLL_L#[P/N] Represents a general IO or a
synchronous input/output
DIfferential signals require the pins of a pair to switch almost
simultaneously. If the signals driving the pins are from IOB
flip-flops, they are synchronous. If the signals driving the
pins are from internal logic, they are asynchronous. Table 2
defines the names and function of the different types of
low-voltage pin pairs in the Virtex-E family.
differential signal, a differential
clock input signal, or a DLL
Example:
IO_LVDS_DLL_L16N
input. When used as a
differential clock input, this pin
is paired with the adjacent
GCK pin. The GCK pin is
always the positive input in the
differential clock input
configuration.
Virtex-E Package Pinouts
The Virtex-E family of FPGAs is available in 12 popular
packages, including chip-scale, plastic and high heat-dissi-
pation quad flat packs, and ball grid and fine-pitch ball grid
arrays. Family members have footprint compatibility across
devices provided in the same package. The pinout tables in
this section indicate function, pin, and bank information for
each package/device combination. Following each pinout
table is an additional table summarizing information specific
to differential pin pairs for all devices provided in that pack-
age.
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CS144 Chip-Scale Package
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in CS144 Chip-scale packages have footprint com-
patibility. In the CS144 package, bank pairs that share a
side are internally interconnected, permitting four choices
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank
Pin Description
IO_VREF
Pin #
A10
B8
1
1
1
for V
. See Table 3.
CCO
IO_VREF
1
IO_VREF
B10
Table 3: I/O Bank Pairs and Shared Vcco Pins
Paired Banks
Banks 0 & 1
Banks 2 & 3
Banks 4 & 5
Banks 6 & 7
Shared V
Pins
CCO
A2, A13, D7
B12, G11, M13
N1, N7, N13
B2, G2, M2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
D12
F12
C11
C12
E10
IO_DOUT_BUSY_L6P_YY
IO_DIN_D0_L6N_YY
IO_D1_L7N
Pins labeled I0_VREF can be used as either in all parts
unless device-dependent, as indicated in the footnotes. If
the pin is not used as V , it can be used as general I/O.
Immediately following Table 4, see Table 5 is Differential
Pair information.
2
IO_VREF_L7P
IO_L8N_YY
D13
E13
E12
F11
F10
F13
REF
IO_D2_L8P_YY
IO_D3_L9N
IO_VREF_L9P
IO_L10P
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank
Pin Description
GCK3
Pin #
A6
1
0
0
0
0
0
0
0
0
0
0
IO_VREF
C13
IO
B3
IO_VREF
D11
2
IO_VREF_L0N_YY
IO_L0P_YY
IO_L1N_YY
IO_L1P_YY
IO_LVDS_DLL_L2N
IO_VREF
B4
A4
B5
A5
C6
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
H13
K13
G13
H11
H12
J13
IO
IO_L10N
IO_VREF_L11N
IO_D4_L11P
IO_D5_L12N_YY
IO_L12P_YY
IO_VREF_L13N
IO_D6_L13P
IO_INIT_L14N_YY
IO_D7_L14P_YY
IO_VREF
1
A3
IO_VREF
C4
D6
IO_VREF
H10
2
J10
1
1
1
1
1
1
1
1
1
GCK2
IO
A7
A8
B7
C8
D8
C9
J11
L13
K10
IO_LVDS_DLL_L2P
IO_L3N_YY
1
K11
IO_L3P_YY
IO_VREF
K12
IO_L4N_YY
2
IO_VREF_L4P_YY
IO_WRITE_L5N_YY
IO_CS_L5P_YY
D9
4
4
4
GCK0
IO
K7
M8
C10
D10
IO
M10
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank
Pin Description
IO_L15N_YY
IO_L15P_YY
IO_L16N_YY
IO_VREF_L16P_YY
IO_L17N_YY
IO_L17P_YY
IO_LVDS_DLL_L18P
IO_VREF
Pin #
M11
L11
K9
Bank
Pin Description
Pin #
4
4
4
4
4
4
4
4
4
4
6
IO_L26N
G1
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
C2
D3
F3
F2
F4
E1
E2
E3
D1
2
N10
K8
N9
N8
L8
IO
IO_L26P
IO_L27N
IO_VREF_L27P
IO_L28N_YY
IO_L28P_YY
IO_L29N
IO_VREF_L29P
IO_VREF
IO_VREF
IO_VREF
L10
1
IO_VREF
N11
2
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO
M7
M4
M6
N5
K6
D2
1
C1
IO_LVDS_DLL_L18N
IO_L19N_YY
IO_L19P_YY
IO_VREF_L20N_YY
IO_L20P_YY
IO_L21N_YY
IO_L21P_YY
IO_VREF
D4
2
CCLK
DONE
M0
B13
M12
M1
2
N4
3
K5
M3
N3
NA
NA
NA
NA
NA
NA
2
M1
L2
M2
N2
1
K4
PROGRAM
TDI
L12
A11
C3
IO_VREF
L4
L6
IO_VREF
TCK
TDO
A12
B1
6
6
6
6
6
6
6
6
6
6
6
6
IO
G4
J4
NA
TMS
IO
IO_L25P
H1
H2
H3
H4
J2
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A9
B6
IO_VREF_L25N
IO_L24P_YY
IO_L24N_YY
IO_L23P
C5
G3
G12
M5
M9
N6
2
IO_VREF_L23N
IO_VREF
J3
K1
1
IO_VREF
K2
IO_L22N_YY
IO_L22P_YY
L1
K3
0
VCCO
A2
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Module 4 of 4
5
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 4: CS144 — XCV50E, XCV100E, XCV200E
CS144 Differential Pin Pairs
Bank
Pin Description
VCCO
Pin #
A13
D7
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
1
1
2
3
3
4
5
5
6
7
7
VCCO
VCCO
B12
G11
M13
N13
N1
VCCO
VCCO
VCCO
VCCO
VCCO
N7
Table 5: CS144 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E
VCCO
M2
VCCO
B2
P
N
Other
VCCO
G2
Pair Bank
Pin
Pin
AO
Functions
Global Differential Clock
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
B9
0
1
2
3
4
5
1
0
K7
M7
A7
A6
N8
M6
NA
NA
NA
NA
IO_DLL_L18P
IO_DLL_L18N
IO_DLL_L2P
IO_DLL_L2N
NA
B11
C7
D5
E4
B7
NA
C6
NA
IO LVDS
NA
Total Pairs: 30, Asynchronous Output Pairs: 18
NA
E11
F1
0
1
0
0
1
1
1
1
2
2
2
2
3
3
3
3
3
4
4
4
A4
A5
B4
B5
√
√
VREF
NA
-
NA
G10
J1
2
B7
C6
NA
√
IO_LVDS_DLL
NA
3
D8
C8
-
VREF
CS, WRITE
DIN, D0
D1, VREF
D2
NA
J12
L3
4
D9
C9
√
NA
5
D10
C11
D13
E12
F10
F13
H12
H10
J11
K10
L11
N10
N9
C10
C12
E10
E13
F11
G13
H11
J13
J10
L13
M11
K9
√
NA
L5
6
√
NA
L7
7
1
NA
L9
8
√
NA
N12
9
1
D3, VREF
-
Notes:
10
11
12
13
14
15
16
17
NA
1
1. VREF or I/O option only in the XCV200E; otherwise, I/O
option only.
D4, VREF
D5
2. VREF or I/O option only in the XCV100E, 200E; otherwise,
I/O option only.
√
1
D6, VREF
INIT
√
√
-
√
VREF
-
K8
√
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 5: CS144 Differential Pin Pair Summary
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV50E, XCV100E, XCV200E
XCV300E, XCV400E
P
N
Other
Pin #
P222
P221
P220
P218
P217
Pin Description
IO
Bank
Pair Bank
Pin
Pin
AO
NA
√
Functions
0
0
0
0
0
0
0
0
18
19
20
21
22
23
24
25
26
27
28
29
5
5
5
5
6
6
6
6
7
7
7
7
N8
K6
K5
N3
K3
J2
M6
N5
N4
M3
L1
IO_LVDS_DLL
IO_L4N_Y
-
IO_L4P_Y
√
VREF
IO_VREF_L5N_Y
IO_L5P_Y
√
-
3
√
-
P216
P215
P213
IO_VREF
J3
1
VREF
IO_LVDS_DLL_L6N
GCK3
H3
H1
F2
E1
E3
D2
H4
H2
G1
F4
E2
D1
√
-
1
VREF
-
NA
1
P210
P209
GCK2
IO_LVDS_DLL_L6P
IO_VREF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VREF
-
3
√
P208
P206
P205
P203
P202
P201
P200
P199
P195
1
VREF
IO_L7N_Y
Note 1: AO in the XCV50E
IO_VREF_L7P_Y
IO_L8N_Y
PQ240 Plastic Quad Flat-Pack Packages
IO_L8P_Y
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in PQ240 Plastic Flat-pack packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as V , it can be used as gen-
eral I/O. Immediately following Table 6, see Table 7 for
Differential Pair information.
IO
IO_L9N_YY
IO_L9P_YY
REF
IO_L10N_YY
IO_VREF_L10P_YY
IO
1
P194
P193
P192
P191
P189
P188
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
IO_L11N_YY
IO_VREF_L11P_YY
IO_L12N_YY
IO_L12P_YY
IO_VREF_L13N_Y
IO_L13P_Y
Pin #
P238
P237
Pin Description
IO
Bank
0
0
0
0
0
0
0
0
0
0
0
IO_L0N_Y
2
2
P187
P186
P185
P184
P236
P235
P234
P231
P230
IO_VREF_L0P_Y
IO_L1N_YY
IO_L1P_YY
IO_VREF
IO_WRITE_L14N_YY
IO_CS_L14P_YY
IO
1
P178
P177
IO_DOUT_BUSY_L15P_YY
IO_DIN_D0_L15N_YY
IO_VREF
2
2
2
2
P229
P228
P224
P223
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N_YY
IO_L3P_YY
2
P175
P174
IO_L16P_Y
DS022-4 (v2.5) March 14, 2003
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Module 4 of 4
7
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
XCV300E, XCV400E
Pin #
P173
P171
P170
P169
Pin Description
IO_L16N_Y
Bank
Pin #
P125
P124
P123
Pin Description
IO_L30N_Y
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
IO_VREF_L17P_Y
IO_L17N_Y
IO_D7_L31P_YY
IO_INIT_L31N_YY
IO
1
P168
P167
P163
P162
P161
P160
P159
P157
P156
P155
IO_VREF_L18P_Y
IO_D1_L18N_Y
IO_D2_L19P_YY
IO_L19N_YY
IO
P118
P117
IO_L32P_YY
IO_L32N_YY
IO_VREF
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
P115
P114
P113
P111
P110
P109
IO_L33P_YY
IO_L33N_YY
IO_VREF_L34P_YY
IO_L34N_YY
IO
IO_L20P_Y
IO_L20N_Y
IO_VREF_L21P_Y
IO_D3_L21N_Y
IO_L22P_Y
1
P108
P107
P103
P102
P101
P100
P99
IO_VREF_L35P_YY
IO_L35N_YY
IO_L36P_YY
IO_L36N_YY
IO
3
P154
P153
P152
IO_VREF_L22N_Y
IO_L23P_YY
IO_L23N_YY
IO_L37P_Y
P149
IO
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L37N_Y
3
P147
P145
P144
P142
P141
P140
P139
P138
P134
IO_VREF
P97
IO_VREF_L38P_Y
IO_L38N_Y
IO_D4_L24P_Y
IO_VREF_L24N_Y
IO_L25P_Y
P96
P95
IO_L39P_Y
3
P94
IO_VREF_L39N_Y
IO_LVDS_DLL_L40P
GCK0
IO_L25N_Y
P93
P92
IO
IO_L26P_YY
IO_D5_L26N_YY
IO_D6_L27P_Y
IO_VREF_L27N_Y
IO
P89
P87
GCK1
IO_LVDS_DLL_L40N
IO_VREF
5
5
5
5
5
5
5
5
5
1
3
P133
P132
P131
P130
P128
P127
P86
P84
P82
P81
P80
P79
P78
IO_VREF_L41P_Y
IO_L41N_Y
IO
IO_L28P_Y
IO_VREF_L28N_Y
IO_L29P_Y
IO
IO_L29N_Y
IO_L42P_YY
IO_L42N_YY
2
P126
IO_VREF_L30P_Y
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
XCV300E, XCV400E
Pin #
Pin Description
IO_L43P_YY
IO_VREF_L43N_YY
IO
Bank
Pin #
Pin Description
IO_VREF
Bank
7
3
P74
5
5
5
5
5
5
5
5
5
5
5
P26
1
P73
P24
P23
P21
P20
P19
P18
P17
P13
IO_L57N_Y
IO_VREF_L57P_Y
IO_L58N_Y
IO_L58P_Y
IO
7
P72
P71
P70
P68
P67
7
IO_L44P_YY
IO_VREF_L44N_YY
IO_L45P_YY
IO_L45N_YY
IO_VREF_L46P_Y
IO_L46N_Y
7
7
7
IO_L59N_YY
IO_L59P_YY
IO_L60N_Y
IO_VREF_L60P_Y
IO
7
2
P66
7
P65
P64
P63
7
1
IO_L47P_YY
IO_L47N_YY
P12
7
P11
P10
P9
7
IO_L61N_Y
IO_VREF_L61P_Y
IO_L62N_Y
IO_L62P_Y
IO_VREF_L63N_Y
IO_L63P_Y
IO
7
P57
P56
IO_L48N_YY
IO_L48P_YY
IO_VREF
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
P7
7
2
P54
P6
7
2
P53
P52
P50
P49
P48
IO_L49N_Y
IO_L49P_Y
IO_VREF_L50N_Y
IO_L50P_Y
IO
P5
7
P4
P3
7
7
P179
P120
P60
CCLK
DONE
M0
2
1
P47
IO_VREF_L51N_Y
IO_L51P_Y
IO_L52N_YY
IO_L52P_YY
IO
3
P46
P42
P41
P40
P39
P38
P36
P35
P34
NA
NA
NA
NA
NA
NA
2
P58
M1
P62
M2
P122
P183
P239
P181
P2
PROGRAM
TDI
IO_L53N_Y
IO_L53P_Y
IO_VREF_L54N_Y
IO_L54P_Y
IO_L55N_Y
IO_VREF_L55P_Y
IO
TCK
TDO
TMS
NA
3
P33
P225
P214
P198
P164
P148
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
NA
NA
NA
NA
NA
P31
P28
P27
IO_L56N_YY
IO_L56P_YY
7
7
DS022-4 (v2.5) March 14, 2003
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Module 4 of 4
9
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
XCV300E, XCV400E
Pin #
P137
P104
P88
Pin Description
VCCINT
Bank
NA
NA
NA
NA
NA
NA
NA
Pin #
P219
P211
P204
P196
P190
P182
P172
P166
P158
P151
P143
P135
P129
P119
P112
P106
P98
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
P77
VCCINT
P43
VCCINT
P32
VCCINT
P16
VCCINT
P240
P232
P226
P212
P207
P197
P180
P176
P165
P150
P146
P136
P121
P116
P105
P90
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
7
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
P91
P83
P75
P69
P59
P51
P45
P85
P37
P76
P29
P61
P22
P55
P14
P44
P8
P30
P1
Notes:
P25
1. VREF or I/O option only in the XCV100E, 200E, 300E, 400E;
P15
otherwise, I/O option only.
2.
V
REF or I/O option only in the XCV200E, 300E, 400E;
otherwise, I/O option only.
3. VREF or I/O option only in the XCV400E; otherwise, I/O
option only.
P233
P227
GND
GND
NA
NA
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
PQ240 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
Other
Pair Bank P Pin
N Pin AO
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
P174
P171
P168
P163
P160
P157
P155
P153
P145
P142
P139
P134
P131
P128
P126
P124
P118
P114
P111
P108
P103
P100
P97
P173
P170
P167
P162
P159
P156
P154
P152
P144
P141
P138
P133
P130
P127
P125
P123
P117
P113
P110
P107
P102
P99
2
3
4
√
2
4
5
√
4
2
√
4
3
2
6
√
√
√
√
√
√
3
3
7
NA
8
√
√
√
√
1
√
-
VREF
D1, VREF
D2
-
a differential pair or differential clock.
D3, VREF
.
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
VREF
-
Other
D4, VREF
Pair Bank P Pin
N Pin AO
Functions
-
Global Differential Clock
D5
0
1
2
3
4
5
1
0
P92
P89
P93
P87
NA
NA
NA
NA
IO_DLL_L40P
IO_DLL_L40N
IO_DLL_L6P
IO_DLL_L6N
VREF
VREF
P210
P213
P209
-
P215
VREF
IO LVDS
Total Pairs: 64, Asynchronous Outputs Pairs: 27
INIT
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
P236
P234
P228
P223
P220
P217
P209
P205
P202
P199
P194
P191
P188
P186
P184
P178
P237
P235
P229
P224
P221
P218
P215
P206
P203
P200
P195
P192
P189
P187
P185
P177
1
√
VREF
-
-
-
2
√
VREF
VREF
3
√
-
VREF
4
3
-
-
5
3
VREF
-
6
NA
3
IO_LVDS_DLL
P96
VREF
7
VREF
-
P95
P94
VREF
8
3
P93
P87
IO_LVDS_DLL
9
√
-
P84
P82
VREF
10
11
12
13
14
15
√
VREF
VREF
-
P79
P78
-
√
P74
P73
VREF
VREF
-
√
P71
P70
1
VREF
CS
P68
P67
√
P66
P65
VREF
-
√
DIN, D0
P64
P63
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Module 4 of 4
11
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
HQ240 High-Heat Quad Flat-Pack Packages
XCV600E and XCV1000E devices in High-heat dissipation
Quad Flat-pack packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
Other
Pair Bank P Pin
N Pin AO
Functions
48
49
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
P56
P52
P49
P46
P41
P38
P35
P33
P27
P23
P20
P17
P12
P9
P57
P53
P50
P47
P42
P39
P36
P34
P28
P24
P21
P18
P13
P10
P7
√
2
3
4
√
2
4
5
√
4
2
√
4
3
2
6
-
not used as V , it can be used as general I/O. Immedi-
REF
ately following Table 8, see Table 9 for Differential Pair infor-
mation.
-
50
VREF
Table 8: HQ240 — XCV600E, XCV1000E
51
VREF
Pin #
P240
P239
P238
P237
P236
P235
P234
P233
P232
P231
P230
P229
P228
P227
P226
P225
P224
P223
P222
P221
P220
P219
P218
P217
P216
P215
P214
P213
P212
P211
Pin Description
VCCO
Bank
7
52
-
53
-
TCK
NA
0
54
VREF
VREF
-
IO
55
IO_L0N
0
56
IO_VREF_L0P
IO_L1N_YY
IO_L1P_YY
GND
0
57
VREF
-
0
58
0
59
-
NA
0
VCCO
60
VREF
VREF
-
IO_VREF
IO_VREF
IO_VREF_L2N_YY
IO_L2P_YY
GND
0
61
0
62
P6
0
63
P4
P5
VREF
0
Notes:
1. AO in the XCV50E.
NA
0
2. AO in the XCV50E, 100E, 200E, 300E.
3. AO in the XCV50E, 200E, 300E, 400E.
4. AO in the XCV50E, 300E, 400E.
5. AO in the XCV100E, 200E, 400E.
6. AO in the XCV100E, 400E.
VCCO
VCCINT
NA
0
IO_L3N_YY
IO_L3P_YY
IO_VREF
IO_L4N_Y
IO_L4P_Y
GND
7. AO in the XCV50E, 200E, 400E.
8. AO in the XCV100E.
0
1
0
0
0
NA
0
IO_VREF_L5N_Y
IO_L5P_Y
IO_VREF
IO_LVDS_DLL_L6N
VCCINT
0
0
0
NA
0
GCK3
VCCO
0
GND
NA
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 8: HQ240 — XCV600E, XCV1000E
Table 8: HQ240 — XCV600E, XCV1000E
Pin #
P210
P209
P208
P207
P206
P205
P204
P203
P202
Pin Description
GCK2
Bank
1
Pin #
P174
P173
P172
P171
P170
P169
P168
P167
P166
P165
P164
P163
P162
Pin Description
IO_L16P_Y
IO_L16N_Y
GND
Bank
2
IO_LVDS_DLL_L6P
IO_VREF
1
2
1
NA
2
VCCO
1
IO_VREF_L17P_Y
IO_L17N_Y
IO_VREF
IO_L7N_Y
1
2
IO_VREF_L7P_Y
GND
1
2
NA
1
IO_VREF_L18P_Y
IO_D1_L18N_Y
GND
2
IO_L8N_Y
2
IO_L8P_Y
1
NA
2
1
P201
P200
P199
P198
P197
P196
P195
P194
P193
P192
P191
P190
P189
P188
P187
P186
P185
P184
P183
P182
P181
P180
P179
P178
P177
P176
P175
IO_VREF
1
VCCO
IO_L9N_YY
IO_L9P_YY
VCCINT
1
VCCINT
NA
2
1
IO_D2_L19P_YY
IO_L19N_YY
IO_VREF
NA
1
2
1
VCCO
P161
P160
P159
P158
P157
P156
P155
P154
P153
P152
P151
P150
P149
P148
P147
P146
P145
P144
P143
P142
P141
2
GND
NA
1
IO_L20P_Y
IO_L20N_Y
GND
2
IO_L10N_YY
IO_VREF_L10P_YY
IO_VREF
2
1
NA
2
1
IO_VREF_L21P_Y
IO_D3_L21N_Y
IO_L22P_Y
IO_VREF_L22N_Y
IO_L23P_YY
IO_L23N_YY
GND
IO_L11N_YY
IO_VREF_L11P_YY
GND
1
2
1
2
NA
1
2
IO_L12N_YY
IO_L12P_YY
IO_VREF_L13N
IO_L13P
2
1
2
1
NA
2
1
VCCO
IO_WRITE_L14N_YY
IO_CS_L14P_YY
TDI
1
IO
3
1
VCCINT
NA
3
NA
NA
2
IO_VREF
GND
VCCO
3
TDO
IO_D4_L24P_Y
IO_VREF_L24N_Y
GND
3
VCCO
1
3
CCLK
2
NA
3
IO_DOUT_BUSY_L15P_YY
IO_DIN_D0_L15N_YY
VCCO
2
IO_L25P_Y
IO_L25N_Y
IO_VREF
2
3
1
2
P140
P139
3
IO_VREF
2
IO_L26P_YY
3
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 8: HQ240 — XCV600E, XCV1000E
Table 8: HQ240 — XCV600E, XCV1000E
Pin #
P138
P137
P136
P135
P134
P133
P132
P131
P130
P129
P128
P127
P126
P125
P124
P123
P122
P121
P120
P119
P118
P117
P116
P115
P114
P113
P112
P111
P110
P109
P108
P107
P106
P105
P104
P103
Pin Description
IO_D5_L26N_YY
VCCINT
Bank
3
Pin #
Pin Description
IO_L36N_YY
IO_VREF
Bank
4
P102
1
NA
3
P101
P100
P99
P98
P97
P96
P95
P94
P93
P92
P91
P90
P89
P88
P87
P86
P85
P84
P83
P82
P81
4
VCCO
IO_L37P_Y
IO_L37N_Y
GND
4
GND
NA
3
4
IO_D6_L27P_Y
IO_VREF_L27N_Y
IO_VREF
NA
4
3
IO_VREF_L38P_Y
IO_L38N_Y
IO_L39P
3
4
IO_L28P_Y
IO_VREF_L28N_Y
GND
3
4
3
IO_VREF_L39N
IO_LVDS_DLL_L40P
GCK0
4
NA
3
4
IO_L29P_Y
IO_L29N_Y
IO_VREF_L30P_Y
IO_L30N_Y
IO_D7_L31P_YY
IO_INIT_L31N_YY
PROGRAM
VCCO
4
3
GND
NA
4
3
VCCO
3
GCK1
5
3
VCCINT
NA
5
3
IO_LVDS_DLL_L40N
IO_VREF
NA
3
5
VCCO
5
DONE
3
IO_VREF_L41P
GND
5
GND
NA
4
NA
5
IO_L32P_YY
IO_L32N_YY
VCCO
IO_L41N
4
IO
5
1
4
P80
IO_VREF
5
IO_VREF
4
P79
P78
P77
P76
P75
P74
P73
P72
P71
P70
P69
P68
P67
IO_L42P_YY
IO_L42N_YY
VCCINT
5
IO_L33P_YY
IO_L33N_YY
GND
4
5
4
NA
5
NA
4
VCCO
IO_VREF_L34P_YY
IO_L34N_YY
IO_VREF
GND
NA
5
4
IO_L43P_YY
IO_VREF_L43N_YY
IO_VREF
4
5
IO_VREF_L35P_YY
IO_L35N_YY
GND
4
5
4
IO_L44P_YY
IO_VREF_L44N_YY
GND
5
NA
4
5
VCCO
NA
5
VCCINT
NA
4
IO_L45P_YY
IO_L45N_YY
IO_L36P_YY
5
Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 8: HQ240 — XCV600E, XCV1000E
Table 8: HQ240 — XCV600E, XCV1000E
Pin #
P66
P65
P64
P63
P62
P61
P60
P59
P58
P57
P56
P55
P54
P53
P52
P51
P50
P49
P48
P47
P46
P45
P44
P43
P42
P41
Pin Description
IO_VREF_L46P
IO_L46N
Bank
5
Pin #
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
Pin Description
VCCO
Bank
6
5
GND
NA
7
IO_L47P_YY
IO_L47N_YY
M2
5
IO_L56N_YY
IO_L56P_YY
IO_VREF
5
7
NA
5
7
VCCO
VCCO
7
M0
NA
NA
NA
6
IO_L57N_Y
IO_VREF_L57P_Y
GND
7
GND
7
M1
NA
7
IO_L48N_YY
IO_L48P_YY
VCCO
IO_L58N_Y
IO_L58P_Y
IO_VREF
6
7
1
6
P19
7
IO_VREF
IO_L49N_Y
IO_L49P_Y
GND
6
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
IO_L59N_YY
IO_L59P_YY
VCCINT
7
6
7
6
NA
7
NA
6
VCCO
IO_VREF_L50N_Y
IO_L50P_Y
IO_VREF
IO_VREF_L51N_Y
IO_L51P_Y
GND
GND
NA
7
6
IO_L60N_Y
IO_VREF_L60P_Y
IO_VREF
6
7
6
7
6
IO_L61N_Y
IO_VREF_L61P_Y
GND
7
NA
6
7
VCCO
P8
NA
7
VCCINT
NA
6
P7
IO_L62N_Y
IO_L62P_Y
IO_VREF_L63N_Y
IO_L63P_Y
IO
IO_L52N_YY
IO_L52P_YY
IO_VREF
IO_L53N_Y
IO_L53P_Y
GND
P6
7
6
P5
7
1
P40
6
P4
7
P39
P38
P37
P36
P35
P34
P33
P32
P31
6
P3
7
6
P2
TMS
NA
NA
NA
6
P1
GND
Notes:
IO_VREF_L54N_Y
IO_L54P_Y
IO_L55N_Y
IO_VREF_L55P_Y
VCCINT
1. VREF or I/O option only in the XCV1000E; otherwise, I/O
6
option only.
6
6
NA
6
IO
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Module 4 of 4
15
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
HQ240 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
√
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
P174
P171
P168
P163
P160
P157
P155
P153
P145
P142
P139
P134
P131
P128
P126
P124
P118
P114
P111
P108
P103
P100
P97
P173
P170
P167
P162
P159
P156
P154
P152
P144
P141
P138
P133
P130
P127
P125
P123
P117
P113
P110
P107
P102
P99
-
√
VREF
√
D1
√
D2
√
-
√
D3
Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
1
VREF
√
-
P
N
Other
√
D4, VREF
Pair Bank
Pin
Pin
AO
Functions
√
-
Global Differential Clock
√
D5
0
1
2
3
4
5
1
0
P92
P89
P93
P87
NA
NA
NA
NA
IO _DLL_L40P
IO _DLL_L40N
IO _DLL_L6P
IO _DLL_L6N
√
VREF
√
VREF
P210
P213
P209
√
-
P215
1
VREF
IO LVDS
Total Pairs: 64, Asynchronous Output Pairs: 53
√
INIT
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
P236
P234
P228
P223
P220
P217
P209
P205
P202
P199
P194
P191
P188
P186
P184
P178
P237
P235
P229
P224
P221
P218
P215
P206
P203
P200
P195
P192
P189
P187
P185
P177
NA
√
VREF
√
-
-
√
-
2
√
VREF
√
VREF
3
√
-
√
VREF
4
√
-
√
-
5
√
VREF
√
-
6
NA
√
IO_LVDS_DLL
P96
√
VREF
7
VREF
-
P95
P94
NA
NA
NA
√
VREF
8
√
P93
P87
IO_LVDS_DLL
9
√
-
P84
P82
VREF
10
11
12
13
14
15
√
VREF
VREF
-
P79
P78
-
√
P74
P73
√
VREF
VREF
-
√
P71
P70
√
NA
√
VREF
CS
P68
P67
√
P66
P65
NA
√
VREF
-
√
DIN, D0
P64
P63
Module 4 of 4
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
BG352 Ball Grid Array Packages
XCV100E, XCV200E, and XCV300E devices in BG352 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
P
N
Other
Pair Bank
Pin
Pin
AO
√
√
√
√
√
√
√
1
√
√
√
√
√
√
√
1
Functions
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
P56
P52
P49
P46
P41
P38
P35
P33
P27
P23
P20
P17
P12
P9
P57
P53
P50
P47
P42
P39
P36
P34
P28
P24
P21
P18
P13
P10
P7
-
not used as V , it can be used as general I/O. Immedi-
REF
ately following Table 10, see Table 11 for Differential Pair
information.
-
VREF
Table 10: BG352 — XCV100E, XCV200E, XCV300E
VREF
Bank
0
Pin Description
Pin #
-
IO
D22
-
1
0
IO
IO
C23
VREF
VREF
-
1
0
B24
0
IO
C22
2
0
IO_VREF_0_L0N_YY
IO_L0P_YY
IO
D21
VREF
-
0
B23
1
0
A24
-
0
IO_L1N_YY
IO_L1P_YY
IO_VREF_0_L2N_YY
IO_L2P_YY
IO
A23
D20
C21
B22
VREF
VREF
-
0
0
P6
0
P4
P5
VREF
1
0
B21
Note 1: AO in the XCV600E.
1
0
IO
C20
0
IO_L3N
B20
A21
D18
C19
B19
D17
C18
0
IO_L3P
0
IO
0
IO_VREF_0_L4N_YY
IO_L4P_YY
IO_L5N_YY
IO_L5P_YY
IO
0
0
0
1
0
B18
0
IO_L6N
C17
A18
0
IO_L6P
1
0
IO
D16
0
IO_L7N_Y
IO_L7P_Y
IO_VREF_0_L8N_Y
IO_L8P_Y
B17
C16
A16
D15
0
0
0
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
0
0
0
0
IO
C15
1
1
1
1
1
IO
B4
1
1
IO
B15
IO
C5
1
IO_LVDS_DLL_L9N
GCK3
A15
D14
IO
A3
IO_WRITE_L20N_YY
IO_CS_L20P_YY
D5
C4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO_LVDS_DLL_L9P
IO
B14
A13
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_DOUT_BUSY_L21P_YY
E4
D3
1
B13
IO_DIN_D0_L21N_YY
1
IO_L10N
C13
A12
B12
C12
A11
B11
IO
IO
C2
1
IO_L10P
E3
IO_L11N_Y
IO_VREF_1_L11P_Y
IO_L12N_Y
IO_L12P_Y
IO
IO
F4
2
IO_VREF_2_L22P_YY
IO_L22N_YY
IO
D2
C1
1
D1
1
B10
IO_L23P_YY
IO_L23N_YY
IO_VREF_2_L24P_Y
IO_L24N_Y
IO
G4
F3
E2
F2
IO_L13N
C11
D11
IO_L13P
1
IO
A9
1
IO_L14N_YY
IO_L14P_YY
IO_L15N_YY
IO_VREF_1_L15P_YY
IO_L16N _Y
IO_L16P _Y
IO
B9
C10
B8
G3
1
IO
G2
IO_L25P
F1
J4
C9
D9
A7
IO_L25N
IO
H3
H2
G1
J3
IO_VREF_2_L26P _Y
IO_D1_L26N _Y
IO_D2_L27P_YY
IO_L27N_YY
IO
B7
1
IO
C8
1
IO
D8
J2
1
IO_L17N_YY
IO_VREF_1_L17P_YY
IO_L18N_YY
IO_L18P_YY
IO
A6
B6
C7
A4
K3
IO_L28P
J1
L4
IO_L28N
1
IO
K2
1
B5
IO_L29P_YY
IO_L29N_YY
IO_VREF_2_L30P _Y
L3
L2
IO_L19N_YY
IO_VREF_1_L19P_YY
C6
2
D6
M4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
Pin Description
IO_D3_L30N _Y
IO_L31P
Pin #
M3
Bank
Pin Description
Pin #
2
2
2
2
2
2
2
3
3
3
3
3
3
IO_VREF_3_L42N_YY
AC2
AB3
M2
IO
1
IO_L31N
M1
IO
AD1
1
1
IO
N3
IO
AB4
AC3
AD2
IO_L32P_YY
IO_L32N_YY
N4
N2
IO_D7_L43P_YY
IO_INIT_L43N_YY
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
P1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L44P_YY
AC5
AD4
1
P3
IO_L44N_YY
1
IO_L33P
R1
R2
R3
R4
T2
U2
IO
IO
AE3
AD5
1
IO_L33N
IO_D4_L34P _Y
IO_VREF_3_L34N _Y
IO_L35P_YY
IO_L35N_YY
IO
IO
AC6
2
IO_VREF_4_L45P_YY
IO_L45N_YY
IO
AE4
AF3
1
AF4
AC7
AD6
AE5
AE6
1
T3
IO_L46P_YY
IO_L46N_YY
IO_VREF_4_L47P_YY
IO_L47N_YY
IO
IO_L36P
T4
V1
IO_L36N
1
IO
V2
1
IO_L37P_YY
IO_D5_L37N_YY
IO_D6_L38P _Y
IO_VREF_3_L38N _Y
IO_L39P _Y
IO_L39N _Y
IO
U3
U4
V3
V4
Y1
Y2
W3
AD7
1
IO
AE7
AF6
AC9
AD8
AE8
AF7
AD9
AE9
AD10
AF9
IO_L48P
IO_L48N
IO
IO_VREF_4_L49P_YY
IO_L49N_YY
IO_L50P_YY
IO_L50N_YY
IO
1
IO
W4
1
IO
AA1
AA2
Y3
1
IO_L40P_Y
IO_VREF_3_L40N_Y
IO_L41P_YY
IO_L41N_YY
IO
IO_L51P
AC1
AB2
IO_L51N
AC11
1
IO
AE10
AD11
AE11
1
AA3
AA4
IO_L52P_Y
IO_L52N_Y
IO_L42P_YY
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
Pin Description
IO_VREF_4_L53P_Y
IO_L53N_Y
IO_L54P
Pin #
AC12
AD12
AE12
AF12
Bank
Pin Description
Pin #
4
4
4
4
4
4
4
5
5
5
5
5
IO_L64P_YY
AC21
2
IO_VREF_5_L64N_YY
AE23
AD22
IO
IO
IO
1
IO_L54N
AF24
AC22
1
1
IO
AD13
AC13
AE13
IO_LVDS_DLL_L55P
GCK0
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L65N_YY
IO_L65P_YY
IO
AC24
AD25
1
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO_LVDS_DLL_L55N
IO
AF14
AD14
AB24
AA23
1
IO
1
AF15
AE15
AD15
AC15
AE16
AE17
IO
AC25
2
IO
IO_VREF_6_L66N_YY
IO_L66P_YY
IO
AD26
IO_L56P_Y
IO_VREF_5_L56N_Y
IO_L57P_Y
IO_L57N_Y
IO
AC26
1
Y23
IO_L67N_YY
IO_L67P_YY
IO_VREF_6_L68N_Y
IO_L68P_Y
IO
AA24
AB25
AA25
Y24
1
AD16
AC16
AF18
IO_L58P
1
IO_L58N
Y25
1
1
IO
AE18
AD17
AC17
AD18
AC18
AF20
AE20
AD19
IO
AA26
V23
W24
W25
Y26
U23
V25
U24
IO_L59P_YY
IO_L59N_YY
IO_L60P_YY
IO_VREF_5_L60N_YY
IO_L61P _Y
IO_L61N _Y
IO
IO_L69N
IO_L69P
IO
IO_VREF_6_L70N _Y
IO_L70P _Y
IO_L71N_YY
IO_L71P_YY
IO
1
1
IO
AC19
V26
1
IO
AF21
AE21
AD20
AF23
AE22
IO_L72N
T23
U25
IO_L62P_YY
IO_VREF_5_L62N_YY
IO_L63P_YY
IO_L63N_YY
IO
IO_L72P
1
IO
T24
IO_L73N_YY
IO_L73P_YY
IO_VREF_6_L74N _Y
T25
T26
R24
1
AD21
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
Pin Description
IO_L74P _Y
IO_L75N
IO_L75P
IO
Pin #
R25
R26
P24
Bank
Pin Description
Pin #
2
6
6
6
6
6
7
7
7
7
7
IO_VREF_7_L86P_YY
E24
IO
IO
IO
IO
C26
1
E23
1
1
P23
D24
IO
N26
C25
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L76N_YY
IO_L76P_YY
IO
N25
N24
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
TDI
TDO
B3
D4
1
M26
CCLK
TCK
C3
IO_L77N
M25
M24
M23
L26
K25
L24
C24
IO_L77P
TMS
D23
IO_L78N _Y
IO_VREF_7_L78P _Y
IO_L79N_YY
IO_L79P_YY
IO
PROGRAM
DONE
DXN
AC4
AD3
AD23
AE24
AC23
AD24
AB23
DXP
1
L23
M2
IO_L80N
J26
J25
M0
IO_L80P
M1
1
IO
K24
IO_L81N_YY
IO_L81P_YY
IO_L82N _Y
IO_VREF_7_L82P _Y
IO_L83N _Y
IO_L83P _Y
IO
K23
H25
J23
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A20
B16
C14
D12
D10
K4
G26
G25
H24
H23
L1
1
IO
F26
P2
1
IO
F25
T1
IO_L84N_Y
IO_VREF_7_L84P_Y
IO_L85N_YY
IO_L85P_YY
IO
G24
D26
E25
F24
W2
AC10
AF11
AE14
AF16
AE19
1
F23
IO_L86N_YY
D25
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
NA
Pin Description
VCCINT
Pin #
V24
R23
P25
L25
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
A19
A14
A8
NA
VCCINT
NA
VCCINT
NA
VCCINT
A5
NA
VCCINT
J24
A2
A1
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
D19
B25
A17
D13
D7
B26
B1
E26
E1
H26
H1
A10
K1
N1
H4
P26
W26
W1
B2
Y4
U1
AB26
AB1
AE26
AE1
AF26
AF25
AF22
AF19
AF13
AF8
AF5
AF2
AF1
P4
AF10
AE2
AC8
AF17
AC20
AC14
AE25
W23
U26
N23
K26
G23
Notes:
1. No Connect in the XCV100E.
2. REF or I/O option only in the XCV200E and XCV300E;
otherwise, I/O option only.
V
NA
NA
NA
GND
GND
GND
A26
A25
A22
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
BG352 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
check (√) in the AO column indicates that the pin pair can be
used as an asynchronous output for all devices provided in
this package. Pairs with a note number in the AO column
are device dependent. They can have asynchronous out-
puts if the pin pair are in the same CLB row and column in
the device. Numbers in this column refer to footnotes that
indicate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates alter-
native function(s) not available when the pair is used as a
differential pair or differential clock
P
N
Pin
C6
Other
Pair
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Bank
1
1
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
Pin
D6
AO
√
√
√
√
√
√
2
√
√
1
√
√
2
√
2
√
√
1
√
√
1
√
√
√
√
√
√
√
√
2
√
√
2
√
√
2
Functions
VREF_1
C4
D5
CS
E4
D3
DIN_D0
D2
C1
VREF_2
G4
F3
-
E2
F2
VREF_2
F1
J4
-
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
H2
G1
D1
P
N
Other
J3
J2
D2
Pair
Bank
Pin
Pin
AO
Functions
J1
L4
-
Global Differential Clock
AE13 AC13 NA
AF14 AD14 NA
L3
L2
-
0
1
2
3
4
5
1
0
IO LVDS 55
IO LVDS 55
IO LVDS 9
IO LVDS 9
M4
M2
N4
M3
M1
N2
D3
-
B14
D14
A13
A15
NA
NA
-
R1
R2
-
IO LVDS
R3
R4
VREF_3
Total Outputs: 87, Asynchronous Output Pairs: 43
T2
U2
-
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
B23
D20
B22
A21
B19
C18
A18
C16
D15
A13
A12
C12
B11
D11
C10
C9
D21
A23
C21
B20
C19
D17
C17
B17
A16
A15
C13
B12
A11
C11
B9
√
√
√
2
√
√
2
√
√
√
2
√
√
2
√
√
1
√
√
VREF_0
T4
V1
-
-
U3
U4
D5
2
VREF_0
V3
V4
VREF_3
3
-
Y1
Y2
-
4
VREF_0
AA2
AC1
AA4
AC3
AC5
AE4
AC7
AE5
AF6
AE8
AD9
AF9
Y3
VREF_3
5
-
AB2
AC2
AD2
AD4
AF3
AD6
AE6
AC9
AF7
AE9
AC11
-
6
-
VREF_3
7
-
INIT
8
VREF_0
-
9
GCLK LVDS 3/2
VREF_4
10
11
12
13
14
15
16
17
18
-
-
VREF_1
VREF_4
-
-
-
VREF_4
-
-
B8
VREF_1
-
A7
D9
-
AD11 AE11
AC12 AD12
AE12 AF12
-
B6
A6
VREF_1
-
VREF_4
-
A4
C7
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Module 4 of 4
23
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
BG432 Ball Grid Array Packages
XCV300E, XCV400E, and XCV600E devices in BG432 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
P
N
Other
Pair
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Notes:
Bank
5
Pin
Pin
AO
√
√
√
2
√
√
1
√
√
√
√
√
√
√
2
√
√
1
√
√
2
√
2
√
√
1
√
√
1
√
√
√
Functions
AC13 AD14
AD15 AC15
AE16 AE17
AC16 AF18
AD17 AC17
AD18 AC18
AF20 AE20
AE21 AD20
AF23 AE22
AC21 AE23
AD25 AC24
AC26 AD26
AB25 AA24
GCLK LVDS 1/0
not used as V , it can be used as general I/O. Immedi-
REF
ately following Table 12, see Table 13 for Differential Pair
information.
5
VREF_5
5
-
Table 12: BG432 — XCV300E, XCV400E, XCV600E
5
-
Bank
0
Pin Description
GCK3
Pin #
D17
A22
A26
B20
C23
C28
B29
D27
B28
C27
D26
A28
B27
C26
D25
A27
D24
C25
B25
D23
5
-
5
VREF_5
0
IO
5
-
0
IO
5
VREF_5
0
IO
5
-
5
VREF_5
0
IO
6
-
0
IO
6
VREF_6
0
IO_L0N_Y
IO_L0P_Y
IO_L1N_YY
IO_L1P_YY
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_Y
IO_L6P_Y
IO_VREF_L7N_Y
IO_L7P_Y
IO_VREF_L8N_YY
IO_L8P_YY
IO_L9N_YY
IO_L9P_YY
IO_L10N_YY
IO_L10P_YY
IO_L11N_YY
IO_L11P_YY
6
-
0
6
Y24
W24
U23
U24
U25
T26
R25
P24
N24
M24
L26
L24
J25
AA25
V23
Y26
V25
T23
T25
R24
R26
N25
M25
M23
K25
J26
VREF_6
0
6
-
0
6
VREF_6
0
6
-
0
6
-
0
6
-
0
6
VREF_6
0
6
-
0
7
-
0
7
-
0
7
VREF_7
0
7
-
0
7
-
1
0
C24
7
H25
G26
H24
D26
F24
E24
K23
J23
-
0
B24
D22
A24
C22
B22
C21
D20
B21
C20
7
VREF_7
0
7
G25
G24
E25
D25
-
0
7
VREF_7
-
0
7
0
7
VREF_7
0
1. AO in the XCV100E.
2. AO in the XCV200E.
0
0
0
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
Pin Description
IO_L12N_YY
Pin #
A20
D19
B19
A19
B18
D18
Bank
Pin Description
IO_L26P_Y
Pin #
B8
C8
B7
D8
A6
B6
D7
A5
C6
B5
D6
A4
C5
B4
D5
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L12P_YY
IO_L27N_YY
IO_VREF_L13N_YY
IO_L13P_YY
IO_VREF_L27P_YY
IO_L28N_YY
IO_L14N_Y
IO_L28P_YY
IO_L14P_Y
IO_L29N_Y
2
IO_VREF_L15N_Y
IO_L15P_Y
C18
IO_L29P_Y
B17
C17
IO_L30N_YY
IO_LVDS_DLL_L16N
IO_VREF_L30P_YY
IO_L31N_YY
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO
A16
A12
B9
IO_L31P_YY
IO_L32N_Y
IO
IO_L32P_Y
IO
B11
C16
D9
IO_WRITE_L33N_YY
IO_CS_L33P_YY
IO
IO
IO_LVDS_DLL_L16P
IO_L17N_Y
IO_VREF_L17P_Y
IO_L18N_Y
IO_L18P_Y
IO_L19N_YY
IO_VREF_L19P_YY
IO_L20N_YY
IO_L20P_YY
IO_L21N_YY
IO_L21P_YY
IO_L22N_YY
IO_L22P_YY
IO_L23N_YY
IO_L23P_YY
IO_L24N_YY
IO_VREF_L24P_YY
IO_L25N_Y
IO_VREF_L25P_Y
IO_L26N_Y
B16
A15
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
H4
J3
2
B15
IO
L3
C15
D15
B14
A13
B13
D14
C13
B12
D13
C12
D12
C11
B10
C10
C9
IO
M1
R2
D3
C2
D2
E4
D1
E3
E2
F4
E1
F3
F2
G4
G3
G2
H3
IO
IO_DOUT_BUSY_L34P_YY
IO_DIN_D0_L34N_YY
IO_L35P
IO_L35N
IO_L36P_Y
IO_L36N_Y
IO_VREF_L37P_Y
IO_L37N_Y
IO_L38P
IO_L38N
IO_L39P_Y
IO_L39N_Y
IO_VREF_L40P_YY
IO_L40N_YY
IO_L41P_Y
1
D10
A8
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
2
Pin Description
IO_L41N_Y
Pin #
Bank
3
Pin Description
IO_L56N_Y
Pin #
Y3
H2
1
2
IO_VREF_L42P_Y
IO_L42N_Y
H1
3
IO_L57P_Y
Y4
2
J4
J2
3
IO_L57N_Y
Y2
2
IO_VREF_L43P_YY
IO_D1_L43N_YY
IO_D2_L44P_YY
IO_L44N_YY
IO_L45P_Y
3
IO_L58P_YY
IO_D5_L58N_YY
IO_D6_L59P_YY
IO_VREF_L59N_YY
IO_L60P_Y
AA3
AB1
AB3
AB4
AD1
2
K4
K2
K1
L2
3
2
3
2
3
2
3
1
2
IO_L45N_Y
M4
M3
M2
N4
N3
N1
P4
P3
P2
3
IO_VREF_L60N_Y
IO_L61P_Y
AC3
2
IO_L46P_Y
3
AC4
AD2
AD3
AD4
AF2
AE3
AE4
AG1
AG2
AF3
AF4
AH1
AH2
AG3
AG4
AJ2
T2
2
IO_L46N_Y
3
IO_L61N_Y
2
IO_L47P_Y
3
IO_L62P_YY
IO_VREF_L62N_YY
IO_L63P_Y
2
IO_L47N_Y
3
2
IO_VREF_L48P_YY
IO_D3_L48N_YY
IO_L49P_Y
3
2
3
IO_L63N_Y
2
3
IO_L64P
2
IO_L49N_Y
3
IO_L64N
2
2
IO_VREF_L50P_Y
IO_L50N_Y
R3
3
IO_L65P_Y
2
R4
R1
T3
3
IO_VREF_L65N_Y
IO_L66P_Y
2
IO_L51P_YY
IO_L51N_YY
3
2
3
IO_L66N_Y
3
IO_L67P
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
AA2
AC2
AE2
U3
3
IO_L67N
3
IO_D7_L68P_YY
IO_INIT_L68N_YY
IO
IO
3
IO
3
IO
W1
U4
IO_L52P_Y
IO_VREF_L52N_Y
IO_L53P_Y
IO_L53N_Y
IO_D4_L54P_YY
IO_VREF_L54N_YY
IO_L55P_Y
IO_L55N_Y
IO_L56P_Y
4
4
4
4
4
4
4
4
4
GCK0
AL16
AH10
AJ11
AK7
2
U2
IO
U1
V3
V4
V2
W3
W4
Y1
IO
IO
IO
AL12
AL15
AJ4
IO
IO_L69P_YY
IO_L69N_YY
IO_L70P_Y
AK3
AH5
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
4
Pin Description
IO_L70N_Y
Pin #
AK4
AJ5
AH6
AL4
AK5
AJ6
AH7
AL5
AK6
AJ7
AL6
AH9
AJ8
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO
Pin #
AJ23
AJ24
AL17
AK17
4
IO_L71P_YY
IO_L71N_YY
IO_VREF_L72P_YY
IO_L72N_YY
IO_L73P_Y
IO
4
IO_LVDS_DLL_L86N
IO_L87P_Y
4
2
4
IO_VREF_L87N_Y
IO_L88P_Y
AJ17
AH17
AK18
AL19
AJ18
AH18
AL20
AK20
AH19
AJ20
AK21
AJ21
AL22
AJ22
AK23
AH22
4
4
IO_L73N_Y
IO_L88N_Y
4
IO_L74P_YY
IO_L74N_YY
IO_VREF_L75P_YY
IO_L75N_YY
IO_L76P_Y
IO_L89P_YY
IO_VREF_L89N_YY
IO_L90P_YY
IO_L90N_YY
IO_L91P_YY
IO_L91N_YY
IO_L92P_YY
IO_L92N_YY
IO_L93P_YY
IO_L93N_YY
IO_L94P_YY
IO_VREF_L94N_YY
IO_L95P_Y
4
4
4
4
4
IO_L76N_Y
1
4
IO_VREF_L77P_Y
IO_L77N_Y
AK8
4
AJ9
AL8
4
IO_VREF_L78P_YY
IO_L78N_YY
IO_L79P_YY
IO_L79N_YY
IO_L80P_YY
IO_L80N_YY
IO_L81P_YY
IO_L81N_YY
IO_L82P_YY
IO_L82N_YY
IO_VREF_L83P_YY
IO_L83N_YY
IO_L84P_Y
4
AK9
4
AK10
AL10
AH12
AK11
AJ12
AK12
AH13
AJ13
AL13
AK14
AH14
AJ14
4
4
1
4
IO_VREF_L95N_Y
IO_L96P_Y
AL24
AK24
AH23
AK25
AJ25
AL26
AK26
AH25
AL27
AJ26
AK27
AH26
AL28
AJ27
AK28
4
4
IO_L96N_Y
4
IO_L97P_YY
IO_VREF_L97N_YY
IO_L98P_YY
IO_L98N_YY
IO_L99P_Y
4
4
4
4
4
IO_L84N_Y
IO_L99N_Y
2
4
IO_VREF_L85P_Y
IO_L85N_Y
AK15
AJ15
AH15
IO_L100P_YY
IO_VREF_L100N_YY
IO_L101P_YY
IO_L101N_YY
IO_L102P_Y
IO_L102N_Y
4
4
IO_LVDS_DLL_L86P
5
5
5
GCK1
IO
AK16
AH20
AJ19
IO
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO
Pin #
AA30
AC30
AD29
U31
Bank
Pin Description
IO_L118P_Y
IO_VREF_L119N_Y
IO_L119P_Y
IO
Pin #
6
6
6
6
U29
2
IO
U28
IO
U30
T30
IO
IO
W28
IO_L103N_YY
IO_L103P_YY
IO_L104N
AJ30
AH30
AG28
AH31
AG29
AG30
AF28
AG31
AF29
AF30
AE28
AF31
AE30
AD28
AD30
AD31
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
C30
H29
H31
L29
M31
R28
T31
R29
R30
IO
IO_L104P
IO
IO_L105N_Y
IO_L105P_Y
IO_VREF_L106N_Y
IO_L106P_Y
IO_L107N
IO
IO
IO_L120N_YY
IO_L120P_YY
IO_L121N_Y
IO_VREF_L121P_Y
IO_L122N_Y
IO_L122P_Y
IO_L123N_YY
IO_VREF_L123P_YY
IO_L124N_Y
IO_L124P_Y
IO_L125N_Y
IO_L125P_Y
IO_L126N_Y
IO_L126P_Y
IO_L127N_YY
IO_L127P_YY
IO_L128N_YY
IO_VREF_L128P_YY
IO_L129N_Y
IO_VREF_L129P_Y
IO_L130N_Y
IO_L130P_Y
IO_L131N_YY
IO_VREF_L131P_YY
IO_L132N_Y
2
IO_L107P
R31
IO_L108N_Y
IO_L108P_Y
IO_VREF_L109N_YY
IO_L109P_YY
IO_L110N_Y
IO_L110P_Y
IO_VREF_L111N_Y
IO_L111P_Y
IO_VREF_L112N_YY
IO_L112P_YY
IO_L113N_YY
IO_L113P_YY
IO_L114N_Y
IO_L114P_Y
IO_L115N_Y
IO_L115P_Y
IO_L116N_Y
IO_L116P_Y
IO_VREF_L117N_YY
IO_L117P_YY
IO_L118N_Y
P29
P28
P30
N30
N28
N31
M29
M28
M30
L30
K31
K30
K28
J30
1
AC28
AC29
AB28
AB29
AB31
AA29
Y28
Y29
Y30
J29
1
Y31
J28
W29
W30
V28
H30
G30
H28
F31
G29
V29
V30
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
Pin Description
IO_L132P_Y
IO_L133N
Pin #
G28
E31
E30
F29
F28
D31
D30
E29
E28
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
T1
7
7
7
7
7
7
7
7
7
T29
IO_L133P
W2
IO_L134N_Y
IO_VREF_L134P_Y
IO_L135N_Y
IO_L135P_Y
IO_L136N
W31
AB2
AB30
AE29
AF1
IO_L136P
AH8
AH24
AJ10
AJ16
AK22
AK13
AK19
2
CCLK
DONE
DXN
D4
AH4
AH27
AK29
AH28
AH29
AJ28
AH3
D28
B3
3
NA
NA
NA
NA
NA
NA
NA
NA
2
DXP
M0
M1
M2
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
A21
C29
D21
A1
PROGRAM
TCK
TDI
TDO
C4
A11
D11
C3
NA
TMS
D29
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A10
A17
B23
B26
C7
L4
L1
AA1
AA4
AJ3
C14
C19
F1
AH11
AL1
AL11
AH21
AL21
AJ29
AA28
AA31
F30
K3
K29
N2
N29
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
Pin Description
VCCO
Pin #
AL31
A31
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
Pin #
AH16
AJ1
6
7
7
7
VCCO
GND
VCCO
L28
GND
AJ31
AK1
VCCO
L31
GND
GND
AK2
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A2
A3
GND
AK30
AK31
AL2
GND
A7
GND
A9
GND
AL3
A14
A18
A23
A25
A29
A30
B1
GND
AL7
GND
AL9
GND
AL14
AL18
AL23
AL25
AL29
AL30
GND
GND
GND
GND
B2
GND
Notes:
B30
B31
C1
1. VREF or I/O option only in the XCV600E; otherwise, I/O
option only.
2. VREF or I/O option only in the XCV400E, XCV600E;
otherwise, I/O option only.
C31
D16
G1
G31
J1
J31
P1
P31
T4
T28
V1
V31
AC1
AC31
AE1
AE31
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
BG432 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also Vir-
tex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Pair Bank
P
N
AO
Other
Pin
Pin
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B16
B15
D15
A13
D14
B12
C12
C11
C10
D10
B8
C17
A15
C15
B14
B13
C13
D13
D12
B10
C9
NA
1
1
√
√
√
√
√
√
1
1
√
√
2
√
√
1
√
√
3
4
1
5
1
√
4
1
√
√
4
1
1
IO_LVDS_DLL
VREF
-
VREF
-
-
-
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
-
Pair Bank
P
N
AO
Other
VREF
Pin
Pin
Functions
VREF
Global Differential Clock
A8
-
0
1
2
3
4
5
1
0
AL16
AK16
A16
AH15
AL17
B16
NA
NA
NA
NA
IO_DLL_L86P
IO_DLL_L86N
IO_DLL_L16P
IO_DLL_L16N
B7
C8
VREF
A6
D8
-
D7
B6
-
D17
C17
C6
A5
VREF
IO LVDS
D6
B5
-
Total Outputs: 137, Asynchronous Output Pairs: 63
C5
A4
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D27
C27
A28
C26
A27
C25
D23
B24
A24
B22
D20
C20
D19
A19
D18
B17
B29
B28
D26
B27
D25
D24
B25
C24
D22
C22
C21
B21
A20
B19
B18
C18
1
√
√
2
√
√
1
1
√
√
√
√
√
√
1
1
-
D5
B4
CS, WRITE
-
D3
C2
DIN, D0, BUSY
2
VREF
D2
E4
-
3
-
D1
E3
-
4
-
E2
F4
VREF
5
VREF
E1
F3
-
6
-
F2
G4
G2
H2
-
7
VREF
G3
H3
VREF
8
VREF
-
9
-
H1
J4
VREF
10
11
12
13
14
15
-
J2
K4
D1
-
K2
K1
D2
-
L2
M4
M2
N3
-
-
-
VREF
-
M3
N4
VREF
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Module 4 of 4
31
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 13: BG432 Differential Pin Pair Summary
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
XCV300E, XCV400E, XC600E
Pair Bank
P
N
AO
Other
Pair Bank
P
N
AO
Other
Pin
Pin
Functions
Pin
Pin
Functions
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
N1
P3
P4
P2
√
4
1
√
1
4
√
1
1
4
√
√
1
4
√
1
5
1
4
3
√
√
1
√
√
2
√
√
1
1
√
√
D3
80
81
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
AH12
AJ12
AH13
AL13
AH14
AK15
AH15
AK17
AH17
AL19
AH18
AK20
AJ20
AJ21
AJ22
AH22
AK24
AK25
AL26
AH25
AJ26
AH26
AJ27
AH30
AH31
AG30
AG31
AF30
AF31
AD28
AD31
AC29
AK11
AK12
AJ13
AK14
AJ14
AJ15
AL17
AJ17
AK18
AJ18
AL20
AH19
AK21
AL22
AK23
AL24
AH23
AJ25
AK26
AL27
AK27
AL28
AK28
AJ30
AG28
AG29
AF28
AF29
AE28
AE30
AD30
AC28
√
√
√
√
1
1
NA
1
1
√
√
√
√
√
√
1
1
√
√
2
√
√
1
√
3
4
1
5
1
√
4
1
-
-
-
R3
R4
VREF
82
-
R1
T3
-
83
VREF
U4
U2
VREF
84
-
U1
V3
-
85
VREF
V4
V2
VREF
86
IO_LVDS_DLL
W3
W4
-
87
VREF
Y1
Y3
-
88
-
Y4
Y2
-
89
VREF
AA3
AB3
AD1
AC4
AD3
AF2
AE4
AG2
AF4
AH2
AG4
AJ4
AH5
AJ5
AL4
AJ6
AL5
AJ7
AH9
AK8
AL8
AK10
AB1
AB4
AC3
AD2
AD4
AE3
AG1
AF3
AH1
AG3
AJ2
AK3
AK4
AH6
AK5
AH7
AK6
AL6
AJ8
AJ9
AK9
AL10
D5
90
-
VREF
91
-
VREF
92
-
-
93
-
VREF
94
VREF
-
95
VREF
-
96
-
VREF
97
VREF
-
98
-
-
99
-
INIT
100
101
102
103
104
105
106
107
108
109
110
111
VREF
-
-
-
-
-
-
VREF
-
-
-
-
VREF
VREF
-
-
-
VREF
VREF
-
VREF
-
VREF
Module 4 of 4
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
BG560 Ball Grid Array Packages
XCV1000E, XCV1600E, and XCV2000E devices in BG560
Ball Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
Pair Bank
P
N
AO
Other
Pin
Pin
Functions
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
Notes:
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
AB29
AA29
Y29
Y31
W30
V29
U29
U30
R29
R31
P28
N30
N31
M28
L30
AB28
AB31
Y28
Y30
W29
V28
V30
U28
T31
R30
P29
P30
N28
M29
M30
K31
K28
J29
√
√
4
1
1
√
4
1
√
1
4
√
1
1
4
√
√
1
4
√
1
5
1
4
3
VREF
not used as V , it can be used as general I/O. Immedi-
REF
ately following Table 14, see Table 15 for Differential Pair
information.
-
-
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
-
-
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
GCK3
Pin#
A17
A27
B25
C28
C30
D30
E28
D29
D28
A31
E27
C29
B30
D27
E26
B29
D26
C27
E25
A28
D25
C26
E24
B26
C25
D24
E23
A25
D23
See Note
VREF
IO
-
IO
VREF
IO
-
IO
VREF
IO
-
IO_L0N
VREF
IO_VREF_L0P
IO_L1N_YY
IO_L1P_YY
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_Y
IO_VREF_L6P_Y
IO_L7N_Y
IO_L7P_Y
IO_VREF_L8N_Y
IO_L8P_Y
IO_L9N_Y
IO_L9P_Y
IO_VREF_L10N_YY
IO_L10P_YY
IO_L11N_YY
3
-
-
-
K30
J30
-
VREF
J28
VREF
G30
F31
G28
E30
F28
D30
E28
H30
H28
G29
E31
F29
D31
E29
-
VREF
-
-
VREF
-
-
1
4
1. AO in the XCV300E, 600E.
2. AO in the XCV300E.
3. AO in the XCV400E, 600E.
4. AO in the XCV300E, 400E.
5. AO in the XCV600E.
DS022-4 (v2.5) March 14, 2003
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
33
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
0
Pin Description
IO_L11P_YY
IO_L12N_Y
Pin#
B24
E22
C23
A23
D22
E21
B22
D21
C21
B21
E20
D20
C20
B20
E19
D19
C19
A19
D18
C18
E18
See Note
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L25P_Y
Pin#
C15
D15
E15
C14
D14
A13
E14
C13
D13
C12
E13
A11
D12
B11
C11
B10
D11
C10
A9
See Note
0
IO_L26N_YY
IO_VREF_L26P_YY
IO_L27N_YY
IO_L27P_YY
IO_L28N_Y
0
IO_L12P_Y
0
IO_L13N_YY
IO_L13P_YY
IO_VREF_L14N_YY
IO_L14P_YY
IO_L15N_Y
0
0
3
0
IO_L28P_Y
0
IO_L29N_YY
IO_VREF_L29P_YY
IO_L30N_YY
IO_L30P_YY
IO_L31N_Y
0
IO_L15P_Y
3
0
IO_L16N_YY
IO_L16P_YY
IO_VREF_L17N_YY
IO_L17P_YY
IO_L18N_Y
0
0
0
IO_L31P_Y
0
IO_L32N_YY
IO_L32P_YY
IO_L33N_YY
IO_VREF_L33P_YY
IO_L34N_Y
0
IO_L18P_Y
0
IO_L19N_Y
0
IO_L19P_Y
0
IO_VREF_L20N_Y
IO_L20P_Y
0
IO_L34P_Y
0
IO_LVDS_DLL_L21N
IO_VREF
IO_L35N_Y
C9
0
2
IO_VREF_L35P_Y
IO_L36N_Y
D10
A8
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO
D17
A3
IO_L36P_Y
B8
IO_L37N_Y
E10
C8
IO
D9
IO_VREF_L37P_Y
IO_L38N_YY
IO_VREF_L38P_YY
IO_L39N_YY
IO_L39P_YY
IO_L40N_Y
IO
E8
B7
IO
E11
E17
C17
B17
B16
D16
E16
C16
A15
A6
IO_LVDS_DLL_L21P
IO_VREF_L22N_Y
IO_L22P_Y
IO_L23N_Y
IO_VREF_L23P_Y
IO_L24N_Y
IO_L24P_Y
IO_L25N_Y
C7
2
D8
A5
IO_L40P_Y
B5
IO_L41N_YY
IO_VREF_L41P_YY
IO_L42N_YY
IO_L42P_YY
C6
D7
A4
B4
Module 4 of 4
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
Pin Description
IO_L43N_Y
Pin#
C5
E7
See Note
Bank
2
Pin Description
IO_L58P_Y
Pin#
M5
L3
See Note
1
1
1
1
IO_VREF_L43P_Y
IO_WRITE_L44N_YY
IO_CS_L44P_YY
3
2
IO_L58N_Y
D6
A2
2
IO_L59P_Y
L1
2
IO_L59N_Y
M4
N5
M2
N4
N3
N2
P5
P4
P3
P2
R5
R4
R3
R1
T4
T5
T3
T2
U3
2
IO_VREF_L60P_Y
IO_L60N_Y
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
D3
F3
G1
J2
2
2
IO_L61P_Y
IO
2
IO_L61N_Y
IO
2
IO_L62P_Y
IO_DOUT_BUSY_L45P_YY
IO_DIN_D0_L45N_YY
IO_L46P_Y
D4
E4
F5
B3
F4
C1
G5
E3
D2
G4
H5
E2
H4
G3
J5
2
IO_L62N_Y
2
IO_VREF_L63P_YY
IO_D3_L63N_YY
IO_L64P_Y
2
IO_VREF_L46N_Y
IO_L47P_Y
3
2
2
IO_L64N_Y
IO_L47N_Y
2
IO_L65P_Y
IO_VREF_L48P_Y
IO_L48N_Y
2
IO_L65N_Y
2
IO_VREF_L66P_Y
IO_L66N_Y
IO_L49P_Y
2
IO_L49N_Y
2
IO_L67P_Y
IO_L50P_Y
2
IO_VREF_L67N_Y
IO_L68P_YY
IO_L68N_YY
2
IO_L50N_Y
2
IO_VREF_L51P_YY
IO_L51N_YY
IO_L52P_Y
2
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
AE3
AF3
AH3
AK3
U1
IO_VREF_L52N_Y
IO_L53P_Y
F1
J4
1
4
IO
IO_L53N_Y
H3
K5
H2
J3
IO
IO_VREF_L54P_Y
IO_L54N_Y
IO_VREF_L69P_Y
IO_L69N_Y
IO_L70P_Y
IO_VREF_L70N_Y
IO_L71P_Y
IO_L71N_Y
IO_L72P_Y
IO_L72N_Y
2
U2
IO_L55P_Y
V2
IO_L55N_Y
K4
L5
K3
L4
K2
V4
IO_VREF_L56P_YY
IO_D1_L56N_YY
IO_D2_L57P_YY
IO_L57N_YY
V5
V3
W1
W3
DS022-4 (v2.5) March 14, 2003
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
35
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_D4_L73P_YY
IO_VREF_L73N_YY
IO_L74P_Y
Pin#
W4
See Note
Bank
Pin Description
IO_VREF_L90N_Y
IO_D7_L91P_YY
IO_INIT_L91N_YY
IO
Pin#
AH4
AJ4
AH5
U4
See Note
3
3
3
3
3
W5
Y3
IO_L74N_Y
Y4
IO_L75P_Y
AA1
Y5
IO_L75N_Y
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
IO
AL17
AJ8
IO_L76P_Y
AA3
AA4
AB3
AA5
AC1
AB4
AC3
AB5
AC4
AD3
AE1
AC5
AD4
AF1
AF2
AD5
AG2
AE4
AH1
AE5
AF4
AJ1
AJ2
AF5
AG4
AK2
AJ3
AG5
AL1
IO_VREF_L76N_Y
IO_L77P_Y
3
IO
AJ11
AK6
AK9
AL4
IO
IO_L77N_Y
IO
IO_L78P_Y
IO_L92P_YY
IO_L92N_YY
IO_L93P_Y
IO_L78N_Y
AJ6
IO_L79P_YY
IO_D5_L79N_YY
IO_D6_L80P_YY
IO_VREF_L80N_YY
IO_L81P_Y
AK5
AN3
AL5
IO_VREF_L93N_Y
IO_L94P_YY
IO_L94N_YY
IO_VREF_L95P_YY
IO_L95N_YY
IO_L96P_Y
3
AJ7
AM4
AM5
AK7
AL6
IO_L81N_Y
IO_L82P_Y
IO_VREF_L82N_Y
IO_L83P_Y
4
1
IO_L96N_Y
IO_L97P_YY
IO_L97N_YY
IO_VREF_L98P_YY
IO_L98N_YY
IO_L99P_Y
AM6
AN6
AL7
IO_L83N_Y
IO_L84P_Y
IO_VREF_L84N_Y
IO_L85P_YY
IO_VREF_L85N_YY
IO_L86P_Y
AJ9
AN7
AL8
IO_VREF_L99N_Y
IO_L100P_Y
IO_L100N_Y
IO_VREF_L101P_Y
IO_L101N_Y
IO_L102P_Y
IO_L102N_Y
IO_VREF_L103P_YY
IO_L103N_YY
IO_L104P_YY
1
4
AM8
AJ10
AL9
IO_L86N_Y
IO_L87P_Y
IO_L87N_Y
AM9
AK10
AN9
AL10
AM10
AL11
IO_L88P_Y
IO_VREF_L88N_Y
IO_L89P_Y
IO_L89N_Y
IO_L90P_Y
Module 4 of 4
36
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
4
Pin Description
IO_L104N_YY
IO_L105P_Y
Pin#
AJ12
AN11
AK12
AL12
AM12
AK13
AL13
AM13
AN13
AJ14
AK14
AM14
AN15
AJ15
AK15
AL15
AM16
AL16
AJ16
AK16
AN17
AM17
See Note
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L118N_Y
Pin#
AM20
AJ19
AL20
AN21
AL21
AJ20
AM22
AK21
AN23
AJ21
AM23
AK22
AM24
AL23
AJ22
AK23
AL24
AN26
AJ23
AK24
AM26
AM27
AJ24
AL26
AK25
AN29
AJ25
AK26
AM29
AM30
AJ26
AK27
AL29
AN31
AJ27
See Note
4
IO_L119P_YY
IO_VREF_L119N_YY
IO_L120P_YY
IO_L120N_YY
IO_L121P_Y
4
IO_L105N_Y
4
IO_L106P_YY
IO_L106N_YY
IO_VREF_L107P_YY
IO_L107N_YY
IO_L108P_Y
4
4
3
4
IO_L121N_Y
4
IO_L122P_YY
IO_VREF_L122N_YY
IO_L123P_YY
IO_L123N_YY
IO_L124P_Y
4
IO_L108N_Y
3
4
IO_L109P_YY
IO_L109N_YY
IO_VREF_L110P_YY
IO_L110N_YY
IO_L111P_Y
4
4
4
IO_L124N_Y
4
IO_L125P_YY
IO_L125N_YY
IO_L126P_YY
IO_VREF_L126N_YY
IO_L127P_Y
4
IO_L111N_Y
4
IO_L112P_Y
4
IO_L112N_Y
4
IO_VREF_L113P_Y
IO_L113N_Y
4
IO_L127N_Y
4
IO_L114P_Y
IO_L128P_Y
4
IO_VREF_L114N_Y
IO_LVDS_DLL_L115P
2
IO_VREF_L128N_Y
IO_L129P_Y
4
1
4
IO_L129N_Y
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO
AJ17
AL25
AL28
AL30
AN28
AM18
AL18
AK18
AJ18
AN19
AL19
AK19
IO_L130P_Y
IO_VREF_L130N_Y
IO_L131P_YY
IO_VREF_L131N_YY
IO_L132P_YY
IO_L132N_YY
IO_L133P_Y
IO
IO
IO
IO_LVDS_DLL_L115N
IO_VREF
2
IO_L116P_Y
IO_VREF_L116N_Y
IO_L117P_Y
IO_L117N_Y
IO_L118P_Y
IO_L133N_Y
IO_L134P_YY
IO_VREF_L134N_YY
IO_L135P_YY
IO_L135N_YY
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
37
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
Pin Description
IO_L136P_Y
Pin#
AM31
AK28
See Note
Bank
6
Pin Description
IO_L151N_Y
IO_L151P_Y
Pin#
AB31
AA29
AA30
AA31
AA32
Y29
See Note
5
5
IO_VREF_L136N_Y
3
6
6
IO_VREF_L152N_Y
IO_L152P_Y
3
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
AE33
AF31
AJ32
AL33
AH29
AJ30
AK31
AH30
AG29
AJ31
AK32
AG30
AH31
AF29
AH32
AF30
AE29
AH33
AG33
AE30
AD29
AF32
AE31
AD30
AE32
AC29
AD31
AC30
AB29
AC31
AC33
AB30
6
IO
6
IO_L153N_Y
IO_L153P_Y
IO
6
IO
6
IO_L154N_Y
IO_L154P_Y
AA33
Y30
IO_L137N_YY
IO_L137P_YY
IO_L138N_Y
IO_VREF_L138P_Y
IO_L139N_Y
IO_L139P_Y
IO_VREF_L140N_Y
IO_L140P_Y
IO_L141N_Y
IO_L141P_Y
IO_L142N_Y
IO_L142P_Y
IO_VREF_L143N_YY
IO_L143P_YY
IO_L144N_Y
IO_VREF_L144P_Y
IO_L145N_Y
IO_L145P_Y
IO_VREF_L146N_Y
IO_L146P_Y
IO_L147N_Y
IO_L147P_Y
IO_VREF_L148N_YY
IO_L148P_YY
IO_L149N_YY
IO_L149P_YY
IO_L150N_Y
IO_L150P_Y
6
6
IO_VREF_L155N_YY
IO_L155P_YY
IO_L156N_Y
IO_L156P_Y
Y32
6
W29
W30
W31
W33
V30
3
6
6
6
IO_L157N_Y
IO_L157P_Y
6
6
IO_VREF_L158N_Y
IO_L158P_Y
V29
6
V31
6
IO_L159N_Y
IO_VREF_L159P_Y
IO
V32
6
U33
2
6
U29
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
E30
F29
F33
G30
K30
U31
U32
T32
T30
T29
T31
R33
R31
R30
R29
1
4
IO
IO
IO
IO_L160N_YY
IO_L160P_YY
IO_VREF_L161N_Y
IO_L161P_Y
IO_L162N_Y
IO_VREF_L162P_Y
IO_L163N_Y
IO_L163P_Y
IO_L164N_Y
IO_L164P_Y
2
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L165N_YY
IO_VREF_L165P_YY
IO_L166N_Y
Pin#
P32
P31
P30
P29
M32
N31
N30
L33
M31
L32
M30
L31
M29
J33
See Note
Bank
Pin Description
Pin#
See Note
7
IO_VREF_L182P_Y
D31
3
2
CCLK
DONE
DXN
C4
AJ5
IO_L166P_Y
3
IO_L167N_Y
NA
NA
NA
NA
NA
NA
NA
NA
2
AK29
AJ28
AJ29
AK30
AN32
AM1
E29
IO_L167P_Y
DXP
IO_L168N_Y
M0
IO_VREF_L168P_Y
IO_L169N_Y
3
M1
M2
IO_L169P_Y
PROGRAM
TCK
IO_L170N_Y
IO_L170P_Y
TDI
D5
IO_L171N_YY
IO_L171P_YY
IO_L172N_YY
IO_VREF_L172P_YY
IO_L173N_Y
TDO
E6
NA
TMS
B33
L30
K31
L29
H33
J31
NA
NA
NA
NA
NC
NC
NC
NC
C31
AC2
AK4
AL3
IO_L173P_Y
IO_L174N_Y
IO_VREF_L174P_Y
IO_L175N_Y
H32
K29
H31
J30
4
1
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A21
B12
B14
B18
B28
C22
C24
E9
IO_L175P_Y
IO_L176N_Y
IO_VREF_L176P_Y
IO_L177N_YY
IO_VREF_L177P_YY
IO_L178N_Y
G32
J29
G31
E33
E32
H29
F31
D32
E31
G29
C33
F30
IO_L178P_Y
IO_L179N_Y
E12
F2
IO_L179P_Y
IO_L180N_Y
H30
J1
IO_VREF_L180P_Y
IO_L181N_Y
K32
M3
IO_L181P_Y
IO_L182N_Y
N1
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
39
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin#
N29
See Note
Bank
2
Pin Description
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
Pin#
M1
See Note
N33
2
R2
U5
3
V1
U30
3
AA2
AD1
AK1
AL2
Y2
3
Y31
3
AB2
3
AB32
AD2
AD32
AG3
AG31
AJ13
AK8
4
AN4
AN8
AN12
AM2
AM15
AL31
AM21
AN18
AN24
AN30
W32
AB33
AF33
AK33
AM32
C32
4
4
4
4
5
5
AK11
AK17
AK20
AL14
AL22
AL27
AN25
5
5
5
6
6
6
6
6
0
0
0
0
0
1
1
1
1
1
2
2
2
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
A22
A26
A30
B19
B32
A10
A16
B13
C3
7
7
D33
7
K33
7
N32
7
T33
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
A1
A7
A12
A14
A18
A20
A24
E5
B2
D1
H1
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin#
A29
A32
A33
B1
See Note
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Notes:
Pin Description
GND
Pin#
AL32
AM3
See Note
GND
GND
AM7
GND
AM11
AM19
AM25
AM28
AM33
AN1
B6
GND
B9
GND
B15
B23
B27
B31
C2
GND
GND
GND
GND
AN2
GND
AN5
E1
GND
AN10
AN14
AN16
AN20
AN22
AN27
AN33
F32
G2
GND
GND
G33
J32
K1
GND
GND
GND
L2
GND
M33
P1
1. VREF or I/O option only in the XCV2000E; otherwise, I/O
option only.
2. VREF or I/O option only in the XCV1600E & 2000E;
otherwise, I/O option only.
P33
R32
T1
3. VREF or I/O option only in the XCV1000E, 1600E, & 2000E;
otherwise, I/O option only.
4. VREF or I/O option only in the XCV600E, 1000E, 1600E, &
2000E; otherwise, I/O option only.
V33
W2
Y1
Y33
AB1
AC32
AD33
AE2
AG1
AG32
AH2
AJ33
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
41
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
BG560 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
√
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
E20
C20
E19
C19
D18
E17
B17
D16
C16
C15
E15
D14
E14
D13
E13
D12
C11
D11
A9
B21
D20
B20
D19
A19
C18
C17
B16
E16
A15
D15
C14
A13
C13
C12
A11
B11
B10
C10
C9
-
√
VREF
9
-
-
7
7
VREF
NA IO_LVDS_DLL
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
2
7
VREF
P
N
Other
VREF
Pair Bank
Pin
Pin
AO
Functions
7
-
Global Differential Clock
9
-
0
1
2
3
4
5
1
0
AL17
AJ17
D17
AM17
AM18
E17
NA
NA
NA
NA
IO_DLL_L15P
IO_DLL_L15N
IO_DLL_L21P
IO_DLL_L21N
√
VREF
√
-
3
-
A17
C18
√
VREF
IO LVDS
√
-
Total Outputs: 183, Asynchronous Outputs: 87
8
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D29
A31
C29
D27
B29
C27
A28
C26
B26
D24
A25
B24
C23
D22
B22
C21
E28
D28
E27
B30
E26
D26
E25
D25
E24
C25
E23
D23
E22
A23
E21
D21
8
√
√
3
√
√
9
7
7
2
√
√
8
√
√
3
VREF
√
-
VREF
-
-
√
2
VREF
10
7
3
-
D10
B8
VREF
-
4
-
A8
7
5
VREF
C8
E10
B7
5
VREF
VREF
-
6
VREF
A6
√
7
-
D8
C7
√
8
VREF
B5
A5
11
√
-
9
-
D7
C6
VREF
-
10
11
12
13
14
15
VREF
B4
A4
√
-
E7
C5
12
√
VREF
CS
-
A2
D6
-
VREF
-
D4
E4
√
DIN, D0
VREF
F5
B3
17
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 15: BG560 Differential Pin Pair Summary
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
14
15
16
15
√
Functions
Pair Bank
Pin
Pin
AO
17
√
Functions
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
F4
G5
D2
H5
H4
J5
C1
E3
G4
E2
G3
F1
-
78
79
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
AC1
AC3
AC4
AE1
AD4
AF2
AG2
AH1
AF4
AJ2
AB4
AB5
AD3
AC5
AF1
AD5
AE4
AE5
AJ1
-
VREF
D5
-
80
√
VREF
-
81
4
-
VREF
82
18
14
20
√
VREF
17
14
18
19
√
VREF
83
-
J4
H3
H2
K4
K3
K2
L3
-
84
VREF
K5
J3
VREF
85
VREF
-
86
15
14
15
14
14
√
-
L5
D1
87
AF5
AK2
AG5
AH4
AH5
AJ6
-
L4
√
D2
88
AG4
AJ3
VREF
M5
L1
17
14
15
16
15
√
-
89
-
M4
M2
N3
P5
P3
R5
R3
T4
-
90
AL1
VREF
N5
N4
N2
P4
P2
R4
R1
T5
VREF
91
AJ4
INIT
-
92
AL4
√
-
-
93
AK5
AL5
AN3
AJ7
8
VREF
D3
94
√
-
17
14
18
19
√
-
95
AM4
AK7
AM6
AL7
AM5
AL6
√
VREF
-
96
3
-
VREF
97
AN6
AJ9
√
-
T3
VREF
98
√
VREF
T2
U3
U2
V4
V3
W3
W5
Y4
Y5
AA4
AA5
-
99
AN7
AM8
AL9
AL8
9
VREF
U1
V2
V5
W1
W4
Y3
AA1
AA3
AB3
19
18
14
17
√
VREF
100
101
102
103
104
105
106
107
108
AJ10
AM9
AN9
AM10
AJ12
AK12
AM12
AL13
7
-
VREF
7
VREF
-
AK10
AL10
AL11
AN11
AL12
AK13
2
-
-
√
VREF
VREF
√
-
15
16
15
14
-
8
-
-
VREF
-
√
-
VREF
-
√
AM13 AN13
3
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
43
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
√
Functions
Pair Bank
Pin
Pin
AO
15
16
15
√
Functions
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
AJ14
AM14
AJ15
AL15
AL16
AK16
AK14
AN15
AK15
AM16
AJ16
AN17
-
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
AG30
AF29
AF30
AH33
AE30
AF32
AD30
AC29
AC30
AC31
AB30
AA29
AA31
Y29
AK32
AH31
AH32
AE29
AG33
AD29
AE31
AE32
AD31
AB29
AC33
AB31
AA30
AA32
AA33
Y32
VREF
√
VREF
-
-
1
-
7
-
VREF
7
VREF
VREF
17
14
18
19
√
VREF
2
-
AM17 AM18
NA IO_LVDS_DLL
VREF
AK18
AN19
AK19
AJ19
AN21
AJ20
AK21
AJ21
AK22
AL23
AK23
AN26
AK24
AM27
AL26
AN29
AK26
AM30
AK27
AN31
AM31
AJ30
AH30
AJ31
AJ18
AL19
AM20
AL20
AL21
AM22
AN23
AM23
AM24
AJ22
AL24
AJ23
AM26
AJ24
AK25
AJ25
AM29
AJ26
AL29
AJ27
AK28
AH29
AK31
AG29
7
7
VREF
-
-
VREF
9
-
√
-
√
VREF
17
14
15
16
15
√
-
√
-
-
3
-
VREF
√
VREF
-
√
-
Y30
-
8
-
W29
W31
V30
VREF
√
-
W30
W33
V29
17
14
18
19
√
-
√
VREF
-
13
7
-
V31
VREF
VREF
U33
V32
VREF
7
-
U32
U31
-
5
VREF
T30
T32
19
18
14
17
√
VREF
√
VREF
T31
T29
VREF
√
-
R31
R33
-
11
√
-
R29
R30
-
VREF
P31
P32
VREF
√
-
P29
P30
15
16
15
14
17
-
12
√
VREF
N31
M32
-
-
VREF
-
L33
N30
VREF
17
14
L32
M31
-
-
L31
M30
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
FG256 Fine-Pitch Ball Grid Array Packages
XCV50E, XCV100E, XCV200E, and XCV300E devices in
FG256 fine-pitch Ball Grid Array packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
P
N
Other
Pair Bank
Pin
Pin
AO
√
Functions
171
172
173
174
175
176
177
178
179
180
181
182
Notes:
7
7
7
7
7
7
7
7
7
7
7
7
J33
K31
H33
H32
H31
G32
G31
E32
F31
E31
C33
D31
M29
L30
L29
J31
K29
J30
J29
E33
H29
D32
G29
F30
-
notes. If the pin is not used as V , it can be used as gen-
REF
eral I/O. Immediately following Table 16, see Table 17 for
Differential Pair information.
√
VREF
4
-
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
18
14
20
√
VREF
Bank
0
Pin Description
GCK3
Pin #
B8
-
VREF
0
IO
B3
VREF
0
IO
E7
15
14
15
14
14
-
0
IO
D8
-
0
IO_L0N_Y
C5
VREF
-
2
0
IO_VREF_L0P_Y
IO_L1N_YY
IO_L1P_YY
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N_Y
A3
0
D5
E6
B4
A4
D6
B5
VREF
0
0
1. AO in the XCV1600E.
2. AO in the XCV2000E.
0
3. AO in the XCV1600E, 2000E.
4. AO in the XCV1000E, 1600E.
5. AO in the XCV1000E, 2000E.
6. AO in the XCV1000E.
0
0
IO_L3P_Y
1
0
IO_VREF_L4N_YY
IO_L4P_YY
IO_L5N_YY
IO_L5P_YY
IO_L6N_Y
C6
7. AO in the XCV1000E, 1600E, 2000E.
8. AO in the XCV600E, 1600E.
0
A5
B6
C7
D7
C8
B7
A6
A7
0
9. AO in the XCV400E, 600E, 1600E.
10. AO in the XCV400E, 600E, 1000E, 2000E.
11. AO in the XCV400E, 600E, 1000E.
12. AO in the XCV400E, 1000E, 2000E.
13. AO in the XCV400E, 600E, 1000E, 1600E.
14. AO in the XCV400E, 1000E, 1600E.
15. AO in the XCV600E, 1000E, 2000E.
16. AO in the XCV600E, 2000E.
0
0
0
IO_L6P_Y
0
IO_VREF_L7N_Y
IO_L7P_Y
0
0
IO_LVDS_DLL_L8N
17. AO in the XCV400E, 600E, 1600E, 2000E.
18. AO in the XCV600E, 1000E, 1600E, 2000E.
19. AO in the XCV400E, 600E, 2000E.
20. AO in the XCV400E, 1000E.
1
1
1
1
1
1
1
GCK2
IO
C9
B10
A8
IO_LVDS_DLL_L8P
IO_L9N_Y
D9
IO_L9P_Y
A9
IO_L10N_Y
IO_VREF_L10P_Y
E10
B9
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16: FG256 Package — XCV50E, XCV100E,
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
XCV200E, XCV300E
Bank
Pin Description
IO_L11N_Y
Pin #
A10
D10
C10
A11
B11
Bank
Pin Description
IO_VREF_L28P_Y
IO_D3_L28N_Y
IO_L29P
Pin #
H13
G16
J13
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
IO_L11P_Y
IO_L12N_YY
IO_L12P_YY
IO_L29N
H15
H14
H16
IO_L13N_YY
IO_L30P_YY
IO_L30N_YY
1
IO_VREF_L13P_YY
IO_L14N_Y
E11
A12
D11
A13
C11
B12
D12
IO_L14P_Y
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
J15
K15
J14
J16
K16
K12
L15
K13
L16
K14
M16
N16
IO_L15N_YY
IO_L31P
IO_VREF_L15P_YY
IO_L16N_YY
IO_L31N
IO_D4_L32P_Y
IO_VREF_L32N_Y
IO_L33P_YY
IO_L33N_YY
IO_L34P
IO_L16P_YY
2
IO_VREF_L17N_Y
IO_L17P_Y
A14
C12
C13
B13
IO_WRITE_L18N_YY
IO_CS_L18P_YY
IO_L34N
IO_L35P_YY
IO_D5_L35N_YY
IO_D6_L36P_Y
IO_VREF_L36N_Y
IO_L37P
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_DOUT_BUSY_L19P_YY
IO_DIN_D0_L19N_YY
IO_L20P
C15
D14
B16
1
L13
2
IO_VREF_L20N
IO_L21P_YY
E13
P16
L12
M15
L14
M14
R16
C16
E14
F13
E15
F12
D16
IO_L37N
IO_L21N_YY
IO_VREF_L22P_Y
IO_L22N_Y
IO_L38P_Y
IO_VREF_L38N_Y
IO_L39P_YY
IO_L39N_YY
IO_VREF_L40P
IO_L40N
IO_L23P
2
IO_L23N
M13
1
IO_VREF_L24P_Y
IO_D1_L24N_Y
IO_D2_L25P_YY
IO_L25N_YY
IO_L26P
F14
T15
N14
N15
E16
F15
G13
F16
G12
G15
G14
IO_D7_L41P_YY
IO_INIT_L41N_YY
4
4
4
4
GCK0
IO
N8
IO_L26N
P10
T14
P13
IO_L27P_YY
IO_L42P_YY
IO_L42N_YY
IO_L27N_YY
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16: FG256 Package — XCV50E, XCV100E,
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
XCV200E, XCV300E
Bank
4
Pin Description
IO_L43P_Y
Pin #
Bank
Pin Description
IO_VREF_L58N_YY
IO_L59P_YY
Pin #
T4
P12
5
5
5
5
5
2
4
IO_VREF_L43N_Y
IO_L44P_YY
R13
T3
4
N12
T13
T12
P11
R12
N11
IO_L59N_YY
P5
2
4
IO_L44N_YY
IO_VREF_L45P_YY
IO_L45N_YY
IO_L46P_Y
IO_VREF_L60P_Y
IO_L60N_Y
T2
4
N5
4
4
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L61N_YY
IO_L61P_YY
IO_L62N
M3
R1
M4
4
IO_L46N_Y
1
4
IO_VREF_L47P_YY
IO_L47N_YY
IO_L48P_YY
T11
2
4
M11
R11
T10
R10
M10
P9
IO_VREF_L62P
IO_L63N_YY
IO_L63P_YY
IO_VREF_L64N_Y
IO_L64P_Y
IO_L65N
N2
4
L5
P1
N1
L3
4
IO_L48N_YY
IO_L49P_Y
4
4
IO_L49N_Y
4
IO_VREF_L50P_Y
IO_L50N_Y
M2
L4
4
T9
IO_L65P
1
4
IO_L51P_Y
N10
R9
IO_VREF_L66N_Y
IO_L66P_Y
IO_L67N_YY
IO_L67P_YY
IO_L68N
M1
4
IO_L51N_Y
K4
L2
L1
K3
K1
K2
K5
J3
J1
J4
H1
J2
4
IO_LVDS_DLL_L52P
N9
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO
R8
N7
T7
T8
R7
P8
P7
T6
M7
R6
P6
IO_L68P
IO
IO_L69N_YY
IO_L69P_YY
IO_VREF_L70N_Y
IO_L70P_Y
IO_L71N
IO_LVDS_DLL_L52N
IO_L53P_Y
IO_VREF_L53N_Y
IO_L54P_Y
IO_L54N_Y
IO_L55P_YY
IO_L55N_YY
IO_L56P_YY
IO_VREF_L56N_YY
IO_L57P_Y
IO_L57N_Y
IO_L58P_YY
IO_L71P
IO
7
7
7
7
7
IO
C2
G1
H4
G5
H2
1
R5
IO_L72N_YY
IO_L72P_YY
IO_L73N
N6
T5
M6
IO_L73P
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16: FG256 Package — XCV50E, XCV100E,
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
XCV200E, XCV300E
Bank
7
Pin Description
IO_L74N_Y
Pin #
G4
H3
G2
F5
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
D13
E5
7
IO_VREF_L74P_Y
IO_L75N_YY
IO_L75P_YY
IO_L76N
7
E12
M5
7
7
F4
M12
N4
7
IO_L76P
F1
7
IO_L77N_YY
IO_L77P_YY
IO_L78N_Y
G3
F2
N13
P3
7
7
E1
P14
1
7
IO_VREF_L78P_Y
IO_L79N
D1
7
E4
E2
F3
C1
D2
E3
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
F8
E8
7
IO_L79P
7
IO_L80N_Y
F9
7
IO_VREF_L80P_Y
IO_L81N_YY
IO_L81P_YY
IO_VREF_L82N
IO_L82P
E9
7
H12
H11
J12
J11
M9
L9
7
2
7
B1
7
A2
2
CCLK
DONE
DXN
D15
R14
R4
3
M8
L8
NA
NA
NA
NA
NA
NA
NA
NA
2
DXP
P4
J6
M0
N3
J5
M1
P2
H6
H5
M2
R3
PROGRAM
TCK
P15
C4
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
T16
T1
TDI
A15
B14
D3
TDO
R15
R2
NA
TMS
L11
L10
L7
NA
NA
NA
VCCINT
VCCINT
VCCINT
C3
C14
D4
L6
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
FG256 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
K11
K10
K9
K8
K7
K6
J10
J9
Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E
J8
P
N
Other
J7
Pair
Bank
Pin
Pin
AO
Functions
H10
H9
Global Differential Clock
0
1
2
3
4
5
1
0
N8
R8
C9
B8
N9
T8
NA
NA
NA
NA
IO_DLL_L52P
IO_DLL_L52N
IO_DLL_L8P
IO_DLL_L8N
H8
H7
A8
G11
G10
G9
G8
G7
G6
F11
F10
F7
A7
IO LVDS
Total Pairs: 83, Asynchronous Outputs: 35
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A3
E6
C5
D5
7
√
√
2
√
√
1
1
VREF
-
2
A4
B4
VREF
3
B5
D6
-
4
A5
C6
VREF
5
C7
B6
-
-
6
C8
D7
F6
7
A6
B7
VREF
B15
B2
8
A8
A7
NA IO_LVDS_DLL
9
A9
D9
2
1
1
√
√
2
√
√
7
√
-
A16
A1
10
11
12
13
14
15
16
17
18
B9
E10
A10
C10
B11
A12
A13
B12
A14
C13
VREF
D10
A11
E11
D11
C11
D12
C12
B13
-
Notes:
1. VREF or I/O option only in the XCV100E, 200E, 300E;
-
otherwise, I/O option only.
VREF
-
2. VREF or I/O option only in the XCV200E, 300E; otherwise,
I/O option only.
VREF
-
VREF
CS
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 17: FG256 Differential Pin Pair Summary
Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E
XCV50E, XCV100E, XCV200E, XCV300E
P
N
Other
P
N
Other
Pair
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Bank
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
5
5
5
Pin
Pin
D14
E13
E14
E15
D16
E16
G13
G12
G14
G16
H15
H16
J14
K16
L15
L16
M16
L13
L12
L14
R16
T15
N15
P13
R13
T13
P11
N11
M11
T10
M10
T9
AO
√
6
√
1
5
3
√
6
√
3
4
√
4
3
√
6
√
3
5
1
√
6
√
√
7
√
√
2
√
√
1
1
1
Functions
Pair
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Notes:
Bank
5
Pin
M7
P6
N6
M6
T3
T2
R1
N2
P1
L3
Pin
R6
R5
T5
T4
P5
N5
M3
M4
L5
AO
√
√
2
√
√
7
√
6
√
1
5
3
√
6
√
3
4
√
4
3
√
6
√
3
5
1
√
6
Functions
C15
B16
C16
F13
F12
F14
F15
F16
G15
H13
J13
H14
K15
J16
K12
K13
K14
N16
P16
M15
M14
M13
N14
T14
P12
N12
T12
R12
T11
R11
R10
P9
DIN, D0
-
VREF
5
VREF
-
5
-
VREF
5
VREF
-
5
-
D1
5
VREF
D2
6
-
-
6
VREF
-
6
-
D3
6
N1
M2
M1
L2
VREF
-
6
L4
-
-
6
K4
L1
VREF
-
6
-
VREF
6
K1
K5
J1
K3
K2
J3
-
-
6
-
-
6
VREF
D5
6
H1
H4
H2
H3
F5
F1
F2
D1
E2
C1
E3
A2
J4
-
VREF
7
G1
G5
G4
G2
F4
G3
E1
E4
F3
D2
B1
-
-
7
-
VREF
7
VREF
-
7
-
VREF
7
-
INIT
7
-
-
7
VREF
-
VREF
7
-
7
VREF
-
VREF
7
-
7
VREF
VREF
1. AO in the XCV50E, 200E, 300E.
2. AO in the XCV50E, 200E.
3. AO in the XCV50E, 300E.
4. AO in the XCV100E, 200E.
5. AO in the XCV200E.
-
-
VREF
-
6. AO in the XCV100E.
7. AO in the XCV50E.
N10
N9
R9
T8
NA IO_LVDS_DLL
R7
P8
1
1
VREF
-
P7
T6
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
FG456 Fine-Pitch Ball Grid Array Packages
Bank
Pin Description
IO_L10N
Pin #
C9
XCV200E and XCV300E devices in FG456 fine-pitch Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in both devices pro-
0
0
0
0
0
0
0
IO_L10P
E10
A9
vided in this package. If the pin is not used as V , it can be
REF
used as general I/O. Immediately following Table 18, see
Table 19 for Differential Pair information.
IO_VREF_L11N_YY
IO_L11P_YY
IO_L12N_Y
C10
F11
B10
B11
Table 18: FG456 — XCV200E and XCV300E
Bank
0
Pin Description
GCK3
Pin #
IO_L12P_Y
C11
IO_LVDS_DLL_L13N
1
0
IO
A2
0
IO
A3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO
A11
1
0
IO
A6
1
A12
0
IO
A10
B5
IO
A14
0
IO
1
IO
B16
0
IO
B9
IO
B19
E13
E15
E16
0
IO
C5
IO
0
IO
D8
IO
0
IO
D10
IO
1
0
IO
E11
1
IO
E17
0
IO_L0N
D5
B3
B4
E6
A4
E7
C6
D6
A5
B6
D7
C7
E8
B7
A7
E9
C8
B8
D9
A8
IO_LVDS_DLL_L13P
IO_L14N_Y
IO_L14P_Y
IO_L15N_Y
IO_L15P_Y
IO_L16N_YY
IO_VREF_L16P_YY
IO_L17N_YY
IO_L17P_YY
IO_L18N_Y
IO_L18P_Y
IO_L19N_Y
IO_L19P_Y
IO_L20N_YY
IO_L20P_YY
IO_L21N_YY
IO_VREF_L21P_YY
IO_L22N_Y
IO_L22P_Y
IO_L23N_Y
D11
C12
D12
B12
A13
E12
B13
C13
D13
B14
C14
F12
A15
B15
C15
A16
E14
D14
C16
D15
0
IO_L0P
0
IO_VREF_L1N_YY
IO_L1P_YY
IO_L2N
0
0
0
IO_L2P
0
IO_VREF_L3N_YY
IO_L3P_YY
IO_L4N_Y
IO_L4P_Y
IO_L5N_Y
IO_L5P_Y
IO_VREF_L6N_YY
IO_L6P_YY
IO_L7N_YY
IO_L7P_YY
IO_L8N_Y
IO_L8P_Y
IO_L9N_Y
IO_L9P_Y
0
0
0
0
0
0
0
0
0
0
0
0
0
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51
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
Pin Description
IO_L23P_Y
Pin #
A17
B17
A18
D16
C17
B18
A19
D17
C18
A20
C19
Bank
Pin Description
IO_D2_L37P_YY
IO_L37N_YY
IO_L38P_YY
IO_L38N_YY
IO_L39P_YY
IO_L39N_YY
IO_L40P_Y
Pin #
H20
H19
H21
J19
J18
J20
K18
J21
K22
K21
K19
L22
L21
L18
L17
L20
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L24N_YY
IO_VREF_L24P_YY
IO_L25N_YY
IO_L25P_YY
IO_L26N_YY
IO_VREF_L26P_YY
IO_L27N_YY
IO_L40N_Y
IO_L27P_YY
IO_L41P
IO_WRITE_L28N_YY
IO_CS_L28P_YY
IO_VREF_L41N
IO_L42P_Y
IO_L42N_Y
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
D18
IO_L43P_YY
IO_L43N_YY
IO_L44P_YY
IO_L44N_YY
1
E19
IO
E20
F20
G21
IO
IO
1
1
IO
G22
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
M21
IO
J22
P22
1
1
IO
L19
IO
R20
IO_D3
K20
C21
D20
C22
D21
D22
E21
E22
F18
F21
F19
F22
G19
G20
G18
H18
H22
IO
R22
T19
IO_DOUT_BUSY_L29P_YY
IO_DIN_D0_L29N_YY
IO_L30P_YY
IO_L30N_YY
IO_VREF_L31P_YY
IO_L31N_YY
IO_L32P_YY
IO_L32N_YY
IO_VREF_L33P_YY
IO_L33N_YY
IO_L34P_Y
IO_L34N_Y
IO_L35P_Y
IO_L35N_Y
IO_VREF_L36P_Y
IO_D1_L36N_Y
IO
1
IO
U18
IO
V20
V21
IO
1
IO
Y22
IO_L45P_YY
IO_L45N_YY
IO_L46P_Y
IO_L46N_Y
IO_D4_L47P_Y
IO_VREF_L47N_Y
IO_L48P_YY
IO_L48N_YY
IO_L49P_YY
IO_L49N_YY
IO_L50P_YY
M18
M20
M19
M17
N22
N21
N20
N18
N19
P21
P20
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
3
Pin Description
IO_L50N_YY
IO_L51P_YY
Pin #
P19
P18
R21
T22
R19
U22
R18
T21
V22
T20
U21
W22
T18
U19
U20
W21
AA22
Y21
V19
M22
Bank
4
Pin Description
IO_L63N
Pin #
V16
3
4
IO_VREF_L64P_YY
IO_L64N_YY
IO_L65P_Y
AB19
AB18
W16
AA17
Y16
3
IO_D5_L51N_YY
IO_D6_L52P_Y
IO_VREF_L52N_Y
IO_L53P_Y
4
3
4
3
4
IO_L65N_Y
3
4
IO_L66P_Y
3
IO_L53N_Y
4
IO_L66N_Y
V15
3
IO_L54P_YY
4
IO_VREF_L67P_YY
IO_L67N_YY
IO_L68P_YY
IO_L68N_YY
IO_L69P_Y
AB16
Y15
3
IO_L54N_YY
IO_L55P_YY
4
3
4
AA15
AB15
W15
Y14
3
IO_VREF_L55N_YY
IO_L56P_YY
4
3
4
3
IO_L56N_YY
IO_L57P_YY
4
IO_L69N_Y
3
4
IO_L70P_Y
V14
3
IO_VREF_L57N_YY
IO_L58P_YY
4
IO_L70N_Y
AA14
AB14
V13
3
4
IO_L71P
3
IO_L58N_YY
IO_D7_L59P_YY
IO_INIT_L59N_YY
IO
4
IO_L71N
3
4
IO_VREF_L72P_YY
IO_L72N_YY
IO_L73P_Y
AA13
AB13
W13
AA12
Y12
3
4
3
4
4
IO_L73N_Y
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
W12
W14
Y13
Y17
4
IO_L74P_Y
IO
4
IO_L74N_Y
V12
IO
4
IO_LVDS_DLL_L75P
U12
IO
1
1
IO
IO
AA16
AA19
5
5
5
5
5
5
5
5
5
5
5
5
IO
U11
IO
V8
1
IO
AB12
AB17
IO
W5
1
IO
IO
AA3
1
IO
AB21
W18
AA20
Y18
IO
AA9
AA10
AB4
IO_L60P_YY
IO_L60N_YY
IO_L61P
IO_L61N
IO_VREF_L62P_YY
IO_L62N_YY
IO_L63P
IO
IO
1
IO
IO
AB7
V17
AB8
Y11
AB20
W17
AA18
GCK1
IO_LVDS_DLL_L75N
IO_L76P_Y
AA11
AB11
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
53
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
5
Pin Description
IO_L76N_Y
Pin #
W11
V11
Y10
AB10
W10
V10
Y9
Bank
6
Pin Description
IO_L90N_YY
IO_L90P_YY
IO_VREF_L91N_YY
IO_L91P_YY
IO_L92N_YY
IO_L92P_YY
IO_VREF_L93N_YY
IO_L93P_YY
IO_L94N_Y
Pin #
V4
V3
Y1
U4
V2
W1
T3
5
IO_L77P_YY
IO_VREF_L77N_YY
IO_L78P_YY
IO_L78N_YY
IO_L79P_Y
6
5
6
5
6
5
6
5
6
5
IO_L79N_Y
6
5
IO_L80P_Y
AB9
W9
6
U2
T5
5
IO_L80N_Y
6
5
IO_L81P_YY
IO_L81N_YY
IO_L82P_YY
IO_VREF_L82N_YY
IO_L83P_Y
V9
6
IO_L94P_Y
V1
R5
U1
R4
T1
5
AA8
Y8
6
IO_L95N_Y
5
6
IO_L95P_Y
5
W8
6
IO_VREF_L96N_Y
IO_L96P_Y
5
W7
6
5
IO_L83N_Y
AA7
AB6
AA6
AB5
AA5
Y7
6
IO_L97N_YY
IO_L97P_YY
IO_L98N_YY
IO_L98P_YY
IO_L99N_YY
IO_L99P_YY
IO_L100N_Y
IO_L100P_Y
IO_L101N
R2
P3
P5
R1
P2
N5
P1
N4
N3
N2
N1
M4
M3
M6
M1
5
IO_L84P_Y
6
5
IO_L84N_Y
6
5
IO_L85P_YY
IO_VREF_L85N_YY
IO_L86P_YY
IO_L86N_YY
IO_L87P_YY
IO_VREF_L87N_YY
IO_L88P_YY
IO_L88N_YY
6
5
6
5
6
5
W6
6
5
AA4
Y6
6
5
6
5
V7
6
IO_VREF_L101P
IO_L102N_Y
IO_L102P_Y
IO_L103N_YY
IO_L103P_YY
IO
5
AB3
6
6
1
6
6
6
6
6
6
6
6
6
6
6
IO
M2
6
IO
M5
P4
6
IO
6
1
IO
R3
IO
T2
T4
7
7
7
7
7
7
7
IO
IO
IO
IO
IO
IO
IO
B1
1
IO
C2
1
1
IO
IO
U3
D1
W2
E4
F4
1
IO
AA1
1
IO_L89N_YY
IO_L89P_YY
W3
Y2
G2
G4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
7
Pin Description
IO
Pin #
J1
Bank
NA
NA
NA
NA
NA
NA
NA
2
Pin Description
Pin #
V6
DXP
M0
7
IO
J4
AB2
U5
1
7
IO
L2
M1
7
IO_L104N_YY
IO_L104P_YY
IO_L105N_YY
IO_L105P_YY
IO_L106N_Y
IO_L106P_Y
IO_L107N_Y
IO_VREF_L107P_Y
IO_L108N_YY
IO_L108P_YY
IO_L109N_YY
IO_L109P_YY
IO_L110N_YY
IO_L110P_YY
IO_L111N_YY
IO_L111P_YY
IO_L112N_Y
IO_VREF_L112P_Y
IO_L113N_Y
IO_L113P_Y
IO_L114N_YY
IO_L114P_YY
IO_L115N_YY
IO_VREF_L115P_YY
IO_L116N_YY
IO_L116P_YY
IO_L117N_YY
IO_VREF_L117P_YY
IO_L118N_YY
IO_L118P_YY
L3
L4
L5
L1
L6
K2
K4
K3
K1
K5
J3
M2
Y4
7
PROGRAM
TCK
W20
C4
7
7
TDI
B20
A21
D3
7
TDO
TMS
7
NA
7
7
NA
NA
NA
NA
NC
NC
NC
NC
W19
W4
7
7
D19
D4
7
7
J2
7
J5
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E5
E18
F6
7
H1
H2
H3
G1
H4
F1
F2
H5
G3
E1
E2
F3
G5
E3
D2
F5
C1
7
7
F17
G7
7
7
G8
7
G9
7
G14
G15
H7
7
7
7
G16
H16
J7
7
7
7
J16
P7
7
7
P16
R7
7
7
R16
T7
2
3
CCLK
DONE
DXN
B22
Y19
Y5
T8
T9
NA
T14
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
NA
Pin Description
VCCINT
Pin #
T15
T16
U6
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
Pin #
K17
J17
H17
G17
L16
K16
G13
G12
F16
F15
F14
F13
G11
G10
F10
F9
NA
VCCINT
NA
VCCINT
NA
VCCINT
U17
V5
NA
VCCINT
NA
VCCINT
V18
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
L7
K7
K6
J6
H6
G6
N7
M7
T6
R6
F8
P6
F7
N6
U10
U9
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AB22
AB1
AA21
AA2
Y20
Y3
U8
U7
T11
T10
U16
U15
U14
U13
T13
T12
T17
R17
P17
N17
N16
M16
P14
P13
P12
P11
P10
P9
N14
N13
N12
N11
N10
N9
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Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
FG456 Differential Pin Pairs
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
M14
M13
M12
M11
M10
M9
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
L14
L13
L12
L11
L10
L9
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
P
N
Other
Pair
Bank
Pin
Pin
AO
Functions
Global Differential Clock
K14
K13
K12
K11
K10
K9
0
1
2
3
4
5
1
0
W12
Y11
A11
C11
U12
AA11
D11
NA
NA
NA
NA
IO_DLL_L75P
IO_DLL_L75N
IO_DLL_L13P
IO_DLL_L13N
B11
IO LVDS
Total Pairs: 119, Asynchronous Output Pairs: 69
J14
J13
J12
J11
J10
J9
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
B3
E6
D5
B4
NA
√
-
VREF
2
E7
A4
NA
√
-
3
D6
C6
VREF
4
B6
A5
1
-
5
C7
D7
1
-
C20
C3
6
B7
E8
√
VREF
7
E9
A7
√
-
B21
B2
8
B8
C8
1
-
9
A8
D9
1
-
A22
A1
10
11
12
13
14
15
16
17
E10
C10
B10
D11
D12
A13
B13
D13
C9
NA
√
-
A9
VREF
Note 1: NC in the XCV200E device.
F11
B11
C12
B12
E12
C13
2
-
NA
2
IO_LVDS_DLL
-
2
-
VREF
-
√
√
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57
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 19: FG456 Differential Pin Pair Summary
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
XCV200E, XCV300E
P
N
P
N
Other
Other
Pair
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Bank
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
Pin
Pin
AO
2
2
√
√
2
2
√
√
√
√
√
√
√
√
√
√
2
1
2
√
√
√
2
1
2
√
√
√
2
2
√
√
√
√
2
Functions
Pair
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Bank
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin
Pin
AO
2
Functions
C14
A15
C15
E14
C16
A17
A18
C17
A19
C18
C19
C21
C22
D22
E22
F21
F22
G20
H18
H20
H21
J18
B14
F12
B15
A16
D14
D15
B17
D16
B18
D17
A20
D20
D21
E21
F18
F19
G19
G18
H22
H19
J19
-
U22
T21
R18
V22
-
-
√
-
-
T20
U21
T18
√
VREF
VREF
W22
U19
W21
Y21
√
-
-
U20
AA22
V19
√
VREF
-
√
-
VREF
√
INIT
-
W18
Y18
AA20
V17
√
-
VREF
NA
√
-
-
AB20
AA18
W17
V16
VREF
CS
NA
√
-
DIN, D0
AB19 AB18
VREF
-
W16
Y16
AA17
V15
1
-
VREF
1
-
-
AB16
Y15
√
VREF
VREF
AA15 AB15
√
-
-
W15
V14
Y14
AA14
V13
1
-
-
1
-
D1, VREF
AB14
NA
√
-
D2
AA13 AB13
VREF
-
W13
Y12
U12
AB11
V11
AB10
V10
AB9
V9
AA12
V12
AA11
W11
Y10
W10
Y9
2
-
J20
-
2
-
K18
K22
K19
L21
L17
M18
M19
N22
N20
N19
P20
P18
T22
J21
-
NA
1
IO_LVDS_DLL
K21
L22
L18
L20
M20
M17
N21
N18
P21
P19
R21
R19
VREF
-
-
√
VREF
-
√
-
-
2
-
-
W9
2
-
-
AA8
W8
√
-
VREF
Y8
√
VREF
-
W7
AA7
AA6
AA5
W6
2
-
-
-
AB6
AB5
Y7
2
-
√
VREF
-
D5
√
VREF
AA4
Y6
√
VREF
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
FG676 Fine-Pitch Ball Grid Array Package
XCV400E and XCV600E devices in the FG676 fine-pitch
Ball Grid Array package have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
P
N
Other
Pair
88
Bank
5
Pin
Pin
AO
√
√
√
√
√
√
2
1
2
√
√
√
2
1
2
√
√
√
2
2
√
√
√
√
2
2
√
√
√
√
√
Functions
V7
Y2
V3
U4
W1
U2
V1
U1
T1
P3
R1
N5
N4
N2
M4
M6
L4
AB3
W3
V4
Y1
V2
T3
T5
R5
R4
R2
P5
P2
P1
N3
N1
M3
L3
-
not used as V , it can be used as general I/O. Immedi-
REF
ately following Table 20, see Table 21 for Differential Pair
information.
89
6
-
90
6
-
Table 20: FG676 — XCV400E, XCV600E
91
6
VREF
Bank
0
Pin Description
GCK3
Pin #
E13
A6
92
6
-
93
6
VREF
0
IO
94
6
-
1
0
IO
A9
95
6
-
1
0
IO
A10
96
6
VREF
0
IO
B3
97
6
-
1
0
IO
B4
98
6
-
1
0
IO
B12
99
6
-
0
IO
C6
C8
D5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
Notes:
6
-
0
IO
6
VREF
0
IO
6
-
1
0
IO
D13
6
-
0
IO
G13
C4
F7
7
-
0
IO_L0N_Y
IO_L0P_Y
IO_L1N_YY
IO_L1P_YY
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N
IO_L3P
7
L1
L5
-
0
7
K2
K3
K5
J2
L6
-
0
G8
C5
D6
E7
A4
F8
7
K4
K1
J3
VREF
0
7
-
0
7
-
0
7
H1
H3
H4
F2
G3
E2
G5
D2
C1
J5
-
0
7
H2
G1
F1
H5
E1
F3
E3
F5
-
0
7
VREF
0
IO_L4N
IO_L4P
B5
D7
E8
G9
A5
F9
7
-
0
7
-
0
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_YY
IO_L6P_YY
IO_L7N_Y
IO_L7P_Y
IO_VREF_L8N_Y
IO_L8P_Y
7
VREF
0
7
-
VREF
-
0
7
0
7
0
D8
C7
1. AO in the XCV200E.
2. AO in the XCV300E.
0
2
0
B7
0
E9
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
0
Pin Description
IO_L9N
Pin #
A7
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L22N
Pin #
E14
F13
D14
A14
C14
H14
G14
C15
E15
D15
C16
F15
G15
D16
E16
A17
C17
E17
F16
D17
F17
C18
A18
G16
C19
G17
D18
0
IO_L9P
D9
IO_L22P
0
IO_L10N
B8
IO_L23N_Y
0
IO_VREF_L10P
IO_L11N_YY
IO_L11P_YY
IO_L12N_Y
G10
C9
IO_VREF_L23P_Y
IO_L24N_Y
0
0
F10
A8
IO_L24P_Y
0
IO_L25N_YY
IO_L25P_YY
IO_L26N_YY
IO_VREF_L26P_YY
IO_L27N_YY
IO_L27P_YY
IO_L28N
0
IO_L12P_Y
E10
G11
D10
B10
F11
C10
E11
G12
D11
C11
F12
A11
E12
D12
C12
A12
H13
B13
0
IO_L13N_YY
IO_L13P_YY
IO_L14N_YY
IO_L14P_YY
IO_L15N
0
0
0
0
0
IO_L15P
IO_L28P
0
IO_L16N_YY
IO_L16P_YY
IO_VREF_L17N_YY
IO_L17P_YY
IO_L18N_YY
IO_L18P_YY
IO_L19N_Y
IO_L29N_YY
IO_L29P_YY
IO_L30N_YY
IO_L30P_YY
IO_L31N_Y
0
0
0
0
0
IO_L31P_Y
0
IO_L32N_YY
IO_L32P_YY
IO_L33N_YY
IO_VREF_L33P_YY
IO_L34N_YY
IO_L34P_YY
IO_L35N_Y
0
IO_L19P_Y
0
IO_VREF_L20N_Y
IO_L20P_Y
0
0
IO_LVDS_DLL_L21N
1
1
1
1
1
1
1
1
1
1
1
GCK2
C13
1
2
IO
A13
IO_VREF_L35P_Y
IO_L36N_Y
B19
1
IO
A16
D19
E18
F18
B20
G19
C20
G18
E19
A21
IO
A19
A20
A22
IO_L36P_Y
IO
IO_L37N_YY
IO_L37P_YY
IO_L38N_YY
IO_VREF_L38P_YY
IO_L39N_YY
IO_L39P_YY
IO_L40N_YY
IO
1
IO
A24
1
IO
B15
1
IO
B17
IO
B23
F14
IO_LVDS_DLL_L21P
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
Pin Description
IO_L40P_YY
Pin #
D20
F19
C21
B22
E20
A23
D21
C22
E21
Bank
2
Pin Description
IO_VREF_L54P_Y
IO_L54N_Y
Pin #
2
1
1
1
1
1
1
1
1
1
G26
IO_L41N_YY
2
J22
H24
J23
IO_VREF_L41P_YY
IO_L42N_YY
2
IO_L55P_YY
IO_L55N_YY
IO_L56P_YY
IO_VREF_L56N_YY
IO_D2_L57P_YY
IO_L57N_YY
IO_L58P_YY
IO_L58N_YY
IO_L59P_Y
2
IO_L42P_YY
2
J24
IO_L43N_Y
2
K20
K22
K21
H25
K23
L20
J26
IO_L43P_Y
2
IO_WRITE_L44N_YY
IO_CS_L44P_YY
2
2
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
D25
2
D26
E26
F26
2
IO_L59N_Y
IO
2
IO_L60P_Y
K25
L22
L21
L23
M20
L24
M23
M22
L26
M21
N19
M24
M26
N20
N24
N21
N23
N22
IO
2
IO_L60N_Y
1
IO
H26
2
IO_L61P_Y
1
IO
K26
2
IO_L61N_Y
1
IO
M25
2
IO_L62P_Y
1
IO
N26
2
IO_L62N_Y
IO_D1
K24
E23
F22
E24
F20
G21
G22
F24
H20
E25
H21
F23
G23
H23
J20
2
IO_VREF_L63P_YY
IO_D3_L63N_YY
IO_L64P_YY
IO_L64N_YY
IO_L65P_Y
IO_DOUT_BUSY_L45P_YY
IO_DIN_D0_L45N_YY
IO_L46P_YY
IO_L46N_YY
IO_L47P_Y
IO_L47N_Y
IO_VREF_L48P_Y
IO_L48N_Y
IO_L49P_Y
IO_L49N_Y
IO_L50P_YY
IO_L50N_YY
IO_VREF_L51P_YY
IO_L51N_YY
IO_L52P_YY
IO_L52N_YY
IO_L53P_Y
IO_L53N_Y
2
2
2
2
2
IO_L65N_Y
2
IO_VREF_L66P_Y
IO_L66N_Y
2
2
IO_L67P_YY
IO_L67N_YY
IO_L68P_YY
IO_L68N_YY
2
2
2
3
3
3
3
3
3
IO
IO
IO
IO
IO
IO
P24
1
P26
1
G24
H22
J21
R26
1
T26
1
U26
G25
W25
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO
Pin #
Y26
Bank
Pin Description
IO_VREF_L85N_YY
IO_L86P_Y
Pin #
W23
AA24
Y23
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
AB25
1
IO
AC25
AC26
P21
P23
P22
R25
P19
P20
R21
R22
R24
R23
T24
R20
T22
U24
T23
U25
T21
U20
U22
V26
T20
U23
V24
U21
V23
W24
V22
IO_L86N_Y
IO
IO_L87P_Y
AB26
W21
Y22
IO_L69P_YY
IO_L69N_YY
IO_L70P_Y
IO_VREF_L70N_Y
IO_L71P_Y
IO_L71N_Y
IO_L72P_YY
IO_L72N_YY
IO_D4_L73P_YY
IO_VREF_L73N_YY
IO_L74P_Y
IO_L74N_Y
IO_L75P_Y
IO_L75N_Y
IO_L76P_Y
IO_L76N_Y
IO_L77P_Y
IO_L77N_Y
IO_L78P_YY
IO_L78N_YY
IO_L79P_YY
IO_D5_L79N_YY
IO_D6_L80P_YY
IO_VREF_L80N_YY
IO_L81P_YY
IO_L81N_YY
IO_L82P_Y
IO_VREF_L82N_Y
IO_L83P_Y
IO_L83N_Y
IO_L84P_YY
IO_L84N_YY
IO_L85P_YY
IO_L87N_Y
IO_L88P_Y
IO_VREF_L88N_Y
IO_L89P_Y
W22
AA23
AB24
W20
AC24
AB23
Y21
IO_L89N_Y
IO_L90P_YY
IO_L90N_YY
IO_D7_L91P_YY
IO_INIT_L91N_YY
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
AA14
AC18
IO
IO
1
AE15
AE20
AE23
IO
IO
1
IO
AF14
AF16
AF18
1
1
IO
IO
IO
AF21
1
IO
AF23
AC22
AD26
AD23
AA20
Y19
IO_L92P_YY
IO_L92N_YY
IO_L93P_Y
IO_L93N_Y
IO_L94P_YY
IO_L94N_YY
IO_VREF_L95P_YY
IO_L95N_YY
IO_L96P
IO_L96N
IO_L97P
IO_L97N
IO_VREF_L98P_YY
AC21
AD22
AB20
AE22
Y18
2
W26
Y25
V21
V20
AF22
AA19
AD21
AA26
Y24
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L98N_YY
IO_L99P_YY
IO_L99N_YY
IO_L100P_Y
IO_L100N_Y
IO_VREF_L101P_Y
IO_L101N_Y
IO_L102P
Pin #
AB19
AC20
AA18
AC19
AD20
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO
Pin #
AD7
AD13
AE4
IO
IO
IO
AE7
1
IO
AE12
2
1
AF20
AB18
AD19
Y17
IO
AF3
AF5
IO
1
1
IO
AF10
AF11
IO_L102N
IO
IO_L103P
AE19
AD18
AF19
AA17
AC17
AB17
Y16
IO_LVDS_DLL_L115N
IO_L116P_Y
IO_VREF_L116N_Y
IO_L117P_Y
IO_L117N_Y
IO_L118P_YY
IO_L118N_YY
IO_L119P_YY
IO_VREF_L119N_YY
IO_L120P_YY
IO_L120N_YY
IO_L121P
AF13
AA13
AF12
AC13
W13
AA12
AD12
AC12
AB12
AD11
Y12
IO_VREF_L103N
IO_L104P_YY
IO_L104N_YY
IO_L105P_Y
IO_L105N_Y
IO_L106P_YY
IO_L106N_YY
IO_L107P_YY
IO_L107N_YY
IO_L108P
AE17
AF17
AA16
AD17
AB16
AC16
AD16
AC15
Y15
IO_L108N
AB11
AD10
AC11
AE10
AC10
AA11
Y11
IO_L109P_YY
IO_L109N_YY
IO_VREF_L110P_YY
IO_L110N_YY
IO_L111P_YY
IO_L111N_YY
IO_L112P_Y
IO_L112N_Y
IO_VREF_L113P_Y
IO_L113N_Y
IO_L114P
IO_L121N
IO_L122P_YY
IO_L122N_YY
IO_L123P_YY
IO_L123N_YY
IO_L124P_Y
IO_L124N_Y
IO_L125P_YY
IO_L125N_YY
IO_L126P_YY
IO_VREF_L126N_YY
IO_L127P_YY
IO_L127N_YY
IO_L128P_Y
IO_VREF_L128N_Y
IO_L129P_Y
AD15
AA15
W14
AD9
AB15
AF15
Y14
AB10
AF9
AD8
AD14
AB14
AC14
AA10
AE8
IO_L114N
IO_LVDS_DLL_L115P
Y10
AC9
2
5
5
GCK1
IO
AB13
AF8
1
Y13
AF7
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
Pin Description
IO_L129N_Y
Pin #
AB9
AA9
AF6
AC8
AC7
AD6
Y9
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L142P_YY
IO_VREF_L143N_YY
IO_L143P_YY
IO_L144N_YY
IO_L144P_YY
IO_L145N_Y
Pin #
Y4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L130P_YY
IO_L130N_YY
IO_L131P_YY
IO_VREF_L131N_YY
IO_L132P_YY
IO_L132N_YY
IO_L133P_YY
IO_L133N_YY
IO_L134P_YY
IO_VREF_L134N_YY
IO_L135P_YY
IO_L135N_YY
IO_L136P_Y
V5
W5
AA1
V6
W4
Y3
IO_L145P_Y
2
AE5
AA8
AC6
AB8
AD5
AA7
AF4
AC5
IO_VREF_L146N_Y
IO_L146P_Y
Y1
U7
W1
V4
W2
U6
V3
T5
U5
U4
T7
U3
U2
T6
U1
T4
R7
T3
R4
R6
R3
R5
P8
P7
R1
P6
P5
P4
IO_L147N_YY
IO_L147P_YY
IO_L148N_YY
IO_VREF_L148P_YY
IO_L149N_YY
IO_L149P_YY
IO_L150N_YY
IO_L150P_YY
IO_L151N_Y
IO_L136N_Y
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
P3
IO
IO
AA3
1
AC1
IO_L151P_Y
1
IO
P1
IO_L152N_Y
1
IO
R2
IO_L152P_Y
1
IO
T1
IO_L153N_Y
1
IO
V1
IO_L153P_Y
IO
W3
Y2
IO_L154N_Y
IO
IO_L154P_Y
IO
Y6
IO_VREF_L155N_YY
IO_L155P_YY
IO_L156N_YY
IO_L156P_YY
IO_L157N_Y
IO_L137N_YY
IO_L137P_YY
IO_L138N_YY
IO_L138P_YY
IO_L139N_Y
IO_L139P_Y
IO_VREF_L140N_Y
IO_L140P_Y
IO_L141N_Y
IO_L141P_Y
IO_L142N_YY
AA5
AC3
AC2
AB4
W6
IO_L157P_Y
AA4
AB3
Y5
IO_VREF_L158N_Y
IO_L158P_Y
IO_L159N_YY
IO_L159P_YY
AB2
V7
1
AB1
7
IO
D1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO
Pin #
D2
Bank
7
Pin Description
IO_L174N_Y
Pin #
J5
2
IO
D3
7
IO_VREF_L174P_Y
IO_L175N_Y
H1
IO
E1
7
G2
J6
IO
G1
H2
7
IO_L175P_Y
IO
7
IO_L176N_YY
IO_L176P_YY
IO_L177N_YY
IO_VREF_L177P_YY
IO_L178N_Y
J7
1
IO
J1
7
F1
H4
G4
F3
H5
E2
H6
G5
F4
H7
G6
E3
E4
1
IO
L1
7
1
IO
M1
7
1
IO
N1
7
IO_L160N_YY
IO_L160P_YY
IO_L161N_YY
IO_L161P_YY
IO_L162N_Y
IO_VREF_L162P_Y
IO_L163N_Y
IO_L163P_Y
IO_L164N_YY
IO_L164P_YY
IO_L165N_YY
IO_VREF_L165P_YY
IO_L166N_Y
IO_L166P_Y
IO_L167N_Y
IO_L167P_Y
IO_L168N_Y
IO_L168P_Y
IO_L169N_Y
IO_L169P_Y
IO_L170N_YY
IO_L170P_YY
IO_L171N_YY
IO_L171P_YY
IO_L172N_YY
IO_VREF_L172P_YY
IO_L173N_YY
IO_L173P_YY
N5
N8
N6
N3
N4
M2
N7
M7
M6
M3
M4
M5
L3
7
IO_L178P_Y
7
IO_L179N_Y
7
IO_L179P_Y
7
IO_L180N_Y
7
IO_VREF_L180P_Y
IO_L181N_Y
7
7
IO_L181P_Y
7
IO_L182N_YY
IO_L182P_YY
7
2
CCLK
DONE
DXN
D24
AB21
AB7
Y8
3
NA
NA
NA
NA
NA
NA
NA
NA
2
L7
DXP
L6
M0
AD4
W7
K2
L4
M1
M2
AB6
AA22
E6
K1
K3
L5
PROGRAM
TCK
TDI
D22
C23
F5
K5
J3
TDO
NA
TMS
K4
J4
NA
NA
NA
NA
NA
NC
NC
NC
NC
NC
T25
T2
H3
K6
K7
G3
P2
N25
L25
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
NC
Pin #
L2
Bank
NA
Pin Description
Pin #
A2
NC
NC
NC
F6
NA
A15
NC
F25
F21
F2
NC
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
G7
G20
H8
NC
NC
C26
C25
C2
NC
H19
J9
NC
NC
C1
J10
J11
J16
J17
J18
K9
NC
B6
NC
B26
B24
B21
B16
B11
B1
NC
NC
NC
NC
K18
L9
NC
NC
AF25
AF24
AF2
AE6
AE3
AE26
AE24
AE21
AE16
AE14
AE11
AE1
AD25
AD2
AD1
AA6
AA25
AA21
AA2
A3
L18
T9
NC
NC
T18
U9
NC
NC
U18
V9
NC
NC
V10
V11
V16
V17
V18
Y7
NC
NC
NC
NC
NC
NC
Y20
W8
W19
NC
NC
NC
NC
0
0
0
0
0
VCCO
VCCO
VCCO
VCCO
VCCO
J13
J12
H9
NC
NC
NC
H12
H11
NC
A25
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
0
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
5
5
5
5
5
5
6
6
6
6
6
6
Pin Description
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
Pin #
H10
J15
J14
H18
H17
H16
H15
N18
M19
M18
L19
K19
J19
V19
U19
T19
R19
R18
P18
W18
W17
W16
W15
V15
V14
W9
Bank
Pin Description
VCCO
Pin #
N9
M9
M8
L8
7
7
7
7
7
7
VCCO
VCCO
VCCO
VCCO
K8
VCCO
J8
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V25
V2
U17
U16
U15
U14
U13
U12
U11
U10
T17
T16
T15
T14
T13
T12
T11
T10
R17
R16
R15
R14
R13
R12
R11
R10
P25
P17
P16
P15
W12
W11
W10
V13
V12
V8
U8
T8
R9
R8
P9
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
P14
P13
P12
P11
P10
N2
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Notes:
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
K10
J25
J2
E5
E22
D4
N17
N16
N15
N14
N13
N12
N11
N10
M17
M16
M15
M14
M13
M12
M11
M10
L17
L16
L15
L14
L13
L12
L11
L10
K17
K16
K15
K14
K13
K12
K11
D23
C3
C24
B9
B25
B2
B18
B14
AF26
AF1
AE9
AE25
AE2
AE18
AE13
AD3
AD24
AC4
AC23
AB5
AB22
A26
A1
1. NC in the XCV400E.
2. VREF or I/O option only in the XCV600E; otherwise, I/O
option only.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
FG676 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Ban
k
Pair
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Pin
Pin
AO
√
Functions
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
E12
C12
H13
F14
F13
A14
H14
C15
D15
F15
D16
A17
E17
D17
C18
G16
G17
B19
E18
B20
C20
E19
D20
C21
E20
D21
E21
E23
E24
G21
F24
E25
F23
H23
A11
D12
A12
B13
E14
D14
C14
G14
E15
C16
G15
E16
C17
F16
F17
A18
C19
D18
D19
F18
G19
G18
A21
F19
B22
A23
C22
F22
F20
G22
H20
H21
G23
J20
-
1
-
1
VREF
NA
NA
1
IO_LVDS_DLL
-
VREF
1
-
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
√
-
P
N
Other
Ban
k
√
VREF
Pair
Pin
Pin
AO
Functions
√
-
Global Differential Clock
-
-
3
2
1
0
0
1
5
4
E13
C13
B13
F14
NA
NA
IO_DLL_L21N
IO_DLL_L21P
√
-
√
-
AB13
AA14
AF13
AC14
IOLVDS
NA IO_DLL_L115N
NA IO_DLL_L115P
1
-
√
-
√
VREF
Total Pairs: 183, Asynchronous Output Pairs: 97
√
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F7
C5
C4
G8
D6
1
√
-
1
VREF
-
1
-
2
E7
√
VREF
√
-
3
F8
A4
NA
NA
√
-
√
VREF
4
D7
B5
-
√
-
5
G9
E8
VREF
√
-
6
F9
A5
√
-
√
VREF
7
C7
D8
1
-
√
-
8
E9
B7
1
VREF
2
-
9
D9
A7
NA
NA
√
-
√
CS
10
11
12
13
14
15
16
17
G10
F10
E10
D10
F11
E11
D11
F12
B8
VREF
√
DIN, D0
C9
-
√
-
A8
1
-
2
-
G11
B10
C10
G12
C11
√
-
1
VREF
√
-
1
-
-
NA
√
-
-
√
√
VREF
√
VREF
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 21: FG676 Differential Pin Pair Summary
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
XCV400E, XCV600E
P
N
Other
P
N
Other
Ban
k
Ban
k
Pair
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Pin
Pin
AO
√
2
1
√
√
√
√
2
1
1
1
√
√
2
1
√
√
√
1
2
√
√
1
1
1
2
√
√
√
√
1
2
√
√
Functions
Pair
86
Pin
Pin
AO
1
Functions
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
G24
J21
H22
G25
J22
-
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
AA24
AB26
Y22
Y23
W21
-
-
87
2
-
G26
H24
J24
VREF
88
W22
1
VREF
J23
-
89
AA23
W20
AB24
AC24
Y21
2
-
K20
K21
K23
J26
VREF
90
√
-
K22
H25
L20
K25
L21
M20
M23
L26
N19
M26
N24
N23
P21
P22
P19
R21
R24
T24
T22
T23
T21
U22
T20
V24
V23
V22
Y25
V20
Y24
D2
91
AB23
AC22
AD23
Y19
√
INIT
-
92
AD26
AA20
AC21
AB20
Y18
√
-
-
93
1
-
L22
-
94
√
-
L23
-
95
AD22
AE22
AF22
AD21
AC20
AC19
AF20
AD19
AE19
AF19
AC17
Y16
√
VREF
L24
-
96
NA
NA
√
-
M22
M21
M24
N20
N21
N22
P23
R25
P20
R22
R23
R20
U24
U25
U20
V26
U23
U21
W24
W26
V21
AA26
W23
D3
97
AA19
AB19
AA18
AD20
AB18
Y17
-
-
98
VREF
-
99
√
-
VREF
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
1
-
-
1
VREF
-
NA
NA
√
-
-
AD18
AA17
AB17
AE17
AA16
AB16
AD16
Y15
VREF
VREF
-
-
1
-
-
√
-
VREF
AF17
AD17
AC16
AC15
AD15
W14
√
-
-
NA
√
-
-
-
-
√
VREF
-
AA15
AB15
Y14
√
-
-
1
-
D5
AF15
AD14
AC14
AA13
AC13
AA12
AC12
1
VREF
VREF
AB14
AF13
AF12
W13
NA
NA
1
-
-
IO_LVDS_DLL
VREF
VREF
-
-
1
-
-
AD12
AB12
√
VREF
√
VREF
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 21: FG676 Differential Pin Pair Summary
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
XCV400E, XCV600E
P
N
Other
P
N
Other
Ban
k
Ban
k
Pair
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Pin
Pin
AO
√
NA
√
√
1
√
√
√
1
1
√
√
√
√
√
√
2
√
√
2
1
1
√
√
√
2
1
√
√
√
√
2
1
1
Functions
Pair
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
Notes:
Pin
Pin
AO
1
√
√
2
1
√
√
√
1
2
√
√
1
1
1
2
√
√
√
√
1
2
√
√
1
2
1
2
√
Functions
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
AD11
AB11
AC11
AC10
Y11
AB10
AD8
AE8
AC9
AF7
AA9
AC8
AD6
AE5
AC6
AD5
AF4
AC3
AB4
AA4
Y5
Y12
AD10
AE10
AA11
AD9
AF9
AA10
Y10
AF8
AB9
AF6
AC7
Y9
-
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T3
R6
R5
P7
P6
P4
N8
N3
M2
M7
M3
M5
L7
R7
R4
R3
P8
R1
P5
N5
N6
N4
N7
M6
M4
L3
-
-
VREF
-
-
-
-
-
VREF
-
-
VREF
-
-
-
VREF
VREF
-
-
-
-
VREF
VREF
-
-
AA8
AB8
AA7
AC5
AA5
AC2
W6
-
K2
K1
L5
L6
-
VREF
L4
-
-
K3
K5
K4
H3
K7
J5
-
-
J3
-
-
J4
-
-
K6
G3
H1
J6
VREF
-
-
AB3
AB2
AB1
V5
VREF
VREF
V7
-
G2
J7
-
Y4
-
F1
G4
H5
H6
F4
G6
E4
-
W5
VREF
H4
F3
E2
G5
H7
E3
VREF
V6
AA1
W4
-
-
Y3
-
-
U7
Y1
VREF
VREF
V4
W1
-
-
-
U6
W2
VREF
T5
V3
-
-
-
-
-
1. AO in the XCV600E.
2. AO in the XCV400E.
U4
U5
U3
T7
T6
U2
T4
U1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
FG680 Fine-Pitch Ball Grid Array Package
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L13N_Y
Pin #
A29
B29
B28
A28
C28
B27
D27
A27
C27
B26
D26
C26
XCV600E, XCV1000E, XCV1600E, and XCV2000E
devices in the FG680 fine-pitch Ball Grid Array package
have footprint compatibility. Pins labeled I0_VREF can be
used as either in all parts unless device-dependent as indi-
IO_L13P_Y
cated in the footnotes. If the pin is not used as V , it can
REF
IO_VREF_L14N_YY
IO_L14P_YY
IO_L15N_YY
IO_L15P_YY
IO_L16N_Y
be used as general I/O. Immediately following Table 22, see
Table 23 for Differential Pair information.
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
0
Pin Description
GCK3
Pin #
A20
D35
B36
C35
A36
IO_L16P_Y
0
IO
IO_L17N_Y
0
IO
IO_L17P_Y
0
IO_L0N_Y
IO_L18N_YY
IO_L18P_YY
IO_VREF_L19N_YY
IO_L19P_YY
IO_L20N_Y
0
IO_L0P_Y
1
0
IO_VREF_L1N_Y
IO_L1P_Y
D34
1
A26
0
B35
C34
A35
D33
B34
C33
A34
D32
B33
C32
D31
A33
C31
B32
B31
D25
B25
C25
A25
D24
A24
B23
C24
A23
B24
B22
E23
A22
D23
B21
C23
A21
E22
B20
C22
0
IO_L2N_YY
IO_L2P_YY
IO_VREF_L3N_YY
IO_L3P_YY
IO_L4N
0
IO_L20P_Y
0
IO_L21N_Y
0
IO_L21P_Y
0
IO_L22N_YY
IO_L22P_YY
IO_VREF_L23N_YY
IO_L23P_YY
IO_L24N_Y
0
IO_L4P
0
IO_L5N_Y
0
IO_L5P_Y
0
IO_L6N_YY
IO_L6P_YY
IO_VREF_L7N_YY
IO_L7P_YY
IO_L8N_Y
0
IO_L24P_Y
0
IO_L25N_Y
0
IO_L25P_Y
0
IO_L26N_YY
IO_L26P_YY
IO_VREF_L27N_YY
IO_L27P_YY
IO_L28N_Y
0
IO_L8P_Y
3
0
IO_VREF_L9N_Y
IO_L9P_Y
A32
0
D30
A31
C30
B30
D29
A30
C29
0
IO_L10N_YY
IO_L10P_YY
IO_VREF_L11N_YY
IO_L11P_YY
IO_L12N_Y
IO_L12P_Y
0
IO_L28P_Y
0
IO_LVDS_DLL_L29N
IO_VREF
0
2
D22
0
0
1
GCK2
D21
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO
Pin #
C5
Bank
1
Pin Description
IO_L47N_Y
Pin #
B11
C11
A10
D11
B10
C10
A9
IO_LVDS_DLL_L29P
IO_L30N_Y
A19
C21
1
IO_L47P_Y
1
IO_L48N_YY
IO_VREF_L48P_YY
IO_L49N_YY
IO_L49P_YY
IO_L50N_Y
2
IO_VREF_L30P_Y
IO_L31N_Y
B19
1
C19
A18
D19
B18
C18
A17
D18
B17
E18
A16
C17
D17
B16
E17
A15
C16
B15
D16
A14
1
IO_L31P_Y
1
IO_L32N_YY
IO_VREF_L32P_YY
IO_L33N_YY
IO_L33P_YY
IO_L34N_Y
1
3
1
IO_VREF_L50P_Y
IO_L51N_Y
D10
1
B9
C9
A8
B8
D9
A7
C8
B7
D8
A6
C7
B6
D7
A5
C6
1
IO_L51P_Y
1
IO_L52N_YY
IO_VREF_L52P_YY
IO_L53N_YY
IO_L53P_YY
IO_L54N_Y
IO_L34P_Y
1
IO_L35N_Y
1
IO_L35P_Y
1
IO_L36N_YY
IO_VREF_L36P_YY
IO_L37N_YY
IO_L37P_YY
IO_L38N_Y
1
1
IO_L54P_Y
1
IO_L55N_Y
1
IO_L55P_Y
1
IO_L56N_YY
IO_VREF_L56P_YY
IO_L57N_YY
IO_L57P_YY
IO_L58N_Y
IO_L38P_Y
1
IO_L39N_Y
1
IO_L39P_Y
1
IO_L40N_YY
IO_VREF_L40P_YY
IO_L41N_YY
IO_L41P_YY
IO_L42N_Y
1
1
1
B14
1
IO_VREF_L58P_Y
IO_L59N_Y
B5
C15
A13
D15
B13
C14
A12
D14
C13
B12
D13
A11
C12
1
D6
A4
B4
D5
1
IO_L59P_Y
1
IO_WRITE_L60N_YY
IO_CS_L60P_YY
IO_L42P_Y
1
IO_L43N_Y
IO_L43P_Y
2
2
2
2
2
2
2
IO
IO
D1
F4
E3
C2
D3
F3
IO_L44N_YY
IO_L44P_YY
IO_L45N_YY
IO_VREF_L45P_YY
IO_L46N_Y
IO_DOUT_BUSY_L61P_YY
IO_DIN_D0_L61N_YY
IO_L62P_Y
IO_L62N_Y
1
IO_L46P_Y
IO_VREF_L63P
D2
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L63N
Pin #
G4
G3
E2
H4
E1
H3
F2
Bank
2
Pin Description
IO_L81N_Y
IO_L82P_YY
IO_L82N_YY
IO_L83P
Pin #
T3
IO_L64P
2
P2
IO_L64N
2
U5
P1
IO_VREF_L65P_Y
IO_L65N_Y
IO_L66P_YY
IO_L66N_YY
IO_L67P
2
2
IO_L83N
U4
R2
U3
V5
2
IO_L84P_Y
2
IO_L84N_Y
IO_VREF_L85P_YY
IO_D3_L85N_YY
IO_L86P_YY
IO_L86N_YY
IO_L87P
J4
2
IO_L67N
F1
2
R1
V4
IO_L68P_Y
IO_L68N_Y
IO_VREF_L69P_YY
IO_L69N_YY
IO_L70P_YY
IO_L70N_YY
IO_VREF_L71P
IO_L71N
J3
2
G2
G1
K4
H2
K3
2
T2
2
V3
2
IO_L87N
T1
2
IO_L88P
W4
U2
W3
U1
AA3
V2
2
IO_L88N
3
H1
2
IO_VREF_L89P_YY
IO_L89N_YY
IO_L90P_YY
IO_L90N_YY
IO_VREF_L91P
IO_L91N
L4
J2
2
IO_L72P
2
IO_L72N
L3
2
2
IO_VREF_L73P_YY
IO_L73N_YY
IO_L74P_YY
IO_L74N_YY
IO_L75P
J1
2
AA4
M3
K2
N4
K1
N3
L2
2
V1
AB2
W2
2
IO_L92P_YY
IO_L92N_YY
2
IO_L75N
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
AP3
AT3
AB3
AB4
IO_VREF_L76P_YY
IO_D1_L76N_YY
IO_D2_L77P_YY
IO_L77N_YY
IO_L78P_Y
IO_L78N_Y
IO_L79P
P4
P3
L1
IO
IO_L93P
2
IO_VREF_L93N
IO_L94P_YY
IO_L94N_YY
IO_L95P_YY
IO_VREF_L95N_YY
IO_L96P
W1
R4
M2
R3
M1
T4
N2
AB5
Y2
AC2
Y1
IO_L79N
IO_L80P
AC3
AA1
AC4
IO_L80N
IO_L96N
1
IO_VREF_L81P_Y
N1
IO_L97P
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L97N
Pin #
AA2
AC5
AB1
AD3
AC1
AD1
AD4
AD2
AE3
AE1
AE4
AE2
Bank
Pin Description
IO_VREF_L115N_YY
IO_L116P_Y
Pin #
AL4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L98P_YY
IO_L98N_YY
IO_D4_L99P_YY
IO_VREF_L99N_YY
IO_L100P_Y
IO_L100N_Y
IO_L101P
AM3
AN1
AM4
AP1
AN2
AP2
AN3
AR1
AN4
AT1
IO_L116N_Y
IO_L117P
IO_L117N
IO_L118P_YY
IO_L118N_YY
IO_L119P_Y
IO_L101N
IO_VREF_L119N_Y
IO_L120P
IO_L102P_YY
IO_L102N_YY
IO_L103P_Y
IO_VREF_L103N_Y
IO_L104P
IO_L120N
IO_L121P
AR2
1
1
AF3
IO_VREF_L121N
IO_L122P_Y
AP4
AF4
AF1
AG3
AF2
AG4
AG1
AH3
AG2
AH1
AJ2
AH2
AJ3
AJ1
AJ4
AK1
AK3
AK2
AK4
AL1
AT2
AR3
AR4
AU2
IO_L104N
IO_L122N_Y
IO_L105P
IO_D7_L123P_YY
IO_INIT_L123N_YY
IO_L105N
IO_L106P_Y
IO_L106N_Y
IO_L107P_YY
IO_D5_L107N_YY
IO_D6_L108P_YY
IO_VREF_L108N_YY
IO_L109P
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
IO
AW19
AV3
AU4
AV5
AT6
IO_L124P_YY
IO_L124N_YY
IO_L125P_Y
IO_L125N_Y
IO_VREF_L126P_Y
IO_L126N_Y
IO_L127P_YY
IO_L127N_YY
IO_VREF_L128P_YY
IO_L128N_YY
IO_L129P_Y
IO_L129N_Y
IO_L130P_Y
IO_L130N_Y
IO_L131P_YY
IO_L131N_YY
AV4
1
IO_L109N
AU6
IO_L110P_YY
IO_L110N_YY
IO_L111P_YY
IO_VREF_L111N_YY
IO_L112P
AW4
AT7
AW5
AU7
AV6
AT8
IO_L112N
IO_L113P
AW6
AU8
AV7
AT9
3
IO_VREF_L113N
IO_L114P_YY
IO_L114N_YY
IO_L115P_YY
AL2
AM1
AL3
AM2
AW7
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_VREF_L132P_YY
IO_L132N_YY
IO_L133P_Y
Pin #
AV8
Bank
Pin Description
IO_L150P_Y
Pin #
AT18
AV17
AU18
AW17
AT19
AV18
AU19
AW18
4
4
4
4
4
4
4
4
4
4
4
AU9
IO_L150N_Y
AW8
AT10
IO_L151P_YY
IO_L151N_YY
IO_VREF_L152P_YY
IO_L152N_YY
IO_L153P_Y
IO_L133N_Y
3
IO_VREF_L134P_Y
IO_L134N_Y
AV9
AU10
AW9
IO_L135P_YY
IO_L135N_YY
IO_VREF_L136P_YY
IO_L136N_YY
IO_L137P_Y
AT11
AV10
AU11
AW10
AU12
AV11
AT13
AW11
AU13
AT14
AV12
AU14
AW12
AT15
AV13
AU15
AW13
IO_L153N_Y
2
IO_VREF_L154P
IO_L154N
AU21
AV19
AT21
IO_LVDS_DLL_L155P
IO_L137N_Y
IO_L138P_Y
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO
AU22
AT34
AW20
AT22
IO_L138N_Y
IO_VREF_L139P_YY
IO_L139N_YY
IO_L140P_YY
IO_L140N_YY
IO_L141P_Y
IO
IO_LVDS_DLL_L155N
IO_VREF_L156P_Y
IO_L156N_Y
2
AV20
AR22
AV23
AW21
AU23
AV21
AT23
AW22
AR23
AV22
AV24
AW23
AW24
AU24
AW25
AT24
AV25
AU25
AW26
IO_L157P_YY
IO_VREF_L157N_YY
IO_L158P_YY
IO_L158N_YY
IO_L159P_Y
IO_L141N_Y
IO_L142P_Y
IO_L142N_Y
IO_L143P_YY
IO_L143N_YY
IO_VREF_L144P_YY
IO_L144N_YY
IO_L145P_Y
IO_L159N_Y
1
AV14
IO_L160P_Y
AT16
AW14
AU16
AV15
AR17
AW15
AT17
IO_L160N_Y
IO_L161P_YY
IO_VREF_L161N_YY
IO_L162P_YY
IO_L162N_YY
IO_L163P_Y
IO_L145N_Y
IO_L146P_Y
IO_L146N_Y
IO_L147P_YY
IO_L147N_YY
IO_VREF_L148P_YY
IO_L148N_YY
IO_L149P_Y
IO_L163N_Y
AU17
AV16
AR18
AW16
IO_L164P_Y
IO_L164N_Y
IO_L165P_YY
IO_VREF_L165N_YY
1
IO_L149N_Y
AT25
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L166P_YY
IO_L166N_YY
IO_L167P_Y
Pin #
AV26
AW27
AU26
AV27
AT26
AW28
AU27
AV28
AW29
AT27
AW30
AU28
AV30
AV29
AW31
AU29
AV31
AT29
AW32
Bank
Pin Description
IO_L184P_Y
IO_L184N_Y
Pin #
AU34
AU36
5
5
IO_L167N_Y
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
IO
W39
AR37
AR39
AR36
AT38
AR38
AP36
IO_L168P_Y
IO_L168N_Y
IO
IO_L169P_YY
IO_L169N_YY
IO_L170P_YY
IO_VREF_L170N_YY
IO_L171P_Y
IO_L185N_YY
IO_L185P_YY
IO_L186N_Y
IO_L186P_Y
IO_VREF_L187N
IO_L187P
1
AT39
IO_L171N_Y
AP37
AP38
AP39
AN36
AN38
AN37
AN39
AM36
AM38
AM37
AL36
AM39
AL37
AL38
AK36
IO_L172P_Y
IO_L188N
IO_L172N_Y
IO_L188P
IO_L173P_YY
IO_VREF_L173N_YY
IO_L174P_YY
IO_L174N_YY
IO_L175P_Y
IO_VREF_L189N_Y
IO_L189P_Y
IO_L190N_YY
IO_L190P_YY
IO_L191N
3
IO_VREF_L175N_Y
IO_L176P_Y
AU30
IO_L191P
AW33
AT30
AV33
AU31
AT31
AW34
AV32
AV34
AU32
AW35
AT32
AV35
AU33
AW36
AT33
IO_L192N_Y
IO_L192P_Y
IO_VREF_L193N_YY
IO_L193P_YY
IO_L194N_YY
IO_L194P_YY
IO_VREF_L195N
IO_L195P
IO_L176N_Y
IO_L177P_YY
IO_VREF_L177N_YY
IO_L178P_YY
IO_L178N_YY
IO_L179P_Y
3
AL39
IO_L179N_Y
AK37
AK38
AJ36
AK39
AJ37
AJ38
AH37
AJ39
AH38
IO_L180P_Y
IO_L196N
IO_L180N_Y
IO_L196P
IO_L181P_YY
IO_VREF_L181N_YY
IO_L182P_YY
IO_L182N_YY
IO_L183P_Y
IO_VREF_L197N_YY
IO_L197P_YY
IO_L198N_YY
IO_L198P_YY
IO_L199N
1
IO_VREF_L183N_Y
AV36
IO_L199P
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
6
Pin Description
IO_VREF_L200N_YY
IO_L200P_YY
IO_L201N_YY
IO_L201P_YY
IO_L202N_Y
IO_L202P_Y
IO_L203N
Pin #
AH39
AG38
AG36
AG39
AG37
AF39
AF36
AE38
AF37
AF38
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L216N_YY
IO_L216P_YY
IO_L217N
Pin #
AA37
W38
W37
6
6
2
6
IO_VREF_L217P
IO_L218N_YY
IO_L218P_YY
IO_L219N_YY
IO_VREF_L219P_YY
IO_L220N
V39
6
W36
U39
V38
U38
V37
T39
V36
T38
V35
R39
U37
U36
R38
U35
P39
T37
P38
T36
N39
6
6
6
IO_L203P
6
IO_L204N
6
IO_L204P
IO_L220P
1
6
IO_VREF_L205N_Y
IO_L205P_Y
IO_L206N_YY
IO_L206P_YY
IO_L207N
AE39
AE36
AD38
AE37
AD39
AD36
AC38
AC39
AD37
AB38
AC35
AB39
AC36
AA38
AC37
AA39
AB35
Y38
IO_L221N
6
IO_L221P
6
IO_L222N_YY
IO_L222P_YY
IO_L223N_YY
IO_VREF_L223P_YY
IO_L224N_Y
IO_L224P_Y
IO_L225N
6
6
6
IO_L207P
6
IO_L208N_Y
IO_L208P_Y
IO_VREF_L209N_YY
IO_L209P_YY
IO_L210N_YY
IO_L210P_YY
IO_L211N
6
6
6
IO_L225P
6
IO_L226N_YY
IO_L226P_YY
IO_L227N_Y
IO_VREF_L227P_Y
IO_L228N
6
6
1
6
IO_L211P
N38
6
IO_L212N
R37
M39
R36
M38
P37
L39
P36
N37
L38
N36
K39
M37
6
IO_L212P
IO_L228P
6
IO_VREF_L213N_YY
IO_L213P_YY
IO_L214N_YY
IO_L214P_YY
IO_VREF_L215N
IO_L215P
IO_L229N
6
IO_L229P
6
AB36
Y39
IO_L230N_Y
IO_L230P_Y
IO_L231N_YY
IO_L231P_YY
IO_L232N_YY
IO_VREF_L232P_YY
IO_L233N
6
2
6
AB37
AA36
6
7
7
7
IO
IO
IO
C38
B37
F37
IO_L233P
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
7
Pin Description
IO_L234N_YY
IO_L234P_YY
IO_L235N_YY
IO_VREF_L235P_YY
IO_L236N
Pin #
K38
L37
J39
Bank
NA
2
Pin Description
Pin #
B3
TDI
TDO
TMS
7
C4
7
NA
E36
7
L36
J38
7
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E8
E9
7
IO_L236P
K37
H39
7
IO_L237N
E15
E16
E24
E25
E31
E32
H5
3
7
IO_VREF_L237P
IO_L238N_YY
IO_L238P_YY
IO_L239N_YY
IO_VREF_L239P_YY
IO_L240N_Y
IO_L240P_Y
IO_L241N
K36
7
H38
J37
7
7
G39
G38
J36
7
7
7
F39
H37
F38
H36
E39
G37
E38
G36
D39
D38
H35
J5
7
7
IO_L241P
J35
7
IO_L242N_YY
IO_L242P_YY
IO_L243N_Y
IO_VREF_L243P_Y
IO_L244N
R5
7
R35
T5
7
7
T35
7
AD5
AD35
AE5
AE35
AL5
AL35
AM5
AM35
AR8
AR9
AR15
AR16
AR24
AR25
AR31
AR32
7
IO_L244P
7
IO_L245N
1
7
IO_VREF_L245P
IO_L246N_Y
IO_L246P_Y
F36
7
D37
E37
7
2
CCLK
DONE
DXN
E4
3
AU5
NA
NA
NA
NA
NA
NA
NA
AV37
AU35
AT37
AU38
AT35
AT5
DXP
M0
M1
M2
PROGRAM
TCK
C36
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
Pin Description
Pin #
Bank
Pin Description
VCCO
Pin #
AR26
AP35
AN35
AK35
AJ35
AG35
AF35
P35
5
6
6
6
6
6
6
7
7
7
7
7
7
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
5
5
5
5
5
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
E34
E33
E30
E29
E27
E26
E10
E11
E13
E14
E6
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
N35
VCCO
L35
VCCO
K35
VCCO
G35
E7
VCCO
F35
P5
N5
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y5
Y4
L5
K5
Y37
Y36
Y35
Y3
G5
F5
AP5
AN5
AK5
AJ5
AG5
AF5
AR10
AR11
AR13
AR14
AR6
AR7
AR34
AR33
AR30
AR29
AR27
W5
W35
M5
M4
M36
M35
E5
E35
E28
E21
E20
E19
E12
D4
D36
D28
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
D20
Bank
NA
Pin Description
GND
Pin #
AR19
AR12
AH5
AH4
AH36
AH35
AA5
AA35
A39
D12
NA
GND
C39
NA
GND
C37
NA
GND
C3
NA
GND
C20
NA
GND
C1
NA
GND
B39
NA
GND
B38
NA
GND
B2
NA
GND
A38
B1
NA
GND
A37
AW39
AW38
AW37
AW3
AW2
AW1
AV39
AV38
AV2
NA
GND
A3
NA
GND
A2
NA
GND
A1
Notes:
1. VREF or I/O option only in the XCV1000E, 1600E, 2000E;
otherwise, I/O option only.
2. VREF or I/O option only in the XCV1600E, 2000E; otherwise,
I/O option only.
3. VREF or I/O option only in the XCV2000E; otherwise, I/O
option only.
AV1
AU39
AU37
AU3
AU20
AU1
AT4
AT36
AT28
AT20
AT12
AR5
AR35
AR28
AR21
AR20
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
FG680 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
√
√
3
3
√
√
5
5
√
√
2
NA
2
2
√
√
5
5
√
√
3
3
√
√
5
5
√
√
2
2
√
√
5
5
Functions
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C26
D25
C25
D24
B23
A23
B22
A22
B21
A21
B20
A19
B19
A18
B18
A17
B17
A16
D17
E17
C16
D16
B14
A13
B13
A12
C13
D13
C12
C11
D11
C10
D10
C9
D26
A26
B25
A25
A24
C24
B24
E23
D23
C23
E22
C22
C21
C19
D19
C18
D18
E18
C17
B16
A15
B15
A14
C15
D15
C14
D14
B12
A11
B11
A10
B10
A9
-
VREF
-
-
-
VREF
-
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
-
P
N
Other
-
Pair Bank
Pin
Pin
AO
Functions
VREF
GCLK LVDS
-
3
2
1
0
0
1
5
4
A20
D21
C22
A19
NA
NA
IO_DLL_L29N
IO_DLL_L29P
IO_DLL_L155N
IO_DLL_L155P
IO_LVDS_DLL
VREF
AU22 AT22 NA
AW19 AT21 NA
IO LVDS
-
VREF
-
Total Pairs: 247, Asynchronous Output Pairs: 111
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A36
B35
A35
B34
A34
B33
D31
C31
B31
D30
C30
D29
C29
B29
A28
B27
A27
B26
C35
D34
C34
D33
C33
D32
C32
A33
B32
A32
A31
B30
A30
A29
B28
C28
D27
C27
5
5
√
√
3
3
√
√
5
5
√
√
2
2
√
√
5
5
-
-
VREF
VREF
2
-
-
3
VREF
-
4
-
-
5
-
VREF
6
-
-
7
VREF
-
8
-
-
9
VREF
-
10
11
12
13
14
15
16
17
-
VREF
VREF
-
-
-
-
VREF
VREF
-
VREF
-
-
-
-
B9
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 23: FG680 Differential Pin Pair Summary
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
√
√
3
3
√
√
5
5
√
√
6
4
4
6
√
4
6
√
√
7
4
√
√
4
√
√
6
4
4
6
√
4
6
√
Functions
Pair Bank
Pin
Pin
AO
√
7
4
√
√
4
√
4
√
√
4
7
√
√
6
4
√
6
4
4
6
√
√
4
√
√
4
7
√
√
6
4
√
6
Functions
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B8
A7
B7
A6
B6
A5
B5
A4
D5
E3
D3
D2
G3
H4
H3
J4
A8
D9
C8
D8
C7
D7
C6
D6
B4
C2
F3
G4
E2
E1
F2
F1
G2
K4
K3
L4
VREF
86
87
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
V4
T2
T1
-
-
V3
-
-
88
W4
U2
-
-
89
W3
U1
VREF
VREF
90
AA3
AA4
AB2
AB4
AB5
AC2
AC3
AC4
AC5
AD3
AD1
AD2
AE1
AE2
AF4
AG3
AG4
AH3
AH1
AH2
AJ1
AK1
AK2
AL1
AM1
AM2
AM3
AM4
AN2
AN3
V2
-
-
91
V1
VREF
VREF
92
W2
-
-
93
W1
VREF
CS
94
Y2
-
DIN, D0
95
Y1
VREF
-
96
AA1
AA2
AB1
AC1
AD4
AE3
AE4
AF3
AF1
AF2
AG1
AG2
AJ2
AJ3
AJ4
AK3
AK4
AL2
AL3
AL4
AN1
AP1
AP2
AR1
-
VREF
97
-
-
98
-
VREF
99
VREF
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
-
-
-
J3
-
-
G1
H2
H1
J2
VREF
VREF
-
-
VREF
-
L3
-
-
J1
M3
N4
N3
P4
L1
VREF
D5
K2
K1
L2
P3
R4
R3
T4
N1
P2
P1
R2
V5
-
VREF
-
-
D1
-
D2
VREF
M2
M1
N2
T3
U5
U4
U3
R1
-
-
-
VREF
-
-
VREF
VREF
-
-
-
-
-
-
D3
VREF
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 23: FG680 Differential Pin Pair Summary
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
4
4
6
√
√
5
5
√
√
3
3
√
√
5
5
√
√
2
2
√
√
5
5
√
√
3
3
√
√
5
5
√
√
2
Functions
Pair Bank
Pin
Pin
AO
Functions
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
AN4
AR2
AT2
AR4
AU4
AT6
AU6
AT7
AU7
AT8
AU8
AT9
AV8
AW8
AV9
AW9
AT1
AP4
AR3
AU2
AV5
-
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
AU21 AV19
AT21
2
VREF
VREF
AT22 NA
IO_LVDS_DLL
-
AV20 AR22
AV23 AW21
AU23 AV21
AT23 AW22
AR23 AV22
AV24 AW23
AW24 AU24
AW25 AT24
AV25 AU25
AW26 AT25
AV26 AW27
AU26 AV27
AT26 AW28
AU27 AV28
AW29 AT27
AW30 AU28
AV30 AV29
AW31 AU29
8
√
√
5
5
√
√
3
3
√
√
5
5
√
√
2
2
√
√
5
5
√
√
3
3
√
√
5
5
√
6
4
VREF
INIT
VREF
-
-
AV4
-
-
AW4
AW5
AV6
VREF
-
-
VREF
VREF
-
AW6
AV7
-
-
-
-
AW7
AU9
AT10
AU10
AT11
-
VREF
VREF
-
-
-
VREF
-
-
-
AV10 AU11
AW10 AU12
VREF
VREF
-
-
AV11
AW11 AU13
AT14 AV12
AU14 AW12
AT15 AV13
AU15 AW13
AV14 AT16
AT13
-
-
VREF
VREF
-
AV31
AT29
-
-
AW32 AU30
AW33 AT30
AV33 AU31
AT31 AW34
AV32 AV34
AU32 AW35
VREF
-
-
-
VREF
VREF
-
AW14 AU16
AV15 AR17
AW15 AT17
AU17 AV16
AR18 AW16
-
-
-
-
-
AT32
AU33 AW36
AT33 AV36
AV35
VREF
VREF
-
-
VREF
AT18
AU18 AW17
AT19 AV18
AU19 AW18
AV17
-
AU34 AU36
AT38 AR36
AP36 AR38
AP37 AT39
-
-
VREF
-
-
-
VREF
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 23: FG680 Differential Pin Pair Summary
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
4
6
√
4
6
√
√
7
4
√
√
4
√
√
6
4
4
6
√
4
6
√
√
7
4
√
√
4
√
4
√
√
4
7
Functions
Pair Bank
Pin
Pin
AO
√
√
6
4
√
6
4
4
6
√
√
4
√
√
4
√
√
√
6
4
√
6
4
4
6
Functions
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
AP39 AP38
AN38 AN36
AN39 AN37
AM38 AM36
AL36 AM37
AL37 AM39
AK36 AL38
AK37 AL39
AJ36 AK38
AJ37 AK39
AH37 AJ38
AH38 AJ39
AG38 AH39
AG39 AG36
AF39 AG37
AE38 AF36
AF38 AF37
AE36 AE39
AE37 AD38
AD36 AD39
AC39 AC38
AB38 AD37
AB39 AC35
AA38 AC36
AA39 AC37
-
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
Notes:
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
R39
U36
U35
T37
T36
N38
M39
M38
L39
N37
N36
M37
L37
L36
K37
K36
J37
V35
U37
R38
P39
P38
N39
R37
R36
P37
P36
L38
K39
K38
J39
-
VREF
VREF
-
-
-
-
-
-
VREF
VREF
-
-
VREF
-
-
-
VREF
-
-
VREF
-
-
VREF
-
-
VREF
-
J38
-
-
H39
H38
G39
J36
VREF
-
-
VREF
G38
F39
F38
E39
E38
D39
F36
E37
VREF
-
-
-
H37
H36
G37
G36
D38
D37
-
-
-
VREF
VREF
-
-
VREF
-
-
-
Y38
Y39
AB35
AB36
VREF
1. AO in the XCV1000E, 1600E, 2000E.
2. AO in the XCV600E, 1000E, 1600E.
3. AO in the XCV600E, 1000E.
4. AO in the XCV1000E, 1600E.
5. AO in the XCV1000E, 2000E.
6. AO in the XCV600E, 1000E, 2000E.
7. AO in the XCV1000E.
-
AA36 AB37
VREF
W38
V39
U39
U38
T39
T38
AA37
W37
W36
V38
-
VREF
8. AO in the XCV2000E.
-
VREF
V37
-
-
V36
DS022-4 (v2.5) March 14, 2003
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
FG860 Fine-Pitch Ball Grid Array Package
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L8P_YY
Pin #
C32
C36
B32
A32
D35
XCV1000E, XCV1600E, and XCV2000E devices in the
FG680 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
IO_VREF_L9N_YY
IO_L9P_YY
notes. If the pin is not used as V , it can be used as gen-
REF
eral I/O. Immediately following Table 24, see Table 25 for
Differential Pair information.
IO_L10N_Y
IO_L10P_Y
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
2
IO_VREF_L11N_Y
IO_L11P_Y
C31
Bank
0
Pin Description
GCK3
Pin #
C22
A26
B31
B34
C24
C29
C34
D24
D36
D40
E26
E28
E35
A38
D38
B37
E37
A37
C39
B36
C38
A36
B35
A35
D37
C37
A34
E36
B33
A33
C35
E34
A31
D34
C30
B30
E33
A30
D33
C33
B29
E32
A29
D32
C28
E31
B28
D31
A28
D30
C27
E29
B27
D29
A27
C26
D28
B26
F27
E27
C25
IO_L12N_YY
IO_L12P_YY
IO_VREF_L13N_YY
IO_L13P_YY
IO_L14N_Y
0
IO
0
IO
0
IO
0
IO
0
IO
IO_L14P_Y
0
IO
IO_L15N_Y
0
IO
IO_L15P_Y
0
IO
IO_VREF_L16N_YY
IO_L16P_YY
IO_L17N_YY
IO_L17P_YY
IO_L18N_Y
0
IO
0
IO
0
IO
0
IO
0
IO_L0N_Y
IO_L0P_Y
IO_L1N_Y
IO_L1P_Y
IO_VREF_L2N_Y
IO_L2P_Y
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_Y
IO_L6P_Y
IO_L7N_Y
IO_L7P_Y
IO_L8N_YY
IO_L18P_Y
0
IO_L19N_Y
0
IO_L19P_Y
0
IO_L20N_Y
0
IO_L20P_Y
0
IO_L21N_Y
0
IO_L21P_Y
0
IO_L22N_YY
IO_L22P_YY
IO_VREF_L23N_YY
IO_L23P_YY
IO_L24N_Y
0
0
0
0
0
IO_L24P_Y
0
IO_L25N_Y
0
IO_L25P_Y
0
IO_L26N_YY
IO_L26P_YY
0
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
Pin Description
IO_VREF_L27N_YY
IO_L27P_YY
Pin #
D27
B25
A25
D26
A24
E25
D25
B24
E24
A23
C23
E23
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L38P_YY
IO_L39N_Y
Pin #
E19
D18
A19
E18
C19
B19
E17
A18
D16
E16
B18
F16
A17
C17
E15
B17
D14
A16
E14
C16
D13
B16
D12
A15
E12
C15
C11
B15
D11
E11
C14
C10
B14
A13
E10
C13
C9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L28N_Y
IO_L39P_Y
IO_L28P_Y
IO_L40N_Y
IO_L29N_Y
IO_L40P_Y
IO_L29P_Y
IO_L41N_YY
IO_VREF_L41P_YY
IO_L42N_YY
IO_L42P_YY
IO_L43N_Y
IO_L30N_YY
IO_L30P_YY
IO_VREF_L31N_YY
IO_L31P_YY
IO_L32N_Y
IO_L43P_Y
IO_L32P_Y
IO_L44N_Y
1
IO_VREF_L33N_Y
IO_L33P_Y
B23
IO_L44P_Y
D23
A22
IO_L45N_YY
IO_VREF_L45P_YY
IO_L46N_YY
IO_L46P_YY
IO_L47N_Y
IO_LVDS_DLL_L34N
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
B22
A14
A20
B11
B13
C8
IO
IO
IO_L47P_Y
IO
IO_L48N_Y
IO
IO_L48P_Y
IO
IO_L49N_Y
IO
C18
C21
D7
IO_L49P_Y
IO
IO
IO_L50N_Y
IO_L50P_Y
IO
D10
D15
D17
E20
D22
D21
IO_L51N_YY
IO_L51P_YY
IO_L52N_YY
IO_VREF_L52P_YY
IO_L53N_Y
IO
IO
IO
IO_LVDS_DLL_L34P
IO_L35N_Y
IO_VREF_L35P_Y
IO_L36N_Y
IO_L36P_Y
IO_L37N_YY
IO_VREF_L37P_YY
IO_L38N_YY
IO_L53P_Y
1
B21
IO_L54N_Y
D20
A21
C20
D19
B20
IO_L54P_Y
IO_L55N_YY
IO_VREF_L55P_YY
IO_L56N_YY
IO_L56P_YY
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
1
Pin Description
IO_L57N_Y
Pin #
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO
Pin #
Y3
AA3
F5
D9
2
1
IO_VREF_L57P_Y
IO_L58N_Y
A12
IO
1
E9
C12
B12
D8
A11
E8
IO_DOUT_BUSY_L70P_YY
IO_DIN_D0_L70N_YY
IO_L71P_Y
1
IO_L58P_Y
D2
E4
E2
D3
F2
1
IO_L59N_YY
IO_VREF_L59P_YY
IO_L60N_YY
IO_L60P_YY
IO_L61N_Y
1
IO_L71N_Y
1
IO_L72P_Y
1
IO_L72N_Y
1
C7
A10
C6
B10
A9
IO_VREF_L73P_Y
IO_L73N_Y
E1
F4
1
IO_L61P_Y
1
IO_L62N_Y
IO_L74P
G2
E3
F1
1
IO_L62P_Y
IO_L74N
1
IO_L63N_YY
IO_VREF_L63P_YY
IO_L64N_YY
IO_L64P_YY
IO_L65N_Y
IO_L75P_Y
1
B9
IO_L75N_Y
G5
G1
F3
1
A8
IO_VREF_L76P_Y
IO_L76N_Y
1
E7
1
B8
IO_L77P_YY
IO_L77N_YY
IO_L78P_Y
G4
H1
J2
1
IO_L65P_Y
C5
A7
1
IO_L66N_Y
1
IO_VREF_L66P_Y
IO_L67N_Y
A6
IO_L78N_Y
G3
H5
K2
H4
K1
L2
1
B7
IO_L79P_Y
1
IO_L67P_Y
D6
A5
IO_L79N_Y
1
IO_L68N_Y
IO_VREF_L80P_YY
IO_L80N_YY
IO_L81P_YY
IO_L81N_YY
IO_VREF_L82P_Y
IO_L82N_Y
1
IO_L68P_Y
C4
B6
1
IO_WRITE_L69N_YY
IO_CS_L69P_YY
1
E6
L3
2
L1
2
2
2
2
2
2
2
2
2
2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
H2
H3
J1
J5
J4
IO_L83P_Y
IO_L83N_Y
M3
J3
K5
M2
N1
R5
U1
U4
W3
IO_VREF_L84P_YY
IO_L84N_YY
IO_L85P_YY
IO_L85N_YY
IO_L86P_Y
M1
N2
K4
N3
K3
L5
IO_L86N_Y
IO_VREF_L87P_YY
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88
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_D1_L87N_YY
IO_D2_L88P_YY
IO_L88N_YY
IO_L89P_Y
Pin #
P2
P3
L4
Bank
Pin Description
Pin #
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
AB4
AC2
AD1
AE3
AF4
AH5
AJ2
P1
R2
M5
R3
M4
R1
N4
T2
IO
IO_L89N_Y
IO
IO_L90P_Y
IO
IO_L90N_Y
IO
IO_L91P_Y
IO
IO_L91N_Y
IO
AL1
AM3
AP3
AR5
AU4
AB2
AB3
IO_L92P
IO
IO_L92N
IO
IO_L93P_Y
P5
T3
IO
IO_L93N_Y
IO
IO_VREF_L94P_Y
IO_L94N_Y
P4
T1
IO
IO_L106P_Y
IO_VREF_L106N_Y
IO_L107P_YY
IO_L107N_YY
IO_L108P_YY
IO_VREF_L108N_YY
IO_L109P_Y
IO_L109N_Y
IO_L110P_Y
IO_L110N_Y
IO_L111P_YY
IO_L111N_YY
IO_D4_L112P_YY
IO_VREF_L112N_YY
IO_L113P_Y
IO_L113N_Y
IO_L114P_Y
IO_L114N_Y
IO_L115P_YY
IO_L115N_YY
IO_L116P_Y
IO_VREF_L116N_Y
IO_L117P_Y
1
IO_L95P_YY
IO_L95N_YY
IO_L96P_Y
U2
R4
U3
T5
AC4
AB1
AC5
AD4
AC3
AC1
AD5
AE4
AD3
AE5
AD2
AE1
AF5
AE2
AG4
AG5
AF1
AH4
AF2
AF3
AJ4
IO_L96N_Y
IO_L97P_Y
T4
IO_L97N_Y
V2
U5
V3
V1
V5
W2
V4
W5
W1
Y2
W4
Y1
Y5
IO_VREF_L98P_YY
IO_D3_L98N_YY
IO_L99P_YY
IO_L99N_YY
IO_L100P_Y
IO_L100N_Y
IO_L101P_Y
IO_L101N_Y
IO_VREF_L102P_YY
IO_L102N_YY
IO_L103P_YY
IO_L103N_YY
IO_VREF_L104P_Y
IO_L104N_Y
IO_L105P_YY
IO_L105N_YY
1
AA1
Y4
AA4
AA2
AG1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L117N_Y
Pin #
AJ5
Bank
Pin Description
IO_L136P
Pin #
AR2
AT1
3
3
3
3
3
3
3
3
3
3
IO_L118P
AG2
AK4
AG3
AL4
AH1
AL5
AH2
AM4
AH3
AM5
AJ1
IO_L136N
IO_L118N
IO_L137P_Y
AV4
AT2
IO_L119P_Y
IO_VREF_L137N_Y
IO_L138P_Y
IO_L119N_Y
AU1
AU5
AU2
AW3
AV1
AW5
IO_L120P_Y
IO_L138N_Y
IO_L120N_Y
IO_L139P_Y
IO_L121P_Y
IO_L139N_Y
IO_L121N_Y
IO_D7_L140P_YY
IO_INIT_L140N_YY
IO_L122P_YY
IO_D5_L122N_YY
IO_D6_L123P_YY
IO_VREF_L123N_YY
IO_L124P_Y
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
BA22
AV17
AY11
AY12
AY13
AY14
BA8
AN3
AN4
AJ3
IO
IO
IO_L124N_Y
IO
IO
IO_L125P_YY
IO_L125N_YY
IO_L126P_YY
IO_VREF_L126N_YY
IO_L127P_Y
AN5
AK1
AK2
AP4
AK3
AP5
AR3
IO
IO
IO
BA17
BA19
BA20
BA21
BB9
IO
IO_L127N_Y
IO
IO_L128P_Y
IO
2
IO_VREF_L128N_Y
IO_L129P_YY
IO_L129N_YY
IO_L130P_YY
IO_VREF_L130N_YY
IO_L131P_Y
AL2
IO
AR4
AL3
AM1
AT3
AM2
AT4
AT5
AN1
AU3
AN2
AP1
AP2
AR1
AV3
IO
BB18
AV6
IO_L141P_YY
IO_L141N_YY
IO_L142P_Y
IO_L142N_Y
IO_L143P_Y
IO_L143N_Y
IO_VREF_L144P_Y
IO_L144N_Y
IO_L145P_Y
IO_L145N_Y
IO_L146P_YY
IO_L146N_YY
IO_VREF_L147P_YY
BA4
AY4
BA5
IO_L131N_Y
AW6
BB5
IO_L132P_Y
IO_L132N_Y
BA6
IO_L133P_YY
IO_L133N_YY
IO_L134P_Y
AY5
BB6
AY6
IO_VREF_L134N_Y
IO_L135P_Y
BA7
AV7
IO_L135N_Y
BB7
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L147N_YY
IO_L148P_Y
Pin #
AW7
AY7
Bank
4
Pin Description
IO_L166P_Y
Pin #
AY17
AW15
BB17
AU16
AV16
AY18
AW16
BA18
BB19
AW17
AY19
AV18
AW18
BB20
AY20
AV19
BB21
AW19
4
IO_L166N_Y
IO_L148N_Y
BB8
4
IO_L167P_Y
IO_L149P_Y
BA9
AV8
4
IO_L167N_Y
IO_L149N_Y
4
IO_L168P_YY
IO_L168N_YY
IO_VREF_L169P_YY
IO_L169N_YY
IO_L170P_Y
IO_L150P_YY
IO_L150N_YY
IO_VREF_L151P_YY
IO_L151N_YY
IO_L152P_Y
AW8
BA10
BB10
AY8
4
4
4
4
AV9
4
IO_L170N_Y
IO_L152N_Y
BA11
4
IO_L171P_Y
2
IO_VREF_L153P_Y
IO_L153N_Y
BB11
AW9
4
IO_L171N_Y
4
IO_L172P_YY
IO_L172N_YY
IO_VREF_L173P_YY
IO_L173N_YY
IO_L174P_Y
IO_L154P_YY
IO_L154N_YY
IO_VREF_L155P_YY
IO_L155N_YY
IO_L156P_Y
AY9
4
BA12
BB12
AV10
BA13
AW10
BB13
AY10
AV11
BA14
AW11
BB14
AV12
BA15
AW12
AY15
AW13
BB15
AV14
BA16
AW14
AY16
BB16
AV15
4
4
4
4
IO_L174N_Y
1
IO_L156N_Y
4
IO_VREF_L175P_Y
IO_L175N_Y
AY21
IO_L157P_Y
4
AV20
IO_L157N_Y
4
IO_LVDS_DLL_L176P
AW20
IO_VREF_L158P_YY
IO_L158N_YY
IO_L159P_YY
IO_L159N_YY
IO_L160P_Y
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
AY22
AV24
AV34
AW27
AW36
AY23
AY31
AY33
BA26
BA29
BA33
BB25
AW21
BB22
IO
IO
IO
IO_L160N_Y
IO
IO_L161P_Y
IO
IO_L161N_Y
IO
IO_L162P_Y
IO
IO_L162N_Y
IO
IO_L163P_Y
IO
IO
IO_L163N_Y
IO_L164P_YY
IO_L164N_YY
IO_VREF_L165P_YY
IO_L165N_YY
IO
IO_LVDS_DLL_L176N
IO_L177P_Y
IO_VREF_L177N_Y
1
AW22
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L178P_Y
Pin #
BB23
AW23
AV23
BA23
AW24
BB24
AY24
AW25
BA24
AV25
AW26
AY25
AV26
BA25
BB26
AV27
AY26
AU27
AW28
BB27
AY27
AV28
BA27
AW29
BB28
AV29
AY28
AW30
BA28
AW31
BB29
AV31
AY29
AY32
AW32
BB30
AV32
Bank
5
Pin Description
IO_L196N_Y
Pin #
AY30
BA30
AW33
BB31
AV33
AY34
IO_L178N_Y
5
IO_L197P_YY
IO_VREF_L197N_YY
IO_L198P_YY
IO_L198N_YY
IO_L199P_Y
IO_L179P_YY
IO_VREF_L179N_YY
IO_L180P_YY
IO_L180N_YY
IO_L181P_Y
5
5
5
5
2
5
IO_VREF_L199N_Y
IO_L200P_Y
BA31
IO_L181N_Y
5
AW34
BB32
BA32
AY35
BB33
AW35
AV35
BB34
AY36
BA34
BB35
AV36
BA35
AY37
BB36
BA36
AW37
BB37
BA37
AY38
BB38
AY39
IO_L182P_Y
5
IO_L200N_Y
IO_L182N_Y
5
IO_L201P_YY
IO_VREF_L201N_YY
IO_L202P_YY
IO_L202N_YY
IO_L203P_Y
IO_L183P_YY
IO_VREF_L183N_YY
IO_L184P_YY
IO_L184N_YY
IO_L185P_Y
5
5
5
5
5
IO_L203N_Y
IO_L185N_Y
5
IO_L204P_Y
IO_L186P_Y
5
IO_L204N_Y
IO_L186N_Y
5
IO_L205P_YY
IO_VREF_L205N_YY
IO_L206P_YY
IO_L206N_YY
IO_L207P_Y
IO_L187P_YY
IO_VREF_L187N_YY
IO_L188P_YY
IO_L188N_YY
IO_L189P_Y
5
5
5
5
5
IO_L207N_Y
IO_L189N_Y
5
IO_L208P_Y
IO_L190P_Y
5
IO_VREF_L208N_Y
IO_L209P_Y
IO_L190N_Y
5
IO_L191P_Y
5
IO_L209N_Y
IO_L191N_Y
5
IO_L210P_Y
IO_L192P_Y
5
IO_L210N_Y
IO_L192N_Y
IO_L193P_YY
IO_L193N_YY
IO_L194P_YY
IO_VREF_L194N_YY
IO_L195P_Y
6
6
6
6
6
6
6
IO
IO
IO
IO
IO
IO
IO
AA40
AB41
AC42
AD39
AE40
AF38
AF40
IO_L195N_Y
IO_L196P_Y
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO
Pin #
AJ40
AL41
AN38
AN42
AP41
AR39
AV41
AV42
AW40
AU41
AV39
AU42
AT41
AU38
AT42
AV40
AR41
AU39
AR42
AU40
AT38
AP42
AN41
AT39
AT40
AM40
AR38
AM41
AM42
AR40
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L226P_YY
IO_L227N_Y
Pin #
AN39
AK42
AN40
AM38
AJ41
AJ42
AM39
AH40
AH41
AL38
AH42
AL39
AG41
AK39
AG40
AJ38
AG42
AF42
AJ39
AF41
AH38
AE42
AH39
AG38
AE41
AG39
AD42
AD40
AF39
AD41
AE38
AE39
AC40
AD38
AC41
AB42
AC38
IO
IO
IO_L227P_Y
IO
IO_VREF_L228N_YY
IO_L228P_YY
IO_L229N_YY
IO_L229P_YY
IO_L230N_Y
IO
IO
IO_L211N_YY
IO_L211P_YY
IO_L212N_Y
IO_L212P_Y
IO_L213N_Y
IO_L213P_Y
IO_VREF_L214N_Y
IO_L214P_Y
IO_L215N
IO_L230P_Y
IO_L231N_Y
IO_L231P_Y
IO_L232N_Y
IO_L232P_Y
IO_L233N
IO_L233P
IO_L215P
IO_L234N_Y
IO_L216N_Y
IO_L216P_Y
IO_VREF_L217N_Y
IO_L217P_Y
IO_L218N_YY
IO_L218P_YY
IO_L219N_Y
IO_L219P_Y
IO_L220N_Y
IO_L220P_Y
IO_VREF_L221N_YY
IO_L221P_YY
IO_L222N_YY
IO_L222P_YY
IO_VREF_L223N_Y
IO_L223P_Y
IO_L224N_Y
IO_L224P_Y
IO_VREF_L225N_YY
IO_L225P_YY
IO_L226N_YY
IO_L234P_Y
IO_VREF_L235N_Y
IO_L235P_Y
IO_L236N_YY
IO_L236P_YY
IO_L237N_Y
IO_L237P_Y
IO_L238N_Y
IO_L238P_Y
IO_VREF_L239N_YY
IO_L239P_YY
IO_L240N_YY
IO_L240P_YY
IO_L241N_Y
2
AL40
IO_L241P_Y
AP38
AP39
AL42
AP40
AK40
AK41
IO_L242N_Y
IO_L242P_Y
IO_VREF_L243N_YY
IO_L243P_YY
IO_L244N_YY
IO_L244P_YY
DS022-4 (v2.5) March 14, 2003
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
Pin Description
IO_VREF_L245N_Y
IO_L245P_Y
Pin #
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L256P_YY
IO_L257N_Y
Pin #
T38
R39
T42
R42
R38
R40
P39
R41
P38
P42
N39
P40
M39
P41
M38
N42
L39
L38
N41
K40
M42
M40
K38
M41
J40
1
6
6
AB40
AC39
IO_VREF_L257P_Y
IO_L258N_Y
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
F38
H40
H41
J42
IO_L258P_Y
IO
IO_L259N
IO
IO_L259P
IO
K39
L42
IO_L260N_Y
IO
IO_L260P_Y
IO
N40
T40
IO_L261N_Y
IO
IO_L261P_Y
IO
U40
V38
W42
Y42
AA42
AA41
AB39
Y41
IO_L262N_Y
IO
IO_L262P_Y
IO
IO_L263N_YY
IO_L263P_YY
IO_L264N_YY
IO_VREF_L264P_YY
IO_L265N_Y
IO
IO
IO_L246N_YY
IO_L246P_YY
IO_L247N_Y
IO_VREF_L247P_Y
IO_L248N_YY
IO_L248P_YY
IO_L249N_YY
IO_VREF_L249P_YY
IO_L250N_Y
IO_L250P_Y
IO_L251N_Y
IO_L251P_Y
IO_L252N_YY
IO_L252P_YY
IO_L253N_YY
IO_VREF_L253P_YY
IO_L254N_Y
IO_L254P_Y
IO_L255N_Y
IO_L255P_Y
IO_L256N_YY
IO_L265P_Y
1
AA39
Y40
Y39
Y38
W41
W40
W39
W38
V41
V39
V40
V42
U39
U41
U38
U42
T39
T41
IO_L266N_YY
IO_L266P_YY
IO_L267N_YY
IO_VREF_L267P_YY
IO_L268N_Y
IO_L268P_Y
IO_L269N_Y
J39
IO_VREF_L269P_Y
IO_L270N_YY
IO_L270P_YY
IO_L271N_YY
IO_VREF_L271P_YY
IO_L272N_Y
L40
J38
L41
K42
H39
K41
H38
J41
IO_L272P_Y
IO_L273N_Y
IO_L273P_Y
G40
H42
G39
IO_L274N_YY
IO_L274P_YY
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
Pin Description
IO_L275N_Y
IO_VREF_L275P_Y
IO_L276N_Y
IO_L276P_Y
IO_L277N
Pin #
G38
G42
G41
F40
F42
F41
F39
E42
E40
E41
E39
D41
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
K37
7
7
7
7
7
7
7
7
7
7
7
7
T6
T37
U6
U37
IO_L277P
V6
IO_L278N_Y
IO_VREF_L278P_Y
IO_L279N_Y
IO_L279P_Y
IO_L280N_Y
IO_L280P_Y
V37
AE6
AE37
AF6
AF37
AG6
AG37
AN6
AN37
AP6
2
CCLK
DONE
DXN
B4
AW2
BA38
AW38
AW41
AV37
BA39
AV2
3
NA
NA
NA
NA
NA
NA
NA
NA
2
DXP
AP37
AU9
AU10
AU17
AU18
AU25
AU26
AU33
AU34
M0
M1
M2
PROGRAM
TCK
B38
TDI
B5
TDO
D5
NA
TMS
B39
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
F9
F10
F17
F18
F25
F26
F33
F34
J6
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
F23
F24
F28
F29
F31
F32
F35
F36
F11
F12
F14
J37
K6
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
Pin #
F15
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin #
AC37
AD37
AH37
AJ37
AL37
AM37
AR37
AT37
G37
F19
F20
F7
F8
G6
H6
L6
M6
P6
H37
R6
L37
W6
M37
Y6
P37
AC6
AD6
AH6
AJ6
R37
W37
Y37
AL6
AM6
AR6
AT6
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N6
N5
N38
N37
F6
AU11
AU12
AU14
AU15
AU19
AU20
AU7
AU8
AU23
AU24
AU28
AU29
AU31
AU32
AU35
AU36
F37
F30
F22
F21
F13
E5
E38
E30
E22
E21
E13
D42
D4
D39
D1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
C42
C41
C40
C3
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
AV22
AV21
AV13
AU6
C2
AU37
AU30
AU22
AU21
AU13
AK6
C1
BB41
BB40
BB4
BB39
BB3
BB2
BA42
BA41
BA40
BA3
BA2
BA1
B42
AK5
AK38
AK37
AB6
AB5
AB38
AB37
AA6
AA5
B41
AA38
AA37
A41
B40
B3
B2
A40
B1
A4
AY42
AY41
AY40
AY3
A39
A3
A2
Notes:
1. REF or I/O option only in the XCV1600E, 2000E; otherwise,
I/O option only.
V
AY2
2. VREF or I/O option only in the XCV2000E; otherwise, I/O
AY1
option only.
AW42
AW4
AW39
AW1
AV5
AV38
AV30
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
FG860 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
2
1
1
5
√
√
5
5
√
√
1
1
√
√
2
2
NA
2
2
√
√
1
1
√
√
5
5
√
√
5
1
1
2
√
Functions
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C28
B28
A28
C27
B27
A27
D28
F27
C25
B25
D26
E25
B24
A23
E23
D23
D22
B21
A21
D19
E19
A19
C19
E17
D16
B18
A17
E15
D14
E14
D13
D12
E12
C11
D32
E31
D31
D30
E29
D29
C26
B26
E27
D27
A25
A24
D25
E24
C23
B23
A22
D21
D20
C20
B20
D18
E18
B19
A18
E16
F16
C17
B17
A16
C16
B16
A15
C15
-
-
-
-
-
VREF
-
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
-
P
N
Other
-
Pair Bank
Pin
Pin
AO
Functions
VREF
Global Differential Clock
-
3
2
1
0
0
1
5
4
C22
B22
A22
D22
NA
NA
IO_DLL_L34N
IO_DLL_L34P
IO_DLL_L176N
IO_DLL_L176P
-
-
AY22 AW21 NA
BA22 AW20 NA
IO LVDS
VREF
-
VREF
Total Pairs: 281, Asynchronous Output Pairs: 111
IO_LVDS_DLL
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D38
E37
C39
C38
B35
D37
A34
B33
C32
B32
D35
C35
A31
C30
E33
D33
B29
A29
A38
B37
A37
B36
A36
A35
C37
E36
A33
C36
A32
C31
E34
D34
B30
A30
C33
E32
2
1
1
1
√
√
5
5
√
√
1
1
√
√
2
2
√
√
-
VREF
-
-
2
VREF
VREF
3
-
-
4
-
-
5
VREF
-
6
-
VREF
7
-
-
8
-
-
9
VREF
-
10
11
12
13
14
15
16
17
-
VREF
VREF
-
-
-
-
-
-
-
VREF
-
-
VREF
-
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
√
2
2
√
√
1
1
√
√
5
5
√
√
5
1
1
2
√
√
3
1
2
4
2
1
√
2
1
√
√
5
2
√
√
Functions
Pair Bank
Pin
Pin
AO
2
√
√
3
1
2
4
2
1
√
2
1
√
√
5
2
√
√
2
√
2
√
√
2
5
√
√
1
2
√
1
2
4
2
Functions
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
D11
C14
B14
E10
C9
A12
C12
D8
E8
B15
E11
C10
A13
C13
D9
E9
VREF
86
87
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
N3
L5
K3
P2
-
-
D1
-
88
P3
L4
D2
VREF
89
P1
R2
-
-
90
M5
R3
-
VREF
91
M4
R1
-
-
92
N4
T2
-
B12
A11
C7
C6
A9
VREF
93
P5
T3
-
-
94
P4
T1
VREF
A10
B10
B9
-
95
U2
R4
-
-
96
U3
T5
-
VREF
97
T4
V2
-
E7
A8
-
98
U5
V3
D3
C5
A6
B8
-
99
V1
V5
-
A7
VREF
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
W2
W5
Y2
V4
-
D6
C4
E6
B7
-
W1
W4
Y5
-
A5
-
VREF
B6
CS
Y1
-
F5
D2
E2
DIN, D0
AA1
AA4
AB3
AB1
AD4
AC1
AE4
AE5
AE1
AE2
AG5
AH4
AF3
AG1
AG2
AG3
Y4
VREF
E4
-
AA2
AC4
AC5
AC3
AD5
AD3
AD2
AF5
AG4
AF1
AF2
AJ4
AJ5
AK4
AL4
-
D3
E1
F2
-
VREF
F4
VREF
-
G2
F1
E3
-
VREF
G5
F3
-
-
G1
G4
J2
VREF
-
H1
G3
K2
-
-
-
VREF
H5
H4
L2
-
-
K1
VREF
-
L3
-
-
L1
J5
VREF
VREF
J4
M3
M1
K4
-
VREF
-
-
-
-
J3
N2
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
1
3
√
√
2
√
√
2
5
√
√
1
2
√
1
2
4
2
1
3
√
√
2
1
1
5
√
√
5
5
√
√
1
1
Functions
Pair Bank
Pin
Pin
AO
√
√
2
2
√
√
2
1
1
5
√
√
5
5
√
√
1
1
√
√
2
2
Functions
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
AH1
AH2
AH3
AJ1
AL5
AM4
AM5
AN3
AJ3
-
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
AY9
BA12
AV10
-
-
BB12
VREF
D5
BA13 AW10
-
VREF
BB13
AV11
AY10
BA14
-
AN4
AN5
AK2
AK3
AR3
AR4
AM1
AM2
AT5
-
VREF
AK1
AP4
AP5
AL2
AL3
AT3
-
AW11 BB14
AV12 BA15
-
VREF
-
-
AW12 AY15
AW13 BB15
-
VREF
-
-
AV14
AW14 AY16
BB16 AV15
BA16
-
VREF
-
AT4
-
VREF
AN1
AN2
AP2
AV3
AT1
-
AY17 AW15
BB17 AU16
-
AU3
AP1
AR1
AR2
AV4
AU1
AU2
AV1
AV6
AY4
AW6
BA6
BB6
BA7
BB7
AY7
BA9
AW8
BB10
AV9
BB11
-
-
VREF
AV16
AY18
-
-
AW16 BA18
BB19 AW17
VREF
-
-
AT2
VREF
AY19
AW18 BB20
AY20 AV19
BB21 AW19
AY21 AV20
AW20 AW21 NA
AV18
-
AU5
AW3
AW5
BA4
BA5
BB5
AY5
AY6
AV7
AW7
BB8
AV8
BA10
AY8
BA11
AW9
-
-
-
VREF
INIT
-
-
VREF
-
IO_LVDS_DLL
-
BB22 AW22
BB23 AW23
2
2
√
√
1
1
√
√
5
5
√
VREF
VREF
-
-
AV23
BA23
VREF
-
AW24 BB24
AY24 AW25
-
VREF
-
-
BA24
AV25
-
-
AW26 AY25
VREF
-
AV26
BB26
AY26
BA25
AV27
AU27
-
VREF
-
-
-
VREF
AW28 BB27
VREF
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
√
5
1
1
2
√
√
2
2
√
√
1
1
√
√
5
5
√
√
5
1
1
2
√
3
1
2
4
2
1
√
2
1
√
Functions
Pair Bank
Pin
Pin
AO
√
5
2
√
√
2
√
√
3
1
2
4
2
1
√
2
1
√
√
5
2
√
√
2
√
2
√
√
2
5
√
√
1
2
Functions
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
AY27
AV28
-
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
AR40 AM42
-
BA27 AW29
BB28 AV29
-
AP38
AL42
AL40
AP39
VREF
-
-
AY28 AW30
BA28 AW31
-
AK40 AP40
AN39 AK41
AN40 AK42
AJ41 AM38
AM39 AJ42
AH41 AH40
VREF
-
-
BB29
AY29
AV31
AY32
-
-
VREF
VREF
AW32 BB30
AV32 AY30
BA30 AW33
-
-
-
-
VREF
AH42
AL38
-
BB31
AY34
AV33
BA31
-
AG41 AL39
AG40 AK39
-
VREF
-
AW34 BB32
BA32 AY35
BB33 AW35
-
AG42
AJ39
AJ38
AF42
-
VREF
VREF
-
AH38 AF41
AH39 AE42
AE41 AG38
AD42 AG39
AF39 AD40
AE38 AD41
AC40 AE39
AC41 AD38
AC38 AB42
AC39 AB40
AB39 AA41
-
AV35
AY36
BB35
BA35
BB34
BA34
AV36
AY37
-
-
-
-
VREF
VREF
-
-
BB36 BA36
AW37 BB37
-
-
VREF
-
BA37
BB38
AV42
AY38
AY39
AV41
-
VREF
-
-
-
VREF
AU41 AW40
-
-
AU42
AU38
AV40
AV39
AT41
AT42
-
AA39
Y39
W41
W39
V41
V40
U39
U38
T39
Y41
Y40
Y38
W40
W38
V39
V42
U41
U42
VREF
VREF
-
-
VREF
AU39 AR41
AU40 AR42
-
-
VREF
-
AP42
AT39
AT38
-
-
AN41
-
-
VREF
AM40 AT40
AM41 AR38
-
-
VREF
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
101
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
FG900 Fine-Pitch Ball Grid Array Package
XCV600E, XCV1000E, and XCV1600E devices in the
FG900 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
P
N
Other
Pair Bank
Pin
Pin
AO
√
1
2
4
2
1
3
√
√
2
√
√
2
5
√
√
1
2
√
1
2
4
2
1
3
Functions
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
Notes:
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T38
T42
R38
P39
P38
N39
M39
M38
L39
N41
M42
K38
J40
T41
R39
R42
R40
R41
P42
P40
P41
N42
L38
K40
M40
M41
J39
-
notes. If the pin is not used as V , it can be used as gen-
REF
eral I/O. Immediately following Table 26, see Table 27 for
Differential Pair information.
VREF
-
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
-
Bank
0
Pin Description
Pin #
-
GCK3
C15
-
4
0
IO
A7
-
4
0
IO
A13
-
4
0
IO
C5
VREF
4
0
IO
C6
-
4
0
IO
C14
-
5
0
IO
D8
VREF
0
IO
D10
-
4
0
IO
IO
D13
L40
L41
H39
H38
G40
G39
G42
F40
F41
E42
E41
D41
VREF
0
E6
J38
-
5
0
IO
E9
K42
K41
J41
VREF
5
0
IO
E14
-
4
0
IO
F9
-
5
0
IO
F14
H42
G38
G41
F42
F39
E40
E39
-
0
IO
G15
VREF
5
0
IO
K11
-
0
IO
K12
-
4
0
IO
L13
VREF
4
0
IO_L0N_YY
IO_L0P_YY
IO_L1N_Y
IO_L1P_Y
IO_VREF_L2N_Y
IO_L2P_Y
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
C4
-
-
3
0
F7
0
D5
G8
0
1. AO in the XCV1000E, 2000E.
2. AO in the XCV1000E, 1600E.
3. AO in the XCV2000E.
4. AO in the XCV1600E.
5. AO in the XCV1000E.
1
0
A3
0
H9
4
0
B4
4
0
J10
0
A4
D6
E7
B5
0
0
0
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Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L6N_Y
Pin #
A5
Bank
0
Pin Description
IO_L24P_Y
Pin #
A11
G13
B12
A12
K13
F13
B13
G14
E13
D14
B14
A14
J14
IO_L6P_Y
F8
0
IO_L25N_Y
IO_L7N_Y
D7
0
IO_L25P_Y
IO_L7P_Y
N11
G9
0
IO_L26N_YY
IO_L26P_YY
IO_VREF_L27N_YY
IO_L27P_YY
IO_L28N_Y
IO_L8N_YY
IO_L8P_YY
IO_VREF_L9N_YY
IO_L9P_YY
IO_L10N_Y
IO_L10P_Y
IO_L11N_Y
IO_L11P_Y
IO_L12N_YY
IO_L12P_YY
IO_VREF_L13N_YY
IO_L13P_YY
IO_L14N
0
E8
0
A6
0
J11
C7
0
0
IO_L28P_Y
B7
0
IO_L29N_Y
C8
0
IO_L29P_Y
H10
G10
F10
A8
0
IO_L30N_YY
IO_L30P_YY
IO_VREF_L31N_YY
IO_L31P_YY
IO_L32N
0
0
K14
J15
0
4
H11
0
B15
4
3
D9
0
IO_L32P
H15
3
2,3
IO_L14P
C9
0
IO_VREF_L33N_YY
IO_L33P_YY
IO_LVDS_DLL_L34N
F15
4
IO_L15N_YY
IO_L15P_YY
IO_L16N
B9
0
D15
J12
0
A15
4
E10
IO_VREF_L16P
IO_L17N
A9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
E15
4
G11
B10
A25
4
IO_L17P
B17
4
4
IO_L18N_YY
IO_L18P_YY
IO_L19N_Y
IO_L19P_Y
IO_L20N_Y
IO_L20P_Y
IO_L21N_Y
IO_L21P_Y
IO_L22N_YY
IO_L22P_YY
IO_VREF_L23N_YY
IO_L23P_YY
IO_L24N_Y
H12
B18
4
4
C10
C23
4
H13
F11
E11
D11
D16
5
D17
4
D23
4
E19
4
5
B11
E24
4
4
G12
F22
5
F12
C11
G17
4
G20
1
4
A10
J16
4
D12
E12
J17
5
J19
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
103
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO
Pin #
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L52N_YY
IO_VREF_L52P_YY
IO_L53N_YY
IO_L53P_YY
IO_L54N_YY
IO_L54P_YY
IO_L55N_YY
IO_VREF_L55P_YY
IO_L56N_YY
IO_L56P_YY
IO_L57N_Y
Pin #
C21
A22
H19
B22
E21
D22
F21
C22
H20
E22
G21
A23
A24
K19
C24
B24
H21
G22
E23
C25
D24
A26
B26
K20
D25
J21
5
J20
4
IO
L18
IO_LVDS_DLL_L34P
IO_L35N_YY
IO_VREF_L35P_YY
IO_L36N_YY
IO_L36P_YY
IO_L37N_YY
IO_VREF_L37P_YY
IO_L38N_YY
IO_L38P_YY
IO_L39N_Y
E16
B16
2
F16
A16
H16
C16
K15
K16
G16
A17
E17
F17
C17
E18
A18
D18
A19
B19
G18
D19
H18
F18
IO_L57P_Y
IO_L39P_Y
IO_L58N_Y
IO_L40N_Y
IO_L58P_Y
IO_L40P_Y
IO_L59N_YY
IO_VREF_L59P_YY
IO_L60N_YY
IO_L60P_YY
IO_L61N_Y
IO_L41N_YY
IO_VREF_L41P_YY
IO_L42N_YY
IO_L42P_YY
IO_L43N_Y
IO_L61P_Y
IO_L43P_Y
IO_L62N_Y
IO_L44N_Y
IO_L62P_Y
IO_L44P_Y
IO_L63N_YY
IO_VREF_L63P_YY
IO_L64N_YY
IO_L64P_YY
IO_L65N_Y
IO_L45N_YY
IO_VREF_L45P_YY
IO_L46N_YY
IO_L46P_YY
IO_L47N_Y
1
F19
B20
K17
4
C26
4
4
D20
IO_L65P_Y
F23
4
IO_L47P_Y
A20
IO_L66N_Y
B27
1
IO_L48N_Y
G19
C20
K18
E20
IO_VREF_L66P_Y
IO_L67N_Y
G23
IO_L48P_Y
A27
F24
IO_L49N_Y
IO_L67P_Y
3
IO_L49P_Y
IO_L68N_YY
IO_L68P_YY
IO_WRITE_L69N_YY
IO_CS_L69P_YY
B28
4
4
IO_L50N_YY
IO_L50P_YY
IO_L51N_YY
IO_L51P_YY
B21
A28
4
D21
K21
C27
F20
A21
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
Pin #
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L80N_YY
IO_L81P_YY
IO_L81N_YY
IO_L82P
Pin #
L22
5
IO
D29
4
IO
G26
H27
G29
G30
M21
J24
4
IO
H24
4
IO
H25
5
IO
H28
IO_L82N
4
IO
IO
J25
IO_L83P_YY
IO_L83N_YY
IO_VREF_L84P_YY
IO_L84N_YY
IO_L85P_YY
IO_L85N_YY
IO_L86P_YY
IO_L86N_YY
IO_L87P_YY
IO_VREF_L87N_YY
IO_D1_L88P
IO_D2_L88N
IO_L89P_YY
IO_L89N_YY
IO_L90P
5
J27
J26
4
IO
K30
H30
L23
4
IO
M24
4
4
IO
M25
K26
3
IO
N20
J28
4
IO
N23
J29
5
IO
P26
K24
5
4
IO
P27
K27
4
IO
P30
J30
M22
K29
IO
R30
J22
E27
IO_DOUT_BUSY_L70P_YY
IO_DIN_D0_L70N_YY
IO_L71P
3
K28
4
4
C29
L25
3
IO_L71N
D28
N21
K25
L24
L27
IO_L72P_Y
IO_L72N_Y
IO_VREF_L73P_YY
IO_L73N_YY
IO_L74P_Y
IO_L74N_Y
IO_L75P_YY
IO_L75N_YY
IO_VREF_L76P_Y
IO_L76N_Y
IO_L77P_YY
IO_L77N_YY
IO_L78P_YY
IO_L78N_YY
IO_L79P
G25
E25
IO_L90N
IO_L91P_YY
IO_L91N_YY
IO_L92P_Y
1
E28
4
C30
L29
4
4
K22
IO_L92N_Y
M23
3
F27
IO_L93P_YY
IO_L93N_YY
IO_VREF_L94P
IO_L94N
L26
L28
D30
J23
1
L30
L21
F28
G28
E30
G27
E29
K23
H26
F30
M27
M26
M29
N29
M30
N25
N27
N30
P21
IO_L95P_YY
IO_L95N_YY
IO_L96P_YY
IO_L96N_YY
IO_L97P
IO_L97N
IO_L79N
IO_VREF_L98P_YY
IO_D3_L98N_YY
IO_VREF_L80P_YY
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
105
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
Pin Description
IO_L99P_YY
Pin #
N26
P28
P29
N24
P22
R26
P25
R29
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L108N_YY
IO_L109P_YY
IO_VREF_L109N_YY
IO_L110P_YY
IO_L110N_YY
IO_L111P
Pin #
T28
T21
T25
U28
U30
T23
U27
U25
V27
U24
V29
W30
U22
U21
W29
V26
W27
W26
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L99N_YY
IO_L100P
IO_L100N
IO_L101P_YY
IO_L101N_YY
IO_VREF_L102P_YY
IO_L102N_YY
IO_L103P_YY
IO_L103N_YY
IO_VREF_L104P_YY
IO_L104N_YY
IO_L105P_YY
IO_L105N_YY
IO_L106P
IO_L111N
IO_L112P_YY
IO_L112N_YY
IO_D4_L113P_YY
IO_VREF_L113N_YY
IO_L114P
4
R21
3
R28
2
R25
T30
4
P24
IO_L114N
3
R27
IO_L115P_YY
IO_L115N_YY
IO_L116P_YY
IO_L116N_YY
IO_L117P
R24
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
T22
4
IO
T24
4
1
IO
T26
IO_VREF_L117N
IO_L118P_YY
IO_L118N_YY
IO_L119P_Y
Y29
4
IO
T29
W25
Y30
5
IO
U26
4
4
IO
V23
V24
4
4
IO
V25
IO_L119N_Y
Y28
5
IO
V30
IO_L120P_YY
IO_L120N_YY
IO_L121P
AA30
W24
AA29
V20
4
IO
Y21
4
IO
AA26
AA23
AB27
AB29
AC28
4
4
4
5
4
IO
IO_L121N
4
IO
IO_L122P
Y27
4
IO
IO_L122N
W23
IO
IO_L123P_YY
IO_D5_L123N_YY
IO_D6_L124P_YY
IO_VREF_L124N_YY
IO_L125P_YY
IO_L125N_YY
IO_L126P_YY
IO_L126N_YY
Y26
AB30
V21
IO
IO
AD26
AD29
5
5
IO
AE27
U29
AA28
Y25
IO_L106N
IO_L107P_YY
IO_VREF_L107N_YY
IO_L108P_YY
R22
AA27
W22
Y23
2
T27
R23
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
3
Pin Description
IO_L127P_YY
IO_VREF_L127N_YY
IO_L128P_YY
IO_L128N_YY
IO_L129P
Pin #
Y24
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO
Pin #
4
AE15
AE18
4
3
AB28
AC30
AA25
W21
IO
3
IO
AE21
5
3
IO
AE24
5
3
IO
AF17
AF18
5
3
IO_L129N
AA24
AB26
AD30
Y22
IO
4
3
IO_L130P_YY
IO_L130N_YY
IO_L131P_YY
IO_VREF_L131N_YY
IO_L132P
IO
AJ18
AK18
3
IO
5
3
IO
AK25
AK27
4
4
3
AC27
AD28
AB25
AC26
AE30
AD27
AF30
AF29
AB24
AB23
AE28
IO
3
IO
AH23
AH24
5
3
IO_L132N
IO
3
IO_L133P_YY
IO_L133N_YY
IO_L134P_YY
IO_L134N_YY
IO_L135P
IO_L142P_YY
IO_L142N_YY
IO_L143P_YY
IO_L143N_YY
IO_L144P
IO_L144N
IO_VREF_L145P
IO_L145N
IO_L146P
IO_L146N
IO_L147P_YY
IO_L147N_YY
IO_VREF_L148P_YY
IO_L148N_YY
IO_L149P
IO_L149N
IO_L150P
IO_L150N
IO_L151P_YY
IO_L151N_YY
IO_VREF_L152P_YY
IO_L152N_YY
IO_L153P
IO_L153N
IO_L154P
AF27
AK28
3
4
3
AG26
AH27
3
3
3
AD23
AJ27
3
IO_VREF_L135N
IO_L136P_YY
IO_L136N_YY
IO_L137P_Y
1
3
AB21
AF25
3
3
4
3
AG30
AC22
AH26
4
4
3
IO_L137N_Y
AC25
AE26
3
IO_L138P_YY
IO_VREF_L138N_YY
IO_L139P
AA21
AG25
AJ26
AD22
AA20
AH25
AC21
AF24
AG24
AK26
AJ24
AF23
AE23
AB20
AC20
1
3
AG29
AH30
AC24
3
3
IO_L139N
3
3
IO_L140P
AF28
AD25
4
3
IO_L140N
3
IO_D7_L141P_YY
IO_INIT_L141N_YY
AH29
AA22
3
4
4
4
4
4
4
GCK0
IO
AJ16
4
AB19
AC16
4
IO
IO
AC19
4
IO
AD18
AD21
4
IO
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L154N
Pin #
AG23
AF22
AE22
AJ22
AG22
Bank
Pin Description
IO_L173P_YY
Pin #
AE16
AE17
AG17
AJ17
4
4
4
4
4
4
4
4
4
IO_L155P_YY
IO_L155N_YY
IO_VREF_L156P_YY
IO_L156N_YY
IO_L157P
IO_L173N_YY
IO_VREF_L174P_YY
IO_L174N_YY
4
IO_L175P
AD15
AH17
AG16
4
3
2
AK24
AD20
IO_L175N
3
IO_L157N
IO_VREF_L176P_YY
IO_L176N_YY
IO_L158P_YY
IO_L158N_YY
IO_L159P
AA19
AF21
AK17
AF16
IO_LVDS_DLL_L177P
4
AH22
AA18
AG21
AK23
IO_VREF_L159N
IO_L160P
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
AK16
4
IO
AA11
AA14
4
4
IO_L160N
IO
4
IO_L161P_YY
IO_L161N_YY
IO_L162P
AH21
AD19
IO
AD14
4
5
IO
AE7
AE8
5
AE20
AJ21
AG20
AF20
IO
4
4
4
IO_L162N
IO
AE10
4
IO_L163P
IO
AF6
IO_L163N
IO
AF10
4
4
IO_L164P
AC18
IO
AG9
4
IO_L164N
AF19
AJ20
AE19
IO
IO
AG12
AG14
5
IO_L165P_YY
IO_L165N_YY
IO_VREF_L166P_YY
IO_L166N_YY
IO_L167P
4
IO
AH8
AK6
1
5
AK22
AH20
AG19
AB17
AJ19
AD17
AA16
AA17
AK21
AB16
AG18
AK20
AK19
AD16
IO
5
IO
AK14
4
IO
AJ13
AJ15
4
IO_L167N
IO
IO_L168P
IO_LVDS_DLL_L177N
IO_L178P_YY
IO_VREF_L178N_YY
IO_L179P_YY
IO_L179N_YY
IO_L180P_YY
IO_VREF_L180N_YY
IO_L181P_YY
IO_L181N_YY
IO_L182P
AH16
4
IO_L168N
AC15
2,3
IO_L169P_YY
IO_L169N_YY
IO_VREF_L170P_YY
IO_L170N_YY
IO_L171P
AG15
AB15
AF15
AA15
AF14
AH15
AK15
AB14
IO_L171N
IO_L172P
IO_L172N
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L182N
Pin #
AF13
AH14
AJ14
AE14
AG13
AK13
AD13
AE13
AF12
AC13
AA13
AA12
Bank
5
Pin Description
IO_L201P
Pin #
AC11
AG8
AK8
AF7
IO_L183P
5
IO_L201N
IO_L183N
5
IO_L202P_YY
IO_VREF_L202N_YY
IO_L203P_YY
IO_L203N_YY
IO_L204P
IO_L184P_YY
IO_VREF_L184N_YY
IO_L185P_YY
IO_L185N_YY
IO_L186P
5
5
AG7
AK7
5
5
AJ7
5
IO_L204N
AD10
AH6
AC10
AD9
AG6
AB10
AJ5
IO_L186N
5
IO_L205P
IO_L187P
5
IO_L205N
IO_L187N
5
IO_L206P_YY
IO_VREF_L206N_YY
IO_L207P_YY
IO_L207N_YY
IO_L208P
IO_L188P_YY
IO_VREF_L188N_YY
IO_L189P_YY
IO_L189N_YY
IO_L190P
5
1
AJ12
5
AB12
AE11
5
4
5
AD8
4
4
AK12
5
IO_L208N
AK5
4
IO_L190N
Y13
5
IO_L209P
AC9
1
IO_L191P
AG11
AF11
AH11
AJ11
5
IO_VREF_L209N
IO_L210P
AJ4
IO_L191N
5
AG5
AK4
IO_L192P
5
IO_L210N
3
IO_L192N
5
IO_L211P_YY
IO_L211N_YY
AH5
4
4
IO_L193P_YY
IO_L193N_YY
IO_L194P_YY
IO_L194N_YY
IO_L195P_YY
IO_VREF_L195N_YY
IO_L196P_YY
IO_L196N_YY
IO_L197P_YY
IO_L197N_YY
IO_L198P_YY
IO_VREF_L198N_YY
IO_L199P_YY
IO_L199N_YY
IO_L200P
AE12
5
AG3
4
AG10
4
AD12
AK11
AJ10
AC12
AK10
AD11
AJ9
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
T2
4
T10
U1
5
U4
4
U6
4
U7
4
V1
5
AE9
V5
AH10
AF9
V8
4
Y10
4
AH9
AA4
5
AK9
AB5
4
AF8
AB7
5
IO_L200N
AB11
AC3
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Production Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO
Pin #
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L229N_YY
IO_VREF_L229P_YY
IO_L230N
Pin #
4
4
AC5
Y7
4
IO
AD1
AC1
V11
AA3
5
IO
AE5
IO_L212N_YY
IO_L212P_YY
IO_L213N
AF3
AC6
IO_L230P
3
IO_L231N_YY
IO_L231P_YY
IO_L232N
AA2
4
4
AH2
U10
3
IO_L213P
AG2
W7
AA6
Y6
IO_L214N
AB9
AE4
IO_L232P
IO_L214P
IO_L233N_YY
IO_L233P_YY
IO_L234N_Y
IO_L234P_Y
1
IO_VREF_L215N_YY
IO_L215P_YY
IO_L216N_Y
IO_L216P_Y
IO_L217N_YY
IO_L217P_YY
IO_VREF_L218N
IO_L218P
AE3
Y4
4
AH1
AA1
4
4
AB8
V7
3
AD6
IO_L235N_YY
IO_L235P_YY
IO_VREF_L236N
IO_L236P
Y3
Y2
AG1
AA10
AA9
AD4
AD5
AD2
AD3
AF2
AA8
AA7
AF1
Y9
1
Y5
W5
W4
W6
V6
IO_L237N_YY
IO_L237P_YY
IO_L238N_YY
IO_L238P_YY
IO_L239N
IO_L219N_YY
IO_L219P_YY
IO_L220N_YY
IO_L220P_YY
IO_L221N
W2
U9
V4
IO_L239P
IO_L221P
IO_VREF_L240N_YY
IO_L240P_YY
IO_L241N_YY
IO_L241P_YY
IO_L242N
AB2
T8
IO_VREF_L222N_YY
IO_L222P_YY
IO_L223N_YY
IO_L223P_YY
IO_L224N
U5
W1
Y1
AB6
AC4
AE1
W8
IO_L242P
T9
IO_L224P
IO_L243N_YY
IO_L243P_YY
IO_VREF_L244N_YY
IO_L244P_YY
IO_L245N_YY
IO_L245P_YY
IO_VREF_L246N_YY
IO_L246P_YY
IO_L247N
T7
IO_L225N_YY
IO_L225P_YY
IO_VREF_L226N_YY
IO_L226P_YY
IO_L227N_YY
IO_L227P_YY
IO_L228N_YY
IO_L228P_YY
Y8
U3
T5
AB4
AB3
W9
V2
4
R9
4
3
AA5
T6
3
2
W10
T4
AB1
V10
U2
T1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
Pin Description
Pin #
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L256P
Pin #
N6
7
7
7
7
7
7
7
7
7
7
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
E3
IO_L257N_YY
IO_L257P_YY
IO_L258N_YY
IO_L258P_YY
IO_L259N
N5
4
F1
N1
5
G1
M4
M5
M2
5
G4
5
H3
4
1
J1
IO_VREF_L259P
IO_L260N_YY
IO_L260P_YY
IO_L261N_Y
IO_L261P_Y
IO_L262N_YY
IO_L262P_YY
IO_L263N
M1
4
J3
L4
L2
4
J4
4
4
J6
M7
4
4
L10
L5
L1
M8
K2
M9
4
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
N2
4
N8
4
IO
N10
IO_L263P
5
4
IO
P3
IO_L264N
L3
4
4
IO
P9
IO_L264P
M10
5
IO
R1
IO_L265N_YY
IO_L265P_YY
IO_L266N_YY
IO_VREF_L266P_YY
IO_L267N_YY
IO_L267P_YY
IO_L268N_YY
IO_L268P_YY
IO_L269N_YY
IO_VREF_L269P_YY
IO_L270N_YY
IO_L270P_YY
IO_L271N
K5
K1
L6
K3
L7
K4
L8
J5
4
IO
T3
IO_L247P
R10
3
IO_L248N_YY
IO_L248P_YY
IO_L249N_YY
IO_VREF_L249P_YY
IO_L250N_YY
IO_L250P_YY
IO_L251N_YY
IO_VREF_L251P_YY
IO_L252N_YY
IO_L252P_YY
IO_L253N
R5
4
R6
R8
2
R4
R7
R3
P10
P6
P5
P2
P7
P4
N4
R2
N7
P1
M6
K6
H4
H1
K7
J7
IO_L271P
J2
IO_L253P
IO_L272N_YY
IO_L272P_YY
IO_L273N_YY
IO_VREF_L273P_YY
IO_L274N
H5
G2
L9
G5
F3
K8
IO_L254N_YY
IO_L254P_YY
IO_L255N_YY
IO_VREF_L255P_YY
IO_L256N
IO_L274P
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
Pin Description
IO_L275N_YY
IO_L275P_YY
IO_L276N_YY
IO_L276P_YY
IO_L277N
Pin #
G3
E1
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
M20
N13
N14
N15
N16
N17
N18
P13
P18
R13
R18
T13
T18
U13
U18
V13
V14
V15
V16
V17
V18
W11
W12
W19
W20
Y11
Y12
Y19
Y20
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
H6
E2
E4
K9
IO_VREF_L277P
IO_L278N_YY
IO_L278P_YY
IO_L279N_Y
J8
F4
3
D1
4
IO_L279P_Y
H7
IO_L280N_YY
IO_VREF_L280P_YY
IO_L281N
G6
1
C2
D2
F5
IO_L281P
4
IO_L282N_YY
IO_L282P_YY
D3
3
K10
2
CCLK
DONE
DXN
F26
AJ28
AJ3
AH4
AF4
AC7
AK3
AG28
B3
3
NA
NA
NA
NA
NA
NA
NA
NA
2
DXP
M0
M1
M2
PROGRAM
TCK
TDI
H22
D26
C1
TDO
NA
TMS
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
L11
L12
L19
L20
M11
M12
M19
NA
NA
NA
NA
NA
NA
NA
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
B6
M15
M14
L15
L14
H14
M13
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
Pin #
C12
B25
C19
M18
M17
L17
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin #
Y14
W14
W13
AH12
AE2
V12
U12
T12
U11
T11
U8
H17
L16
M16
F29
M28
P23
R20
P20
R19
N19
P19
AE29
W28
U23
U20
T20
W3
F2
R12
P12
N12
R11
P11
P8
M3
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y18
AH7
AK30
AJ30
B30
V19
T19
U19
AJ25
AH19
W18
AC17
Y17
W17
W16
Y16
AJ6
A30
AK29
AJ29
AC29
H29
B29
A29
AH28
V28
Y15
W15
AC14
N28
C28
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
AG27
D27
AF26
E26
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Notes:
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
J13
C13
V9
N9
F25
J9
AE25
G24
AJ23
AD24
H23
B23
AJ8
AC8
H8
AD7
B8
AE6
G7
AC23
AB22
V22
F6
AF5
E5
N22
AH18
AB18
J18
AG4
D4
V3
C18
U17
T17
N3
C3
AK2
AH3
AC2
H2
R17
P17
U16
T16
B2
R16
P16
A2
AK1
AJ2
AJ1
A1
U15
T15
R15
P15
B1
U14
T14
1. VREF or I/O option only in the XCV1000E and XCV1600E;
otherwise, I/O option only.
2. VREF or I/O option only in the XCV1600E; otherwise, I/O
option only.
3. I/O option only in the XCV600E.
4. No Connect in the XCV600E.
R14
P14
AH13
AB13
5. No Connect in the XCV600E, 1000E.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
FG900 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
4
Functions
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C10
F11
D11
G12
C11
D12
A11
B12
K13
B13
E13
B14
J14
H12
H13
E11
B11
F12
A10
E12
G13
A12
F13
G14
D14
A14
K14
B15
F15
A15
B16
A16
C16
K16
A17
F17
E18
D18
B19
D19
F18
B20
D20
G19
K18
B21
F20
-
2
-
2
-
2
-
√
-
√
VREF
1
-
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
1
-
P
N
Other
√
-
Pair Bank
Pin
Pin
AO
Functions
√
VREF
GCLK LVDS
A15
2
-
3
2
1
0
0
1
5
4
C15
E15
NA
NA
NA
NA
IO_DLL_ 34N
IO_DLL_ 34P
IO_DLL_ 177N
IO_DLL_ 177P
2
-
E16
√
-
AK16 AH16
J15
√
VREF
-
AJ16
AF16
H15
D15
E16
F16
H16
K15
G16
E17
C17
A18
A19
G18
H18
F19
K17
A20
C20
E20
D21
A21
NA
√
IO LVDS
VREF
Total Pairs: 283, Asynchronous Output Pairs: 168
NA IO_ LVDS_DLL
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F7
G8
C4
D5
A3
4
2
-
4
4
√
√
2
2
√
√
1
1
√
√
2
2
2
4
√
VREF
-
-
2
H9
2
VREF
VREF
3
J10
D6
B4
2
-
-
4
A4
√
-
-
5
B5
E7
√
VREF
-
6
F8
A5
1
-
VREF
7
N11
E8
D7
G9
A6
1
-
-
8
√
-
-
9
J11
B7
√
VREF
-
10
11
12
13
14
15
16
17
C7
C8
G10
A8
2
-
VREF
H10
F10
H11
C9
2
-
-
-
-
-
-
-
√
-
√
VREF
D9
B9
NA
4
-
J12
A9
-
VREF
-
E10
G11
NA
NA
B10
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
XCV600E, XCV1000E, XCV1600E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
√
4
4
√
√
2
2
√
√
1
1
√
√
2
2
2
4
√
√
NA
1
4
3
4
1
√
4
1
√
√
2
4
4
4
Functions
Pair Bank
Pin
Pin
AO
4
Functions
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
A22
B22
D22
C22
E22
A23
K19
B24
G22
C25
A26
K20
J21
C21
H19
E21
F21
H20
G21
A24
C24
H21
E23
D24
B26
D25
C26
B27
A27
B28
K21
E27
D28
E25
C30
F27
J23
VREF
86
87
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
J29
K27
M22
K28
N21
L24
L29
L26
L30
M26
N29
N25
N30
N26
P29
P22
P25
R21
R25
P24
R24
R22
R23
T21
U28
T23
U25
U24
W30
U21
V26
W26
W25
V24
K24
J30
-
-
4
VREF
-
88
K29
L25
K25
L27
M23
L28
M27
M29
M30
N27
P21
P28
N24
R26
R29
R28
T30
R27
U29
T27
T28
T25
U30
U27
V27
V29
U22
W29
W27
Y29
Y30
Y28
NA
4
D2
VREF
89
-
-
90
1
-
-
91
4
-
-
92
3
-
VREF
93
4
-
-
94
1
VREF
-
95
√
-
-
96
4
-
VREF
97
1
-
-
98
√
D3
F23
G23
F24
A28
C27
J22
-
99
√
-
VREF
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
2
-
-
√
-
-
4
VREF
CS
4
-
VREF
-
DIN, D0
4
C29
G25
E28
K22
D30
L21
G28
G27
K23
F30
H27
G30
J24
-
4
-
NA
4
VREF
VREF
-
4
-
-
4
VREF
F28
E30
E29
H26
L22
G29
M21
J26
VREF
4
-
-
2
-
-
√
-
-
√
VREF
VREF
1
-
-
4
-
-
√
-
-
VREF
-
1
VREF
H30
K26
L23
J28
4
-
-
3
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
XCV600E, XCV1000E, XCV1600E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
4
Functions
Pair Bank
Pin
Pin
AO
2
Functions
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
AA30
AA29
Y27
W24
V20
-
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
AC20 AG23
-
1
-
AF22
AJ22
AE22
AG22
√
-
W23
AB30
AA28
AA27
Y23
NA
√
-
√
VREF
Y26
D5
AK24 AD20
AA19 AF21
NA
4
-
V21
√
VREF
-
Y25
4
-
AH22 AA18
AG21 AK23
AH21 AD19
NA
NA
4
VREF
W22
Y24
4
-
-
AB28
4
VREF
-
AC30 AA25
W21 AA24
AB26 AD30
Y22 AC27
√
-
AE20
AJ21
2
-
2
-
AG20 AF20
2
-
√
-
AC18
AJ20
AF19
AE19
2
-
√
VREF
√
-
AD28 AB25
AC26 AE30
AD27 AF30
2
-
AK22 AH20
AG19 AB17
√
VREF
4
-
1
-
√
-
AJ19
AD17
1
-
AF29
AB24
1
VREF
AA16 AA17
AK21 AB16
AG18 AK20
AK19 AD16
AE16 AE17
√
-
AB23 AE28
AG30 AC25
AE26 AG29
AH30 AC24
AF28 AD25
AH29 AA22
4
-
√
VREF
3
-
2
-
4
VREF
2
-
1
-
√
-
NA
√
-
AG17
AJ17
√
VREF
-
INIT
AD15 AH17
AG16 AK17
AF16 AH16
AC15 AG15
NA
4
AF27
AK28
√
-
VREF
AG26 AH27
4
-
NA IO_ LVDS_DLL
AD23
AB21
AJ27
AF25
2
-
4
√
√
√
2
2
√
√
1
1
VREF
2
VREF
AB15
AA15
AF15
AF14
-
AC22 AH26
AA21 AG25
2
-
VREF
√
-
AH15 AK15
-
AJ26
AA20 AH25
AC21 AF24
AG24 AK26
AJ24 AF23
AE23 AB20
AD22
√
VREF
AB14
AH14
AF13
AJ14
-
1
-
-
1
-
AE14 AG13
AK13 AD13
VREF
√
-
VREF
-
-
-
-
√
AE13
AF12
2
AC13 AA13
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
XCV600E, XCV1000E, XCV1600E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
√
√
2
2
2
4
√
√
4
4
√
√
2
2
√
√
1
1
√
√
2
2
2
4
√
NA
1
4
3
4
1
√
4
1
Functions
Pair Bank
Pin
Pin
AO
√
Functions
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
AA12
AJ12
VREF
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
Y9
AC4
W8
AB4
W9
W10
V10
AC1
AA3
U10
AA6
Y4
AF1
AB6
AE1
Y8
VREF
AB12 AE11
AK12 Y13
AG11 AF11
AH11 AJ11
-
√
-
-
2
-
-
4
-
-
AB3
AA5
AB1
Y7
4
VREF
AE12 AG10
AD12 AK11
-
4
-
-
4
-
AJ10
AC12
VREF
4
VREF
AK10 AD11
-
V11
AA2
W7
Y6
NA
4
-
AJ9
AH10
AH9
AF8
AC11
AK8
AG7
AJ7
AE9
AF9
AK9
AB11
AG8
AF7
AK7
AD10
AC10
AG6
AJ5
-
-
VREF
1
-
-
4
-
-
V7
AA1
Y3
3
-
-
Y2
4
-
VREF
W5
W6
W2
V4
Y5
1
VREF
-
W4
V6
√
-
-
4
-
AH6
AD9
AB10
AD8
AC9
AG5
AH5
AC6
AG2
AE4
AH1
AD6
AA10
AD4
AD2
AF2
AA7
-
U9
1
-
VREF
T8
AB2
U5
√
VREF
-
W1
T9
√
-
AK5
AJ4
-
Y1
2
-
VREF
U3
T7
4
-
AK4
AG3
AF3
AH2
AB9
AE3
AB8
AG1
AA9
AD5
AD3
AA8
-
V2
T5
4
VREF
-
-
T6
R9
4
-
U2
T4
4
VREF
-
R10
R6
T1
NA
4
-
R5
-
VREF
R4
R8
4
VREF
-
R3
R7
4
-
-
P6
P10
P5
4
VREF
VREF
P2
4
-
-
-
-
P4
P7
2
-
-
R2
N4
√
P1
N7
√
VREF
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
FG1156 Fine-Pitch Ball Grid Array Package
XCV1000E, XCV1600E, XCV2000E, XCV2600E, and
XCV3200E devices in the FG1156 fine-pitch Ball Grid Array
package have footprint compatibility. Pins labeled IO_VREF
P
N
Other
Pair Bank
Pin
Pin
AO
1
Functions
can be used as either V
or general I/O, unless indicated
REF
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
Notes:
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
N6
N1
M5
M1
L2
M6
N5
M4
M2
L4
-
in the footnotes. If the pin is not used as V , it can be used
REF
as general I/O. Immediately following Table 28, see
Table 29 for Differential Pair information.
4
-
√
-
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
1
VREF
4
-
Bank
0
Pin Description
Pin #
E17
B4
L5
M7
L1
3
-
GCK3
M8
M9
M10
K1
K3
K4
J5
4
-
0
IO
K2
L3
1
-
0
IO
B9
NA
√
-
0
IO
B10
K5
L6
-
3
0
IO
IO
D9
√
VREF
0
D16
L7
4
-
3
0
IO
E7
L8
4
-
3
0
IO
E11
H4
K7
J2
K6
H1
J7
4
VREF
3
0
IO
E13
4
-
3
0
IO
E16
2
-
3
0
IO
F17
G2
G5
K8
E1
E2
K9
F4
H5
L9
√
-
3
0
IO
J12
√
VREF
3
0
IO
J13
F3
G3
H6
E4
J8
1
-
3
0
IO
J14
4
-
3
0
IO
K11
√
-
0
IO_L0N_Y
IO_L0P_Y
IO_L1N_Y
IO_L1P_Y
IO_VREF_L2N_Y
IO_L2P_Y
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_YY
F7
H9
C5
J10
E6
D6
A4
G8
C6
J11
G9
F8
1
VREF
0
4
-
0
H7
C2
F5
D1
G6
D2
D3
3
-
0
4
VREF
0
1
-
-
0
K10
4
0
1. AO in the XCV600E, 1000E.
2. AO in the XCV1000E.
3. AO in the XCV1600E.
4. AO in the XCV1000E, XCV1600E.
0
0
0
0
0
4
0
A5
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L6P_YY
IO_L7N_Y
Pin #
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
Pin #
C12
K15
A12
B12
H14
D12
F13
A13
B13
5
H10
IO_L23P_Y
IO_L24N_Y
IO_L24P_Y
IO_L25N_Y
IO_L25P_Y
IO_L26N_YY
IO_L26P_YY
IO_VREF_L27N_YY
IO_L27P_YY
IO_L28N_YY
IO_L28P_YY
IO_L29N_Y
IO_L29P_Y
IO_L30N_Y
IO_L30P_Y
IO_L31N
D7
B5
IO_L7P_Y
IO_L8N_Y
K12
E8
IO_L8P_Y
4
IO_L9N
B6
5
IO_L9P
F9
IO_L10N_YY
IO_L10P_YY
IO_VREF_L11N_YY
IO_L11P_YY
IO_L12N
G10
C7
4
D8
J15
5
B7
G14
4
H11
C13
F14
H15
D13
5
IO_L12P
C8
IO_L13N_Y
IO_L13P_Y
IO_VREF_L14N_Y
IO_L14P_Y
IO_L15N
E9
B8
2
4
K13
A14
5
G11
IO_L31P
K16
4
A8
IO_L32N_YY
IO_L32P_YY
IO_VREF_L33N_YY
IO_L33P_YY
IO_L34N
E14
B14
G15
D14
5
IO_L15P
F10
IO_L16N_YY
IO_L16P_YY
IO_VREF_L17N_YY
IO_L17P_YY
IO_L18N_Y
IO_L18P_Y
IO_L19N_Y
IO_L19P_Y
IO_VREF_L20N_YY
IO_L20P_YY
IO_L21N_YY
IO_L21P_YY
IO_L22N_Y
IO_L22P_Y
IO_L23N_Y
C9
H12
D10
A9
4
J16
5
IO_L34P
D15
F11
A10
K14
C10
H13
G12
A11
B11
E12
D11
G13
IO_L35N_Y
IO_L35P_Y
IO_L36N_Y
IO_L36P_Y
IO_L37N
F15
B15
A15
E15
4
G16
5
IO_L37P
A16
IO_L38N_YY
IO_L38P_YY
IO_VREF_L39N_YY
IO_L39P_YY
IO_L40N_Y
F16
J17
C16
B16
H17
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
XCV2600E, XCV3200E
Bank
Pin Description
IO_L40P_Y
Pin #
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L49P_Y
IO_L50N
Pin #
0
0
0
0
A17
G20
1
5
IO_VREF_L41N_Y
IO_L41P_Y
G17
B20
4
B17
C17
IO_L50P
F20
IO_LVDS_DLL_L42N
IO_L51N_YY
IO_VREF_L51P_YY
IO_L52N_YY
IO_L52P_YY
IO_L53N
D20
E20
H20
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
D17
A18
IO
3
5
IO
B18
E21
4
IO
B24
B25
IO_L53P
J20
IO
IO_L54N_Y
IO_L54P_Y
IO_L55N_Y
IO_L55P_Y
IO_L56N_YY
IO_L56P_YY
IO_L57N_YY
IO_VREF_L57P_YY
IO_L58N_YY
IO_L58P_YY
IO_L59N_Y
IO_L59P_Y
IO_L60N_Y
IO_L60P_Y
IO_L61N_Y
IO_L61P_Y
IO_L62N_Y
IO_L62P_Y
IO_L63N_YY
IO_L63P_YY
IO_L64N_YY
IO_VREF_L64P_YY
IO_L65N_Y
IO_L65P_Y
IO_L66N_Y
D21
K20
B21
H21
3
IO
E22
3
IO
IO
E23
3
D18
5
IO
D19
G21
3
4
IO
D25
F21
3
IO
D26
A22
B22
J21
3
IO
D28
3
IO
D29
3
IO
G23
C22
D22
G22
K21
A23
F22
B23
C23
H22
D23
K22
A24
J22
3
IO
J23
IO_LVDS_DLL_L42P
IO_L43N_Y
IO_VREF_L43P_Y
IO_L44N_Y
IO_L44P_Y
IO_L45N_YY
IO_VREF_L45P_YY
IO_L46N_YY
IO_L46P_YY
IO_L47N
IO_L47P
IO_L48N_Y
IO_L48P_Y
IO_L49N_Y
J18
G18
1
C18
H18
F18
B19
A19
K19
C19
5
F19
4
E19
G19
J19
A20
H23
D24
A25
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
121
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L66P_Y
Pin #
E24
A26
C25
F24
B26
Bank
Pin Description
Pin #
B30
B31
E29
A31
D30
1
1
1
1
1
IO_L83P_Y
IO_L84N
IO_L67N_YY
IO_VREF_L67P_YY
IO_L68N_YY
IO_L68P_YY
IO_L69N
IO_L84P
IO_WRITE_L85N_YY
IO_CS_L85P_YY
5
K23
4
3
IO_L69P
F25
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
F31
IO_L70N_Y
C26
IO
J32
2
3
IO_VREF_L70P_Y
IO_L71N_Y
H24
IO
K27
3
G24
A27
IO
K31
3
IO_L71P_Y
IO
L28
5
3
IO_L72N
B27
IO
L30
4
3
IO_L72P
G25
IO
M32
IO_L73N_YY
IO_VREF_L73P_YY
IO_L74N_YY
IO_L74P_YY
IO_L75N
E26
C27
J24
B28
IO
N26
3
IO
IO
N28
3
P25
3
IO
U26
5
K24
IO
U30
4
3
IO_L75P
H25
IO
U32
IO_L76N_Y
D27
F26
G26
C28
IO
U34
M30
D32
J27
IO_L76P_Y
IO_D2
IO_L77N_Y
IO_DOUT_BUSY_L86P_YY
IO_DIN_D0_L86N_YY
IO_L87P_Y
IO_L87N_Y
IO_L88P_Y
IO_L88N_Y
IO_VREF_L89P_Y
IO_L89N_Y
IO_L90P
IO_L77P_Y
5
IO_L78N_YY
IO_L78P_YY
IO_L79N_YY
IO_VREF_L79P_YY
IO_L80N_YY
IO_L80P_YY
IO_L81N_Y
E27
E31
F30
G29
F32
E32
G30
M25
G31
L26
D33
D34
4
J25
A30
H26
G27
B29
F27
C29
E28
F28
L25
IO_L81P_Y
IO_L90N
IO_L82N_Y
IO_L91P_Y
IO_L91N_Y
IO_VREF_L92P_Y
IO_VREF_L82P_Y
IO_L83N_Y
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
XCV2600E, XCV3200E
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L92N_Y
Pin #
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L109N_Y
IO_L110P_Y
IO_L110N_Y
IO_L111P
Pin #
L33
H29
4
IO_L93P_YY
IO_L93N_YY
IO_L94P_YY
IO_L94N_YY
IO_L95P_Y
J28
P27
M33
M31
R26
N30
P28
N29
N33
5
E33
H28
H30
H32
K28
IO_L111N
IO_L112P_Y
IO_L112N_Y
IO_VREF_L113P_Y
IO_L113N_Y
IO_L114P_YY
IO_L114N_YY
IO_L115P_YY
IO_L115N_YY
IO_L116P_Y
IO_L116N_Y
IO_L117P_Y
IO_L117N_Y
IO_L118P_Y
IO_L118N_Y
IO_VREF_L119P_YY
IO_D3_L119N_YY
IO_L120P_YY
IO_L120N_YY
IO_L121P_YY
IO_L121N_YY
IO_L122P_Y
IO_L122N_Y
IO_L123P
IO_L95N_Y
4
IO_L96P_Y
L27
5
IO_L96N_Y
F33
4
IO_L97P_Y
M26
E34
H31
G32
T25
5
IO_L97N_Y
N34
IO_VREF_L98P_YY
IO_L98N_YY
IO_L99P_YY
IO_L99N_YY
IO_L100P_YY
IO_L100N_YY
IO_VREF_L101P_Y
IO_L101N_Y
IO_L102P
P34
R27
P29
P31
4
N25
5
J31
4
J30
P33
5
G33
T26
2
H34
R34
R28
N31
N32
J29
4
M27
5
IO_L102N
H33
4
IO_L103P_Y
IO_L103N_Y
IO_VREF_L104P_YY
IO_L104N_YY
IO_L105P_YY
IO_L105N_YY
IO_L106P_Y
IO_L106N_Y
IO_VREF_L107P_YY
IO_D1_L107N_YY
IO_L108P_Y
IO_L108N_Y
IO_L109P_Y
K29
J34
L29
J33
M28
K34
N27
L34
K33
P26
R25
M34
L31
P30
5
R33
R29
T34
R30
T30
4
T28
5
IO_L123N
R31
IO_L124P_Y
IO_L124N_Y
IO_VREF_L125P_YY
IO_L125N_YY
IO_L126P_YY
T29
U27
T31
T33
U28
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
123
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
Pin Description
IO_L126N_YY
IO_VREF_L127P_Y
IO_L127N_Y
Pin #
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
Pin #
5
2
2
2
2
2
T32
IO_L136P_YY
IO_L136N_YY
IO_D4_L137P_YY
IO_VREF_L137N_YY
IO_L138P_Y
AA34
1
4
U29
W31
AA33
Y29
U33
V33
U31
IO_L128P_YY
IO_L128N_YY
W25
AB34
IO_L138N_Y
3
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
V27
IO_L139P_Y
Y28
4
IO
V31
IO_L139N_Y
AB33
AA30
Y26
3
IO
V32
IO_L140P_Y
IO
W33
IO_L140N_Y
3
IO
IO
AB25
AB26
AB31
AC31
IO_L141P_YY
IO_L141N_YY
IO_L142P_YY
IO_L142N_YY
IO_L143P_Y
Y27
3
3
3
AA31
5
IO
AA27
AA29
4
IO
IO
AF34
AB32
AB29
AA28
AC34
Y25
3
IO
AG31
AG33
IO_VREF_L143N_Y
IO_L144P_Y
3
IO
IO
AG34
IO_L144N_Y
3
IO
AH29
IO_L145P
3
IO
AJ30
V26
IO_L145N
AD34
AB30
AC33
AA26
AC32
AD33
AB28
AE34
AB27
AE33
AC30
AA25
AE32
AE31
AD29
IO_L129P_Y
IO_VREF_L129N_Y
IO_L130P_YY
IO_L130N_YY
IO_L131P_YY
IO_VREF_L131N_YY
IO_L132P_Y
IO_L132N_Y
IO_L133P
IO_L133N
IO_L134P_Y
IO_L134N_Y
IO_L135P_YY
IO_L135N_YY
IO_L146P_Y
1
V30
W34
V28
W32
W30
V29
Y34
IO_L146N_Y
IO_L147P_Y
IO_L147N_Y
IO_L148P_Y
IO_L148N_Y
IO_L149P_YY
IO_D5_L149N_YY
IO_D6_L150P_YY
IO_VREF_L150N_YY
IO_L151P_Y
5
W29
4
Y33
W26
W28
Y31
Y30
IO_L151N_Y
IO_L152P_YY
IO_L152N_YY
Module 4 of 4
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DS022-4 (v2.5) March 14, 2003
Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
XCV2600E, XCV3200E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L153P_YY
IO_VREF_L153N_YY
IO_L154P_Y
Pin #
AD31
AF33
AC28
AF31
Bank
Pin Description
IO_L170P_Y
Pin #
AK33
AH30
AK32
AK31
V34
3
3
3
3
3
IO_L170N_Y
IO_D7_L171P_YY
IO_INIT_L171N_YY
IO
IO_L154N_Y
5
IO_L155P_Y
AC27
4
IO_L155N_Y
AF32
IO_L156P_Y
AE29
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
AH18
2
3
IO_VREF_L156N_Y
IO_L157P_YY
IO_L157N_YY
IO_L158P_YY
IO_L158N_YY
IO_L159P_YY
IO_VREF_L159N_YY
IO_L160P_Y
AD28
AD30
AG32
IO
AE21
AG18
AG23
IO
IO
5
3
AC26
AH33
IO
AH24
AH25
4
3
IO
IO
3
AD26
AF30
AC25
AH32
AJ28
AK18
AK19
3
3
IO
IO
IO_L160N_Y
IO
AL25
5
3
IO_L161P_Y
AE28
IO
AL27
AL30
4
3
IO_L161N_Y
AL34
AG30
AD27
AF29
AK34
IO
IO_L162P_Y
IO
AN18
3
IO_L162N_Y
IO
AN22
AN24
3
IO_L163P_YY
IO_L163N_YY
IO_L164P_YY
IO_L164N_YY
IO_L165P_Y
IO
IO_L172P_YY
IO_L172N_YY
IO_L173P_Y
IO_L173N_Y
IO_L174P_Y
IO_L174N_Y
IO_VREF_L175P_Y
IO_L175N_Y
IO_L176P_Y
IO_L176N_Y
IO_L177P_YY
IO_L177N_YY
IO_VREF_L178P_YY
AP31
AK29
AP30
AN31
AH27
AN30
AM30
AK28
AG26
AN29
AF25
AM29
AL29
5
AD25
4
AE27
AJ33
AH31
AE26
AL33
AF28
AL32
AJ31
AF27
AG29
AJ32
IO_VREF_L165N_Y
IO_L166P_Y
IO_L166N_Y
IO_L167P
IO_L167N
IO_L168P_Y
IO_VREF_L168N_Y
IO_L169P_Y
IO_L169N_Y
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
125
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L178N_YY
IO_L179P_YY
IO_L179N_YY
IO_L180P_Y
IO_L180N_Y
IO_L181P_Y
IO_L181N_Y
IO_L182P
Pin #
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
Pin #
AN23
AP23
AM23
AH22
AP22
AL23
AF21
AL22
AJ22
AK22
AM22
AL28
IO_L195N_Y
IO_L196P_Y
IO_L196N_Y
IO_L197P_Y
IO_L197N_Y
IO_L198P_Y
IO_L198N_Y
IO_L199P_YY
IO_L199N_YY
IO_VREF_L200P_YY
IO_L200N_YY
IO_L201P_YY
IO_L201N_YY
IO_L202P_Y
IO_L202N_Y
IO_L203P_Y
IO_L203N_Y
IO_L204P
4
AE24
5
AN28
AJ27
AH26
AG25
AK27
4
AM28
5
IO_L182N
AF24
AJ26
AP27
AK26
AN27
IO_L183P_YY
IO_L183N_YY
IO_VREF_L184P_YY
IO_L184N_YY
IO_L185P
4
AG21
5
AJ21
AP21
AE20
AH21
AL21
4
AE23
5
IO_L185N
AM27
IO_L186P_Y
IO_L186N_Y
IO_VREF_L187P_Y
IO_L187N_Y
IO_L188P
AL26
AP26
2
4
AN26
AN21
5
AJ25
IO_L204N
AF20
AK21
AP20
AE19
AN20
4
AG24
IO_L205P_YY
IO_L205N_YY
IO_VREF_L206P_YY
IO_L206N_YY
IO_L207P_Y
IO_L207N_Y
IO_L208P_Y
IO_L208N_Y
IO_L209P_Y
IO_L209N_Y
IO_L210P
5
IO_L188N
AP25
AF23
AM26
AJ24
AN25
AE22
AM25
AK24
AH23
AF22
AP24
AL24
AK23
AG22
IO_L189P_YY
IO_L189N_YY
IO_VREF_L190P_YY
IO_L190N_YY
IO_L191P_Y
IO_L191N_Y
IO_L192P_Y
IO_L192N_Y
IO_VREF_L193P_YY
IO_L193N_YY
IO_L194P_YY
IO_L194N_YY
IO_L195P_Y
4
AG20
5
AL20
AH20
AK20
AN19
AJ20
4
AF19
5
IO_L210N
AP19
IO_L211P_YY
IO_L211N_YY
IO_VREF_L212P_YY
AM19
AH19
AJ19
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
XCV2600E, XCV3200E
Bank
Pin Description
IO_L212N_YY
Pin #
AP18
AF18
AP17
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L222P_Y
Pin #
AN15
AF16
4
4
4
4
4
4
IO_L213P_Y
IO_L222N_Y
IO_L223P_Y
5
IO_L213N_Y
AP14
AE16
1
4
IO_VREF_L214P_Y
IO_L214N_Y
AJ18
AL18
AM18
IO_L223N_Y
IO_L224P_YY
IO_VREF_L224N_YY
IO_L225P_YY
IO_L225N_YY
IO_L226P
AK15
AJ15
AH15
AN14
IO_LVDS_DLL_L215P
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
AL19
3
5
IO
AF17
AK14
AG15
3
4
IO
AG12
IO_L226N
IO
AH12
IO_L227P_Y
AM13
AF15
AG14
AP13
3
IO
AJ10
IO_L227N_Y
IO_L228P_Y
3
IO
AJ11
3
IO
IO
AK7
IO_L228N_Y
IO_L229P_YY
IO_L229N_YY
IO_L230P_YY
IO_VREF_L230N_YY
IO_L231P_YY
IO_L231N_YY
IO_L232P_Y
3
5
AK13
AE14
AE15
3
4
IO
AL13
3
IO
AM4
AN13
AG13
AH14
AP12
AJ14
AL14
AF13
AN12
AF14
AP11
AN11
AH13
AM12
AL12
AJ13
AP10
AK12
AM10
IO
AN9
3
IO
AN10
IO
AN16
3
IO
AN17
IO_LVDS_DLL_L215N
IO_L216P_Y
IO_VREF_L216N_Y
IO_L217P_Y
IO_L217N_Y
IO_L218P_YY
IO_VREF_L218N_YY
IO_L219P_YY
IO_L219N_YY
IO_L220P
IO_L220N
IO_L221P_Y
IO_L221N_Y
AL17
AH17
IO_L232N_Y
IO_L233P_Y
1
AM17
IO_L233N_Y
IO_L234P_Y
AJ17
AG17
AP16
AL16
AJ16
AM16
IO_L234N_Y
IO_L235P_Y
IO_L235N_Y
IO_L236P_YY
IO_L236N_YY
IO_L237P_YY
IO_VREF_L237N_YY
IO_L238P_Y
5
AK16
4
AP15
AL15
AH16
IO_L238N_Y
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
127
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L239P_Y
Pin #
AP9
Bank
Pin Description
Pin #
AH8
AP4
AN4
AJ7
5
5
5
5
5
5
IO_L256P_Y
IO_L256N_Y
IO_L257P_Y
IO_L257N_Y
IO_L258P_YY
IO_L258N_YY
IO_L239N_Y
AK11
AL11
AL10
AE13
AM9
IO_L240P_YY
IO_VREF_L240N_YY
IO_L241P_YY
IO_L241N_YY
IO_L242P
AM5
AK6
5
AF12
4
IO_L242N
AP8
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
T1
V2
V3
IO_L243P_Y
AL9
IO
2
IO_VREF_L243N_Y
IO_L244P_Y
AH11
IO
3
AF11
AN8
IO
V5
3
IO_L244N_Y
IO
V8
5
3
IO_L245P_Y
AM8
IO
IO
AA10
4
3
IO_L245N_Y
AG11
AL8
AB5
AB7
AB9
3
3
3
IO_L246P_YY
IO_VREF_L246N_YY
IO_L247P_YY
IO_L247N_YY
IO_L248P
IO
AK9
IO
AH10
AN7
IO
AD7
AD8
3
IO
5
AE12
IO
AE2
AE4
4
IO_L248N
AJ9
IO
3
IO_L249P_Y
AM7
AL7
IO
AJ4
3
IO_L249N_Y
IO
AH5
IO_L250P_Y
AG10
AN6
IO_L259N_YY
IO_L259P_YY
IO_L260N_Y
IO_L260P_Y
IO_L261N_Y
IO_L261P_Y
IO_VREF_L262N_Y
IO_L262P_Y
IO_L263N
IO_L263P
IO_L264N_Y
IO_L264P_Y
AH6
AF8
AE9
AK3
AD10
AL2
AL1
AH4
AG6
AK1
AF7
AK2
IO_L250N_Y
5
IO_L251P_YY
IO_L251N_YY
IO_L252P_YY
IO_VREF_L252N_YY
IO_L253P_YY
IO_L253N_YY
IO_L254P_Y
AK8
4
AH9
AP5
AJ8
AE11
AN5
AF10
AM6
AL6
IO_L254N_Y
IO_L255P_Y
IO_VREF_L255N_Y
AG9
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
XCV2600E, XCV3200E
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_VREF_L265N_Y
IO_L265P_Y
Pin #
AJ3
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L282N_Y
IO_L282P_Y
IO_L283N_Y
IO_L283P_Y
IO_L284N_Y
IO_L284P_Y
IO_L285N
Pin #
AA9
AC3
AC4
AD4
AA8
AB6
AB1
Y10
AB2
AA7
AA4
AA1
AG5
4
IO_L266N_YY
IO_L266P_YY
IO_L267N_YY
IO_L267P_YY
IO_L268N_Y
AD9
5
AJ2
AC10
AH2
AH3
AF5
IO_L268P_Y
IO_L285P
4
IO_L269N_Y
AE8
IO_L286N_Y
IO_L286P_Y
IO_VREF_L287N_Y
IO_L287P_Y
IO_L288N_YY
IO_L288P_YY
IO_L289N_YY
IO_L289P_YY
IO_L290N_Y
IO_L290P_Y
IO_L291N_Y
IO_L291P_Y
IO_L292N_Y
IO_L292P_Y
IO_VREF_L293N_YY
IO_L293P_YY
IO_L294N_YY
IO_L294P_YY
IO_L295N_YY
IO_L295P_YY
IO_L296N_Y
IO_L296P_Y
IO_L297N_Y
IO_L297P_Y
IO_L298N_Y
IO_L298P_Y
5
IO_L269P_Y
AG3
IO_L270N_Y
AE7
AG2
AF6
AG1
IO_L270P_Y
4
IO_VREF_L271N_YY
IO_L271P_YY
IO_L272N_YY
IO_L272P_YY
IO_L273N_YY
IO_L273P_YY
IO_VREF_L274N_Y
IO_L274P_Y
Y9
5
AB4
4
AC9
AA2
Y8
5
AG4
AE6
AF3
AA6
AA5
2
4
AF1
AB3
5
AF4
Y7
4
IO_L275N
AB10
Y1
W10
Y5
5
IO_L275P
AF2
AC8
AE1
AD5
AE3
AC7
AD1
AD6
AD2
AB8
AC1
AC5
AC2
IO_L276N_Y
IO_L276P_Y
Y2
4
IO_VREF_L277N_YY
IO_L277P_YY
IO_L278N_YY
IO_L278P_YY
IO_L279N_Y
W9
5
W2
W7
Y4
W1
Y6
IO_L279P_Y
4
IO_VREF_L280N_YY
IO_L280P_YY
IO_L281N_YY
IO_L281P_YY
W6
5
W3
V9
W4
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
129
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
Pin Description
IO_VREF_L299N_YY
IO_L299P_YY
Pin #
W5
V1
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
Pin #
4
6
6
6
6
6
6
IO_L307P_Y
IO_L308N_Y
IO_L308P_Y
IO_L309N_YY
IO_L309P_YY
IO_L310N_YY
IO_VREF_L310P_YY
IO_L311N_Y
IO_L311P_Y
IO_L312N_Y
IO_L312P_Y
IO_L313N_Y
IO_L313P_Y
IO_L314N_YY
IO_L314P_YY
IO_L315N_YY
IO_L315P_YY
IO_L316N_Y
IO_VREF_L316P_Y
IO_L317N_Y
IO_L317P_Y
IO_L318N
R1
R6
T10
R2
R5
P1
P5
R8
P2
IO_L300N_YY
V7
IO_L300P_YY
U2
1
IO_VREF_L301N_Y
IO_L301P_Y
V6
U1
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
F5
3
IO
G6
5
IO
H1
R9
3
4
IO
H7
N1
3
IO
K2
P4
R10
P8
3
IO
K4
3
IO
L6
3
IO
M5
N2
3
5
IO
IO
M10
P6
3
4
N5
P7
IO
N10
M1
N4
N6
N3
P9
M2
N7
M3
P10
M4
L1
4
IO
R7
IO
T2
3
IO
T7
IO
U8
3
IO
V4
IO_L318P
IO_L302N_YY
IO_L302P_YY
IO_L303N_Y
IO_VREF_L303P_Y
IO_L304N_YY
IO_L304P_YY
IO_L305N_YY
IO_VREF_L305P_YY
IO_L306N_Y
IO_L306P_Y
IO_L307N_Y
U9
U4
U7
IO_L319N_Y
IO_L319P_Y
IO_L320N_Y
IO_L320P_Y
IO_L321N_Y
IO_L321P_Y
IO_L322N_YY
IO_L322P_YY
IO_L323N_YY
IO_VREF_L323P_YY
IO_L324N_Y
1
U5
U3
U6
T3
T6
T9
T4
N8
L2
N9
M7
K1
M8
5
T5
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Production Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
XCV2600E, XCV3200E
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L324P_Y
Pin #
L4
Bank
Pin Description
IO_VREF_L341P_Y
IO_L342N_Y
Pin #
J8
7
7
7
7
7
IO_L325N_YY
IO_L325P_YY
IO_L326N_YY
IO_VREF_L326P_YY
IO_L327N_Y
J1
E4
L5
IO_L342P_Y
D2
F4
J2
IO_L343N_Y
K3
L7
IO_L343P_Y
D3
IO_L327P_Y
J3
2
CCLK
DONE
DXN
C31
AM31
AJ5
AL5
AK4
AG7
AL3
AG28
D5
5
IO_L328N_Y
M9
3
4
IO_L328P_Y
H2
NA
NA
NA
NA
NA
NA
NA
NA
2
IO_L329N_Y
J4
DXP
2
IO_VREF_L329P_Y
IO_L330N_YY
IO_L330P_YY
IO_L331N_YY
IO_L331P_YY
IO_L332N_YY
IO_VREF_L332P_YY
IO_L333N_Y
K6
M0
L8
M1
G2
M2
5
H3
PROGRAM
TCK
4
K7
G3
J5
TDI
C30
K26
C4
TDO
L9
H5
NA
TMS
IO_L333P_Y
5
IO_L334N_Y
J6
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
K10
K17
K18
K25
L11
L24
M12
M23
N13
N14
N15
N16
N19
N20
N21
4
IO_L334P_Y
H4
IO_L335N_Y
G4
K8
J7
IO_L335P_Y
IO_L336N_YY
IO_L336P_YY
IO_L337N_YY
IO_L337P_YY
IO_L338N_Y
F2
5
F3
4
L10
E1
H6
G5
E2
K9
D1
E3
IO_VREF_L338P_Y_Y
IO_L339N_Y
IO_L339P_Y
IO_L340N
IO_L340P
IO_L341N_Y
DS022-4 (v2.5) March 14, 2003
Production Product Specification
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Module 4 of 4
131
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
N22
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
Pin #
M17
L17
L16
E10
C14
A6
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
P13
P22
R13
R22
T13
T22
M13
M14
M15
M16
L12
L13
L14
L15
M18
L18
L23
E25
C21
A29
M19
M20
M21
M22
L19
L20
L21
L22
U24
U23
N24
M24
K30
F34
U10
U25
V10
V25
W13
W22
Y13
Y22
AA13
AA22
AB13
AB14
AB15
AB16
AB19
AB20
AB21
AB22
AC12
AC23
AD24
AD11
AE10
AE17
AE18
AE25
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Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
XCV2600E, XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
Pin #
T23
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin #
AD22
AD23
AC17
AD17
AC13
AC14
AC15
AC16
AP6
T24
R23
R24
P23
P24
P32
N23
V23
V24
AM14
AK10
AD12
AD13
AD14
AD15
AD16
V11
Y23
Y24
W23
W24
AJ34
AE30
AC24
AB23
AB24
AA23
AA24
AA32
AD18
AC18
AC19
AC20
AC21
AC22
AP29
AM21
AK25
AD19
AD20
AD21
V12
Y11
Y12
W11
W12
AJ1
AE5
AC11
AB11
AB12
AA3
AA11
AA12
U11
U12
N12
M11
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin #
K5
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
Pin #
AK17
AH34
AC6
AA21
Y21
W20
V20
U21
T21
R20
P20
H16
F23
C3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F1
T11
T12
R11
R12
P3
P11
P12
N11
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K32
R4
AN1
AM11
AK5
AH28
AD32
AA20
Y20
W19
V19
U20
T20
R19
P19
H8
B2
A28
AP34
AM3
AL31
AH7
AD3
AA19
Y19
W18
V18
U19
T19
R18
P18
J26
F12
C2
B1
A7
F6
AP1
AN2
AM15
C1
C34
A3
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
XCV2600E, XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
AP2
AN3
AM20
AK30
AG8
AC29
Y3
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
E5
C15
B32
A33
AP7
AN33
AM32
AJ12
AG19
AA15
Y15
Y32
W21
V21
T8
T27
W14
V14
R21
P21
H19
F29
U15
T15
R14
P14
C11
B3
M29
G1
A32
AP3
AN32
AM24
AJ6
E18
C20
B33
A34
AG16
AA14
Y14
W8
AP28
AN34
AM33
AJ23
AG27
AA16
Y16
W27
U14
T14
R3
W15
V15
R32
M6
U16
T16
H27
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Module 4 of 4
135
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
R15
P15
L3
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
Pin #
U18
T18
R17
P17
J9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
G7
E30
C24
B34
AP32
AM1
AM34
AJ29
AF9
AA17
Y17
W16
V16
U17
T17
G34
D31
C33
A2
AB17
AB18
N17
N18
U13
V13
U22
V22
Notes:
1. VREF or I/O option only in the XCV1600E, XCV2000E,
XCV2600E, and XCV3200E; otherwise, I/O option only.
R16
P16
L32
2. VREF or I/O option only in the XCV2000E, XCV2600E, and
XCV3200E; otherwise, I/O option only.
3. No Connect in the XCV1000E, XCV1600E.
4. No Connect in the XCV1000E.
5. I/O in the XCV1000E.
G28
D4
C32
A1
AP33
AM2
AL4
AH1
AF26
AA18
Y18
W17
V17
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Production Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
FG1156 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. The
AO column in Table 29 indicates which devices in this pack-
age can use the pin pair as an asynchronous output. The
“Other Functions” column indicates alternative function(s)
that are not available when the pair is used as a differential
pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
3200 2000
1000
13
0
B8
E9
-
3200 2000
1000
14
15
0
0
G11
F10
K13
A8
VREF
-
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
3200 2600
P
N
Other
3200 2600
2000 1600
1000
Pair Bank
Pin
Pin
AO
Functions
16
17
0
0
H12
A9
C9
-
GCLK LVDS
3200 2600
2000 1600
1000
3
2
1
0
0
1
5
4
E17
D17
C17
J18
NA
NA
NA
NA
IO_DLL_L 42N
IO_DLL_L 42P
IO_DLL_L 215N
IO_DLL_L 215P
D10
VREF
AL19 AL17
AH18 AM18
2600 1600
1000
18
19
0
0
A10
C10
F11
K14
-
-
2600 1600
1000
IO LVDS
Total Pairs: 344, Asynchronous Output Pairs: 134
3200 1600
3200 2600
2000 1600
1000
20
21
0
0
G12
B11
H13
A11
VREF
-
0
1
2
3
0
0
0
0
H9
J10
D6
F7
C5
E6
A4
-
1000
3200 2000
1000
3200 2600
2000 1600
1000
-
VREF
-
3200 2000
1000
3200 1600
1000
22
23
24
25
0
0
0
0
D11
C12
A12
H14
E12
G13
K15
B12
-
-
-
-
3200 2600
1000
G8
3200 2000
1000
3200 2600
2000 1600
1000
4
5
0
0
J11
F8
C6
G9
-
3200 2000
1000
3200 2600
2000 1600
1000
3200 2600
1000
VREF
3200 2600
2000 1600
1000
6
7
8
9
0
0
0
0
H10
B5
A5
D7
2000 1600
3200 1000
3200 1000
3200 2600
-
-
-
-
26
27
0
0
F13
B13
D12
A13
-
3200 2600
2000 1600
1000
E8
K12
B6
VREF
F9
3200 2600
2000 1600
1000
28
29
0
0
G14
F14
J15
2000 1600
-
-
10
0
C7
G10
-
3200 2600
1000
C13
3200 2600
2000 1600
1000
3200 2600
1000
11
12
0
0
B7
C8
D8
VREF
-
30
31
0
0
D13
K16
H15
A14
-
-
3200
H11
3200 1600
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
32
33
0
0
B14
D14
E14
G15
-
52
1
A21
H20
-
3200 2600
2000 1600
1000
53
54
1
1
J20
K20
E21
D21
3200
-
-
VREF
3200 2600
1000
34
35
0
0
D15
B15
J16
F15
3200 1600
-
-
3200 2600
1000
55
56
1
1
H21
F21
B21
G21
-
-
3200 2000
1000
2000 1600
3200 2000
1000
36
37
0
0
E15
A16
A15
G16
-
-
3200 2600
2000 1600
1000
57
58
1
1
B22
C22
A22
J21
VREF
-
3200 2600
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
38
0
J17
F16
-
3200 2600
2000 1600
1000
3200 2600
1000
59
60
61
62
1
1
1
1
G22
A23
B23
H22
D22
K21
F22
C23
-
-
-
-
39
40
0
0
B16
A17
C16
H17
VREF
-
3200 2000
1000
2600 1600
1000
3200 2000
1000
2600 1600
1000
41
42
43
0
1
1
B17
J18
C18
G17
C17
G18
VREF
IO_LVDS_DLL
VREF
3200 1600
1000
None
2600 1600
1000
3200 2600
2000 1600
1000
63
64
1
1
K22
J22
D23
A24
-
2600 1600
1000
44
45
1
1
F18
A19
H18
B19
-
3200 2600
2000 1600
1000
VREF
3200 2600
2000 1600
1000
VREF
2600 1600
1000
65
66
1
1
D24
E24
H23
A25
-
-
3200 2600
2000 1600
1000
46
1
C19
K19
-
2600 1600
1000
47
48
1
1
E19
J19
F19
G19
3200 2600
-
-
3200 2600
2000 1600
1000
67
68
1
1
C25
B26
A26
F24
VREF
-
3200 2000
1000
3200 2600
2000 1600
1000
3200 2000
1000
49
50
1
1
G20
F20
A20
B20
-
-
3200 1600
69
70
1
1
F25
H24
K23
C26
3200 2600
-
3200 2600
2000 1600
1000
3200 2000
1000
51
1
E20
D20
VREF
VREF
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
3200 2000
1000
3200 2600
1600 1000
71
72
1
1
A27
G25
G24
B27
-
-
91
92
93
2
2
2
L26
D34
J28
D33
H29
E33
-
VREF
-
3200 1600
2600 2000
1000
3200 2600
2000 1600
1000
73
74
1
1
C27
B28
E26
J24
VREF
-
3200 2600
2000 1600
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
94
2
H28
H30
-
75
76
77
78
1
1
1
1
H25
F26
C28
J25
K24
D27
G26
E27
3200 2600
3200 1000
3200 1000
2000 1600
-
-
-
-
3200 2600
1600 1000
95
96
97
2
2
2
H32
L27
M26
K28
F33
E34
-
-
-
3200 2600
2000
2600 2000
1000
3200 2600
2000 1600
1000
79
80
1
1
H26
B29
A30
G27
VREF
-
3200 2600
2000 1600
1000
98
99
2
2
2
H31
N25
J30
G32
J31
VREF
3200 2600
2000 1600
1000
2000 1600
-
-
3200 2600
2000 1600
1000
3200 2600
1000
81
82
83
84
1
1
1
1
C29
F28
B30
E29
F27
E28
L25
B31
-
100
G33
3200 2000
1000
VREF
101
102
2
2
H34
M27
J29
2600 1000
VREF
-
3200 2600
1600
3200 2000
1000
H33
-
-
3200 2600
1600 1000
3200 1600
1000
103
104
2
2
K29
L29
J34
J33
-
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
VREF
85
86
1
2
D30
D32
A31
J27
CS
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
105
2
M28
K34
-
DIN, D0
3200 1600
1000
3200 2600
2000
106
107
2
2
N27
K33
L34
P26
-
87
88
2
2
E31
G29
F30
F32
-
-
2000 1600
1000
2600 2000
1000
D1
3200 2600
2000
3200 2600
1600 1000
108
109
110
2
2
2
R25
L31
P27
M34
L33
-
-
-
89
90
2
2
E32
M25
G30
G31
VREF
-
2000 1000
2600 1600
3200 2600
1600 1000
M33
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
111
112
2
2
M31
N30
R26
P28
2600 1600
-
-
3200 2600
1600 1000
132
3
V29
Y34
-
3200 1600
1000
133
134
3
3
W29
W26
Y33
3200 1600
1000
-
-
2600 2000
1000
W28
113
114
2
2
N29
T25
N33
N34
VREF
-
3200 2600
2000 1600
1000
3200 2600
2000 1600
135
3
Y31
Y30
-
3200 2600
2000 1600
1000
136
137
3
3
AA34 W31
AA33 Y29
2000 1600
-
115
2
P34
R27
-
2000 1600
1000
VREF
3200 2600
1600 1000
116
117
118
2
2
2
P29
P33
R34
P31
T26
R28
-
-
-
2600 2000
1000
138
139
140
3
3
3
W25 AB34
-
-
-
3200 2600
2000
3200 2600
2000
Y28
AB33
Y26
2600 2000
1000
3200 2600
1600 1000
AA30
2000 1600
1000
119
120
2
2
N31
P30
N32
R33
D3
-
3200 2600
2000 1600
1000
141
3
Y27
AA31
-
2000 1600
3200 2600
2000 1600
1000
3200 2600
2000 1600
142
143
3
3
AA27 AA29
AB32 AB29
-
121
2
R29
T34
-
2600 2000
1000
VREF
122
123
2
2
R30
T28
T30
R31
1000
-
-
3200 1600
3200 1600
1000
144
145
146
147
148
3
3
3
3
3
AA28 AC34
Y25 AD34
AB30 AC33
AA26 AC32
AD33 AB28
-
-
-
-
-
3200 2600
1600 1000
124
125
126
127
2
2
2
2
T29
T31
U28
U29
U27
T33
T32
U33
-
2600 1600
2000 1600
1000
3200 2600
1600 1000
VREF
-
2000 1600
1000
2000 1000
3200 2600
2000
3200 2600
1600 1000
VREF
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
149
3
AE34 AB27
D5
128
2
V33
U31
-
2000 1600
1000
150
151
3
3
AE33 AC30
AA25 AE32
VREF
-
3200 2600
1600 1000
129
130
131
3
3
3
V26
W34
W32
V30
V28
W30
VREF
-
3200 1600
1000
2000 1600
1000
3200 2600
2000 1600
1000
2000 1600
1000
152
3
AE31 AD29
-
VREF
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Table 29: FG1156 Differential Pin Pair Summary:
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
153
154
3
3
AD31 AF33
AC28 AF31
VREF
-
172
4
AP31 AK29
-
3200 2600
1600 1000
3200 1600
1000
173
174
175
176
4
4
4
4
AP30 AN31
AH27 AN30
AM30 AK28
AG26 AN29
-
3200 2600
1600
3200 2000
1000
155
156
3
3
AC27 AF32
AE29 AD28
-
-
VREF
-
2600 1000
VREF
3200 2000
1000
3200 2600
2000 1600
1000
157
158
159
3
3
3
AD30 AG32
AC26 AH33
AD26 AF30
-
-
3200 2600
1000
2000 1600
3200 2600
2000 1600
1000
177
178
4
4
AF25 AM29
AL29 AL28
-
3200 2600
2000 1600
1000
VREF
3200 2600
2000 1600
1000
VREF
2600 2000
1000
160
161
162
3
3
3
AC25 AH32
AE28 AL34
AG30 AD27
-
-
-
179
180
181
182
4
4
4
4
AE24 AN28
AJ27 AH26
AG25 AK27
AM28 AF24
2000 1600
3200 1000
3200 1000
3200 2600
-
-
-
-
3200 2600
2000
3200 2600
1600 1000
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
163
3
AF29 AK34
-
183
184
4
4
AJ26 AP27
AK26 AN27
-
3200 2600
2000 1600
164
165
3
3
AD25 AE27
AJ33 AH31
-
3200 2600
2000 1600
1000
VREF
2600 2000
1000
VREF
185
186
4
4
AE23 AM27
AL26 AP26
3200 1600
-
-
3200 2600
1600 1000
166
167
168
3
3
3
AE26 AL33
AF28 AL32
AJ31 AF27
-
-
3200 2000
1000
2600 1600
3200 2000
1000
187
188
4
4
AN26 AJ25
AG24 AP25
VREF
-
3200 2600
1600 1000
VREF
3200 2600
2600 2000
1000
169
170
3
3
AG29 AJ32
AK33 AH30
-
-
3200 2600
2000 1600
1000
189
4
AF23 AM26
-
3200 2600
2000
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
190
191
4
4
AJ24 AN25
AE22 AM25
VREF
-
171
3
AK32 AK31
INIT
2600 1600
1000
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Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
2600 1600
1000
3200 2600
2000 1600
1000
192
193
4
4
AK24 AH23
AF22 AP24
-
211
4
AM19 AH19
-
3200 2600
2000 1600
1000
VREF
3200 2600
2000 1600
1000
212
213
4
4
AJ19 AP18
AF18 AP17
VREF
-
3200 2600
2000 1600
1000
194
4
AL24 AK23
-
2600 1600
1000
3200 1600
1000
2600 1600
1000
195
196
197
198
4
4
4
4
AG22 AN23
AP23 AM23
AH22 AP22
AL23 AF21
-
-
-
-
214
215
216
4
5
5
AJ18 AL18
AM18 AL17
AH17 AM17
VREF
IO_LVDS_DLL
VREF
3200 2000
1000
None
2600 1600
1000
3200 2000
1000
2600 1600
1000
217
218
5
5
AJ17 AG17
AP16 AL16
-
3200 2600
1000
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
VREF
199
200
4
4
AL22 AJ22
AK22 AM22
-
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
219
5
AJ16 AM16
-
VREF
220
221
5
5
AK16 AP15
AL15 AH16
3200 2600
-
-
201
202
4
4
AG21 AJ21
AP21 AE20
2000 1600
-
-
3200 2000
1000
3200 2600
1000
3200 2000
1000
222
223
5
5
AN15 AF16
AP14 AE16
-
-
3200 2600
1000
203
204
4
4
AH21 AL21
AN21 AF20
-
-
3200 1600
3200
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
224
225
5
5
AK15 AJ15
AH15 AN14
VREF
-
205
206
4
4
AK21 AP20
AE19 AN20
-
3200 2600
2000 1600
1000
3200 2600
2000 1600
1000
VREF
226
227
5
5
AK14 AG15
AM13 AF15
3200
-
-
207
208
4
4
AG20 AL20
AH20 AK20
3200 1600
-
-
3200 2600
1000
3200 2000
1000
3200 2600
1000
228
229
5
5
AG14 AP13
AE14 AE15
-
-
3200 2000
1000
209
210
4
4
AN19 AJ20
AF19 AP19
-
-
2000 1600
3200 2600
3200 2600
2000 1600
1000
230
5
AN13 AG13
VREF
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Table 29: FG1156 Differential Pin Pair Summary:
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
3200 2600
2000 1600
1000
251
5
AK8
AH9
2000 1600
-
231
5
AH14 AP12
-
3200 2600
2000 1600
1000
252
5
AP5
AJ8
VREF
3200 2600
1000
232
233
234
235
5
5
5
5
AJ14 AL14
AF13 AN12
AF14 AP11
AN11 AH13
-
-
-
-
3200 2600
2000 1600
1000
3200 2000
1000
253
5
AE11 AN5
AF10 AM6
-
3200 2000
1000
3200 2600
1000
254
255
256
257
5
5
5
5
-
3200 1600
1000
3200 2000
1000
AL6
AH8
AN4
AG9
AP4
AJ7
VREF
3200 2600
2000 1600
1000
3200 2000
1000
-
-
236
237
5
5
AM12 AL12
AJ13 AP10
-
3200 1600
1000
3200 2600
2000 1600
1000
VREF
3200 2600
2000 1600
1000
258
259
5
6
AM5
AK6
-
-
2600 1600
1000
238
239
5
5
AK12 AM10
AP9 AK11
-
-
3200 2600
2000 1600
1000
2600 1600
1000
AF8
AK3
AH6
AE9
3200 2600
2000 1600
1000
3200 2600
2000
260
261
6
6
-
-
240
241
5
5
AL11 AL10
AE13 AM9
VREF
-
2600 2000
1000
AL2 AD10
3200 2600
2000 1600
1000
3200 2600
1600 1000
262
263
264
6
6
6
AH4
AK1
AK2
AL1
AG6
AF7
VREF
242
243
5
5
AF12 AP8
AL9 AH11
3200 2600
-
2600 1600
-
-
3200 2000
1000
VREF
3200 2600
1600 1000
3200 2000
1000
244
245
5
5
AF11 AN8
AM8 AG11
-
-
2600 2000
1000
265
266
6
6
AG5
AJ2
AJ3
VREF
-
3200 1600
3200 2600
2000 1600
AD9
3200 2600
2000 1600
1000
246
247
5
5
AL8
AK9
VREF
-
3200 2600
2000 1600
1000
267
6
AH2 AC10
-
3200 2600
2000 1600
1000
AH10 AN7
3200 2600
1600 1000
268
269
6
6
AF5
AG3
AH3
AE8
-
-
248
249
250
5
5
5
AE12
AM7
AJ9
AL7
3200 2600
3200 1000
3200 1000
-
-
-
3200 2600
2000
AG10 AN6
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Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
2600 2000
1000
3200 2600
1600 1000
270
6
AG2
AE7
-
290
291
292
6
6
6
AA5
Y7
AA6
AB3
Y1
-
-
-
3200 2600
2000 1600
1000
3200 2600
2000
271
272
273
6
6
6
AG1
AG4
AF3
AF4
AF6
AC9
AE6
AF1
VREF
2600 2000
1000
W10
2000 1600
-
-
3200 2600
2000 1600
1000
2000 1600
1000
293
294
6
6
Y2
Y5
VREF
-
W2
W9
2000 1600
274
275
6
6
2600 1000
VREF
-
3200 2600
2000 1600
1000
3200 2600
1600
295
6
Y4
W7
-
AF2 AB10
3200 2600
1600 1000
296
297
6
6
Y6
W1
W6
1000
-
-
276
277
6
6
AE1
AE3
AC8
AD5
-
W3
3200 1600
3200 2600
2000 1600
1000
3200 2600
1600 1000
VREF
298
299
300
301
6
6
6
6
W4
V1
U2
U1
V9
W5
V7
V6
-
2000 1600
1000
3200 2600
2000 1600
1000
VREF
-
278
6
AD1
AC7
-
2000 1600
1000
3200 1600
1000
279
280
6
6
AD2
AC1
AD6
AB8
-
3200 2600
1600 1000
VREF
2000 1600
1000
VREF
3200 2600
2000 1600
1000
302
7
U4
U9
-
3200 2600
2000 1600
1000
281
6
AC2
AC5
-
3200 2600
1600 1000
303
304
305
306
7
7
7
7
U5
U6
T6
T4
U7
U3
T3
T9
VREF
3200 2600
2000
282
283
284
285
286
6
6
6
6
6
AC3
AD4
AB6
Y10
AA7
AA9
AC4
AA8
AB1
AB2
-
-
-
-
-
2000 1600
1000
-
VREF
-
2000 1000
2000 1600
1000
3200 2600
1600 1000
3200 2600
1600 1000
2600 1600
3200 1600
1000
307
308
7
7
R1
T5
R6
3200 1600
1000
-
-
T10
2600 2000
1000
287
288
6
6
AA1
AB4
AA4
Y9
VREF
-
3200 2600
2000 1600
1000
309
310
7
7
R5
P5
R2
P1
-
3200 2600
2000 1600
2000 1600
1000
3200 2600
2000 1600
1000
VREF
289
6
Y8
AA2
-
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Table 29: FG1156 Differential Pin Pair Summary:
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
2600 2000
1000
331
7
K7
H3
2000 1600
-
311
312
313
7
7
7
P2
N1
R8
R9
P4
-
-
-
3200 2600
2000 1600
1000
3200 2600
2000
332
7
J5
G3
VREF
3200 2600
1600 1000
2600 2000
1000
R10
333
334
335
7
7
7
H5
H4
K8
L9
J6
-
-
-
3200 2600
2000 1600
1000
3200 2600
2000
314
7
N2
P8
-
3200 2600
1600 1000
G4
3200 2600
2000 1600
315
316
7
7
P7
N4
P6
-
3200 2600
2000 1600
1000
2600 2000
1000
336
7
F2
J7
-
M1
VREF
3200 1600
1000
3200 2600
2000 1600
317
318
319
320
321
7
7
7
7
7
N3
M2
M3
M4
N8
N6
P9
-
-
-
-
-
337
338
7
7
L10
H6
F3
E1
-
2600 1600
2600 2000
1000
VREF
3200 2600
1600 1000
N7
P10
L1
3200 2600
1600 1000
339
340
341
7
7
7
E2
D1
J8
G5
K9
E3
-
-
2000 1000
2600 1600
3200 2600
2000
3200 2600
1600 1000
VREF
3200 2600
2000 1600
1000
322
7
N9
L2
-
2600 2000
1000
342
343
7
7
D2
D3
E4
F4
-
-
2000 1600
1000
3200 2600
2000
323
324
7
7
K1
L4
M7
M8
VREF
-
3200 1600
1000
3200 2600
2000 1600
1000
325
7
L5
J1
-
3200 2600
2000 1600
1000
326
327
7
7
K3
J3
J2
L7
VREF
-
3200 2600
1600 1000
3200 2600
1600
328
329
7
7
H2
K6
M9
J4
-
2600 1000
VREF
3200 2600
2000 1600
1000
330
7
G2
L8
-
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Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T
values, buffered Hex Line info, p. 8, I/O Timing
BYP
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
7/10/00
1.3
1.4
1.5
Updated pinout tables, V page 20, and corrected Figure 20.
CC
Correction to table on p. 22.
•
Numerous minor edits.
•
•
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
•
•
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
8/1/00
1.6
1.7
•
•
Min values added to Virtex-E Electrical Characteristics tables.
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
9/20/00
tables (Module 3).
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate V
pins in Table ~ (Module 4).
CCINT
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF or I/O option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
•
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
11/20/00
1.8
•
•
•
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for T
, T
, T
, and T
.
SHCKO32 REG BCCS
ICKOF
•
Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
•
•
Revised maximum T
in -6 speed grade for DLL Timing Parameters.
DLLPW
Changed GCLK0 to BA22 for FG860 package in Table 46.
Revised footnote for Table 14.
•
•
2/12/01
1.9
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
•
•
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
•
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
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Revision
Date
Version
•
•
Updated numerous values in Virtex-E Switching Characteristics tables.
Changed pinout table footnotes from "VREF option only" to "VREF or I/O option only" to
improve clarity.
4/2/01
2.0
•
•
Converted file to modularized format. See the Virtex-E Data Sheet section.
Changed pinout table footnotes from "VREF or I/O option only" to "VREF or I/O option only;
otherwise I/O only" to improve clarity.
7/26/01
2.1
2.2
•
•
Changed designation for pin pair 300 in Table 29 from AO to footnote 9.
Changed Table 29 to clarify which devices in the FG1156 package can use each pin
pair as an asynchronous output.
10/25/01
•
•
Updated references to the XCV3200E device in the FG1156 package.
Fixed cosmetic error.
11/15/01
07/17/02
2.3
2.4
•
•
Added “VREF” to the description for pin B15 in Table 12.
Changed designation for pin pair 129 in Table 15 from AO to “AO in the XCV1000E,
1600E, 2000E“.
•
•
Data sheet designation upgraded from Preliminary to Production.
Removed the Virtex-E XCV300E section under Pinout Differences Between Virtex
and Virtex-E Families (and revised Table 1), since these differences do not exist.
03/14/03
2.5
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•
DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•
DS022-2, Virtex-E 1.8V FPGAs:
DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
Pinout Tables (Module 4)
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