XCV400E-6PQG240C [XILINX]
Field Programmable Gate Array, 2400 CLBs, 129600 Gates, 357MHz, 10800-Cell, CMOS, PQFP240, PLASTIC, QFP-240;
| 型号： | XCV400E-6PQG240C |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 2400 CLBs, 129600 Gates, 357MHz, 10800-Cell, CMOS, PQFP240, PLASTIC, QFP-240 时钟 栅 可编程逻辑 |
| 文件： | 总99页 (文件大小：927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Spartan-II FPGA Family
Data Sheet
DS001 June 13, 2008
Product Specification
This document includes all four modules of the Spartan®-II FPGA data sheet.
Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS001-1 (v2.8) June 13, 2008
DS001-3 (v2.8) June 13, 2008
•
•
•
•
•
•
Introduction
•
DC Specifications
-
-
-
-
-
Absolute Maximum Ratings
Recommended Operating Conditions
DC Characteristics
Power-On Requirements
DC Input and Output Levels
Features
General Overview
Product Availability
User I/O Chart
Ordering Information
•
Switching Characteristics
-
-
-
-
-
-
-
-
Pin-to-Pin Parameters
Module 2:
IOB Switching Characteristics
Clock Distribution Characteristics
DLL Timing Parameters
CLB Switching Characteristics
Block RAM Switching Characteristics
TBUF Switching Characteristics
JTAG Switching Characteristics
Functional Description
DS001-2 (v2.8) June 13, 2008
•
Architectural Description
-
-
-
-
-
-
Spartan-II Array
Input/Output Block
Configurable Logic Block
Block RAM
Clock Distribution: Delay-Locked Loop
Boundary Scan
Module 4:
Pinout Tables
•
•
Development System
Configuration
DS001-4 (v2.8) June 13, 2008
•
•
Pin Definitions
Pinout Tables
-
Configuration Timing
•
Design Considerations
IMPORTANT NOTE: This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001 June 13, 2008
www.xilinx.com
Product Specification
1
6
Spartan-II FPGA Family:
Introduction and Ordering
Information
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0
DS001-1 (v2.8) June 13, 2008
Product Specification
•
System level features
Introduction
The Spartan®-II Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in Table 1. System
performance is supported up to 200 MHz. Features include
block RAM (to 56K bits), distributed RAM (to 75,264 bits),
16 selectable I/O standards, and four DLLs. Fast,
-
SelectRAM™ hierarchical memory:
·
·
·
16 bits/LUT distributed RAM
Configurable 4K bit block RAM
Fast interfaces to external RAM
-
-
-
-
-
-
-
-
-
Fully PCI compliant
Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Efficient multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution
nets
predictable interconnect means that successive design
iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial
cost, lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
-
IEEE 1149.1 compatible boundary scan logic
•
Versatile I/O and packaging
-
-
-
-
-
-
Pb-free package options
Low-cost packages available in all densities
Family footprint compatibility in common packages
16 high-performance interface standards
Hot swap Compact PCI friendly
Features
•
Second generation ASIC replacement technology
-
Densities as high as 5,292 logic cells with up to
200,000 system gates
Zero hold time simplifies system timing
-
Streamlined features based on Virtex® FPGA
architecture
•
•
Core logic powered at 2.5V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx® ISE® development
system
-
-
-
Unlimited reprogrammability
Very low cost
Cost-effective 0.18 micron process
-
Fully automatic mapping, placement, and routing
Table 1: Spartan-II FPGA Family Members
CLB
Array
(R x C)
Maximum
Available
User I/O(1)
Total
Total
Logic
Cells
System Gates
(Logic and RAM)
Total
CLBs
Distributed RAM Block RAM
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Bits
Bits
16K
24K
32K
40K
48K
56K
432
15,000
30,000
8 x 12
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
96
86
6,144
972
216
92
13,824
24,576
38,400
55,296
75,264
1,728
2,700
3,888
5,292
50,000
384
176
176
260
284
100,000
150,000
200,000
600
864
1,176
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 2, page 4.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001-1 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 1 of 4
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Spartan-II FPGA Family: Introduction and Ordering Information
serial mode), or written into the FPGA in slave serial, slave
parallel, or Boundary Scan modes.
General Overview
The Spartan-II family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-II FPGAs are typically used in high-volume
applications where the versatility of a fast programmable
solution adds benefits. Spartan-II FPGAs are ideal for
shortening product development cycles while offering a
cost-effective solution for high volume production.
Spartan-II FPGAs achieve high-performance, low-cost
operation through advanced architecture and
semiconductor technology. Spartan-II devices provide
system clock rates up to 200 MHz. In addition to the
conventional benefits of high-volume programmable logic
solutions, Spartan-II FPGAs also offer on-chip synchronous
single-port and dual-port RAM (block and distributed form),
DLL clock drivers, programmable set and reset on all
flip-flops, fast carry logic, and many other features.
Spartan-II FPGAs are customized by loading configuration
data into internal static memory cells. Unlimited
reprogramming cycles are possible with this approach.
Stored values in these cells determine logic functions and
interconnections implemented in the FPGA. Configuration
data can be read from an external serial PROM (master
DLL
DLL
CLBs
CLBs
CLBs
CLBs
DLL
DLL
I/O LOGIC
XC2S15
DS001_01_091800
Figure 1: Basic Spartan-II Family FPGA Block Diagram
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Product Specification
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Spartan-II FPGA Family: Introduction and Ordering Information
Spartan-II Product Availability
Table 2 shows the maximum user I/Os available on the device and the number of user I/Os available for each
device/package combination. The four global clock pins are usable as additional user I/Os when not used as a global clock
pin. These pins are not included in user I/O counts.
Table 2: Spartan-II FPGA User I/O Chart(1)
Available User I/O According to Package Type
Maximum
User I/O
VQ100
VQG100
TQ144
TQG144
CS144
CSG144
PQ208
PQG208
FG256
FGG256
FG456
FGG456
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
86
92
60
60
-
86
92
92
92
-
(Note 2)
-
(Note 2)
140
-
-
92
-
-
-
-
176
176
260
284
176
176
176
176
-
-
140
(Note 2)
260
-
-
140
-
-
-
140
284
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
2. Discontinued by PDN2004-01.
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Spartan-II FPGA Family: Introduction and Ordering Information
Ordering Information
Spartan-II devices are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a special "G" character in the ordering code.
Standard Packaging
Example: XC2S50 -6 PQ 208 C
Device Type
Speed Grade
Package Type
Temperature Range
Number of Pins
DS077-1_01a_072204
Pb-Free Packaging
Example: XC2S50 -6 PQ G 208 C
Device Type
Temperature Range
Number of Pins
Pb-free
Speed Grade
Package Type
DS077-1_01b_072204
Device Ordering Options
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Speed Grade
Number of Pins / Package Type
Temperature Range (TJ)
-5 Standard Performance
-6 Higher Performance(1)
VQ(G)100 100-pin Plastic Very Thin QFP
CS(G)144 144-ball Chip-Scale BGA
TQ(G)144 144-pin Plastic Thin QFP
PQ(G)208 208-pin Plastic QFP
C = Commercial
I = Industrial
0°C to +85°C
–40°C to +100°C
FG(G)256 256-ball Fine Pitch BGA
FG(G)456 456-ball Fine Pitch BGA
Notes:
1. The -6 speed grade is exclusively available in the Commercial temperature range.
Device Part Marking
R
R
SPARTAN
XC2S50TM
PQ208AFP0025
A1134280A
6C
Date Code
Lot Code
Device Type
Package
Speed
Operating Range
Sample package with part marking
for XC2S50-6PQ208C.
ds001-1_02_090303
DS001-1 (v2.8) June 13, 2008
Product Specification
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Module 1 of 4
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Spartan-II FPGA Family: Introduction and Ordering Information
Revision History
Date
Version No.
Description
09/18/00
2.0
Sectioned the Spartan-II Family data sheet into four modules. Added industrial temperature
range information.
10/31/00
03/05/01
11/01/01
09/03/03
08/02/04
06/13/08
2.1
2.2
2.3
2.4
2.5
2.8
Removed Power down feature.
Added statement on PROMs.
Updated Product Availability chart. Minor text edits.
Added device part marking.
Added information on Pb-free packaging options and removed discontinued options.
Updated description and links. Updated all modules for continuous page, figure, and table
numbering. Synchronized all modules to v2.8.
PN 011311
DS001-1 (v2.8) June 13, 2008
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Spartan-II FPGA Family:
Functional Description
DS001-2 (v2.8) June 13, 2008
Product Specification
memory elements for easy and quick routing of signals on
and off the chip.
Architectural Description
Spartan-II FPGA Array
Values stored in static memory cells control all the
The Spartan®-II field-programmable gate array, shown in
Figure 2, is composed of five major configurable elements:
configurable logic elements and interconnect resources.
These values load into the memory cells on power-up, and
can reload if necessary to change the function of the device.
•
IOBs provide the interface between the package pins
and the internal logic
Each of these elements will be discussed in detail in the
following sections.
•
CLBs provide the functional elements for constructing
most logic
Input/Output Block
•
•
Dedicated block RAM memories of 4096 bits each
The Spartan-II FPGA IOB, as seen in Figure 2, features
inputs and outputs that support a wide variety of I/O
signaling standards. These high-speed inputs and outputs
are capable of supporting various state of the art memory
and bus interfaces. Table 3 lists several of the standards
which are supported along with the required reference,
output and termination voltages needed to meet the
standard.
Clock DLLs for clock-distribution delay compensation
and clock domain control
•
Versatile multi-level interconnect structure
As can be seen in Figure 2, the CLBs form the central logic
structure with easy access to all support and routing
structures. The IOBs are located around all the logic and
T
SR
V
CCO
D
Q
Package
Pin
TFF
CLK
TCE
SR
CK
EC
VCC
OE
I/O
Programmable
Bias &
ESD Network
Package Pin
SR
O
D
Q
Programmable
Output Buffer
OFF
CK
EC
Internal
Reference
OCE
Programmable
Delay
IQ
I
I/O, V
REF
SR
Programmable
Input Buffer
Package Pin
D
Q
IFF
CK
EC
To Next I/O
To Other
External V
Inputs
ICE
REF
of Bank
DS001_02_090600
Figure 2: Spartan-II FPGA Input/Output Block (IOB)
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
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Spartan-II FPGA Family: Functional Description
The three IOB registers function either as edge-triggered
D-type flip-flops or as level-sensitive latches. Each IOB has
a clock signal (CLK) shared by the three registers and
independent Clock Enable (CE) signals for each register. In
addition to the CLK and CE control signals, the three
registers share a Set/Reset (SR). For each register, this
signal can be independently configured as a synchronous
Set, a synchronous Reset, an asynchronous Preset, or an
asynchronous Clear.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Two
forms of over-voltage protection are provided, one that
permits 5V compliance, and one that does not. For 5V
compliance, a zener-like structure connected to ground
turns on when the output rises to approximately 6.5V. When
5V compliance is not required, a conventional clamp diode
may be connected to the output supply voltage, VCCO. The
type of over-voltage protection can be selected
independently for each pad.
A feature not shown in the block diagram, but controlled by
the software, is polarity control. The input and output buffers
and all of the IOB control signals have independent polarity
controls.
All Spartan-II FPGA IOBs support IEEE 1149.1-compatible
boundary scan testing.
Input Path
Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each pad. Prior to
configuration all outputs not involved in configuration are
forced into their high-impedance state. The pull-down
resistors and the weak-keeper circuits are inactive, but
inputs may optionally be pulled up.
A buffer In the Spartan-II FPGA IOB input path routes the
input signal either directly to internal logic or through an
optional input flip-flop.
An optional delay element at the D-input of this flip-flop
eliminates pad-to-pad hold time. The delay is matched to
the internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Table 3: Standards Supported by I/O (Typical Values)
Input
Reference Source Termination
Voltage Voltage Voltage
Output
Board
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
constraints on which standards can used in close proximity
to each other. See "I/O Banking," page 9.
I/O Standard
LVTTL (2-24 mA)
LVCMOS2
(VREF
)
(VCCO
)
(VTT
N/A
N/A
N/A
)
N/A
3.3
N/A
2.5
There are optional pull-up and pull-down resistors at each
input for use after configuration.
PCI (3V/5V,
N/A
3.3
33 MHz/66 MHz)
Output Path
GTL
0.8
1.0
N/A
N/A
1.5
1.5
1.5
3.3
1.2
1.5
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
0.75
0.9
0.75
1.5
1.5
1.5
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides
synchronous enable and disable.
0.9
SSTL3 Class I
and II
1.5
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.
SSTL2 Class I
and II
1.25
2.5
1.25
CTT
1.5
3.3
3.3
1.5
In most signaling standards, the output high voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. See "I/O
Banking".
AGP-2X
1.32
N/A
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins will float.
Consequently, external pull-up or pull-down resistors must
be provided on pins required to be at a well-defined logic
level prior to configuration.
An optional weak-keeper circuit is connected to each
output. When selected, the circuit monitors the voltage on
the pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source
signal, the weak keeper holds the signal in its last state if all
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Spartan-II FPGA Family: Functional Description
drivers are disabled. Maintaining a valid logic level in this
way helps eliminate bus chatter.
automatically configured as inputs for the VREF voltage.
About one in six of the I/O pins in the bank assume this role.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate VREF voltage must
be provided if the signaling standard requires one. The
provision of this voltage must comply with the I/O banking
rules.
VREF pins within a bank are interconnected internally and
consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be
connected to the external voltage source for correct
operation.
In a bank, inputs requiring VREF can be mixed with those
that do not but only one VREF voltage may be used within a
bank. Input buffers that use VREF are not 5V tolerant.
LVTTL, LVCMOS2, and PCI are 5V tolerant. The VCCO and
VREF pins for each bank appear in the device pinout tables.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages are externally
connected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to VREF pins. Since these are always
a superset of the VREF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device. All VREF pins for the largest device anticipated must
be connected to the VREF voltage, and not used for I/O.
Eight I/O banks result from separating each edge of the
FPGA into two banks (see Figure 3). Each bank has
multiple VCCO pins which must be connected to the same
voltage. Voltage is determined by the output standards in
use.
Independent Banks Available
Package
VQ100
PQ208
CS144
TQ144
FG256
FG456
Bank 0
Bank 1
GCLK3 GCLK2
Independent Banks
1
4
8
Configurable Logic Block
Spartan-II
Device
The basic building block of the Spartan-II FPGA CLB is the
logic cell (LC). An LC includes a 4-input function generator,
carry logic, and storage element. Output from the function
generator in each LC drives the CLB output and the D input
of the flip-flop. Each Spartan-II FPGA CLB contains four
LCs, organized in two similar slices; a single slice is shown
in Figure 4.
GCLK1 GCLK0
Bank 5
Bank 4
In addition to the four basic LCs, the Spartan-II FPGA CLB
contains logic that combines function generators to provide
functions of five or six inputs.
DS001_03_060100
Figure 3: Spartan-II I/O Banks
Within a bank, output standards may be mixed only if they
use the same VCCO. Compatible standards are shown in
Table 4. GTL and GTL+ appear under all voltages because
Look-Up Tables
Spartan-II FPGA function generators are implemented as
4-input look-up tables (LUTs). In addition to operating as a
function generator, each LUT can provide a 16 x 1-bit
synchronous RAM. Furthermore, the two LUTs within a
slice can be combined to create a 16 x 2-bit or 32 x 1-bit
synchronous RAM, or a 16 x 1-bit dual-port synchronous
RAM.
their open-drain outputs do not depend on VCCO
.
Table 4: Compatible Output Standards
VCCO
Compatible Standards
3.3V
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,
GTL, GTL+
The Spartan-II FPGA LUT can also provide a 16-bit shift
register that is ideal for capturing high-speed or burst-mode
data. This mode can also be used to store data in
applications such as Digital Signal Processing.
2.5V
1.5V
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
HSTL I, HSTL III, HSTL IV, GTL, GTL+
Some input standards require a user-supplied threshold
voltage, VREF. In this case, certain user-I/O pins are
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Spartan-II FPGA Family: Functional Description
COUT
YB
Y
I4
I3
I2
I1
G4
G3
G2
G1
S
Look-Up
Table
YQ
D
Q
Carry
and
Control
Logic
O
CK
EC
R
F5IN
BY
SR
XB
X
F4
F3
F2
F1
I4
I3
I2
I1
S
R
Look-Up
Table
XQ
D
Q
Carry
and
Control
Logic
O
CK
EC
BX
CIN
CLK
CE
DS001_04_091400
Figure 4: Spartan-II CLB Slice (two identical slices in each CLB)
opposite state. Alternatively, these signals may be
Storage Elements
configured to operate asynchronously.
Storage elements in the Spartan-II FPGA slice can be
configured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
function generators within the slice or directly from slice
inputs, bypassing the function generators.
All control signals are independently invertible, and are
shared by the two flip-flops within the slice.
Additional Logic
The F5 multiplexer in each slice combines the function
generator outputs. This combination provides either a
function generator that can implement any 5-input function,
a 4:1 multiplexer, or selected functions of up to nine inputs.
In addition to Clock and Clock Enable signals, each slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state
specified for it in the configuration. BY forces it into the
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Spartan-II FPGA Family: Functional Description
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected
functions of up to 19 inputs.
Each block RAM cell, as illustrated in Figure 5, is a fully
synchronous dual-ported 4096-bit RAM with independent
control signals for each port. The data widths of the two
ports can be configured independently, providing built-in
bus-width conversion.
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional
local routing that does not consume logic resources.
RAMB4_S#_S#
WEA
ENA
RSTA
Arithmetic Logic
DOA[#:0]
CLKA
ADD[#:0]
DIA[#:0]
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-II FPGA CLB supports
two separate carry chains, one per slice. The height of the
carry chains is two bits per CLB.
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation.
DOB[#:0]
The dedicated carry path can also be used to cascade
function generators for implementing wide logic functions.
DS001_05_060100
BUFTs
Figure 5: Dual-Port Block RAM
Each Spartan-II FPGA CLB contains two 3-state drivers
(BUFTs) that can drive on-chip busses. See "Dedicated
Routing," page 12. Each Spartan-II FPGA BUFT has an
independent 3-state control pin and an independent input
pin.
Table 6 shows the depth and width aspect ratios for the
block RAM.
Table 6: Block RAM Port Aspect Ratios
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
Block RAM
1
2
Spartan-II FPGAs incorporate several large block RAM
memories. These complement the distributed RAM
Look-Up Tables (LUTs) that provide shallow memory
structures implemented in CLBs.
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
4
8
Block RAM memory blocks are organized in columns. All
Spartan-II devices contain two such columns, one along
each vertical edge. These columns extend the full height of
the chip. Each memory block is four CLBs high, and
consequently, a Spartan-II device eight CLBs high will
contain two memory blocks per column, and a total of four
blocks.
16
256
The Spartan-II FPGA block RAM also includes dedicated
routing to provide an efficient interface with both CLBs and
other block RAMs.
Programmable Routing Matrix
Table 5: Spartan-II Block RAM Amounts
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Spartan-II routing
architecture and its place-and-route software were defined
in a single optimization process. This joint optimization
minimizes long-path delays, and consequently, yields the
best system performance.
Spartan-II
Device
Total Block RAM
Bits
# of Blocks
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
4
6
16K
24K
32K
40K
48K
56K
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
8
10
12
14
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Spartan-II FPGA Family: Functional Description
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
Local Routing
The local routing resources, as shown in Figure 6, provide
the following three types of connections:
I/O Routing
•
Interconnections among the LUTs, flip-flops, and
General Routing Matrix (GRM)
Spartan-II devices have additional routing resources
around their periphery that form an interface between the
CLB array and the IOBs. This additional routing, called the
VersaRing, facilitates pin-swapping and pin-locking, such
that logic redesigns can adapt to existing PCB layouts.
Time-to-market is reduced, since PCBs and other system
components can be manufactured while the logic design is
still in progress.
•
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
•
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM
Dedicated Routing
To Adjacent
GRM
Some classes of signal require dedicated routing resources
to maximize performance. In the Spartan-II architecture,
dedicated routing resources are provided for two classes of
signal.
To
Adjacent
GRM
To Adjacent
GRM
GRM
•
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in Figure 7.
To Adjacent
GRM
Direct
Direct Connection
To Adjacent
CLB
CLB
Connection
To Adjacent
CLB
•
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
Global Routing
DS001_06_032300
Figure 6: Spartan-II Local Routing
Global Routing resources distribute clocks and other
signals with very high fanout throughout the device.
Spartan-II devices include two tiers of global routing
resources referred to as primary and secondary global
routing resources.
General Purpose Routing
Most Spartan-II FPGA signals are routed on the general
purpose routing, and consequently, the majority of
interconnect resources are associated with this level of the
routing hierarchy. The general routing resources are
located in horizontal and vertical routing channels
associated with the rows and columns CLBs. The
general-purpose routing resources are listed below.
•
The primary global routing resources are four
dedicated global nets with dedicated input pins that are
designed to distribute high-fanout clock signals with
minimal skew. Each global clock net can drive all CLB,
IOB, and block RAM clock pins. The primary global
nets may only be driven by global buffers. There are
four global buffers, one for each global net.
•
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
•
The secondary global routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
•
•
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
96 buffered Hex lines route GRM signals to other
GRMs six blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
may be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of
the Hex lines are bidirectional, while the remaining
ones are unidirectional.
•
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
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Spartan-II FPGA Family: Functional Description
3-State
Lines
CLB
CLB
CLB
CLB
DS001_07_090600
Figure 7: BUFT Connections to Dedicated Horizontal Bus Lines
networks. The DLL monitors the input clock and the
Clock Distribution
distributed clock, and automatically adjusts a clock delay
element. Additional delay is introduced such that clock
edges reach internal flip-flops exactly one clock period after
they arrive at the input. This closed-loop system effectively
eliminates clock-distribution delay by ensuring that clock
edges arrive at internal flip-flops in synchronism with clock
edges arriving at the input.
The Spartan-II family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Figure 8.
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. It has six outputs.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the
general purpose routing. Global clock pins do not have the
option for internal, weak pull-up resistors.
The DLL also operates as a clock mirror. By driving the
output from a DLL off-chip and then back on again, the DLL
can be used to deskew a board level clock among multiple
Spartan-II devices.
GCLKPAD2
GCLKBUF2
GCLKPAD3
GCLKBUF3
Global
Clock Rows
Global Clock
Column
In order to guarantee that the system clock is operating
correctly prior to the FPGA starting up after configuration,
the DLL can delay the completion of the configuration
process until after it has achieved lock.
Boundary Scan
Global Clock
Spine
Spartan-II devices support all the mandatory boundary-
scan instructions specified in the IEEE standard 1149.1. A
Test Access Port (TAP) and registers are provided that
implement the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. The TAP also supports two USERCODE
instructions and internal scan chains.
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the VCCO
for Bank 2 must be 3.3V. Otherwise, TDO switches
rail-to-rail between ground and VCCO. TDI, TMS, and TCK
have a default internal weak pull-up resistor, and TDO has
no default resistor. Bitstream options allow setting any of
the four TAP pins to have an internal pull-up, pull-down, or
neither.
DS001_08_060100
Figure 8: Global Clock Distribution Network
Delay-Locked Loop (DLL)
Associated with each global clock input buffer is a fully
digital Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
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Spartan-II FPGA Family: Functional Description
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including unbonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
The public boundary-scan instructions are available prior to
configuration. After configuration, the public instructions
remain available together with any USERCODE
instructions installed during the configuration. While the
SAMPLE and BYPASS instructions are available during
configuration, it is recommended that boundary-scan
operations not be performed during this transitional period.
Table 7 lists the boundary-scan instructions supported in
Spartan-II FPGAs. Internal signals can be captured during
EXTEST by connecting them to unbonded or unused IOBs.
They may also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the FPGA,
and also to read back the configuration data.
To facilitate internal scan chains, the User Register
provides three outputs (Reset, Update, and Shift) that
represent the corresponding states in the boundary-scan
internal state machine.
Table 7: Boundary-Scan Instructions
Boundary-Scan
Command
Binary
Code[4:0]
Description
EXTEST
SAMPLE
USR1
00000
00001
00010
00011
00100
Enables boundary-scan
EXTEST operation
Enables boundary-scan
SAMPLE operation
Access user-defined
register 1
USR2
Access user-defined
register 2
CFG_OUT
Access the
configuration bus for
Readback
CFG_IN
00101
Access the
configuration bus for
Configuration
INTEST
USRCODE
IDCODE
HIZ
00111
01000
01001
01010
Enables boundary-scan
INTEST operation
Enables shifting out
USER code
Enables shifting out of
ID Code
Disables output pins
while enabling the
Bypass Register
JSTART
01100
11111
Clock the start-up
sequence when
StartupClk is TCK
BYPASS
Enables BYPASS
RESERVED
All other
codes
Xilinx® reserved
instructions
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Spartan-II FPGA Family: Functional Description
Figure 9 is a diagram of the Spartan-II family boundary scan
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction
Register with decodes.
DATA IN
IOB.T
0
1
sd
1
D
D
Q
Q
D
Q
0
LE
IOB IOB IOB IOB IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
sd
1
0
D
Q
LE
1
0
IOB.I
1
sd
D
Q
D
Q
0
LE
1
0
IOB.Q
IOB.T
Bypass
Register
0
1
M
U
X
TDO
1
sd
Instruction Register
D
Q
D
Q
TDI
0
LE
1
sd
D
Q
D
Q
0
LE
1
0
IOB.I
DATAOUT
UPDATE
EXTEST
CLOCK DATA
REGISTER
SHIFT/
CAPTURE
DS001_09_032300
Figure 9: Spartan-II Family Boundary Scan Logic
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins
contributes all three bits.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 10.
BSDL (Boundary Scan Description Language) files for
Spartan-II family devices are available on the Xilinx
website, in the Downloads area.
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Spartan-II FPGA Family: Functional Description
Design Implementation
TDO.T
TDO.O
Bit 0 ( TDO end)
Bit 1
Bit 2
The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The
partitioner takes the EDIF netlist for the design and maps
the logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best locations for these blocks based on their
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
interconnections and the desired performance. Finally, the
router interconnects the blocks.
MODE.I
The PAR algorithms support fully automatic implementation
of most designs. For demanding applications, however, the
user can exercise various degrees of control over the
process. User partitioning, placement, and routing
information is optionally specified during the design-entry
process. The implementation of highly structured designs
can benefit greatly from basic floorplanning.
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
(TDI end)
DS001_10_032300
The implementation software incorporates timing-driven
placement and routing. Designers specify timing
Figure 10: Boundary Scan Bit Sequence
requirements along entire paths during design entry. The
timing path analysis routines in PAR then recognize these
user-specified requirements and accommodate them.
Development System
Spartan-II FPGAs are supported by the Xilinx ISE®
development tools. The basic methodology for Spartan-II
FPGA design consists of three interrelated steps: design
entry, implementation, and verification. Industry-standard
tools are used for design entry and simulation, while Xilinx
provides proprietary architecture-specific tools for
implementation.
Timing requirements are entered in a form directly relating
to the system requirements, such as the targeted clock
frequency, or the maximum allowable delay between two
registers. In this way, the overall performance of the system
along entire signal paths is automatically tailored to
user-generated specifications. Specific timing information
for individual nets is unnecessary.
The Xilinx development system is integrated under a single
graphical interface, providing designers with a common
user interface regardless of their choice of entry and
verification tools. The software simplifies the selection of
implementation options with pull-down menus and on-line
help.
Design Verification
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be
verified in real time without the need for extensive sets of
software simulation vectors.
For HDL design entry, the Xilinx FPGA development
system provides interfaces to several synthesis design
environments.
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the netlist for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
static timing analyzer.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Spartan-II FPGAs supported by a unified library of standard
functions. This library contains over 400 primitives and
macros, ranging from 2-input AND gates to 16-bit
accumulators, and includes arithmetic functions,
comparators, counters, data registers, decoders, encoders,
I/O functions, latches, Boolean functions, multiplexers, shift
registers, and barrel shifters.
For in-circuit debugging, the development system includes
a download cable, which connects the FPGA in the target
system to a PC or workstation. After downloading the
design into the FPGA, the designer can read back the
contents of the flip-flops, and so observe the internal logic
state. Simple modifications can be downloaded into the
system in a matter of minutes.
The design environment supports hierarchical design entry.
These hierarchical design elements are automatically
combined by the implementation tools. Different design
entry tools can be combined within a hierarchical design,
thus allowing the most convenient entry method to be used
for each portion of the design.
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Spartan-II FPGA Family: Functional Description
Configuration
Table 8: Spartan-II Configuration File Size
Configuration is the process by which the bitstream of a
design, as generated by the Xilinx software, is loaded into
the internal configuration memory of the FPGA. Spartan-II
devices support both serial configuration, using the
master/slave serial and JTAG modes, as well as byte-wide
configuration employing the Slave Parallel mode.
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Configuration File Size (Bits)
197,696
336,768
559,200
781,216
1,040,096
1,335,840
Configuration File
Spartan-II devices are configured by sequentially loading
frames of data that have been concatenated into a
configuration file. Table 8 shows how much nonvolatile
storage space is needed for Spartan-II devices.
Modes
It is important to note that, while a PROM is commonly used
to store configuration data before loading them into the
FPGA, it is by no means required. Any of a number of
different kinds of under populated nonvolatile storage
already available either on or off the board (i.e., hard drives,
FLASH cards, etc.) can be used. For more information on
configuration without a PROM, refer to XAPP098, The
Low-Cost, Efficient Serial Configuration of Spartan FPGAs.
Spartan-II devices support the following four configuration
modes:
•
•
•
•
Slave Serial mode
Master Serial mode
Slave Parallel mode
Boundary-scan mode
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
the end of configuration. The selection codes are listed in
Table 9.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
Table 9: Configuration Modes
Preconfiguration
CCLK
Configuration Mode
Pull-ups
M0
0
M1
0
M2
0
Direction
Data Width
Serial DOUT
Master Serial mode
No
Out
1
Yes
Yes
Yes
No
0
0
1
Slave Parallel mode
Boundary-Scan mode
Slave Serial mode
Notes:
0
1
0
In
N/A
In
8
1
1
No
No
0
1
1
Yes
No
1
0
0
1
0
1
Yes
No
1
1
0
Yes
1
1
1
1. During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os
(those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration
(see Answer 10504).
2. If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode
pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine
whether the unused I/Os have a pull-up, pull-down, or no resistor.
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Spartan-II FPGA Family: Functional Description
by driving DONE Low, then enters the memory-clearing
phase.
Signals
There are two kinds of pins that are used to configure
Spartan-II devices: Dedicated pins perform only specific
configuration-related functions; the other pins can serve as
general purpose I/Os once user operation has begun.
Configuration
at Power-up
Configuration During
User Operation
The dedicated pins comprise the mode pins (M2, M1, M0),
the configuration clock pin (CCLK), the PROGRAM pin, the
DONE pin and the boundary-scan pins (TDI, TDO, TMS,
TCK). Depending on the selected configuration mode,
CCLK may be an output generated by the FPGA, or may be
generated externally, and provided to the FPGA as an
input.
VCCO
AND
VCCINT
High?
No
User Pulls
PROGRAM
Low
Yes
Note that some configuration pins can act as outputs. For
correct operation, these pins require a VCCO of 3.3V to drive
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the
relevant pins fall in banks 2 or 3. The CS and WRITE pins
for Slave Parallel mode are located in bank 1.
FPGA
Drives INIT
and DONE Low
For a more detailed description than that given below, see
"Pinout Tables" in Module 4 and XAPP176, Spartan-II
FPGA Series Configuration and Readback.
Clear
Configuration
Memory
Delay
Configuration
The Process
Yes
User Holding
PROGRAM
Low?
The sequence of steps necessary to configure Spartan-II
devices are shown in Figure 11. The overall flow can be
divided into three different phases.
No
•
•
•
•
Initiating Configuration
Configuration memory clear
Loading data frames
Start-up
Delay
Configuration
Yes
User Holding
INIT
Low?
No
The memory clearing and start-up phases are the same for
all configuration modes; however, the steps for the loading
of data frames are different. Thus, the details for data frame
loading are described separately in the sections devoted to
each mode.
FPGA
Samples
Mode Pins
Load
Configuration
Data Frames
Initiating Configuration
There are two different ways to initiate the configuration
process: applying power to the device or asserting the
PROGRAM input.
FPGA Drives
INIT Low
Abort Start-up
No
Configuration on power-up occurs automatically unless it is
delayed by the user, as described in a separate section
below. The waveform for configuration on power-up is
shown in Figure 12, page 19. Before configuration can
begin, VCCO Bank 2 must be greater than 1.0V.
Furthermore, all VCCINT power pins must be connected to a
2.5V supply. For more information on delaying
configuration, see "Clearing Configuration Memory,"
page 19.
CRC
Correct?
Yes
Start-up Sequence
FPGA Drives DONE High,
Activates I/Os,
Releases GSR net
User Operation
Once in user operation, the device can be re-configured
simply by pulling the PROGRAM pin Low. The device
acknowledges the beginning of the configuration process
DS001_11_111501
Figure 11: Configuration Flow Diagram
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Spartan-II FPGA Family: Functional Description
(1)
T
V
POR
CC
PROGRAM
INIT
T
PL
T
ICCK
Valid
CCLK Output or Input
M0, M1, M2
(Required)
DS001_12_102301
.
Symbol
TPOR
Description
Min
Max
Power-on reset
Program latency
-
2 ms
100 μs
4 μs
-
TPL
-
TICCK
CCLK output delay (Master Serial mode only)
Program pulse width
0.5 μs
300 ns
TPROGRAM
Notes: (referring to waveform above:)
1. Before configuration can begin, VCCINT must be greater than 1.6V and VCCO Bank 2 must be greater than 1.0V.
Figure 12: Configuration Timing on Power-Up
do not match, the FPGA drives INIT Low to indicate that a
frame error has occurred and configuration is aborted.
Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low. At this time, the user can
delay configuration by holding either PROGRAM or INIT
Low, which causes the device to remain in the memory
clearing phase. Note that the bidirectional INIT line is
driving a Low logic level during memory clearing. To avoid
contention, use an open-drain driver to keep INIT Low.
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See "Clearing
Configuration Memory".
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the
configuration data, initiates the sequence.
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
Loading Configuration Data
During start-up, the device performs four operations:
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the
configuration data are discussed in the sections treating the
configuration modes individually. The sequence of
operations necessary to load configuration data using the
serial modes is shown in Figure 14. Loading data using the
Slave Parallel mode is shown in Figure 19, page 25.
1. The assertion of DONE. The failure of DONE to go High
may indicate the unsuccessful loading of configuration
data.
2. The release of the Global Three State net. This
activates I/Os to which signals are assigned. The
remaining I/Os stay in a high-impedance state with
internal weak pull-down resistors present.
CRC Error Checking
3. Negates Global Set Reset (GSR). This allows all
flip-flops to change state.
During the loading of configuration data, a CRC value
embedded in the configuration file is checked against a
CRC value calculated within the FPGA. If the CRC values
4. The assertion of Global Write Enable (GWE). This
allows all RAMs and flip-flops to change state.
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Spartan-II FPGA Family: Functional Description
By default, these operations are synchronized to CCLK.
The entire start-up sequence lasts eight cycles, called
C0-C7, after which the loaded design is fully functional. The
default timing for start-up is shown in the top half of
Figure 13. The four operations can be selected to switch on
any CCLK cycle C1-C6 through settings in the Xilinx
software. Heavy lines show default settings.
Serial Modes
There are two serial configuration modes: In Master Serial
mode, the FPGA controls the configuration process by
driving CCLK as an output. In Slave Serial mode, the FPGA
passively receives CCLK as an input from an external agent
(e.g., a microprocessor, CPLD, or second FPGA in master
mode) that is controlling the configuration process. In both
modes, the FPGA is configured by loading one bit per
CCLK cycle. The MSB of each configuration data byte is
always written to the DIN pin first.
Default Cycles
Start-up CLK
See Figure 14 for the sequence for loading data into the
Spartan-II FPGA serially. This is an expansion of the "Load
Configuration Data Frames" block in Figure 11. Note that
CS and WRITE normally are not used during serial
configuration. To ensure successful loading of the FPGA,
do not toggle WRITE with CS Low during serial
configuration.
Phase
0
1
2
3
4
5
6 7
DONE
GTS
GSR
After INIT
Goes High
GWE
User Load One
Configuration
Sync to DONE
Bit on Next
CCLK Rising Edge
Start-up CLK
Phase
0
1
2
3
4
5
6 7
End of
No
Configuration
Data File?
DONE High
Yes
DONE
GTS
To CRC Check
DS001_14_042403
Figure 14: Loading Serial Mode Configuration Data
GSR
GWE
DS001_13_090600
Figure 13: Start-Up Waveforms
The bottom half of Figure 13 shows another commonly
used version of the start-up timing known as
Sync-to-DONE. This version makes the GTS, GSR, and
GWE events conditional upon the DONE pin going High.
This timing is important for a daisy chain of multiple FPGAs
in serial mode, since it ensures that all FPGAs go through
start-up together, after all their DONE pins have gone High.
Sync-to-DONE timing is selected by setting the GTS, GSR,
and GWE cycles to a value of DONE in the configuration
options. This causes these signals to transition one clock
cycle after DONE externally transitions High.
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Spartan-II FPGA Family: Functional Description
Multiple FPGAs in Slave Serial mode can be daisy-chained
for configuration from a single source. The maximum
amount of data that can be sent to the DOUT pin for a serial
daisy chain is 220-1 (1,048,575) 32-bit words, or 33,554,400
bits, which is approximately 25 XC2S200 bitstreams. The
configuration bitstream of downstream devices is limited to
this size.
Slave Serial Mode
In Slave Serial mode, the FPGA’s CCLK pin is driven by an
external source, allowing FPGAs to be configured from
other logic devices such as microprocessors or in a
daisy-chain configuration. Figure 15 shows connections for
a Master Serial FPGA configuring a Slave Serial FPGA
from a PROM. A Spartan-II device in slave serial mode
should be connected as shown for the third device from the
left. Slave Serial mode is selected by a <11x> on the mode
pins (M0, M1, M2).
After an FPGA is configured, data for the next device is
routed to the DOUT pin. Data on the DOUT pin changes on
the rising edge of CCLK. Configuration must be delayed
until INIT pins of all daisy-chained FPGAs are High. For
more information, see "Start-up," page 19.
Figure 16 shows the timing for Slave Serial configuration.
The serial bitstream must be setup at the DIN input pin a
short time before each rising edge of an externally
generated CCLK.
3.3V
3.3V
2.5V
3.3V
3.3V
2.5V
3.3 K
M0 M1
M2
VCCO
M0 M1
M2
VCCO
VCCINT
VCCINT
DOUT
DOUT
DIN
CCLK
Spartan-II
(Master Serial)
Spartan-II
(Slave)
Vcc
CCLK
CLK
DATA
CE
PROM
DIN
CEO
PROGRAM
PROGRAM
DONE
RESET/OE
DONE
INIT
INIT
GND
GND
GND
PROGRAM
Notes:
DS001_15_060608
1. If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 330Ω resistor.
Figure 15: Master/Slave Serial Configuration Circuit Diagram
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Spartan-II FPGA Family: Functional Description
DIN
T
T
T
CCD
CCL
DCC
CCLK
T
CCH
T
CCO
DOUT
(Output)
DS001_16_032300
.
Symbol
TDCC
Description
Units
DIN setup
DIN hold
5
0
ns, min
ns, min
TCCD
TCCO
TCCH
TCCL
FCC
DOUT
12
5
ns, max
ns, min
CCLK
High time
Low time
5
ns, min
Maximum frequency
66
MHz, max
Figure 16: Slave Serial Mode Timing
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Spartan-II FPGA Family: Functional Description
the configuration data are being loaded, the CCLK
frequency is always 2.5 MHz. This frequency is used until
the ConfigRate bits, part of the configuration file, have been
loaded into the FPGA, at which point, the frequency
changes to the selected ConfigRate. Unless a different
frequency is specified in the design, the default ConfigRate
is 4 MHz. The frequency of the CCLK signal created by the
internal oscillator has a variance of +45%, –30% from the
specified value.
Master Serial Mode
In Master Serial mode, the CCLK output of the FPGA drives
a Xilinx PROM which feeds a serial stream of configuration
data to the FPGA’s DIN input. Figure 15 shows a Master
Serial FPGA configuring a Slave Serial FPGA from a
PROM. A Spartan-II device in Master Serial mode should
be connected as shown for the device on the left side.
Master Serial mode is selected by a <00x> on the mode
pins (M0, M1, M2). The PROM RESET pin is driven by INIT,
and CE input is driven by DONE. The interface is identical
to the slave serial mode except that an oscillator internal to
the FPGA is used to generate the configuration clock
(CCLK). Any of a number of different frequencies ranging
from 4 to 60 MHz can be set using the ConfigRate option in
the Xilinx software. On power-up, while the first 60 bytes of
Figure 17 shows the timing for Master Serial configuration.
The FPGA accepts one bit of configuration data on each
rising CCLK edge. After the FPGA has been loaded, the
data for the next device in a daisy-chain is presented on the
DOUT pin after the rising CCLK edge.
CCLK
(Output)
T
CKDS
T
DSCK
Serial Data In
T
CCO
Serial DOUT
(Output)
DS001_17_110101
.
Symbol
TDSCK
Description
Units
ns, min
ns, min
-
DIN setup
DIN hold
5.0
0.0
TCKDS
CCLK
Frequency tolerance with respect to
nominal
+45%, –30%
Figure 17: Master Serial Mode Timing
The agent controlling configuration is not shown. Typically,
a processor, a microcontroller, or CPLD controls the Slave
Parallel interface. The controlling agent provides byte-wide
configuration data, CCLK, a Chip Select (CS) signal and a
Write signal (WRITE). If BUSY is asserted (High) by the
FPGA, the data must be held until BUSY goes Low.
Slave Parallel Mode
The Slave Parallel mode is the fastest configuration option.
Byte-wide data is written into the FPGA. A BUSY flag is
provided for controlling the flow of data at a clock frequency
FCCNH above 50 MHz.
Figure 18, page 24 shows the connections for two
Spartan-II devices using the Slave Parallel mode. Slave
Parallel mode is selected by a <011> on the mode pins (M0,
M1, M2).
After configuration, the pins of the Slave Parallel port
(D0-D7) can be used as additional user I/O. Alternatively,
the port may be retained to permit high-speed 8-bit
readback. Then data can be read by de-asserting WRITE.
See "Readback," page 25.
If a configuration file of the format .bit, .rbt, or non-swapped
HEX is used for parallel programming, then the most
significant bit (i.e. the left-most bit of each configuration
byte, as displayed in a text editor) must be routed to the D0
input on the FPGA.
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Spartan-II FPGA Family: Functional Description
DATA[7:0]
CCLK
WRITE
BUSY
M1 M2
M0
M1 M2
M0
Spartan-II
FPGA
Spartan-II
FPGA
D0:D7
D0:D7
CCLK
WRITE
BUSY
CCLK
WRITE
BUSY
CS
CS(0)
CS(1)
CS
PROGRAM
PROGRAM
330Ω
DONE
GND
INIT
DONE
GND
INIT
DONE
INIT
PROGRAM
DS001_18_060608
Figure 18: Slave Parallel Configuration Circuit Diagram
Multiple Spartan-II FPGAs can be configured using the
Slave Parallel mode, and be made to start-up
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or de-asserted. Otherwise an abort
will be initiated, as in the next section.
simultaneously. To configure multiple devices in this way,
wire the individual CCLK, Data, WRITE, and BUSY pins of
all the devices in parallel. The individual devices are loaded
separately by asserting the CS pin of each device in turn
and writing the appropriate data. Sync-to-DONE start-up
timing is used to ensure that the start-up sequence does not
begin until all the FPGAs have been loaded. See "Start-up,"
page 19.
1. Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
2. On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 19, page 25 shows a flowchart of the write sequence
used to load data into the Spartan-II FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
Figure 11, page 18. The timing for write operations is shown
in Figure 20, page 26.
3. Repeat steps 1 and 2 until all the data has been sent.
4. De-assert CS and WRITE.
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Spartan-II FPGA Family: Functional Description
If CCLK is slower than FCCNH, the FPGA will never assert
BUSY. In this case, the above handshake is unnecessary,
and data can simply be entered into the FPGA every CCLK
cycle.
interface does not expect any data and ignores all CCLK
transitions. However, to avoid aborting configuration,
WRITE must continue to be asserted while CS is asserted.
Abort
To abort configuration during a write sequence, de-assert
WRITE while holding CS Low. The abort operation is
initiated at the rising edge of CCLK, as shown in Figure 21,
page 26. The device will remain BUSY until the aborted
operation is complete. After aborting configuration, data is
assumed to be unaligned to word boundaries and the FPGA
requires a new synchronization word prior to accepting any
new packets.
After INIT
Goes High
User Drives
WRITE and CS
Low
Boundary-Scan Mode
In the boundary-scan mode, no nondedicated pins are
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port.
Load One
Configuration
Byte on Next
CCLK Rising Edge
Configuration through the TAP uses the special CFG_IN
instruction. This instruction allows data input on TDI to be
converted into data packets for the internal configuration
bus.
FPGA
Yes
The following steps are required to configure the FPGA
through the boundary-scan port.
Driving BUSY
High?
1. Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
No
2. Enter the Shift-DR (SDR) state
3. Shift a standard configuration bitstream into TDI
4. Return to Run-Test-Idle (RTI)
End of
No
Configuration
Data File?
5. Load the JSTART instruction into IR
6. Enter the SDR state
Yes
User Drives
WRITE and CS
High
7. Clock TCK through the sequence (the length is
programmable)
8. Return to RTI
Configuration and readback via the TAP is always available.
The boundary-scan mode simply locks out the other modes.
The boundary-scan mode is selected by a <10x> on the
mode pins (M0, M1, M2).
To CRC Check
DS001_19_032300
Figure 19: Loading Configuration Data for the Slave
Parallel Mode
Readback
The configuration data stored in the Spartan-II FPGA
configuration memory can be readback for verification.
Along with the configuration data it is possible to readback
the contents of all flip-flops/latches, LUT RAMs, and block
RAMs. This capability is used for real-time debugging.
A configuration packet does not have to be written in one
continuous stretch, rather it can be split into many write
sequences. Each sequence would involve assertion of CS.
In applications where multiple clock cycles may be required
to access the configuration data before each byte can be
loaded into the Slave Parallel interface, a new byte of data
may not be ready for each consecutive CCLK edge. In such
a case the CS signal may be de-asserted until the next byte
is valid on D0-D7. While CS is High, the Slave Parallel
For more detailed information see XAPP176, Spartan-II
FPGA Family Configuration and Readback.
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Spartan-II FPGA Family: Functional Description
CCLK
CS
T
T
SMCCCS
SMCSCC
T
WRITE
T
SMWCC
SMCCW
T
SMDCC
T
SMCCD
DATA[7:0]
BUSY
T
SMCKBY
No Write
Write
No Write
Write
DS001_20_061200
Symbol
Description
Units
TSMDCC
TSMCCD
TSMCSCC
TSMCCCS
TSMCCW
TSMWCC
TSMCKBY
FCC
D0-D7 setup/hold
D0-D7 hold
5
0
ns, min
ns, min
CS setup
7
ns, min
CS hold
0
ns, min
CCLK
WRITE setup
7
ns, min
WRITE hold
0
ns, min
BUSY propagation delay
Maximum frequency
Maximum frequency with no handshake
12
66
50
ns, max
MHz, max
MHz, max
FCCNH
Figure 20: Slave Parallel Write Timing
CCLK
CS
WRITE
DATA[7:0]
BUSY
Abort
DS001_21_032300
Figure 21: Slave Parallel Write Abort Waveforms
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Spartan-II FPGA Family: Functional Description
the device configuration process until after the DLL
achieves lock.
Design Considerations
This section contains more detailed design information on
the following features:
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance
clocks.
•
•
•
Delay-Locked Loop . . . see page 27
Block RAM . . . see page 32
Versatile I/O . . . see page 36
Library DLL Primitives
Using Delay-Locked Loops
Figure 22 shows the simplified Xilinx library DLL macro,
BUFGDLL. This macro delivers a quick and efficient way to
provide a system clock with zero propagation delay
throughout the device. Figure 23 and Figure 24 show the
two library DLL primitives. These primitives provide access
to the complete set of DLL features when implementing
more complex applications.
The Spartan-II FPGA family provides up to four fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits that improve and
simplify system level design.
I
O
Introduction
0 ns
Quality on-chip clock distribution is important. Clock skew
and clock delay impact device performance and the task of
managing clock skew and clock delay with conventional
clock trees becomes more difficult in large devices. The
Spartan-II family of devices resolve this potential problem
by providing up to four fully digital dedicated on-chip
Delay-Locked Loop (DLL) circuits which provide zero
propagation delay and low clock skew between output clock
signals distributed throughout the device.
DS001_22_032300
Figure 22: Simplified DLL Macro BUFGDLL
CLKDLL
CLK0
CLKIN
CLKFB
CLK90
CLK180
CLK270
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network
minimizes clock skews due to loading differences. By
monitoring a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the
individual clock loads within the device.
CLK2X
CLKDV
LOCKED
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
RST
DS001_23_032300
Figure 23: Standard DLL Primitive CLKDLL
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at
100 MHz. This technique can simplify board design
because the clock path on the board no longer distributes
such a high-speed signal. A multiplied clock also provides
designers the option of time-domain-multiplexing, using one
circuit twice per clock cycle, consuming less area than two
copies of the same circuit.
CLKDLLHF
CLKIN
CLKFB
CLK0
CLK180
CLKDV
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to de-skew a board level clock between multiple devices.
RST
LOCKED
DS001_24_032300
In order to guarantee the system clock establishes prior to
the device "waking up," the DLL can delay the completion of
Figure 24: High-Frequency DLL Primitive CLKDLLHF
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Spartan-II FPGA Family: Functional Description
or one of the global clock input buffers (IBUFG) on the same
edge of the device (top or bottom) must source this clock
signal.
BUFGDLL Pin Descriptions
Use the BUFGDLL macro as the simplest way to provide
zero propagation delay for a high-fanout on-chip clock from
an external input. This macro uses the IBUFG, CLKDLL and
BUFG primitives to implement the most basic DLL
application as shown in Figure 25.
Feedback Clock Input — CLKFB
The DLL requires a reference or feedback signal to provide
the delay-compensated output. Connect only the CLK0 or
CLK2X DLL outputs to the feedback clock input (CLKFB)
pin to provide the necessary feedback to the DLL. Either a
global clock buffer (BUFG) or one of the global clock input
buffers (IBUFG) on the same edge of the device (top or
bottom) must source this clock signal.
IBUFG
BUFG
CLKDLL
I
O
O
I
CLKIN
CLK0
CLK90
CLK180
CLK270
CLKFB
If an IBUFG sources the CLKFB pin, the following special
rules apply.
CLK2X
CLKDV
RST
1. An external input port must source the signal that drives
the IBUFG I pin.
LOCKED
2. The CLK2X output must feed back to the device if both
the CLK0 and CLK2X outputs are driving off chip
devices.
DS001_25_032300
Figure 25: BUFGDLL Block Diagram
3. That signal must directly drive only OBUFs and nothing
else.
This macro does not provide access to the advanced clock
domain controls or to the clock multiplication or clock
division features of the DLL. This macro also does not
provide access to the RST or LOCKED pins of the DLL. For
access to these features, a designer must use the DLL
primitives described in the following sections.
These rules enable the software to determine which DLL
clock output sources the CLKFB pin.
Reset Input — RST
When the reset pin RST activates, the LOCKED signal
deactivates within four source clock cycles. The RST pin,
active High, must either connect to a dynamic signal or be
tied to ground. As the DLL delay taps reset to zero, glitches
can occur on the DLL clock output pins. Activation of the
RST pin can also severely affect the duty cycle of the clock
output pins. Furthermore, the DLL output clocks no longer
deskew with respect to one another. The DLL must be reset
when the input clock frequency changes, if the device is
reconfigured in Boundary-Scan mode, if the device
Source Clock Input — I
The I pin provides the user source clock, the clock signal on
which the DLL operates, to the BUFGDLL. For the
BUFGDLL macro the source clock frequency must fall in the
low frequency range as specified in the data sheet. The
BUFGDLL requires an external signal source clock.
Therefore, only an external input port can source the signal
that drives the BUFGDLL I pin.
Clock Output — O
undergoes a hot swap, and after the device is configured if
the input clock is not stable during the startup sequence.
The clock output pin O represents a delay-compensated
version of the source clock (I) signal. This signal, sourced
by a global clock buffer BUFG primitive, takes advantage of
the dedicated global clock routing resources of the device.
2x Clock Output — CLK2X
The output pin CLK2X provides a frequency-doubled clock
with an automatic 50/50 duty-cycle correction. Until the
CLKDLL has achieved lock, the CLK2X output appears as a
1x version of the input clock with a 25/75 duty cycle. This
behavior allows the DLL to lock on the correct edge with
respect to source clock. This pin is not available on the
CLKDLLHF primitive.
The output clock has a 50/50 duty cycle unless you
deactivate the duty cycle correction property.
CLKDLL Primitive Pin Descriptions
The library CLKDLL primitives provide access to the
complete set of DLL features needed when implementing
more complex applications with the DLL.
Clock Divide Output — CLKDV
The clock divide output pin CLKDV provides a lower
frequency version of the source clock. The CLKDV_DIVIDE
property controls CLKDV such that the source clock is
divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.
Source Clock Input — CLKIN
The CLKIN pin provides the user source clock (the clock
signal on which the DLL operates) to the DLL. The CLKIN
frequency must fall in the ranges specified in the data sheet.
A global clock buffer (BUFG) driven from another CLKDLL
This feature provides automatic duty cycle correction. The
CLKDV output pin has a 50/50 duty cycle for all values of the
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Spartan-II FPGA Family: Functional Description
division factor N except for non-integer division in High
Frequency (HF) mode. For division factor 1.5 the duty cycle
in the HF mode is 33.3% High and 66.7% Low. For division
factor 2.5, the duty cycle in the HF mode is 40.0% High and
60.0% Low.
spurious movement. In particular the CLK2X output will
appear as a 1x clock with a 25/75 duty cycle.
DLL Properties
Properties provide access to some of the Spartan-II family
DLL features, (for example, clock division and duty cycle
correction).
1x Clock Outputs — CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a
Duty Cycle Correction Property
delay-compensated version of the source clock (CLKIN)
signal. The CLKDLL primitive provides three phase-shifted
versions of the CLK0 signal while CLKDLLHF provides only
the 180 degree phase-shifted version. The relationship
between phase shift and the corresponding period shift
appears in Table 10.
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, such that they exhibit a
50/50 duty cycle. The DUTY_CYCLE_CORRECTION
property (by default TRUE) controls this feature. To
deactivate the DLL duty-cycle correction for the 1x clock
outputs, attach the DUTY_CYCLE_CORRECTION=FALSE
property to the DLL primitive.
The timing diagrams in Figure 26 illustrate the DLL clock
output characteristics.
0
90 180 270
0
90 180 270
Table 10: Relationship of Phase-Shifted Output Clock
to Period Shift
T
CLKIN
CLK2X
Phase (degrees)
Period Shift (percent)
0
0%
90
25%
50%
75%
CLKDV_DIVIDE = 2
180
270
CLKDV
DUTY_CYCLE_CORRECTION = FALSE
The DLL provides duty cycle correction on all 1x clock
outputs such that all 1x clock outputs by default have a
50/50 duty cycle. The DUTY_CYCLE_CORRECTION
property (TRUE by default), controls this feature. In order to
deactivate the DLL duty cycle correction, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL primitive. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
CLK0
CLK90
CLK180
CLK270
The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).
DUTY_CYCLE_CORRECTION = TRUE
CLK0
CLK90
CLK180
CLK270
Locked Output — LOCKED
In order to achieve lock, the DLL may need to sample
several thousand clock cycles. After the DLL achieves lock
the LOCKED signal activates. The "DLL Timing
Parameters" section of Module 3 provides estimates for
locking times.
DS001_26_032300
Figure 26: DLL Output Characteristics
In order to guarantee that the system clock is established
prior to the device "waking up," the DLL can delay the
completion of the device configuration process until after
the DLL locks. The STARTUP_WAIT property activates this
feature.
Clock Divide Property
The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.
Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other
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Spartan-II FPGA Family: Functional Description
clock period. The DLL operates reliably on an input
waveform with a frequency drift of up to 1 ns — orders of
magnitude in excess of that needed to support any crystal
oscillator in the industry. However, the cycle-to-cycle jitter
must be kept to less than 300 ps in the low frequencies and
150 ps for the high frequencies.
Startup Delay Property
This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the Startup
Sequence following device configuration is paused at a
user-specified point until the DLL locks. XAPP176:
Configuration and Readback of the Spartan-II and
Spartan-IIE Families explains how this can result in delaying
the assertion of the DONE pin until the DLL locks.
Input Clock Changes
Changing the period of the input clock beyond the
maximum drift amount requires a manual reset of the
CLKDLL. Failure to reset the DLL will produce an unreliable
lock signal and output clock.
DLL Location Constraints
The DLLs are distributed such that there is one DLL in each
corner of the device. The location constraint LOC, attached
to the DLL primitive with the numeric identifier 0, 1, 2, or 3,
controls DLL location. The orientation of the four DLLs and
their corresponding clock resources appears in Figure 27.
It is possible to stop the input clock in a way that has little
impact to the DLL. Stopping the clock should be limited to
less than approximately 100 μs to keep device cooling to a
minimum and maintain the validity of the current tap setting.
The clock should be stopped during a Low phase, and when
restored the full High period should be seen. During this
time LOCKED will stay High and remain High when the
clock is restored. If these conditions may not be met in the
design, apply a manual reset to the DLL after re-starting the
input clock, even if the LOCKED signal has not changed.
The LOC property uses the following form.
LOC = DLL2
GCLKPAD2
GCLKPAD3
When the clock is stopped, one to four more clocks will still
be observed as the delay line is flushed. When the clock is
restarted, the output clocks will not be observed for one to
four clocks as the delay line is filled. The most common
case will be two or three clocks.
DLL3
DLL2
GCLKBUF2
GCLKBUF3
In a similar manner, a phase shift of the input clock is also
possible. The phase shift will propagate to the output one to
four clocks after the original shift, with no disruption to the
CLKDLL control.
GCLKBUF1
DLL1
GCLKBUF0
DLL0
GCLKPAD0
GCLKPAD1
Output Clocks
As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or route directly to destination clock
pins. The only BUFGs that the DLL clock outputs can drive
are the two on the same edge of the device (top or bottom).
One DLL output can drive more than one OBUF; however,
this adds skew.
DS001_27_061308
Figure 27: Orientation of DLLs
Design Considerations
Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.
Input Clock
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
The output clock signal of a DLL, essentially a delayed
version of the input clock signal, reflects any instability on
the input clock in the output waveform. For this reason the
quality of the DLL input clock relates directly to the quality of
the output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the "DLL Timing
Parameters" section of the data sheet.
In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially
available quartz crystal oscillator. For example, most crystal
oscillators produce an output waveform with a frequency
tolerance of 100 PPM, meaning 0.01 percent change in the
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Spartan-II FPGA Family: Functional Description
If other clock output is needed, the clock could access a
BUFG only if the DLLs are constrained to exist on opposite
edges (Top or Bottom) of the device.
Useful Application Examples
The Spartan-II FPGA DLL can be used in a variety of
creative and useful applications. The following examples
show some of the more common applications.
CLKDLL
Standard Usage
IBUFG
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
The circuit shown in Figure 28 resembles the BUFGDLL
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
BUFG
IBUFG
CLK2X
CLKDV
CLKDLL
BUFG
CLKIN
CLKFB
CLK0
INV
CLK90
CLK180
CLK270
SRL16
RST
D
Q
LOCKED
WCLK
CLK2X
CLKDV
IBUF
OBUF
A3
CLKDLL
RST
LOCKED
A2
A1
A0
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
DS001_28_061200
Figure 28: Standard DLL Implementation
BUFG
CLK2X
CLKDV
Deskew of Clock and Its 2x Multiple
OBUF
The circuit shown in Figure 29 implements a 2x clock
multiplier and also uses the CLK0 clock output with zero ns
skew between registers on the same chip. A clock divider
circuit could alternatively be implemented using similar
connections.
RST
LOCKED
DS001_30_061200
IBUFG
CLKDLL
BUFG
Figure 30: DLL Generation of 4x Clock
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
When using this circuit it is vital to use the SRL16 cell to
reset the second DLL after the initial chip reset. If this is not
done, the second DLL may not recognize the change of
frequencies from when the input changes from a 1x (25/75)
waveform to a 2x (50/50) waveform. It is not recommended
to cascade more than two DLLs.
BUFG
OBUF
CLK2X
CLKDV
IBUF
RST
LOCKED
For design examples and more information on using the
DLL, see XAPP174, Using Delay-Locked Loops in Spartan-II
FPGAs.
DS001_29_061200
Figure 29: DLL Deskew of Clock and 2x Multiple
Because any single DLL can only access at most two
BUFGs, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
Generating a 4x Clock
By connecting two DLL circuits each implementing a 2x
clock multiplier in series as shown in Figure 30, a 4x clock
multiply can be implemented with zero skew between
registers in the same device.
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Spartan-II FPGA Family: Functional Description
Library Primitives
Using Block RAM Features
The Spartan-II FPGA family provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block RAM memory
can be independently configured as a read/write port, a
read port, a write port, and can be configured to a specific
data width. The block RAM memory offers new capabilities
allowing the FPGA designer to simplify designs.
Figure 31 and Figure 32 show the two generic library block
RAM primitives. Table 11 describes all of the available
primitives for synthesis and simulation.
RAMB4_S#_S#
WEA
ENA
DOA[#:0]
RSTA
CLKA
Operating Modes
ADDRA[#:0]
DIA[#:0]
Block RAM memory supports two operating modes.
•
•
Read Through
Write Back
WEB
ENB
RSTB
Read Through (One Clock Edge)
DOB[#:0]
CLKB
ADDRB[#:0]
DIB[#:0]
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories may place the latch/register at the outputs
depending on the desire to have a faster clock-to-out versus
setup time. This is generally considered to be an inferior
solution since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the
read pulse clock.
DS001_31_061200
Figure 31: Dual-Port Block RAM Memory
RAMB4_S#
WE
EN
RST
CLK
DO[#:0]
Write Back (One Clock Edge)
ADDR[#:0]
DI[#:0]
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the write port input.
DS001_32_061200
Figure 32: Single-Port Block RAM Memory
Block RAM Characteristics
Table 11: Available Library Primitives
1. All inputs are registered with the port clock and have a
setup to clock timing specification.
Primitive
RAMB4_S1
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
Port A Width
Port B Width
1
N/A
1
2
4
8
2. All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
3. The block RAM are true SRAM memories and do not
have a combinatorial path from the address to the
output. The LUT cells in the CLBs are still available with
this function.
16
RAMB4_S2
2
N/A
2
4
8
16
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
4. The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
5. A write operation requires only one clock edge.
6. A read operation requires only one clock edge.
The output ports are latched with a self timed circuit to
guarantee a glitch free read. The state of the output port will
not change until the port executes another read or write
operation.
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Table 11: Available Library Primitives
Reset—RST[A|B]
Primitive
Port A Width
Port B Width
The reset pin forces the data output bus latches to zero
synchronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.
RAMB4_S4
4
N/A
4
8
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
16
Address Bus—ADDR[A|B]<#:0>
RAMB4_S8
RAMB4_S8_S8
RAMB4_S8_S16
8
N/A
8
16
The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in Table 12.
RAMB4_S16
RAMB4_S16_S16
16
N/A
16
Data In Bus—DI[A|B]<#:0>
The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width,
as shown in Table 12.
Port Signals
Each block RAM port operates independently of the others
while accessing the same set of 4096 memory cells.
Data Output Bus—DO[A|B]<#:0>
The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in Table 12.
Table 12 describes the depth and width aspect ratios for the
block RAM memory.
Table 12: Block RAM Port Aspect Ratios
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
Inverting Control Pins
1
2
The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration
option.
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
4
8
Address Mapping
16
256
Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port. The physical RAM location addressed for a particular
width are described in the following formula (of interest only
when the two ports use different aspect ratios).
Clock—CLK[A|B]
Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time
referenced to the CLK pin.
Start = ([ADDRport + 1] * Widthport) – 1
End = ADDRport * Widthport
Enable—EN[A|B]
Table 13 shows low order address mapping for each port
width.
The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the
memory cells.
Table 13: Port Address Mapping
Port
Widt
h
Port
Addresses
Write Enable—WE[A|B]
Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the
contents of the memory cells referenced by the address bus
reflect on the data out bus.
1
4095... 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2
4
2047... 07 06 05 04 03 02 01 00
1023...
511...
255...
03
02
01
00
8
01
00
16
00
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Spartan-II FPGA Family: Functional Description
the DI bus. The DI bus is written to the memory location
0x0F.
Creating Larger RAM Structures
The block RAM columns have specialized routing to allow
cascading blocks together with minimal routing delays. This
achieves wider or deeper RAM structures with a smaller
timing penalty than when using normal routing channels.
At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
and the WE pin is Low indicating a read operation. The DO
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.
Location Constraints
At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low
indicating that the block RAM memory is now disabled. The
DO bus retains the last value.
Block RAM instances can have LOC properties attached to
them to constrain the placement. The block RAM placement
locations are separate from the CLB location naming
convention, allowing the LOC properties to transfer easily
from array to array.
Dual Port Timing
The LOC properties use the following form:
LOC = RAMB4_R#C#
Figure 34 shows a timing diagram for a true dual-port
read/write block RAM memory. The clock on port A has a
longer period than the clock on Port B. The timing
parameter TBCCS, (clock-to-clock setup) is shown on this
diagram. The parameter, TBCCS is violated once in the
diagram. All other timing parameters are identical to the
single port version shown in Figure 33.
RAMB4_R0C0 is the upper left RAMB4 location on the
device.
Conflict Resolution
The block RAM memory is a true dual-read/write port RAM
that allows simultaneous access of the same memory cell
from both ports. When one port writes to a given memory
cell, the other port must not address that memory cell (for a
write or a read) within the clock-to-clock setup window. The
following lists specifics of port and memory cell write conflict
resolution.
TBCCS is only of importance when the address of both ports
are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is
violated for a WRITE-WRITE condition, the contents of the
memory at that location will be invalid. When the
clock-to-clock set-up parameter is violated for a
WRITE-READ condition, the contents of the memory will be
correct, but the read port will have invalid data. At the first
rising edge of the CLKA, memory location 0x00 is to be
written with the value 0xAAAA and is mirrored on the DOA
bus. The last operation of Port B was a read to the same
memory location 0x00. The DOB bus of Port B does not
change with the new value on Port A, and retains the last
read value. A short time later, Port B executes another read
to memory location 0x00, and the DOB bus now reflects the
new memory value written by Port A.
•
If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.
•
If one port attempts a read of the same memory cell
the other simultaneously writes, violating the
clock-to-clock setup requirement, the following occurs.
-
-
The write succeeds
The data out on the writing port accurately reflects
the data written.
-
The data out on the reading port is invalid.
At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
memory location without violating the TBCCS parameter and
the DOB reflects the new memory values written by Port A.
Conflicts do not cause any physical damage.
Single Port Timing
Figure 33 shows a timing diagram for a single port of a block
RAM memory. The block RAM AC switching characteristics
are specified in the data sheet. The block RAM memory is
initially disabled.
At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus
contains the contents of the memory location, 0x00, as
indicated by the ADDR bus.
At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors
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T
T
BPWL
BPWH
CLK
T
T
BACK
00
ADDR
0F
7E
8F
BDCK
DDDD
CCCC
BBBB
2222
DIN
DOUT
EN
T
BCKO
MEM (00)
CCCC
MEM (7E)
T
BECK
RST
WE
T
BWCK
DISABLED
READ
WRITE
READ
DISABLED
DS001_33_061200
Figure 33: Timing Diagram for Single-Port Block RAM Memory
T
BCCS
VIOLATION
CLK_A
ADDR_A
00
7E
0F
0F
7E
EN_A
WE_A
DI_A
T
BCCS
T
BCCS
AAAA
9999
AAAA
0000
1111
AAAA
9999
AAAA
UNKNOWN
2222
DO_A
CLK_B
ADDR_B
00
00
7E
0F
0F
7E
1A
EN_B
WE_B
DI_B
1111
1111
1111
BBBB
1111
2222
FFFF
DO_B
MEM (00)
AAAA
9999
BBBB
UNKNOWN
2222
FFFF
DS001_34_061200
Figure 34: Timing Diagram for a True Dual-Port Read/Write Block RAM Memory
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At the third rising edge of CLKA, the TBCCS parameter is
violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x7E is invalid.
Table 14: RAM Initialization Properties
Property
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0a
INIT_0b
INIT_0c
INIT_0d
INIT_0e
INIT_0f
Memory Cells
1535 to 1280
1791 to 1536
2047 to 1792
2303 to 2048
2559 to 2304
2815 to 2560
3071 to 2816
3327 to 3072
3583 to 3328
3839 to 3584
4095 to 3840
At the fourth rising edge of CLKA, a read operation is
performed at memory location 0x0F and invalid data is
present on the DOA bus. Port B also executes a read
operation to memory location 0x0F and also reads invalid
data.
At the fifth rising edge of CLKA a read operation is
performed that does not violate the TBCCS parameter to the
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
Initialization
The block RAM memory can initialize during the device
configuration sequence. The 16 initialization properties of
64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in Table 14. Any
initialization properties not explicitly set configure as zeros.
Partial initialization strings pad with zeros. Initialization
strings greater than 64 hex values generate an error. The
RAMs can be simulated with the initialization values using
generics in VHDL simulators and parameters in Verilog
simulators.
For design examples and more information on using the
Block RAM, see XAPP173, Using Block SelectRAM+
Memory in Spartan-II FPGAs.
Using Versatile I/O
The Spartan-II FPGA family includes a highly configurable,
high-performance I/O resource called Versatile I/O to
provide support for a wide variety of I/O standards. The
Versatile I/O resource is a robust set of features including
programmable control of output drive strength, slew rate,
and input delay and hold time. Taking advantage of the
flexibility and Versatile I/O features and the design
considerations described in this document can improve and
simplify system level design.
Initialization in VHDL
The block RAM structures may be initialized in VHDL for
both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization.
Initialization in Verilog
The block RAM structures may be initialized in Verilog for
both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a
defparam to pass the initialization.
Introduction
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for
Block Memory Generation
high-performance I/O becomes more important. While
chip-to-chip delays have an increasingly substantial impact
on overall system speed, the task of achieving the desired
system performance becomes more difficult with the
proliferation of low-voltage I/O standards. Versatile I/O, the
revolutionary input/output resources of Spartan-II devices,
has resolved this potential problem by providing a highly
configurable, high-performance alternative to the I/O
resources of more conventional programmable devices.
The Spartan-II FPGA Versatile I/O features combine the
flexibility and time-to-market advantages of programmable
logic with the high performance previously available only
with ASICs and custom ICs.
The CORE Generator™ software generates memory
structures using the block RAM features. This program
outputs VHDL or Verilog simulation code templates and an
EDIF file for inclusion in a design.
Table 14: RAM Initialization Properties
Property
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
Memory Cells
255 to 0
511 to 256
767 to 512
1023 to 768
1279 to 1024
Each Versatile I/O block can support up to 16 I/O standards.
Supporting such a variety of I/O standards allows the
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support of a wide variety of applications, from general
purpose standard applications to high-speed low-voltage
memory busses.
Table 15: Versatile I/O Supported Standards (Typical
Values)
Input
Reference Source Termination
Voltage Voltage Voltage
Output
Board
Versatile I/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL
output buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak "keeper" circuit ideal for
use in external bussing applications.
I/O Standard
LVTTL (2-24 mA)
LVCMOS2
(VREF
)
(VCCO
)
(VTT
N/A
N/A
N/A
)
N/A
3.3
N/A
2.5
Each Input/Output Block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
PCI (3V/5V,
N/A
3.3
33 MHz/66 MHz)
GTL
0.8
1.0
N/A
N/A
1.5
1.5
1.5
3.3
1.2
1.5
The input buffer has an optional delay element used to
guarantee a zero hold time requirement for input signals
registered within the IOB.
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
0.75
0.9
0.9
0.75
1.5
1.5
The Versatile I/O features also provide dedicated resources
for input reference voltage (VREF) and output source
voltage (VCCO), along with a convenient banking system
that simplifies board design.
SSTL3 Class I
and II
1.5
1.5
By taking advantage of the built-in features and wide variety
of I/O standards supported by the Versatile I/O features,
system-level design and board design can be greatly
simplified and improved.
SSTL2 Class I
and II
1.25
2.5
1.25
CTT
1.5
3.3
3.3
1.5
Fundamentals
AGP-2X
1.32
N/A
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored
specifically to the needs of that application. The bus I/O
standards provide specifications to other vendors who
create products designed to interface with these
applications. Each standard often has its own specifications
for current, voltage, I/O buffering, and termination
techniques.
Overview of Supported I/O Standards
This section provides a brief overview of the I/O standards
supported by all Spartan-II devices.
While most I/O standards specify a range of allowed
voltages, this document records typical voltage values only.
Detailed information on each specification may be found on
the Electronic Industry Alliance JEDEC website at
http://www.jedec.org. For more details on the I/O standards
and termination application examples, see XAPP179, "Using
SelectIO Interfaces in Spartan-II and Spartan-IIE FPGAs."
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly
dependent on the capability of the programmable logic
device to support an ever increasing variety of I/O
standards
LVTTL — Low-Voltage TTL
The Low-Voltage TTL (LVTTL) standard is a general
purpose EIA/JESDSA standard for 3.3V applications that
uses an LVTTL input buffer and a Push-Pull output buffer.
This standard requires a 3.3V output source voltage
(VCCO), but does not require the use of a reference voltage
(VREF) or a termination voltage (VTT).
The Versatile I/O resources feature highly configurable
input and output buffers which provide support for a wide
variety of I/O standards. As shown in Table 15, each buffer
type can support a variety of voltage requirements.
LVCMOS2 — Low-Voltage CMOS for 2.5V
The Low-Voltage CMOS for 2.5V or lower (LVCMOS2)
standard is an extension of the LVCMOS standard (JESD
8.5) used for general purpose 2.5V applications. This
standard requires a 2.5V output source voltage (VCCO), but
does not require the use of a reference voltage (VREF) or a
board termination voltage (VTT).
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PCI — Peripheral Component Interface
AGP-2X — Advanced Graphics Port
The Peripheral Component Interface (PCI) standard
specifies support for both 33 MHz and 66 MHz PCI bus
applications. It uses a LVTTL input buffer and a push-pull
output buffer. This standard does not require the use of a
reference voltage (VREF) or a board termination voltage
(VTT), however, it does require a 3.3V output source voltage
(VCCO). I/Os configured for the PCI, 33 MHz, 5V standard
are also 5V-tolerant.
The AGP standard is a 3.3V Advanced Graphics Port-2X
bus standard used with processors for graphics
applications. This standard requires a Push-Pull output
buffer and a Differential Amplifier input buffer.
Library Primitives
The Xilinx library includes an extensive list of primitives
designed to provide support for the variety of Versatile I/O
features. Most of these primitives represent variations of the
five generic Versatile I/O primitives:
GTL — Gunning Transceiver Logic Terminated
The Gunning Transceiver Logic (GTL) standard is a
high-speed bus standard (JESD8.3). Xilinx has
implemented the terminated variation of this standard. This
standard requires a differential amplifier input buffer and an
open-drain output buffer.
•
•
•
•
•
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
GTL+ — Gunning Transceiver Logic Plus
The Gunning Transceiver Logic Plus (GTL+) standard is a
high-speed bus standard (JESD8.3).
These primitives are available with various extensions to
define the desired I/O standard. However, it is
recommended that customers use a a property or attribute
on the generic primitive to specify the I/O standard. See
"Versatile I/O Properties".
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic (HSTL) standard is a
general purpose high-speed, 1.5V bus standard (EIA/JESD
8-6). This standard has four variations or classes. Versatile
I/O devices support Class I, III, and IV. This standard
requires a Differential Amplifier input buffer and a Push-Pull
output buffer.
IBUF
Signals used as inputs to the Spartan-II device must source
an input buffer (IBUF) via an external input port. The generic
IBUF primitive appears in Figure 35. The assumed standard
is LVTTL when the generic IBUF has no specified extension
or property.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3V (SSTL3)
standard is a general purpose 3.3V memory bus standard
(JESD8-8). This standard has two classes, I and II.
Versatile I/O devices support both classes for the SSTL3
standard. This standard requires a Differential Amplifier
input buffer and an Push-Pull output buffer.
IBUF
I
O
DS001_35_061200
SSTL2 — Stub Series Terminated Logic for 2.5V
Figure 35: Input Buffer (IBUF) Primitive
The Stub Series Terminated Logic for 2.5V (SSTL2)
standard is a general purpose 2.5V memory bus standard
(JESD8-9). This standard has two classes, I and II.
Versatile I/O devices support both classes for the SSTL2
standard. This standard requires a Differential Amplifier
input buffer and an Push-Pull output buffer.
When the IBUF primitive supports an I/O standard such as
LVTTL, LVCMOS, or PCI33_5, the IBUF automatically
configures as a 5V tolerant input buffer unless the VCCO for
the bank is less than 2V. If the single-ended IBUF is placed
in a bank with an HSTL standard (VCCO < 2V), the input
buffer is not 5V tolerant.
CTT — Center Tap Terminated
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all
packages there are eight independent VREF banks
internally. See Figure 36 for a representation of the I/O
banks. Within each bank approximately one of every six I/O
pins is automatically configured as a VREF input.
The Center Tap Terminated (CTT) standard is a 3.3V
memory bus standard (JESD8-4). This standard requires a
Differential Amplifier input buffer and a Push-Pull output
buffer.
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same
standard. How to specify a specific location for the IBUF via
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Spartan-II FPGA Family: Functional Description
the LOC property is described below. Table 16 summarizes
the input standards compatibility requirements.
only drive a CLKDLL, CLKDLLHF, or a BUFG primitive. The
generic IBUFG primitive appears in Figure 37.
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.
IBUFG
I
O
When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher
performance. To delay the input signal, activate the delay
element with the DELAY=TRUE property.
DS001_37_061200
Figure 37: Global Clock Input Buffer (IBUFG) Primitive
With no extension or property specified for the generic
IBUFG primitive, the assumed standard is LVTTL.
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all
packages there are eight independent VREF banks
internally. See Figure 36 for a representation of the I/O
banks. Within each bank approximately one of every six I/O
pins is automatically configured as a VREF input.
Bank 0
Bank 1
GCLK3 GCLK2
Spartan-II
Device
IBUFG placement restrictions require any differential
amplifier input signals within a bank be of the same
standard. The LOC property can specify a location for the
IBUFG.
GCLK1 GCLK0
As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP primitive
represents a combination of the LVTTL IBUFG and BUFG
primitives, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
Bank 5
Bank 4
DS001_03_060100
Figure 36: I/O Banks
The Spartan-II FPGA BUFGP primitive can only be placed
in a global clock pad location. The LOC property can specify
a location for the BUFGP.
Table 16: Xilinx Input Standards Compatibility
Requirements
OBUF
Rule 1 All differential amplifier input signals within a
bank are required to be of the same standard.
An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) primitive appears in
Figure 38.
Rule 2 There are no placement restrictions for inputs
with standards that require a single-ended input
buffer.
OBUF
I
O
IBUFG
Signals used as high fanout clock inputs to the
Spartan-II device should drive a global clock input buffer
(IBUFG) via an external input port in order to take
advantage of one of the four dedicated global clock
distribution networks. The output of the IBUFG primitive can
DS001_38_061200
Figure 38: Output Buffer (OBUF) Primitive
With no extension or property specified for the generic
OBUF primitive, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
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Spartan-II FPGA Family: Functional Description
LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF primitive names is as follows.
OBUF_<slew_rate>_<drive_strength>
<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
IOBUFT
T
<slew_rate> is either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24). The default is slew rate limited with 12 mA drive.
I
IO
OBUF placement restrictions require that within a given
VCCO bank each OBUF share the same output source drive
voltage. Input buffers of any type and output buffers that do
not require VCCO can be placed within any VCCO bank.
Table 17 summarizes the output compatibility requirements.
The LOC property can specify a location for the OBUF.
DS001_39_032300
Figure 39: 3-State Output Buffer Primitive (OBUFT
The Versatile I/O OBUFT placement restrictions require
that within a given VCCO bank each OBUFT share the same
output source drive voltage. Input buffers of any type and
output buffers that do not require VCCO can be placed within
the same VCCO bank.
Table 17: Output Standards Compatibility
Requirements
Rule 1 Only outputs with standards which share
compatible VCCO may be used within the same
bank.
The LOC property can specify a location for the OBUFT.
Rule 2 There are no placement restrictions for outputs
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak "keeper" circuit. Control this feature by adding the
appropriate primitive to the output net of the OBUFT
(PULLUP, PULLDOWN, or KEEPER).
with standards that do not require a VCCO
.
VCCO Compatible Standards
3.3
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
The weak "keeper" circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
an I/O standard that requires a VREF have automatic
placement of a VREF in the bank with an OBUFT configured
with a weak "keeper" circuit. This restriction does not affect
most circuit design as applications using an OBUFT
configured with a weak "keeper" typically implement a
bidirectional I/O. In this case the IBUF (and the
2.5
1.5
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
OBUFT
The generic 3-state output buffer OBUFT, shown in
Figure 39, typically implements 3-state outputs or
bidirectional I/O.
corresponding VREF) are explicitly placed.
The LOC property can specify a location for the OBUFT.
With no extension or property specified for the generic
OBUFT primitive, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
IOBUF
Use the IOBUF primitive for bidirectional signals that
require both an input buffer and a 3-state output buffer with
an active high 3-state pin. The generic input/output buffer
IOBUF appears in Figure 40.
The LVTTL OBUFT can support one of two slew rate modes
to minimize bus transients. By default, the slew rate for each
output buffer is reduced to minimize power bus transients
when switching non-critical signals.
With no extension or property specified for the generic
IOBUF primitive, the assumed standard is LVTTL input
buffer and slew rate limited LVTTL with 12 mA drive strength
for the output buffer.
LVTTL 3-state output buffers have selectable drive
strengths.
The format for LVTTL OBUFT primitive names is as follows.
OBUFT_<slew_rate>_<drive_strength>
The LVTTL IOBUF can support one of two slew rate modes
to minimize bus transients. By default, the slew rate for each
output buffer is reduced to minimize power bus transients
when switching non-critical signals.
LVTTL bidirectional buffers have selectable output drive
strengths.
The format for LVTTL IOBUF primitive names is as follows:
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Spartan-II FPGA Family: Functional Description
IOBUF_<slew_rate>_<drive_strength>
Versatile I/O Properties
<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
Access to some of the Versatile I/O features (for example,
location constraints, input delay, output drive strength, and
slew rate) is available through properties associated with
these features.
Input Delay Properties
IOBUF
T
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element activates by default to ensure a zero hold-time
requirement. Use the NODELAY=TRUE property to
override this default.
I
IO
In the case when the IBUF does not drive a flip-flop within
the IOB, the delay element by default de-activates to
provide higher performance. To delay the input signal,
activate the delay element with the DELAY=TRUE property.
O
DS001_40_061200
Figure 40: Input/Output Buffer Primitiveprimitive
IOB Flip-Flop/Latch Property
(IOBUF)
The I/O Block (IOB) includes an optional register on the
input path, an optional register on the output path, and an
optional register on the 3-state control pin. The design
implementation software automatically takes advantage of
these registers when the following option for the Map
program is specified:
When the IOBUF primitive supports an I/O standard such
as LVTTL, LVCMOS, or PCI33_5, the IBUF automatically
configures as a 5V tolerant input buffer unless the VCCO for
the bank is less than 2V. If the single-ended IBUF is placed
in a bank with an HSTL standard (VCCO < 2V), the input
buffer is not 5V tolerant.
map -pr b <filename>
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all
packages there are eight independent VREF banks
internally. See Figure 36, page 39 for a representation of
the Spartan-II FPGA I/O banks. Within each bank
approximately one of every six I/O pins is automatically
configured as a VREF input.
Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.
Location Constraints
Specify the location of each Versatile I/O primitive with the
location constraint LOC attached to the Versatile I/O
primitive. The external port identifier indicates the value of
the location constrain. The format of the port identifier
depends on the package chosen for the specific design.
Additional restrictions on the Versatile I/O IOBUF
placement require that within a given VCCO bank each
IOBUF must share the same output source drive voltage.
Input buffers of any type and output buffers that do not
require VCCO can be placed within the same VCCO bank.
The LOC property can specify a location for the IOBUF.
The LOC properties use the following form:
LOC=A42
LOC=P37
An optional delay element is associated with the input path
in each IOBUF. When the IOBUF drives an input flip-flop
within the IOB, the delay element activates by default to
ensure a zero hold-time requirement. Override this default
with the NODELAY=TRUE property.
Output Slew Rate Property
In the case of the LVTTL output buffers (OBUF, OBUFT, and
IOBUF), slew rate control can be programmed with the
SLEW= property. By default, the slew rate for each output
buffer is reduced to minimize power bus transients when
switching non-critical signals. The SLEW= property has one
of the two following values.
In the case when the IOBUF does not drive an input flip-flop
within the IOB, the delay element de-activates by default to
provide higher performance. To delay the input signal,
activate the delay element with the DELAY=TRUE property.
SLEW=SLOW
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak "keeper" circuit. Control this feature by adding the
appropriate primitive to the output net of the IOBUF
(PULLUP, PULLDOWN, or KEEPER).
SLEW=FAST
Output Drive Strength Property
For the LVTTL output buffers (OBUF, OBUFT, and IOBUF,
the desired drive strength can be specified with the DRIVE=
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Spartan-II FPGA Family: Functional Description
property. This property could have one of the following
seven values.
Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or
non-existent) termination or changes in the transmission
line impedance cause these reflections and can cause
additional delay in longer traces. As system speeds
continue to increase, the effect of I/O delays can become a
limiting factor and therefore transmission line termination
becomes increasingly more important.
DRIVE=2
DRIVE=4
DRIVE=6
DRIVE=8
DRIVE=12 (Default)
DRIVE=16
DRIVE=24
Termination Techniques
A variety of termination techniques reduce the impact of
transmission line effects.
The following lists output termination techniques:
Design Considerations
None
Reference Voltage (V
) Pins
Series
REF
Parallel (Shunt)
Series and Parallel (Series-Shunt)
Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (VREF). Provide
the VREF as an external signal to the device.
Input termination techniques include the following:
The voltage reference signal is "banked" within the device
on a half-edge basis such that for all packages there are
eight independent VREF banks internally. See Figure 36,
page 39 for a representation of the I/O banks. Within each
bank approximately one of every six I/O pins is
None
Parallel (Shunt)
These termination techniques can be applied in any
combination. A generic example of each combination of
termination methods appears in Figure 41.
automatically configured as a VREF input.
Within each VREF bank, any input buffers that require a
VREF signal must be of the same type. Output buffers of any
type and input buffers can be placed without requiring a
reference voltage within the same VREF bank.
Unterminated
Double Parallel Terminated
V
V
TT
TT
Z=50
Z=50
V
REF
Output Drive Source Voltage (V
) Pins
CCO
Unterminated Output Driving
a Parallel Terminated Input
Series Terminated Output Driving
a Parallel Terminated Input
Many of the low voltage I/O standards supported by
Versatile I/Os require a different output drive source voltage
(VCCO). As a result each device can often have to support
multiple output drive source voltages.
V
V
TT
TT
Z=50
Z=50
V
V
REF
REF
The VCCO supplies are internally tied together for some
packages. The VQ100 and the PQ208 provide one
combined VCCO supply. The TQ144 and the CS144
packages provide four independent VCCO supplies. The
FG256 and the FG456 provide eight independent VCCO
supplies.
Series-Parallel Terminated Output
Driving a Parallel Terminated Input
Series Terminated Output
V
V
TT
TT
Z=50
Z=50
V
V
REF
REF
DS001_41_032300
Output buffers within a given VCCO bank must share the
same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, PCI33_3, and PCI 66_3 use the VCCO voltage
for Input VCCO voltage.
Figure 41: Overview of Standard Input and Output
Termination Methods
Simultaneous Switching Guidelines
Transmission Line Effects
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short
distance. Transmission line delays vary with inductance
and capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
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Spartan-II FPGA Family: Functional Description
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Table 18: Maximum Number of Simultaneously
Switching Outputs per Power/Ground Pair
Package
PQ,
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Standard
SSTL2 Class II
CS, FG TQ, VQ
10
11
7
5
6
4
7
5
SSTL3 Class I
SSTL3 Class II
CTT
14
9
Table 18 provides the guidelines for the maximum number
of simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce.
Refer to Table 19 for the number of effective output
power/ground pairs for each Spartan-II device and package
combination.
AGP
Notes:
1. This analysis assumes a 35 pF load for each output.
Table 19: Effective Output Power/Ground Pairs for
Table 18: Maximum Number of Simultaneously
Spartan-II Devices
Switching Outputs per Power/Ground Pair
Spartan-II Devices
Package
XC2S XC2S XC2S XC2S
XC2S
150
XC2S
200
Pkg.
15
30
50
100
PQ,
Standard
CS, FG TQ, VQ
VQ100
CS144
TQ144
PQ208
FG256
FG456
8
8
-
-
-
-
-
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVCMOS2
68
41
29
22
17
14
9
36
20
15
12
9
12
12
-
12
12
16
-
-
-
-
12
16
16
-
12
16
16
48
-
-
16
16
48
16
16
48
-
-
-
7
Termination Examples
5
Creating a design with the Versatile I/O features requires
the instantiation of the desired library primitive within the
design code. At the board level, designers need to know the
termination techniques required for each I/O standard.
40
24
17
13
10
8
21
12
9
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the Versatile I/O
features. For a full range of accepted values for the DC
voltage specifications for each standard, refer to the table
associated with each figure.
7
5
4
5
3
10
8
5
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
PCI
4
GTL
4
4
GTL+
4
4
HSTL Class I
18
9
9
HSTL Class III
5
HSTL Class IV
5
3
SSTL2 Class I
15
8
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Spartan-II FPGA Family: Functional Description
GTL
Table 21: GTL+ Voltage Specifications
Parameter
Min
Typ
-
Max
A sample circuit illustrating a valid termination technique for
GTL is shown in Figure 42. Table 20 lists DC voltage
specifications for the GTL standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
VCCO
REF = N × VTT
-
0.88
1.35
0.98
-
-
1.12
1.65
-
(1)
V
1.0
1.5
1.1
0.9
-
VTT
VIH ≥ VREF + 0.1
VIL ≤ VREF – 0.1
VOH
GTL
V
= 1.2V
V
= 1.2V
TT
TT
1.02
-
50Ω
50Ω
-
V
= NA
CCO
Z = 50
VOL
0.3
-
0.45
-
0.6
-
V
= 0.8V
REF
I
I
I
OH at VOH (mA)
DS001_43_061200
OL at VOL (mA) at 0.6V
OL at VOL (mA) at 0.3V
36
-
-
-
Figure 42: Terminated GTL
Table 20: GTL Voltage Specifications
-
48
Notes:
1. N must be greater than or equal to 0.653 and less than or
equal to 0.68.
Parameter
Min
Typ
Max
VCCO
-
N/A
0.8
1.2
0.85
0.75
-
-
0.86
1.26
-
HSTL Class I
(1)
VREF = N × VTT
0.74
A sample circuit illustrating a valid termination technique for
HSTL_I appears in Figure 44. DC voltage specifications
appear in Table 22 for the HSTL_1 standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
VTT
1.14
VIH ≥ VREF + 0.05
VIL ≤ VREF – 0.05
VOH
0.79
-
-
0.81
-
HSTL Class I
VOL
-
0.2
-
0.4
-
V
= 0.75V
TT
V
= 1.5V
I
I
I
OH at VOH (mA)
-
CCO
50Ω
OL at VOL (mA) at 0.4V
OL at VOL (mA) at 0.2V
32
-
-
-
Z = 50
-
40
V
= 0.75V
REF
Notes:
DS001_44_061200
1. N must be greater than or equal to 0.653 and less than or
equal to 0.68.
Figure 44: Terminated HSTL Class I
Table 22: HSTL Class I Voltage Specification
GTL+
A sample circuit illustrating a valid termination technique for
GTL+ appears in Figure 43. DC voltage specifications
appear in Table 21 for the GTL+ standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
Parameter
VCCO
Min
Typ
Max
1.40
1.50
1.60
VREF
VTT
VIH
0.68
0.75
0.90
-
VCCO × 0.5
-
VREF + 0.1
-
-
-
-
-
GTL+
V
= 1.5V
V
= 1.5V
TT
TT
VIL
VREF – 0.1
50Ω
50Ω
VOH
VOL
VCCO – 0.4
-
0.4
-
V
= NA
CCO
Z = 50
V
= 1.0V
REF
I
OH at VOH (mA)
OL at VOL (mA)
–8
8
-
-
DS001_43_061200
I
-
Figure 43: Terminated GTL+
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Spartan-II FPGA Family: Functional Description
HSTL Class III
HSTL Class IV
A sample circuit illustrating a valid termination technique for
HSTL_III appears in Figure 45. DC voltage specifications
appear in Table 23 for the HSTL_III standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in Figure 46.DC voltage specifications
appear in Table 23 for the HSTL_IV standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics
HSTL Class III
HSTL Class IV
V
= 1.5V
V
= 1.5V
V
= 1.5V
TT
TT
TT
V
= 1.5V
V
= 1.5V
CCO
CCO
50Ω
50Ω
50Ω
Z = 50
Z = 50
V
= 0.9V
V
= 0.9V
REF
REF
DS001_45_061200
DS001_46_061200
Figure 46: Terminated HSTL Class IV
Figure 45: Terminated HSTL Class III
Table 23: HSTL Class III Voltage Specification
Table 24: HSTL Class IV Voltage Specification
Parameter
VCCO
Min
Typ
Max
Parameter
VCCO
Min
Typ
Max
1.40
1.50
1.60
1.40
1.50
1.60
(1)
VREF
VTT
VIH
-
0.90
-
VREF
VTT
VIH
-
0.90
-
-
VCCO
-
-
VCCO
-
VREF + 0.1
-
-
-
-
-
-
-
VREF + 0.1
-
-
-
-
-
-
-
VIL
-
VREF – 0.1
VIL
-
VREF – 0.1
VOH
VOL
VCCO – 0.4
-
0.4
-
VOH
VOL
VCCO – 0.4
-
0.4
-
-
-
I
OH at VOH (mA)
OL at VOL (mA)
–8
48
I
OH at VOH (mA)
OL at VOL (mA)
–8
24
I
-
I
-
Notes:
Notes:
1. Per EIA/JESD8-6, "The value of VREF is to be selected by the
user to provide optimum noise margin in the use conditions
specified by the user."
1. Per EIA/JESD8-6, "The value of VREF is to be selected by the
user to provide optimum noise margin in the use conditions
specified by the user."
DS001-2 (v2.8) June 13, 2008
Product Specification
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Module 2 of 4
45
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Spartan-II FPGA Family: Functional Description
SSTL3 Class I
SSTL3 Class II
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in Figure 47. DC voltage specifications
appear in Table 25 for the SSTL3_I standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in Figure 48. DC voltage specifications
appear in Table 26 for the SSTL3_II standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
SSTL3 Class I
SSTL3 Class II
V
= 1.5V
V
= 1.5V
V
= 1.5V
TT
TT
TT
V
= 3.3V
V
= 3.3V
CCO
CCO
50Ω
50Ω
50Ω
25Ω
25Ω
Z = 50
Z = 50
V
= 1.5V
V
= 1.5V
REF
REF
DS001_47_061200
DS001_48_061200
Figure 47: Terminated SSTL3 Class I
Table 25: SSTL3_I Voltage Specifications
Figure 48: Terminated SSTL3 Class II
Table 26: SSTL3_II Voltage Specifications
Parameter
Min
3.0
1.3
1.3
1.5
–0.3(2)
1.9
-
Typ
3.3
1.5
1.5
1.7
1.3
-
Max
3.6
1.7
1.7
3.9(1)
1.5
-
Parameter
Min
3.0
1.3
1.3
1.5
–0.3(2)
2.1
-
Typ
3.3
1.5
1.5
1.7
1.3
-
Max
3.6
1.7
1.7
3.9(1)
1.5
-
VCCO
VCCO
V
REF = 0.45 × VCCO
V
REF = 0.45 × VCCO
V
TT = VREF
V
TT = VREF
VIH ≥ VREF + 0.2
VIL ≤ VREF – 0.2
VOH ≥ VREF + 0.6
VOL ≤ VREF – 0.6
VIH ≥ VREF + 0.2
VIL ≤ VREF – 0.2
VOH ≥ VREF + 0.8
VOL ≤ VREF – 0.8
-
1.1
-
-
0.9
-
I
OH at VOH (mA)
OL at VOL (mA)
–8
-
I
OH at VOH (mA)
OL at VOL (mA)
–16
16
-
I
8
-
-
I
-
-
Notes:
Notes:
1. VIH maximum is VCCO + 0.3.
1. VIH maximum is VCCO + 0.3
2. VIL minimum does not conform to the formula.
2. VIL minimum does not conform to the formula
DS001-2 (v2.8) June 13, 2008
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Module 2 of 4
46
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Spartan-II FPGA Family: Functional Description
SSTL2_I
SSTL2 Class II
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in Figure 49. DC voltage specifications
appear in Table 27 for the SSTL2_I standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics
A sample circuit illustrating a valid termination technique for
SSTL2_II appears in Figure 50. DC voltage specifications
appear in Table 28 for the SSTL2_II standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
SSTL2 Class I
SSTL2 Class II
V
= 1.25V
V
= 1.25V
V
= 1.25V
TT
TT
TT
V
= 2.5V
V
= 2.5V
CCO
CCO
50Ω
50Ω
50Ω
25Ω
25Ω
Z = 50
Z = 50
V
= 1.25V
V
= 1.25V
REF
REF
DS001_49_061200
DS001_50_061200
Figure 49: Terminated SSTL2 Class I
Table 27: SSTL2_I Voltage Specifications
Figure 50: Terminated SSTL2 Class II
Table 28: SSTL2_II Voltage Specifications
Parameter
Min
2.3
Typ
2.5
1.25
1.25
1.43
1.07
-
Max
2.7
1.35
1.39
3.0(2)
1.17
-
Parameter
Min
2.3
Typ
2.5
1.25
1.25
1.43
1.07
-
Max
2.7
1.35
1.39
3.0(2)
1.17
-
VCCO
VCCO
V
REF = 0.5 × VCCO
TT = VREF + N(1)
1.15
1.11
1.33
–0.3(3)
1.76
-
V
REF = 0.5 × VCCO
TT = VREF + N(1)
1.15
1.11
1.33
–0.3(3)
1.95
-
V
V
VIH ≥ VREF + 0.18
VIL ≤ VREF – 0.18
VOH ≥ VREF + 0.61
VOL ≤ VREF – 0.61
VIH ≥ VREF + 0.18
VIL ≤ VREF – 0.18
VOH ≥ VREF + 0.8
VOL ≤ VREF - 0.8
-
0.74
-
-
0.55
-
I
OH at VOH (mA)
OL at VOL (mA)
–7.6
7.6
-
I
OH at VOH (mA)
OL at VOL (mA)
–15.2
15.2
-
I
-
-
I
-
-
Notes:
Notes:
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2. VIH maximum is VCCO + 0.3.
2. VIH maximum is VCCO + 0.3.
3.
VIL minimum does not conform to the formula.
3.
VIL minimum does not conform to the formula.
DS001-2 (v2.8) June 13, 2008
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Module 2 of 4
47
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Spartan-II FPGA Family: Functional Description
CTT
PCI33_3 and PCI66_3
A sample circuit illustrating a valid termination technique for
CTT appear in Figure 51. DC voltage specifications appear
in Table 29 for the CTT standard. See "DC Specifications" in
Module 3 for the actual FPGA characteristics .
PCI33_3 or PCI66_3 require no termination. DC voltage
specifications appear in Table 30 for the PCI33_3 and
PCI66_3 standards. See "DC Specifications" in Module 3
for the actual FPGA characteristics.
Table 30: PCI33_3 and PCI66_3 Voltage Specifications
CTT
V
= 1.5V
TT
Parameter
Min
3.0
-
Typ
Max
V
= 3.3V
CCO
VCCO
VREF
VTT
3.3
3.6
50Ω
-
-
Z = 50
V
= 1.5V
-
-
-
REF
DS001_51_061200
V
IH = 0.5 × VCCO
1.5
–0.5
2.7
-
1.65
VCCO+ 0.5
Figure 51: Terminated CTT
Table 29: CTT Voltage Specifications
VIL = 0.3 × VCCO
0.99
1.08
V
OH = 0.9 × VCCO
OL = 0.1 × VCCO
-
-
-
-
-
V
0.36
Parameter
Min
2.05(1)
1.35
1.35
1.55
-
Typ
3.3
1.5
1.5
1.7
1.3
1.9
1.1
-
Max
I
OH at VOH (mA)
OL at VOL (mA)
Note 1
Note 1
-
-
VCCO
VREF
VTT
3.6
I
1.65
Notes:
1.65
1. Tested according to the relevant specification.
VIH ≥ VREF + 0.2
VIL ≤ VREF – 0.2
VOH ≥ VREF + 0.4
VOL ≤ VREF – 0.4
-
1.45
PCI33_5
1.75
-
-
PCI33_5 requires no termination. DC voltage specifications
appear in Table 31 for the PCI33_5 standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
1.25
I
OH at VOH (mA)
OL at VOL (mA)
–8
-
-
I
8
-
Table 31: PCI33_5 Voltage Specifications
Notes:
1. Timing delays are calculated based on VCCO min of 3.0V.
Parameter
Min
3.0
Typ
Max
VCCO
VREF
VTT
3.3
3.6
-
-
-
-
-
-
5.5
1.05
-
VIH
1.425
–0.5
2.4
1.5
VIL
1.0
VOH
VOL
-
-
-
-
-
0.55
-
I
OH at VOH (mA)
OL at VOL (mA)
Note 1
Note 1
I
-
Notes:
1. Tested according to the relevant specification.
DS001-2 (v2.8) June 13, 2008
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Module 2 of 4
48
R
Spartan-II FPGA Family: Functional Description
LVTTL
AGP-2X
LVTTL requires no termination. DC voltage specifications
appears in Table 32 for the LVTTL standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
The specification for the AGP-2X standard does not
document a recommended termination technique. DC
voltage specifications appear in Table 34 for the AGP-2X
standard. See "DC Specifications" in Module 3 for the actual
FPGA characteristics.
Table 32: LVTTL Voltage Specifications
Table 34: AGP-2X Voltage Specifications
Parameter
Min
3.0
-
Typ
Max
Parameter
Min
3.0
Typ
3.3
1.32
-
Max
VCCO
VREF
VTT
3.3
3.6
VCCO
REF = N × VCCO
3.6
-
-
-
-
-
-
-
-
-
-
(1)
V
1.17
-
1.48
-
VTT
-
VIH
2.0
–0.5
2.4
-
5.5
0.8
-
VIH ≥ VREF + 0.2
VIL ≤ VREF – 0.2
VOH ≥ 0.9 × VCCO
VOL ≤ 0.1 × VCCO
1.37
-
1.52
1.12
3.0
0.33
-
-
VIL
1.28
VOH
VOL
2.7
-
0.4
-
-
0.36
I
OH at VOH (mA)
OL at VOL (mA)
–24
24
I
OH at VOH (mA)
OL at VOL (mA)
Note 2
Note 2
-
-
I
-
I
-
Notes:
1. OL and VOH for lower drive currents sample tested.
V
Notes:
1. N must be greater than or equal to 0.39 and less than or
equal to 0.41.
2. Tested according to the relevant specification.
LVCMOS2
LVCMOS2 requires no termination. DC voltage
specifications appear in Table 33 for the LVCMOS2
standard. See "DC Specifications" in Module 3 for the actual
FPGA characteristics.
For design examples and more information on using the I/O,
see XAPP179, Using SelectIO Interfaces in Spartan-II and
Spartan-IIE FPGAs.
Table 33: LVCMOS2 Voltage Specifications
Parameter
Min
2.3
-
Typ
Max
VCCO
VREF
VTT
2.5
2.7
-
-
-
-
-
-
-
-
-
-
-
VIH
1.7
–0.5
1.9
-
5.5
0.7
-
VIL
VOH
VOL
0.4
-
I
OH at VOH (mA)
OL at VOL (mA)
–12
12
I
-
DS001-2 (v2.8) June 13, 2008
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Module 2 of 4
49
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Spartan-II FPGA Family: Functional Description
Revision History
Date
Version
2.0
Description
09/18/00
03/05/01
09/03/03
Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description.
Clarified guidelines for applying power to VCCINT and VCCO
The following changes were made:
2.1
2.2
•
•
"Serial Modes," page 20 cautions about toggling WRITE during serial configuration.
Maximum VIH values in Table 32 and Table 33 changed to 5.5V.
•
•
•
In "Boundary Scan," page 13, removed sentence about lack of INTEST support.
In Table 9, page 17, added note about the state of I/Os after power-on.
In "Slave Parallel Mode," page 23, explained configuration bit alignment to SelectMap
port.
06/13/08
2.8
Added note that TDI, TMS, and TCK have a default pull-up resistor. Added note on maximum
daisy chain limit. Updated Figure 15 and Figure 18 since Mode pins can be pulled up to either
2.5V or 3.3V. Updated DLL section. Recommended using property or attribute instead of
primitive to define I/O properties. Updated description and links. Updated all modules for
continuous page, figure, and table numbering. Synchronized all modules to v2.8.
DS001-2 (v2.8) June 13, 2008
Product Specification
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Module 2 of 4
50
68
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Spartan-II FPGA Family:
DCand Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Product Specification
Definition of Terms
In this document, some specifications may be designated as Advance or Preliminary. These terms are defined as follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values
are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All limits are representative of worst-case supply voltage and junction
temperature conditions. Typical numbers are based on measurements taken at a nominal VCCINT level of 2.5V and a junction
temperature of 25°C. The parameters included are common to popular designs and typical applications. All specifications
are subject to change without notice.
DC Specifications
(1)
Absolute Maximum Ratings
Symbol
VCCINT
VCCO
VREF
Description
Supply voltage relative to GND(2)
Supply voltage relative to GND(2)
Input reference voltage
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–65
-
Max
3.0
Units
V
4.0
V
3.6
V
VIN
Input voltage relative to GND(3)
5V tolerant I/O(4)
No 5V tolerance(5)
5V tolerant I/O(4)
No 5V tolerance(5)
5.5
V
VCCO + 0.5
5.5
V
VTS
Voltage applied to 3-state output
V
VCCO +0.5
+150
+125
V
TSTG
TJ
Storage temperature (ambient)
Junction temperature
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Power supplies may turn on in any order.
3. VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day).
4. Spartan®-II device I/Os are 5V Tolerant whenever the LVTTL, LVCMOS2, or PCI33_5 signal standard has been selected. With 5V
Tolerant I/Os selected, the Maximum DC overshoot must be limited to either +5.5V or 10 mA, and undershoot must be limited to
either –0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot
to –2.0V or overshoot to +7.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
5. Without 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must
be limited to –0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may
undershoot to –2.0V or overshoot to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no
greater than 100 mA.
6. For soldering guidelines, see the Packaging Information on the Xilinx® web site.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001-3 (v2.8) June 13, 2008
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Module 3 of 4
51
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Spartan-II FPGA Family: DC and Switching Characteristics
Recommended Operating Conditions
Symbol
Description
Junction temperature(1)
Min
Max
85
Units
°C
°C
V
TJ
Commercial
Industrial
0
–40
100
VCCINT
VCCO
TIN
Supply voltage relative to GND(2,5) Commercial
2.5 – 5%
2.5 – 5%
1.4
2.5 + 5%
2.5 + 5%
3.6
Industrial
V
Supply voltage relative to GND(3,5) Commercial
Industrial
Input signal transition time(4)
V
1.4
3.6
V
-
250
ns
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Functional operation is guaranteed down to a minimum VCCINT of 2.25V (Nominal VCCINT – 10%). For every 50 mV reduction in
VCCINT below 2.375V (nominal VCCINT – 5%), all delay parameters increase by 3%.
3. Minimum and maximum values for VCCO vary according to the I/O standard selected.
4. Input and output measurement threshold is ~50% of VCCO. See "Delay Measurement Methodology," page 60 for specific levels.
5. Supply voltages may be applied in any order desired.
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Typ
Max
Units
VDRINT
Data Retention VCCINT voltage (below which configuration data
may be lost)
2.0
-
-
V
VDRIO
Data Retention VCCO voltage (below which configuration data may
be lost)
1.2
-
-
V
ICCINTQ
Quiescent VCCINT supply current(1) XC2S15
Commercial
Industrial
-
10
10
10
10
12
12
12
12
15
15
15
15
-
30
60
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
-
XC2S30
XC2S50
Commercial
Industrial
-
30
-
60
Commercial
Industrial
-
50
-
100
50
XC2S100 Commercial
Industrial
-
-
100
50
XC2S150 Commercial
Industrial
-
-
100
75
XC2S200 Commercial
Industrial
-
-
150
2
ICCOQ
IREF
IL
Quiescent VCCO supply current(1)
VREF current per VREF pin
Input or output leakage current(2)
-
-
–10
-
-
20
-
+10
8
μA
pF
CIN
Input capacitance (sample tested)
VQ, CS, TQ, PQ, FG
packages
-
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
(sample tested)(3)
Pad pull-down (when selected) @ VIN = 3.6V (sample tested)(3)
-
-
-
-
0.25
0.15
mA
mA
IRPD
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. The I/O leakage current specification applies only when the VCCINT and VCCO supply voltages have reached their respective
minimum Recommended Operating Conditions.
3. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not provide valid logic levels when input pins are connected to other circuits.
DS001-3 (v2.8) June 13, 2008
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Module 3 of 4
52
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Spartan-II FPGA Family: DC and Switching Characteristics
Power-On Requirements
Spartan-II FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can
consume more than ICCPO minimum, though this cannot
adversely affect reliability.
A maximum limit for ICCPO is not specified. Therefore the
use of foldback/crowbar supplies and fuses deserves
special attention. In these cases, limit the ICCPO current to a
level below the trip point for over-current protection in order
to avoid inadvertently shutting down the supply.
New
Old
Requirements(1) Requirements(1)
For Devices with For Devices with
Date Code 0321
or Later
Date Code
before 0321
Conditions
Device
Temperature
Grade
Junction
Symbol
Description
Temperature(2)
Min
1.50
1.00
0.25
0.50
-
Max
Min
2.00
2.00
0.50
0.50
-
Max
Units
A
(3)
ICCPO
Total VCCINT supply
current required
during power-on
–40°C≤ TJ<–20°C
–20°C ≤ TJ < 0°C
0°C ≤ TJ ≤ 85°C
85°C < TJ ≤ 100°C
–40°C≤ TJ≤ 100°C
Industrial
Industrial
Commercial
Industrial
All
-
-
-
-
A
-
-
A
-
-
A
(4,5)
TCCPO
VCCINT ramp time
50
50
ms
Notes:
1. The date code is printed on the top of the device’s package. See the "Device Part Marking" section in Module 1.
2. The expected TJ range for the design determines the ICCPO minimum requirement. Use the applicable ranges in the junction
temperature column to find the associated current values in the appropriate new or old requirements column according to the date
code. Then choose the highest of these current values to serve as the minimum ICCPO requirement that must be met. For example,
if the junction temperature for a given design is -25°C ≤ TJ ≤ 75°C, then the new minimum ICCPO requirement is 1.5A.
If 5°C ≤ TJ ≤ 90°C, then the new minimum ICCPO requirement is 0.5A.
3. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 2.5V.
4. The ramp time is measured from GND to VCCINT max on a fully loaded board.
5. During power-on, the VCCINT ramp must increase steadily in voltage with no dips.
6. For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Requirements for the Spartan-II and Spartan-IIE Families"
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
VIL
VIH
VOL
V, Max
0.4
VOH
V, Min
IOL
mA
24
IOH
mA
Input/Output
Standard
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V, Max
0.8
V, Min
2.0
V, Max
5.5
LVTTL(1)
LVCMOS2
PCI, 3.3V
PCI, 5.0V
GTL
2.4
–24
0.7
1.7
5.5
0.4
1.9
12
–12
44% VCCINT
0.8
60% VCCINT
2.0
VCCO + 0.5
5.5
10% VCCO
0.55
90% VCCO
2.4
Note (2)
Note (2)
40
Note (2)
Note (2)
N/A
VREF – 0.05
VREF – 0.1
VREF + 0.05
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
3.6
0.4
N/A
GTL+
3.6
0.6
N/A
36
N/A
HSTL I
V
REF – 0.1
VREF – 0.1
REF – 0.1
VREF – 0.2
REF – 0.2
VREF – 0.2
REF – 0.2
3.6
0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VREF + 0.6
VREF + 0.8
VREF + 0.6
VREF + 0.8
8
–8
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
3.6
0.4
24
–8
V
3.6
0.4
48
–8
3.6
VREF – 0.6
VREF – 0.8
VREF – 0.6
VREF – 0.8
8
–8
V
3.6
16
–16
3.6
7.6
–7.6
–15.2
V
3.6
15.2
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Spartan-II FPGA Family: DC and Switching Characteristics
VIL
VIH
VOL
VOH
IOL
mA
IOH
mA
Input/Output
Standard
V, Min
–0.5
V, Max
V, Min
V, Max
3.6
V, Max
V, Min
CTT
AGP
VREF – 0.2
VREF – 0.2
VREF + 0.2
VREF + 0.2
VREF – 0.4
10% VCCO
VREF + 0.4
90% VCCO
8
–8
–0.5
3.6
Note (2)
Note (2)
Notes:
1.
VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and
junction temperature). Values apply to all Spartan-II devices
unless otherwise noted.
(1)
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)
Speed Grade
All
-6
-5
Symbol
Description
Device
Min
Max
2.9
Max
3.3
Units
TICKOFDLL
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, with DLL.
All
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables "Constants for Calculating TIOOP" and "Delay Measurement
Methodology," page 60.
3. DLL output jitter is already included in the timing calculation.
4. For data output with different standards, adjust delays with the values shown in "IOB Output Delay Adjustments for Different
Standards," page 59. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Global Clock Input Adjustments," page 61.
(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)
Speed Grade
All
-6
Max
4.5
4.5
4.5
4.6
4.6
4.7
-5
Max
5.4
5.4
5.4
5.5
5.5
5.6
Symbol
Description
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Min
Units
ns
TICKOF
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, without DLL.
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables "Constants for Calculating TIOOP" and "Delay Measurement
Methodology," page 60.
3. For data output with different standards, adjust delays with the values shown in "IOB Output Delay Adjustments for Different
Standards," page 59. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Global Clock Input Adjustments," page 61.
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Spartan-II FPGA Family: DC and Switching Characteristics
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Speed Grade
-6
-5
Symbol
Description
Device
Min
Min
Units
T
PSDLL / TPHDLL Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,(1)
with DLL
All
1.7 / 0
1.9 / 0
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
4. A zero hold time listing indicates no hold time or a negative hold time.
5. For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Global Clock Input Adjustments," page 61.
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Speed Grade
-6
-5
Symbol
Description
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Min
Min
Units
ns
T
PSFD / TPHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,(1)
without DLL
2.2 / 0
2.2 / 0
2.2 / 0
2.3 / 0
2.4 / 0
2.4 / 0
2.7 / 0
2.7 / 0
2.7 / 0
2.8 / 0
2.9 / 0
3.0 / 0
ns
ns
ns
ns
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. A zero hold time listing indicates no hold time or a negative hold time.
4. For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Global Clock Input Adjustments," page 61.
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Spartan-II FPGA Family: DC and Switching Characteristics
(1)
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in "IOB Input Delay Adjustments for Different Standards," page 57.
Speed Grade
-6
-5
Symbol
Propagation Delays
TIOPI
Description
Device
Min
Max
Min
Max Units
Pad to I output, no delay
Pad to I output, with delay
All
All
All
-
-
-
0.8
1.5
1.7
-
-
-
1.0
1.8
2.0
ns
ns
ns
TIOPID
TIOPLI
Pad to output IQ via transparent latch,
no delay
TIOPLID
Pad to output IQ via transparent latch,
with delay
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
-
-
-
-
-
-
3.8
3.8
3.8
3.8
4.0
4.0
-
-
-
-
-
-
4.5
4.5
4.5
4.5
4.7
4.7
ns
ns
ns
ns
ns
ns
Sequential Delays
TIOCKIQ
Clock CLK to output IQ
All
-
0.7
-
0.8
ns
Setup/Hold Times with Respect to Clock CLK(2)
TIOPICK / TIOICKP Pad, no delay
IOPICKD / TIOICKPD Pad, with delay(1)
All
1.7 / 0
3.8 / 0
3.8 / 0
3.8 / 0
3.8 / 0
3.9 / 0
3.9 / 0
0.9 / 0.01
-
-
-
-
-
-
-
-
1.9 / 0
4.4 / 0
4.4 / 0
4.4 / 0
4.4 / 0
4.6 / 0
4.6 / 0
0.9 / 0.01
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
T
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
All
TIOICECK / TIOCKICE ICE input
Set/Reset Delays
TIOSRCKI
TIOSRIQ
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
All
All
All
-
-
-
1.1
1.5
9.9
-
-
-
1.2
1.7
ns
ns
ns
TGSRQ
11.7
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table "Delay Measurement Methodology," page 60.
2. A zero hold time listing indicates no hold time or a negative hold time.
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Spartan-II FPGA Family: DC and Switching Characteristics
(1)
IOB Input Delay Adjustments for Different Standards
Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A
delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-6
-5
Units
Data Input Delay Adjustments
TILVTTL
TILVCMOS2
TIPCI33_3
TIPCI33_5
TIPCI66_3
TIGTL
Standard-specific data input delay
adjustments
LVTTL
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS2
PCI, 33 MHz, 3.3V
PCI, 33 MHz, 5.0V
PCI, 66 MHz, 3.3V
GTL
–0.04
–0.11
0.26
–0.05
–0.13
0.30
–0.11
0.20
–0.13
0.24
TIGTLP
GTL+
0.11
0.13
TIHSTL
HSTL
0.03
0.04
TISSTL2
TISSTL3
TICTT
SSTL2
–0.08
–0.04
0.02
–0.09
–0.05
0.02
SSTL3
CTT
TIAGP
AGP
–0.06
–0.07
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table "Delay Measurement Methodology," page 60.
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Spartan-II FPGA Family: DC and Switching Characteristics
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in "IOB Output Delay Adjustments for Different Standards," page 59.
Speed Grade
-6
-5
Symbol
Propagation Delays
TIOOP
Description
Min
Max
Min
Max Units
O input to pad
-
-
2.9
3.4
-
-
3.4
4.0
ns
ns
TIOOLP
O input to pad via transparent latch
3-state Delays
TIOTHZ
T input to pad high-impedance(1)
-
-
-
-
-
2.0
3.0
2.5
3.5
5.0
-
-
-
-
-
2.3
3.6
2.9
4.2
5.9
ns
ns
ns
ns
ns
TIOTON
T input to valid data on pad
TIOTLPHZ
T input to pad high impedance via transparent latch(1)
T input to valid data on pad via transparent latch
GTS to pad high impedance(1)
TIOTLPON
TGTS
Sequential Delays
TIOCKP
Clock CLK to pad
Clock CLK to pad high impedance (synchronous)(1)
-
-
-
2.9
2.3
3.3
-
-
-
3.4
2.7
4.0
ns
ns
ns
TIOCKHZ
TIOCKON
Clock CLK to valid data on pad (synchronous)
Setup/Hold Times with Respect to Clock CLK(2)
TIOOCK / TIOCKO O input
1.1 / 0
-
-
1.3 / 0
-
-
ns
ns
TIOOCECK
TIOCKOCE
TIOSRCKO
TIOCKOSR
TIOTCK / TIOCKT 3-state setup times, T input
/
OCE input
0.9 / 0.01
0.9 / 0.01
/
SR input (OFF)
1.2 / 0
-
1.3 / 0
-
ns
0.8 / 0
1.0 / 0
-
-
0.9 / 0
1.0 / 0
-
-
ns
ns
TIOTCECK
TIOCKTCE
TIOSRCKT
TIOCKTSR
/
3-state setup times, TCE input
/
3-state setup times, SR input (TFF)
1.1 / 0
-
1.2 / 0
-
ns
Set/Reset Delays
TIOSRP
SR input to pad (asynchronous)
SR input to pad high impedance (asynchronous)(1)
SR input to valid data on pad (asynchronous)
GSR to pad
-
-
-
-
3.7
3.1
4.1
9.9
-
-
-
-
4.4
3.7
ns
ns
ns
ns
TIOSRHZ
TIOSRON
4.9
TIOGSRQ
11.7
Notes:
1. Three-state turn-off delays should not be adjusted.
2. A zero hold time listing indicates no hold time or a negative hold time.
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Spartan-II FPGA Family: DC and Switching Characteristics
(1)
IOB Output Delay Adjustments for Different Standards
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-6
-5
Units
Output Delay Adjustments (Adj)
TOLVTTL_S2
TOLVTTL_S4
TOLVTTL_S6
TOLVTTL_S8
TOLVTTL_S12
TOLVTTL_S16
TOLVTTL_S24
TOLVTTL_F2
TOLVTTL_F4
TOLVTTL_F6
TOLVTTL_F8
TOLVTTL_F12
TOLVTTL_F16
TOLVTTL_F24
TOLVCMOS2
TOPCI33_3
TOPCI33_5
TOPCI66_3
TOGTL
Standard-specific adjustments for LVTTL, Slow, 2 mA
14.2
7.2
16.9
8.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
output delays terminating at pads
4 mA
(based on standard capacitive
6 mA
4.7
5.5
load, CSL
)
8 mA
2.9
3.5
12 mA
16 mA
24 mA
1.9
2.2
1.7
2.0
1.3
1.5
LVTTL, Fast, 2 mA
12.6
5.1
15.0
6.1
4 mA
6 mA
3.0
3.6
8 mA
1.0
1.2
12 mA
16 mA
24 mA
0
0
–0.1
–0.1
0.2
–0.1
–0.2
0.2
LVCMOS2
PCI, 33 MHz, 3.3V
PCI, 33 MHz, 5.0V
PCI, 66 MHz, 3.3V
GTL
2.4
2.9
2.9
3.5
–0.3
0.6
–0.4
0.7
TOGTLP
GTL+
0.9
1.1
TOHSTL_I
HSTL I
–0.4
–0.8
–0.9
–0.4
–0.8
–0.4
–0.9
–0.5
–0.8
–0.5
–1.0
–1.1
–0.5
–1.0
–0.5
–1.1
–0.6
–1.0
TOHSTL_III
TOHSTL_IV
TOSSTL2_I
TOSSLT2_II
TOSSTL3_I
TOSSTL3_II
TOCTT
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
TOAGP
AGP
Notes:
1. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables "Constants for Calculating TIOOP" and "Delay Measurement Methodology," page 60.
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Spartan-II FPGA Family: DC and Switching Characteristics
Calculation of T
Capacitance
as a Function of
Constants for Calculating T
IOOP
IOOP
(1)
CSL
FL
Standard
(pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
50
10
10
0
(ns/pF)
TIOOP is the propagation delay from the O Input of the IOB
to the pad. The values for TIOOP are based on the standard
capacitive load (CSL) for each I/O standard as listed in the
table "Constants for Calculating TIOOP", below.
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
0.41
0.20
0.13
For other capacitive loads, use the formulas below to
calculate an adjusted propagation delay, TIOOP1
.
0.079
0.044
0.043
0.033
0.41
T
IOOP1 = TIOOP + Adj + (CLOAD – CSL) * FL
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVCMOS2
Where:
Adj
is selected from "IOB Output Delay
Adjustments for Different Standards", page 59,
according to the I/O standard used
0.20
CLOAD is the capacitive load for the design
FL is the capacitance scaling factor
0.100
0.086
0.058
0.050
0.048
0.041
0.050
0.050
0.033
0.014
0.017
0.022
0.016
0.014
0.028
0.016
0.029
0.016
0.035
0.037
Delay Measurement Methodology
VREF
Point Typ(2)
Meas.
(1)
(1)
Standard
LVTTL
VL
VH
0
3
1.4
-
LVCMOS2
PCI33_5
PCI33_3
PCI66_3
GTL
0
2.5
1.125
-
PCI 33 MHz 5V
Per PCI Spec
Per PCI Spec
Per PCI Spec
-
PCI 33 MHZ 3.3V
-
PCI 66 MHz 3.3V
-
GTL
V
V
V
V
REF – 0.2 VREF + 0.2 VREF
REF – 0.2 VREF + 0.2 VREF
REF – 0.5 VREF + 0.5 VREF
REF – 0.5 VREF + 0.5 VREF
0.80
1.0
0.75
0.90
0.90
1.5
1.25
1.5
GTL+
0
GTL+
HSTL Class I
20
20
20
30
30
30
30
20
10
HSTL Class I
HSTL Class III
HSTL Class III
HSTL Class IV
HSTL Class IV VREF – 0.5 VREF + 0.5 VREF
SSTL3 I and II VREF – 1.0 VREF + 1.0 VREF
SSTL2 I and II VREF – 0.75 VREF + 0.75 VREF
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
CTT
AGP
V
REF – 0.2 VREF + 0.2 VREF
VREF VREF VREF
(0.2xVCCO) (0.2xVCCO
SSTL3 Class II
–
+
Per AGP
Spec
CTT
)
AGP
Notes:
Notes:
1. Input waveform switches between VL and VH.
1. I/O parameter measurements are made with the capacitance
values shown above. See Xilinx application note XAPP179
for the appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
2. Measurements are made at VREF Typ, Maximum, and
Minimum. Worst-case values are reported.
3. I/O parameter measurements are made with the capacitance
values shown in the table, "Constants for Calculating TIOOP".
See Xilinx application note XAPP179 for the appropriate
terminations.
4. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
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Spartan-II FPGA Family: DC and Switching Characteristics
(1)
Clock Distribution Guidelines
Speed Grade
-6
-5
Symbol
Description
Max
Max
Units
GCLK Clock Skew
TGSKEWIOB
Notes:
Global clock skew between IOB flip-flops
0.13
0.14
ns
1. These clock distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under
worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
Clock Distribution Switching Characteristics
TGPIO is specified for LVTTL levels. For other standards, adjust TGPIO with the values shown in "I/O Standard Global Clock
Input Adjustments".
Speed Grade
-6
-5
Symbol
Description
Max
Max
Units
GCLK IOB and Buffer
TGPIO
TGIO
Global clock pad to output
0.7
0.7
0.8
0.8
ns
ns
Global clock buffer I input to O output
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-6
-5
Units
Data Input Delay Adjustments
TGPLVTTL
TGPLVCMOS2
TGPPCI33_3
TGPPCI33_5
TGPPCI66_3
TGPGTL
Standard-specific global clock
input delay adjustments
LVTTL
LVCMOS2
PCI, 33 MHz, 3.3V
PCI, 33 MHz, 5.0V
PCI, 66 MHz, 3.3V
GTL
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–0.04
–0.11
0.26
–0.11
0.80
0.71
0.63
0.52
0.56
0.62
0.54
–0.05
–0.13
0.30
–0.13
0.84
0.73
0.64
0.51
0.55
0.62
0.53
TGPGTLP
GTL+
TGPHSTL
HSTL
TGPSSTL2
TGPSSTL3
TGPCTT
SSTL2
SSTL3
CTT
TGPAGP
AGP
Notes:
1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table "Delay Measurement Methodology," page 60.
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Spartan-II FPGA Family: DC and Switching Characteristics
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of
the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark
timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
Speed Grade
-6
-5
Symbol
FCLKINHF
FCLKINLF
TDLLPWHF
TDLLPWLF
Description
Min
60
Max
200
100
-
Min
60
Max
180
90
-
Units
MHz
MHz
ns
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width (CLKDLLHF)
Input clock pulse width (CLKDLL)
25
25
2.0
2.5
2.4
3.0
-
-
ns
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were
determined through statistical measurement at the package
pins using a clock mirror configuration and matched drivers.
Figure 52, page 63, provides definitions for various
parameters in the table below.
CLKDLLHF
CLKDLL
Min Max
Symbol
TIPTOL
TIJITCC
TLOCK
Description
FCLKIN
Min
Max
1.0
±150
20
Units
ns
Input clock period tolerance
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.0
±300
20
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock
ps
> 60 MHz
50-60 MHz
40-50 MHz
30-40 MHz
25-30 MHz
μs
μs
μs
μs
μs
ps
-
25
-
50
-
90
-
120
±60
±100
±140
±160
±200
TOJITCC
TPHIO
TPHOO
TPHIOM
Output jitter (cycle-to-cycle) for any DLL clock output(1)
Phase offset between CLKIN and CLKO(2)
±60
±100
±140
±160
±200
ps
Phase offset between clock outputs on the DLL(3)
Maximum phase difference between CLKIN and CLKO(4)
ps
ps
TPHOOM Maximum phase difference between clock outputs on the DLL(5)
ps
Notes:
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase Difference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
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Period Tolerance: the allowed input clock period change in nanoseconds.
1
T
=
CLKIN
F
+ T
_
IPTOL
T
CLKIN
CLKIN
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
Phase Offset and Maximum Phase Difference
Ideal Period
Actual Period
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
DS001_52_090800
Figure 52: Period Tolerance and Clock Jitter
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Spartan-II FPGA Family: DC and Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Speed Grade
-6
-5
Symbol
Description
Min
Max
Min
Max
Units
Combinatorial Delays
TILO
TIF5
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
-
-
-
-
-
-
0.6
0.7
0.9
1.0
0.4
0.7
-
-
-
-
-
-
0.7
0.9
1.1
1.1
0.4
0.9
ns
ns
ns
ns
ns
ns
TIF5X
TIF6Y
TF5INY
TIFNCTL
Incremental delay routing through transparent latch
to XQ/YQ outputs
TBYYB
Sequential Delays
TCKO
BY input to YB output
-
0.6
-
0.7
ns
FF clock CLK to XQ/YQ outputs
Latch clock CLK to XQ/YQ outputs
-
-
1.1
1.2
-
-
1.3
1.5
ns
ns
TCKLO
Setup/Hold Times with Respect to Clock CLK(1)
TICK / TCKI
4-input function: F/G inputs
5-input function: F/G inputs
1.3 / 0
1.6 / 0
1.0 / 0
1.6 / 0
0.8 / 0
0.9 / 0
0.8 / 0
-
-
-
-
-
-
-
1.4 / 0
1.8 / 0
1.1 / 0
1.8 / 0
0.8 / 0
0.9 / 0
0.8 / 0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
T
IF5CK / TCKIF5
T
F5INCK / TCKF5IN 6-input function: F5IN input
T
IF6CK / TCKIF6
6-input function: F/G inputs via F6 MUX
BX/BY inputs
T
DICK / TCKDI
T
CECK / TCKCE
CE input
T
RCK / TCKR
SR/BY inputs (synchronous)
Clock CLK
TCH
Minimum pulse width, High
Minimum pulse width, Low
-
-
1.9
1.9
-
-
1.9
1.9
ns
ns
TCL
Set/Reset
TRPW
Minimum pulse width, SR/BY inputs
3.1
-
-
3.1
-
-
ns
ns
TRQ
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
1.1
1.3
TIOGSRQ
FTOG
Delay from GSR to XQ/YQ outputs
Toggle frequency (for export control)
-
-
9.9
-
-
11.7
263
ns
263
MHz
Notes:
1. A zero hold time listing indicates no hold time or a negative hold time.
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Spartan-II FPGA Family: DC and Switching Characteristics
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Speed Grade
-6
-5
Symbol
Description
Min
Max
Min
Max
Units
Combinatorial Delays
TOPX
TOPXB
F operand inputs to X via XOR
F operand input to XB output
F operand input to Y via XOR
F operand input to YB output
F operand input to COUT output
G operand inputs to Y via XOR
G operand input to YB output
G operand input to COUT output
BX initialization input to COUT
CIN input to X output via XOR
CIN input to XB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
1.3
1.7
1.7
1.3
0.9
1.6
1.2
0.9
0.4
0.1
0.5
0.6
0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.9
1.5
2.0
2.0
1.5
1.1
2.0
1.4
1.0
0.5
0.1
0.6
0.7
0.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TOPY
TOPYB
TOPCYF
TOPGY
TOPGYB
TOPCYG
TBXCY
TCINX
TCINXB
TCINY
CIN input to Y via XOR
TCINYB
CIN input to YB
TBYP
CIN input to COUT output
Multiplier Operation
TFANDXB
TFANDYB
TFANDCY
TGANDYB
TGANDCY
F1/2 operand inputs to XB output via AND
F1/2 operand inputs to YB output via AND
F1/2 operand inputs to COUT output via AND
G1/2 operand inputs to YB output via AND
G1/2 operand inputs to COUT output via AND
-
-
-
-
-
0.5
0.9
0.5
0.6
0.2
-
-
-
-
-
0.5
1.1
0.6
0.7
0.2
ns
ns
ns
ns
ns
Setup/Hold Times with Respect to Clock CLK(1)
TCCKX / TCKCX
CCKY / TCKCY
Notes:
CIN input to FFX
CIN input to FFY
1.1 / 0
1.2 / 0
-
-
1.2 / 0
1.3 / 0
-
-
ns
ns
T
1. A zero hold time listing indicates no hold time or a negative hold time.
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Spartan-II FPGA Family: DC and Switching Characteristics
Speed Grade
CLB Distributed RAM Switching Characteristics
-6
-5
Symbol
Sequential Delays
TSHCKO16
Description
Min
Max
Min
Max
Units
Clock CLK to X/Y outputs (WE active, 16 x 1 mode)
Clock CLK to X/Y outputs (WE active, 32 x 1 mode)
-
-
2.2
2.5
-
-
2.6
3.0
ns
ns
TSHCKO32
Setup/Hold Times with Respect to Clock CLK(1)
TAS / TAH
DS / TDH
WS / TWH
F/G address inputs
BX/BY data inputs (DIN)
CE input (WS)
0.7 / 0
0.8 / 0
0.9 / 0
-
-
-
0.7 / 0
0.9 / 0
1.0 / 0
-
-
-
ns
ns
ns
T
T
Clock CLK
TWPH
Minimum pulse width, High
-
-
-
2.9
2.9
5.8
-
-
-
2.9
2.9
5.8
ns
ns
ns
TWPL
Minimum pulse width, Low
TWC
Minimum clock period to meet address write cycle time
Notes:
1. A zero hold time listing indicates no hold time or a negative hold time.
CLB Shift Register Switching Characteristics
Speed Grade
-6
-5
Symbol
Sequential Delays
TREG
Description
Min
Max
Min
Max
Units
Clock CLK to X/Y outputs
-
3.47
-
3.88
ns
Setup Times with Respect to Clock CLK
TSHDICK
TSHCECK
Clock CLK
TSRPH
BX/BY data inputs (DIN)
CE input (WS)
0.8
0.9
-
-
0.9
1.0
-
-
ns
ns
Minimum pulse width, High
Minimum pulse width, Low
-
-
2.9
2.9
-
-
2.9
2.9
ns
ns
TSRPL
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Block RAM Switching Characteristics
Speed Grade
-6
-5
Symbol
Sequential Delays
TBCKO
Description
Min
Max
Min
Max
Units
Clock CLK to DOUT output
-
3.4
-
4.0
ns
Setup/Hold Times with Respect to Clock CLK(1)
TBACK / TBCKA
BDCK/ TBCKD
BECK/ TBCKE
BRCK/ TBCKR
BWCK/ TBCKW
ADDR inputs
DIN inputs
EN inputs
1.4 / 0
1.4 / 0
2.9 / 0
2.7 / 0
2.6 / 0
-
-
-
-
-
1.4 / 0
1.4 / 0
3.2 / 0
2.9 / 0
2.8 / 0
-
-
-
-
-
ns
ns
ns
ns
ns
T
T
T
RST input
WEN input
T
Clock CLK
TBPWH
Minimum pulse width, High
-
-
-
1.9
1.9
3.0
-
-
-
1.9
1.9
4.0
ns
ns
ns
TBPWL
Minimum pulse width, Low
TBCCS
CLKA -> CLKB setup time for different ports
Notes:
1. A zero hold time listing indicates no hold time or a negative hold time.
TBUF Switching Characteristics
Speed Grade
-6
-5
Symbol
Description
Max
Max
Units
Combinatorial Delays
TIO
TOFF
TON
IN input to OUT output
0
0
ns
ns
ns
TRI input to OUT output high impedance
TRI input to valid data on OUT output
0.1
0.1
0.2
0.2
JTAG Test Access Port Switching Characteristics
Speed Grade
-6
-5
Symbol
Description
Min
Max
Min
Max
Units
Setup and Hold Times with Respect to TCK
TTAPTCK / TTCKTAP
Sequential Delays
TTCKTDO
TMS and TDI setup and hold times
4.0 / 2.0
-
4.0 / 2.0
-
ns
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
-
-
11.0
33
-
-
11.0
33
ns
MHz
FTCK
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Revision History
Date
Version No.
Description
09/18/00
2.0
Sectioned the Spartan-II Family data sheet into four modules. Updated timing to reflect the
latest speed files. Added current supply numbers and XC2S200 -5 timing numbers. Approved
-5 timing numbers as preliminary information with exceptions as noted.
11/02/00
01/19/01
2.1
2.2
Removed Power Down feature.
DC and timing numbers updated to Preliminary for the XC2S50 and XC2S100. Industrial
power-on current specifications and -6 DLL timing numbers added. Power-on specification
clarified.
03/09/01
08/28/01
2.3
2.4
Added note on power sequencing. Clarified power-on current requirement.
Added -6 preliminary timing. Added typical and industrial standby current numbers. Specified
min. power-on current by junction temperature instead of by device type (Commercial vs.
Industrial). Eliminated minimum VCCINT ramp time requirement. Removed footnote limiting
DLL operation to the Commercial temperature range.
07/26/02
2.5
Clarified that I/O leakage current is specified over the Recommended Operating Conditions for
VCCINT and VCCO
.
08/26/02
09/03/03
2.6
2.7
Added references for XAPP450 to Power-On Current Specification.
Added relaxed minimum power-on current (ICCPO) requirements to page 53. On page 64,
moved TRPW values from maximum to minimum column.
06/13/08
2.8
Updated I/O measurement thresholds. Updated description and links. Updated all modules for
continuous page, figure, and table numbering. Synchronized all modules to v2.8.
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Spartan-II FPGA Family:
Pinout Tables
DS001-4 (v2.8) June 13, 2008
Product Specification
information for the standard package applies equally to the
Pb-free package.
Introduction
This section describes how the various pins on a
Spartan®-II FPGA connect within the supported component
packages, and provides device-specific thermal
characteristics. Spartan-II FPGAs are available in both
standard and Pb-free, RoHS versions of each package,
with the Pb-free version adding a “G” to the middle of the
package code. Except for the thermal characteristics, all
Pin Types
Most pins on a Spartan-II FPGA are general-purpose,
user-defined I/O pins. There are, however, different
functional types of pins on Spartan-II FPGA packages, as
outlined in Table 35.
Table 35: Pin Definitions
Pin Name
Dedicated
Direction
Input
Description
GCK0, GCK1, GCK2,
GCK3
No
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
M0, M1, M2
CCLK
Yes
Yes
Input
Mode pins are used to specify the configuration mode.
Input or Output The configuration Clock I/O pin. It is an input for slave-parallel and slave-serial
modes, and output in master-serial mode.
PROGRAM
DONE
Yes
Yes
Input
Initiates a configuration sequence when asserted Low.
Bidirectional
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output may be open drain.
INIT
No
No
Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being cleared. This pin
becomes a user I/O after configuration.
BUSY/DOUT
Output
In Slave Parallel mode, BUSY controls the rate at which configuration data is
loaded. This pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In serial modes, DOUT provides configuration data to downstream devices in
a daisy-chain. This pin becomes a user I/O after configuration.
D0/DIN, D1, D2, D3, D4,
D5, D6, D7
No
Input or Output In Slave Parallel mode, D0-D7 are configuration data input pins. During
readback, D0-D7 are output pins. These pins become user I/Os after
configuration unless the Slave Parallel port is retained.
In serial modes, DIN is the single data input. This pin becomes a user I/O after
configuration.
WRITE
CS
No
No
Input
Input
In Slave Parallel mode, the active-low Write Enable signal. This pin becomes
a user I/O after configuration unless the Slave Parallel port is retained.
In Slave Parallel mode, the active-low Chip Select signal. This pin becomes a
user I/O after configuration unless the Slave Parallel port is retained.
TDI, TDO, TMS, TCK
Yes
Yes
Yes
No
Mixed
Input
Input
Input
Boundary Scan Test Access Port pins (IEEE 1149.1).
Power supply pins for the internal core logic.
VCCINT
VCCO
VREF
Power supply pins for output drivers (subject to banking rules)
Input threshold voltage pins. Become user I/Os when an external threshold
voltage is not needed (subject to banking rules).
GND
Yes
No
Input
Ground.
IRDY, TRDY
See PCI core
These signals can only be accessed when using Xilinx® PCI cores. If the
documentation cores are not used, these pins are available as user I/Os.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
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Table 36: Spartan-II Family Package Options
(1)
Maximum Lead Pitch
Footprint
Area (mm)
Height
(mm)
Mass
(g)
Package
Leads
Type
I/O
(mm)
VQ100 / VQG100
TQ144 / TQG144
CS144 / CSG144
PQ208 / PQG208
FG256 / FGG256
FG456 / FGG456
100
144
144
208
256
456
Very Thin Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
60
0.5
16 x 16
22 x 22
1.20
1.60
1.20
3.70
2.00
2.60
0.6
1.4
0.3
5.3
0.9
2.2
92
0.5
Chip Scale Ball Grid Array (CSBGA)
Plastic Quad Flat Pack (PQFP)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
92
0.8
12 x 12
140
176
284
0.5
30.6 x 30.6
17 x 17
1.0
1.0
23 x 23
Notes:
1. Package mass is 10%.
Note: Some early versions of Spartan-II devices, including
the XC2S15 and XC2S30 ES devices and the XC2S150
with date code 0045 or earlier, included a power-down pin.
For more information, see Answer Record 10500.
For additional package information, see UG112: Device
Package User Guide.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Table 38.
VCCO Banks
Some of the I/O standards require specific VCCO voltages.
These voltages are externally connected to device pins that
serve groups of IOBs, called banks. Eight I/O banks result
from separating each edge of the FPGA into two banks (see
Figure 3 in Module 2). Each bank has multiple VCCO pins
which must be connected to the same voltage. In the
smaller packages, the VCCO pins are connected between
banks, effectively reducing the number of independent
banks available (see Table 37). These interconnected
banks are shown in the Pinout Tables with VCCO pads for
multiple banks connected to the same pin.
Material Declaration Data Sheets (MDDS) are also
available on the Xilinx web site for each package.
Table 38: Xilinx Package Documentation
Package
VQ100
Drawing
MDDS
Package Drawing
PK173_VQ100
PK130_VQG100
PK169_TQ144
PK126_TQG144
PK149_CS144
PK103_CSG144
PK166_PQ208
PK123_PQG208
PK151_FG256
PK105_FGG256
PK154_FG456
PK109_FGG456
VQG100
TQ144
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
TQG144
CS144
Table 37: Independent VCCO Banks Available
Package
VQ100
PQ208
CS144
TQ144
FG256
FG456
CSG144
PQ208
Independent Banks
1
4
8
PQG208
FG256
Package Overview
FGG256
FG456
Table 36 shows the six low-cost, space-saving production
package styles for the Spartan-II family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “CS144” package becomes
“CSG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx sales for more information.
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in Table 38.
FGG456
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value similarly reports the difference between the board and
junction temperature. The junction-to-ambient (θJA) value
reports the temperature difference between the ambient
environment and the junction temperature. The θJA value is
reported at different air velocities, measured in linear feet
per minute (LFM). The “Still Air (0 LFM)” column shows the
Package Thermal Characteristics
Table 39 provides the thermal characteristics for the various
Spartan-II FPGA package offerings. This information is also
available using the Thermal Query tool on xilinx.com
(www.xilinx.com/cgi-bin/thermal/thermal.pl).
θ
JA value in a system without a fan. The thermal resistance
drops with increasing air flow.
The junction-to-case thermal resistance (θJC) indicates the
difference between the temperature measured on the
package body (case) and the die junction temperature per
watt of power consumption. The junction-to-board (θJB)
Table 39: Spartan-II Package Thermal Characteristics
Junction-to-Ambient (θ
)
JA
at Different Air Flows
Junction-to-Case
(θ
Junction-to-
Still Air
(0 LFM)
Package
Device
XC2S15
XC2S30
XC2S15
XC2S30
XC2S50
XC2S100
)
Board (θ
)
250 LFM
36.7
500 LFM
34.2
750 LFM
33.3
Units
JC
JB
11.3
10.1
7.3
N/A
44.1
40.7
38.6
34.7
32.2
31.4
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
VQ100
VQG100
N/A
33.9
31.5
30.8
N/A
30.0
25.7
24.1
6.7
N/A
27.0
23.1
21.7
TQ144
TQG144
5.8
N/A
25.1
21.4
20.1
5.3
N/A
24.4
20.9
19.6
CS144
CSG144
XC2S30
2.8
N/A
34.0
26.0
23.9
23.2
°C/Watt
XC2S50
XC2S100
XC2S150
XC2S200
XC2S50
6.7
5.9
5.0
4.1
7.1
5.8
4.6
3.5
2.0
2.0
N/A
N/A
N/A
N/A
17.6
15.1
12.7
10.7
N/A
N/A
25.2
24.6
23.8
23.0
27.2
25.1
23.0
21.4
21.9
21.0
18.6
18.1
17.6
17.0
21.4
19.5
17.6
16.1
17.3
16.6
16.4
16.0
15.6
15.0
20.3
18.3
16.3
14.7
15.8
15.1
15.2
14.9
14.4
13.9
19.8
17.8
15.8
14.2
15.2
14.5
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
PQ208
PQG208
XC2S100
XC2S150
XC2S200
XC2S150
XC2S200
FG256
FGG256
FG456
FGG456
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
71
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Spartan-II FPGA Family: Pinout Tables
XC2S15 Device Pinouts (Continued)
Pinout Tables
XC2S15 Pad Name
The following device-specific pinout tables include all
packages available for each Spartan®-II device. They follow
the pad locations around the die, and include Boundary
Scan register locations.
Bndry
Scan
Function Bank VQ100 TQ144 CS144
M2
I/O
-
P27
-
P106
P103
P102
P100
P99
P98
P97
P96
P95
P94
P93
P92
P91
P90
P90
P89
P88
P87
P86
P85
P84
P83
P82
P81
P80
P79
P77
P76
P75
P74
P73
P72
P71
P70
P69
P68
P67
P66
P65
P63
P62
N2
K4
148
155
158
161
164
-
5
5
5
5
-
XC2S15 Device Pinouts
I/O, VREF
I/O
P30
P31
P32
-
L4
XC2S15 Pad Name
N4
Bndry
Function
GND
Bank VQ100 TQ144 CS144
Scan
-
I/O
K5
-
P1
P2
P3
-
P143
P142
P141
P140
P139
P137
P136
P135
P134
P133
P132
P131
P130
P129
P128
P127
P127
P126
P125
P124
P123
P122
P121
P120
P119
P118
P117
P115
P114
P113
P112
P111
P110
P109
P108
P107
A1
B1
C2
C1
D4
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
G2
G2
G1
G3
G4
H1
H2
H3
H4
J1
GND
L5
TMS
I/O
-
-
VCCINT
I/O
-
P33
-
M5
N5
-
7
7
7
7
7
-
77
80
83
86
89
-
5
5
5
5
-
167
170
173
176
-
I/O
I/O
-
K6
I/O, VREF
I/O
P4
P5
P6
-
I/O, VREF
I/O
P34
-
L6
M6
N6
I/O
VCCINT
I, GCK1
VCCO
VCCO
GND
P35
P36
P37
P37
P38
P39
P40
-
GND
I/O
5
5
4
-
M7
N7
185
-
7
7
7
7
7
7
-
P7
-
92
95
98
101
104
107
-
I/O
N7
-
I/O, VREF
I/O
P8
P9
-
L7
-
I, GCK0
I/O
4
4
4
4
4
4
-
K7
186
190
193
196
199
202
-
I/O
N8
I/O, IRDY(1)
GND
VCCO
VCCO
I/O, TRDY(1)
VCCINT
I/O
P10
P11
P12
P12
P13
P14
-
I/O
M8
L8
I/O, VREF
I/O
P41
-
7
6
6
-
-
K8
-
I/O
-
N9
110
-
VCCINT
GND
P42
-
M9
L9
-
-
6
6
6
6
6
-
113
116
119
122
125
-
I/O
4
4
4
4
4
4
-
P43
P44
P45
-
K9
205
208
211
214
217
220
-
I/O
P15
P16
-
I/O
N10
L10
N11
M11
L11
N12
M12
N13
M13
L12
L13
K10
K11
K12
J10
J11
I/O, VREF
I/O
I/O, VREF
I/O
I/O
P17
-
I/O
P46
P47
P48
P49
P50
P50
P51
P52
P53
-
GND
I/O
I/O
6
6
6
6
6
6
-
P18
P19
P20
-
J2
128
131
134
137
140
143
146
-
GND
I/O
J3
DONE
VCCO
VCCO
PROGRAM
I/O (INIT)
I/O (D7)
I/O
3
4
3
-
223
-
I/O, VREF
I/O
K1
K2
K3
L1
-
I/O
P21
P22
P23
P24
P25
P26
P26
226
227
230
233
236
239
242
I/O
3
3
3
3
3
3
M1
L2
GND
M0
-
L3
-
M1
M2
N1
147
-
I/O, VREF
I/O
P54
P55
P56
VCCO
VCCO
6
5
-
I/O (D6)
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
72
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Spartan-II FPGA Family: Pinout Tables
XC2S15 Device Pinouts (Continued)
XC2S15 Device Pinouts (Continued)
XC2S15 Pad Name
XC2S15 Pad Name
Function Bank VQ100 TQ144 CS144
I/O, VREF
Bndry
Scan
Bndry
Scan
Function
GND
Bank VQ100 TQ144 CS144
-
-
P61
P60
P59
P58
P57
P56
P55
P54
P53
P53
P52
P51
P50
P49
P48
P47
P46
P45
P44
P43
P41
P40
P39
P38
J12
J13
-
1
1
1
1
-
P86
-
P21
P20
P19
P18
P17
P16
P16
P15
P14
P13
P12
P11
P10
P9
B8
A8
B7
A7
C7
D7
D7
A6
B6
C6
D6
A5
B5
C5
D5
A4
B4
C4
A3
B3
C3
A2
B2
24
27
30
36
-
I/O (D5)
I/O
3
3
3
3
3
-
P57
P58
P59
P60
-
245
248
251
254
257
-
I/O
H10
H11
H12
H13
G12
G13
G11
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D11
C13
C12
C11
I/O
P87
P88
P89
P90
P90
P91
P92
-
I/O, VREF
I/O (D4)
I/O
I, GCK2
GND
VCCO
VCCO
I, GCK3
VCCINT
I/O
1
0
0
-
-
VCCINT
I/O, TRDY(1)
VCCO
P61
P62
P63
P63
P64
P65
-
-
3
3
2
-
260
-
37
-
VCCO
-
0
0
0
0
-
44
47
50
53
-
GND
-
I/O, VREF
I/O
P93
-
I/O, IRDY(1)
2
2
2
2
2
2
-
263
266
269
272
275
278
-
I/O
I/O
-
I/O (D3)
I/O, VREF
I/O
P66
P67
P68
P69
-
VCCINT
GND
I/O
P94
-
-
P8
-
0
0
0
0
0
-
P95
P96
P97
-
P7
56
59
62
65
68
-
I/O (D2)
GND
I/O
P6
I/O, VREF
I/O
P5
I/O (D1)
I/O
2
2
2
2
2
2
P70
P71
P72
-
281
284
287
290
293
296
P4
I/O
P98
P99
P100
P100
P3
I/O, VREF
I/O
TCK
P2
VCCO
0
7
P1
-
I/O (DIN, D0)
P73
P74
VCCO
P144
-
04/18/01
I/O (DOUT,
BUSY)
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx
PCI cores.
2. See "VCCO Banks" for details on VCCO banking.
CCLK
VCCO
VCCO
TDO
2
2
1
2
-
P75
P76
P76
P77
P78
P79
P80
P81
-
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
B13
B12
A13
A12
B11
A11
D10
C10
B10
A10
D9
299
-
-
-
Additional XC2S15 Package Pins
GND
TDI
-
VQ100
-
-
Not Connected Pins
I/O (CS)
I/O (WRITE)
I/O
1
1
1
1
1
1
-
0
P28
P29
-
-
-
-
11/02/00
3
TQ144
6
Not Connected Pins
I/O, VREF
I/O
P82
P83
P84
-
9
P42
P116
P64
P138
P78
-
P101
-
P104
-
P105
-
12
15
-
11/02/00
I/O
C9
GND
VCCINT
I/O
B9
CS144
Not Connected Pins
-
P85
-
A9
-
D3
M10
D12
N3
J4
-
K13
-
M3
-
M4
-
1
1
D8
18
21
I/O
-
C8
11/02/00
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
73
R
Spartan-II FPGA Family: Pinout Tables
XC2S30 Device Pinouts (Continued)
XC2S30 Device Pinouts
XC2S30 Pad Name
XC2S30 Pad Name
Bndry
Bank VQ100 TQ144 CS144 PQ208 Scan
Bndry
Function
I/O, VREF
I/O
Function
GND
Bank VQ100 TQ144 CS144 PQ208 Scan
6
6
6
6
6
-
P20
P115
-
K1
-
P45
P46
P47
P48
P49
P50
P51
P52
P53
P53
P54
P57
P58
P59
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P78
P79
P80
P81
P82
P83
P84
P85
P86
203
206
209
212
215
218
-
-
P1
P143
P142
P141
P140
-
A1
B1
C2
C1
-
P1
-
-
-
TMS
I/O
-
P2
P2
-
I/O
P114
P113
P112
P111
P110
P109
P108
P107
P106
P103
-
K2
K3
L1
L2
L3
M1
M2
N1
N2
K4
-
7
7
7
7
7
7
7
-
P3
P3
113
116
119
122
125
128
131
-
I/O
P21
P22
P23
P24
P25
P26
P26
P27
-
I/O
-
P4
I/O
I/O
-
P5
M1
I/O, VREF
I/O
P4
P139
P138
P137
P136
P135
-
D4
D3
D2
D1
E4
-
P6
GND
M0
-
-
P8
-
219
-
I/O
P5
P9
VCCO
VCCO
M2
6
5
-
I/O
P6
P10
P11
P12
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P39
P40
P41
P42
P43
-
GND
VCCO
I/O
-
220
227
230
233
236
239
242
-
7
7
7
7
7
7
-
-
-
I/O
5
5
5
5
5
5
-
P7
P134
P133
-
E3
E2
-
134
137
140
143
146
-
I/O
-
I/O
-
I/O, VREF
I/O
P30
-
P102
P101
P100
P99
P98
-
L4
M4
N4
K5
L5
-
I/O
-
I/O
-
-
-
I/O
P31
P32
-
I/O
-
-
-
I/O
GND
I/O, VREF
I/O
-
P8
P9
-
-
-
GND
VCCO
VCCINT
I/O
7
7
7
7
7
-
P132
P131
P130
-
E1
F4
F3
-
149
152
155
158
161
-
5
-
-
-
P33
-
P97
P96
P95
-
M5
N5
K6
-
-
I/O
5
5
5
5
5
-
245
248
251
254
257
-
I/O
-
I/O, IRDY(1)
GND
VCCO
VCCO
I/O, TRDY(1)
VCCINT
I/O
P10
P11
P12
P12
P13
P14
-
P129
P128
P127
P127
P126
P125
P124
P123
P122
-
F2
F1
G2
G2
G1
G3
G4
H1
H2
-
I/O
-
I/O
-
I/O
-
-
-
7
6
6
-
-
I/O
-
-
-
-
GND
I/O, VREF
I/O
-
-
-
164
-
5
5
5
-
P34
-
P94
-
L6
-
260
263
266
-
6
6
6
-
170
173
176
-
I/O
-
P93
P92
P91
P90
P90
P89
P88
P87
P86
-
M6
N6
M7
N7
N7
L7
K7
N8
M8
-
I/O
P15
P16
-
VCCINT
I, GCK1
VCCO
VCCO
GND
I, GCK0
I/O
P35
P36
P37
P37
P38
P39
P40
-
I/O, VREF
GND
I/O
5
5
4
-
275
-
6
6
6
6
6
6
-
-
-
-
179
182
185
188
191
-
-
I/O
-
-
-
-
I/O
-
-
-
4
4
4
4
4
-
276
280
283
286
289
-
I/O
-
P121
P120
-
H3
H4
-
I/O
P17
-
I/O
VCCO
GND
I/O
I/O
-
-
P119
P118
P117
P116
J1
J2
J3
J4
-
I/O, VREF
GND
I/O
P41
-
P85
-
L8
-
6
6
6
P18
P19
-
194
197
200
I/O
4
-
-
-
292
I/O
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
74
R
Spartan-II FPGA Family: Pinout Tables
XC2S30 Device Pinouts (Continued)
XC2S30 Device Pinouts (Continued)
XC2S30 Pad Name
XC2S30 Pad Name
Function Bank VQ100 TQ144 CS144 PQ208 Scan
VCCO
Bndry
Bndry
Function
I/O
Bank VQ100 TQ144 CS144 PQ208 Scan
4
4
4
4
-
-
-
-
-
P87
P88
295
298
301
304
-
3
2
-
P63
P63
P64
P65
-
P53
P53
P52
P51
-
G11
G11
G10
F13
-
P130
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P144
P145
P146
P147
P148
P150
P151
P152
P153
P154
-
I/O
-
-
VCCO
GND
-
I/O
-
P84
P83
P82
-
K8
P89
-
I/O
-
N9
M9
-
P90
I/O, IRDY(1)
2
2
2
2
2
-
389
392
395
398
401
-
VCCINT
VCCO
GND
I/O
P42
-
P91
I/O
4
-
P92
-
I/O
-
P50
P49
P48
-
F12
F11
F10
-
-
P81
P80
P79
P78
P77
-
L9
P93
-
I/O (D3)
I/O, VREF
GND
P66
P67
-
4
4
4
4
4
4
4
4
-
P43
P44
-
K9
P94
307
310
313
316
319
322
325
328
-
I/O
N10
M10
L10
-
P95
I/O
P96
I/O
2
2
2
2
2
2
-
-
-
-
404
407
410
413
416
-
I/O, VREF
I/O
P45
-
P98
I/O
-
-
-
P99
I/O
-
-
-
I/O
-
P76
P75
P74
P73
P72
P71
P70
P69
P68
P67
P66
-
N11
M11
L11
N12
M12
N13
M13
L12
L13
K10
K11
-
P100
P101
P102
P103
P104
P105
P105
P106
P107
P108
P109
P110
P111
P113
P114
P115
P116
P117
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
I/O
P68
P69
-
P47
P46
-
E13
E12
-
I/O
P46
P47
P48
P49
P50
P50
P51
P52
P53
-
I/O (D2)
VCCO
GND
I/O
GND
DONE
VCCO
VCCO
PROGRAM
I/O (INIT)
I/O (D7)
I/O
-
P45
P44
P43
P42
P41
-
E11
E10
D13
D12
D11
-
-
3
4
3
-
331
-
I/O (D1)
I/O
2
2
2
2
2
2
2
2
P70
P71
-
419
422
425
428
431
434
437
440
-
I/O
334
335
338
341
344
347
350
353
356
-
I/O, VREF
I/O
P72
-
3
3
3
3
3
3
3
3
-
I/O
-
P40
P39
P38
C13
C12
C11
I/O (DIN, D0)
P73
P74
I/O
-
I/O (DOUT,
BUSY)
I/O, VREF
I/O
P54
-
P65
P64
P63
P62
P61
-
K12
K13
J10
J11
J12
-
CCLK
VCCO
VCCO
TDO
2
2
1
2
-
P75
P76
P76
P77
P78
P79
P80
P81
-
P37
P36
P35
P34
P33
P32
P31
P30
P29
-
B13
B12
A13
A12
B11
A11
D10
C10
B10
-
P155
P156
P156
P157
P158
P159
P160
P161
P162
P163
P164
P166
P167
P168
P169
P170
443
-
I/O
P55
P56
-
-
I/O (D6)
GND
VCCO
I/O (D5)
I/O
-
GND
TDI
-
3
3
3
3
3
3
-
-
-
-
-
P57
P58
-
P60
P59
-
J13
H10
-
359
362
365
368
371
-
I/O (CS)
I/O (WRITE)
I/O
1
1
1
1
1
1
1
1
-
0
3
I/O
6
I/O
-
-
-
I/O
-
9
I/O
-
-
-
I/O, VREF
I/O
P82
-
P28
-
A10
-
12
15
18
21
-
GND
I/O, VREF
I/O (D4)
I/O
-
-
-
3
3
3
-
P59
P60
-
P58
P57
P56
P55
P54
H11
H12
H13
G12
G13
374
377
380
-
I/O
P83
P84
-
P27
P26
P25
-
D9
I/O
C9
GND
VCCO
B9
VCCINT
I/O, TRDY(1)
P61
P62
1
-
-
-
3
386
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Product Specification
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Module 4 of 4
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XC2S30 Device Pinouts (Continued)
XC2S30 Device Pinouts (Continued)
XC2S30 Pad Name
XC2S30 Pad Name
Bndry
Bndry
Bank VQ100 TQ144 CS144 PQ208 Scan
Function
VCCINT
Bank VQ100 TQ144 CS144 PQ208 Scan
Function
I/O, VREF
I/O
-
P85
P24
P23
P22
-
A9
D8
C8
-
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
-
0
0
0
0
-
P97
-
P5
-
C4
-
P203
P204
P205
P206
P207
P208
P208
95
98
101
104
-
I/O
1
1
1
1
1
-
-
24
27
30
33
36
-
I/O
-
I/O
-
P4
P3
P2
P1
P144
A3
B3
C3
A2
B2
I/O
-
I/O
P98
P99
P100
P100
I/O
-
-
-
TCK
I/O
-
-
-
VCCO
0
7
-
GND
I/O, VREF
I/O
-
-
-
VCCO
-
04/18/01
1
1
1
1
1
-
P86
P21
-
B8
-
39
42
45
48
54
-
Notes:
-
1. IRDY and TRDY can only be accessed when using Xilinx
PCI cores.
2. See "VCCO Banks" for details on VCCO banking.
I/O
-
P20
P19
P18
P17
P16
P16
P15
P14
P13
-
A8
B7
A7
C7
D7
D7
A6
B6
C6
-
I/O
P87
I, GCK2
GND
VCCO
VCCO
I, GCK3
VCCINT
I/O
P88
P89
Additional XC2S30 Package Pins
1
0
0
-
P90
-
VQ100
Not Connected Pins
P90
-
P28
11/02/00
P29
P105
N3
-
-
-
-
-
-
-
-
P91
55
-
P92
TQ144
0
0
0
-
-
62
65
68
-
Not Connected Pins
I/O
-
P104
11/02/00
-
-
I/O, VREF
GND
I/O
P93
P12
-
D6
-
-
CS144
Not Connected Pins
0
0
0
0
0
-
-
-
-
71
74
77
80
83
-
M3
-
-
I/O
-
-
-
11/02/00
I/O
-
-
-
PQ208
I/O
-
P11
P10
P9
-
A5
B5
C5
-
Not Connected Pins
P7
P60
P13
P97
P38
P112
-
P44
P118
-
P55
P143
-
P56
P149
-
I/O
-
P94
-
VCCINT
VCCO
GND
I/O
P165
P202
0
-
-
11/02/00
-
P8
P7
P6
-
D5
A4
B4
-
-
Notes:
1. For the PQ208 package, P13, P38, P118, and P143, which
are Not Connected Pins on the XC2S30, are assigned to
VCCINT on larger devices.
0
0
0
P95
P96
-
86
89
92
I/O
I/O
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XC2S50 Device Pinouts (Continued)
XC2S50 Device Pinouts
XC2S50 Pad Name
Function Bank TQ144
GND
XC2S50 Pad Name
Bndry
Scan
Bndry
Scan
PQ208
P32
P33
P34
P35
-
FG256
GND*
K5
Function
GND
Bank TQ144
PQ208
P1
P2
P3
-
FG256
GND*
D3
-
-
-
-
P143
-
I/O
6
6
6
6
6
6
-
-
236
239
242
245
248
251
-
TMS
I/O
-
P142
-
I/O
-
K2
7
7
7
7
7
-
P141
C2
149
152
155
158
161
-
I/O
-
K1
I/O
-
A2
I/O
-
K3
I/O
P140
P4
-
B1
I/O
P121
P36
P37
P38
P39
L1
I/O
-
E3
I/O
P120
L2
I/O
-
P5
-
D2
VCCINT
VCCO
-
-
VCCINT*
GND
I/O, VREF
I/O
-
GND*
C1
6
VCCO
Bank 6*
-
7
7
7
7
7
7
-
P139
-
P6
P7
-
164
167
170
173
176
179
-
F3
GND
I/O
-
6
6
6
6
6
6
-
P119
P118
P117
P116
-
P40
P41
P42
P43
-
GND*
K4
-
I/O
-
E2
254
257
260
263
266
269
-
I/O
P138
P137
P136
P135
-
P8
P9
P10
P11
P12
E4
I/O
M1
L4
I/O
D1
I/O
I/O
E1
I/O
M2
L3
GND
VCCO
GND*
I/O
-
P44
P45
-
7
VCCO
Bank 7*
-
I/O, VREF
GND
I/O
P115
-
N1
GND*
P1
VCCINT
I/O
-
-
P13
P14
P15
-
VCCINT
*
-
6
6
6
6
6
6
-
-
P46
-
272
275
278
281
284
287
290
-
7
7
7
7
7
7
-
P134
F2
182
185
188
191
194
197
-
I/O
-
L5
I/O
P133
G3
I/O
P114
-
P47
-
N2
I/O
-
F1
I/O
M4
R1
I/O
-
P16
P17
P18
P19
P20
P21
-
F4
I/O
P113
P112
P111
P110
P109
P108
P48
P49
P50
P51
P52
P53
I/O
-
F5
I/O
M3
P2
I/O
-
G2
M1
GND
I/O, VREF
I/O
-
GND*
H3
GND
M0
-
GND*
N3
7
7
7
7
7
7
-
P132
P131
-
200
203
206
209
212
215
-
-
291
-
G4
VCCO
6
VCCO
Bank 6*
I/O
H2
I/O
P130
-
P22
P23
P24
P25
P26
G5
VCCO
5
P107
P53
VCCO
Bank 5*
-
I/O
H4
I/O, IRDY(1)
GND
VCCO
P129
P128
P127
G1
M2
-
P106
P54
-
R3
N5
292
299
302
305
308
-
GND*
I/O
5
5
5
5
-
-
7
VCCO
Bank 7*
-
I/O
P103
P57
-
T2
I/O
-
P5
VCCO
6
P127
P26
VCCO
Bank 6*
-
I/O
-
P58
-
T3
I/O, TRDY(1)
VCCINT
I/O
6
-
P126
P125
P124
-
P27
P28
P29
-
J2
218
-
GND
I/O, VREF
I/O
-
GND*
T4
5
5
5
5
5
P102
-
P59
P60
-
311
314
317
320
323
VCCINT
*
M6
T5
6
6
6
6
H1
224
227
230
233
I/O
-
I/O
J4
I/O
P101
P100
P61
P62
N6
I/O
P123
P122
P30
P31
J1
I/O
R5
I/O, VREF
J3
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Module 4 of 4
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XC2S50 Device Pinouts (Continued)
XC2S50 Device Pinouts (Continued)
XC2S50 Pad Name
XC2S50 Pad Name
Function Bank TQ144
I/O
Bndry
Scan
Bndry
Scan
Function
I/O
Bank TQ144
PQ208
P63
FG256
P6
PQ208
P97
P98
-
FG256
P11
5
-
P99
P98
-
326
4
4
-
-
415
418
-
GND
VCCO
P64
GND*
-
-
I/O, VREF
GND
I/O
P77
-
T12
5
P65
VCCO
Bank 5*
GND*
T13
4
4
4
4
4
4
-
-
P99
-
421
424
427
430
433
436
-
VCCINT
I/O
-
P97
P96
P95
-
P66
P67
P68
P69
P70
P71
P72
P73
P74
-
VCCINT
*
-
I/O
-
N12
R13
P12
5
5
5
5
5
-
R6
329
332
338
341
344
-
I/O
P76
-
P100
-
I/O
M7
I/O
I/O
N7
I/O
P75
P74
P73
P72
P71
P101
P102
P103
P104
P105
P13
I/O
-
T6
I/O
T14
I/O
-
P7
GND
DONE
VCCO
GND*
R14
GND
I/O, VREF
I/O
-
GND*
P8
3
4
439
-
5
5
5
5
-
P94
-
347
350
353
356
-
VCCO
Bank 4*
R7
I/O
-
T7
VCCO
3
P70
P105
VCCO
Bank 3*
-
I/O
P93
P92
P91
P90
P75
P76
P77
P78
T8
PROGRAM
I/O (INIT)
I/O (D7)
I/O
-
P69
P68
P67
-
P106
P107
P108
-
P15
N15
N14
T15
442
443
446
449
452
455
458
-
VCCINT
I, GCK1
VCCO
VCCINT
*
3
3
3
3
3
3
-
5
5
R8
365
-
VCCO
Bank 5*
VCCO
4
P90
P78
VCCO
Bank 4*
-
I/O
P66
-
P109
-
M13
R16
M14
GND*
L14
I/O
GND
I, GCK0
I/O
-
P89
P79
P80
P81
P82
-
GND*
N8
-
I/O
-
P110
-
4
4
4
4
4
4
-
P88
366
370
373
376
379
382
-
GND
I/O, VREF
I/O
-
P87
N9
3
3
3
3
3
3
-
P65
-
P111
P112
-
461
464
467
470
473
476
-
I/O
P86
R9
M15
L12
I/O
-
N10
T9
I/O
-
I/O
-
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
I/O
P64
P63
P62
P61
-
P113
P114
P115
P116
P117
P16
L13
I/O, VREF
GND
I/O
P85
P9
I/O
-
GND*
M10
R10
P10
T10
R11
I/O (D6)
GND
VCCO
N16
GND*
4
4
4
4
4
-
-
-
385
388
391
397
400
-
I/O
3
VCCO
Bank 3*
-
I/O
-
I/O
P84
P83
P82
-
VCCINT
I/O (D5)
I/O
-
-
P118
P119
P120
-
VCCINT
M16
K14
*
-
I/O
3
3
3
3
3
3
-
P60
479
482
485
488
491
494
-
VCCINT
VCCO
VCCINT
*
P59
4
VCCO
-
I/O
-
L16
Bank 4*
GND*
M11
I/O
-
P121
P122
P123
P124
P125
P126
K13
GND
I/O
-
P81
P80
P79
P78
-
P93
P94
P95
P96
-
-
I/O
-
-
L15
4
4
4
4
403
406
409
412
I/O
K12
I/O
T11
GND
I/O, VREF
I/O (D4)
-
GND*
K16
I/O
N11
3
3
P58
P57
497
500
I/O
R12
J16
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Module 4 of 4
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Spartan-II FPGA Family: Pinout Tables
XC2S50 Device Pinouts (Continued)
XC2S50 Device Pinouts (Continued)
XC2S50 Pad Name
XC2S50 Pad Name
Function Bank TQ144
VCCO
Bndry
Scan
Bndry
Scan
Function
Bank TQ144
PQ208
-
FG256
J14
PQ208
FG256
I/O
I/O
3
3
-
-
503
506
-
1
P35
P156
VCCO
Bank 1*
-
P56
P55
P54
P53
P127
P128
P129
P130
K15
TDO
GND
TDI
2
-
P34
P33
P32
P31
P30
-
P157
P158
P159
P160
P161
-
B14
GND*
A15
-
-
VCCINT
VCCINT
*
I/O, TRDY(1)
3
3
J15
512
-
-
-
VCCO
VCCO
Bank 3*
I/O (CS)
I/O (WRITE)
I/O
1
1
1
1
1
1
-
B13
0
VCCO
2
P53
P130
VCCO
Bank 2*
-
C13
C12
A14
3
6
GND
I/O, IRDY(1)
I/O
-
P52
P131
P132
P133
P134
-
GND*
H16
H14
H15
J13
-
I/O
P29
-
P162
-
9
2
2
2
2
2
2
-
P51
515
518
521
524
527
530
-
I/O
D12
B12
12
15
-
-
I/O
-
P163
-
I/O
P50
GND
I/O, VREF
I/O
-
GND*
C11
A13
I/O
-
1
1
1
1
1
1
-
P28
-
P164
P165
-
18
21
24
27
30
33
-
I/O (D3)
I/O, VREF
GND
I/O
P49
P135
P136
P137
P138
P139
P140
-
G16
H13
GND*
G14
G15
G12
F16
P48
I/O
-
D11
A12
-
I/O
-
P166
P167
P168
P169
P170
2
2
2
2
2
2
-
-
533
536
539
542
545
548
-
I/O
P27
P26
P25
-
E11
I/O
-
I/O
B11
I/O
-
GND
VCCO
GND*
I/O
-
P47
P46
-
1
VCCO
Bank 1*
-
I/O
P141
P142
P143
P144
G13
F15
I/O (D2)
VCCINT
VCCO
VCCINT
I/O
-
P24
P23
P22
-
P171
P172
P173
P174
P175
P176
P177
P178
P179
-
VCCINT
A11
C10
B10
D10
A10
GND*
B9
*
-
VCCINT
*
1
1
1
1
1
-
36
39
45
48
51
-
2
-
VCCO
-
I/O
Bank 2*
GND*
E16
I/O
GND
I/O (D1)
I/O
-
P45
P44
P43
P42
-
P145
P146
P147
P148
-
-
I/O
-
2
2
2
2
2
2
-
551
554
557
560
563
566
-
I/O
-
F14
GND
I/O, VREF
I/O
-
I/O
D16
F12
1
1
1
1
1
1
-
P21
-
54
57
60
63
66
72
-
I/O
E10
A9
I/O
-
P149
P150
-
E15
I/O
-
I/O, VREF
GND
I/O
P41
-
F13
I/O
P20
P19
P18
P17
P16
P180
P181
P182
P183
P184
D9
GND*
E14
I/O
A8
2
2
2
2
2
2
-
P151
-
569
572
575
578
581
584
I, GCK2
GND
VCCO
C9
I/O
-
C16
E13
GND*
I/O
P40
-
P152
-
1
VCCO
Bank 1*
-
I/O
B16
I/O (DIN, D0)
P39
P38
P153
P154
D14
C15
VCCO
0
P16
P184
VCCO
Bank 0*
-
I/O (DOUT,
BUSY)
I, GCK3
VCCINT
I/O
0
-
P15
P14
P13
P185
P186
P187
B8
73
-
CCLK
VCCO
2
2
P37
P36
P155
P156
D15
587
-
VCCINT
*
VCCO
0
A7
80
Bank 2*
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Module 4 of 4
79
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Spartan-II FPGA Family: Pinout Tables
XC2S50 Device Pinouts (Continued)
Additional XC2S50 Package Pins
XC2S50 Pad Name
TQ144
Bndry
Scan
Not Connected Pins
Function
Bank TQ144
PQ208
-
FG256
D8
P104
P105
-
-
-
-
I/O
I/O
0
0
0
-
-
83
86
89
-
11/02/00
-
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
A6
I/O, VREF
GND
I/O
P12
B7
-
GND*
C8
0
0
0
0
0
-
-
-
92
95
98
104
107
-
I/O
D7
I/O
-
E7
I/O
P11
P10
P9
-
C7
I/O
B6
VCCINT
VCCO
VCCINT*
0
VCCO
-
Bank 0*
GND
I/O
-
P8
P7
P6
-
P198
P199
P200
P201
-
GND*
A5
-
0
0
0
0
0
0
-
110
113
116
119
122
125
-
I/O
C6
I/O
B5
I/O
-
D6
I/O
-
P202
P203
-
A4
I/O, VREF
GND
I/O
P5
-
B4
GND*
E6
0
0
0
0
0
-
-
P204
-
128
131
134
137
140
-
I/O
-
D5
I/O
P4
-
P205
-
A3
I/O
C5
I/O
P3
P2
P1
P206
P207
P208
B3
TCK
VCCO
C4
0
VCCO
-
Bank 0*
VCCO
7
P144
P208
VCCO
-
Bank 7*
04/18/01
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx PCI
cores.
2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*,
VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*,
VCCO Bank 6*, VCCO Bank 7* are internally bonded to
independent ground or power planes within the package.
3. See "VCCO Banks" for details on VCCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
80
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Spartan-II FPGA Family: Pinout Tables
Additional XC2S50 Package Pins (Continued)
XC2S100 Device Pinouts (Continued)
XC2S100 Pad
Name
PQ208
Not Connected Pins
Bndry
P55
11/02/00
P56
-
-
-
-
Function Bank TQ144 PQ208 FG256 FG456 Scan
I/O
7
7
7
7
7
7
-
-
-
P7
-
F3
E2
E1
H5
209
215
218
221
224
227
-
FG256
I/O
VCCINT Pins
I/O
P138
-
P8
-
E4
F2
C3
M5
C14
M12
D4
N4
D13
N13
E5
P3
E12
P14
I/O
-
F1
V
V
V
V
V
V
V
V
CCO Bank 0 Pins
I/O, VREF
I/O
P137
P136
P135
-
P9
P10
P11
P12
D1
H4
E8
E9
F8
F9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E1
G1
CCO Bank 1 Pins
-
-
GND
VCCO
GND*
GND*
CCO Bank 2 Pins
7
VCCO
Bank 7* Bank 7*
VCCO
-
H11
J11
L9
H12
J12
M9
M8
J6
-
-
CCO Bank 3 Pins
VCCINT
I/O
-
-
P13 VCCINT* VCCINT
*
-
-
-
7
7
7
7
7
7
-
P134
P14
P15
-
F2
G3
H3
H2
230
233
236
239
245
248
-
CCO Bank 4 Pins
-
-
I/O
P133
CCO Bank 5 Pins
I/O
-
F1
J5
L8
-
-
I/O
-
P16
P17
P18
P19
P20
P21
-
F4
J2
CCO Bank 6 Pins
I/O
-
F5
K5
J5
-
-
CCO Bank 7 Pins
I/O
-
G2
K1
H5
H6
-
-
GND
I/O, VREF
I/O
-
GND*
H3
GND*
K3
GND Pins
7
7
7
7
7
7
-
P132
P131
-
251
254
257
260
266
269
-
A1
F10
G10
J7
K8
L10
A16
F11
G11
J8
K9
L11
B2
G6
H7
J9
K10
R2
B15
G7
H8
J10
K11
R15
F6
G8
H9
K6
L6
F7
G9
H10
K7
L7
T16
G4
K4
I/O
H2
L6
I/O
P130
-
P22
P23
P24
P25
P26
G5
L1
I/O
H4
L4
T1
I/O, IRDY(1)
GND
VCCO
P129
P128
P127
G1
L3
Not Connected Pins
P4
11/02/00
R4
-
-
-
-
GND*
VCCO
GND*
VCCO
7
-
Bank 7* Bank 7*
VCCO VCCO
Bank 6* Bank 6*
J2 M1
XC2S100 Device Pinouts
VCCO
6
P127
P26
P27
-
XC2S100 Pad
Name
I/O, TRDY(1)
VCCINT
I/O
6
-
P126
272
-
Bndry
Function Bank TQ144 PQ208 FG256 FG456 Scan
P125
P28 VCCINT* VCCINT*
GND
TMS
I/O
-
P143
P1
P2
P3
-
GND*
D3
GND*
D3
-
6
6
6
6
-
P124
P29
-
H1
J4
M3
M4
M5
N2
281
284
287
290
-
-
P142
-
I/O
-
7
7
7
7
7
7
-
P141
C2
B1
185
191
194
197
200
203
-
I/O
P123
P30
P31
P32
P33
P34
P35
-
J1
I/O
-
A2
F5
I/O, VREF
GND
I/O
P122
J3
I/O
P140
P4
-
B1
D2
-
GND*
K5
K2
K1
K3
L1
GND*
N3
I/O
-
-
-
-
-
-
E3
6
6
6
6
6
6
-
293
296
302
305
308
311
I/O
-
E3
G5
I/O
-
N4
I/O
P5
-
D2
F3
I/O
-
P2
GND
VCCO
GND*
GND*
I/O
-
P4
7
-
VCCO
Bank 7* Bank 7*
C1 E2
VCCO
-
I/O
P121
P120
P36
P37
P3
I/O
L2
R2
I/O, VREF
7
P139
P6
206
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
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XC2S100 Device Pinouts (Continued)
XC2S100 Device Pinouts (Continued)
XC2S100 Pad
Name
XC2S100 Pad
Name
Bndry
Bndry
Function Bank TQ144 PQ208 FG256 FG456 Scan
Function Bank TQ144 PQ208 FG256 FG456 Scan
VCCINT
VCCO
-
-
-
P38 VCCINT* VCCINT
*
-
-
I/O, VREF
I/O
5
5
-
P100
P99
P98
-
P62
P63
P64
P65
R5
P6
W8
Y8
407
6
P39
VCCO
VCCO
410
Bank 6* Bank 6*
GND
GND*
GND*
-
-
GND
I/O
-
P119
P40
P41
P42
-
GND*
K4
GND*
T1
-
VCCO
5
VCCO
Bank 5* Bank 5*
VCCO
6
6
6
6
6
6
6
6
P118
314
317
320
323
326
332
335
-
I/O, VREF
I/O
P117
M1
-
R4
VCCINT
I/O
-
P97
P66 VCCINT* VCCINT*
-
-
T2
5
5
5
5
5
5
-
P96
P67
P68
-
R6
M7
-
AA8
V9
413
416
419
422
428
431
-
I/O
P116
P43
-
L4
U1
I/O
P95
I/O
-
M2
L3
R5
I/O
-
AB9
Y9
I/O
-
P115
-
P44
P45
-
U2
I/O
-
P69
P70
P71
P72
P73
P74
-
N7
T6
I/O, VREF
VCCO
N1
T3
I/O
-
-
W10
AB10
GND*
Y10
VCCO
VCCO
I/O
P7
GND*
P8
R7
T7
Bank 6* Bank 6*
GND
I/O, VREF
I/O
-
GND
I/O
-
-
-
GND*
P1
GND*
T4
-
5
5
5
5
-
P94
-
434
437
440
443
-
6
6
6
6
6
6
6
-
-
P46
-
338
341
344
347
350
356
359
362
-
V11
I/O
-
L5
W1
I/O
-
W11
AB11
I/O
-
-
-
U4
I/O
P93
P92
P91
P90
P75
T8
I/O
P114
-
P47
-
N2
Y1
VCCINT
I, GCK1
VCCO
P76 VCCINT* VCCINT*
I/O
M4
R1
W2
5
5
P77
P78
R8
Y11
455
-
I/O
P113
P112
P111
P110
P109
P108
P48
P49
P50
P51
P52
P53
Y2
VCCO
VCCO
I/O
M3
P2
W3
Bank 5* Bank 5*
VCCO VCCO
Bank 4* Bank 4*
M1
U5
VCCO
4
P90
P78
-
GND
M0
-
GND*
N3
GND*
AB2
VCCO
GND
I, GCK0
I/O
-
P89
P79
P80
P81
P82
-
GND*
N8
GND*
W12
U12
-
-
363
-
4
4
4
4
4
4
-
P88
456
460
466
469
472
475
-
VCCO
6
VCCO
Bank 6* Bank 6*
VCCO VCCO
Bank 5* Bank 5*
P87
N9
VCCO
5
P107
P53
-
I/O
P86
R9
Y12
I/O
-
N10
T9
AA12
AB13
AA13
GND*
Y13
M2
-
P106
P54
R3
N5
Y4
V7
364
374
377
380
383
386
-
I/O
-
P83
P84
P85
P86
P87
P88
-
I/O
5
5
5
5
5
-
-
-
I/O, VREF
GND
I/O
P85
P9
I/O
P103
P57
T2
Y6
-
GND*
M10
R10
P10
-
I/O
-
-
-
-
-
-
-
AA4
W6
4
4
4
4
4
4
-
-
478
481
487
490
493
496
-
I/O
-
P5
I/O
-
-
V13
I/O
P58
T3
Y7
I/O
AA14
V14
GND
VCCO
-
-
GND*
GND*
I/O
-
5
VCCO
VCCO
-
I/O
P84
P83
P82
-
P89
P90
T10
R11
AB15
AA15
Bank 5* Bank 5*
I/O
I/O, VREF
I/O
5
5
5
5
5
P102
P59
P60
-
T4
M6
T5
N6
-
AA5
AB5
AB6
AA7
W7
389
392
398
401
404
VCCINT
VCCO
P91 VCCINT* VCCINT*
-
4
P92
VCCO
Bank 4* Bank 4*
VCCO
-
I/O
-
P101
-
I/O
P61
-
GND
I/O
-
P81
P80
P93
P94
GND*
M11
GND*
Y15
-
I/O
4
499
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
82
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XC2S100 Device Pinouts (Continued)
XC2S100 Device Pinouts (Continued)
XC2S100 Pad
Name
XC2S100 Pad
Name
Bndry
Bndry
Function Bank TQ144 PQ208 FG256 FG456 Scan
Function Bank TQ144 PQ208 FG256 FG456 Scan
I/O, VREF
I/O
4
4
4
4
4
4
4
P79
P95
-
T11
-
AB16
AB17
V15
502
505
508
511
517
520
-
VCCO
3
-
P117
VCCO
Bank 3* Bank 3*
VCCO
-
-
VCCINT
I/O (D5)
I/O
-
-
P60
P59
-
P118 VCCINT* VCCINT*
-
I/O
P78
P96
-
N11
R12
P11
T12
VCCO
3
3
3
3
3
3
-
P119
P120
-
M16
K14
L16
K13
L15
K12
GND*
K16
J16
R21
P18
599
602
605
608
614
617
-
I/O
-
Y16
I/O
-
P77
-
P97
P98
-
AB18
AB19
VCCO
I/O
P20
I/O, VREF
VCCO
I/O
-
P121
P122
P123
P124
P125
P126
-
P21
Bank 4* Bank 4*
I/O
-
N18
GND
I/O
-
-
-
GND*
T13
N12
-
GND*
Y17
-
I/O
-
N20
4
4
4
4
4
4
4
-
-
P99
-
523
526
529
532
535
541
544
-
GND
-
GND*
N21
I/O
-
V16
I/O, VREF
I/O (D4)
I/O
3
3
3
3
-
P58
P57
-
620
623
626
629
-
I/O
-
-
W17
AB20
AA19
AA20
W18
GND*
Y19
N22
I/O
P76
-
P100
-
R13
P12
P13
T14
GND*
R14
VCCO
J14
M19
M20
VCCINT
M22
VCCO
I/O
I/O
P56
P55
P54
P53
P127
P128
P129
P130
K15
E5
I/O
P75
P74
P73
P72
P71
P101
P102
P103
P104
P105
VCCINT
I/O, TRDY(1)
VCCO
*
I/O
3
3
J15
638
-
GND
DONE
VCCO
VCCO
Bank 3* Bank 3*
VCCO VCCO
Bank 2* Bank 2*
3
4
547
-
VCCO
2
P53
P130
-
VCCO
Bank 4* Bank 4*
VCCO VCCO
Bank 3* Bank 3*
GND
I/O, IRDY(1)
I/O
-
P52
P131
P132
P133
P134
-
GND*
H16
H14
H15
J13
GND*
L20
-
VCCO
3
P70
P105
-
2
2
2
2
2
2
-
P51
641
644
650
653
656
659
-
PROGRAM
I/O (INIT)
I/O (D7)
I/O
-
P69
P106
P15
N15
N14
T15
M13
-
W20
V19
550
551
554
560
563
566
569
572
-
-
L17
3
3
3
3
3
3
3
-
P68
P107
I/O
P50
L21
P67
P108
Y21
I/O
-
L22
-
-
W21
U20
I/O (D3)
I/O, VREF
GND
I/O
P49
P135
P136
P137
P138
P139
P140
-
G16
H13
GND*
G14
G15
G12
F16
K20
K21
GND*
K22
J21
I/O
P66
P109
P48
I/O
-
-
-
-
-
-
U19
-
I/O
-
R16
M14
GND*
VCCO
T18
2
2
2
2
2
2
-
-
662
665
671
674
677
680
-
I/O
P110
W22
GND*
VCCO
I/O
-
GND
VCCO
-
-
I/O
-
J18
3
-
I/O
-
P47
P46
-
J22
Bank 3* Bank 3*
I/O
P141
P142
G13
F15
H19
H20
I/O, VREF
I/O
3
3
3
3
3
3
3
-
P65
-
P111
P112
-
L14
M15
L12
P16
-
U21
T20
575
578
584
587
590
593
596
-
I/O (D2)
VCCINT
VCCO
P143 VCCINT* VCCINT
*
I/O
-
T21
2
-
P144
VCCO
Bank 2* Bank 2*
VCCO
-
I/O
P64
-
P113
-
R18
U22
R19
T22
I/O
GND
-
P45
P44
P43
-
P145
P146
P147
-
GND*
E16
F14
-
GND*
H22
H18
G21
G18
-
I/O, VREF
I/O (D6)
GND
P63
P62
P61
P114
P115
P116
L13
N16
GND*
I/O (D1)
I/O, VREF
I/O
2
2
2
2
683
686
689
692
GND*
I/O
P42
P148
D16
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
83
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Spartan-II FPGA Family: Pinout Tables
XC2S100 Device Pinouts (Continued)
XC2S100 Device Pinouts (Continued)
XC2S100 Pad
Name
XC2S100 Pad
Name
Bndry
Bndry
Function Bank TQ144 PQ208 FG256 FG456 Scan
Function Bank TQ144 PQ208 FG256 FG456 Scan
I/O
2
2
2
2
-
-
F12
E15
G20
F19
695
701
704
-
VCCO
1
-
P170
VCCO
Bank 1* Bank 1*
VCCO
-
I/O
-
P41
-
P149
P150
-
VCCINT
I/O
-
P24
P23
P22
-
P171 VCCINT* VCCINT
*
-
I/O, VREF
VCCO
F13
F21
1
1
1
1
1
1
-
P172
P173
-
A11
C10
-
C15
B15
48
51
54
57
63
66
-
VCCO
Bank 2* Bank 2*
VCCO
I/O
GND
I/O
-
-
-
GND*
E14
C16
-
GND*
F20
-
I/O
F12
2
2
2
2
2
2
-
P151
707
710
713
716
719
725
I/O
-
P174
P175
P176
P177
P178
P179
-
B10
D10
A10
GND*
B9
C14
D13
C13
GND*
B13
I/O
-
-
-
F18
I/O
-
I/O
-
E21
D22
E20
D20
I/O
-
I/O
P40
-
P152
-
E13
B16
D14
GND
I/O, VREF
I/O
-
I/O
1
1
1
1
1
1
-
P21
-
69
72
75
78
84
90
-
I/O (DIN,
D0)
P39
P153
E10
A9
E12
I/O
-
B12
I/O (DOUT,
BUSY)
2
P38
P154
C15
C21
728
I/O
P20
P19
P18
P17
P16
P180
P181
P182
P183
P184
D9
D12
D11
A11
I/O
A8
CCLK
VCCO
2
2
P37
P36
P155
P156
D15
B22
731
-
I, GCK2
GND
VCCO
C9
VCCO
VCCO
GND*
VCCO
Bank 1* Bank 1*
VCCO VCCO
Bank 0* Bank 0*
B8 C11
GND*
VCCO
Bank 2* Bank 2*
VCCO VCCO
Bank 1* Bank 1*
1
-
VCCO
1
P35
P156
-
VCCO
0
P16
P184
P185
-
TDO
GND
TDI
2
-
P34
P157
B14
GND*
A15
B13
C13
C12
A14
-
A21
GND*
B20
-
-
P33
P158
I, GCK3
VCCINT
I/O
0
-
P15
P14
P13
-
91
-
-
P32
P159
-
P186 VCCINT* VCCINT
*
I/O (CS)
I/O (WRITE)
I/O
1
1
1
1
1
1
1
-
P31
P160
C19
0
0
0
P187
-
A7
D8
A10
B10
101
104
P30
P161
A20
3
I/O
-
-
D17
9
I/O
P29
P162
A19
12
15
18
21
-
I/O
-
-
-
-
-
-
B18
I/O
-
D12
B12
GND*
VCCO
C17
I/O
P163
D16
GND
VCCO
-
-
GND*
1
VCCO
-
Bank 1* Bank 1*
I/O, VREF
I/O
1
1
1
1
1
1
1
-
P28
P164
P165
-
C11
A13
D11
A12
-
A18
B17
24
27
33
36
39
42
45
-
-
-
I/O
D15
C16
D14
E14
A16
I/O
-
P166
-
I/O
-
I/O, VREF
I/O
P27
P26
P25
P167
P168
P169
E11
B11
GND*
GND
GND*
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
84
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Spartan-II FPGA Family: Pinout Tables
XC2S100 Device Pinouts (Continued)
XC2S100 Pad
Name
Bndry
Function Bank TQ144 PQ208 FG256 FG456 Scan
I/O
0
0
-
-
P188
P189
P190
P191
P192
P193
-
A6
B7
C10
A9
107
110
-
I/O, VREF
GND
I/O
P12
-
GND*
C8
D7
E7
GND*
B9
0
0
0
0
0
0
-
-
113
116
122
125
128
131
-
I/O
-
-
E10
A8
I/O
I/O
-
-
D9
I/O
P11
P10
P9
-
P194
P195
C7
B6
E9
I/O
A7
VCCINT
VCCO
P196 VCCINT* VCCINT*
0
P197
VCCO
VCCO
-
Bank 0* Bank 0*
GND
I/O
-
P8
P7
P6
-
P198
P199
P200
-
GND*
A5
GND*
B7
-
0
0
0
0
0
0
0
0
134
137
140
143
146
152
155
-
I/O, VREF
I/O
C6
E8
-
D8
I/O
-
P201
-
B5
C7
I/O
-
D6
D7
I/O
-
P202
P203
-
A4
D6
I/O, VREF
VCCO
P5
-
B4
C6
VCCO
VCCO
Bank 0* Bank 0*
GND
I/O
-
-
-
-
GND*
E6
GND*
B5
-
0
0
0
0
0
0
-
P204
-
158
161
164
167
170
176
-
I/O
-
D5
E7
I/O
-
-
-
E6
I/O
P4
-
P205
-
A3
B4
I/O
C5
A3
I/O
P3
P2
P1
P206
P207
P208
B3
C5
TCK
VCCO
C4
C4
0
VCCO
VCCO
-
Bank 0* Bank 0*
VCCO VCCO
Bank 7* Bank 7*
VCCO
7
P144
P208
-
04/18/01
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx PCI
cores.
2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*,
VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*,
VCCO Bank 6*, VCCO Bank 7* are internally bonded to
independent ground or power planes within the package.
3. See "VCCO Banks" for details on VCCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
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Spartan-II FPGA Family: Pinout Tables
Additional XC2S100 Package Pins (Continued)
Additional XC2S100 Package Pins
F10
F13
G17
M16
T12
T10
M7
F7
F14
H17
N16
T13
T11
N6
F8
VCCO Bank 1 Pins
F15 F16
VCCO Bank 2 Pins
J17 K16
VCCO Bank 3 Pins
N17 P17
VCCO Bank 4 Pins
U13 U14
VCCO Bank 5 Pins
U10 U7
VCCO Bank 6 Pins
N7 P6
VCCO Bank 7 Pins
F9
G10
G12
K17
R17
U15
U8
G11
G13
L16
T17
U16
U9
TQ144
Not Connected Pins
P104
P105
P56
-
-
-
-
-
-
11/02/00
PQ208
Not Connected Pins
P55
-
-
11/02/00
FG256
VCCINT Pins
C3
M5
C14
M12
D4
N4
D13
N13
E5
P3
E12
P14
R6
T6
VCCO Bank 0 Pins
E8
E9
F8
F9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G6
H6
J6
K6
K7
L7
VCCO Bank 1 Pins
GND Pins
-
-
A1
J9
A22
J10
B2
B21
J12
C3
J13
K13
L13
M13
N13
P13
AB1
C20
J14
VCCO Bank 2 Pins
J11
K11
L11
M11
N11
P11
AA2
H11
J11
L9
H12
J12
M9
M8
J6
-
-
K9
L9
M9
N9
P9
Y3
K10
L10
M10
N10
P10
Y20
K12
L12
K14
L14
VCCO Bank 3 Pins
-
-
M12
N12
P12
AA21
M14
N14
P14
AB22
VCCO Bank 4 Pins
-
-
VCCO Bank 5 Pins
L8
-
-
Not Connected Pins
VCCO Bank 6 Pins
A2
A14
B11
C8
A4
A15
B14
C9
A5
A17
B16
C12
D10
E13
F4
A6
B3
A12
B6
A13
B8
J5
-
-
VCCO Bank 7 Pins
B19
C18
D18
E15
F11
G22
J19
L5
C1
C2
H5
H6
-
-
C22
D19
E16
F22
H1
D1
GND Pins
D4
D5
D21
E17
G2
A1
F10
G10
J7
A16
F11
G11
J8
B2
G6
H7
J9
B15
G7
F6
G8
H9
K6
L6
F7
G9
H10
K7
E4
E11
E22
G4
E19
G3
H8
G19
J4
H21
K2
J10
K11
R15
J1
J3
J20
L18
M21
P19
T5
K8
K9
K10
R2
L7
K18
M2
K19
M6
L2
L19
N1
L10
L11
T1
T16
M17
P1
M18
P5
Not Connected Pins
N5
N19
R3
P22
T19
V10
V8
P4
R4
-
-
-
-
R1
R20
U18
V3
R22
V1
11/02/00
U3
U11
V17
V21
W14
Y18
AA10
AB3
AB21
V2
FG456
V12
V20
W13
Y14
AA9
AA22
V4
V6
VCCINT Pins
V22
W15
Y22
AA11
AB4
-
W4
W16
AA1
AA16
AB7
-
W5
W19
AA3
AA17
AB8
-
W9
Y5
E5
G9
J7
E18
G14
J16
T8
F6
G15
P7
F17
G7
H7
R7
T15
-
G8
H16
R16
T16
-
G16
P16
T14
V18
AA6
AA18
AB12
-
T7
U6
T9
U17
V5
AB14
11/02/00
VCCO Bank 0 Pins
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
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XC2S150 Device Pinouts (Continued)
XC2S150 Device Pinouts
XC2S150 Pad Name
XC2S150 Pad Name
Bndry
Scan
Bndry
Scan
Function
I/O
Bank
PQ208
P22
-
FG256
G5
FG456
L1
Function
GND
Bank
PQ208
FG256
GND*
D3
FG456
GND*
D3
7
7
7
7
-
314
317
320
323
-
-
P1
-
I/O
-
L5
TMS
I/O
-
P2
-
I/O
P23
P24
P25
P26
H4
L4
7
7
7
7
-
P3
C2
B1
221
224
227
230
-
I/O, IRDY(1)
G1
L3
I/O
-
-
E4
GND
GND*
GND*
I/O
-
-
-
C1
VCCO
7
VCCO
VCCO
-
I/O
A2
F5
Bank 7* Bank 7*
VCCO VCCO
Bank 6* Bank 6*
GND
I/O
-
GND*
B1
GND*
D2
VCCO
6
P26
-
7
7
7
7
7
-
P4
-
233
236
239
242
245
-
I/O
-
E3
I/O, TRDY(1)
VCCINT
I/O
6
-
P27
P28
-
J2
VCCINT
-
M1
VCCINT
M6
326
-
I/O
-
-
F4
*
*
I/O
-
E3
G5
6
6
6
6
6
6
332
335
338
341
344
-
I/O
P5
-
D2
F3
I/O
P29
-
H1
M3
GND
VCCO
GND*
GND*
I/O
J4
M4
7
-
VCCO
Bank 7* Bank 7*
VCCO
-
I/O
P30
P31
-
J1
M5
I/O, VREF
VCCO
J3
N2
I/O, VREF
I/O
7
7
7
7
7
7
7
7
7
-
P6
P7
-
C1
F3
E2
E1
248
251
254
257
260
263
266
269
272
-
VCCO
Bank 6* Bank 6*
VCCO
I/O
-
G4
GND
I/O
-
P32
P33
P34
-
GND*
K5
GND*
N3
-
I/O
-
-
G3
6
6
6
6
6
6
6
6
-
347
350
356
359
362
365
371
374
-
I/O
-
E2
E4
-
H5
I/O
K2
N4
I/O
P8
-
F2
I/O
-
N5
I/O
F1
I/O
P35
-
K1
P2
I/O, VREF
I/O
P9
P10
P11
P12
D1
E1
GND*
VCCO
H4
I/O
K3
P4
G1
I/O
-
-
R1
GND
VCCO
GND*
I/O
P36
P37
P38
P39
L1
P3
7
VCCO
-
I/O
L2
R2
Bank 7* Bank 7*
VCCINT
VCCO
VCCINT
VCCO
Bank 6* Bank 6*
*
VCCINT
*
VCCINT
I/O
-
P13
P14
P15
-
VCCINT
*
VCCINT
H3
*
-
6
VCCO
-
7
7
7
7
7
7
7
7
-
F2
275
278
284
287
290
293
299
302
-
I/O
G3
-
H2
GND
I/O
-
P40
P41
P42
-
GND*
K4
M1
-
GND*
T1
-
I/O
H1
6
6
6
6
6
6
6
6
6
6
377
380
383
386
389
392
395
398
401
-
I/O
-
F1
J5
I/O, VREF
I/O
R4
I/O
P16
-
F4
J2
T2
I/O
-
J3
I/O
P43
-
L4
U1
I/O
P17
P18
P19
-
F5
K5
I/O
M2
-
R5
I/O
G2
GND*
VCCO
K1
I/O
-
V1
GND
VCCO
GND*
I/O
-
-
T5
7
VCCO
-
I/O
P44
P45
-
L3
U2
Bank 7* Bank 7*
I/O, VREF
VCCO
N1
VCCO
T3
I/O, VREF
I/O
7
7
7
P20
P21
-
H3
G4
H2
K3
K4
L6
305
308
311
VCCO
Bank 6* Bank 6*
I/O
GND
-
-
GND* GND*
-
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
87
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XC2S150 Device Pinouts (Continued)
XC2S150 Device Pinouts (Continued)
XC2S150 Pad Name
XC2S150 Pad Name
Bndry
Scan
Bndry
Scan
Function
I/O
Bank
PQ208
FG256
P1
FG456
T4
Function
VCCO
Bank
PQ208
FG256
FG456
6
6
6
6
6
-
P46
404
407
410
413
416
-
5
P65
VCCO
Bank 5* Bank 5*
VCCO
-
I/O
-
-
L5
W1
VCCINT
I/O
-
P66
P67
P68
-
VCCINT
R6
M7
-
*
VCCINT
AA8
V9
*
-
I/O
-
V2
5
5
5
5
5
5
5
5
-
494
497
503
506
509
512
518
521
-
I/O
-
-
U4
I/O
I/O
P47
-
N2
GND*
M4
-
Y1
I/O
W9
GND
I/O
GND*
W2
I/O
-
-
AB9
Y9
6
6
6
6
6
-
-
419
422
425
428
431
434
-
I/O
P69
-
N7
-
I/O
-
V3
I/O
V10
I/O
-
-
V4
I/O
P70
P71
P72
-
T6
W10
AB10
GND*
VCCO
I/O
P48
P49
P50
P51
P52
P53
R1
M3
P2
Y2
I/O
P7
I/O
W3
GND
VCCO
GND*
VCCO
M1
U5
5
-
GND
M0
-
GND*
N3
VCCO
Bank 6* Bank 6*
VCCO VCCO
Bank 5* Bank 5*
GND*
AB2
VCCO
Bank 5* Bank 5*
-
435
-
I/O, VREF
I/O
5
5
5
5
5
-
P73
P74
-
P8
R7
Y10
V11
524
527
530
533
536
-
VCCO
6
I/O
T7
W11
VCCO
5
P53
-
I/O
P75
-
T8
AB11
U11
M2
-
P54
R3
Y4
W5
436
443
446
449
-
I/O
-
I/O
5
5
5
-
-
-
-
VCCINT
I, GCK1
VCCO
P76
P77
P78
VCCINT
*
VCCINT
Y11
*
I/O
-
AB3
V7
5
5
R8
545
-
I/O
-
N5
GND*
T2
VCCO
VCCO
Bank 5* Bank 5*
VCCO VCCO
Bank 4* Bank 4*
GND
I/O
-
GND*
Y6
VCCO
4
P78
-
5
5
5
5
5
-
P57
452
455
458
461
464
-
I/O
-
-
AA4
AB4
W6
GND
I, GCK0
I/O
-
P79
P80
P81
-
GND*
N8
GND*
W12
U12
-
I/O
-
-
4
4
4
4
4
4
4
4
546
550
553
556
559
562
565
-
I/O
-
P5
N9
I/O
P58
T3
Y7
I/O
-
V12
GND
VCCO
-
-
GND*
GND*
I/O
P82
-
R9
Y12
5
VCCO
Bank 5* Bank 5*
VCCO
-
I/O
N10
T9
AA12
AB13
AA13
VCCO
I/O
P83
P84
-
I/O, VREF
I/O
5
5
5
5
5
5
5
5
5
-
P59
P60
-
T4
M6
-
AA5
AB5
V8
467
470
473
476
479
482
485
488
491
-
I/O, VREF
VCCO
P9
VCCO
Bank 4* Bank 4*
I/O
I/O
-
-
AA6
AB6
AA7
W7
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
P85
P86
P87
-
GND*
M10
R10
-
GND*
Y13
-
I/O
-
T5
N6
-
4
4
4
4
4
4
4
568
571
577
580
583
586
592
I/O
P61
-
V13
I/O
W14
AA14
V14
I/O, VREF
I/O
P62
P63
P64
R5
P6
GND*
W8
P88
-
P10
-
Y8
GND
GND*
-
-
Y14
P89
T10
AB15
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
88
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XC2S150 Device Pinouts (Continued)
XC2S150 Device Pinouts (Continued)
XC2S150 Pad Name
XC2S150 Pad Name
Bndry
Scan
Bndry
Scan
Function
I/O
VCCINT
VCCO
Bank
PQ208
P90
FG256
FG456
Function
I/O
Bank
PQ208
FG256
-
FG456
U19
4
-
R11
AA15
595
3
3
3
3
-
-
677
680
683
686
-
P91
VCCINT
VCCO
Bank 4* Bank 4*
*
VCCINT
*
-
-
I/O
-
-
V21
4
P92
VCCO
I/O
-
R16
M14
GND*
VCCO
T18
I/O
P110
W22
GND*
VCCO
GND
I/O
-
P93
P94
P95
-
GND*
M11
T11
-
GND*
Y15
-
GND
VCCO
-
-
4
4
4
4
4
4
4
4
4
4
598
601
604
607
610
613
616
619
622
-
3
-
I/O, VREF
I/O
AB16
AB17
V15
Bank 3* Bank 3*
I/O, VREF
I/O
3
3
3
3
3
3
3
3
3
-
P111
P112
-
L14
M15
-
U21
T20
689
692
695
698
701
704
707
710
713
-
I/O
P96
-
N11
R12
-
I/O
Y16
I/O
T19
I/O
-
AA17
W16
AB18
AB19
VCCO
I/O
-
-
V22
T21
I/O
-
-
I/O
-
L12
P16
-
I/O
P97
P98
-
P11
T12
VCCO
I/O
P113
-
R18
U22
R19
T22
I/O, VREF
VCCO
I/O
I/O, VREF
I/O (D6)
GND
VCCO
P114
P115
P116
P117
L13
N16
GND*
VCCO
Bank 4* Bank 4*
GND
I/O
-
-
GND*
T13
N12
-
GND*
Y17
-
GND*
4
4
4
4
4
-
P99
625
628
631
634
637
-
3
VCCO
-
I/O
-
V16
Bank 3* Bank 3*
I/O
-
AA18
W17
AB20
GND*
AA19
V17
VCCINT
I/O (D5)
I/O
-
P118
P119
P120
-
VCCINT
M16
K14
-
*
VCCINT
R21
*
-
I/O
-
-
3
3
3
3
3
3
3
3
-
716
719
725
728
731
734
740
743
-
I/O
P100
-
R13
GND*
P12
-
P18
GND
I/O
I/O
P19
4
4
4
4
4
-
-
640
643
646
649
652
-
I/O
-
L16
K13
-
P20
I/O
-
I/O
P121
-
P21
I/O
-
-
Y18
I/O
N19
I/O
P101
P102
P103
P104
P105
P13
T14
GND*
R14
VCCO
AA20
W18
GND*
Y19
I/O
P122
P123
P124
-
L15
K12
GND*
VCCO
N18
I/O
I/O
N20
GND
DONE
VCCO
GND
VCCO
GND*
3
4
655
-
3
VCCO
-
Bank 3* Bank 3*
VCCO
Bank 4* Bank 4*
VCCO VCCO
Bank 3* Bank 3*
I/O, VREF
I/O (D4)
I/O
3
3
3
3
3
-
P125
P126
-
K16
J16
N21
N22
746
749
752
755
758
-
VCCO
3
P105
-
J14
M19
PROGRAM
I/O (INIT)
I/O (D7)
I/O
-
P106
P15
N15
N14
-
W20
V19
658
659
662
665
668
671
-
I/O
P127
-
K15
-
M20
3
3
3
3
3
-
P107
I/O
M18
P108
Y21
VCCINT
I/O, TRDY(1)
VCCO
P128
P129
P130
VCCINT
*
VCCINT
M22
*
-
V20
3
3
J15
764
-
I/O
-
-
AA22
W21
GND*
U20
VCCO
VCCO
I/O
-
-
T15
GND*
M13
Bank 3* Bank 3*
VCCO VCCO
Bank 2* Bank 2*
GND* GND*
GND
VCCO
GND
2
-
P130
P131
-
-
I/O
3
P109
674
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
89
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Spartan-II FPGA Family: Pinout Tables
XC2S150 Device Pinouts (Continued)
XC2S150 Device Pinouts (Continued)
XC2S150 Pad Name
XC2S150 Pad Name
Bndry
Scan
Bndry
Scan
Function
I/O, IRDY(1)
I/O
Bank
PQ208
P132
P133
-
FG256
H16
H14
-
FG456
L20
Function
I/O
Bank
PQ208
-
FG256
-
FG456
C22
2
2
2
2
2
2
2
2
767
770
773
776
779
782
785
-
2
2
2
866
869
872
L17
I/O (DIN, D0)
P153
P154
D14
C15
D20
I/O
L18
I/O (DOUT,
BUSY)
C21
I/O
P134
-
H15
J13
L21
CCLK
VCCO
2
2
P155
P156
D15
B22
875
-
I/O
L22
VCCO
VCCO
I/O (D3)
I/O, VREF
VCCO
P135
P136
-
G16
H13
VCCO
K20
K21
VCCO
Bank 2* Bank 2*
VCCO VCCO
Bank 1* Bank 1*
VCCO
1
P156
-
Bank 2* Bank 2*
TDO
GND
TDI
2
-
P157
B14
GND*
A15
B13
C13
-
A21
GND*
B20
-
-
GND
I/O
-
P137
P138
P139
-
GND*
G14
G15
-
GND*
K22
-
P158
2
2
2
2
2
2
2
2
-
788
791
797
800
803
806
812
815
-
-
P159
-
I/O
J21
I/O (CS)
I/O (WRITE)
I/O
1
1
1
1
1
-
P160
C19
0
I/O
J20
P161
A20
3
I/O
P140
-
G12
F16
-
J18
-
B19
6
I/O
J22
I/O
-
-
C18
9
I/O
-
J19
I/O
-
C12
GND*
A14
-
D17
12
-
I/O
P141
P142
P143
P144
G13
F15
VCCINT
VCCO
H19
H20
VCCINT
VCCO
GND
I/O
-
GND*
A19
I/O (D2)
VCCINT
VCCO
1
1
1
1
1
-
P162
15
18
21
24
27
-
*
*
I/O
-
B18
2
-
I/O
-
-
E16
Bank 2* Bank 2*
I/O
-
D12
B12
GND*
VCCO
C17
GND
I/O (D1)
I/O, VREF
I/O
-
P145
GND*
E16
F14
-
GND*
H22
H18
G21
G18
G20
G19
F22
-
I/O
P163
D16
2
2
2
2
2
2
2
2
2
2
P146
818
821
824
827
830
833
836
839
842
-
GND
VCCO
-
-
GND*
P147
1
VCCO
-
-
Bank 1* Bank 1*
I/O
P148
D16
F12
-
I/O, VREF
I/O
1
1
1
1
1
1
1
1
1
-
P164
P165
-
C11
A13
-
A18
B17
30
33
36
39
42
45
48
51
54
-
I/O
-
I/O
-
I/O
E15
I/O
-
-
I/O
-
-
A17
I/O
P149
P150
-
E15
F13
VCCO
F19
I/O
-
D11
A12
-
D15
C16
D14
E14
I/O, VREF
VCCO
F21
I/O
P166
-
VCCO
I/O
Bank 2* Bank 2*
I/O, VREF
I/O
P167
P168
P169
P170
E11
B11
GND*
VCCO
GND
I/O
-
-
GND*
E14
C16
-
GND*
F20
-
A16
2
2
2
2
2
-
P151
845
848
851
854
857
-
GND
VCCO
GND*
I/O
-
F18
1
VCCO
-
I/O
-
E22
Bank 1* Bank 1*
I/O
-
-
E21
VCCINT
I/O
-
P171
P172
P173
-
VCCINT
*
VCCINT
C15
*
-
I/O
P152
E13
GND*
B16
-
D22
GND*
E20
1
1
1
1
A11
57
60
66
69
GND
I/O
-
-
-
I/O
C10
B15
2
2
860
863
I/O
-
-
A15
I/O
D21
I/O
-
F12
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
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XC2S150 Device Pinouts (Continued)
XC2S150 Device Pinouts (Continued)
XC2S150 Pad Name
XC2S150 Pad Name
Bndry
Scan
Bndry
Scan
Function
I/O
Bank
PQ208
P174
-
FG256
B10
FG456
C14
Function
VCCINT
Bank
PQ208
P196
FG256
VCCINT
VCCO
Bank 0* Bank 0*
FG456
VCCINT
VCCO
1
1
1
1
-
72
75
81
84
-
-
*
*
-
-
I/O
-
B14
VCCO
0
P197
I/O
P175
P176
P177
-
D10
A10
D13
GND
I/O
-
P198
GND*
A5
C6
-
GND*
B7
-
I/O
C13
0
0
0
0
0
0
0
0
0
0
P199
161
164
167
170
173
176
179
182
185
-
GND
VCCO
GND*
GND*
I/O, VREF
I/O
P200
E8
1
VCCO
Bank 1* Bank 1*
VCCO
-
-
D8
I/O, VREF
I/O
1
1
1
1
1
1
1
-
P178
P179
-
B9
E10
A9
B13
E12
87
90
93
96
99
102
108
-
I/O
P201
B5
D6
-
C7
I/O
-
D7
I/O
B12
I/O
-
B6
I/O
P180
-
D9
D12
C12
D11
A11
I/O
-
-
A5
I/O
-
I/O
P202
P203
-
A4
B4
VCCO
D6
I/O
P181
P182
P183
P184
A8
I/O, VREF
VCCO
C6
I, GCK2
GND
VCCO
C9
VCCO
Bank 0* Bank 0*
GND*
VCCO
Bank 1* Bank 1*
VCCO VCCO
Bank 0* Bank 0*
GND*
VCCO
GND
I/O
-
-
GND*
E6
D5
-
GND*
B5
-
1
-
0
0
0
0
0
-
P204
188
191
194
197
200
-
VCCO
0
P184
-
I/O
-
E7
I/O
-
A4
I, GCK3
VCCINT
I/O
0
-
P185
P186
-
B8
VCCINT
-
C11
VCCINT
E11
109
-
I/O
-
-
E6
*
*
I/O
P205
A3
GND*
C5
-
B4
0
0
0
0
0
0
116
119
122
125
128
-
GND
I/O
-
GND*
A3
I/O
P187
-
A7
A10
0
0
0
0
-
-
203
206
209
212
-
I/O
D8
B10
I/O
-
B3
I/O
P188
P189
-
A6
C10
I/O
-
-
D5
I/O, VREF
VCCO
B7
A9
I/O
P206
P207
P208
B3
C4
VCCO
C5
VCCO
Bank 0* Bank 0*
VCCO
TCK
VCCO
C4
0
VCCO
-
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
P190
P191
P192
-
GND*
C8
D7
-
GND*
B9
-
Bank 0* Bank 0*
VCCO VCCO
Bank 7* Bank 7*
0
0
0
0
0
0
0
0
131
134
140
143
146
149
155
158
VCCO
7
P208
-
E10
D10
A8
04/18/01
P193
-
E7
-
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx PCI
cores.
2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*,
VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*,
VCCO Bank 6*, VCCO Bank 7* are internally bonded to
independent ground or power planes within the package.
D9
-
-
B8
P194
P195
C7
B6
E9
A7
3. See "VCCO Banks" for details on VCCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
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Additional XC2S150 Package Pins (Continued)
Additional XC2S150 Package Pins
FG456
PQ208
VCCINT Pins
Not Connected Pins
E5
G9
J7
E18
G14
J16
T8
F6
G15
P7
F17
G16
P16
T14
V18
G7
H7
R7
T15
-
G8
H16
R16
T16
-
P55
P56
-
-
-
-
11/02/00
FG256
T7
U6
T9
VCCINT Pins
U17
V5
C3
M5
C14
M12
D4
N4
D13
N13
E5
P3
E12
P14
VCCO Bank 0 Pins
F9 F10
VCCO Bank 1 Pins
F15 F16
VCCO Bank 2 Pins
J17 K16
VCCO Bank 3 Pins
N17 P17
VCCO Bank 4 Pins
U13 U14
VCCO Bank 5 Pins
U7 U8
VCCO Bank 6 Pins
N7 P6
VCCO Bank 7 Pins
F7
F13
G17
M16
T12
T10
M7
F8
F14
H17
N16
T13
T11
N6
G10
G12
K17
R17
U15
U9
G11
G13
L16
T17
U16
U10
T6
VCCO Bank 0 Pins
E8
E9
F8
F9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCCO Bank 1 Pins
-
-
V
CCO Bank 2 Pins
H11
J11
L9
H12
J12
M9
M8
J6
-
-
VCCO Bank 3 Pins
-
-
VCCO Bank 4 Pins
-
-
VCCO Bank 5 Pins
L8
-
-
R6
VCCO Bank 6 Pins
J5
-
-
G6
H6
J6
K6
K7
L7
VCCO Bank 7 Pins
GND Pins
H5
H6
-
-
A1
J9
A22
J10
B2
B21
J12
C3
J13
K13
L13
M13
N13
P13
AB1
C20
J14
GND Pins
J11
K11
L11
M11
N11
P11
AA2
A1
F10
G10
J7
A16
F11
G11
J8
B2
G6
H7
J9
B15
G7
F6
G8
H9
K6
L6
F7
G9
H10
K7
K9
L9
M9
N9
P9
Y3
K10
L10
M10
N10
P10
Y20
K12
L12
K14
L14
H8
M12
N12
P12
AA21
M14
N14
P14
AB22
J10
K11
R15
K8
K9
K10
R2
L7
L10
L11
T1
T16
Not Connected Pins
Not Connected Pins
P4
R4
-
-
-
-
A2
B16
D18
G2
A6
C2
A12
C8
A13
C9
A14
D1
B11
D4
11/02/00
D19
G22
K19
N1
E13
H21
L2
E17
J1
E19
J4
F11
K2
K18
M21
R20
W13
AA3
L19
P5
M2
P22
V6
M17
R3
P1
R22
W15
AA9
AB12
U3
U18
Y5
W4
AA1
AB7
-
W19
AA10
AB14
Y22
AA16
-
AA11
AB21
AB8
11/02/00
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
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XC2S200 Device Pinouts (Continued)
XC2S200 Device Pinouts
XC2S200 Pad Name
XC2S200 Pad Name
Bndry
Scan
Bndry
Scan
Function
VCCO
Bank
PQ208
FG256
FG456
Function
GND
Bank
PQ208
FG256
GND*
D3
FG456
GND*
D3
7
-
VCCO
Bank 7* Bank 7*
VCCO
-
-
P1
-
TMS
I/O
-
P2
-
I/O, VREF
I/O
7
7
7
7
7
7
7
7
-
P20
P21
-
H3
G4
-
K3
K4
350
353
359
362
365
368
374
377
-
7
7
7
7
-
P3
C2
B1
257
263
266
269
-
I/O
-
-
E4
I/O
K2
I/O
-
-
C1
I/O
-
H2
L6
I/O
-
-
A2
F5
I/O
P22
-
G5
-
L1
GND
I/O, VREF
I/O
GND*
B1
GND*
D2
I/O
L5
7
7
7
-
P4
-
272
275
281
-
I/O
P23
P24
P25
P26
H4
L4
-
E3
I/O, IRDY(1)
GND
VCCO
G1
GND*
VCCO
Bank 7* Bank 7*
VCCO VCCO
Bank 6* Bank 6*
L3
I/O
-
-
F4
GND*
GND
I/O
-
GND*
E3
GND*
G5
7
VCCO
-
7
7
-
-
284
287
-
I/O
P5
-
D2
F3
VCCO
6
P26
-
GND
VCCO
GND*
VCCO
GND*
VCCO
I/O, TRDY(1)
VCCINT
I/O
6
-
P27
P28
-
J2
VCCINT
-
M1
VCCINT
M6
380
-
7
-
-
Bank 7* Bank 7*
*
*
I/O, VREF
I/O
7
7
7
7
7
-
P6
P7
-
C1
F3
E2
E1
290
293
296
299
302
-
6
6
6
6
6
6
6
389
392
395
398
404
407
-
I/O
P29
-
H1
M3
I/O
-
G4
I/O
J4
M4
I/O
-
-
G3
I/O
-
-
N1
I/O
-
E2
H5
I/O
P30
P31
-
J1
M5
GND
I/O
-
GND*
E4
GND*
F2
I/O, VREF
VCCO
J3
N2
7
7
7
7
-
P8
-
305
308
314
317
-
VCCO
Bank 6* Bank 6*
VCCO
I/O
-
F1
I/O, VREF
I/O
P9
P10
P11
P12
D1
E1
H4
GND
I/O
-
P32
P33
P34
-
GND*
GND*
N3
-
G1
6
6
6
6
6
-
K5
410
413
416
419
422
-
GND
VCCO
GND*
VCCO
GND*
VCCO
I/O
K2
N4
7
-
I/O
-
-
P1
Bank 7* Bank 7*
I/O
-
N5
VCCINT
I/O
-
P13
P14
P15
-
VCCINT
*
VCCINT
H3
*
-
I/O
P35
-
K1
P2
7
7
7
7
7
-
F2
320
323
326
329
332
-
GND
I/O
GND*
K3
GND*
P4
I/O
G3
H2
6
6
6
6
6
-
-
425
428
431
434
437
-
I/O
-
-
J4
I/O
-
-
R1
I/O
-
H1
I/O
-
-
P5
I/O
-
F1
GND*
F4
-
J5
I/O
P36
P37
P38
P39
L1
P3
GND
I/O
-
GND*
J2
I/O
L2
R2
7
7
7
7
7
-
P16
-
335
338
341
344
347
-
VCCINT
VCCO
VCCINT
VCCO
Bank 6* Bank 6*
*
VCCINT
*
I/O
J3
6
VCCO
-
I/O
-
-
J1
I/O
P17
P18
P19
F5
G2
GND*
K5
GND
-
P40
P41
P42
GND*
K4
GND*
T1
-
I/O
K1
I/O
6
6
440
443
GND
GND*
I/O, VREF
M1
R4
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
93
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Spartan-II FPGA Family: Pinout Tables
XC2S200 Device Pinouts (Continued)
XC2S200 Device Pinouts (Continued)
XC2S200 Pad Name
XC2S200 Pad Name
Bndry
Scan
Bndry
Scan
Function
I/O
Bank
PQ208
FG256
FG456
T2
Function
VCCO
Bank
PQ208
FG256
FG456
6
6
-
-
-
L4
449
452
-
5
-
VCCO
Bank 5* Bank 5*
VCCO
-
I/O
P43
U1
I/O, VREF
I/O
5
5
5
5
5
-
P59
P60
-
T4
M6
-
AA5
AB5
V8
545
548
551
554
557
-
GND
I/O
-
GND*
M2
-
GND*
R5
6
6
6
6
6
6
-
455
458
461
464
467
-
I/O
I/O
-
-
V1
I/O
-
-
AA6
AB6
GND*
AA7
W7
I/O
-
T5
I/O
-
T5
I/O
P44
P45
-
L3
U2
GND
I/O
-
GND*
N6
-
I/O, VREF
VCCO
N1
VCCO
T3
5
5
5
5
-
P61
-
560
563
569
572
-
VCCO
Bank 6* Bank 6*
I/O
GND
I/O
-
6
6
-
-
GND*
P1
GND*
T4
-
I/O, VREF
I/O
P62
P63
P64
P65
R5
P6
W8
P46
470
473
-
Y8
I/O
-
L5
W1
GND
VCCO
GND*
GND*
GND
I/O
-
-
GND*
-
GND*
V2
5
VCCO
Bank 5* Bank 5*
VCCO
-
6
6
6
-
476
482
485
-
VCCINT
I/O
-
P66
VCCINT
*
VCCINT
AA8
V9
*
-
I/O
-
-
U4
5
5
5
5
5
-
P67
R6
575
578
581
584
587
-
I/O, VREF
GND
I/O
P47
-
N2
Y1
I/O
P68
M7
GND*
M4
-
GND*
W2
I/O
-
-
AB8
W9
6
6
6
6
6
-
-
488
491
494
500
503
506
-
I/O
-
-
-
I/O
-
V3
I/O
-
-
AB9
GND*
Y9
I/O
-
-
V4
GND
I/O
GND*
N7
-
I/O
P48
P49
P50
P51
P52
P53
R1
Y2
5
5
5
5
5
-
P69
-
590
593
596
599
602
-
I/O
M3
P2
W3
I/O
V10
M1
U5
I/O
-
-
AA9
W10
AB10
GND*
VCCO
GND
M0
-
GND*
N3
GND*
AB2
VCCO
I/O
P70
P71
P72
-
T6
-
507
-
I/O
P7
VCCO
6
VCCO
Bank 6* Bank 6*
VCCO VCCO
Bank 5* Bank 5*
GND
VCCO
GND*
VCCO
VCCO
5
P53
-
5
-
Bank 5* Bank 5*
M2
-
P54
R3
Y4
W5
508
518
521
524
-
I/O, VREF
I/O
5
5
5
5
5
5
-
P73
P74
-
P8
R7
Y10
V11
605
608
614
617
620
623
-
I/O
5
5
5
-
-
-
-
I/O
-
AB3
V7
I/O
-
AA10
W11
I/O
-
N5
GND*
T2
-
I/O
-
T7
GND
I/O, VREF
I/O
-
GND*
Y6
I/O
P75
-
T8
AB11
U11
5
5
5
5
5
-
P57
527
530
536
539
542
-
I/O
-
-
AA4
AB4
W6
VCCINT
I, GCK1
VCCO
P76
P77
P78
VCCINT
*
VCCINT
Y11
*
I/O
-
-
5
5
R8
635
-
I/O
-
P58
-
P5
T3
GND*
VCCO
VCCO
Bank 5* Bank 5*
VCCO VCCO
Bank 4* Bank 4*
GND* GND*
I/O
Y7
VCCO
GND
4
-
P78
P79
-
-
GND
GND*
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Product Specification
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Module 4 of 4
94
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Spartan-II FPGA Family: Pinout Tables
XC2S200 Device Pinouts (Continued)
XC2S200 Device Pinouts (Continued)
XC2S200 Pad Name
XC2S200 Pad Name
Bndry
Scan
Bndry
Scan
Function
I, GCK0
Bank
PQ208
FG256
N8
FG456
W12
U12
Function
I/O
Bank
PQ208
FG256
-
FG456
W17
4
4
4
4
4
4
4
4
4
P80
P81
-
636
640
646
649
652
655
661
664
-
4
4
-
-
739
742
-
I/O
N9
I/O, VREF
GND
I/O
P100
-
R13
GND*
P12
-
AB20
GND*
AA19
V17
I/O
-
V12
I/O
P82
-
R9
Y12
4
4
4
4
4
-
-
745
748
751
757
760
-
I/O
N10
-
AA12
W13
AB13
AA13
VCCO
I/O
-
I/O
-
I/O
-
-
Y18
I/O
P83
P84
-
T9
I/O
P101
P102
P103
P104
P105
P13
T14
GND*
R14
VCCO
Bank 4* Bank 4*
VCCO VCCO
Bank 3* Bank 3*
AA20
W18
I/O, VREF
VCCO
P9
I/O
VCCO
Bank 4* Bank 4*
GND
DONE
VCCO
GND*
Y19
3
4
763
-
GND
I/O
-
P85
P86
P87
-
GND*
M10
R10
-
GND*
Y13
-
VCCO
4
4
4
4
4
-
667
670
673
676
679
-
I/O
V13
VCCO
3
P105
-
I/O
AB14
W14
PROGRAM
I/O (INIT)
I/O (D7)
I/O
-
P106
P15
N15
N14
-
W20
V19
766
767
770
776
779
782
-
I/O
-
-
3
3
3
3
3
-
P107
I/O
P88
-
P10
GND*
-
AA14
GND*
V14
P108
Y21
GND
I/O
-
V20
4
4
4
4
4
-
-
682
685
688
691
694
-
I/O
-
-
AA22
W21
GND*
U20
I/O
-
-
Y14
I/O
-
T15
GND*
M13
-
I/O
-
-
W15
GND
I/O, VREF
I/O
-
I/O
P89
P90
P91
P92
T10
R11
VCCINT
VCCO
AB15
AA15
VCCINT
VCCO
3
3
3
-
P109
785
788
794
-
I/O
-
U19
VCCINT
VCCO
*
*
I/O
-
-
V21
4
-
Bank 4* Bank 4*
GND
I/O
-
GND*
R16
M14
GND*
VCCO
GND*
T18
GND
I/O
-
P93
GND*
M11
T11
-
GND*
Y15
-
3
3
-
-
797
800
-
4
4
4
4
-
P94
697
700
706
709
-
I/O
P110
W22
GND*
VCCO
I/O, VREF
I/O
P95
AB16
AB17
V15
GND
VCCO
-
-
-
3
-
Bank 3* Bank 3*
I/O
P96
N11
GND*
R12
-
I/O, VREF
I/O
3
3
3
3
3
-
P111
L14
M15
-
U21
T20
803
806
809
812
815
-
GND
I/O
-
GND*
Y16
P112
4
4
4
4
4
4
-
712
715
718
721
724
-
I/O
-
T19
I/O
-
-
AA17
W16
I/O
-
-
-
V22
I/O
-
I/O
L12
GND*
P16
-
T21
I/O
P97
P98
-
P11
T12
VCCO
AB18
AB19
VCCO
GND
I/O
-
GND*
R18
U22
R19
T22
I/O, VREF
VCCO
3
3
3
3
-
P113
-
818
821
827
830
-
Bank 4* Bank 4*
I/O
GND
I/O
-
-
GND*
T13
N12
-
GND*
Y17
-
I/O, VREF
I/O (D6)
GND
P114
P115
P116
L13
N16
GND*
4
4
4
P99
727
730
733
I/O
-
-
V16
GND*
I/O
AA18
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
95
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Spartan-II FPGA Family: Pinout Tables
XC2S200 Device Pinouts (Continued)
XC2S200 Device Pinouts (Continued)
XC2S200 Pad Name
XC2S200 Pad Name
Bndry
Scan
Bndry
Scan
Function
VCCO
Bank
PQ208
FG256
FG456
Function
I/O
Bank
PQ208
FG256
FG456
K18
J20
3
P117
VCCO
Bank 3* Bank 3*
VCCO
-
2
2
2
-
-
-
-
929
932
935
-
I/O
-
VCCINT
I/O (D5)
I/O
-
P118
VCCINT
M16
K14
-
*
VCCINT
R21
*
-
I/O
P140
G12
GND*
F16
-
J18
3
3
3
3
3
-
P119
833
836
839
842
845
-
GND
I/O
-
-
GND*
J22
P120
P18
2
2
2
2
2
-
938
941
944
947
950
-
I/O
-
R22
I/O
-
J19
I/O
-
-
P19
I/O
-
-
H21
H19
H20
I/O
-
L16
GND*
K13
-
P20
I/O
P141
P142
P143
P144
G13
F15
GND
I/O
-
P121
-
GND*
P21
I/O (D2)
VCCINT
VCCO
3
3
3
3
3
-
848
851
854
857
860
-
VCCINT
VCCO
Bank 2* Bank 2*
*
VCCINT
*
I/O
N19
2
VCCO
-
I/O
-
-
P22
I/O
P122
P123
P124
-
L15
K12
GND*
VCCO
N18
GND
I/O (D1)
I/O, VREF
I/O
-
P145
GND*
E16
F14
-
GND*
H22
H18
G21
G18
GND*
G20
G19
F22
-
I/O
N20
2
2
2
2
-
P146
953
956
962
965
-
GND
VCCO
GND*
VCCO
P147
3
-
-
Bank 3* Bank 3*
I/O
P148
D16
GND*
F12
-
I/O, VREF
I/O (D4)
I/O
3
3
3
3
3
3
-
P125
P126
-
K16
J16
-
N21
N22
863
866
872
875
878
881
-
GND
I/O
-
2
2
2
2
2
2
-
968
971
974
977
980
-
M17
I/O
-
I/O
-
J14
K15
-
M19
I/O
-
-
I/O
P127
-
M20
I/O
P149
P150
-
E15
F13
VCCO
F19
I/O
M18
I/O, VREF
VCCO
F21
VCCINT
I/O, TRDY(1)
VCCO
P128
P129
P130
VCCINT
J15
VCCO
*
VCCINT
M22
*
VCCO
3
3
890
-
Bank 2* Bank 2*
VCCO
GND
I/O
-
-
GND*
E14
C16
GND*
-
GND*
F20
-
Bank 3* Bank 3*
VCCO VCCO
Bank 2* Bank 2*
2
2
-
P151
983
986
-
VCCO
2
P130
-
I/O
-
F18
GND
I/O
-
GND*
E22
GND
I/O, IRDY(1)
I/O
-
P131
P132
P133
-
GND*
H16
H14
-
GND*
L20
-
2
2
2
-
-
989
995
998
-
2
2
2
2
2
2
2
2
2
893
896
902
905
908
911
917
920
-
I/O
-
-
E21
L17
I/O, VREF
GND
I/O
P152
E13
GND*
B16
-
D22
GND*
E20
I/O
L18
-
I/O
P134
-
H15
J13
-
L21
2
2
2
2
2
-
1001
1004
1007
1013
1016
I/O
L22
I/O
-
D21
C22
D20
C21
I/O
-
K19
K20
K21
VCCO
I/O
-
-
I/O (D3)
I/O, VREF
VCCO
P135
P136
-
G16
H13
VCCO
I/O (DIN, D0)
P153
P154
D14
C15
I/O (DOUT,
BUSY)
Bank 2* Bank 2*
CCLK
VCCO
2
2
P155
P156
D15
B22
1019
-
GND
I/O
-
P137
P138
P139
GND*
G14
GND*
K22
-
VCCO
Bank 2* Bank 2*
VCCO
2
2
923
926
I/O
G15
J21
DS001-4 (v2.8) June 13, 2008
Product Specification
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Module 4 of 4
96
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Spartan-II FPGA Family: Pinout Tables
XC2S200 Device Pinouts (Continued)
XC2S200 Device Pinouts (Continued)
XC2S200 Pad Name
XC2S200 Pad Name
Bndry
Scan
Bndry
Scan
Function
VCCO
Bank
PQ208
FG256
FG456
Function
I/O
Bank
PQ208
P175
P176
P177
-
FG256
D10
FG456
D13
1
P156
VCCO
Bank 1* Bank 1*
VCCO
-
1
1
-
90
93
-
I/O
A10
C13
TDO
GND
TDI
2
-
P157
B14
GND*
A15
B13
C13
-
A21
GND*
B20
-
-
GND
VCCO
GND*
VCCO
GND*
VCCO
P158
1
-
-
P159
-
Bank 1* Bank 1*
I/O (CS)
I/O (WRITE)
I/O
1
1
1
1
1
-
P160
C19
0
I/O, VREF
I/O
1
1
1
1
1
1
1
1
-
P178
P179
-
B9
E10
-
B13
E12
96
99
P161
A20
3
-
B19
9
I/O
A13
105
108
111
114
120
126
-
I/O
-
-
C18
D17
GND*
A19
12
15
-
I/O
-
A9
B12
I/O
-
C12
GND*
A14
-
I/O
P180
-
D9
D12
C12
D11
A11
GND
I/O, VREF
I/O
-
I/O
-
1
1
1
1
1
-
P162
18
21
27
30
33
-
I/O
P181
P182
P183
P184
A8
-
B18
I, GCK2
GND
VCCO
C9
I/O
-
-
E16
GND*
GND*
I/O
-
D12
B12
GND*
VCCO
C17
D16
1
VCCO
VCCO
-
Bank 1* Bank 1*
VCCO VCCO
Bank 0* Bank 0*
I/O
P163
VCCO
0
P184
-
GND
VCCO
-
-
GND*
1
VCCO
-
I, GCK3
VCCINT
I/O
0
-
P185
B8
VCCINT
-
C11
VCCINT
E11
127
-
Bank 1* Bank 1*
P186
*
*
I/O, VREF
I/O
1
1
1
1
1
-
P164
C11
A13
-
A18
B17
36
39
42
45
48
-
0
0
0
0
0
0
0
-
137
140
143
146
152
155
-
P165
I/O
P187
A7
A10
I/O
-
E15
I/O
-
D8
B10
I/O
-
-
A17
I/O
-
-
F11
I/O
-
D11
GND*
A12
-
D15
I/O
P188
P189
-
A6
C10
GND
I/O
-
GND*
C16
I/O, VREF
VCCO
B7
A9
1
1
1
1
-
P166
-
51
54
60
63
-
VCCO
Bank 0* Bank 0*
VCCO
I/O
D14
I/O, VREF
I/O
P167
P168
P169
P170
E11
B11
GND*
VCCO
E14
GND
I/O
-
P190
GND*
GND*
B9
-
A16
0
0
0
0
0
-
P191
C8
158
161
164
167
170
-
GND
VCCO
GND*
I/O
P192
D7
E10
C9
1
VCCO
-
I/O
-
-
Bank 1* Bank 1*
I/O
-
-
E7
D10
A8
VCCINT
I/O
-
P171
VCCINT
*
VCCINT
C15
B15
*
-
I/O
P193
1
1
1
1
1
-
P172
A11
66
69
72
75
78
-
GND
I/O
-
-
GND*
-
GND*
D9
I/O
P173
C10
0
0
0
0
0
-
173
176
179
182
185
-
I/O
-
-
E13
I/O
-
-
B8
I/O
-
-
A15
I/O
-
-
C8
I/O
-
-
F12
I/O
P194
P195
P196
P197
C7
E9
GND
I/O
-
GND*
GND*
C14
B14
I/O
B6
A7
1
1
1
P174
B10
81
84
87
VCCINT
VCCO
VCCINT
VCCO
Bank 0* Bank 0*
*
VCCINT
*
I/O
-
-
-
-
0
VCCO
-
I/O
A14
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
97
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Spartan-II FPGA Family: Pinout Tables
Additional XC2S200 Package Pins
XC2S200 Device Pinouts (Continued)
XC2S200 Pad Name
PQ208
Bndry
Scan
Function
GND
Bank
PQ208
FG256
GND*
A5
FG456
GND*
B7
Not Connected Pins
P55
P56
-
-
-
-
-
P198
-
11/02/00
I/O
0
0
0
0
-
P199
188
191
197
200
-
I/O, VREF
I/O
P200
C6
E8
FG256
-
-
D8
VCCINT Pins
I/O
P201
B5
C7
C3
M5
C14
M12
D4
N4
D13
N13
E5
P3
E12
P14
GND
I/O
-
GND*
D6
GND*
D7
0
0
0
0
0
0
-
203
206
209
212
215
-
V
V
V
V
V
V
V
V
CCO Bank 0 Pins
I/O
-
-
B6
E8
E9
H11
J11
L9
F8
F9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
-
-
A5
CCO Bank 1 Pins
I/O
P202
P203
-
A4
D6
-
-
I/O, VREF
VCCO
B4
C6
CCO Bank 2 Pins
VCCO
Bank 0* Bank 0*
VCCO
H12
J12
M9
M8
J6
-
-
CCO Bank 3 Pins
GND
I/O
-
-
GND*
E6
D5
-
GND*
B5
-
-
-
0
0
0
0
0
-
P204
218
221
224
230
233
-
CCO Bank 4 Pins
I/O
-
E7
-
-
I/O
-
A4
CCO Bank 5 Pins
I/O
-
-
E6
L8
-
-
I/O, VREF
GND
I/O
P205
A3
GND*
C5
-
B4
CCO Bank 6 Pins
-
GND*
A3
J5
-
-
0
0
0
0
-
-
236
239
242
248
-
CCO Bank 7 Pins
I/O
-
B3
H5
H6
-
-
I/O
-
-
D5
GND Pins
I/O
P206
P207
P208
B3
C4
VCCO
Bank 0* Bank 0*
VCCO VCCO
Bank 7* Bank 7*
C5
A1
F10
G10
J7
A16
F11
G11
J8
B2
G6
H7
J9
B15
G7
F6
G8
H9
K6
L6
F7
G9
H10
K7
TCK
VCCO
C4
0
VCCO
-
H8
J10
K11
R15
VCCO
7
P208
-
K8
K9
K10
R2
L7
04/18/01
L10
L11
T1
T16
Not Connected Pins
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx PCI
cores.
P4
R4
-
-
-
-
2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*,
VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*,
VCCO Bank 6*, VCCO Bank 7* are internally bonded to
independent ground or power planes within the package.
3. See "VCCO Banks" for details on VCCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
98
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Spartan-II FPGA Family: Pinout Tables
Additional XC2S200 Package Pins (Continued)
Additional XC2S200 Package Pins (Continued)
11/02/00
G6
H6
J6
K6
K7
L7
GND Pins
FG456
A1
J9
A22
J10
B2
B21
J12
C3
J13
K13
L13
M13
N13
P13
AB1
C20
J14
VCCINT Pins
J11
K11
L11
M11
N11
P11
AA2
E5
G9
J7
E18
G14
J16
T8
F6
G15
P7
F17
G16
P16
T14
V18
G7
H7
R7
T15
-
G8
H16
R16
T16
-
K9
L9
M9
N9
P9
Y3
K10
L10
M10
N10
P10
Y20
K12
L12
K14
L14
M12
N12
P12
AA21
M14
N14
P14
AB22
T7
U6
T9
U17
V5
V
V
V
V
V
V
V
V
CCO Bank 0 Pins
F9 F10
CCO Bank 1 Pins
F15 F16
CCO Bank 2 Pins
J17 K16
CCO Bank 3 Pins
N17 P17
CCO Bank 4 Pins
U13 U14
CCO Bank 5 Pins
U7 U8
CCO Bank 6 Pins
N7 P6
CCO Bank 7 Pins
F7
F13
G17
M16
T12
T10
M7
F8
G10
G12
K17
R17
U15
U9
G11
G13
L16
T17
U16
U10
T6
Not Connected Pins
A2
D1
A6
D4
A12
D18
L2
B11
D19
L19
B16
E17
M2
V6
C2
E19
M21
W4
AA11
-
F14
H17
N16
T13
T11
N6
G2
G22
R20
Y5
R3
U3
U18
AA1
AB21
W19
Y22
AB12
AA3
-
AA16
AB7
11/02/00
R6
Revision History
Version
No.
2.0
2.1
2.2
2.3
2.4
2.5
2.8
Date
Description
09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Corrected all known errors in the pinout tables.
10/04/00 Added notes requiring PWDN to be tied to VCCINT when unused.
11/02/00 Removed the Power Down feature.
03/05/01 Added notes on pinout tables for IRDY and TRDY.
04/30/01 Reinstated XC2S50 VCCO Bank 7, GND, and "not connected" pins missing in version 2.3.
09/03/03 Added caution about Not Connected Pins to XC2S30 pinout tables on page 76.
06/13/08 Added "Package Overview" section. Added notes to clarify shared VCCO banks. Updated description and links.
Updated all modules for continuous page, figure, and table numbering. Synchronized all modules to v2.8.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
99
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