XCV50-5HQ240I [XILINX]
Field Programmable Gate Arrays; 现场可编程门阵列
| 型号： | XCV50-5HQ240I |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Arrays |
| 文件： | 总4页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Virtex™ 2.5 V
Field Programmable Gate Arrays
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DS003-1 (v2.5 ) April 2, 2001
Product Specification
Features
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Fast, high-density Field-Programmable Gate Arrays
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Supported by FPGA Foundation™ and Alliance
Development Systems
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-
-
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Densities from 50k to 1M system gates
System performance up to 200 MHz
66-MHz PCI Compliant
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Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
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Wide selection of PC and workstation platforms
Hot-swappable for Compact PCI
SRAM-based in-system configuration
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Multi-standard SelectIO™ interfaces
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Unlimited re-programmability
Four programming modes
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16 high-performance interface standards
Connects directly to ZBTRAM devices
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0.22 m 5-layer metal process
100% factory tested
Built-in clock-management circuitry
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Four dedicated delay-locked loops (DLLs) for
advanced clock control
Description
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Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 m CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in Table 1.
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Hierarchical memory system
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LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Flexible architecture that balances speed and density
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Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
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IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
Table 1: Virtex Field-Programmable Gate Array Family Members
Maximum
Block RAM
Bits
Maximum
SelectRAM+™ Bits
Device
System Gates
CLB Array
Logic Cells
Available I/O
XCV50
57,906
16x24
1,728
180
180
260
284
316
404
512
512
512
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
24,576
38,400
55,296
75,264
98,304
153,600
221,184
301,056
393,216
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
108,904
20x30
2,700
164,674
24x36
3,888
236,666
28x42
5,292
322,970
32x48
6,912
468,252
40x60
10,800
15,552
21,168
27,648
661,111
48x72
888,439
56x84
1,124,022
64x96
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v2.5 ) April 2, 2001
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
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Virtex™ 2.5 V Field Programmable Gate Arrays
Xilinx thoroughly benchmarked the Virtex family. While per-
formance is design-dependent, many designs operated
internally at speeds in excess of 100 MHz and can achieve
200 MHz. Table 2 shows performance data for representa-
tive circuits, using worst-case timing parameters.
Virtex Architecture
Virtex devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex family to accommodate even the largest and most
complex designs.
Table 2: Performance for Common Circuit Functions
Function
Bits
Virtex -6
Register-to-Register
Virtex FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. In
some modes, the FPGA reads its own configuration data
from an external PROM (master serial mode). Otherwise,
the configuration data is written into the FPGA (Select-
MAP™, slave serial, and JTAG modes).
16
64
5.0 ns
7.2 ns
Adder
Pipelined Multiplier
8 x 8
5.1 ns
6.0 ns
16 x 16
The standard Xilinx Foundation™ and Alliance Series™
Development systems deliver complete design support for
Virtex, covering every aspect from behavioral and sche-
matic entry, through simulation, automatic design transla-
tion and implementation, to the creation, downloading, and
readback of a configuration bit stream.
Address Decoder
16
64
4.4 ns
6.4 ns
16:1 Multiplexer
Parity Tree
5.4 ns
9
4.1 ns
5.0 ns
6.9 ns
18
36
Higher Performance
Virtex devices provide better performance than previous
generations of FPGA. Designs can achieve synchronous
system clock rates up to 200 MHz including I/O. Virtex
inputs and outputs comply fully with PCI specifications, and
interfaces can be implemented that operate at 33 MHz or 66
MHz. Additionally, Virtex supports the hot-swapping
requirements of Compact PCI.
Chip-to-Chip
HSTL Class IV
200 MHz
180 MHz
LVTTL,16mA, fast slew
Module 1 of 4
2
www.xilinx.com
1-800-255-7778
DS003-1 (v2.5 ) April 2, 2001
Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays
Virtex Device/Package Combinations and Maximum I/O
Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
Package
CS144
TQ144
PQ240
HQ240
BG256
BG352
BG432
BG560
FG256
FG456
FG676
FG680
XCV50
94
XCV100
94
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800 XCV1000
98
98
166
166
166
166
166
166
166
166
316
180
176
180
176
180
260
180
260
260
316
316
404
316
404
404
404
512
176
260
176
284
312
404
444
512
444
512
Virtex Ordering Information
Example:
XCV300 -6 PQ 240 C
Device Type
Temperature Range
C = Commercial (TJ = 0 C to +85 C)
I = Industrial (TJ = –40 C to +100 C)
Speed Grade
-4
-5
-6
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine-pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
HQ = High Heat Dissipation QFP
TQ = Thin Quad Flat Pack
CS = Chip-scale Package
Figure 1: Virtex Ordering Information
DS003-1 (v2.5 ) April 2, 2001
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
3
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Virtex™ 2.5 V Field Programmable Gate Arrays
Revision History
Date
11/98
01/99
02/99
05/99
05/99
07/99
Version
1.0
Revision
Initial Xilinx release.
1.2
Updated package drawings and specs.
1.3
Update of package drawings, updated specifications.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
1.4
1.5
1.6
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99
1.7
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, “0” hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to
TOPHASE
.
01/00
01/00
03/00
1.8
1.9
2.0
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00
05/00
09/00
2.1
2.2
2.3
Modified “Pins not listed ...” statement. Speed grade update to Final status.
Modified Table 18.
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Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under IOB Input Switching Characteristics.
Added values to table under CLB SelectRAM Switching Characteristics.
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Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
10/00
04/01
2.4
2.5
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Corrected BG256 Pin Function Diagram.
Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Converted file to modularized format. See Virtex Data Sheet section.
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
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DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
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DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
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DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
Module 1 of 4
4
www.xilinx.com
1-800-255-7778
DS003-1 (v2.5 ) April 2, 2001
Product Specification
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