XCV600-4FGG680I [XILINX]
Field Programmable Gate Array, 3456 CLBs, 661111 Gates, 250MHz, CMOS, PBGA680, FBGA-680;型号: | XCV600-4FGG680I |
厂家: | XILINX, INC |
描述: | Field Programmable Gate Array, 3456 CLBs, 661111 Gates, 250MHz, CMOS, PBGA680, FBGA-680 栅 |
文件: | 总76页 (文件大小:739K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Product Obsolete/Under Obsolescence
0
R
Virtex™ 2.5 V
Field Programmable Gate Arrays
0
0
DS003-1 (v4.0) March 1, 2013
Product Specification
Features
•
Fast, high-density Field Programmable Gate Arrays
•
•
Supported by FPGA Foundation™ and Alliance
Development Systems
-
-
-
-
Densities from 50k to 1M system gates
System performance up to 200 MHz
66-MHz PCI Compliant
-
Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
-
Wide selection of PC and workstation platforms
Hot-swappable for Compact PCI
SRAM-based in-system configuration
•
•
Multi-standard SelectIO™ interfaces
-
-
Unlimited re-programmability
Four programming modes
-
-
16 high-performance interface standards
Connects directly to ZBTRAM devices
•
•
0.22 μm 5-layer metal process
100% factory tested
Built-in clock-management circuitry
-
Four dedicated delay-locked loops (DLLs) for
advanced clock control
Description
-
Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 μm CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in Table 1.
•
•
Hierarchical memory system
-
-
-
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Flexible architecture that balances speed and density
-
-
-
-
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
-
-
-
IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
Table 1: Virtex Field Programmable Gate Array Family Members
Maximum
Block RAM
Bits
Maximum
SelectRAM+™ Bits
Device
System Gates
CLB Array
Logic Cells
Available I/O
XCV50
57,906
16x24
1,728
180
180
260
284
316
404
512
512
512
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
24,576
38,400
55,296
75,264
98,304
153,600
221,184
301,056
393,216
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
108,904
20x30
2,700
164,674
24x36
3,888
236,666
28x42
5,292
322,970
32x48
6,912
468,252
40x60
10,800
15,552
21,168
27,648
661,111
48x72
888,439
56x84
1,124,022
64x96
© 2001-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v4.0) March 1, 2013
Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays
Xilinx thoroughly benchmarked the Virtex family. While per-
formance is design-dependent, many designs operated
internally at speeds in excess of 100 MHz and can achieve
200 MHz. Table 2 shows performance data for representa-
tive circuits, using worst-case timing parameters.
Virtex Architecture
Virtex devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex family to accommodate even the largest and most
complex designs.
Table 2: Performance for Common Circuit Functions
Function
Bits
Virtex -6
Register-to-Register
Virtex FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. In
some modes, the FPGA reads its own configuration data
from an external PROM (master serial mode). Otherwise,
the configuration data is written into the FPGA (Select-
MAP™, slave serial, and JTAG modes).
16
64
5.0 ns
7.2 ns
Adder
Pipelined Multiplier
8 x 8
5.1 ns
6.0 ns
16 x 16
The standard Xilinx Foundation™ and Alliance Series™
Development systems deliver complete design support for
Virtex, covering every aspect from behavioral and sche-
matic entry, through simulation, automatic design transla-
tion and implementation, to the creation, downloading, and
readback of a configuration bit stream.
Address Decoder
16
64
4.4 ns
6.4 ns
16:1 Multiplexer
Parity Tree
5.4 ns
9
4.1 ns
5.0 ns
6.9 ns
18
36
Higher Performance
Virtex devices provide better performance than previous
generations of FPGA. Designs can achieve synchronous
system clock rates up to 200 MHz including I/O. Virtex
inputs and outputs comply fully with PCI specifications, and
interfaces can be implemented that operate at 33 MHz or
66 MHz. Additionally, Virtex supports the hot-swapping
requirements of Compact PCI.
Chip-to-Chip
HSTL Class IV
200 MHz
180 MHz
LVTTL,16mA, fast slew
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Product Specification
Product Obsolete/Under Obsolescence
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Virtex™ 2.5 V Field Programmable Gate Arrays
Virtex Device/Package Combinations and Maximum I/O
Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
Package
CS144
TQ144
PQ240
HQ240
BG256
BG352
BG432
BG560
FG256
FG456
FG676
FG680
XCV50
94
XCV100
94
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800 XCV1000
98
98
166
166
166
166
166
166
166
166
316
180
176
180
176
180
260
180
260
260
316
316
404
316
404
404
404
512
176
260
176
284
312
404
444
512
444
512
Virtex Ordering Information
Example:
XCV300 -6 PQ 240 C
Device Type
Temperature Range
C = Commercial (T = 0°C to +85°C)
J
I = Industrial (T = –40°C to +100°C)
J
Speed Grade
-4
-5
-6
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine-pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
HQ = High Heat Dissipation QFP
TQ = Thin Quad Flat Pack
CS = Chip-scale Package
Figure 1: Virtex Ordering Information
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Virtex™ 2.5 V Field Programmable Gate Arrays
Revision History
Date
11/98
Version
1.0
Revision
Initial Xilinx release.
01/99-02/99
05/99
1.2-1.3
1.4
Both versions updated package drawings and specs.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
05/99
1.5
07/99
1.6
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99
1.7
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, “0” hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added T
parameter, changed T
to
IJITCC
OJIT
T
.
OPHASE
01/00
01/00
03/00
1.8
1.9
2.0
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for V
in CS144 package on p.43.
CCO
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00
05/00
09/00
2.1
2.2
2.3
Modified “Pins not listed...” statement. Speed grade update to Final status.
Modified Table 18.
•
Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under IOB Input Switching Characteristics.
Added values to table under CLB SelectRAM Switching Characteristics.
•
•
•
Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
10/00
2.4
•
•
•
Corrected BG256 Pin Function Diagram.
Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Converted file to modularized format. See Virtex Data Sheet section.
04/01
03/13
2.5
4.0
The products listed in this data sheet are obsolete. See XCN10016 for further information.
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
•
•
DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
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Virtex™ 2.5 V
Field Programmable Gate Arrays
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DS003-2 (v4.0) March 1, 2013
Product Specification
The output buffer and all of the IOB control signals have
independent polarity controls.
Architectural Description
Virtex Array
The Virtex user-programmable gate array, shown in
Figure 1, comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks
(IOBs).
DLL
IOBs
DLL
VersaRing
•
CLBs provide the functional elements for constructing
logic
•
IOBs provide the interface between the package pins
and the CLBs
CLBs
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
VersaRing
IOBs
DLL
DLL
The Virtex architecture also includes the following circuits
that connect to the GRM.
vao_b.eps
•
•
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Figure 1: Virtex Architecture Overview
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Two
forms of over-voltage protection are provided, one that per-
mits 5 V compliance, and one that does not. For 5 V compli-
ance, a Zener-like structure connected to ground turns on
when the output rises to approximately 6.5 V. When PCI
3.3 V compliance is required, a conventional clamp diode is
•
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
connected to the output supply voltage, V
.
CCO
Input/Output Block
The Virtex IOB, Figure 2, features SelectIO™ inputs and
outputs that support a wide variety of I/O signalling stan-
dards, see Table 1.
Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each pad. Prior to con-
figuration, all pins not involved in configuration are forced
into their high-impedance state. The pull-down resistors and
the weak-keeper circuits are inactive, but inputs can option-
ally be pulled up.
The three IOB storage elements function either as edge-trig-
gered D-type flip-flops or as level sensitive latches. Each
IOB has a clock signal (CLK) shared by the three flip-flops
and independent clock enable signals for each flip-flop.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins will float.
Consequently, external pull-up or pull-down resistors must
be provided on pins required to be at a well-defined logic
level prior to configuration.
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
All Virtex IOBs support IEEE 1149.1-compatible boundary
scan testing.
© 1999-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-2 (v4.0) March 1, 2013
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Virtex™ 2.5 V Field Programmable Gate Arrays
R
Q
D
CE
T
TCE
Weak
Keeper
SR
PAD
O
Q
D
CE
OBUFT
OCE
SR
I
Programmable
Delay
IQ
Q
D
CE
IBUF
Vref
SR
SR
CLK
ICE
ds022_02_091300
Figure 2: Virtex Input/Output Block (IOB)
Table 1: Supported Select I/O Standards
Input Reference
Output Source
Board Termination
I/O Standard
Voltage (V
)
Voltage (V
)
Voltage (V
)
5 V Tolerant
REF
CCO
TT
LVTTL 2 – 24 mA
N/A
3.3
N/A
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
LVCMOS2
PCI, 5 V
N/A
2.5
N/A
N/A
3.3
N/A
PCI, 3.3 V
GTL
N/A
3.3
N/A
0.8
N/A
N/A
1.5
1.2
GTL+
1.0
1.5
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 Class I &II
SSTL2 Class I & II
CTT
0.75
0.9
0.75
1.5
1.5
0.9
1.5
1.5
1.5
3.3
1.5
1.25
1.5
2.5
1.25
1.5
3.3
AGP
1.32
3.3
N/A
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Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in Figure 3. Each bank has
Input Path
A buffer In the Virtex IOB input path routes the input signal
either directly to internal logic or through an optional input
flip-flop.
multiple V
pins, all of which must be connected to the
CCO
same voltage. This voltage is determined by the output
standards in use.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Bank 0
Bank 1
GCLK3 GCLK2
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
Virtex
Device
threshold voltage, V . The need to supply V
imposes
REF
REF
constraints on which standards can used in close proximity
to each other. See I/O Banking, page 3.
GCLK1 GCLK0
There are optional pull-up and pull-down resistors at each
user I/O input for use after configuration. Their value is in
the range 50 kΩ – 100 kΩ.
Bank 5
Bank 4
X8778_b
Output Path
Figure 3: Virtex I/O Banks
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
Within a bank, output standards can be mixed only if they
. Compatible standards are shown in
Table 2. GTL and GTL+ appear under all voltages because
use the same V
CCO
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
their open-drain outputs do not depend on V
.
CCO
Table 2: Compatible Output Standards
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48mA. Drive
strength and slew rate controls minimize bus transients.
V
Compatible Standards
CCO
3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+
2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+
In most signalling standards, the output High voltage
depends on an externally supplied V
voltage. The need
CCO
to supply V
imposes constraints on which standards
CCO
can be used in close proximity to each other. See I/O Bank-
ing, page 3.
Some input standards require a user-supplied threshold
voltage, V . In this case, certain user-I/O pins are auto-
REF
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
matically configured as inputs for the V
imately one in six of the I/O pins in the bank assume this
role.
voltage. Approx-
REF
The V
pins within a bank are interconnected internally
REF
and consequently only one V
voltage can be used within
REF
each bank. All V
pins in the bank, however, must be con-
REF
nected to the external voltage source for correct operation.
Because the weak-keeper circuit uses the IOB input buffer
Within a bank, inputs that require V can be mixed with
REF
to monitor the input level, an appropriate V
voltage must
REF
those that do not. However, only one V
used within a bank. Input buffers that use V
tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V
tolerant.
voltage can be
REF
be provided if the signalling standard requires one. The pro-
vision of this voltage must comply with the I/O banking
rules.
are not 5 V
REF
I/O Banking
The V
and V
pins for each bank appear in the device
REF
CCO
Some of the I/O standards described above require V
Pinout tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
CCO
and/or V
voltages. These voltages externally and con-
REF
nected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Within a given package, the number of V
can vary depending on the size of device. In larger devices,
and V
pins
CCO
REF
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Virtex™ 2.5 V Field Programmable Gate Arrays
R
more I/O pins convert to V
pins. Since these are always
of five or six inputs. Consequently, when estimating the
number of system gates provided by a given device, each
CLB counts as 4.5 LCs.
REF
a superset of the V
pins used for smaller devices, it is
REF
possible to design a PCB that permits migration to a larger
device if necessary. All the V pins for the largest device
anticipated must be connected to the V
used for I/O.
REF
Look-Up Tables
voltage, and not
REF
Virtex function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16x1-bit dual-port synchronous RAM.
In smaller devices, some V
do not connect within the package. These unconnected pins
can be left unconnected externally, or can be connected to
pins used in larger devices
CCO
the V
voltage to permit migration to a larger device if
CCO
necessary.
The Virtex LUT can also provide a 16-bit shift register that is
ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such as
Digital Signal Processing.
In TQ144 and PQ/HQ240 packages, all V
pins are
CCO
bonded together internally, and consequently the same
voltage must be connected to all of them. In the
V
CCO
CS144 package, bank pairs that share a side are intercon-
nected internally, permitting four choices for V . In both
Storage Elements
CCO
cases, the V
pins remain internally connected as eight
REF
The storage elements in the Virtex slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D inputs can be driven either by the func-
tion generators within the slice or directly from slice inputs,
bypassing the function generators.
banks, and can be used as described previously.
Configurable Logic Block
The basic building block of the Virtex CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex CLB contains four LCs,
organized in two similar slices, as shown in Figure 4.
In addition to Clock and Clock Enable signals, each Slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals can be configured to oper-
ate asynchronously. All of the control signals are indepen-
dently invertible, and are shared by the two flip-flops within
the slice.
Figure 5 shows a more detailed view of a single slice.
In addition to the four basic LCs, the Virtex CLB contains
logic that combines function generators to provide functions
COUT
COUT
YB
Y
YB
Y
G4
G3
G2
G4
SP
Q
EC
SP
Q
EC
G3
G2
G1
Carry &
Control
Carry &
Control
LUT
LUT
D
YQ
D
YQ
G1
RC
RC
BY
F4
BY
XB
X
XB
X
F4
F3
F2
F1
SP
SP
Q
F3
F2
LUT
LUT
Carry &
Control
Carry &
Control
D
Q
D
XQ
XQ
EC
EC
F1
RC
Slice 0
RC
Slice 1
BX
BX
slice_c.eps
CIN
CIN
Figure 4: 2-Slice Virtex CLB
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Virtex™ 2.5 V Field Programmable Gate Arrays
COUT
YB
Y
CY
G4
G3
G2
G1
I3
I2
I1
I0
O
LUT
INIT
D
Q
YQ
DI
WE
EC
0
1
REV
BY
XB
F5IN
F6
CY
F5
X
F5
BY DG
CK
WE
A4
WSO
WSH
BX
DI
INIT
D
EC
Q
XQ
BX
DI
WE
I3
I2
I1
I0
F4
F3
F2
F1
REV
O
LUT
0
1
SR
CLK
CE
CIN
viewslc4.eps
Figure 5: Detailed View of Virtex Slice
Additional Logic
Block SelectRAM
The F5 multiplexer in each slice combines the function gen-
erator outputs. This combination provides either a function
generator that can implement any 5-input function, a 4:1
multiplexer, or selected functions of up to nine inputs.
Virtex FPGAs incorporate several large block SelectRAM
memories. These complement the distributed LUT
SelectRAMs that provide shallow RAM structures imple-
mented in CLBs.
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
Block SelectRAM memory blocks are organized in columns.
All Virtex devices contain two such columns, one along
each vertical edge. These columns extend the full height of
the chip. Each memory block is four CLBs high, and conse-
quently, a Virtex device 64 CLBs high contains 16 memory
blocks per column, and a total of 32 blocks.
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Table 3 shows the amount of block SelectRAM memory that
is available in each Virtex device.
Arithmetic Logic
Table 3: Virtex Block SelectRAM Amounts
Dedicated carry logic provides fast arithmetic carry capabil-
ity for high-speed arithmetic functions. The Virtex CLB sup-
ports two separate carry chains, one per Slice. The height
of the carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation.
Device
XCV50
# of Blocks
Total Block SelectRAM Bits
8
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
10
12
14
16
20
24
28
32
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
BUFTs
Each Virtex CLB contains two 3-state drivers (BUFTs) that
can drive on-chip busses. See Dedicated Routing, page 7.
Each Virtex BUFT has an independent 3-state control pin
and an independent input pin.
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Each block SelectRAM cell, as illustrated in Figure 6, is a
fully synchronous dual-ported 4096-bit RAM with indepen-
dent control signals for each port. The data widths of the
two ports can be configured independently, providing
built-in bus-width conversion.
Table 4: Block SelectRAM Port Aspect Ratios
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
1
2
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
4
RAMB4_S#_S#
8
WEA
ENA
RSTA
16
256
DOA[#:0]
CLKA
ADDRA[#:0]
DIA[#:0]
The Virtex block SelectRAM also includes dedicated routing
to provide an efficient interface with both CLBs and other
block SelectRAMs. Refer to XAPP130 for block SelectRAM
timing waveforms.
WEB
ENB
RSTB
CLKB
DOB[#:0]
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex routing archi-
tecture and its place-and-route software were defined in a
single optimization process. This joint optimization mini-
mizes long-path delays, and consequently, yields the best
system performance.
ADDRB[#:0]
DIB[#:0]
xcv_ds_006
Figure 6: Dual-Port Block SelectRAM
Table 4 shows the depth and width aspect ratios for the
block SelectRAM.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
To Adjacent
GRM
To Adjacent
To Adjacent
GRM
GRM
GRM
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
Direct Connection
To Adjacent
CLB
CLB
X8794b
Figure 7: Virtex Local Routing
•
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM.
Local Routing
The VersaBlock provides local routing resources, as shown
in Figure 7, providing the following three types of connec-
tions.
•
•
Interconnections among the LUTs, flip-flops, and GRM
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•
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
General Purpose Routing
Most Virtex signals are routed on the general purpose rout-
ing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. The general routing resources are located in horizon-
tal and vertical routing channels associated with the rows
and columns CLBs. The general-purpose routing resources
are listed below.
I/O Routing
Virtex devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the VersaRing,
facilitates pin-swapping and pin-locking, such that logic
redesigns can adapt to existing PCB layouts. Time-to-mar-
ket is reduced, since PCBs and other system components
can be manufactured while the logic design is still in prog-
ress.
•
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
•
•
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
Dedicated Routing
12 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
can be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of
the Hex lines are bidirectional, while the remaining
ones are uni-directional.
Some classes of signal require dedicated routing resources
to maximize performance. In the Virtex architecture, dedi-
cated routing resources are provided for two classes of sig-
nal.
•
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in Figure 8.
•
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
Tri-State
Lines
CLB
CLB
CLB
CLB
buft_c.eps
Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines
•
The secondary local clock routing resources consist of
Global Routing
24 backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
Global Routing resources distribute clocks and other sig-
nals with very high fanout throughout the device. Virtex
devices include two tiers of global routing resources
referred to as primary global and secondary local clock rout-
ing resources.
•
The primary global routing resources are four
Clock Distribution
dedicated global nets with dedicated input pins that are
designed to distribute high-fanout clock signals with
minimal skew. Each global clock net can drive all CLB,
IOB, and block RAM clock pins. The primary global
nets can only be driven by global buffers. There are
four global buffers, one for each global net.
Virtex provides high-speed, low-skew clock distribution
through the primary global routing resources described
above. A typical clock distribution net is shown in Figure 9.
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
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Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the gen-
eral purpose routing.
GCLKPAD2
GCLKPAD3
GCLKBUF2
Global Clock Column
Global Clock Rows
GCLKBUF3
Global Clock Spine
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
gclkbu_2.eps
Figure 9: Global Clock Distribution Network
Delay-Locked Loop (DLL)
Boundary Scan
Associated with each global clock input buffer is a fully digi-
tal Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
networks.The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element.
Clock edges reach internal flip-flops one to four clock peri-
ods after they arrive at the input. This closed-loop system
effectively eliminates clock-distribution delay by ensuring
that clock edges arrive at internal flip-flops in synchronism
with clock edges arriving at the input.
Virtex devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that implement
the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions. The TAP
also supports two internal scan chains and configura-
tion/readback of the device.The TAP uses dedicated package
pins that always operate using LVTTL. For TDO to operate
using LVTTL, the V
for Bank 2 should be 3.3 V. Other-
CCO
wise, TDO switches rail-to-rail between ground and V
.
CCO
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including un-bonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections, provided the user
design or application is turned off.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16.
The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to de-skew a board level clock among multiple Vir-
tex devices.
Table 5 lists the boundary-scan instructions supported in
Virtex FPGAs. Internal signals can be captured during
EXTEST by connecting them to un-bonded or unused IOBs.
They can also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
In order to guarantee that the system clock is operating cor-
rectly prior to the FPGA starting up after configuration, the
DLL can delay the completion of the configuration process
until after it has achieved lock.
Before the device is configured, all instructions except
USER1 and USER2 are available. After configuration, all
instructions are available. During configuration, it is recom-
mended that those operations using the boundary-scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.
See DLL Timing Parameters, page 21 of Module 3, for fre-
quency range information.
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In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
The FPGA supports up to two additional internal scan
chains that can be specified using the BSCAN macro. The
macro provides two user pins (SEL1 and SEL2) which are
decodes of the USER1 and USER2 instructions respec-
tively. For these instructions, two corresponding pins (TDO1
and TDO2) allow user scan data to be shifted out of TDO.
Figure 10 is a diagram of the Virtex Series boundary scan
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction
Register with decodes.
Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
(TDI) and shared output pins that represent the state of the
TAP controller (RESET, SHIFT, and UPDATE).
Instruction Set
The Virtex Series boundary scan instruction set also
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The
complete instruction set is coded as shown in Table 5.
Bit Sequence
The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out, and 3-State Control. Non-IOB pins have
appropriate partial bit population if input-only or output-only.
Each EXTEST CAPTURED-OR state captures all In, Out,
and 3-state pins.
From a cavity-up view of the chip (as shown in EPIC), start-
ing in the upper right chip corner, the boundary scan
data-register bits are ordered as shown in Figure 11.
BSDL (Boundary Scan Description Language) files for Vir-
tex Series devices are available on the Xilinx web site in the
File Download area.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
DATA IN
IOB.T
0
1
0
sd
1
D
Q
D
Q
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
sd
1
0
D
Q
D
Q
LE
1
0
IOB.I
1
sd
D
Q
D
Q
0
LE
1
0
IOB.Q
IOB.T
BYPASS
REGISTER
0
1
M
U
X
TDO
1
sd
INSTRUCTION REGISTER
TDI
D
Q
D
Q
0
LE
1
sd
D
Q
D
Q
0
LE
1
0
IOB.I
DATAOUT
SHIFT/
CAPTURE
UPDATE
EXTEST
CLOCK DATA
REGISTER
X9016
Figure 10: Virtex Series Boundary Scan Logic
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Identification Registers
Right half of Top-edge IOBs (Right-to-Left)
Bit 0 ( TDO end)
Bit 1
Bit 2
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
GCLK2
GCLK3
Left half of Top-edge IOBs (Right-to-Left)
Left-edge IOBs (Top-to-Bottom)
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
M1
M0
M2
v = the die version number
Left half of Bottom-edge IOBs (Left-to-Right)
f = the family code (03h for Virtex family)
GCLK1
GCLK0
a = the number of CLB rows (ranges from 010h for XCV50
to 040h for XCV1000)
Right half of Bottom-edge IOBs (Left-to-Right)
DONE
PROG
c = the company code (49h for Xilinx)
The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code is embedded in the bitstream during bitstream gener-
ation and is valid only after configuration.
Right-edge IOBs (Bottom -to-Top)
(TDI end)
CCLK
990602001
Figure 11: Boundary Scan Bit Sequence
Table 6: IDCODEs Assigned to Virtex FPGAs
Table 5: Boundary Scan Instructions
FPGA
XCV50
IDCODE
v0610093h
v0614093h
v0618093h
v061C093h
v0620093h
v0628093h
v0630093h
v0638093h
v0640093h
Boundary-Scan
Command
Binary
Code(4:0)
Description
EXTEST
00000
00001
Enables boundary-scan
EXTEST operation
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
SAMPLE/PRELOAD
Enables boundary-scan
SAMPLE/PRELOAD
operation
USER 1
USER 2
00010
00011
00100
00101
00111
01000
01001
01010
Access user-defined
register 1
Access user-defined
register 2
CFG_OUT
CFG_IN
Access the configuration
bus for read operations.
Access the configuration
bus for write operations.
Including Boundary Scan in a Design
Since the boundary scan pins are dedicated, no special ele-
ment needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
INTEST
Enables boundary-scan
INTEST operation
USERCODE
IDCODE
HIGHZ
Enables shifting out
USER code
If an internal data register is used, insert the boundary scan
symbol and connect the necessary pins as appropriate.
Enables shifting out of ID
Code
Development System
3-statesoutputpinswhile
enabling the Bypass
Register
Virtex FPGAs are supported by the Xilinx Foundation and
Alliance CAE tools. The basic methodology for Virtex
design consists of three interrelated steps: design entry,
implementation, and verification. Industry-standard tools
are used for design entry and simulation (for example, Syn-
opsys FPGA Express), while Xilinx provides proprietary
architecture-specific tools for implementation.
JSTART
01100
Clock the start-up
sequence when
StartupClk is TCK
BYPASS
11111
Enables BYPASS
The Xilinx development system is integrated under the
Xilinx Design Manager (XDM™) software, providing design-
RESERVED
All other
codes
Xilinx reserved
instructions
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Virtex™ 2.5 V Field Programmable Gate Arrays
ers with a common user interface regardless of their choice
of entry and verification tools. The XDM software simplifies
the selection of implementation options with pull-down
menus and on-line help.
design, thus allowing the most convenient entry method to
be used for each portion of the design.
Design Implementation
The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The parti-
tioner takes the EDIF net list for the design and maps the
logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best locations for these blocks based on their interconnec-
tions and the desired performance. Finally, the router inter-
connects the blocks.
Application programs ranging from schematic capture to
Placement and Routing (PAR) can be accessed through the
XDM software. The program command sequence is gener-
ated prior to execution, and stored for documentation.
Several advanced software features facilitate Virtex design.
RPMs, for example, are schematic-based macros with rela-
tive location constraints to guide their placement. They help
ensure optimal implementation of common functions.
The PAR algorithms support fully automatic implementation
of most designs. For demanding applications, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floor planning.
For HDL design entry, the Xilinx FPGA Foundation develop-
ment system provides interfaces to the following synthesis
design environments.
•
•
•
Synopsys (FPGA Compiler, FPGA Express)
Exemplar (Spectrum)
Synplicity (Synplify)
®
The implementation software incorporates Timing Wizard
For schematic design entry, the Xilinx FPGA Foundation
and alliance development system provides interfaces to the
following schematic-capture design environments.
timing-driven placement and routing. Designers specify tim-
ing requirements along entire paths during design entry.
The timing path analysis routines in PAR then recognize
these user-specified requirements and accommodate them.
•
•
Mentor Graphics V8 (Design Architect, QuickSim II)
Viewlogic Systems (Viewdraw)
Timing requirements are entered on a schematic in a form
directly relating to the system requirements, such as the tar-
geted clock frequency, or the maximum allowable delay
between two registers. In this way, the overall performance
of the system along entire signal paths is automatically tai-
lored to user-generated specifications. Specific timing infor-
mation for individual nets is unnecessary.
Third-party vendors support many other environments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Virtex FPGAs supported by a unified library of standard
functions. This library contains over 400 primitives and mac-
ros, ranging from 2-input AND gates to 16-bit accumulators,
and includes arithmetic functions, comparators, counters,
data registers, decoders, encoders, I/O functions, latches,
Boolean functions, multiplexers, shift registers, and barrel
shifters.
Design Verification
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be veri-
fied in real time without the need for extensive sets of soft-
ware simulation vectors.
The “soft macro” portion of the library contains detailed
descriptions of common logic functions, but does not con-
tain any partitioning or placement information. The perfor-
mance of these macros depends, therefore, on the
partitioning and placement obtained during implementation.
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the net list for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
RPMs, on the other hand, do contain predetermined parti-
tioning and placement information that permits optimal
implementation of these functions. Users can create their
own library of soft macros or RPMs based on the macros
and primitives in the standard library.
®
TRACE static timing analyzer.
For in-circuit debugging, the development system includes
a download and readback cable. This cable connects the
FPGA in the target system to a PC or workstation. After
downloading the design into the FPGA, the designer can
single-step the logic, readback the contents of the flip-flops,
and so observe the internal logic state. Simple modifica-
tions can be downloaded into the system in a matter of min-
utes.
The design environment supports hierarchical design entry,
with high-level schematics that comprise major functional
blocks, while lower-level schematics define the logic in
these blocks. These hierarchical design elements are auto-
matically combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
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After Virtex devices are configured, unused IOBs function
as 3-state OBUFTs with weak pull downs. For a more
detailed description than that given below, see the
XAPP138, Virtex Configuration and Readback.
Configuration
Virtex devices are configured by loading configuration data
into the internal configuration memory. Some of the pins
used for this are dedicated configuration pins, while others
can be re-used as general purpose inputs and outputs once
configuration is complete.
Configuration Modes
Virtex supports the following four configuration modes.
The following are dedicated pins:
•
•
•
•
Slave-serial mode
Master-serial mode
SelectMAP mode
Boundary-scan mode
•
•
•
•
•
Mode pins (M2, M1, M0)
Configuration clock pin (CCLK)
PROGRAM pin
DONE pin
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
configuration. The selection codes are listed in Table 7.
Boundary-scan pins (TDI, TDO, TMS, TCK)
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or it can be generated
externally and provided to the FPGA as an input. The
PROGRAM pin must be pulled High prior to reconfiguration.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected. However, it is recom-
mended to drive the configuration mode pins externally.
Note that some configuration pins can act as outputs. For
correct operation, these pins can require a V
permit LVTTL operation. All the pins affected are in banks 2
or 3. The configuration pins needed for SelectMap (CS,
Write) are located in bank 1.
of 3.3 V to
CCO
Table 7: Configuration Codes
Configuration Mode
Master-serial mode
Boundary-scan mode
SelectMAP mode
M2 M1 M0 CCLK Direction Data Width Serial D
Configuration Pull-ups
out
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Out
N/A
In
1
1
8
1
1
1
8
1
Yes
No
No
No
No
No
Slave-serial mode
Master-serial mode
Boundary-scan mode
SelectMAP mode
In
Yes
Yes
No
No
Out
N/A
In
Yes
Yes
Yes
Yes
No
Slave-serial mode
In
Yes
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex-only chains.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be setup
at the DIN input pin a short time before each rising edge of
an externally generated CCLK.
Figure 12 shows a full master/slave system. A Virtex device
in slave-serial mode should be connected as shown in the
third device from the left.
Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
pins makes slave-serial the default mode if the pins are left
unconnected. However, it is recommended to drive the con-
figuration mode pins externally. Figure 13 shows
slave-serial mode programming switching characteristics.
For more information on serial PROMs, see the PROM data
sheet at:
http://www.xilinx.com/bvdocs/publications/ds026.pdf.
Multiple FPGAs can be daisy-chained for configuration from a
single source. After a particular FPGA has been configured,
the data for the next device is routed to the DOUT pin. The
data on the DOUT pin changes on the rising edge of CCLK.
Table 8 provides more detail about the characteristics
shown in Figure 13. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.
The change of DOUT on the rising edge of CCLK differs
from previous families, but does not cause a problem for
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Virtex™ 2.5 V Field Programmable Gate Arrays
Table 8: Master/Slave Serial Mode Programming Switching
Figure
Description
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
References
Symbol
T /TCCD
DCC
Values
5.0 / 0
5.0 / 0
12.0
5.0
Units
ns, min
ns, min
ns, max
ns, min
ns, min
MHz, max
1/2
1/2
3
T
/T
DSCK CKDS
T
T
CCO
CCH
High time
4
CCLK
Low time
5
T
5.0
CCL
Maximum Frequency
F
66
CC
Frequency Tolerance, master mode with
respect to nominal
+45%
–30%
V
3.3V
CC
330 Ω
M0 M1
M2
M0 M1
M2
DOUT
DOUT
DIN
CCLK
VIRTEX
MASTER
SERIAL
CCLK
XC1701L
VIRTEX,
XC4000XL,
SLAVE
CLK
DATA
DIN
Optional Pull-up
Resistor on Done
1
PROGRAM
DONE
CEO
CE
PROGRAM
DONE
INIT
INIT
RESET/OE
(Low Reset Option Used)
PROGRAM
Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor
of 330 Ω should be added to the common DONE line. (For Spartan-XL devices, add a 4.7K Ω
pull-up resistor.) This pull-up is not needed if the DriveDONE attribute is set. If used,
DriveDONE should be selected only for the last device in the configuration chain.
xcv_12_050103
Figure 12: Master/Slave Serial Mode Circuit Diagram
DIN
1
2
5
T
T
DCC
T
CCD
CCL
CCLK
4
T
CCH
3
T
CCO
DOUT
(Output)
X5379_a
Figure 13: Slave-Serial Mode Programming Switching Characteristics
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daisy-chained FPGAs are fast enough to support the clock
rate.
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.
On power-up, the CCLK frequency is 2.5 MHz. This fre-
quency is used until the ConfigRate bits have been loaded
when the frequency changes to the selected ConfigRate.
Unless a different frequency is specified in the design, the
default ConfigRate is 4 MHz.
Figure 12 shows a full master/slave system. In this system,
the left-most device operates in master-serial mode. The
remaining devices operate in slave-serial mode. The
SPROM RESET pin is driven by INIT, and the CE input is
driven by DONE. There is the potential for contention on the
DONE pin, depending on the start-up sequence options
chosen.
The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.
Figure 14 shows the timing of master-serial configuration.
Master-serial mode is selected by a <000> or <100> on the
mode pins (M2, M1, M0). Table 8 shows the timing informa-
tion for Figure 14.
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
CCLK
(Output)
T
2
CKDS
T
1
DSCK
Serial Data In
Serial DOUT
(Output)
DS022_44_071201
Figure 14: Master-Serial Mode Programming Switching Characteristics
must rise from 1.0 V to V min in less
At power-up, V
In the SelectMAP mode, multiple Virtex devices can be
chained in parallel. DATA pins (D7:D0), CCLK, WRITE,
BUSY, PROGRAM, DONE, and INIT can be connected in
parallel between all the FPGAs. Note that the data is orga-
nized with the MSB of each byte on pin DO and the LSB of
each byte on D7. The CS pins are kept separate, insuring
that each FPGA can be selected individually. WRITE should
be Low before loading the first bitstream and returned High
after the last device has been programmed. Use CS to
select the appropriate FPGA for loading the bitstream and
sending the configuration data. at the end of the bitstream,
deselect the loaded device and select the next target FPGA
by setting its CS pin High. A free-running oscillator or other
externally generated signal can be used for CCLK. The
BUSY signal can be ignored for frequencies below 50 MHz.
For details about frequencies above 50 MHz, see
XAPP138, Virtex Configuration and Readback. Once all the
devices have been programmed, the DONE pin goes High.
CC
CC
than 50 ms, otherwise delay configuration by pulling
PROGRAM Low until V is valid.
CC
The sequence of operations necessary to configure a Virtex
FPGA serially appears in Figure 15.
SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the FPGA with a BUSY flag
controlling the flow of data.
An external data source provides a byte stream, CCLK, a
Chip Select (CS) signal and a Write signal (WRITE). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low.
Data can also be read using the SelectMAP mode. If
WRITE is not asserted, configuration data is read out of the
FPGA as part of a readback operation.
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Apply Power
Set PROGRAM = High
Release INIT
FPGA starts to clear
configuration memory.
FPGA makes a final
clearing pass and releases
INIT when finished.
If used to delay
configuration
Low
INIT?
High
Load a Configuration Bit
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
No
End of
Bitstream?
If no CRC errors found,
FPGA enters start-up phase
causing DONE to go High.
Yes
Configuration Completed
ds003_154_111799
Figure 15: Serial Configuration Flowchart
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback.
Multiple Virtex FPGAs can be configured using the Select-
MAP mode, and be made to start-up simultaneously. To
configure multiple devices in this way, wire the individual
CCLK, Data, WRITE, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
asserting the CS pin of each device in turn and writing the
appropriate data. See Table 9 for SelectMAP Write Timing
Retention of the SelectMAP port is selectable on a
design-by-design basis when the bitstream is generated. If
retention is selected, PROHIBIT constraints are required to
prevent the SelectMAP-port pins from being used as user
I/O.
Characteristics.
.
Table 9: SelectMAP Write Timing Characteristics
Description
Symbol
/T
SMDCC SMCCD
Units
ns, min
D
Setup/Hold
1/2
3/4
5/6
7
T
5.0 / 1.7
7.0 / 1.7
7.0 / 1.7
12.0
0-7
CS Setup/Hold
T
/T
ns, min
SMCSCC SMCCCS
WRITE Setup/Hold
T
/T
ns, min
SMCCW SMWCC
CCLK
BUSY Propagation Delay
Maximum Frequency
T
ns, max
MHz, max
MHz, max
SMCKBY
F
66
CC
Maximum Frequency with no handshake
F
50
CCNH
1. Assert WRITE and CS Low. Note that when CS is
asserted on successive CCLKs, WRITE must remain
either asserted or de-asserted. Otherwise an abort will
be initiated, as described below.
Write
Write operations send packets of configuration data into the
FPGA. The sequence of operations for a multi-cycle write
operation is shown below. Note that a configuration packet
can be split into many such sequences. The packet does
not have to complete within one assertion of CS, illustrated
in Figure 16.
2. Drive data onto D[7:0]. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
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3. At the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this has happened.
5. De-assert CS and WRITE.
A flowchart for the write operation appears in Figure 17.
Note that if CCLK is slower than f , the FPGA never
asserts BUSY. In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
CCNH
4. Repeat steps 2 and 3 until all the data has been sent.
CCLK
3
4
6
CS
5
WRITE
1
2
DATA[0:7]
7
BUSY
Write
Write
No Write
Write
ds003_16_071902
Figure 16: Write Operations
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Apply Power
FPGA starts to clear
configuration memory.
PROGRAM
from Low
to High
No
FPGA makes a final
clearing pass and releases
INIT when finished.
Yes
If used to delay
configuration
Release INIT
Low
INIT?
High
Set WRITE = Low
Enter Data Source
Sequence A
On first FPGA
Set CS = Low
Apply Configuration Byte
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
High
Busy?
Low
No
End of Data?
Yes
If no errors,
first FPGAs enter start-up phase
releasing DONE.
On first FPGA
Set CS = High
If no errors,
later FPGAs enter start-up phase
releasing DONE.
For any other FPGAs
Repeat Sequence A
Disable Data Source
Set WRITE = High
When all DONE pins
are released, DONE goes High
and start-up sequences complete.
Configuration Completed
ds003_17_090602
Figure 17: SelectMAP Flowchart for Write Operation
ies, and the FPGA requires a new synchronization word
Abort
prior to accepting any new packets.
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
rent packet command to be aborted. The device will remain
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word boundar-
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in Figure 18.
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The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is sig-
nalled by DONE going High.
CCLK
The power-up timing of configuration signals is shown in
Figure 19. The corresponding timing characteristics are
listed in Table 10.
CS
WRITE
V
TPOR
CC
DATA[0:7]
PROGRAM
INIT
BUSY
TPI
Abort
X8797_c
T
ICCK
CCLK OUTPUT or INPUT
M0, M1, M2
(Required)
Figure 18: SelectMAP Write Abort Waveforms
VALID
98122302
Boundary-Scan Mode
Figure 19: Power-Up Timing Configuration Signals
Table 10: Power-up Timing Characteristics
In the boundary-scan mode, configuration is done through
the IEEE 1149.1 Test Access Port. Note that the
PROGRAM pin must be pulled High prior to reconfiguration.
A Low on the PROGRAM pin resets the TAP controller and
no JTAG operations can be performed.
Description
Power-on Reset
Symbol
Value
2.0
Units
ms, max
μs, max
μs, min
μs, max
ns, min
T
POR
Configuration through the TAP uses the CFG_IN instruc-
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus.
Program Latency
CCLK (output) Delay
T
100.0
0.5
PL
T
ICCK
The following steps are required to configure the FPGA
through the boundary-scan port (when using TCK as a
start-up clock).
4.0
Program Pulse Width
T
300
PROGRAM
1. Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
2. Enter the Shift-DR (SDR) state
3. Shift a configuration bitstream into TDI
4. Return to Run-Test-Idle (RTI)
5. Load the JSTART instruction into IR
6. Enter the SDR state
7. Clock TCK through the startup sequence
8. Return to RTI
Start-Up Sequence
Configuration and readback via the TAP is always available.
The boundary-scan mode is selected by a <101> or 001>
on the mode pins (M2, M1, M0). For details on TAP charac-
teristics, refer to XAPP139.
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is released.
This permits device outputs to turn on as necessary.
One CCLK cycle later, the Global Set/Reset (GSR) and
Global Write Enable (GWE) signals are released. This per-
mits the internal storage elements to begin changing state
in response to the logic and the user clock.
Configuration Sequence
The configuration of Virtex devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
The relative timing of these events can be changed. In addi-
tion, the GTS, GSR, and GWE events can be made depen-
dent on the DONE pins of multiple devices all going High,
forcing the devices to start in synchronism. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura-
tion process can also be initiated by asserting PROGRAM.
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Virtex™ 2.5 V Field Programmable Gate Arrays
Data Stream Format
Readback
Virtex devices are configured by sequentially loading
frames of data. Table 11 lists the total number of bits
required to configure each device. For more detailed infor-
mation, see application note XAPP151 “Virtex Configura-
tion Architecture Advanced Users Guide”.
The configuration data stored in the Virtex configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUTRAMs, and block RAMs. This capabil-
ity is used for real-time debugging.
For more detailed information, see Application Note
XAPP138: Virtex FPGA Series Configuration and Readback,
available online at www.xilinx.com.
Table 11: Virtex Bit-Stream Lengths
Device
XCV50
# of Configuration Bits
559,200
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
781,216
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
4,715,616
6,127,744
Revision History
Date
11/98
01/99
02/99
05/99
05/99
07/99
Version
1.0
Revision
Initial Xilinx release.
1.2
Updated package drawings and specs.
1.3
Update of package drawings, updated specifications.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
1.4
1.5
1.6
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99
01/00
1.7
1.8
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, “0” hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added T
parameter, changed T
to T
.
IJITCC
OJIT
OPHASE
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for V
in CS144 package on p.43.
CCO
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Date
Version
Revision
01/00
1.9
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
03/00
2.0
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00
05/00
09/00
2.1
2.2
2.3
Modified “Pins not listed...” statement. Speed grade update to Final status.
Modified Table 18.
•
Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under IOB Input Switching Characteristics.
Added values to table under CLB SelectRAM Switching Characteristics.
•
•
•
Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
10/00
04/01
2.4
2.5
•
•
•
•
•
Corrected BG256 Pin Function Diagram.
Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Updated SelectMAP Write Timing Characteristics values in Table 9.
Converted file to modularized format. See the Virtex Data Sheet section.
Made minor edits to text under Configuration.
07/19/01
07/19/02
09/10/02
2.6
2.7
2.8
•
•
Made minor edit to Figure 16 and Figure 18.
Added clarifications in the Configuration, Boundary-Scan Mode, and Block
SelectRAM sections. Revised Figure 17.
•
•
Added clarification in the Boundary Scan section.
Corrected number of buffered Hex lines listed in General Purpose Routing section.
12/09/02
03/01/13
2.8.1
4.0
The products listed in this data sheet are obsolete. See XCN10016 for further information.
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
•
•
DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
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Field Programmable Gate Arrays
0
0
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Production Product Specification
Virtex Electrical Characteristics
Definition of Terms
Electrical and switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as
follows:
Table 1 correlates the current status of each Virtex device
with a corresponding speed file designation.
Table 1: Virtex Device Speed Grade Designations
Speed Grade Designations
Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Device
XCV50
Advance
Preliminary Production
–6, –5, –4
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
–6, –5, –4
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
–6, –5, –4
–6, –5, –4
–6, –5, –4
–6, –5, –4
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
–6, –5, –4
–6, –5, –4
–6, –5, –4
All specifications are subject to change without notice.
All specifications are representative of worst-case supply
voltage and junction temperature conditions. The parame-
ters included are common to popular designs and typical
applications. Contact the factory for design considerations
requiring more detailed information.
© 1999-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Virtex DC Characteristics
Absolute Maximum Ratings
(1)
Symbol
Description
Units
V
(2)
V
Supply voltage relative to GND
Supply voltage relative to GND
Input Reference Voltage
–0.5 to 3.0
–0.5 to 4.0
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 5.5
–0.5 to 5.5
50
CCINT
(2)
V
V
CCO
V
V
REF
(3)
Input voltage relative to GND
Using V
V
REF
V
IN
Internal threshold
V
V
Voltage applied to 3-state output
V
TS
V
Longest Supply Voltage Rise Time from 1V-2.375V
Storage temperature (ambient)
ms
°C
°C
CC
T
–65 to +150
+125
STG
(4)
T
Junction temperature
Plastic Packages
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.
2. Power supplies can turn on in any order.
3. For protracted periods (e.g., longer than a day), VIN should not exceed VCCO by more than 3.6 V.
4. For soldering guidelines and thermal considerations, see the "Device Packaging" information on www.xilinx.com.
Recommended Operating Conditions
Symbol
Description
Min
2.5 – 5%
2.5 – 5%
1.4
Max
2.5 + 5%
2.5 + 5%
3.6
Units
V
Input Supply voltage relative to GND, T = 0 °C to +85°C
Commercial
J
(1)
V
CCINT
Input Supply voltage relative to GND, T = –40°C to +100°C Industrial
V
J
Supply voltage relative to GND, T = 0 °C to +85°C
Commercial
Industrial
V
J
(4)
V
CCO
Supply voltage relative to GND, T = –40°C to +100°C
1.4
3.6
V
J
T
Input signal transition time
250
ns
IN
Notes:
1. Correct operation is guaranteed with a minimum VCCINT of 2.375 V (Nominal VCCINT –5%). Below the minimum value, all delay
parameters increase by 3% for each 50-mV reduction in VCCINT below the specified range.
2. At junction temperatures above those listed as Operating Conditions, delay parameters do increase. Please refer to the TRCE report.
3. Input and output measurement threshold is ~50% of VCC
4. Min and Max values for VCCO are I/O Standard dependant.
.
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Virtex™ 2.5 V Field Programmable Gate Arrays
DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Voltage
Device
Min
Max
Units
Data Retention V
CCINT
V
All
2.0
V
DRINT
(below which configuration data can be lost)
Data Retention V Voltage
CCO
V
All
1.2
V
DRIO
(below which configuration data can be lost)
(1,3)
I
Quiescent V
supply current
CCINT
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
All
50
50
50
75
75
75
100
100
100
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
CCINTQ
(1)
I
Quiescent V
supply current
CCO
CCOQ
2
2
2
2
2
2
2
2
I
V
current per V pin
REF
20
+10
8
REF
REF
I
Input or output leakage current
All
–10
μA
L
BGA, PQ, HQ, packages
C
Input capacitance (sample tested)
All
pF
IN
I
Pad pull-up (when selected) @ V = 0 V, V
tested)
= 3.3 V (sample
CCO
RPU
in
All
Note (2)
Note (2)
0.25
0.15
mA
mA
I
Pad pull-down (when selected) @ V = 3.6 V (sample tested)
in
RPD
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
3. Multiply ICCINTQ limit by two for industrial grade.
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Product Obsolete/Under Obsolescence
Virtex™ 2.5 V Field Programmable Gate Arrays
R
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
(1)
power supply voltage of the device from 0 V. The current is highest at the fastest suggested ramp rate (0 V to nominal
voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 V to nominal voltage in 50 ms). For more details on power
supply requirements, see Application Note XAPP158 on www.xilinx.com.
(2)
(1,3)
Product
Virtex Family, Commercial Grade
Virtex Family, Industrial Grade
Notes:
Description
Current Requirement
Minimum required current supply
Minimum required current supply
500 mA
2 A
1. Ramp rate used for this specification is from 0 - 2.7 VDC. Peak current occurs on or near the internal power-on reset threshold of
1.0V and lasts for less than 3 ms.
2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3. Larger currents can result if ramp rates are forced to be faster.
DC Input and Output Levels
Values for V and V are recommended input voltages. Values for I and I are guaranteed output currents over the
OH
IL
IH
OL
recommended operating conditions at the V and V test points. Only selected standards are tested. These are chosen
OL
OH
to ensure that all standards meet their specifications. The selected standards are tested at minimum V
for each standard
CCO
with the respective V and V voltage levels shown. Other standards are sample tested.
OL
OH
V
V
V
V
I
I
OH
IL
IH
OL
OH
OL
Input/Output
Standard
V, min
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V, max
V, min
2.0
V, max
5.5
V, Max
0.4
V, Min
2.4
mA
24
mA
–24
–12
Note 2
Note 2
n/a
(1)
LVTTL
0.8
.7
LVCMOS2
PCI, 3.3 V
PCI, 5.0 V
GTL
1.7
5.5
0.4
1.9
12
Note 2
Note 2
40
44% V
60% V
V
+ 0.5 10% V
90% V
CCO
CCINT
CCINT
CCO
CCO
0.8
– 0.05
2.0
+ 0.05
REF
5.5
0.55
0.4
0.6
0.4
0.4
0.4
2.4
n/a
n/a
V
V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
REF
GTL+
V
– 0.1
– 0.1
– 0.1
– 0.1
– 0.2
– 0.2
– 0.2
– 0.2
– 0.2
– 0.2
V
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.2
+ 0.2
+ 0.2
+ 0.2
+ 0.2
+ 0.2
36
n/a
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
(3)
HSTL I
V
V
V
V
V
– 0.4
8
–8
CCO
CCO
CCO
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
CTT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
– 0.4
– 0.4
24
–8
48
–8
V
V
– 0.6
V
V
+ 0.6
+ 0.8
+ 0.61
+ 0.80
+ 0.4
8
–8
REF
REF
REF
REF
– 0.8
– 0.61
– 0.80
– 0.4
16
–16
–7.6
–15.2
–8
V
V
V
V
7.6
15.2
8
REF
REF
REF
REF
V
V
REF
REF
Note 2
Note 2
AGP
10% V
90% V
CCO
CCO
Notes:
1. VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
3. DC input and output levels for HSTL18 (HSTL I/O standard with VCCO of 1.8 V) are provided in an HSTL white paper on
www.xilinx.com.
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R
Virtex™ 2.5 V Field Programmable Gate Arrays
Virtex Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation net list. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Virtex devices unless
otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in , page 6.
Speed Grade
Description
Propagation Delays
Device
Symbol
Min
-6
-5
-4
Units
Pad to I output, no delay
Pad to I output, with delay
All
T
0.39
0.8
0.8
0.8
0.8
0.8
0.9
0.9
1.1
1.1
0.8
0.8
1.5
1.5
1.5
1.5
1.5
1.8
1.8
2.1
2.1
1.6
0.9
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.4
2.4
1.8
1.0
1.9
1.9
1.9
1.9
1.9
2.3
2.3
2.7
2.7
2.0
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
IOPI
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
All
T
IOPID
Pad to output IQ via transparent
latch, no delay
T
IOPLI
Pad to output IQ via transparent
latch, with delay
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
T
1.9
1.9
2.0
2.0
2.0
2.1
2.1
2.2
2.3
3.7
3.7
3.9
4.0
4.0
4.1
4.2
4.4
4.5
4.2
4.2
4.3
4.4
4.4
4.6
4.7
4.9
5.1
4.8
4.8
4.9
5.1
5.1
5.3
5.4
5.6
5.8
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
IOPLID
Sequential Delays
Clock CLK
All
Minimum Pulse Width, High
Minimum Pulse Width, Low
Clock CLK to output IQ
T
0.8
0.8
0.2
1.5
1.5
0.7
1.7
1.7
0.7
2.0
2.0
0.8
ns, min
ns, min
ns, max
CH
T
CL
T
IOCKIQ
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R
Speed Grade
-6 -5
Setup Time / Hold Time
Description
Device
Symbol
Min
-4
Units
Setup and Hold Times with respect to Clock CLK at IOB input
register(1)
Pad, no delay
All
T
/T
0.8 / 0
1.9 / 0
1.9 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.1 / 0
2.2 / 0
2.3 / 0
0.37/ 0
1.6 / 0
1.8 / 0
4.1 / 0
4.1 / 0
4.3 / 0
4.4 / 0
4.4 / 0
4.6 / 0
4.7 / 0
4.9 / 0
5.0 / 0
0.9 / 0
2.0 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, max
IOPICK IOICKP
Pad, with delay
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
All
T
/T
3.7 / 0
3.7 / 0
3.8 / 0
3.9 / 0
3.9 / 0
4.1 / 0
4.2 / 0
4.4 / 0
4.5 / 0
0.8 / 0
4.7 / 0
4.7 / 0
4.9 / 0
5.0 / 0
5.0 / 0
5.3 / 0
5.4 / 0
5.6 / 0
5.8 / 0
1.0 / 0
IOPICKD IOICKPD
ICE input
T
/T
IOICECK IOCKICE
Set/Reset Delays
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
Notes:
All
All
All
T
0.49
0.70
4.9
1.0
1.4
9.7
1.1
1.6
1.3
1.8
ns, max
ns, max
ns, max
IOSRCKI
T
IOSRIQ
T
10.9
12.5
GSRQ
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
2. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
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Virtex™ 2.5 V Field Programmable Gate Arrays
IOB Input Switching Characteristics Standard Adjustments
Speed Grade
(1)
Description
Symbol
Standard
Min
-6
-5
-4
Units
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
T
LVTTL
LVCMOS2
PCI, 33 MHz, 3.3 V
PCI, 33 MHz, 5.0 V
PCI, 66 MHz, 3.3 V
GTL
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ILVTTL
T
–0.02
–0.05
0.13
–0.04
–0.11
0.25
–0.04
–0.12
0.28
–0.05
–0.14
0.33
ILVCMOS2
T
IPCI33_3
IPCI33_5
IPCI66_3
T
T
–0.05
0.10
–0.11
0.20
–0.12
0.23
–0.14
0.26
T
IGTL
T
GTL+
0.06
0.11
0.12
0.14
IGTLP
IHSTL
T
HSTL
0.02
0.03
0.03
0.04
T
T
SSTL2
–0.04
–0.02
0.01
–0.08
–0.04
0.02
–0.09
–0.05
0.02
–0.10
–0.06
0.02
ISSTL2
ISSTL3
SSTL3
T
CTT
ICTT
IAGP
T
AGP
–0.03
–0.06
–0.07
–0.08
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 9.
Speed Grade
Description
Propagation Delays
Symbol
Min
-6
-5
-4
Units
O input to Pad
T
1.2
1.4
2.9
3.4
3.2
3.7
3.5
4.0
ns, max
ns, max
IOOP
O input to Pad via transparent latch
3-State Delays
T
IOOLP
(1)
T input to Pad high-impedance
T
1.0
1.4
2.0
3.1
2.2
3.3
2.4
3.7
ns, max
ns, max
IOTHZ
T input to valid data on Pad
T
IOTON
T input to Pad high-impedance via
transparent latch
T
1.2
2.4
2.6
3.0
ns, max
IOTLPHZ
(1)
T input to valid data on Pad via
transparent latch
T
1.6
2.5
3.5
4.9
3.8
5.5
4.2
6.3
ns, max
ns, max
IOTLPON
(1)
GTS to Pad high impedance
T
GTS
Sequential Delays
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
T
0.8
0.8
1.5
1.5
1.7
1.7
2.0
2.0
ns, min
ns, min
CH
T
CL
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Virtex™ 2.5 V Field Programmable Gate Arrays
R
Speed Grade
Description
Symbol
Min
-6
-5
-4
Units
Clock CLK to Pad delay with OBUFT
enabled (non-3-state)
T
1.0
2.9
3.2
3.5
ns, max
IOCKP
Clock CLK to Pad high-impedance
(synchronous)
T
1.1
1.5
2.3
3.4
2.5
3.7
2.9
4.1
ns, max
ns, max
IOCKHZ
IOCKON
(1)
Clock CLK to valid data on Pad delay, plus
enable delay for OBUFT
T
Setup and Hold Times before/after Clock CLK(2)
Setup Time / Hold Time
O input
T
/T
0.51 / 0
0.37 / 0
0.52 / 0
0.34 / 0
0.41 / 0
0.49 / 0
1.1 / 0
1.2 / 0
0.9 / 0
1.2 / 0
0.8 / 0
0.9 / 0
1.1 / 0
1.3 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
IOOCK IOCKO
OCE input
T
T
/T
0.8 / 0
1.1 / 0
0.7 / 0
0.9 / 0
1.0 / 0
1.0 / 0
1.4 / 0
0.9 / 0
1.1 / 0
1.3 / 0
IOOCECK IOCKOCE
SR input (OFF)
/T
IOSRCKO IOCKOSR
3-State Setup Times, T input
3-State Setup Times, TCE input
3-State Setup Times, SR input (TFF)
Set/Reset Delays
T
/T
IOTCK IOCKT
T
T
/T
IOTCECK IOCKTCE
/T
IOSRCKT IOCKTSR
SR input to Pad (asynchronous)
SR input to Pad high-impedance
T
1.6
1.6
3.8
3.1
4.1
3.4
4.6
3.9
ns, max
ns, max
IOSRP
T
IOSRHZ
(1)
(asynchronous)
SR input to valid data on Pad
(asynchronous)
T
T
2.0
4.9
4.2
9.7
4.6
5.1
ns, max
ns, max
IOSRON
GSR to Pad
10.9
12.5
IOGSRQ
Notes:
1. 3-state turn-off delays should not be adjusted.
2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
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R
Virtex™ 2.5 V Field Programmable Gate Arrays
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Speed Grade
Unit
(1)
Description
Symbol
Standard
Min
-6
-5
-4
s
Output Delay Adjustments
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive load,
Csl)
T
T
T
T
LVTTL, Slow, 2 mA
4 mA
4.2
2.5
14.7
7.5
15.8
8.0
17.0
8.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OLVTTL_S2
OLVTTL_S4
OLVTTL_S6
OLVTTL_S8
6 mA
1.8
4.8
5.1
5.6
8 mA
1.2
3.0
3.3
3.5
T
T
T
12 mA
1.0
1.9
2.1
2.2
OLVTTL_S12
OLVTTL_S16
OLVTTL_S24
16 mA
0.9
1.7
1.9
2.0
24 mA
0.8
1.3
1.4
1.6
T
LVTTL, Fast, 2mA
4 mA
1.9
13.1
5.3
14.0
5.7
15.1
6.1
OLVTTL_F2
T
0.7
OLVTTL_F4
T
6 mA
0.2
3.1
3.3
3.6
OLVTTL_F6
T
8 mA
0.1
1.0
1.1
1.2
OLVTTL_F8
T
12 mA
0
0
0
0
OLVTTL_F12
T
16 mA
–0.10
–0.10
0.10
0.50
0.40
0.10
0.6
–0.05
–0.20
0.10
2.3
–0.05
–0.21
0.11
2.5
–0.05
–0.23
0.12
2.7
OLVTTL_F16
T
24 mA
OLVTTL_F24
T
LVCMOS2
PCI, 33 MHz, 3.3 V
PCI, 33 MHz, 5.0 V
PCI, 66 MHz, 3.3 V
GTL
OLVCMOS2
T
OPCI33_3
OPCI33_5
OPCI66_3
T
T
2.8
3.0
3.3
–0.40
0.50
0.8
–0.42
0.54
0.9
–0.46
0.6
T
OGTL
T
GTL+
0.7
1.0
OGTLP
T
HSTL I
0.10
–0.10
–0.20
–0.10
–0.20
–0.20
–0.30
0
–0.50
–0.9
–1.0
–0.50
–0.9
–0.50
–1.0
–0.6
–0.9
–0.53
–0.9
–1.0
–0.53
–0.9
–0.53
–1.0
–0.6
–0.9
–0.5
–1.0
–1.1
–0.5
–1.0
–0.5
–1.1
–0.6
–1.0
OHSTL_I
T
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
OHSTL_III
T
OHSTL_IV
T
OSSTL2_I
T
OSSLT2_II
T
OSSTL3_I
T
OSSTL3_II
T
OCTT
T
AGP
0
OAGP
Notes:
1. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see
Table 2 and Table 3.
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R
For other capacitive loads, use the formulas below to calcu-
late the corresponding T
Calculation of T
Capacitance
as a Function of
ioop
.
ioop
T
= T
+ T
+ (C
– C ) * fl
load sl
T
is the propagation delay from the O Input of the IOB to
ioop
ioop
opadjust
ioop
the pad. The values for T
capacitive load (Csl) for each I/O standard as listed in
Table 2.
were based on the standard
ioop
Where:
T
is reported above in the Output Delay
opadjust
Adjustment section.
C
is the capacitive load for the design.
load
Table 2: Constants for Calculating T
ioop
Csl
fl
Table 3: Delay Measurement Methodology
Meas.
Point Typ
Standard
LVTTL Fast Slew Rate, 2mA drive
LVTTL Fast Slew Rate, 4mA drive
LVTTL Fast Slew Rate, 6mA drive
LVTTL Fast Slew Rate, 8mA drive
LVTTL Fast Slew Rate, 12mA drive
LVTTL Fast Slew Rate, 16mA drive
LVTTL Fast Slew Rate, 24mA drive
LVTTL Slow Slew Rate, 2mA drive
LVTTL Slow Slew Rate, 4mA drive
LVTTL Slow Slew Rate, 6mA drive
LVTTL Slow Slew Rate, 8mA drive
LVTTL Slow Slew Rate, 12mA drive
LVTTL Slow Slew Rate, 16mA drive
LVTTL Slow Slew Rate, 24mA drive
LVCMOS2
(pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
50
10
10
0
(ns/pF)
V
0.41
0.20
REF
(2)
(1)
(1)
Standard
LVTTL
V
V
H
L
0
3
1.4
-
-
-
-
-
0.13
0.079
0.044
0.043
0.033
0.41
LVCMOS2
PCI33_5
PCI33_3
PCI66_3
GTL
0
2.5
Per PCI Spec
Per PCI Spec
Per PCI Spec
VREF +0.2
1.125
VREF –0.2
REF –0.2
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0.80
1.0
0.20
GTL+
V
VREF +0.2
0.100
0.086
0.058
0.050
0.048
0.041
0.050
0.050
0.033
0.014
0.017
0.022
0.016
0.014
0.028
0.016
0.029
0.016
0.035
0.037
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 I & II
SSTL2 I & II
CTT
VREF –0.5
VREF –0.5
VREF +0.5
0.75
0.90
0.90
1.5
VREF +0.5
V
REF –0.5
VREF +0.5
VREF –1.0
VREF +1.0
VREF –0.75 VREF +0.75
REF –0.2 VREF +0.2
VREF VREF
(0.2xVCCO (0.2xVCCO
1.25
1.5
PCI 33MHz 5V
V
PCI 33MHZ 3.3 V
AGP
–
+
Per
AGP
Spec
PCI 66 MHz 3.3 V
)
)
GTL
GTL+
0
Notes:
1. Input waveform switches between VLand VH.
HSTL Class I
20
20
20
30
30
30
30
20
10
2. Measurements are made at VREF (Typ), Maximum, and
HSTL Class III
Minimum. Worst-case values are reported.
3. I/O parameter measurements are made with the capacitance
values shown in Table 2. See Application Note XAPP133 on
www.xilinx.com for appropriate terminations.
HSTL Class IV
SSTL2 Class I
4. I/O standard measurements are reflected in the IBIS model
SSTL2 Class II
information except where the IBIS format precludes it.
SSTL3 Class I
SSTL3 Class II
CTT
AGP
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. See Application Note XAPP133 on
www.xilinx.com for appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
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Virtex™ 2.5 V Field Programmable Gate Arrays
Clock Distribution Guidelines
Speed Grade
Description
Device
Symbol
-6
-5
-4
Units
(1)
Global Clock Skew
Global Clock Skew between IOB Flip-flops
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
T
0.10
0.12
0.12
0.13
0.14
0.13
0.14
0.16
0.20
0.12
0.13
0.13
0.14
0.16
0.13
0.15
0.17
0.23
0.14
0.15
0.15
0.16
0.18
0.14
0.17
0.20
0.25
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
GSKEWIOB
Notes:
1. These clock-skew delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case
conditions. Precise values for a particular design are provided by the timing analyzer.
Clock Distribution Switching Characteristics
Speed Grade
Description
GCLK IOB and Buffer
Symbol
Min
-6
-5
-4
Units
Global Clock PAD to output.
T
0.33
0.34
0.7
0.7
0.8
0.8
0.9
0.9
ns, max
ns, max
GPIO
Global Clock Buffer I input to O output
T
GIO
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R
I/O Standard Global Clock Input Adjustments
Speed Grade
(1)
Description
Symbol
Standard
Min
-6
-5
-4
Units
Data Input Delay Adjustments
Standard-specific global clock input
delay adjustments
T
LVTTL
0
0
0
0
ns,
max
GPLVTTL
T
LVCMOS2
–0.02
–0.05
0.13
–0.05
0.7
–0.04
–0.11
0.25
–0.11
0.8
–0.04
–0.12
0.28
–0.12
0.9
–0.05
–0.14
0.33
–0.14
0.9
ns,
max
GPLVCMOS
2
T
T
T
PCI, 33 MHz, 3.3
V
ns,
max
GPPCI33_3
GPPCI33_5
GPPCI66_3
PCI, 33 MHz, 5.0
V
ns,
max
PCI, 66 MHz, 3.3
V
ns,
max
T
GTL
GTL+
HSTL
SSTL2
SSTL3
CTT
ns,
max
GPGTL
T
0.7
0.8
0.8
0.8
ns,
max
GPGTLP
GPHSTL
T
0.7
0.7
0.7
0.7
ns,
max
T
T
0.6
0.52
0.6
0.51
0.55
0.7
0.50
0.54
0.7
ns,
max
GPSSTL2
GPSSTL3
0.6
ns,
max
T
0.7
0.7
ns,
GPCTT
max
T
AGP
0.6
0.54
0.53
0.52
ns,
GPAGP
max
Notes:
1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
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Virtex™ 2.5 V Field Programmable Gate Arrays
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Speed Grade
Description
Combinatorial Delays
Symbol
Min
-6
-5
-4
Units
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
T
0.29
0.32
0.36
0.44
0.17
0.31
0.6
0.7
0.7
0.8
0.8
1.0
0.36
0.7
0.8
0.9
1.0
1.2
0.42
0.8
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ILO
T
IF5
T
T
0.8
IF5X
IF6Y
0.9
T
0.32
0.7
F5INY
Incremental delay routing through transparent latch
to XQ/YQ outputs
T
IFNCTL
BY input to YB output
T
0.27
0.53
0.6
0.7
ns, max
BYYB
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
T
0.54
0.6
1.1
1.2
1.2
1.4
1.4
1.6
ns, max
ns, max
CKO
T
CKLO
(1)
Setup and Hold Times before/after Clock CLK
Setup Time / Hold Time
4-input function: F/G Inputs
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
T
/T
0.6 / 0
0.7 / 0
1.2 / 0 1.4 / 0 1.5 / 0 ns, min
1.3 / 0 1.5 / 0 1.7 / 0 ns, min
ICK CKI
T
/T
IF5CK CKIF5
T
/T
0.46 / 0 1.0 / 0 1.1 / 0 1.2 / 0 ns, min
0.8 / 0 1.5 / 0 1.7 / 0 1.9 / 0 ns, min
F5INCK CKF5IN
T
/T
IF6CK CKIF6
T
/T
0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min
0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min
0.33 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min
DICK CKDI
CE input
T
/T
CECK CKCE
SR/BY inputs (synchronous)
Clock CLK
T
T
RCK CKR
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
T
0.8
0.8
1.5
1.5
1.7
1.7
2.0
2.0
ns, min
ns, min
CH
T
CL
Minimum Pulse Width, SR/BY inputs
T
1.3
2.5
1.1
2.8
1.3
3.3
1.4
ns, min
ns, max
RPW
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
T
0.54
RQ
Delay from GSR to XQ/YQ outputs
Toggle Frequency (MHz) (for export control)
Notes:
T
4.9
9.7
10.9
294
12.5
250
ns, max
MHz
IOGSRQ
F
(MHz)
625
333
TOG
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
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R
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Speed Grade
Description
Combinatorial Delays
Symbol
Min
-6
-5
-4
Units
F operand inputs to X via XOR
F operand input to XB output
F operand input to Y via XOR
F operand input to YB output
F operand input to COUT output
G operand inputs to Y via XOR
G operand input to YB output
G operand input to COUT output
BX initialization input to COUT
CIN input to X output via XOR
CIN input to XB
T
0.37
0.54
0.8
0.8
1.1
0.9
1.3
1.0
1.4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
OPX
T
OPXB
T
1.5
1.7
2.0
2.0
1.5
1.2
OPY
T
0.8
1.5
1.7
OPYB
T
0.6
1.2
1.3
OPCYF
T
0.46
0.8
1.0
1.1
OPGY
T
1.6
1.8
2.1
1.6
1.1
OPGYB
T
0.7
1.3
1.4
OPCYG
T
0.41
0.21
0.02
0.23
0.23
0.05
0.9
1.0
BXCY
T
0.41
0.04
0.46
0.45
0.09
0.46
0.05
0.52
0.51
0.10
0.53
0.06
0.6
0.6
0.11
CINX
T
T
CINXB
CIN input to Y via XOR
T
CINY
CIN input to YB
CINYB
CIN input to COUT output
T
BYP
Multiplier Operation
F1/2 operand inputs to XB output via AND
F1/2 operand inputs to YB output via AND
F1/2 operand inputs to COUT output via AND
G1/2 operand inputs to YB output via AND
G1/2 operand inputs to COUT output via AND
T
T
0.18
0.40
0.22
0.25
0.07
0.36
0.8
0.40
0.9
0.46
1.1
ns, max
ns, max
ns, max
ns, max
ns, max
FANDXB
FANDYB
FANDCY
GANDYB
GANDCY
T
T
0.43
0.50
0.13
0.48
0.6
0.6
0.7
T
0.15
0.17
(1)
Setup and Hold Times before/after Clock CLK
Setup Time / Hold Time
CIN input to FFX
CIN input to FFY
Notes:
T
T
/T
0.50 / 0
0.53 / 0
1.0 / 0
1.1 / 0
1.2 / 0
1.2 / 0
1.3 / 0
1.4 / 0
ns, min
ns, min
CCKX CKCX
/T
CCKY CKCY
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
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Virtex™ 2.5 V Field Programmable Gate Arrays
CLB SelectRAM Switching Characteristics
Speed Grade
Description
Sequential Delays
Symbol
Min
-6
-5
-4
Units
Clock CLK to X/Y outputs (WE active) 16 x 1 mode
Clock CLK to X/Y outputs (WE active) 32 x 1 mode
Shift-Register Mode
T
1.2
1.2
2.3
2.7
2.6
3.1
3.0
3.5
ns, max
ns, max
SHCKO16
T
SHCKO32
Clock CLK to X/Y outputs
T
1.2
3.7
4.1
4.7
ns, max
REG
(1)
Setup and Hold Times before/after Clock CLK
Setup Time / Hold Time
F/G address inputs
BX/BY data inputs (DIN)
CE input (WE)
T
/T
0.25 / 0
0.34 / 0
0.38 / 0
0.5 / 0
0.7 / 0
0.8 / 0
0.6 / 0
0.8 / 0
0.9 / 0
0.7 / 0
0.9 / 0
1.0 / 0
ns, min
ns, min
ns, min
AS AH
T
/T
DS DH
T
/T
WS WH
Shift-Register Mode
BX/BY data inputs (DIN)
CE input (WS)
T
0.34
0.38
0.7
0.8
0.8
0.9
0.9
1.0
ns, min
ns, min
SHDICK
T
SHCECK
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
T
1.2
1.2
2.4
2.4
2.4
4.8
2.7
2.7
5.4
3.1
3.1
6.2
ns, min
ns, min
ns, min
WPH
T
WPL
Minimum clock period to meet address write cycle
time
T
WC
Shift-Register Mode
Minimum Pulse Width, High
Minimum Pulse Width, Low
Notes:
T
1.2
1.2
2.4
2.4
2.7
2.7
3.1
3.1
ns, min
ns, min
SRPH
T
SRPL
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
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R
Block RAM Switching Characteristics
Speed Grade
Description
Sequential Delays
Symbol
Min
-6
-5
-4
Units
Clock CLK to DOUT output
T
1.7
3.4
3.8
4.3
ns, max
BCKO
(1)
Setup and Hold Times before/after Clock CLK
Setup Time / Hold Time
ADDR inputs
T
/T
0.6 / 0
0.6 / 0
1.3 / 0
1.3 / 0
1.2 / 0
1.2 / 0
1.2 / 0
2.6 / 0
2.5 / 0
2.3 / 0
1.3 / 0
1.3 / 0
3.0 / 0
2.7 / 0
2.6 / 0
1.5 / 0
1.5 / 0
3.4 / 0
3.2 / 0
3.0 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
BACK BCKA
DIN inputs
T
/T
BDCK BCKD
EN input
T
/T
BECK BCKE
RST input
T
/T
BRCK BCKR
WEN input
T
/T
BWCK BCKW
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
CLKA -> CLKB setup time for different ports
Notes:
T
0.8
0.8
1.5
1.5
3.0
1.7
1.7
3.5
2.0
2.0
4.0
ns, min
ns, min
ns, min
BPWH
T
BPWL
BCCS
T
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
TBUF Switching Characteristics
Speed Grade
Description
Symbol
Min
-6
-5
-4
Units
Combinatorial Delays
IN input to OUT output
T
0
0
0
0
ns, max
ns, max
ns, max
IO
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
T
0.05
0.05
0.09
0.09
0.10
0.10
0.11
0.11
OFF
T
ON
JTAG Test Access Port Switching Characteristics
Speed Grade
Description
Symbol
-6
4.0
2.0
11.0
33
-5
4.0
2.0
11.0
33
-4
Units
ns, min
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
T
T
4.0
2.0
TAPTCK
ns, min
TCKTAP
TCKTDO
T
11.0
33
ns, max
MHz, max
F
TCK
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Production Product Specification
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R
Virtex™ 2.5 V Field Programmable Gate Arrays
Virtex Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Speed Grade
Description
Symbol
Device
XCV50
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
-6
-5
-4
Units
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, with DLL.
For data output with different standards, adjust
delays with the values shown in Output Delay
Adjustments.
T
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ICKOFDLL
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see Table 2 and Table 3.
3. DLL output jitter is already included in the timing calculation.
Global Clock Input-to-Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Speed Grade
Description
Symbol
Device
XCV50
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.6
1.6
1.7
-6
-5
-4
Units
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without DLL.
For data output with different standards, adjust
delays with the values shown in Input and Output
Delay Adjustments.
T
4.6
4.6
4.7
4.7
4.7
4.8
4.9
4.9
5.0
5.1
5.1
5.2
5.2
5.2
5.3
5.4
5.5
5.6
5.7
5.7
5.8
5.8
5.9
6.0
6.0
6.2
6.3
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ICKOF
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
For I/O standards requiring V , such as GTL,
REF
GTL+, SSTL, HSTL, CTT, and AGO, an additional
600 ps must be added.
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see Table 2 and Table 3.
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Virtex™ 2.5 V Field Programmable Gate Arrays
R
Minimum Clock-to-Out for Virtex Devices
With DLL
Without DLL
V100 V150 V200 V300 V400 V600 V800 V1000
I/O Standard
*LVTTL_S2
*LVTTL_S4
*LVTTL_S6
*LVTTL_S8
*LVTTL_S12
*LVTTL_S16
*LVTTL_S24
*LVTTL_F2
*LVTTL_F4
*LVTTL_F6
*LVTTL_F8
*LVTTL_F12
*LVTTL_F16
*LVTTL_F24
LVCMOS2
PCI33_3
All Devices
5.2
3.5
2.8
2.2
2.0
1.9
1.8
2.9
1.7
1.2
1.1
1.0
0.9
0.9
1.1
1.5
1.4
1.1
1.6
1.7
1.1
0.9
0.8
0.9
0.8
0.8
0.7
1.0
1.0
V50
6.0
4.3
3.6
3.1
2.9
2.8
2.6
3.8
2.6
2.0
1.9
1.8
1.7
1.7
1.9
2.4
2.2
1.9
2.5
2.5
1.9
1.7
1.6
1.7
1.6
1.6
1.5
1.8
1.8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0
4.3
3.6
3.1
2.9
2.8
2.6
3.8
2.6
2.0
1.9
1.8
1.8
1.7
1.9
2.4
2.2
1.9
2.5
2.5
1.9
1.7
1.6
1.7
1.6
1.7
1.5
1.8
1.8
6.0
4.3
3.6
3.1
2.9
2.8
2.7
3.8
2.6
2.0
1.9
1.8
1.8
1.7
1.9
2.4
2.3
2.0
2.5
2.6
1.9
1.8
1.6
1.7
1.6
1.7
1.6
1.8
1.9
6.0
4.3
3.6
3.1
2.9
2.8
2.7
3.8
2.6
2.1
1.9
1.8
1.8
1.8
2.0
2.4
2.3
2.0
2.5
2.6
1.9
1.8
1.7
1.7
1.6
1.7
1.6
1.9
1.9
6.1
4.4
3.7
3.1
2.9
2.8
2.7
3.8
2.6
2.1
2.0
1.9
1.8
1.8
2.0
2.4
2.3
2.0
2.5
2.6
2.0
1.8
1.7
1.8
1.7
1.7
1.6
1.9
1.9
6.1
4.4
3.7
3.1
2.9
2.8
2.7
3.8
2.6
2.1
2.0
1.9
1.8
1.8
2.0
2.4
2.3
2.0
2.5
2.6
2.0
1.8
1.7
1.8
1.7
1.7
1.6
1.9
1.9
6.1
4.4
3.7
3.2
3.0
2.9
2.7
3.9
2.7
2.1
2.0
1.9
1.8
1.8
2.0
2.5
2.3
2.0
2.6
2.6
2.0
1.8
1.7
1.8
1.7
1.7
1.6
1.9
1.9
6.1
4.4
3.7
3.2
3.0
2.9
2.7
3.9
2.7
2.1
2.0
1.9
1.9
1.8
2.0
2.5
2.3
2.1
2.6
2.6
2.0
1.8
1.7
1.8
1.7
1.8
1.6
1.9
1.9
6.1
4.4
3.7
3.2
3.0
2.9
2.8
3.9
2.7
2.2
2.0
1.9
1.9
1.9
2.1
2.5
2.4
2.1
2.6
2.7
2.0
1.9
1.8
1.8
1.7
1.8
1.7
2.0
2.0
PCI33_5
PCI66_3
GTL
GTL+
HSTL I
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
AGP
*S = Slow Slew Rate, F = Fast Slew Rate
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Input and output timing is measured at 1.4 V for LVTTL. For other I/O standards, see Table 3. In all cases, an 8 pF external capacitive
load is used.
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Virtex Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Speed Grade
Description
Symbol
Device
Min
-6
-5
-4
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
No Delay
T
/T
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
0.40 / –0.4 1.7 /–0.4 1.8 /–0.4 2.1 /–0.4
0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4
0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4
0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4
0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4
0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4
0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4
0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4
0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4
ns,
min
PSDLL PHDLL
Global Clock and IFF, with DLL
ns,
min
ns,
min
ns,
min
ns,
min
ns,
min
ns,
min
ns,
min
ns,
min
IFF = Input Flip-Flop or Latch
Notes:
1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. DLL output jitter is already included in the timing calculation.
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
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Global Clock Set-Up and Hold for LVTTL Standard, without DLL
Speed Grade
-6 -5
Description
Symbol
Device
Min
-4
Units
(2)
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
Full Delay
T
/T
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
0.6 / 0
0.6 / 0
0.6 / 0
0.7 / 0
0.7 / 0
0.7 / 0
0.7 / 0
0.7 / 0
0.7 / 0
2.3 / 0
2.3 / 0
2.4 / 0
2.5 / 0
2.5 / 0
2.6 / 0
2.6 / 0
2.7 / 0
2.8 / 0
2.6 / 0
2.6 / 0
2.7 / 0
2.8 / 0
2.8 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
2.9 / 0
3.0 / 0
3.1 / 0
3.2 / 0
3.2 / 0
3.3 / 0
3.3 / 0
3.5 / 0
3.6 / 0
ns,
min
PSFD PHFD
Global Clock and IFF, without
DLL
ns,
min
ns,
min
ns,
min
ns,
min
ns,
min
ns,
min
ns,
min
ns,
min
IFF = Input Flip-Flop or Latch
Notes: Notes:
1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
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Virtex™ 2.5 V Field Programmable Gate Arrays
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
Speed Grade
-6
-5
-4
Description
Input Clock Frequency (CLKDLLHF)
Input Clock Frequency (CLKDLL)
Input Clock Pulse Width (CLKDLLHF)
Input Clock Pulse Width (CLKDLL)
Notes:
Symbol
FCLKINHF
FCLKINLF
Min
60
Max
200
100
-
Min
60
Max
180
90
Min
60
Max
180
90
-
Units
MHz
MHz
ns
25
25
25
T
2.0
2.5
2.4
3.0
-
2.4
3.0
DLLPWHF
T
-
-
ns
DLLPWLF
1. All specifications correspond to Commercial Operating Temperatures (0°C to + 85°C).
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
CLKDLLHF
CLKDLL
Description
Input Clock Period Tolerance
Symbol
FCLKIN
Min
Max Min Max Units
T
-
-
-
-
-
-
-
1.0
150
20
-
-
-
-
-
-
-
-
1.0
300
20
ns
ps
μs
μs
μs
μs
μs
ps
ps
ps
IPTOL
IJITCC
Input Clock Jitter Tolerance (Cycle to Cycle)
Time Required for DLL to Acquire Lock
T
T
> 60 MHz
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
25 - 30 MHz
LOCK
25
-
50
-
90
-
120
60
(1)
Output Jitter (cycle-to-cycle) for any DLL Clock Output
T
60
100
140
OJITCC
(2)
Phase Offset between CLKIN and CLKO
T
100
140
PHIO
(3)
Phase Offset between Clock Outputs on the DLL
T
PHOO
Maximum Phase Difference between CLKIN and
CLKO
T
160
200
160
200
ps
ps
PHIOM
(4)
Maximum Phase Difference between Clock Outputs on
T
PHOOM
(5)
the DLL
Notes:
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6. All specifications correspond to Commercial Operating Temperatures (0°C to +85°C).
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Period Tolerance: the allowed input clock period change in nanoseconds.
+ T
_
T
T
IPTOL
CLKIN
CLKIN
Output Jitter: the difference between an ideal Phase Offset and Maximum Phase Difference
reference clock edge and the actual design.
Ideal Period
Actual Period
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
ds003_20c_110399
Figure 1: Frequency Tolerance and Clock Jitter
Revision History
Date
11/98
01/99
02/99
05/99
05/99
07/99
Version
1.0
Revision
Initial Xilinx release.
1.2
Updated package drawings and specs.
1.3
Update of package drawings, updated specifications.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
1.4
1.5
1.6
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99
01/00
1.7
1.8
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, "0" hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added T
parameter, changed T
to T
.
IJITCC
OJIT
OPHASE
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for V
in CS144 package on p.43.
CCO
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Date
Version
Revision
01/00
1.9
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
03/00
2.0
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00
05/00
09/00
2.1
2.2
2.3
Modified "Pins not listed..." statement. Speed grade update to Final status.
Modified Table 18.
•
Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under IOB Input Switching Characteristics.
Added values to table under CLB SelectRAM Switching Characteristics.
•
•
•
Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
10/00
2.4
2.5
•
•
•
•
Corrected BG256 Pin Function Diagram.
Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Converted file to modularized format. See the Virtex Data Sheet section.
Clarified TIOCKP and TIOCKON IOB Output Switching Characteristics descriptors.
04/02/01
04/19/01
07/19/01
07/26/01
10/29/01
2.6
2.7
2.8
2.9
•
•
•
Under Absolute Maximum Ratings, changed (T
) to 220 °C.
SOL
Removed T
parameter and added footnote to Absolute Maximum Ratings table.
SOL
Updated the speed grade designations used in data sheets, and added Table 1, which
shows the current speed grade designation for each device.
•
Added footnote to DC Input and Output Levels table.
02/01/02
07/19/02
3.0
3.1
•
•
•
Removed mention of MIL-M-38510/605 specification.
Added link to xapp158 from the Power-On Power Supply Requirements section.
Added Clock CLK to IOB Input Switching Characteristics and IOB Output Switching
Characteristics.
09/10/02
03/01/13
3.2
4.0
The products listed in this data sheet are obsolete. See XCN10016 for further information.
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
•
•
DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
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Field Programmable Gate Arrays
0
0
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Virtex Pin Definitions
Table 1: Special Purpose Pins
Dedicated
Pin Name
Pin
Direction
Description
GCK0, GCK1,
GCK2, GCK3
Yes
Input
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
M0, M1, M2
CCLK
Yes
Yes
Input
Mode pins are used to specify the configuration mode.
Input or
Output
The configuration Clock I/O pin: it is an input for SelectMAP and
slave-serial modes, and output in master-serial mode. After configuration,
it is input only, logic level = Don’t Care.
PROGRAM
DONE
Yes
Yes
Input
Initiates a configuration sequence when asserted Low.
Bidirectional
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
INIT
No
No
Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being cleared. The
pin becomes a user I/O after configuration.
BUSY/
DOUT
Output
In SelectMAP mode, BUSY controls the rate at which configuration data
is loaded. The pin becomes a user I/O after configuration unless the
SelectMAP port is retained.
In bit-serial modes, DOUT provides header information to downstream
devices in a daisy-chain. The pin becomes a user I/O after configuration.
D0/DIN,
D1, D2,
D3, D4,
D5, D6,
D7
No
Input or
Output
In SelectMAP mode, D0 - D7 are configuration data pins. These pins
become user I/Os after configuration unless the SelectMAP port is
retained.
In bit-serial modes, DIN is the single data input. This pin becomes a user
I/O after configuration.
WRITE
CS
No
No
Input
Input
Mixed
In SelectMAP mode, the active-low Write Enable signal. The pin becomes
a user I/O after configuration unless the SelectMAP port is retained.
In SelectMAP mode, the active-low Chip Select signal. The pin becomes
a user I/O after configuration unless the SelectMAP port is retained.
TDI, TDO,
TMS, TCK
Yes
Boundary-scan Test-Access-Port pins, as defined in IEEE 1149.1.
DXN, DXP
VCCINT
VCCO
Yes
Yes
Yes
No
N/A
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
Power-supply pins for the internal core logic.
Input
Input
Input
Power-supply pins for the output drivers (subject to banking rules)
VREF
Input threshold voltage pins. Become user I/Os when an external
threshold voltage is not needed (subject to banking rules).
GND
Yes
Input
Ground
© 1999-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Virtex Pinout Information
Pinout Tables
See www.xilinx.com for updates or additional pinout information. For convenience, Table 2, Table 3 and Table 4 list the
locations of special-purpose and power-supply pins. Pins not listed are either user I/Os or not connected, depending on the
device/package combination. See the Pinout Diagrams starting on page 17 for any pins not listed for a particular
part/package combination.
Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages)
Pin Name
Device
CS144
TQ144
PQ/HQ240
GCK0
GCK1
GCK2
GCK3
M0
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
K7
90
93
19
16
110
112
108
38
72
74
71
39
40
45
47
51
59
63
65
70
32
33
34
36
143
2
92
M7
89
A7
210
213
60
A6
M1
M1
L2
58
M2
N2
62
CCLK
B13
L12
M12
L13
C11
C12
E10
E12
F11
H12
J13
J11
K10
C10
D10
A11
A12
B1
179
122
120
123
178
177
167
163
156
145
138
134
124
185
184
183
181
2
PROGRAM
DONE
INIT
BUSY/DOUT
D0/DIN
D1
D2
D3
D4
D5
D6
D7
WRITE
CS
TDI
TDO
TMS
TCK
C3
239
V
A9, B6, C5, G3,
G12, M5, M9, N6
10, 15, 25, 57, 84, 94,
99, 126
16, 32, 43, 77, 88, 104,
137, 148, 164, 198,
214, 225
CCINT
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Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)
Pin Name
Device
CS144
TQ144
PQ/HQ240
V
All
Banks 0 and 1:
A2, A13, D7
No I/O Banks in this
package:
No I/O Banks in this
package:
CCO
1, 17, 37, 55, 73, 92,
109, 128
15, 30, 44, 61, 76, 90,
105, 121, 136, 150, 165,
180, 197, 212, 226, 240
Banks 2 and 3:
B12, G11, M13
Banks 4 and 5:
N1, N7, N13
Banks 6 and 7:
B2, G2, M2
V
, Bank 0
XCV50
C4, D6
... + B4
N/A
5, 13
... + 7
N/A
218, 232
... + 229
... + 236
... + 215
... + 230
... + 222
REF
(V
pins are listed
XCV100/150
XCV200/300
XCV400
REF
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
N/A
N/A
XCV600
N/A
N/A
XCV800
N/A
N/A
Within each bank, if
input reference voltage
is not required, all
V
pins are general
REF
I/O.
V
, Bank 1
XCV50
XCV100/150
XCV200/300
XCV400
A10, B8
... + D9
N/A
22, 30
... + 28
N/A
191, 205
... + 194
... + 187
... + 208
... + 193
... + 201
REF
(V
pins are listed
REF
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
N/A
N/A
XCV600
N/A
N/A
XCV800
N/A
N/A
Within each bank, if
input reference voltage
is not required, all
V
pins are general
REF
I/O.
V
, Bank 2
XCV50
XCV100/150
XCV200/300
XCV400
D11, F10
... + D13
N/A
42, 50
... + 44
N/A
157, 171
... + 168
... + 175
... + 154
... + 169
... + 161
REF
(V
pins are listed
REF
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
N/A
N/A
XCV600
N/A
N/A
XCV800
N/A
N/A
Within each bank, if
input reference voltage
is not required, all
V
pins are general
REF
I/O.
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1-800-255-7778
Module 4 of 4
3
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)
Pin Name
Device
XCV50
CS144
H11, K12
... + J10
N/A
TQ144
60, 68
... + 66
N/A
PQ/HQ240
130, 144
... + 133
... + 126
... + 147
... + 132
... + 140
V
, Bank 3
REF
(V
pins are listed
XCV100/150
XCV200/300
XCV400
REF
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
N/A
N/A
XCV600
N/A
N/A
XCV800
N/A
N/A
Within each bank, if
input reference voltage
is not required, all
V
pins are general
REF
I/O.
V
, Bank 4
XCV50
XCV100/150
XCV200/300
XCV400
L8, L10
... + N10
N/A
79, 87
... + 81
N/A
97, 111
... + 108
... + 115
... + 94
REF
(V
pins are listed
REF
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
N/A
N/A
XCV600
N/A
N/A
... + 109
... + 101
XCV800
N/A
N/A
Within each bank, if
input reference voltage
is not required, all
V
pins are general
REF
I/O.
V
, Bank 5
XCV50
XCV100/150
XCV200/300
XCV400
L4, L6
... + N4
N/A
96, 104
... + 102
N/A
70, 84
... + 73
... + 66
... + 87
... + 72
... + 80
REF
(V
pins are listed
REF
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
N/A
N/A
XCV600
N/A
N/A
XCV800
N/A
N/A
Within each bank, if
input reference voltage
is not required, all
V
pins are general
REF
I/O.
Module 4 of 4
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DS003-4 (v4.0) March 1, 2013
Production Product Specification
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)
Pin Name
Device
XCV50
CS144
H2, K1
... + J3
N/A
TQ144
116, 123
... + 118
N/A
PQ/HQ240
36, 50
V
, Bank 6
REF
(V
pins are listed
XCV100/150
XCV200/300
XCV400
... + 47
... + 54
... + 33
... + 48
... + 40
REF
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
N/A
N/A
XCV600
N/A
N/A
XCV800
N/A
N/A
Within each bank, if
input reference voltage
is not required, all
V
pins are general
REF
I/O.
V
, Bank 7
XCV50
XCV100/150
XCV200/300
XCV400
D4, E1
... + D2
N/A
133, 140
... + 138
N/A
9, 23
... + 12
... + 5
REF
(V
pins are listed
REF
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
N/A
N/A
... + 26
... + 11
... + 19
XCV600
N/A
N/A
XCV800
N/A
N/A
Within each bank, if
input reference voltage
is not required, all
V
pins are general
REF
I/O.
GND
All
A1, B9, B11, C7,
D5, E4, E11, F1,
G10, J1, J12, L3,
L5, L7, L9, N12
9, 18, 26, 35, 46, 54, 64, 1, 8, 14, 22, 29, 37, 45, 51,
75, 83, 91, 100, 111, 120, 59, 69, 75, 83, 91, 98, 106,
129, 136, 144,
112, 119, 129, 135, 143,
151, 158, 166, 172, 182,
190, 196, 204, 211, 219,
227, 233
DS003-4 (v4.0) March 1, 2013
Production Product Specification
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1-800-255-7778
Module 4 of 4
5
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 3: Virtex Pinout Tables (BGA)
Pin Name
Device
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
BG256
Y11
Y10
A10
B10
Y1
BG352
AE13
AF14
B14
D14
AD24
AB23
AC23
C3
BG432
AL16
AK16
A16
D17
AH28
AH29
AJ28
D4
BG560
AL17
AJ17
D17
A17
AJ29
AK30
AN32
C4
GCK0
GCK1
GCK2
GCK3
M0
M1
U3
M2
W2
CCLK
PROGRAM
DONE
INIT
B19
Y20
W19
U18
D18
C19
E20
G19
J19
M19
P19
T20
V19
A19
B18
C17
A20
D3
AC4
AD3
AD2
E4
AH3
AH4
AJ2
D3
AM1
AJ5
AH5
D4
BUSY/DOUT
D0/DIN
D1
D3
C2
E4
G1
K4
K3
D2
J3
K2
L4
D3
M3
P4
P3
D4
R3
V4
W4
D5
U4
AB1
AB3
AG4
B4
AB5
AC4
AJ4
D6
D6
V3
D7
AC3
D5
WRITE
CS
C4
D5
A2
TDI
B3
B3
D5
TDO
TMS
TCK
D4
C4
E6
D23
C24
AD23
AE24
D29
D28
AH27
AK29
B33
E29
AK29
AJ28
A1
DXN
DXP
W3
V4
Module 4 of 4
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DS003-4 (v4.0) March 1, 2013
Production Product Specification
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 3: Virtex Pinout Tables (BGA) (Continued)
Pin Name
Device
BG256
BG352
BG432
BG560
V
XCV50/100
C10, D6,
D15, F4,
F17, L3,
L18, R4,
R17, U6,
U15, V10
N/A
N/A
N/A
CCINT
Notes:
• Superset includes all pins,
including the ones in bold
type. Subset excludes pins in
bold type.
• In BG352, for XCV300 all the
VCCINT pins in the superset
XCV150/200/300
Same as
above
A20, C14,
D10, J24,
K4, P2, P25,
V24, W2,
AC10, AE14,
AE19,
A10, A17, B23,
C14, C19, K3,
K29, N2, N29,
T1, T29, W2,
W31, AB2,
AB30, AJ10,
AJ16, AK13,
AK19, AK22,
N/A
must be connected. For
XCV150/200, VCCINT pins in
the subset must be
connected, and pins in bold
type can be left unconnected
(these unconnected pins
cannot be used as user I/O.)
• In BG432, for
B16, D12,
L1, L25,
R23, T1,
AF11, AF16 F30, AE29, AF1,
AH8, AH24
B26, C7, F1,
XCV400/600/800 all VCCINT
pins in the superset must be
connected. For XCV300,
VCCINT pins in the subset
must be connected, and pins
in bold type can be left
unconnected (these
XCV400/600/800/1000
N/A
N/A
Same as above
A21, B14, B18,
B28, C24, E9,
E12, F2, H30,
J1, K32, N1,
N33, U5, U30,
Y2, Y31, AD2,
AD32, AG3,
unconnected pins cannot be
used as user I/O.)
• In BG560, for XCV800/1000
all VCCINT pins in the
AG31, AK8,
superset must be connected.
For XCV400/600, VCCINT
pins in the subset must be
connected, and pins in bold
type can be left unconnected
(these unconnected pins
AK11, AK17,
AK20, AL14,
AL27, AN25,
B12, C22, M3,
N29, AB2,
AB32, AJ13,
AL22
cannot be used as user I/O.)
V
V
V
V
V
V
, Bank 0
, Bank 1
, Bank 2
, Bank 3
, Bank 4
, Bank 5
All
All
All
All
All
All
D7, D8
D13, D14
G17, H17
N17, P17
U13, U14
U7, U8
A17, B25,
D19
A21, C29, D21
A1, A11, D11
C3, L1, L4
A22, A26, A30,
B19, B32
CCO
CCO
CCO
CCO
CCO
CCO
A10, D7,
D13
A10, A16, B13,
C3, E5
B2, H4, K1
B2, D1, H1, M1,
R2
P4, U1, Y4
AA1, AA4, AJ3
V1, AA2, AD1,
AK1, AL2
AC8, AE2,
AF10
AH11, AL1,
AL11
AM2, AM15,
AN4, AN8, AN12
AC14,AC20,
AF17
AH21, AJ29,
AL21
AL31, AM21,
AN18, AN24,
AN30
V
, Bank 6
All
N4, P4
U26, W23,
AE25
AA28, AA31,
AL31
W32, AB33,
AF33, AK33,
AM32
CCO
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Production Product Specification
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Module 4 of 4
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Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 3: Virtex Pinout Tables (BGA) (Continued)
Pin Name
, Bank 7
Device
BG256
BG352
BG432
BG560
V
V
All
G4, H4
G23, K26,
N23
A31, L28, L31
C32, D33, K33,
N32, T33
CCO
, Bank 0
XCV50
A8, B4
... + A4
N/A
N/A
N/A
N/A
N/A
REF
(VREF pins are listed
incrementally. Connect all
pins listed for both the
required device and all
smaller devices listed in the
same package.)
XCV100/150
A16,C19,
C21
XCV200/300
XCV400
... + A2
N/A
... + D21
B19, D22, D24,
D26
N/A
N/A
... + C18
A19, D20,
D26, E23, E27
... + E24
... + E21
... + D29
N/A
Within each bank, if input
reference voltage is not
XCV600
XCV800
N/A
N/A
N/A
N/A
... + C24
... + B21
N/A
required, all V
general I/O.
pins are
REF
XCV1000
XCV50
N/A
N/A
V
, Bank 1
A17, B12
... + B15
N/A
N/A
REF
(VREF pins are listed
incrementally. Connect all
pins listed for both the
required device and all
smaller devices listed in the
same package.)
XCV100/150
B6, C9,
C12
N/A
N/A
XCV200/300
XCV400
... + B17
N/A
... + D6
A13, B7,
C6, C10
... + B15
N/A
N/A
A6, D7,
D11, D16, E15
... + D10
... + D13
... + E7
Within each bank, if input
reference voltage is not
required, all V
general I/O.
pins are
XCV600
XCV800
N/A
N/A
N/A
N/A
... + D10
... + B12
N/A
REF
XCV1000
XCV50
N/A
N/A
V
, Bank 2
C20, J18
... + F19
N/A
N/A
N/A
REF
(V
pins are listed
XCV100/150
E2, H2,
M4
N/A
N/A
REF
incrementally. Connect all
pins listed for both the
required device and all
smaller devices listed in the
same package.)
XCV200/300
XCV400
... + G18
N/A
... + D2
E2, G3,
J2, N1
N/A
N/A
... + R3
G5, H4,
L5, P4, R1
... + K5
Within each bank, if input
reference voltage is not
required, all V
general I/O.
pins are
XCV600
XCV800
XCV1000
N/A
N/A
N/A
N/A
N/A
N/A
... + H1
... + M3
N/A
REF
... + N5
... + B3
Module 4 of 4
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DS003-4 (v4.0) March 1, 2013
Production Product Specification
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 3: Virtex Pinout Tables (BGA) (Continued)
Pin Name
, Bank 3
Device
XCV50
BG256
M18, V20
... + R19
... + P18
BG352
N/A
BG432
N/A
BG560
N/A
V
REF
(V
pins are listed
XCV100/150
XCV200/300
R4, V4, Y3
... + AC2
N/A
N/A
REF
incrementally. Connect all
pins listed for both the
required device and all
smaller devices listed in the
same package.)
V2, AB4, AD4,
AF3
N/A
XCV400
N/A
N/A
... + U2
V4, W5,
AD3, AE5, AK2
... + AF1
... + AA4
... + AH4
N/A
Within each bank, if input
reference voltage is not
XCV600
XCV800
N/A
N/A
N/A
N/A
N/A
N/A
... + AC3
... + Y3
N/A
required, all V
general I/O.
pins are
REF
XCV1000
XCV50
N/A
V
, Bank 4
V12, Y18
N/A
REF
(V
pins are listed
XCV100/150
... + W15 AC12, AE5,
AE8,
N/A
N/A
REF
incrementally. Connect all
pins listed for both the
required device and all
smaller devices listed in the
same package.)
XCV200/300
XCV400
... + V14
... + AE4
AJ7, AL4, AL8,
AL13
N/A
N/A
N/A
... + AK15
AL7, AL10,
AL16, AM4,
AM14
Within each bank, if input
reference voltage is not
required, all V
general I/O.
pins are
XCV600
XCV800
N/A
N/A
N/A
N/A
N/A
N/A
... + AK8
... + AJ12
N/A
... + AL9
... + AK13
... + AN3
N/A
REF
XCV1000
XCV50
N/A
V
, Bank 5
V9, Y3
N/A
REF
(V
pins are listed
XCV100/150
... + W6 AC15, AC18,
AD20
N/A
N/A
REF
incrementally. Connect all
pins listed for both the
required device and all
smaller devices listed in the
same package.)
XCV200/300
XCV400
... + V7
... + AE23
AJ18, AJ25,
AK23, AK27
... + AJ17
N/A
N/A
N/A
AJ18, AJ25,
AL20, AL24,
AL29
Within each bank, if input
reference voltage is not
required, all V
general I/O.
pins are
REF
XCV600
XCV800
N/A
N/A
N/A
N/A
N/A
N/A
... + AL24
... + AH19
N/A
... + AM26
... + AN23
... + AK28
N/A
XCV1000
XCV50
N/A
V
, Bank 6
M2, R3
... + T1
N/A
REF
(V
pins are listed
XCV100/150
R24, Y26,
AA25,
N/A
N/A
REF
incrementally. Connect all
pins listed for both the
required device and all
smaller devices listed in the
same package.)
XCV200/300
XCV400
... + T3
N/A
... + AD26
V28, AB28,
AE30, AF28
N/A
N/A
... + U28
V29, Y32, AD31,
AE29, AK32
Within each bank, if input
reference voltage is not
required, all V
general I/O.
XCV600
XCV800
XCV1000
N/A
N/A
N/A
N/A
N/A
N/A
... + AC28
... + Y30
N/A
... + AE31
... + AA30
... + AH30
pins are
REF
DS003-4 (v4.0) March 1, 2013
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
9
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 3: Virtex Pinout Tables (BGA) (Continued)
Pin Name
, Bank 7
Device
XCV50
BG256
G3, H1
... + D1
BG352
N/A
BG432
N/A
BG560
N/A
V
REF
(V
pins are listed
XCV100/150
D26, G26,
L26
N/A
N/A
REF
incrementally. Connect all
pins listed for both the
required device and all
smaller devices listed in the
same package.)
XCV200/300
... + B2
... + E24
F28, F31,
J30, N30
N/A
Within each bank, if input
reference voltage is not
XCV400
N/A
N/A
... + R31
E31, G31, K31,
P31, T31
required, all V
general I/O.
pins are
REF
XCV600
XCV800
XCV1000
All
N/A
N/A
N/A
N/A
N/A
N/A
... + J28
... + M28
N/A
... + H32
... + L33
... + D31
GND
C3, C18,
D4, D5,
D9, D10,
D11,
D12,
D16,
D17, E4,
E17, J4,
J17, K4,
K17, L4,
L17, M4,
M17, T4,
T17, U4,
U5, U9,
U10,
A1, A2, A5,
A8, A14,
A19, A22,
A25, A26,
B1, B26, E1,
E26, H1,
A2, A3, A7, A9,
A14, A18, A23,
A25, A29, A30,
B1, B2, B30,
B31, C1, C31,
D16, G1, G31,
J1, J31, P1, P31,
T4, T28, V1,
V31, AC1, AC31,
AE1, AE31,
AH16, AJ1,
AJ31, AK1, AK2,
AK30, AK31,
A1, A7, A12,
A14, A18, A20,
A24, A29, A32,
A33, B1, B6, B9,
B15, B23, B27,
B31, C2, E1,
F32, G2, G33,
J32, K1, L2,
M33, P1, P33,
R32, T1, V33,
W2, Y1, Y33,
AB1, AC32,
H26, N1,
P26, W1,
W26, AB1,
AB26, AE1,
AE26, AF1,
AF2, AF5,
AF8, AF13,
AF19, AF22,
AD33, AE2,
AG1, AG32,
AH2, AJ33,
AL2, AL3, AL7,
AF25, AF26 AL9 AL14, AL18
AL23, AL25,
U11,
AL32, AM3,
U12,
U16,
U17, V3,
V18
AL29, AL30
AM7, AM11,
AM19, AM25,
AM28, AM33,
AN1, AN2, AN5,
AN10, AN14,
AN16, AN20,
AN22, AN27,
AN33
(1)
GND
All
All
J9, J10,
J11, J12,
K9, K10,
K11,K12,
L9, L10,
L11, L12,
M9, M10,
M11, M12
N/A
N/A
N/A
N/A
N/A
No Connect
N/A
C31, AC2, AK4,
AL3
Notes:
1. 16 extra balls (grounded) at package center.
Module 4 of 4
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DS003-4 (v4.0) March 1, 2013
Production Product Specification
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 4: Virtex Pinout Tables (Fine-Pitch BGA)
Pin Name
Device
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
FG256
N8
FG456
W12
Y11
A11
C11
AB2
U5
FG676
AA14
AB13
C13
E13
AD4
W7
FG680
AW19
AU22
D21
A20
AT37
AU38
AT35
E4
GCK0
GCK1
GCK2
GCK3
M0
R8
C9
B8
N3
M1
P2
M2
R3
Y4
AB6
D24
AA22
AB21
Y21
E23
F22
CCLK
D15
P15
R14
N15
C15
D14
E16
F15
G16
J16
M16
N16
N14
C13
B13
A15
B14
D3
B22
W20
Y19
V19
C21
D20
H22
H20
K20
N22
R21
T22
Y21
A20
C19
B20
A21
D3
PROGRAM
DONE
INIT
AT5
AU5
AU2
E3
BUSY/DOUT
D0/DIN
D1
C2
K24
K22
M22
R24
U23
V24
AB23
C22
E21
D22
C23
F5
P4
D2
P3
D3
R1
D4
AD3
AG2
AH1
AR4
B4
D5
D6
D7
WRITE
CS
D5
TDI
B3
TDO
TMS
TCK
C4
E36
C36
AV37
AU35
C4
C4
E6
DXN
DXP
R4
Y5
AB7
Y8
P4
V6
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Module 4 of 4
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R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)
Pin Name
Device
FG256
FG456
FG676
FG680
V
All
C3,C14,D4,
D13, E5,
E12, M5,
M12, N4,
N13, P3,
P14
E5, E18, F6,
G7, G20, H8, H19,
AD5, AD35,
CCINT
F17, G7, G8, G9, J9, J10, J11, J16, AE5, AE35, AL5,
G14, G15, G16, J17, J18, K9, K18,
AL35, AM5,
AM35, AR8,
AR9, AR15,
AR16, AR24,
AR25, AR31,
AR32, E8, E9,
E15, E16, E24,
E25, E31, E32,
H5, H35, J5,
J35, R5, R35,
T5, T35
H7, H16, J7,
J16, P7, P16,
R7, R16, T7, T8,
T9, T14, T15,
T16, U6, U17,
V5, V18
L9, L18, T9, T18,
U9, U18, V9, V10,
V11, V16, V17,
V18, W8, W19, Y7,
Y20
V
V
V
V
V
, Bank 0
, Bank 1
, Bank 2
, Bank 3
, Bank 4
All
All
All
All
All
E8, F8
E9, F9
F7, F8, F9, F10
G10, G11
H9, H10, H11,
H12, J12, J13
E26, E27, E29,
E30, E33, E34
CCO
CCO
CCO
CCO
CCO
F13, F14, F15,
F16, G12, G13
H15, H16, H17,
H18, J14, J15
E6, E7, E10,
E11, E13, E14
H11, H12
J11, J12
L9. M9
G17, H17, J17,
K16, K17, L16
J19, K19, L19,
M18, M19, N18
F5, G5, K5, L5,
N5, P5
M16, N16, N17,
P17, R17, T17
P18, R18, R19,
T19, U19, V19
AF5, AG5, AN5,
AK5, AJ5, AP5
T12, T13, U13,
U14, U15, U16,
V14, V15, W15,
W16, W17, W18
AR6, AR7,
AR10, AR11,
AR13, AR14
V
V
, Bank 5
, Bank 6
, Bank 7
All
All
All
L8, M8
J5, J6
T10, T11, U7,
U8, U9, U10
V12, V13,
W9,W10, W11,
W12
AR26, AR27,
AR29, AR30,
AR33, AR34
CCO
CCO
CCO
M7, N6, N7, P6,
R6, T6
P9, R8, R9, T8,
U8, V8
AF35, AG35,
AJ35, AK35,
AN35, AP35
V
V
H5, H6
G6, H6, J6, K6,
K7, L7
J8, K8, L8, M8,
M9, N9
F35, G35, K35,
L35, N35, P35
, Bank 0
XCV50
B4, B7
... + C6
... + A3
N/A
N/A
A9, C6, E8
... + B4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF
(VREF pins are listed
incrementally. Connect
all pins listed for both
the required device and
all smaller devices
listed in the same
package.)
XCV100/150
XCV200/300
XCV400
A12, C11, D6, E8,
G10
XCV600
N/A
N/A
... + B7
A33, B28, B30,
C23, C24, D33
Within each bank, if
input reference voltage
is not required, all V
pins are general I/O.
XCV800
N/A
N/A
N/A
N/A
... + B10
N/A
... + A26
... + D34
REF
XCV1000
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Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)
Pin Name
, Bank 1
Device
XCV50
FG256
B9, C11
... + E11
... + A14
N/A
FG456
N/A
FG676
N/A
FG680
N/A
V
REF
(VREF pins are listed
incrementally. Connect
all pins listed for both
the required device and
all smaller devices
listed in the same
package.)
XCV100/150
XCV200/300
XCV400
A18, B13, E14
... + A19
N/A
N/A
N/A
N/A
N/A
A14, C20, C21,
D15, G16
N/A
XCV600
N/A
N/A
... + B19
B6, B8, B18,
D11, D13, D17
Within each bank, if
input reference voltage
is not required, all V
pins are general I/O.
XCV800
N/A
N/A
N/A
N/A
... + A17
N/A
... + B14
... + B5
REF
XCV1000
V
, Bank 2
XCV50
F13, H13
... + F14
... + E13
N/A
N/A
F21, H18, K21
... + D22
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF
(V
pins are listed
XCV100/150
XCV200/300
XCV400
REF
incrementally. Connect
all pins listed for both
the required device and
all smaller devices
listed in the same
package.)
F24, H23, K20,
M23, M26
XCV600
N/A
N/A
... + G26
G1, H4, J1, L2,
V5, W3
Within each bank, if
input reference voltage
is not required, all V
pins are general I/O.
XCV800
N/A
N/A
N/A
N/A
... + K25
N/A
... + N1
... + D2
REF
XCV1000
V
, Bank 3
XCV50
K16, L14
... + L13
... + M13
N/A
N/A
N21, R19, U21
... + U20
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF
(V
pins are listed
XCV100/150
XCV200/300
XCV400
REF
incrementally. Connect
all pins listed for both
the required device and
all smaller devices
listed in the same
package.)
R23, R25, U21,
W22, W23
XCV600
N/A
N/A
... + W26
AC1, AJ2, AK3,
AL4, AR1, Y1
Within each bank, if
input reference voltage
is not required, all V
pins are general I/O.
XCV800
N/A
N/A
N/A
N/A
... + U25
N/A
... + AF3
... + AP4
REF
XCV1000
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Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)
Pin Name
Device
XCV50
FG256
P9, T12
... + T11
FG456
FG676
N/A
FG680
N/A
V
, Bank 4
N/A
REF
(V
pins are listed
XCV100/150
AA13, AB16,
AB19
N/A
N/A
REF
incrementally. Connect
all pins listed for both
the required device and
all smaller devices
listed in the same
package.)
XCV200/300
XCV400
... + R13
N/A
... + AB20
N/A
N/A
N/A
N/A
AC15, AD18,
AD21, AD22,
AF15
Within each bank, if
input reference voltage
XCV600
N/A
N/A
... + AF20
AT19, AU7,
AU17, AV8,
AV10, AW11
is not required, all V
REF
pins are general I/O.
XCV800
XCV1000
XCV50
N/A
N/A
N/A
N/A
... + AF17
N/A
... + AV14
... + AU6
N/A
V
, Bank 5
T4, P8
... + R5
... + T2
N/A
N/A
N/A
REF
(V
pins are listed
XCV100/150
XCV200/300
XCV400
W8, Y10, AA5
... + Y6
N/A
N/A
N/A
REF
incrementally. Connect
all pins listed for both
the required device and
all smaller devices
listed in the same
package.)
N/A
N/A
AA10, AB8, AB12,
AC7, AF12
N/A
XCV600
N/A
N/A
... + AF8
AT27, AU29,
AU31, AV35,
AW21, AW23
Within each bank, if
input reference voltage
XCV800
XCV1000
XCV50
N/A
N/A
N/A
N/A
... + AE10
N/A
... + AT25
... + AV36
N/A
is not required, all V
REF
pins are general I/O.
V
, Bank 6
J3, N1
... + M1
... + N2
N/A
N/A
N/A
REF
(V
pins are listed
XCV100/150
XCV200/300
XCV400
N2, R4, T3
... + Y1
N/A
N/A
N/A
REF
incrementally. Connect
all pins listed for both
the required device and
all smaller devices
listed in the same
package.)
N/A
N/A
AB3, R1, R4, U6,
V5
N/A
XCV600
N/A
N/A
... + Y1
AB35, AD37,
AH39, AK39,
AM39, AN36
Within each bank, if
input reference voltage
XCV800
N/A
N/A
N/A
N/A
... + U2
N/A
... + AE39
... + AT39
is not required, all V
REF
pins are general I/O.
XCV1000
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Virtex™ 2.5 V Field Programmable Gate Arrays
Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)
Pin Name
Device
XCV50
FG256
C1, H3
... + D1
... + B1
N/A
FG456
N/A
FG676
N/A
FG680
N/A
V
, Bank 7
REF
(V
pins are listed
XCV100/150
XCV200/300
XCV400
E2, H4, K3
... + D2
N/A
N/A
N/A
REF
incrementally. Connect
all pins listed for both
the required device and
all smaller devices
listed in the same
package.)
N/A
N/A
F4, G4, K6, M2,
M5
N/A
XCV600
N/A
N/A
... + H1
E38, G38, L36,
N36, U36, U38
Within each bank, if
input reference voltage
is not required, all V
pins are general I/O.
XCV800
N/A
N/A
N/A
N/A
... + K1
N/A
... + N38
... + F36
REF
XCV1000
GND
All
A1, A16, B2,
B15, F6, F7,
F10, F11,
G6, G7, G8,
G9, G10,
A1, A22, B2,
B21, C3, C20,
J9, J10, J11,
J12, J13, J14,
K9, K10, K11,
K12, K13, K14,
L9, L10, L11,
L12, L13, L14,
M9, M10, M11,
A1, A26, B2, B9,
B14, B18, B25,
C3, C24, D4, D23,
E5, E22, J2, J25,
K10, K11, K12,
K13, K14, K15,
K16, K17, L10,
L11, L12, L13,
L14, L15, L16,
L17, M10, M11,
M12, M13, M14,
M15, M16, M17,
N2, N10, N11,
N12, N13, N14,
N15, N16, N17,
P10, P11, P12,
P13, P14, P15,
P16, P17, P25,
R10, R11, R12,
R13, R14, R15,
R16, R17, T10,
T11, T12, T13,
T14, T15, T16,
T17, U10, U11,
U12, U13, U14,
U15, U16, U17,
V2, V25, AB5,
A1, A2, A3, A37,
A38, A39, AA5,
AA35, AH4,
AH5, AH35,
AH36, AR5,
G11, H7,
AR12, AR19,
AR20, AR21,
AR28, AR35,
AT4,AT12,AT20,
AT28, AT36,
AU1, AU3, AU20,
AU37, AU39,
AV1, AV2, AV38,
AV39, AW1,
H8,H9,H10,
J7, J8, J9,
J10, K6, K7,
K8, K9, K10, M12, M13, M14,
K11, L6, L7,
L10, L11,
R2, R15, T1,
T16
N9, N10, N11,
N12, N13, N14,
P9, P10, P11,
P12, P13, P14,
Y3, Y20, AA2,
AA21, AB1,
AW2, AW3,
AW37, AW38,
AW39, B1, B2,
B38, B39, C1,
C3, C20, C37,
C39, D4, D12,
D20, D28, D36,
E5, E12, E19,
E20, E21, E28,
E35, M4, M5,
M35, M36, W5,
W35, Y3, Y4, Y5,
Y35, Y36, Y37
AB22
AB22, AC4, AC23,
AD3, AD24, AE2,
AE9, AE13, AE18,
AE25, AF1, AF26
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Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)
Pin Name
No Connect
Device
FG256
FG456
FG676
FG680
XCV800
N/A
N/A
A2, A3, A15, A25,
B1, B6, B11, B16,
B21, B24, B26,
C1, C2, C25, C26,
F2, F6, F21, F25,
L2, L25, N25, P2,
T2, T25, AA2,
AA6, AA21, AA25,
AD1, AD2, AD25,
AE1, AE3, AE6,
AE11, AE14,
N/A
(No-connect pins are
listed incrementally. All
pins listed for both the
required device and all
larger devices listed in
the same package are
no connects.)
AE16, AE21,
AE24, AE26, AF2,
AF24, AF25
XCV600
XCV400
N/A
N/A
N/A
N/A
same as above
N/A
N/A
... + A9, A10, A13,
A16, A24, AC1,
AC25, AE12,
AE15, AF3, AF10,
AF11, AF13,
AF14, AF16,
AF18, AF23, B4,
B12, B13, B15,
B17, D1, D25,
H26, J1, K26, L1,
M1, M25, N1, N26,
P1, P26, R2, R26,
T1, T26, U26, V1
XCV300
XCV200
N/A
N/A
D4, D19, W4,
W19
N/A
N/A
N/A
... + A2, A6, A12,
B11, B16, C2,
D1, D18, E17,
E19, G2, G22,
L2, L19, M2,
N/A
M21, R3, R20,
U3, U18, Y22,
AA1,AA3,AA11,
AA16, AB7,
AB12, AB21,
XCV150
N/A
... + A13, A14,
C8, C9, E13,
F11, H21, J1, J4,
K2, K18, K19,
M17, N1, P1, P5,
P22, R22, W13,
W15, AA9,
N/A
N/A
AA10, AB8,
AB14
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Virtex™ 2.5 V Field Programmable Gate Arrays
Pinout Diagrams
The following diagrams, CS144 Pin Function Diagram,
page 17 through FG680 Pin Function Diagram, page 27,
illustrate the locations of special-purpose pins on Virtex
FPGAs. Table 5 lists the symbols used in these diagrams.
The diagrams also show I/O-bank boundaries.
Table 5: Pinout Diagram Symbols (Continued)
Symbol
Pin Function
❿, ❶, ❷
M0, M1, M2
➉, ➀, ➁,
➂, ➃, ➄, ➅,
➆
D0/DIN, D1, D2, D3, D4, D5, D6, D7
Table 5: Pinout Diagram Symbols
Symbol
Pin Function
B
D
P
I
DOUT/BUSY
✳
❄
General I/O
DONE
Device-dependent general I/O, n/c on
smaller devices
PROGRAM
INIT
V
V
CCINT
K
W
S
T
+
–
CCLK
v
Device-dependent V
devices
, n/c on smaller
CCINT
WRITE
O
R
r
V
CS
CCO
V
Boundary-scan Test Access Port
Temperature diode, anode
Temperature diode, cathode
No connect
REF
Device-dependent V , remains I/O on
REF
smaller devices
G
Ground
n
Ø, 1, 2, 3
Global Clocks
CS144 Pin Function Diagram
Bank 0
Bank 1
A
B
C
D
E
F
GO✳
3 2 ✳ V R T T O
A
✳✳
r
T O
V
RG GO K
B
C
D
E
F
✳
✳
✳
✳
T R V
G
WB
Bank 7
Bank 2
Bank 3
✳✳
✳
✳✳
✳
➉
✳
r
RGRO r S R
r
✳
R
G
✳
✳
G
R
✳
❿
O
✳
✳
G
G
➂
✳✳
✳✳✳
➁ ✳
✳
✳
➀
R
CS144GO V ✳
G
H
J
O V
G
H
J
✳
✳✳
(Top view)
R
✳R
✳
➄
R✳
➃
G
r
r
➆
✳
✳
➅
✳
K
L
✳✳✳Ø
✳
K
L
✳✳
❶
✳
Bank 6
GRGRGR R✳ P I
G
M
N
O
✳ V ✳ 1 ✳ V ✳ DO
M
N
✳
❷ ✳
✳
r
V O ✳ r GO
✳
✳
✳
Bank 5
Bank 4
Figure 1: CS144 Pin Function Diagram
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TQ144 Pin Function Diagram
❶
R
✳✳✳
G T
R
r
G
R
✳✳ ✳✳✳
GO
V
R
✳✳ ✳✳
G
r
G❿ O
✳✳
✳
✳
✳
✳
✳
1
2
O
T
❷ 108
107
106
105
✳
✳
✳
3
Bank 7
Bank 6
✳
✳
R
4
5
R 104
6
103
✳
✳
7
r
r 102
101
✳
8
✳
G
V
9
G 100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bank 0
Bank 5
V
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
✳
✳
R
✳
✳
R
✳
V
3
✳
V
1
TQ144
O
G
2
O
G
Ø
(Top view)
✳
✳
R
✳
✳
R
✳
✳
V
✳
✳
V
G
Bank 1
Bank 4
G
✳
✳
r
r
✳
✳
R
R
✳
✳
✳
✳
G
D
O
32 W
33
34
35
36
S
T
Bank 2
Bank 3
➃ R
➄ G➅ r
G
T
O K B
R
r
G➁
R
GO
V
R
✳
I P
➉
✳
✳
✳✳
✳✳
✳
✳
✳✳
✳
➀
➂
➆
Figure 2: TQ144 Pin Function Diagram
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Virtex™ 2.5 V Field Programmable Gate Arrays
PQ240/HQ240 Pin Function Diagram
T
G
R
r
G
V
G
r
3
G
R
r
O
V
r
R
r
W
T
T
✳
✳
✳
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
S G
O
r
r
O
r
V
O
2
r
G
G
r
G
1
3
G
O
Bank 0
Bank 1
179
T
K
➉
r
✳
B
✳
✳
G
177
175
173
✳
5
7
r
✳
✳
✳
R
r
G
9
11
13
R
171
169
✳
r
✳
r
r
✳
167
165
163
➀
O
➁
r
G
15
17
O
G
V
Bank 7
Bank 2
V
✳
✳
19
21
23
✳
r
161
159
✳
✳
✳
G
➂
r
G
✳
R
PQ240/HQ240
157
155
153
✳
R
25
27
✳
r
✳
✳
G
(Top view)
✳
✳
29
31
33
✳
O
G
O
151
149
Pins are shown staggered
for readability
✳
V
✳
r
r
V
✳
R
✳
r
147
145
143
✳
35
37
✳
R
➃
G
✳
G
✳
39
41
43
✳
r
141
139
✳
✳
Bank 6
Bank 3
✳
V
➄
O
V
137
135
133
O
45
47
G
G
✳
r
➅
r
r
r
49
51
53
✳
R
131
129
✳
G
✳
G
R
✳
✳
✳
127
125
123
r
55
57
r
✳
✳
✳
I
✳
➆
❶
Bank 5
Bank 4
59
G
P
O
121
❿
r
R
r
O
r
R
G
V
O
Ø
r
G
V
G
r
G
D
❷
✳
✳
✳
G
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳ ✳ ✳
r
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
G
O
r
G
V
r
1
G
R
r
O
r
R
Figure 3: PQ240/HQ240 Pin Function Diagram
DS003-4 (v4.0) March 1, 2013
Production Product Specification
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1-800-255-7778
Module 4 of 4
19
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
BG256 Pin Function Diagram
r ✳
✳ r ✳
✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
✳
A
B
C
D
E
F
G
H
J
T
r
R
2
3
V
R
W T
A
B
C
D
E
F
G
H
J
✳
✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
✳ r
✳
R
✳ ✳ ✳ ✳ ✳ ✳
R
r
S K
T G
✳ ✳
➉
✳ ✳
G
R
✳
✳ ✳ ✳
r
T G G V O O G G G G O O V G G B
✳ ✳ ➀
✳
r
G
V
G
V
O
O
Bank 0
Bank 1
✳ ✳ ✳
✳ ✳
✳
r
➁ ✳
R O
BG256
✳ ✳
✳ ✳ ✳
✳ ✳ ✳
➂ ✳
✳ ✳ ✳
R
O
G
G
Bank 7
Bank 6
Bank 2
Bank 3
G G G G
G G G G
G G G G
G G G G
G R
✳ ✳ ✳
✳ ✳
K
L
G
K
L
✳ ✳
➃ ✳
V G
G V
G R
✳
✳
M
N
P
R
T
U
V
W
Y
R
G
O
O
M
N
P
R
T
U
V
W
Y
✳ ✳ ✳
✳ ✳ ✳
✳ ✳ ✳
➄ ✳
O
O
V
(Top View)
r
✳ ✳
✳ ✳
r
✳ ✳ ➅
R V
✳ r
r
✳ ✳
G
G
Bank 5
Bank 4
✳ ✳
❶ G G V O O G G G G O O V G G I
✳ ✳
✳ ✳ r ✳
r
✳ ✳ ✳ ✳ ✳ ✳
✳
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳ r ✳ ✳ ✳
➆
D
✳
G +
✳ ✳
R V
R
G
✳ ✳ ✳
R
✳
P
✳
❿
❷ –
r
✳
✳ ✳ ✳ ✳ ✳ ✳
1 Ø R
R
DS003_18_100300
Figure 4: BG256 Pin Function Diagram
Module 4 of 4
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R
Virtex™ 2.5 V Field Programmable Gate Arrays
BG352 Pin Function Diagram
✳ ✳
✳ ✳
R
✳ ✳ ✳ ✳
✳
✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳ ✳
✳
✳
✳
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳
✳ ✳
G
A
B
C
D
E
G G
G
✳ ✳
G
O
G
2
V
R O
V
G V
G G
O G
✳ ✳
A
B
C
D
E
G O T
✳ ✳
✳
✳ ✳
✳
✳
✳ ✳ ✳ ✳
✳ ✳ ✳ ✳
✳
✳
✳ ✳
T
K S
R
✳ ✳
R
R
O
R
r
➉
✳
✳ ✳
✳
r
r
T W r O
V
V O 3
T
R
G
✳
✳ ✳ ✳ ✳
✳
G R
B
✳ ✳ ✳ ✳
F
F
Bank 1
Bank 0
➀ ✳ ✳ ✳
✳
O
✳ ✳
✳ ✳ ✳
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
O
R
G
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
G R
✳ ✳ ➁ ✳
✳
✳ ✳ ✳
✳ ✳
V
✳ ✳
✳ ✳ ✳
O
V
V
O
Bank 2
Bank 7
Bank 6
✳ ✳
V R
✳ ✳ ➂
✳ ✳ ✳ ✳
✳ ✳ ✳
O
R
✳ ✳ ✳
G
BG352
✳
✳ ✳ ➃
✳
(Top View)
✳ ✳
V
O
R
V G
✳ ✳
V R
✳ ✳ ✳ ✳
✳ ✳ ✳
✳ ✳ ➄
V
✳ ✳ ✳
✳
O
✳ ✳ ➅
O
✳ ✳
Bank 3
R
✳ ✳
V
✳ ✳
G V
✳ ✳
O
G
R
✳
✳ ✳ ✳
✳ ✳
❶ ✳ ✳
R O
✳ ✳ ✳ ✳
R
AA
Bank 4
Bank 5
✳ ✳ ✳
➆
G
✳
✳
G AB
✳ ✳ ✳
✳
✳
✳
✳ ✳
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳
✳ ✳ ❷ ✳ ✳ ✳
❿ ✳
r
r
P
O
V
R
O R
R
O
R
AC
AD
✳ ✳
I D
–
✳
✳ ✳
✳ ✳
✳ ✳ ✳ ✳
✳
✳ ✳ ✳ ✳
✳
✳ ✳ ✳
✳ ✳
G
G O
G G
r R
✳ ✳
R
G
Ø V
G 1
V
G
r + O G AE
✳ ✳
✳
✳
G
O V
V O
G G AF
DS003_19_100600
Figure 5: BG352 Pin Function Diagram
DS003-4 (v4.0) March 1, 2013
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
21
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
BG432 Pin Function Diagram
✳ ✳ ✳
✳ ✳
✳
✳
✳
✳ ✳
✳
✳ ✳ ✳ ✳
r V
✳ ✳ ✳
✳
✳
✳
✳ ✳
✳ ✳ ✳
G
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
O G G
G G T W
G
R
G V O
✳ ✳ ✳ ✳
R G
✳ ✳
2 V G
✳ ✳ ✳
O
r
G
V
G G O
✳ ✳ ✳
V G G
A
B
C
D
E
F
G
H
J
r
r
✳ ✳ ✳
R
➉
✳ ✳
✳
✳ ✳
✳ ✳ ✳
✳ ✳ ✳ ✳
✳
G
✳ ✳
G
O T
R V
✳ ✳ ✳ ✳
R
r O
V
✳ ✳ ✳ ✳
r
O
✳
✳
✳
B K S
✳ ✳
G 3
O R
Bank 0
R
R
T T
✳
✳ ✳ ✳ ✳
✳
✳ ✳ ✳
R
✳ ✳ ✳
V
G
R
V R
Bank 1
✳
✳
✳ ✳ ✳
R
G
✳ ✳ ✳ ✳
r
✳ ✳
✳
G R
✳ ➁
r
R G
✳ ✳
➀
O
✳
✳
O
r
V
V
K
L
Bank 2
Bank 7
✳ ✳
✳ ✳
✳ ✳ ✳
O
✳ ✳
O
r
M
N
P
R
T
U
V
W
Y
✳ ✳
✳ ✳ ➂
✳
✳
G
r
R V
V R
✳ ✳ ✳
✳ ✳ ✳
G
✳ ✳
✳
r
BG432
✳ ✳
(Top View)
✳ ✳
✳ ✳ ✳
V
G
G V
r
R
✳ ✳ ✳
✳ ✳
✳
✳ ✳
✳ ➃
✳ ✳
r
✳ ✳
V
W
Y
G R
G
V
✳
✳
✳ ✳
V
✳
O
R
✳
R
r
r
✳ ✳
✳ ✳
➅
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
O
➄
G
O
R
r
O AA
✳
✳
V
V
AB
✳ ✳
G AC
Bank 3
Bank 6
✳
r
✳ ✳ ✳
✳ ✳ ✳ ✳
✳
✳ ✳ ✳
R
✳ ✳ ✳ ✳
AD
✳ ✳ ✳
✳
G
V
V R G AE
✳
R
AF
AG
Bank 4
Bank 5
✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ➆
✳ ✳
✳ ✳ ✳
✳ ✳
✳ ✳ ✳ ✳
✳ ✳ ✳
✳ ✳
✳
✳ ✳
R
✳ ✳
P D
✳ ✳ ✳
✳ ✳ ✳ ✳ ✳
V
✳ ✳
O
G
r
O
V
– ❿ ❶ AH
✳
✳ ✳
✳
❷ O G AJ
G I O
G G
R
V
r
V r R
✳ ✳
✳ ✳ ✳ ✳
✳
✳
✳ ✳
V
✳ ✳
✳ ✳ ✳
✳
r
V
r 1
✳
V R
✳
R
+ G G AK
✳ ✳ ✳
G r G G G O AL
Ø
✳ ✳
✳
✳
O G G R
G R G
O
R G
G
O
DS003_21_100300
Figure 6: BG432 Pin Function Diagram
Module 4 of 4
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R
Virtex™ 2.5 V Field Programmable Gate Arrays
BG560 Pin Function Diagram
✳ ✳ ✳
✳ ✳
✳ ✳
G
✳
✳ ✳
✳
✳
✳
G
✳
✳
✳ ✳ ✳
✳ ✳
✳
G O
A
B
C
D
E
G S
G O r
R G
G
O
G
G
O 3 G R G V O
✳ ✳ ✳ ✳ ✳
G
O
G G
G O T
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
✳ ✳
✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
V O V G
V O
G V
✳
O
G
✳
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳
G O K
✳ ✳
✳ ✳ ➉
V
V
n O
r
R
✳ ✳
✳
✳
✳ ✳
✳ ✳
✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳
✳ ✳
✳
✳
✳
✳
✳ ✳
B T W R
r R
✳ ✳
r
✳ ✳
R 2
R
R
✳ ✳
r
T
O
✳
O T r
V
V
R
r
R r
Bank 0
R
✳ ✳ ✳
✳ ✳
✳ ✳ ✳
✳ ✳
✳
G
✳
✳
F
V
G
✳
r
Bank 1
✳
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
G
✳ ✳
R
✳
R
✳
✳ ✳ ✳
✳
O
V
R
V
✳ ✳ ✳ ✳
✳ ➀ ✳
G
✳ ✳
G
✳
r
R V O
Bank 2
Bank 7
✳ ➁
✳ ✳ ✳ ✳
✳ ✳ ✳ ✳
G
R
✳ ✳
r
G
O V
✳
O
V
V
✳ ✳ ✳
✳ ✳
r
V
✳ ✳
✳ ➂
✳
✳ ✳ ✳
✳
G
✳
G
R O
R
R
G
✳
O
✳ ✳ ✳
✳ ✳
BG560
✳ ✳ ✳ ✳
(Top View)
G
✳ ✳ ✳ ✳
R
✳
✳ ✳ ✳
G
V
✳
R
V
✳ ✳ ✳
U
V
W
Y
AA
✳ ✳
G
O
✳
R
✳ ➃
R
✳ ✳ ✳
✳
O
✳ ✳ ✳
✳ ✳
✳
✳ ✳ ✳
G V
V R G
✳ ✳ ✳
✳
✳
✳
✳ ✳ ➄
AA
AB G V
O
r
r
V O AB
✳
✳ ➅ ✳
✳ ✳
✳ ✳ ✳
✳ ✳
✳
AC
n
G
AC
Bank 3
Bank 6
AD O V R
R V G AD
✳
✳ ✳
✳ ✳ ✳ ✳
✳
✳ ✳ ✳ ✳
✳ ✳
r AE
AE
AF
G
R
R
r
O AF
✳
✳ ✳
r
✳ ✳
✳
r
❿ ✳ ✳ ✳
✳
AG
AH
AJ
G
✳
V
✳
V G
✳ ✳ ✳
AG
AH
Bank 4
✳ ✳ ✳ ✳ ✳ ✳ ✳
Bank 5
✳ ✳ ✳ ✳ ✳ ✳
G
I
✳ ✳ ✳ ➆
✳
✳ ✳ ✳
✳ ✳ ✳
✳ ✳
✳ ✳ ✳ ✳ ✳ ✳ ✳
D
✳ ✳ ✳
V
r
1 R
V
R
+
G AJ
✳ ✳
✳
✳ ✳ ✳
✳ ✳
✳ ✳
❶ ✳
AK O R
n
✳ ✳ ✳
V
V
V
R
✳
G
r – R O AK
✳
✳
✳ ✳ ✳
✳
✳
O
✳
✳
✳ ✳ ✳
✳ ✳
G r
✳
✳
✳ ✳ ✳
✳
AL
O n
AM P O G R
AN G G r O G
R
G
✳ ✳
r R
V
R Ø
V
R
V
✳
G
R
O G
AL
O G AM
✳ ✳
✳ ✳
✳
✳ ✳ ✳
✳
G
✳
R O
G
G
✳ ✳
✳
✳
✳
✳
✳ ❷
O
G
O
G
G
O
G r O V
O G AN
DS003_22_100300
Figure 7: BG560 Pin Function Diagram
DS003-4 (v4.0) March 1, 2013
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
23
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
FG256 Pin Function Diagram
Bank 0
Bank 1
G r
✳ ✳✳✳✳✳✳✳✳✳✳
r T G
A
B
C
D
E
F
A
B
C
D
E
F
r G R
R 3 R
S T G
✳✳✳
✳ ✳✳
✳
✳
✳
➀
✳
➂
R V T r
2 R W VB
V K
✳
✳ ✳✳ ✳ ✳
Bank 7
Bank 6
Bank 2
Bank 3
r T V
✳
✳✳✳✳✳✳✳✳
➉
✳✳
V
OO r V r
✳✳✳✳ ✳✳
✳
GGOOGG R r
➁
✳✳✳✳✳
✳
GGGGG
G
H
J
G
H
J
✳✳✳✳✳
G✳✳✳✳
R OOGGGGOOR
✳✳ ✳
✳✳✳
R OOGGGGOO
➃
✳✳ ✳
✳✳✳
✳✳✳✳
GGGGGG
R
K
L
K
L
✳✳✳✳✳
✳✳✳✳✳
GGOOGG r R
✳
✳✳
r
V
OO
Ø
V r
M
N
P
R
T
➄
➅
✳
M
N
P
R
T
✳✳✳ ✳✳
✳✳
✳✳
➆
V P
R r V
V I
❿
✳✳✳ ✳✳✳✳
V +
R R
❶
✳
✳✳✳
✳✳✳✳
G – r
1
r DG
❷
✳
✳✳ ✳✳✳✳
✳
G r R
r R
G
✳ ✳✳✳✳✳✳
✳✳✳
Bank 5
Bank 4
FG256
(Top view)
Figure 8: FG256 Pin Function Diagram
Module 4 of 4
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1-800-255-7778
DS003-4 (v4.0) March 1, 2013
Production Product Specification
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
FG456 Pin Function Diagram
Bank 0
Bank 1
G
✳ ✳ ✳✳✳✳✳✳❅ ✳ ✳✳❅ ✳✳✳
R 2
❅ ✳✳✳❅ ✳✳ ✳ ❅ ❅ ❅ ✳✳✳
R r WT G
A
B
A
B
G
✳❅
r
R
✳ ✳❅ ❅ ✳ ✳✳✳✳✳✳✳
T G K
G T R 3
✳✳✳✳✳✳✳✳✳✳✳✳✳❅
S G B
C
D
E
C
D
E
✳
r T n
n
r
➉
✳
Bank 7
Bank 2
❅
R
V
R
R
V
✳ ✳✳ ✳✳ ✳✳✳✳❅ ✳✳❅ ❅ ✳✳✳
V OOOO
OOOO V
R
✳✳✳ ✳
✳✳✳✳❅
F
F
✳✳✳✳✳
✳❅ ✳✳✳
❅ ✳
O V V V OOOO V V V O
G
H
J
G
H
J
R O V
V OR
✳ ❅
➁
✳✳✳ ✳
❅ ✳✳❅ ✳
➀
O V GGGGGG V O
OO GGGGGG OO
O GGGGGG O
✳✳✳✳✳
R
✳
R
K
➂
K
✳❅ ✳✳
❅ ❅
✳✳❅ ✳✳✳
L
L
✳❅ ✳✳✳✳
O GGGGGG O
M
N
P
M
N
P
✳❅ ✳✳✳✳
❅ ✳✳✳❅ ✳
R
❅ ✳✳✳
❅ ✳✳✳❅
OO GGGGGG OO
O V GGGGGG V O
R
➃
✳✳✳
✳✳✳✳❅
R O V
V O R
➄
✳ ❅ ❅
✳✳✳✳
R
T
R
T
✳✳❅ ✳
R
O V V V OOOO V V V O
➅
✳
✳✳ ✳✳
V OOOO
OOOO V
✳✳✳✳✳✳✳✳✳✳✳
r R
U
V
❶
V +
U
V
✳✳❅ ✳
✳✳✳✳
n
✳✳
❅ ✳
V I
✳✳✳
Bank 6
Bank 3
R
✳✳✳
Ø
n P
W
Y
W
Y
✳✳✳ ✳✳✳ ✳✳✳ ❅ ✳❅ ✳✳✳
✳✳
r
G – r
R 1
DG
✳✳✳✳✳✳✳
➆
❷
✳
G
❅
R
R
G
AA
AB
AA
AB
❅ ❅ ✳ ✳✳✳❅ ❅ ❅ ✳ ✳✳❅ ✳✳✳✳ ✳
G
R
✳✳✳✳ ❅❅ ✳✳✳❅ ✳❅ ✳ ✳✳
R r
G
❅
❿
Bank 5
Bank 4
FG456
(Top view)
Figure 9: FG456 Pin Function Diagram
Notes:
Packages FG456 and FG676 are layout compatible.
DS003-4 (v4.0) March 1, 2013
Production Product Specification
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1-800-255-7778
Module 4 of 4
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Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
FG676 Pin Function Diagram
Bank 0
Bank 1
✳ ✳ ✳ ✳ ✳
❄
❄
✳
n
R
❄
❄
2
❄
✳ ✳ ✳ ✳ ✳ ✳
❄
n
G
K
A
B
C
D
E
G
n
n
❄
n
G
n
n
✳
R
❄
✳
R
G
n
❄
r
❄
n
G
n
G
n
n
A
B
C
D
E
❄
✳
✳
✳
✳ ✳
n
n
r
G
r
✳ ✳ ✳ ✳ ✳ ✳ ✳
n
G
r
✳ ✳ ✳ ✳ ✳ ✳
G
R
✳ ✳ ✳ ✳ ✳ ✳
R W T
✳ ✳
✳
G
T
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
❄
✳
G
R
T
n
R
✳ ✳ ✳ ✳ ✳ ✳ ✳
T
G
➉
G
B
✳
✳ ✳ ✳ ✳
✳
✳ ✳ ✳ ✳
✳ ✳ ✳
R
3
S
n
✳
✳
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳
Bank 7
F
n
R
R
R
n
F
Bank 2
✳ ✳ ✳
✳ ✳
✳
V
✳ ✳ ✳ ✳ ✳
✳ ✳ ✳
✳ ✳ ✳ ✳ ✳
V
✳
G
H
J
K
L
M
N
P
R
T
V
R
R
r
G
H
J
K
L
M
N
P
R
T
✳ ✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳
✳ ✳
✳ ✳ ✳ ✳ ✳
R
✳ ✳ ✳ ✳ ✳
❄
✳
❄
✳
R
❄
❄
❄
❄
❄
r
❄
O O O O
O O O O
V
O
O
O
G
✳ ✳ ✳ ✳
O
O
O
V
V
V
V
V
O O O O
V
V
V
V
V
G
r
✳
✳
✳
➁ ➀
✳ ✳ ✳ ✳ ✳
r
R
✳ ✳ ✳ ✳ ✳
G G G G G G G G
G G G G G G G G
R
❄
❄
❄
❄
R
❄
✳
n
R
G
n
❄
n
r
n
❄
n
G
R
n
r
✳ ✳
✳ ✳
✳
R
R
O O G G G G G G G G O O
➂
✳ ✳
✳ ✳ ✳
✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
O G G G G G G G G O
O G G G G G G G G O
✳
✳ ✳ ✳
R
✳ ✳ ✳ ✳ ✳
R
O O G G G G G G G G O O
➃
✳ ✳ ✳ ✳ ✳
O
O
O
V
V
V
G G G G G G G G
G G G G G G G G
V
V
V
O
O
O
✳ ✳ ✳
✳
✳
✳
✳
U
R
R
U
➄
✳ ✳ ✳ ✳
❄
✳ ✳
✳ ✳
✳
V
G
R
V
V
O O O O
✳ ✳
V
V
G
V
➅
✳ ✳ ✳ ✳ ✳ ✳
✳ ✳
✳ ✳
R
Bank 6
W
V
O O O O
O O O O
V
R
r
W
Bank 3
❶
✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳
Y
r
V
V
I
Y
+
✳ ✳ ✳
✳
✳ ✳ ✳
✳
✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
✳ ✳
✳
n
AA
AB
AC
AD
AE
AF
n
n
R
0
n
P
AA
AB
AC
AD
AE
AF
✳ ✳
-
R
✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳ ✳
✳ ✳ ✳
R
G
R
R
1
D G
❷
✳ ✳
➆
G
✳
❄
✳ ✳
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
R
✳
❄
✳
✳
G
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳ ✳
✳ ✳
n
n
G
n
G
n
G
R
R
n
R
G
n
n
n
G
n
❿
✳ ✳
✳ ✳
❄
❄
✳
✳ ✳
n
❄
n
✳ ✳ ✳ ✳
G
r
n
G
n
n
G
n
✳
❄
❄
❄
❄
❄
❄
✳
✳ ✳ ❄
r
r
R
R
r
G
Bank 5
Bank 4
FG676
(Top view)
fg676a
Figure 10: FG676 Pin Function Diagram
Notes:
Packages FG456 and FG676 are layout compatible.
Module 4 of 4
26
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1-800-255-7778
DS003-4 (v4.0) March 1, 2013
Production Product Specification
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
FG680 Pin Function Diagram
Bank 1
Bank 0
A
B
C
G
G
G
G
G
G
T
✳
W
T
✳
r
✳
R
✳
✳
O
✳
✳
✳
✳
O
✳
R
✳
✳
V
✳
✳
✳
✳
V
✳
✳
✳
✳
O
✳
✳
✳
R
O
✳
✳
✳
G
G
✳
✳
✳
R
O
✳
r
✳
✳
✳
✳
V
✳
✳
✳
✳
V
✳
✳
✳
R
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
G
3
✳
✳
✳
2
✳
✳
✳
✳
✳
✳
✳
R
✳
✳
✳
✳
R
✳
V
✳
✳
✳
✳
V
r
✳
✳
✳
✳
O
✳
R
✳
G
G
✳
✳
✳
✳
O
✳
R
✳
✳
O
✳
✳
✳
✳
V
✳
✳
✳
✳
V
R
✳
✳
R
O
✳
✳
✳
r
✳
✳
✳
✳
✳
T
G
✳
G
G
G
✳
G
G
G
A
B
C
✳
G
G
G
✳
✳
✳
O
G
✳
✳
✳
O
➉
r
D
E
F
G
H
J
✳
✳
✳
R
✳
R
✳
✳
✳
B
✳
✳
✳
✳
✳
✳
G
K
✳
✳
R
✳
✳
✳
S
G
O
O
V
V
O
O
✳
G
O
O
V
V
O
O
G
T
r
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
✳
R
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
D
E
F
G
H
J
✳
✳
✳
✳
✳
✳
R
G
O
Bank 2
Bank 7
K
L
K
L
M
N
P
R
T
✳
r
✳
✳
✳
✳
✳
✳
✳
✳
G
G
O
O
V
G
O
O
V
G
R
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
r
✳
✳
✳
✳
✳
✳
M
N
P
R
T
✳
✳
✳
✳
✳
R
➁ ➀
✳
✳
✳
✳
✳
✳
➂
✳
✳
V
V
U
✳
✳
U
V
W
Y
✳
✳
R
✳
✳
✳
✳
✳
✳
R
G
✳
✳
✳
G
✳
R
G
G
G
✳
G
G
G
✳
✳
G
✳
✳
✳
G
✳
✳
✳
✳
✳
✳
✳
✳
✳
V
W
Y
FG680
Top View)
AA
AA
(
AB
AC
AD
AE
AF
AG
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
✳
➄
✳
✳
➃
✳
r
✳
✳
✳
✳
✳
✳
✳
✳
V
V
O
O
R
✳
V
V
O
O
✳
✳
✳
✳
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
r
AB
AC
AD
AE
AF
AG
Bank 7
Bank 2
✳
✳
✳
AH
AJ
AK
AL
AM
AN
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
G
✳
✳
R
✳
✳
r
G
O
O
V
G
O
O
V
G
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
R
✳
R
✳
R
✳
✳
✳
AH
AJ
AK
AL
AM
AN
➅
✳
✳
✳
✳
✳
✳
V
V
O
O
G
O
O
G
Bank 3 AP
AP Bank 6
AR
AT
R
O
O
V
V
O
O
G
G
O
O
V
V
✳
✳
✳
✳
G
R
G
G
G
✳
✳
✳
✳
V
V
r
O
O
R
G
G
O
O
V
V
O
O
AR
AT
➆
✳
✳
✳
G
P
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
G
✳
r
❷
❿
AU
AV
G
G
G
I
G
✳
G
✳
✳
✳
D
✳
✳
r
R
✳
✳
✳
R
✳
✳
✳
✳
✳
R
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
r
✳
✳
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
0
G
✳
✳
✳
✳
R
1
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
R
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
✳
G
G
G
G
AU
AV
❶
G
G
+
R
✳
G
G
✳
✳
r
-
AW
✳
✳
G
AW
Bank 4
Bank 5
fg680_12a
Note: AA3, AA4, and AB2 are in Bank 2
Note: AA37 is in Bank 7
Figure 11: FG680 Pin Function Diagram
DS003-4 (v4.0) March 1, 2013
Production Product Specification
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1-800-255-7778
Module 4 of 4
27
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Revision History
Date
11/98
Version
1.0
Revision
Initial Xilinx release.
01/99-02/99
05/99
1.2-1.3
1.4
Both versions updated package drawings and specs.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
05/99
1.5
07/99
1.6
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99
01/00
01/00
03/00
1.7
1.8
1.9
2.0
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, "0" hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added T
parameter, changed T
to T
.
IJITCC
OJIT
OPHASE
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for V
in CS144 package on p.43.
CCO
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00
05/00
09/00
2.1
2.2
2.3
Modified "Pins not listed..." statement. Speed grade update to Final status.
Modified Table 18.
•
Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under IOB Input Switching Characteristics.
Added values to table under CLB SelectRAM Switching Characteristics.
Corrected pinout info for devices in the BG256, BG432, and BG560 pkgs in Table 18.
Corrected BG256 Pin Function Diagram.
Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Converted file to modularized format. See section Virtex Data Sheet, below.
Corrected pinout information for FG676 device in Table 4. (Added AB22 pin.)
•
•
•
•
•
•
•
10/00
2.4
2.5
04/02/01
04/19/01
07/19/01
2.6
2.7
•
•
•
Clarified V
pinout information and added AE19 pin for BG352 devices in Table 3.
CCINT
Changed pinouts listed for BG352 XCV400 devices in banks 0 thru 7.
Changed pinouts listed for GND in TQ144 devices (see Table 2).
07/19/02
03/01/13
2.8
4.0
The products listed in this data sheet are obsolete. See XCN10016 for further information.
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
•
DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
•
•
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
•
Module 4 of 4
28
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1-800-255-7778
DS003-4 (v4.0) March 1, 2013
Production Product Specification
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