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Virtex™ 2.5 V

Field Programmable Gate Arrays

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Product Specification

Features

•

Fast, high-density Field Programmable Gate Arrays

•

Supported by FPGA Foundation™ and Alliance

Development Systems

-

Densities from 50k to 1M system gates

System performance up to 200 MHz

66-MHz PCI Compliant

-

Complete support for Unified Libraries, Relationally

Placed Macros, and Design Manager

-

Wide selection of PC and workstation platforms

Hot-swappable for Compact PCI

SRAM-based in-system configuration

•

Multi-standard SelectIO™ interfaces

-

Unlimited re-programmability

Four programming modes

-

16 high-performance interface standards

Connects directly to ZBTRAM devices

•

0.22 μm 5-layer metal process

100% factory tested

Built-in clock-management circuitry

-

Four dedicated delay-locked loops (DLLs) for

advanced clock control

Description

-

Four primary low-skew global clock distribution

nets, plus 24 secondary local clock nets

The Virtex FPGA family delivers high-performance,

high-capacity programmable logic solutions. Dramatic

increases in silicon efficiency result from optimizing the new

architecture for place-and-route efficiency and exploiting an

aggressive 5-layer-metal 0.22 μm CMOS process. These

advances make Virtex FPGAs powerful and flexible alterna-

tives to mask-programmed gate arrays. The Virtex family

comprises the nine members shown in Table 1.

•

Hierarchical memory system

-

LUTs configurable as 16-bit RAM, 32-bit RAM,

16-bit dual-ported RAM, or 16-bit Shift Register

Configurable synchronous dual-ported 4k-bit

RAMs

Fast interfaces to external high-performance RAMs

Flexible architecture that balances speed and density

-

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

Internal 3-state bussing

Building on experience gained from previous generations of

FPGAs, the Virtex family represents a revolutionary step

forward in programmable logic design. Combining a wide

variety of programmable system features, a rich hierarchy of

fast, flexible interconnect resources, and advanced process

technology, the Virtex family delivers a high-speed and

high-capacity programmable logic solution that enhances

design flexibility while reducing time-to-market.

-

IEEE 1149.1 boundary-scan logic

Die-temperature sensor diode

Table 1: Virtex Field Programmable Gate Array Family Members

Maximum

Block RAM

Bits

Maximum

SelectRAM+™ Bits

Device

System Gates

CLB Array

Logic Cells

Available I/O

XCV50

57,906

16x24

1,728

180

260

284

316

404

512

32,768

40,960

49,152

57,344

65,536

81,920

98,304

114,688

131,072

24,576

38,400

55,296

75,264

98,304

153,600

221,184

301,056

393,216

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

108,904

20x30

2,700

164,674

24x36

3,888

236,666

28x42

5,292

322,970

32x48

6,912

468,252

40x60

10,800

15,552

21,168

27,648

661,111

48x72

888,439

56x84

1,124,022

64x96

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Virtex™ 2.5 V Field Programmable Gate Arrays

Xilinx thoroughly benchmarked the Virtex family. While per-

formance is design-dependent, many designs operated

internally at speeds in excess of 100 MHz and can achieve

200 MHz. Table 2 shows performance data for representa-

tive circuits, using worst-case timing parameters.

Virtex Architecture

Virtex devices feature a flexible, regular architecture that

comprises an array of configurable logic blocks (CLBs) sur-

rounded by programmable input/output blocks (IOBs), all

interconnected by a rich hierarchy of fast, versatile routing

resources. The abundance of routing resources permits the

Virtex family to accommodate even the largest and most

complex designs.

Table 2: Performance for Common Circuit Functions

Function

Bits

Virtex -6

Register-to-Register

Virtex FPGAs are SRAM-based, and are customized by

loading configuration data into internal memory cells. In

some modes, the FPGA reads its own configuration data

from an external PROM (master serial mode). Otherwise,

the configuration data is written into the FPGA (Select-

MAP™, slave serial, and JTAG modes).

16

64

5.0 ns

7.2 ns

Adder

Pipelined Multiplier

8 x 8

5.1 ns

6.0 ns

16 x 16

The standard Xilinx Foundation™ and Alliance Series™

Development systems deliver complete design support for

Virtex, covering every aspect from behavioral and sche-

matic entry, through simulation, automatic design transla-

tion and implementation, to the creation, downloading, and

readback of a configuration bit stream.

Address Decoder

16

64

4.4 ns

6.4 ns

16:1 Multiplexer

Parity Tree

5.4 ns

9

4.1 ns

5.0 ns

6.9 ns

18

36

Higher Performance

Virtex devices provide better performance than previous

generations of FPGA. Designs can achieve synchronous

system clock rates up to 200 MHz including I/O. Virtex

inputs and outputs comply fully with PCI specifications, and

interfaces can be implemented that operate at 33 MHz or

66 MHz. Additionally, Virtex supports the hot-swapping

requirements of Compact PCI.

Chip-to-Chip

HSTL Class IV

200 MHz

180 MHz

LVTTL,16mA, fast slew

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Virtex™ 2.5 V Field Programmable Gate Arrays

Virtex Device/Package Combinations and Maximum I/O

Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)

Package

CS144

TQ144

PQ240

HQ240

BG256

BG352

BG432

BG560

FG256

FG456

FG676

FG680

XCV50

94

XCV100

94

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800 XCV1000

98

166

316

180

176

180

176

180

260

180

260

316

404

316

404

512

176

260

176

284

312

404

444

512

444

512

Virtex Ordering Information

Example:

XCV300 -6 PQ 240 C

Device Type

Temperature Range

C = Commercial (T = 0°C to +85°C)

J

I = Industrial (T = –40°C to +100°C)

J

Speed Grade

-4

-5

-6

Number of Pins

Package Type

BG = Ball Grid Array

FG = Fine-pitch Ball Grid Array

PQ = Plastic Quad Flat Pack

HQ = High Heat Dissipation QFP

TQ = Thin Quad Flat Pack

CS = Chip-scale Package

Figure 1: Virtex Ordering Information

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Virtex™ 2.5 V Field Programmable Gate Arrays

Revision History

Date

11/98

Version

1.0

Revision

Initial Xilinx release.

01/99-02/99

05/99

1.2-1.3

1.4

Both versions updated package drawings and specs.

Addition of package drawings and specifications.

Replaced FG 676 & FG680 package drawings.

05/99

1.5

07/99

1.6

Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit

Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O

Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and

new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and

Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.

Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated

IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.

Added IOB Input Switching Characteristics Standard Adjustments.

09/99

1.7

Speed grade update to preliminary status, Power-on specification and Clock-to-Out

Minimums additions, “0” hold time listing explanation, quiescent current listing update, and

Figure 6 ADDRA input label correction. Added T

parameter, changed T

to

IJITCC

OJIT

T

.

OPHASE

01/00

03/00

1.8

1.9

2.0

Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,

117153, 117154, and 117612. Modified notes for Recommended Operating Conditions

(voltage and temperature). Changed Bank information for V

in CS144 package on p.43.

CCO

Updated DLL Jitter Parameter table and waveforms, added Delay Measurement

Methodology table for different I/O standards, changed buffered Hex line info and

Input/Output Timing measurement notes.

New TBCKO values; corrected FG680 package connection drawing; new note about status

of CCLK pin after configuration.

05/00

09/00

2.1

2.2

2.3

Modified “Pins not listed...” statement. Speed grade update to Final status.

Modified Table 18.

•

Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.

Corrected Units column in table under IOB Input Switching Characteristics.

Added values to table under CLB SelectRAM Switching Characteristics.

•

Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in

Table 18.

10/00

2.4

•

Corrected BG256 Pin Function Diagram.

Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.

Converted file to modularized format. See Virtex Data Sheet section.

04/01

03/13

2.5

4.0

The products listed in this data sheet are obsolete. See XCN10016 for further information.

Virtex Data Sheet

The Virtex Data Sheet contains the following modules:

•

DS003-1, Virtex 2.5V FPGAs:

Introduction and Ordering Information (Module 1)

•

DS003-3, Virtex 2.5V FPGAs:

DC and Switching Characteristics (Module 3)

DS003-4, Virtex 2.5V FPGAs:

Pinout Tables (Module 4)

DS003-2, Virtex 2.5V FPGAs:

Functional Description (Module 2)

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Virtex™ 2.5 V

Field Programmable Gate Arrays

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Product Specification

The output buffer and all of the IOB control signals have

independent polarity controls.

Architectural Description

Virtex Array

The Virtex user-programmable gate array, shown in

Figure 1, comprises two major configurable elements: con-

figurable logic blocks (CLBs) and input/output blocks

(IOBs).

DLL

IOBs

DLL

VersaRing

•

CLBs provide the functional elements for constructing

logic

•

IOBs provide the interface between the package pins

and the CLBs

CLBs

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a VersaBlock™ that also provides local

routing resources to connect the CLB to the GRM.

The VersaRing™ I/O interface provides additional routing

resources around the periphery of the device. This routing

improves I/O routability and facilitates pin locking.

VersaRing

IOBs

DLL

The Virtex architecture also includes the following circuits

that connect to the GRM.

vao_b.eps

•

Dedicated block memories of 4096 bits each

Clock DLLs for clock-distribution delay compensation

and clock domain control

Figure 1: Virtex Architecture Overview

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. Two

forms of over-voltage protection are provided, one that per-

mits 5 V compliance, and one that does not. For 5 V compli-

ance, a Zener-like structure connected to ground turns on

when the output rises to approximately 6.5 V. When PCI

3.3 V compliance is required, a conventional clamp diode is

•

3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing

resources

Values stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memory cells on power-up, and can reload if

necessary to change the function of the device.

connected to the output supply voltage, V

.

CCO

Input/Output Block

The Virtex IOB, Figure 2, features SelectIO™ inputs and

outputs that support a wide variety of I/O signalling stan-

dards, see Table 1.

Optional pull-up and pull-down resistors and an optional

weak-keeper circuit are attached to each pad. Prior to con-

figuration, all pins not involved in configuration are forced

into their high-impedance state. The pull-down resistors and

the weak-keeper circuits are inactive, but inputs can option-

ally be pulled up.

The three IOB storage elements function either as edge-trig-

gered D-type flip-flops or as level sensitive latches. Each

IOB has a clock signal (CLK) shared by the three flip-flops

and independent clock enable signals for each flip-flop.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins will float.

Consequently, external pull-up or pull-down resistors must

be provided on pins required to be at a well-defined logic

level prior to configuration.

In addition to the CLK and CE control signals, the three

flip-flops share a Set/Reset (SR). For each flip-flop, this sig-

nal can be independently configured as a synchronous Set,

a synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

All Virtex IOBs support IEEE 1149.1-compatible boundary

scan testing.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Virtex™ 2.5 V Field Programmable Gate Arrays

R

Q

D

CE

T

TCE

Weak

Keeper

SR

PAD

O

Q

D

CE

OBUFT

OCE

SR

I

Programmable

Delay

IQ

Q

D

CE

IBUF

Vref

SR

CLK

ICE

ds022_02_091300

Figure 2: Virtex Input/Output Block (IOB)

Table 1: Supported Select I/O Standards

Input Reference

Output Source

Board Termination

I/O Standard

Voltage (V

)

Voltage (V

)

Voltage (V

)

5 V Tolerant

REF

CCO

TT

LVTTL 2 – 24 mA

N/A

3.3

N/A

Yes

No

LVCMOS2

PCI, 5 V

N/A

2.5

N/A

3.3

N/A

PCI, 3.3 V

GTL

N/A

3.3

N/A

0.8

N/A

1.5

1.2

GTL+

1.0

1.5

HSTL Class I

HSTL Class III

HSTL Class IV

SSTL3 Class I &II

SSTL2 Class I & II

CTT

0.75

0.9

0.75

1.5

0.9

1.5

3.3

1.5

1.25

1.5

2.5

1.25

1.5

3.3

AGP

1.32

3.3

N/A

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Virtex™ 2.5 V Field Programmable Gate Arrays

Eight I/O banks result from separating each edge of the

FPGA into two banks, as shown in Figure 3. Each bank has

Input Path

A buffer In the Virtex IOB input path routes the input signal

either directly to internal logic or through an optional input

flip-flop.

multiple V

pins, all of which must be connected to the

CCO

same voltage. This voltage is determined by the output

standards in use.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is zero.

Bank 0

Bank 1

GCLK3 GCLK2

Each input buffer can be configured to conform to any of the

low-voltage signalling standards supported. In some of

these standards the input buffer utilizes a user-supplied

Virtex

Device

threshold voltage, V . The need to supply V

imposes

REF

constraints on which standards can used in close proximity

to each other. See I/O Banking, page 3.

GCLK1 GCLK0

There are optional pull-up and pull-down resistors at each

user I/O input for use after configuration. Their value is in

the range 50 kΩ – 100 kΩ.

Bank 5

Bank 4

X8778_b

Output Path

Figure 3: Virtex I/O Banks

The output path includes a 3-state output buffer that drives

the output signal onto the pad. The output signal can be

routed to the buffer directly from the internal logic or through

an optional IOB output flip-flop.

Within a bank, output standards can be mixed only if they

. Compatible standards are shown in

Table 2. GTL and GTL+ appear under all voltages because

use the same V

CCO

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

their open-drain outputs do not depend on V

.

CCO

Table 2: Compatible Output Standards

Each output driver can be individually programmed for a

wide range of low-voltage signalling standards. Each output

buffer can source up to 24 mA and sink up to 48mA. Drive

strength and slew rate controls minimize bus transients.

V

Compatible Standards

CCO

3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+

2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+

1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+

In most signalling standards, the output High voltage

depends on an externally supplied V

voltage. The need

CCO

to supply V

imposes constraints on which standards

CCO

can be used in close proximity to each other. See I/O Bank-

ing, page 3.

Some input standards require a user-supplied threshold

voltage, V . In this case, certain user-I/O pins are auto-

REF

An optional weak-keeper circuit is connected to each out-

put. When selected, the circuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way eliminates bus chatter.

matically configured as inputs for the V

imately one in six of the I/O pins in the bank assume this

role.

voltage. Approx-

REF

The V

pins within a bank are interconnected internally

REF

and consequently only one V

voltage can be used within

REF

each bank. All V

pins in the bank, however, must be con-

REF

nected to the external voltage source for correct operation.

Because the weak-keeper circuit uses the IOB input buffer

Within a bank, inputs that require V can be mixed with

REF

to monitor the input level, an appropriate V

voltage must

REF

those that do not. However, only one V

used within a bank. Input buffers that use V

tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V

tolerant.

voltage can be

REF

be provided if the signalling standard requires one. The pro-

vision of this voltage must comply with the I/O banking

rules.

are not 5 V

REF

I/O Banking

The V

and V

pins for each bank appear in the device

REF

CCO

Some of the I/O standards described above require V

Pinout tables and diagrams. The diagrams also show the

bank affiliation of each I/O.

CCO

and/or V

voltages. These voltages externally and con-

REF

nected to device pins that serve groups of IOBs, called

banks. Consequently, restrictions exist about which I/O

standards can be combined within a given bank.

Within a given package, the number of V

can vary depending on the size of device. In larger devices,

and V

pins

CCO

REF

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Virtex™ 2.5 V Field Programmable Gate Arrays

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more I/O pins convert to V

pins. Since these are always

of five or six inputs. Consequently, when estimating the

number of system gates provided by a given device, each

CLB counts as 4.5 LCs.

REF

a superset of the V

pins used for smaller devices, it is

REF

possible to design a PCB that permits migration to a larger

device if necessary. All the V pins for the largest device

anticipated must be connected to the V

used for I/O.

REF

Look-Up Tables

voltage, and not

REF

Virtex function generators are implemented as 4-input

look-up tables (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16x1-bit dual-port synchronous RAM.

In smaller devices, some V

do not connect within the package. These unconnected pins

can be left unconnected externally, or can be connected to

pins used in larger devices

CCO

the V

voltage to permit migration to a larger device if

CCO

necessary.

The Virtex LUT can also provide a 16-bit shift register that is

ideal for capturing high-speed or burst-mode data. This

mode can also be used to store data in applications such as

Digital Signal Processing.

In TQ144 and PQ/HQ240 packages, all V

pins are

CCO

bonded together internally, and consequently the same

voltage must be connected to all of them. In the

V

CCO

CS144 package, bank pairs that share a side are intercon-

nected internally, permitting four choices for V . In both

Storage Elements

CCO

cases, the V

pins remain internally connected as eight

REF

The storage elements in the Virtex slice can be configured

either as edge-triggered D-type flip-flops or as level-sensi-

tive latches. The D inputs can be driven either by the func-

tion generators within the slice or directly from slice inputs,

bypassing the function generators.

banks, and can be used as described previously.

Configurable Logic Block

The basic building block of the Virtex CLB is the logic cell

(LC). An LC includes a 4-input function generator, carry

logic, and a storage element. The output from the function

generator in each LC drives both the CLB output and the D

input of the flip-flop. Each Virtex CLB contains four LCs,

organized in two similar slices, as shown in Figure 4.

In addition to Clock and Clock Enable signals, each Slice

has synchronous set and reset signals (SR and BY). SR

forces a storage element into the initialization state speci-

fied for it in the configuration. BY forces it into the opposite

state. Alternatively, these signals can be configured to oper-

ate asynchronously. All of the control signals are indepen-

dently invertible, and are shared by the two flip-flops within

the slice.

Figure 5 shows a more detailed view of a single slice.

In addition to the four basic LCs, the Virtex CLB contains

logic that combines function generators to provide functions

COUT

YB

Y

YB

Y

G4

G3

G2

G4

SP

Q

EC

SP

Q

EC

G3

G2

G1

Carry &

Control

Carry &

Control

LUT

D

YQ

D

YQ

G1

RC

BY

F4

BY

XB

X

XB

X

F4

F3

F2

F1

SP

Q

F3

F2

LUT

Carry &

Control

Carry &

Control

D

Q

D

XQ

EC

F1

RC

Slice 0

RC

Slice 1

BX

slice_c.eps

CIN

Figure 4: 2-Slice Virtex CLB

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Virtex™ 2.5 V Field Programmable Gate Arrays

COUT

YB

Y

CY

G4

G3

G2

G1

I3

I2

I1

I0

O

LUT

INIT

D

Q

YQ

DI

WE

EC

0

1

REV

BY

XB

F5IN

F6

CY

F5

X

F5

BY DG

CK

WE

A4

WSO

WSH

BX

DI

INIT

D

EC

Q

XQ

BX

DI

WE

I3

I2

I1

I0

F4

F3

F2

F1

REV

O

LUT

0

1

SR

CLK

CE

CIN

viewslc4.eps

Figure 5: Detailed View of Virtex Slice

Additional Logic

Block SelectRAM

The F5 multiplexer in each slice combines the function gen-

erator outputs. This combination provides either a function

generator that can implement any 5-input function, a 4:1

multiplexer, or selected functions of up to nine inputs.

Virtex FPGAs incorporate several large block SelectRAM

memories. These complement the distributed LUT

SelectRAMs that provide shallow RAM structures imple-

mented in CLBs.

Similarly, the F6 multiplexer combines the outputs of all four

function generators in the CLB by selecting one of the

F5-multiplexer outputs. This permits the implementation of

any 6-input function, an 8:1 multiplexer, or selected func-

tions of up to 19 inputs.

Block SelectRAM memory blocks are organized in columns.

All Virtex devices contain two such columns, one along

each vertical edge. These columns extend the full height of

the chip. Each memory block is four CLBs high, and conse-

quently, a Virtex device 64 CLBs high contains 16 memory

blocks per column, and a total of 32 blocks.

Each CLB has four direct feedthrough paths, one per LC.

These paths provide extra data input lines or additional local

routing that does not consume logic resources.

Table 3 shows the amount of block SelectRAM memory that

is available in each Virtex device.

Arithmetic Logic

Table 3: Virtex Block SelectRAM Amounts

Dedicated carry logic provides fast arithmetic carry capabil-

ity for high-speed arithmetic functions. The Virtex CLB sup-

ports two separate carry chains, one per Slice. The height

of the carry chains is two bits per CLB.

The arithmetic logic includes an XOR gate that allows a

1-bit full adder to be implemented within an LC. In addition,

a dedicated AND gate improves the efficiency of multiplier

implementation.

Device

XCV50

# of Blocks

Total Block SelectRAM Bits

8

32,768

40,960

49,152

57,344

65,536

81,920

98,304

114,688

131,072

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

10

12

14

16

20

24

28

32

The dedicated carry path can also be used to cascade func-

tion generators for implementing wide logic functions.

BUFTs

Each Virtex CLB contains two 3-state drivers (BUFTs) that

can drive on-chip busses. See Dedicated Routing, page 7.

Each Virtex BUFT has an independent 3-state control pin

and an independent input pin.

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Each block SelectRAM cell, as illustrated in Figure 6, is a

fully synchronous dual-ported 4096-bit RAM with indepen-

dent control signals for each port. The data widths of the

two ports can be configured independently, providing

built-in bus-width conversion.

Table 4: Block SelectRAM Port Aspect Ratios

Width

Depth

4096

2048

1024

512

ADDR Bus

ADDR<11:0>

ADDR<10:0>

ADDR<9:0>

ADDR<8:0>

ADDR<7:0>

Data Bus

DATA<0>

1

2

DATA<1:0>

DATA<3:0>

DATA<7:0>

DATA<15:0>

4

RAMB4_S#_S#

8

WEA

ENA

RSTA

16

256

DOA[#:0]

CLKA

ADDRA[#:0]

DIA[#:0]

The Virtex block SelectRAM also includes dedicated routing

to provide an efficient interface with both CLBs and other

block SelectRAMs. Refer to XAPP130 for block SelectRAM

timing waveforms.

WEB

ENB

RSTB

CLKB

DOB[#:0]

Programmable Routing Matrix

It is the longest delay path that limits the speed of any

worst-case design. Consequently, the Virtex routing archi-

tecture and its place-and-route software were defined in a

single optimization process. This joint optimization mini-

mizes long-path delays, and consequently, yields the best

system performance.

ADDRB[#:0]

DIB[#:0]

xcv_ds_006

Figure 6: Dual-Port Block SelectRAM

Table 4 shows the depth and width aspect ratios for the

block SelectRAM.

The joint optimization also reduces design compilation

times because the architecture is software-friendly. Design

cycles are correspondingly reduced due to shorter design

iteration times.

To Adjacent

GRM

To Adjacent

GRM

To Adjacent

GRM

Direct Connection

To Adjacent

CLB

Direct Connection

To Adjacent

CLB

X8794b

Figure 7: Virtex Local Routing

•

Internal CLB feedback paths that provide high-speed

connections to LUTs within the same CLB, chaining

them together with minimal routing delay

Direct paths that provide high-speed connections

between horizontally adjacent CLBs, eliminating the

delay of the GRM.

Local Routing

The VersaBlock provides local routing resources, as shown

in Figure 7, providing the following three types of connec-

tions.

•

Interconnections among the LUTs, flip-flops, and GRM

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•

12 Longlines are buffered, bidirectional wires that

distribute signals across the device quickly and

efficiently. Vertical Longlines span the full height of the

device, and horizontal ones span the full width of the

device.

General Purpose Routing

Most Virtex signals are routed on the general purpose rout-

ing, and consequently, the majority of interconnect

resources are associated with this level of the routing hier-

archy. The general routing resources are located in horizon-

tal and vertical routing channels associated with the rows

and columns CLBs. The general-purpose routing resources

are listed below.

I/O Routing

Virtex devices have additional routing resources around

their periphery that form an interface between the CLB array

and the IOBs. This additional routing, called the VersaRing,

facilitates pin-swapping and pin-locking, such that logic

redesigns can adapt to existing PCB layouts. Time-to-mar-

ket is reduced, since PCBs and other system components

can be manufactured while the logic design is still in prog-

ress.

•

Adjacent to each CLB is a General Routing Matrix

(GRM). The GRM is the switch matrix through which

horizontal and vertical routing resources connect, and

is also the means by which the CLB gains access to

the general purpose routing.

•

24 single-length lines route GRM signals to adjacent

GRMs in each of the four directions.

Dedicated Routing

12 buffered Hex lines route GRM signals to another

GRMs six-blocks away in each one of the four

directions. Organized in a staggered pattern, Hex lines

can be driven only at their endpoints. Hex-line signals

can be accessed either at the endpoints or at the

midpoint (three blocks from the source). One third of

the Hex lines are bidirectional, while the remaining

ones are uni-directional.

Some classes of signal require dedicated routing resources

to maximize performance. In the Virtex architecture, dedi-

cated routing resources are provided for two classes of sig-

nal.

•

Horizontal routing resources are provided for on-chip

3-state busses. Four partitionable bus lines are

provided per CLB row, permitting multiple busses

within a row, as shown in Figure 8.

•

Two dedicated nets per CLB propagate carry signals

vertically to the adjacent CLB.

Tri-State

Lines

CLB

buft_c.eps

Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines

•

The secondary local clock routing resources consist of

Global Routing

24 backbone lines, 12 across the top of the chip and 12

across bottom. From these lines, up to 12 unique

signals per column can be distributed via the 12

longlines in the column. These secondary resources

are more flexible than the primary resources since they

are not restricted to routing only to clock pins.

Global Routing resources distribute clocks and other sig-

nals with very high fanout throughout the device. Virtex

devices include two tiers of global routing resources

referred to as primary global and secondary local clock rout-

ing resources.

•

The primary global routing resources are four

Clock Distribution

dedicated global nets with dedicated input pins that are

designed to distribute high-fanout clock signals with

minimal skew. Each global clock net can drive all CLB,

IOB, and block RAM clock pins. The primary global

nets can only be driven by global buffers. There are

four global buffers, one for each global net.

Virtex provides high-speed, low-skew clock distribution

through the primary global routing resources described

above. A typical clock distribution net is shown in Figure 9.

Four global buffers are provided, two at the top center of the

device and two at the bottom center. These drive the four

primary global nets that in turn drive any clock pin.

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Four dedicated clock pads are provided, one adjacent to

each of the global buffers. The input to the global buffer is

selected either from these pads or from signals in the gen-

eral purpose routing.

GCLKPAD2

GCLKPAD3

GCLKBUF2

Global Clock Column

Global Clock Rows

GCLKBUF3

Global Clock Spine

GCLKBUF1

GCLKPAD1

GCLKBUF0

GCLKPAD0

gclkbu_2.eps

Figure 9: Global Clock Distribution Network

Delay-Locked Loop (DLL)

Boundary Scan

Associated with each global clock input buffer is a fully digi-

tal Delay-Locked Loop (DLL) that can eliminate skew

between the clock input pad and internal clock-input pins

throughout the device. Each DLL can drive two global clock

networks.The DLL monitors the input clock and the distrib-

uted clock, and automatically adjusts a clock delay element.

Clock edges reach internal flip-flops one to four clock peri-

ods after they arrive at the input. This closed-loop system

effectively eliminates clock-distribution delay by ensuring

that clock edges arrive at internal flip-flops in synchronism

with clock edges arriving at the input.

Virtex devices support all the mandatory boundary-scan

instructions specified in the IEEE standard 1149.1. A Test

Access Port (TAP) and registers are provided that implement

the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions. The TAP

also supports two internal scan chains and configura-

tion/readback of the device.The TAP uses dedicated package

pins that always operate using LVTTL. For TDO to operate

using LVTTL, the V

for Bank 2 should be 3.3 V. Other-

CCO

wise, TDO switches rail-to-rail between ground and V

.

CCO

Boundary-scan operation is independent of individual IOB

configurations, and unaffected by package type. All IOBs,

including un-bonded ones, are treated as independent

3-state bidirectional pins in a single scan chain. Retention of

the bidirectional test capability after configuration facilitates

the testing of external interconnections, provided the user

design or application is turned off.

In addition to eliminating clock-distribution delay, the DLL

provides advanced control of multiple clock domains. The

DLL provides four quadrature phases of the source clock,

can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,

5, 8, or 16.

The DLL also operates as a clock mirror. By driving the out-

put from a DLL off-chip and then back on again, the DLL can

be used to de-skew a board level clock among multiple Vir-

tex devices.

Table 5 lists the boundary-scan instructions supported in

Virtex FPGAs. Internal signals can be captured during

EXTEST by connecting them to un-bonded or unused IOBs.

They can also be connected to the unused outputs of IOBs

defined as unidirectional input pins.

In order to guarantee that the system clock is operating cor-

rectly prior to the FPGA starting up after configuration, the

DLL can delay the completion of the configuration process

until after it has achieved lock.

Before the device is configured, all instructions except

USER1 and USER2 are available. After configuration, all

instructions are available. During configuration, it is recom-

mended that those operations using the boundary-scan

register (SAMPLE/PRELOAD, INTEST, EXTEST) not be

performed.

See DLL Timing Parameters, page 21 of Module 3, for fre-

quency range information.

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In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FPGA, and also to read back the configuration data.

The FPGA supports up to two additional internal scan

chains that can be specified using the BSCAN macro. The

macro provides two user pins (SEL1 and SEL2) which are

decodes of the USER1 and USER2 instructions respec-

tively. For these instructions, two corresponding pins (TDO1

and TDO2) allow user scan data to be shifted out of TDO.

Figure 10 is a diagram of the Virtex Series boundary scan

logic. It includes three bits of Data Register per IOB, the

IEEE 1149.1 Test Access Port controller, and the Instruction

Register with decodes.

Likewise, there are individual clock pins (DRCK1 and

DRCK2) for each user register. There is a common input pin

(TDI) and shared output pins that represent the state of the

TAP controller (RESET, SHIFT, and UPDATE).

Instruction Set

The Virtex Series boundary scan instruction set also

includes instructions to configure the device and read back

configuration data (CFG_IN, CFG_OUT, and JSTART). The

complete instruction set is coded as shown in Table 5.

Bit Sequence

The order within each IOB is: In, Out, 3-State. The

input-only pins contribute only the In bit to the boundary

scan I/O data register, while the output-only pins contributes

all three bits.

Data Registers

The primary data register is the boundary scan register. For

each IOB pin in the FPGA, bonded or not, it includes three

bits for In, Out, and 3-State Control. Non-IOB pins have

appropriate partial bit population if input-only or output-only.

Each EXTEST CAPTURED-OR state captures all In, Out,

and 3-state pins.

From a cavity-up view of the chip (as shown in EPIC), start-

ing in the upper right chip corner, the boundary scan

data-register bits are ordered as shown in Figure 11.

BSDL (Boundary Scan Description Language) files for Vir-

tex Series devices are available on the Xilinx web site in the

File Download area.

The other standard data register is the single flip-flop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

DATA IN

IOB.T

0

1

0

sd

1

D

Q

D

Q

LE

IOB

sd

1

0

D

Q

D

Q

LE

1

0

IOB.I

1

sd

D

Q

D

Q

0

LE

1

0

IOB.Q

IOB.T

BYPASS

REGISTER

0

1

M

U

X

TDO

1

sd

INSTRUCTION REGISTER

TDI

D

Q

D

Q

0

LE

1

sd

D

Q

D

Q

0

LE

1

0

IOB.I

DATAOUT

SHIFT/

CAPTURE

UPDATE

EXTEST

CLOCK DATA

REGISTER

X9016

Figure 10: Virtex Series Boundary Scan Logic

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Identification Registers

Right half of Top-edge IOBs (Right-to-Left)

Bit 0 ( TDO end)

Bit 1

Bit 2

The IDCODE register is supported. By using the IDCODE,

the device connected to the JTAG port can be determined.

GCLK2

GCLK3

Left half of Top-edge IOBs (Right-to-Left)

Left-edge IOBs (Top-to-Bottom)

The IDCODE register has the following binary format:

vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1

where

M1

M0

M2

v = the die version number

Left half of Bottom-edge IOBs (Left-to-Right)

f = the family code (03h for Virtex family)

GCLK1

GCLK0

a = the number of CLB rows (ranges from 010h for XCV50

to 040h for XCV1000)

Right half of Bottom-edge IOBs (Left-to-Right)

DONE

PROG

c = the company code (49h for Xilinx)

The USERCODE register is supported. By using the USER-

CODE, a user-programmable identification code can be

loaded and shifted out for examination. The identification

code is embedded in the bitstream during bitstream gener-

ation and is valid only after configuration.

Right-edge IOBs (Bottom -to-Top)

(TDI end)

CCLK

990602001

Figure 11: Boundary Scan Bit Sequence

Table 6: IDCODEs Assigned to Virtex FPGAs

Table 5: Boundary Scan Instructions

FPGA

XCV50

IDCODE

v0610093h

v0614093h

v0618093h

v061C093h

v0620093h

v0628093h

v0630093h

v0638093h

v0640093h

Boundary-Scan

Command

Binary

Code(4:0)

Description

EXTEST

00000

00001

Enables boundary-scan

EXTEST operation

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

SAMPLE/PRELOAD

Enables boundary-scan

SAMPLE/PRELOAD

operation

USER 1

USER 2

00010

00011

00100

00101

00111

01000

01001

01010

Access user-defined

register 1

Access user-defined

register 2

CFG_OUT

CFG_IN

Access the configuration

bus for read operations.

Access the configuration

bus for write operations.

Including Boundary Scan in a Design

Since the boundary scan pins are dedicated, no special ele-

ment needs to be added to the design unless an internal

data register (USER1 or USER2) is desired.

INTEST

Enables boundary-scan

INTEST operation

USERCODE

IDCODE

HIGHZ

Enables shifting out

USER code

If an internal data register is used, insert the boundary scan

symbol and connect the necessary pins as appropriate.

Enables shifting out of ID

Code

Development System

3-statesoutputpinswhile

enabling the Bypass

Register

Virtex FPGAs are supported by the Xilinx Foundation and

Alliance CAE tools. The basic methodology for Virtex

design consists of three interrelated steps: design entry,

implementation, and verification. Industry-standard tools

are used for design entry and simulation (for example, Syn-

opsys FPGA Express), while Xilinx provides proprietary

architecture-specific tools for implementation.

JSTART

01100

Clock the start-up

sequence when

StartupClk is TCK

BYPASS

11111

Enables BYPASS

The Xilinx development system is integrated under the

Xilinx Design Manager (XDM™) software, providing design-

RESERVED

All other

codes

Xilinx reserved

instructions

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Virtex™ 2.5 V Field Programmable Gate Arrays

ers with a common user interface regardless of their choice

of entry and verification tools. The XDM software simplifies

the selection of implementation options with pull-down

menus and on-line help.

design, thus allowing the most convenient entry method to

be used for each portion of the design.

Design Implementation

The place-and-route tools (PAR) automatically provide the

implementation flow described in this section. The parti-

tioner takes the EDIF net list for the design and maps the

logic into the architectural resources of the FPGA (CLBs

and IOBs, for example). The placer then determines the

best locations for these blocks based on their interconnec-

tions and the desired performance. Finally, the router inter-

connects the blocks.

Application programs ranging from schematic capture to

Placement and Routing (PAR) can be accessed through the

XDM software. The program command sequence is gener-

ated prior to execution, and stored for documentation.

Several advanced software features facilitate Virtex design.

RPMs, for example, are schematic-based macros with rela-

tive location constraints to guide their placement. They help

ensure optimal implementation of common functions.

The PAR algorithms support fully automatic implementation

of most designs. For demanding applications, however, the

user can exercise various degrees of control over the pro-

cess. User partitioning, placement, and routing information

is optionally specified during the design-entry process. The

implementation of highly structured designs can benefit

greatly from basic floor planning.

For HDL design entry, the Xilinx FPGA Foundation develop-

ment system provides interfaces to the following synthesis

design environments.

•

Synopsys (FPGA Compiler, FPGA Express)

Exemplar (Spectrum)

Synplicity (Synplify)

®

The implementation software incorporates Timing Wizard

For schematic design entry, the Xilinx FPGA Foundation

and alliance development system provides interfaces to the

following schematic-capture design environments.

timing-driven placement and routing. Designers specify tim-

ing requirements along entire paths during design entry.

The timing path analysis routines in PAR then recognize

these user-specified requirements and accommodate them.

•

Mentor Graphics V8 (Design Architect, QuickSim II)

Viewlogic Systems (Viewdraw)

Timing requirements are entered on a schematic in a form

directly relating to the system requirements, such as the tar-

geted clock frequency, or the maximum allowable delay

between two registers. In this way, the overall performance

of the system along entire signal paths is automatically tai-

lored to user-generated specifications. Specific timing infor-

mation for individual nets is unnecessary.

Third-party vendors support many other environments.

A standard interface-file specification, Electronic Design

Interchange Format (EDIF), simplifies file transfers into and

out of the development system.

Virtex FPGAs supported by a unified library of standard

functions. This library contains over 400 primitives and mac-

ros, ranging from 2-input AND gates to 16-bit accumulators,

and includes arithmetic functions, comparators, counters,

data registers, decoders, encoders, I/O functions, latches,

Boolean functions, multiplexers, shift registers, and barrel

shifters.

Design Verification

In addition to conventional software simulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

devices are infinitely reprogrammable, designs can be veri-

fied in real time without the need for extensive sets of soft-

ware simulation vectors.

The “soft macro” portion of the library contains detailed

descriptions of common logic functions, but does not con-

tain any partitioning or placement information. The perfor-

mance of these macros depends, therefore, on the

partitioning and placement obtained during implementation.

The development system supports both software simulation

and in-circuit debugging techniques. For simulation, the

system extracts the post-layout timing information from the

design database, and back-annotates this information into

the net list for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

RPMs, on the other hand, do contain predetermined parti-

tioning and placement information that permits optimal

implementation of these functions. Users can create their

own library of soft macros or RPMs based on the macros

and primitives in the standard library.

®

TRACE static timing analyzer.

For in-circuit debugging, the development system includes

a download and readback cable. This cable connects the

FPGA in the target system to a PC or workstation. After

downloading the design into the FPGA, the designer can

single-step the logic, readback the contents of the flip-flops,

and so observe the internal logic state. Simple modifica-

tions can be downloaded into the system in a matter of min-

utes.

The design environment supports hierarchical design entry,

with high-level schematics that comprise major functional

blocks, while lower-level schematics define the logic in

these blocks. These hierarchical design elements are auto-

matically combined by the implementation tools. Different

design entry tools can be combined within a hierarchical

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After Virtex devices are configured, unused IOBs function

as 3-state OBUFTs with weak pull downs. For a more

detailed description than that given below, see the

XAPP138, Virtex Configuration and Readback.

Configuration

Virtex devices are configured by loading configuration data

into the internal configuration memory. Some of the pins

used for this are dedicated configuration pins, while others

can be re-used as general purpose inputs and outputs once

configuration is complete.

Configuration Modes

Virtex supports the following four configuration modes.

The following are dedicated pins:

•

Slave-serial mode

Master-serial mode

SelectMAP mode

Boundary-scan mode

•

Mode pins (M2, M1, M0)

Configuration clock pin (CCLK)

PROGRAM pin

DONE pin

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Table 7.

Boundary-scan pins (TDI, TDO, TMS, TCK)

Depending on the configuration mode chosen, CCLK can

be an output generated by the FPGA, or it can be generated

externally and provided to the FPGA as an input. The

PROGRAM pin must be pulled High prior to reconfiguration.

Configuration through the boundary-scan port is always

available, independent of the mode selection. Selecting the

boundary-scan mode simply turns off the other modes. The

three mode pins have internal pull-up resistors, and default

to a logic High if left unconnected. However, it is recom-

mended to drive the configuration mode pins externally.

Note that some configuration pins can act as outputs. For

correct operation, these pins can require a V

permit LVTTL operation. All the pins affected are in banks 2

or 3. The configuration pins needed for SelectMap (CS,

Write) are located in bank 1.

of 3.3 V to

CCO

Table 7: Configuration Codes

Configuration Mode

Master-serial mode

Boundary-scan mode

SelectMAP mode

M2 M1 M0 CCLK Direction Data Width Serial D

Configuration Pull-ups

out

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Out

N/A

In

1

8

1

8

1

Yes

No

Slave-serial mode

Master-serial mode

Boundary-scan mode

SelectMAP mode

In

Yes

No

Out

N/A

In

Yes

No

Slave-serial mode

In

Yes

mixed configuration chains. This change was made to

improve serial configuration rates for Virtex-only chains.

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data

in bit-serial form from a serial PROM or other source of

serial configuration data. The serial bitstream must be setup

at the DIN input pin a short time before each rising edge of

an externally generated CCLK.

Figure 12 shows a full master/slave system. A Virtex device

in slave-serial mode should be connected as shown in the

third device from the left.

Slave-serial mode is selected by applying <111> or <011>

to the mode pins (M2, M1, M0). A weak pull-up on the mode

pins makes slave-serial the default mode if the pins are left

unconnected. However, it is recommended to drive the con-

figuration mode pins externally. Figure 13 shows

slave-serial mode programming switching characteristics.

For more information on serial PROMs, see the PROM data

sheet at:

http://www.xilinx.com/bvdocs/publications/ds026.pdf.

Multiple FPGAs can be daisy-chained for configuration from a

single source. After a particular FPGA has been configured,

the data for the next device is routed to the DOUT pin. The

data on the DOUT pin changes on the rising edge of CCLK.

Table 8 provides more detail about the characteristics

shown in Figure 13. Configuration must be delayed until the

INIT pins of all daisy-chained FPGAs are High.

The change of DOUT on the rising edge of CCLK differs

from previous families, but does not cause a problem for

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Virtex™ 2.5 V Field Programmable Gate Arrays

Table 8: Master/Slave Serial Mode Programming Switching

Figure

Description

DIN setup/hold, slave mode

DIN setup/hold, master mode

DOUT

References

Symbol

T /T_CCD

DCC

Values

5.0 / 0

12.0

5.0

Units

ns, min

ns, max

ns, min

MHz, max

1/2

3

T

/T

DSCK CKDS

T

CCO

CCH

High time

4

CCLK

Low time

5

T

5.0

CCL

Maximum Frequency

F

66

CC

Frequency Tolerance, master mode with

respect to nominal

+45%

–30%

V

3.3V

CC

330 Ω

M0 M1

M2

M0 M1

M2

DOUT

DIN

CCLK

VIRTEX

MASTER

SERIAL

CCLK

XC1701L

VIRTEX,

XC4000XL,

SLAVE

CLK

DATA

DIN

Optional Pull-up

Resistor on Done

1

PROGRAM

DONE

CEO

CE

PROGRAM

DONE

INIT

RESET/OE

(Low Reset Option Used)

PROGRAM

Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor

of 330 Ω should be added to the common DONE line. (For Spartan-XL devices, add a 4.7K Ω

pull-up resistor.) This pull-up is not needed if the DriveDONE attribute is set. If used,

DriveDONE should be selected only for the last device in the configuration chain.

xcv_12_050103

Figure 12: Master/Slave Serial Mode Circuit Diagram

DIN

1

2

5

T

DCC

T

CCD

CCL

CCLK

4

T

CCH

3

T

CCO

DOUT

(Output)

X5379_a

Figure 13: Slave-Serial Mode Programming Switching Characteristics

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daisy-chained FPGAs are fast enough to support the clock

rate.

Master-Serial Mode

In master-serial mode, the CCLK output of the FPGA drives

a Xilinx Serial PROM that feeds bit-serial data to the DIN

input. The FPGA accepts this data on each rising CCLK

edge. After the FPGA has been loaded, the data for the next

device in a daisy-chain is presented on the DOUT pin after

the rising CCLK edge.

On power-up, the CCLK frequency is 2.5 MHz. This fre-

quency is used until the ConfigRate bits have been loaded

when the frequency changes to the selected ConfigRate.

Unless a different frequency is specified in the design, the

default ConfigRate is 4 MHz.

Figure 12 shows a full master/slave system. In this system,

the left-most device operates in master-serial mode. The

remaining devices operate in slave-serial mode. The

SPROM RESET pin is driven by INIT, and the CE input is

driven by DONE. There is the potential for contention on the

DONE pin, depending on the start-up sequence options

chosen.

The interface is identical to slave-serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK which always starts at a slow default frequency. Con-

figuration bits then switch CCLK to a higher frequency for

the remainder of the configuration. Switching to a lower fre-

quency is prohibited.

Figure 14 shows the timing of master-serial configuration.

Master-serial mode is selected by a <000> or <100> on the

mode pins (M2, M1, M0). Table 8 shows the timing informa-

tion for Figure 14.

The CCLK frequency is set using the ConfigRate option in

the bitstream generation software. The maximum CCLK fre-

quency that can be selected is 60 MHz. When selecting a

CCLK frequency, ensure that the serial PROM and any

CCLK

(Output)

T

2

CKDS

T

1

DSCK

Serial Data In

Serial DOUT

(Output)

DS022_44_071201

Figure 14: Master-Serial Mode Programming Switching Characteristics

must rise from 1.0 V to V min in less

At power-up, V

In the SelectMAP mode, multiple Virtex devices can be

chained in parallel. DATA pins (D7:D0), CCLK, WRITE,

BUSY, PROGRAM, DONE, and INIT can be connected in

parallel between all the FPGAs. Note that the data is orga-

nized with the MSB of each byte on pin DO and the LSB of

each byte on D7. The CS pins are kept separate, insuring

that each FPGA can be selected individually. WRITE should

be Low before loading the first bitstream and returned High

after the last device has been programmed. Use CS to

select the appropriate FPGA for loading the bitstream and

sending the configuration data. at the end of the bitstream,

deselect the loaded device and select the next target FPGA

by setting its CS pin High. A free-running oscillator or other

externally generated signal can be used for CCLK. The

BUSY signal can be ignored for frequencies below 50 MHz.

For details about frequencies above 50 MHz, see

XAPP138, Virtex Configuration and Readback. Once all the

devices have been programmed, the DONE pin goes High.

CC

than 50 ms, otherwise delay configuration by pulling

PROGRAM Low until V is valid.

CC

The sequence of operations necessary to configure a Virtex

FPGA serially appears in Figure 15.

SelectMAP Mode

The SelectMAP mode is the fastest configuration option.

Byte-wide data is written into the FPGA with a BUSY flag

controlling the flow of data.

An external data source provides a byte stream, CCLK, a

Chip Select (CS) signal and a Write signal (WRITE). If

BUSY is asserted (High) by the FPGA, the data must be

held until BUSY goes Low.

Data can also be read using the SelectMAP mode. If

WRITE is not asserted, configuration data is read out of the

FPGA as part of a readback operation.

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Virtex™ 2.5 V Field Programmable Gate Arrays

Apply Power

Set PROGRAM = High

Release INIT

FPGA starts to clear

configuration memory.

FPGA makes a final

clearing pass and releases

INIT when finished.

If used to delay

configuration

Low

INIT?

High

Load a Configuration Bit

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

No

End of

Bitstream?

If no CRC errors found,

FPGA enters start-up phase

causing DONE to go High.

Yes

Configuration Completed

ds003_154_111799

Figure 15: Serial Configuration Flowchart

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained to permit high-speed 8-bit readback.

Multiple Virtex FPGAs can be configured using the Select-

MAP mode, and be made to start-up simultaneously. To

configure multiple devices in this way, wire the individual

CCLK, Data, WRITE, and BUSY pins of all the devices in

parallel. The individual devices are loaded separately by

asserting the CS pin of each device in turn and writing the

appropriate data. ^See Table 9 for SelectMAP Write Timing

Retention of the SelectMAP port is selectable on a

design-by-design basis when the bitstream is generated. If

retention is selected, PROHIBIT constraints are required to

prevent the SelectMAP-port pins from being used as user

I/O.

Characteristics.

.

Table 9: SelectMAP Write Timing Characteristics

Description

Symbol

/T

SMDCC SMCCD

Units

ns, min

D

Setup/Hold

1/2

3/4

5/6

7

T

5.0 / 1.7

7.0 / 1.7

12.0

0-7

CS Setup/Hold

T

/T

ns, min

SMCSCC SMCCCS

WRITE Setup/Hold

T

/T

ns, min

SMCCW SMWCC

CCLK

BUSY Propagation Delay

Maximum Frequency

T

ns, max

MHz, max

SMCKBY

F

66

CC

Maximum Frequency with no handshake

F

50

CCNH

1. Assert WRITE and CS Low. Note that when CS is

asserted on successive CCLKs, WRITE must remain

either asserted or de-asserted. Otherwise an abort will

be initiated, as described below.

Write

Write operations send packets of configuration data into the

FPGA. The sequence of operations for a multi-cycle write

operation is shown below. Note that a configuration packet

can be split into many such sequences. The packet does

not have to complete within one assertion of CS, illustrated

in Figure 16.

2. Drive data onto D[7:0]. Note that to avoid contention,

the data source should not be enabled while CS is Low

and WRITE is High. Similarly, while WRITE is High, no

more that one CS should be asserted.

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3. At the rising edge of CCLK: If BUSY is Low, the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance will instead

occur on the first clock after BUSY goes Low, and the

data must be held until this has happened.

5. De-assert CS and WRITE.

A flowchart for the write operation appears in Figure 17.

Note that if CCLK is slower than f , the FPGA never

asserts BUSY. In this case, the above handshake is unnec-

essary, and data can simply be entered into the FPGA every

CCLK cycle.

CCNH

4. Repeat steps 2 and 3 until all the data has been sent.

CCLK

3

4

6

CS

5

WRITE

1

2

DATA[0:7]

7

BUSY

Write

No Write

Write

ds003_16_071902

Figure 16: Write Operations

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Virtex™ 2.5 V Field Programmable Gate Arrays

Apply Power

FPGA starts to clear

configuration memory.

PROGRAM

from Low

to High

No

FPGA makes a final

clearing pass and releases

INIT when finished.

Yes

If used to delay

configuration

Release INIT

Low

INIT?

High

Set WRITE = Low

Enter Data Source

Sequence A

On first FPGA

Set CS = Low

Apply Configuration Byte

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

High

Busy?

Low

No

End of Data?

Yes

If no errors,

first FPGAs enter start-up phase

releasing DONE.

On first FPGA

Set CS = High

If no errors,

later FPGAs enter start-up phase

releasing DONE.

For any other FPGAs

Repeat Sequence A

Disable Data Source

Set WRITE = High

When all DONE pins

are released, DONE goes High

and start-up sequences complete.

Configuration Completed

ds003_17_090602

Figure 17: SelectMAP Flowchart for Write Operation

ies, and the FPGA requires a new synchronization word

Abort

prior to accepting any new packets.

During a given assertion of CS, the user cannot switch from

a write to a read, or vice-versa. This action causes the cur-

rent packet command to be aborted. The device will remain

BUSY until the aborted operation has completed. Following

an abort, data is assumed to be unaligned to word boundar-

To initiate an abort during a write operation, de-assert

WRITE. At the rising edge of CCLK, an abort is initiated, as

shown in Figure 18.

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The end of the memory-clearing phase is signalled by INIT

going High, and the completion of the entire process is sig-

nalled by DONE going High.

CCLK

The power-up timing of configuration signals is shown in

Figure 19. The corresponding timing characteristics are

listed in Table 10.

CS

WRITE

V

TPOR

CC

DATA[0:7]

PROGRAM

INIT

BUSY

TPI

Abort

X8797_c

T

ICCK

CCLK OUTPUT or INPUT

M0, M1, M2

(Required)

Figure 18: SelectMAP Write Abort Waveforms

VALID

98122302

Boundary-Scan Mode

Figure 19: Power-Up Timing Configuration Signals

Table 10: Power-up Timing Characteristics

In the boundary-scan mode, configuration is done through

the IEEE 1149.1 Test Access Port. Note that the

PROGRAM pin must be pulled High prior to reconfiguration.

A Low on the PROGRAM pin resets the TAP controller and

no JTAG operations can be performed.

Description

Power-on Reset

Symbol

Value

2.0

Units

ms, max

μs, max

μs, min

μs, max

ns, min

T

POR

Configuration through the TAP uses the CFG_IN instruc-

tion. This instruction allows data input on TDI to be con-

verted into data packets for the internal configuration bus.

Program Latency

CCLK (output) Delay

T

100.0

0.5

PL

T

ICCK

The following steps are required to configure the FPGA

through the boundary-scan port (when using TCK as a

start-up clock).

4.0

Program Pulse Width

T

300

PROGRAM

1. Load the CFG_IN instruction into the boundary-scan

instruction register (IR)

Delaying Configuration

INIT can be held Low using an open-drain driver. An

open-drain is required since INIT is a bidirectional

open-drain pin that is held Low by the FPGA while the con-

figuration memory is being cleared. Extending the time that

the pin is Low causes the configuration sequencer to wait.

Thus, configuration is delayed by preventing entry into the

phase where data is loaded.

2. Enter the Shift-DR (SDR) state

3. Shift a configuration bitstream into TDI

4. Return to Run-Test-Idle (RTI)

5. Load the JSTART instruction into IR

6. Enter the SDR state

7. Clock TCK through the startup sequence

8. Return to RTI

Start-Up Sequence

Configuration and readback via the TAP is always available.

The boundary-scan mode is selected by a <101> or 001>

on the mode pins (M2, M1, M0). For details on TAP charac-

teristics, refer to XAPP139.

The default Start-up sequence is that one CCLK cycle after

DONE goes High, the global 3-state signal (GTS) is released.

This permits device outputs to turn on as necessary.

One CCLK cycle later, the Global Set/Reset (GSR) and

Global Write Enable (GWE) signals are released. This per-

mits the internal storage elements to begin changing state

in response to the logic and the user clock.

Configuration Sequence

The configuration of Virtex devices is a three-phase pro-

cess. First, the configuration memory is cleared. Next, con-

figuration data is loaded into the memory, and finally, the

logic is activated by a start-up process.

The relative timing of these events can be changed. In addi-

tion, the GTS, GSR, and GWE events can be made depen-

dent on the DONE pins of multiple devices all going High,

forcing the devices to start in synchronism. The sequence

can also be paused at any stage until lock has been

achieved on any or all DLLs.

Configuration is automatically initiated on power-up unless

it is delayed by the user, as described below. The configura-

tion process can also be initiated by asserting PROGRAM.

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Virtex™ 2.5 V Field Programmable Gate Arrays

Data Stream Format

Readback

Virtex devices are configured by sequentially loading

frames of data. Table 11 lists the total number of bits

required to configure each device. For more detailed infor-

mation, see application note XAPP151 “Virtex Configura-

tion Architecture Advanced Users Guide”.

The configuration data stored in the Virtex configuration

memory can be readback for verification. Along with the

configuration data it is possible to readback the contents all

flip-flops/latches, LUTRAMs, and block RAMs. This capabil-

ity is used for real-time debugging.

For more detailed information, see Application Note

XAPP138: Virtex FPGA Series Configuration and Readback,

available online at www.xilinx.com.

Table 11: Virtex Bit-Stream Lengths

Device

XCV50

# of Configuration Bits

559,200

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

781,216

1,040,096

1,335,840

1,751,808

2,546,048

3,607,968

4,715,616

6,127,744

Revision History

Date

11/98

01/99

02/99

05/99

07/99

Version

1.0

Revision

Initial Xilinx release.

1.2

Updated package drawings and specs.

1.3

Update of package drawings, updated specifications.