XCZU7EV-1FFVF1517I_技术文档

Zynq UltraScale+ MPSoC Data Sheet:

DC and AC Switching Characteristics

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

Summary

The Xilinx^®Zynq^®UltraScale+™ MPSoCs are available in -3, -2, -1 speed grades, with -3E devices having the

highest performance. The -2LE and -1LI devices can operate at a V_CCINTvoltage at 0.85V or 0.72V and are

screened for lower maximum staꢀc power. When operated at V_CCINT= 0.85V, using -2LE and -1LI devices, the

speed speciꢁcaꢀon for the L devices is the same as the -2I or -1I speed grades. When operated at

V_CCINT= 0.72V, the -2LE and -1LI performance and staꢀc and dynamic power is reduced.

DC and AC characterisꢀcs are speciꢁed in extended (E) and industrial (I) temperature ranges. Except the

operaꢀng temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same

for a parꢀcular speed grade (that is, the ꢀming characterisꢀcs of a -1 speed grade extended device are the same

as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in

each temperature range.

All supply voltage and juncꢀon temperature speciꢁcaꢀons are representaꢀve of worst-case condiꢀons. The

parameters included are common to popular designs and typical applicaꢀons.

This data sheet, part of an overall set of documentaꢀon on the Zynq UltraScale+ MPSoCs, is available on the

Xilinx website at www.xilinx.com/documentaꢀon.

DC Characteristics

Absolute Maximum Ratings

Table 1: Absolute Maximum Ratings

Symbol

Description¹

Min

Max

Units

Processor System (PS)

V_{CC_PSINTFP}

PS primary logic full-power domain supply voltage

PS primary logic low-power domain supply voltage

PS auxiliary supply voltage

–0.500

1.000

2.000

1.000

2.000

1.320

V

V_{CC_PSINTLP}

V_{CC_PSAUX}

V_{CC_PSINTFP_DDR}

V_{CC_PSADC}

PS DDR controller and PHY supply voltage

PS SYSMON ADC supply voltage relative to GND_PSADC

PS PLL supply voltage

V_{CC_PSPLL}

herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and

PrimeCell are trademarks of ARM in the EU and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other

trademarks are the property of their respective owners.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 1: Absolute Maximum Ratings (cont'd)

Symbol

Description¹

Min

Max

Units

V_{PS_MGTRAVCC}

PS-GTR supply voltage

–0.500

1.000

2.000

V

V_{PS_MGTRAVTT}

V_{PS_MGTREFCLK}

V_{PS_MGTRIN}

PS-GTR termination voltage

PS-GTR reference clock input voltage

PS-GTR receiver input voltage

PS DDR I/O supply voltage

PS DDR PLL supply voltage

PS I/O supply

1.100

V_{CCO_PSDDR}

V_{CC_PSDDR_PLL}

V_{CCO_PSIO}

1.650

2.000

3.630

2

V_PSIN

PS I/O input voltage

V_{CCO_PSIO}+ 0.550

V_{CCO_PSDDR}+ 0.550

2.000

PS DDR I/O input voltage

V_{CC_PSBATT}

PS battery-backed RAM and battery-backed real-time clock (RTC)

supply voltage

Programmable Logic (PL)

V_CCINT

Internal supply voltage

–0.500

–0.550

–20

1.000

V

3

V_{CCINT_IO}

V_CCAUX

V_CCBRAM

V_CCO

Internal supply voltage for the I/O banks

Auxiliary supply voltage

2.000

V

Supply voltage for the block RAM memories

Output drivers supply voltage for HD I/O banks

Output drivers supply voltage for HP I/O banks

Auxiliary supply voltage for the I/O banks

Input reference voltage

1.000

V

3.400

V

2.000

V

4

V_{CCAUX_IO}

V_REF

2.000

V

2.000

V

2, 5, 6,

V_IN

I/O input voltage for HD I/O banks

I/O input voltage for HP I/O banks

Available output current at the pad

Available RMS output current at the pad

V_CCO+ 0.550

20

V

I_DC

mA

I_RMS

–20

20

GTH or GTY Transceiver⁷

V_MGTAVCC

Analog supply voltage for transceiver circuits

–0.500

1.000

1.300

1.900

1.300

V

V_MGTAVTT

Analog supply voltage for transceiver termination circuits

Auxiliary analog Quad PLL (QPLL) voltage supply for transceivers

Transceiver reference clock absolute input voltage

V_MGTVCCAUX

V_MGTREFCLK

V_MGTAVTTRCAL

Analog supply voltage for the resistor calibration circuit of the

transceiver column

V_IN

Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input

voltage

–0.500

1.200

V

I_DCIN-FLOAT

I_DCIN-MGTAVTT

I_DCIN-GND

DC input current for receiver input pins DC coupled RX

termination = floating⁸

–

10

0

mA

DC input current for receiver input pins DC coupled RX

termination = V_MGTAVTT

DC input current for receiver input pins DC coupled RX

termination = GND⁹

I_DCIN-PROG

I_DCOUT-FLOAT

I_{DCOUT-MGTAVTT}

DC input current for receiver input pins DC coupled RX

termination = programmable¹⁰

0

DC output current for transmitter pins DC coupled RX

termination = floating

6

DC output current for transmitter pins DC coupled RX

termination = V_MGTAVTT

6

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2

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 1: Absolute Maximum Ratings (cont'd)

Symbol

Description¹

Min

Max

Units

Video Codec Unit

V_{CCINT_VCU}

PL System Monitor

V_CCADC

Internal supply voltage for the video codec unit

–0.500

1.000

V

PL System Monitor supply relative to GNDADC

–0.500

2.000

V

V_REFP

PL System Monitor reference input relative to GNDADC

Temperature¹¹

T_STG

Storage temperature (ambient)

–65

–

150

260

250

°C

T_SOL

Maximum dry rework soldering temperature

Maximum reflow soldering temperature for SBVB484, SFVA625,

and SFVC784 packages

–

Maximum reflow soldering temperature for FBVB900, FFVC900,

FFVB1156, FFVC1156, FFVB1517, FFVF1517, FFVC1760, FFVD1760,

and FFVE1924 packages

–

245

125

°C

T_j

Maximum junction temperature

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not

implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2. When operating outside of the recommended operating conditions, refer to Table 6, Table 7, and Table 8 for maximum overshoot and

undershoot specifications.

3.

4.

V

_{CCINT_IO}must be connected to V_CCBRAM

.

V_{CCAUX_IO}must be connected to V_CCAUX

.

5. The lower absolute voltage specification always applies.

6. For I/O operation, see the UltraScale Architecture SelectIO Resources User Guide (UG571)

7. For more information on supported GTH or GTY transceiver terminations see the UltraScale Architecture GTH Transceivers User Guide

(UG576) or UltraScale Architecture GTY Transceivers User Guide (UG578).

8. AC coupled operation is not supported for RX termination = floating.

9. For GTY transceivers, DC coupled operation is not supported for RX termination = GND.

10. DC coupled operation is not supported for RX termination = programmable.

11. For soldering guidelines and thermal considerations, see the Zynq UltraScale+ Device Packaging and Pinouts Product Specification User

Guide (UG1075).

Recommended Operating Conditions

Table 2: Recommended Operating Conditions

Symbol

Description^{1, 2}

Min

Typ

Max

Units

Processor System

3

V_{CC_PSINTFP}

PS full-power domain supply voltage

0.808

0.850

0.892

V

For -1LI and -2LE (V_CCINT= 0.72V) devices: PS full-power domain

supply voltage

For -3E devices: PS full-power domain supply voltage

PS low-power domain supply voltage

0.873

0.808

0.900

0.850

0.927

0.892

V

V_{CC_PSINTLP}

For -1LI and -2LE (V_CCINT= 0.72V) devices: PS low-power domain

supply voltage

For -3E devices: PS low-power domain supply voltage

0.873

0.900

0.927

V

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 2: Recommended Operating Conditions (cont'd)

Symbol

Description^{1, 2}

Min

Typ

Max

Units

V_{CC_PSAUX}

PS auxiliary supply voltage

1.710

0.808

1.800

0.850

1.890

0.892

V

3

V_{CC_PSINTFP_DDR}

PS DDR controller and PHY supply voltage

For -1LI and -2LE (V_CCINT= 0.72V) devices: PS DDR controller and

PHY supply voltage

For -3E devices: PS DDR controller and PHY supply voltage

PS SYSMON ADC supply voltage relative to GND_PSADC

PS PLL supply voltage

0.873

1.710

1.164

0.825

1.746

1.06

0.900

1.800

1.200

0.850

1.800

–

0.927

1.890

V

V_{CC_PSADC}

V_{CC_PSPLL}

1.236

4

V_{PS_MGTRAVCC}

PS-GTR supply voltage

0.875

4

V_{PS_MGTRAVTT}

PS-GTR termination voltage

PS DDR I/O supply voltage

1.854

5

V_{CCO_PSDDR}

1.575

V_{CC_PSDDR_PLL}

PS DDR PLL supply voltage

1.710

–0.200

1.200

1.800

–

1.890

6

V_{CCO_PSIO}

PS I/O supply

3.465

V_PSIN

PS I/O input voltage

–

V_{CCO_PSIO}+ 0.200

V_{CCO_PSDDR}+ 0.200

1.500

PS DDR I/O input voltage

–

7

V_{CC_PSBATT}

PS battery-backed RAM and battery-backed real-time clock (RTC)

supply voltage

–

Programmable Logic

V_CCINT

PL internal supply voltage

0.825

0.698

0.850

0.720

0.876

0.742

V

For -1LI and -2LE (V_CCINT= 0.72V) devices: PL internal supply

voltage

For -3E devices: PL internal supply voltage

PL internal supply voltage for the I/O banks

0.873

0.825

0.900

0.850

0.927

0.876

V

8

V_{CCINT_IO}

For -1LI and -2LE (V_CCINT= 0.72V) devices: PL internal supply

voltage for the I/O banks

For -3E devices: PL internal supply voltage for the I/O banks

Block RAM supply voltage

0.873

0.825

0.873

1.746

1.140

0.950

1.746

–0.200

–

0.900

0.850

0.900

1.800

–

0.927

0.876

V

V_CCBRAM

For -3E devices: block RAM supply voltage

Auxiliary supply voltage

0.927

V

V_CCAUX

1.854

V

9

V_CCO

Supply voltage for HD I/O banks

Supply voltage for HP I/O banks

Auxiliary I/O supply voltage

3.400

V

–

1.900

V

10

V_{CCAUX_IO}

1.800

–

1.854

V

11

V_IN

I/O input voltage

V_CCO+ 0.200

10

V

12

I_IN

Maximum current through any PL or PS pin in a powered or

unpowered bank when forward biasing the clamp diode

–

mA

GTH or GTY Transceiver

13

V_MGTAVCC

Analog supply voltage for the GTH or GTY transceiver

0.873

1.164

0.900

1.200

0.927

1.236

V

13

V_MGTAVTT

Analog supply voltage for the GTH or GTY transmitter and

receiver termination circuits

13

V_MGTVCCAUX

Auxiliary analog QPLL voltage supply for the transceivers

1.746

1.164

1.800

1.200

1.854

1.236

V

13

V_MGTAVTTRCAL

Analog supply voltage for the resistor calibration circuit of the

GTH or GTY transceiver column

VCU

V_{CCINT_VCU}

Internal supply voltage for the VCU

0.873

0.900

0.927

V

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 2: Recommended Operating Conditions (cont'd)

Symbol

Description^{1, 2}

Min

Typ

Max

Units

PL System Monitor

V_CCADC

PL System Monitor supply relative to GNDADC

1.746

1.200

1.800

1.250

1.854

1.300

V

V_REFP

PL System Monitor externally supplied reference voltage relative

to GNDADC

Temperature

T_j¹⁴

Junction temperature operating range for extended (E)

temperature devices¹⁵

0

–

100

125

°C

Junction temperature operating range for industrial (I)

temperature devices

–40

Junction temperature operating range for automotive (Q)

temperature devices

Junction temperature operating range for eFUSE programming

Notes:

1. All voltages are relative to GND.

2. For the design of the power distribution system consult the UltraScale Architecture PCB Design User Guide (UG583).

3. V_{CC_PSINTFP_DDR}must be tied to V_{CC_PSINTFP}

4. Each voltage listed requires filtering as described in the UltraScale Architecture PCB Design User Guide (UG583).

.

5. Includes V_{CCO_PSDDR}of 1.2V, 1.35V, 1.5V at ±5% and 1.1V +0.07V/–0.04V depending upon the tolerances required by specific memory

standards.

6. Applies to all PS I/O supply banks. Includes V_{CCO_PSIO}of 1.8V, 2.5V, and 3.3V at ±5%.

7. If the battery-backed RAM or RTC is not used, connect V_{CC_PSBATT}to GND or V_{CC_PSAUX}. The V_{CC_PSAUX}maximum of 1.89V is acceptable on

an unused V_{CC_PSBATT}

8. V_{CCINT_IO}must be connected to V_CCBRAM

9. Includes V_CCOof 1.0V (HP I/O only), 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HD I/O only) at ±5%, and 3.3V (HD I/O only) at +3/–5%.

10. V_{CCAUX_IO}must be connected to V_CCAUX

.

11. The lower absolute voltage specification always applies.

12. A total of 200 mA per bank should not be exceeded.

13. Each voltage listed requires filtering as described in the UltraScale Architecture GTH Transceivers User Guide (UG576) or the UltraScale

Architecture GTY Transceivers User Guide (UG578).

14. Xilinx recommends measuring the T_jof a device using the system monitor as described in the UltraScale Architecture System Monitor User

Guide (UG580). The SYSMON temperature measurement errors (that are described in Table 69 and Table 124) must be accounted for in

your design. For example, when using the PL system monitor with an external reference of 1.25V, and when SYSMON reports 97°C, there

is a measurement error ±3°C. A reading of 97°C is considered the maximum adjusted T_j(100°C – 3°C = 97°C).

15. Devices labeled with the speed/temperature grade of -2LE can operate for a limited time at a junction temperature between 100°C and

110°C. Timing parameters adhere to the same speed file at 110°C as they do below 110°C, regardless of operating voltage (nominal

voltage of 0.85V or a low-voltage of 0.72V). Operation up to T_j= 110°C is limited to 1% of the device lifetime and can occur sequentially or

at regular intervals as long as the total time does not exceed 1% of the device lifetime.

Available Speed Grades and Operating Voltages

Table 3 describes the speed grades per device and the V_CCINToperaꢀng supply voltages for the full-power, low-

power, and DDR domains. For more informaꢀon on selecꢀng devices and speed grades, see the UltraScale

Architecture and Product Data Sheet: Overview (DS890).

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 3: Available Speed Grades and Operating Voltages

Speed Grade

V_CCINT

V_{CC_PSINTLP}

V_{CC_PSINTFP}

V_{CC_PSINTFP_DDR}

Units

-3E

-2E

0.90

0.85

0.72

0.90

0.85

0.90

0.85

0.90

0.85

V

-2I

-2LE

-1E

-1I

-1Q

-1LI

-2LE

-1LI

DC Characteristics Over Recommended Operating Conditions

Table 4: DC Characteristics Over Recommended Operating Conditions

Symbol

Description

Min

Typ¹

Max

Units

V_DRINT

V_DRAUX

Data retention V_CCINTvoltage (below which configuration data

might be lost)

0.68

–

V

Data retention V_CCAUXvoltage (below which configuration data

might be lost)

1.5

–

V

I_REF

I_L

V_REFleakage current per pin

Input or output leakage current per pin (sample-tested)²

–

15

µA

pF

3

C_IN

Die input capacitance at the pad (HP I/O)

–

3.1

4.75

190

169

120

100

200

120

8

Die input capacitance at the pad (HD I/O)

–

pF

I_RPU

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 3.3V

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 2.5V

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 1.8V

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 1.5V

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 1.2V

Pad pull-down (when selected) at V_IN= 3.3V

Pad pull-down (when selected) at V_IN= 1.8V

75

50

60

30

10

60

29

–

µA

mA

I_RPD

I_CCADCONPL

I_CCADCONPS

I_CCADCOFFPL

I_CCADCOFFPS

Analog supply current for the PL SYSMON circuits in the power-up

state

Analog supply current for the PS SYSMON circuits in the power-up

state

–

10

1.5

1.8

mA

Analog supply current for the PL SYSMON circuits in the power-

down state

Analog supply current for the PS SYSMON circuits in the power-

down state

4, 5

I_{CC_PSBATT}

Battery supply current at V_{CC_PSBATT}= 1.50V, RTC enabled

Battery supply current at V_{CC_PSBATT}= 1.50V, RTC disabled

Battery supply current at V_{CC_PSBATT}= 1.20V, RTC enabled

Battery supply current at V_{CC_PSBATT}= 1.20V, RTC disabled

–

3650

650

nA

3150

150

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 4: DC Characteristics Over Recommended Operating Conditions (cont'd)

Symbol

Description

Min

Typ¹

Max

Units

6

I_PSFS

PS V_{CC_PSAUX}additional supply current during eFUSE

programming

–

115

mA

Calibrated programmable on-die termination (DCI) in HP I/O banks⁷(measured per JEDEC specification)

R⁹

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 where ODT = RTT_40

–10%⁸

40

48

60

+10%⁸

Ω

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 where ODT = RTT_48

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 where ODT = RTT_60

Programmable input termination to V_CCOwhere ODT = RTT_40

Programmable input termination to V_CCOwhere ODT = RTT_48

Programmable input termination to V_CCOwhere ODT = RTT_60

Programmable input termination to V_CCOwhere ODT = RTT_120

Programmable input termination to V_CCOwhere ODT = RTT_240

–10%⁸

40

48

+10%⁸

Ω

60

120

240

Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)

R⁹

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 where ODT = RTT_40

–50%

40

48

60

+50%

Ω

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 where ODT = RTT_48

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 where ODT = RTT_60

Programmable input termination to V_CCOwhere ODT = RTT_40

Programmable input termination to V_CCOwhere ODT = RTT_48

Programmable input termination to V_CCOwhere ODT = RTT_60

Programmable input termination to V_CCOwhere ODT = RTT_120

Programmable input termination to V_CCOwhere ODT = RTT_240

–50%

40

48

+50%

Ω

60

120

240

Uncalibrated programmable on-die termination in HD I/O banks (measured per JEDEC specification)

R⁹

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 where ODT = RTT_48

–50%

48

+50%

Ω

Internal V_REF

50% V_CCO

70% V_CCO

V_CCOx 0.49 V_CCOx 0.50 V_CCOx 0.51

V_CCOx 0.69 V_CCOx 0.70 V_CCOx 0.71

V

Differential termination Programmable differential termination (TERM_100) for HP I/O

banks

–35%

100

+35%

Ω

n

Temperature diode ideality factor

Temperature diode series resistance

–

1.026

2

–

r

Ω

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. For the HP I/O banks with a V_CCOof 1.8V and separated V_CCOand V_{CCAUX_IO}power supplies, the I_Lmaximum current is 70 µA.

3. This measurement represents the die capacitance at the pad, not including the package.

4. Maximum value specified for worst case process at 25°C.

5. I_{CC_PSBATT}is measured when the battery-backed RAM (BBRAM) is enabled.

6. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is

active).

7. VRP resistor tolerance is (240Ω ±1%)

8. If VRP resides at a different bank (DCI cascade), the range increases to ±15%.

9. On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide (UG571).

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 5: PS MIO Pull-up and Pull-down Current

Symbol

Description

Min

Max

Units

1

I_RPU

Pad pull-up (when selected) at V_IN= 0V, V_{CCO_PSMIO}= 3.3V

Pad pull-up (when selected) at V_IN= 0V, V_{CCO_PSMIO}= 2.5V

Pad pull-up (when selected) at V_IN= 0V, V_{CCO_PSMIO}= 1.8V

Pad pull-down (when selected) at V_IN= 3.3V

20

15

20

15

80

65

80

65

µA

I_RPD

Pad pull-down (when selected) at V_IN= 2.5V

Pad pull-down (when selected) at V_IN= 1.8V

Notes:

1. After power-on, the reset values of the MIO pin configuration registers enable and select the PS MIO pull-ups.

V_INMaximum Allowed AC Voltage Overshoot and Undershoot

Table 6: V_INMaximum Allowed AC Voltage Overshoot and Undershoot for HD I/O Banks

AC Voltage Overshoot¹

% of UI²at –40°C to 100°C³

AC Voltage Undershoot¹

% of UI²at –40°C to 100°C³

V_CCO+ 0.30

V_CCO+ 0.35

V_CCO+ 0.40

V_CCO+ 0.45

V_CCO+ 0.50

V_CCO+ 0.55

V_CCO+ 0.60

V_CCO+ 0.65

V_CCO+ 0.70

V_CCO+ 0.75

V_CCO+ 0.80

V_CCO+ 0.85

V_CCO+ 0.90

V_CCO+ 0.95

Notes:

100%

92%

–0.30

–0.35

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

–0.75

–0.80

–0.85

–0.90

–0.95

100%

90%

78%

40%

24%

18.0%

13.0%

10.8%

9.0%

7.0%

6.0%

5.0%

4.0%

2.5%

92%

1. A total of 200 mA per bank should not be exceeded.

2. For UI smaller than 20 µs.

3. For the -1Q devices, the upper temperature limit is 125°C.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 7: V_INMaximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks

AC Voltage Overshoot¹

% of UI²at –40°C to 100°C³

AC Voltage Undershoot¹

% of UI²at –40°C to 100°C³

V_CCO+ 0.30

V_CCO+ 0.35

V_CCO+ 0.40

V_CCO+ 0.45

V_CCO+ 0.50

V_CCO+ 0.55

V_CCO+ 0.60

V_CCO+ 0.65

V_CCO+ 0.70

Notes:

100%

92%

50%

20%

10%

6%

–0.30

–0.35

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

100%

92%

50%

20%

10%

6%

2%

1. A total of 200 mA per bank should not be exceeded.

2. For UI smaller than 20 µs.

3. For the -1Q devices, the upper temperature limit is 125°C.

Table 8: V_PSINMaximum Allowed AC Voltage Overshoot and Undershoot for PS I/O Banks

AC Voltage Overshoot¹

% of UI²at –40°C to 100°C³

AC Voltage Undershoot¹

% of UI²at –40°C to 100°C³

V_{CCO_PSIO}+ 0.30

V_{CCO_PSIO}+ 0.35

V_{CCO_PSIO}+ 0.40

V_{CCO_PSIO}+ 0.45

V_{CCO_PSIO}+ 0.50

V_{CCO_PSIO}+ 0.55

V_{CCO_PSIO}+ 0.60

V_{CCO_PSIO}+ 0.65

V_{CCO_PSIO}+ 0.70

V_{CCO_PSIO}+ 0.75

V_{CCO_PSIO}+ 0.80

V_{CCO_PSIO}+ 0.85

V_{CCO_PSIO}+ 0.90

V_{CCO_PSIO}+ 0.95

Notes:

100%

75%

60%

30%

20%

10%

8%

–0.30

–0.35

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

–0.75

–0.80

–0.85

–0.90

–0.95

100%

75%

45%

40%

10%

6%

2%

0%

6%

0%

6%

0%

1. A total of 200 mA per bank should not be exceeded.

2. For UI smaller than 20 µs.

3. For the -1Q devices, the upper temperature limit is 125°C.

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9

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Quiescent Supply Current

Table 9: Typical Quiescent Supply Current

Speed Grade and V_CCINTOperating Voltages

Symbol

Description^{1, 2, 3, 4}

Device

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

I_CCINTQ

Quiescent V_CCINTsupply current

XCZU2

N/A

719

1629

1263

1629

1786

1987

2728

N/A

61

393

684

1549

1201

1549

1699

1890

2594

N/A

44

393

684

1549

1201

1549

1699

1890

2594

393

684

44

344

601

1358

1055

1358

1491

1660

2275

N/A

44

344

601

1358

1055

1358

1491

1660

2275

344

601

44

mA

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

XCZU2

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

All devices

I_{CCINT_IOQ}

Quiescent V_{CCINT_IO}supply current

44

59

61

59

61

59

120

61

115

59

115

59

115

59

115

59

120

61

115

59

115

59

115

59

115

59

164

N/A

1

158

N/A

1

158

44

158

N/A

1

158

44

59

I_CCOQ

Quiescent V_CCOsupply current

1

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10

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 9: Typical Quiescent Supply Current (cont'd)

Speed Grade and V_CCINTOperating Voltages

Symbol

Description^{1, 2, 3, 4}

Device

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

I_CCAUXQ

Quiescent V_CCAUXsupply current

XCZU2

N/A

90

55

mA

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

XCZU2

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

90

227

174

227

255

266

396

N/A

32

227

174

227

255

266

396

N/A

26

227

174

227

255

266

396

55

227

174

227

255

266

396

N/A

26

227

174

227

255

266

396

55

90

I_{CCAUX_IOQ}

Quiescent V_{CCAUX_IO}supply current

26

32

33

56

33

56

33

74

N/A

26

N/A

26

32

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11

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 9: Typical Quiescent Supply Current (cont'd)

Speed Grade and V_CCINTOperating Voltages

Symbol

Description^{1, 2, 3, 4}

Device

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

I_CCBRAMQ

Quiescent V_CCBRAMsupply current

XCZU2

N/A

9

6

mA

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

9

25

24

15

24

22

28

35

N/A

24

15

24

22

28

35

6

24

15

24

22

28

35

N/A

24

15

24

22

28

35

6

16

25

23

29

37

N/A

6

9

Notes:

1. Typical values are specified at nominal voltage, 85°C junction temperatures (T_j) with single-ended SelectIO™ resources.

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and

floating.

3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for

conditions or supplies other than those specified.

4. Typical values depend upon your configuration. To accurately estimate all PS supply currents, use the interactive XPE spreadsheet tool.

Power Supply Sequencing

PS Power-On/Off Power Supply Sequencing

The low-power domain (LPD) must operate before the full-power domain (FPD) can funcꢀon. The low-power

and full-power domains can be powered simultaneously. The PS_POR_B input must be asserted to GND during

the power-on sequence (see Table 37). The FPD (when used) must be powered before PS_POR_B is released.

To achieve minimum current draw and ensure that the I/Os are 3-stated at power-on, the recommended power-

on sequence for the low-power domain (LPD) is listed. The recommended power-oﬀ sequence is the reverse of

the power-on sequence.

1. V_{CC_PSINTLP}

2. V_{CC_PSAUX}, V_{CC_PSADC}, and V_{CC_PSPLL}in any order or simultaneously.

3. V_{CCO_PSIO}

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12

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

To achieve minimum current draw and ensure that the I/Os are 3-stated at power-on, the recommended power-

on sequence for the full-power domain (FPD) is listed. The recommended power-oﬀ sequence is the reverse of

the power-on sequence.

1. V_{CC_PSINTFP}and V_{CC_PSINTFP_DDR}driven from the same supply source.

2. V_{PS_MGTRAVCC}and V_{CC_PSDDR_PLL}in any order or simultaneously.

3. V_{PS_MGTRAVTT}and V_{CCO_PSDDR}in any order or simultaneously.

PL Power-On/Off Power Supply Sequencing

The recommended power-on sequence is V_CCINT, V_{CCINT_IO}/V_CCBRAM/V_{CCINT_VCU}, V_CCAUX/V_{CCAUX_IO}, and V_CCO

to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-

oﬀ sequence is the reverse of the power-on sequence. If V_CCINTand V_{CCINT_IO}/V_CCBRAMhave the same

recommended voltage levels, they can be powered by the same supply and ramped simultaneously. V_{CCINT_IO}

must be connected to V_CCBRAM. If V_CCAUX/V_{CCAUX_IO}and V_CCOhave the same recommended voltage levels,

they can be powered by the same supply and ramped simultaneously. V_CCAUXand V_{CCAUX_IO}must be connected

together. V_CCADCand V_REFcan be powered at any ꢀme and have no power-up sequencing requirements.

The recommended power-on sequence to achieve minimum current draw for the GTH or GTY transceivers is

V_CCINT, V_MGTAVCC, V_MGTAVTTOR V_MGTAVCC, V_CCINT, V_MGTAVTT. There is no recommended sequencing for

V_MGTVCCAUX. Both V_MGTAVCCand V_CCINTcan be ramped simultaneously. The recommended power-oﬀ sequence

is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences

are not met, current drawn from V_MGTAVTTcan be higher than speciꢁcaꢀons during power-up and power-down.

PS-PL Power Sequencing

The PS and PL power supplies are fully independent. All PS power supplies can be powered before or aꢂer any

PL power supplies. The PS and PL power regions are isolated to prevent damage.

Power Supply Requirements

Table 10 shows the minimum current, in addiꢀon to I_CCQmaximum, required by each Zynq UltraScale+ MPSoC

for proper power-on and conꢁguraꢀon. If these current minimums are met, the device powers on aꢂer all

supplies have passed through their power-on reset threshold voltages. The device must not be conꢁgured unꢀl

aꢂer V_CCINTis applied. Once iniꢀalized and conꢁgured, use the Xilinx Power Esꢀmator (XPE) tools to esꢀmate

current drain on these supplies. The XPE spreadsheet tool (download at hꢃp://www.xilinx.com/power) is also

used to esꢀmate power-on current for all supplies.

DS925 (v1.10) February 07, 2018

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13

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 10: Power-on Current by Device

I_CCMin =

I_CCQ

I_CCINTMIN

I_{CCINT_IOMIN}+ I_CCBRAMMIN

I_CCOMIN

I_CCAUXMIN+ I_{CCAUX_IOMIN}

Units

+

I_CCINTQ

+

I_CCBRAMQ+ I_{CCINT_IOQ}

+

I_CCOQ

+

I_CCAUXQ+ I_{CCAUX_IOQ}+

XCZU2

XAZU2

464

155

50

111

mA

XCZU3

XAZU3

464

770

155

257

50

111

386

mA

XCZU4

XAZU4

XCZU5

XAZU5

XCZU6

XCZU7

1800

1514

1800

1961

2242

3433

600

505

50

55

63

96

650

362

mA

XCZU9

600

650

XCZU11

XCZU15

XCZU17

XCZU19

654

709

748

810

1145

1240

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14

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 11: Power Supply Ramp Time

Symbol

Description

Min

Max

Units

T_VCCINT

Ramp time from GND to 95% of V_CCINT

0.2

40

ms

T_{VCCINT_IO}

T_{VCCINT_VCU}

T_VCCO

Ramp time from GND to 95% of V_{CCINT_IO}

Ramp time from GND to 95% of V_{CCINT_VCU}

Ramp time from GND to 95% of V_CCO

T_VCCAUX

Ramp time from GND to 95% of V_CCAUX

Ramp time from GND to 95% of V_CCBRAM

Ramp time from GND to 95% of V_MGTAVCC

Ramp time from GND to 95% of V_MGTAVTT

Ramp time from GND to 95% of V_MGTVCCAUX

Ramp time from GND to 95% of V_{CC_PSINTFP}

Ramp time from GND to 95% of V_{CC_PSINTLP}

Ramp time from GND to 95% of V_{CC_PSAUX}

Ramp time from GND to 95% of V_{CC_PSINTFP_DDR}

Ramp time from GND to 95% of V_{CC_PSADC}

Ramp time from GND to 95% of V_{CC_PSPLL}

Ramp time from GND to 95% of V_{CC_MGTRAVCC}

Ramp time from GND to 95% of V_{CC_MGTRAVTT}

Ramp time from GND to 95% of V_{CCO_PSDDR}

Ramp time from GND to 95% of V_{CC_PSDDR_PLL}

Ramp time from GND to 95% of V_{CCO_PSIO}

T_VCCBRAM

T_MGTAVCC

T_MGTAVTT

T_MGTVCCAUX

T_{VCC_PSINTFP}

T_{VCC_PSINTLP}

T_{VCC_PSAUX}

T_{VCC_PSINTFP_DDR}

T_{VCC_PSADC}

T_{VCC_PSPLL}

T_{PS_MGTRAVCC}

T_{PS_MGTRAVTT}

T_{VCCO_PSDDR}

T_{VCC_PSDDR_PLL}

T_{VCCO_PSIO}

DC Input and Output Levels

Values for V_ILand V_IHare recommended input voltages. Values for I_OLand I_OHare guaranteed over the

recommended operaꢀng condiꢀons at the V_OLand V_OHtest points. Only selected standards are tested. These

are chosen to ensure that all standards meet their speciꢁcaꢀons. The selected standards are tested at a

minimum V_CCOwith the respecꢀve V_OLand V_OHvoltage levels shown. Other standards are sample tested.

PS I/O Levels

Table 12: PS MIO and CONFIG DC Input and Output Levels

V_IL

V, Max

V_IH

V_OL

V_OH

I_OL

I_OH

I/O

Standard¹

V, Min

V, Max

V, Min

mA mA

LVCMOS33

LVCMOS25

LVCMOS18

Notes:

–0.300

0.800

0.700

2.000

1.700

V_{CCO_PSIO}

0.40

0.70

0.45

2.40

1.70

12

–12

V_{CCO_PSIO}+ 0.30

35% V_{CCO_PSIO}

65% V_{CCO_PSIO}

V_{CCO_PSIO}– 0.45

1. Tested according to relevant specifications.

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15

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 13: PS DDR DC Input and Output Levels

2

V_IL

V, Max

V_IH

V_OL

V_OH

I_OLI_OH

mA mA

DDR

Standard¹

V, Min

V, Max

V, Min

DDR4

0.000

V_REF– 0.100

V_REF– 0.090

V_REF+ 0.100

V_REF+ 0.090

V_{CCO_PSDDR}

0.8 x V_{CCO_PSDDR}– 0.150

0.3 x V_{CCO_PSDDR}– 0.150

0.5 x V_{CCO_PSDDR}– 0.175

0.5 x V_{CCO_PSDDR}– 0.150

0.8 x V_{CCO_PSDDR}+ 0.150

0.3 x V_{CCO_PSDDR}+ 0.150

0.5 x V_{CCO_PSDDR}+ 0.175

0.5 x V_{CCO_PSDDR}+ 0.150

10

0.1

8

–0.1

–10

–8

LPDDR4

DDR3

–0.300

0.000

LPDDR3

DDR3L

Notes:

8

–8

–0.300

8

–8

1. Tested according to relevant specifications.

2. DDR4 V_OL/V_OHspecifications are only applicable for DQ/DQS pins.

PL I/O Levels

Table 14: SelectIO DC Input and Output Levels For HD I/O Banks

V_IL

V, Max

V_IH

V_OL

V_OH

I_OL

I_OH

I/O Standard^{1, 2}

V, Min

V, Max

V, Min

mA

HSTL_I

–0.300

V_REF– 0.100

V_REF– 0.130

35% V_CCO

0.700

V_REF+ 0.100

V_REF+ 0.130

65% V_CCO

1.700

V_CCO+ 0.300

3.400

0.400

V_CCO– 0.400

80% V_CCO

8.0

–8.0

HSTL_I_18

HSUL_12

LVCMOS12

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

20% V_CCO

0.400

0.1

–0.1

V_CCO– 0.400

V_CCO– 0.450

V_CCO– 0.400

2.400

Note 3

Note 4

14.25

8.9

Note 3

Note 4

–14.25

–8.9

0.450

0.400

0.800

2.000

0.400

0.800

2.000

3.400

0.400

SSTL12

V_REF– 0.100

V_REF– 0.090

V_REF– 0.100

V_REF– 0.125

V_REF+ 0.100

V_REF+ 0.090

V_REF+ 0.100

V_REF+ 0.125

V_CCO+ 0.300

V_CCO/2 – 0.150

V_CCO/2 – 0.175

V_CCO/2 – 0.470

V_CCO/2 – 0.600

V_CCO/2 + 0.150

V_CCO/2 + 0.175

V_CCO/2 + 0.470

V_CCO/2 + 0.600

SSTL135

SSTL135_II

SSTL15

13.0

–13.0

–8.9

8.9

SSTL15_II

SSTL18_I

SSTL18_II

Notes:

13.0

–13.0

–8.0

8.0

13.4

–13.4

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide

(UG571).

3. Supported drive strengths of 4, 8, or 12 mA in HD I/O banks.

4. Supported drive strengths of 4, 8, 12, or 16 mA in HD I/O banks.

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16

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 15: SelectIO DC Input and Output Levels for HP I/O Banks

V_IL

V, Max

V_IH

V_OL

V_OH

I_OL

I_OH

mA

I/O Standard^{1, 2, 3}

V, Min

V, Max

V, Min

mA

HSTL_I

–0.300

V_REF– 0.100

V_REF– 0.080

V_REF– 0.100

V_REF– 0.130

35% V_CCO

V_REF+ 0.100

V_REF+ 0.080

V_REF+ 0.100

V_REF+ 0.130

65% V_CCO

V_CCO+ 0.300

0.400

25% V_CCO

0.400

V_CCO– 0.400

75% V_CCO

5.8

4.1

–5.8

–4.1

HSTL_I_12

HSTL_I_18

HSUL_12

V_CCO– 0.400

80% V_CCO

6.2

–6.2

20% V_CCO

0.400

0.1

–0.1

LVCMOS12

LVCMOS15

LVCMOS18

LVDCI_15

LVDCI_18

SSTL12

V_CCO– 0.400

V_CCO– 0.450

V_CCO/2 + 0.150

V_CCO/2 + 0.175

V_CCO/2 + 0.470

1.100

Note 4

Note 5

7.0

Note 4

Note 5

–7.0

35% V_CCO

65% V_CCO

0.450

35% V_CCO

65% V_CCO

0.450

35% V_CCO

65% V_CCO

0.450

35% V_CCO

65% V_CCO

0.450

7.0

–7.0

V_REF– 0.100

V_REF– 0.090

V_REF– 0.100

V_REF– 0.125

0.550

V_REF+ 0.100

V_REF+ 0.090

V_REF+ 0.100

V_REF+ 0.125

0.880

V_CCO/2 – 0.150

V_CCO/2 – 0.175

V_CCO/2 – 0.470

0.050

8.0

–8.0

SSTL135

9.0

–9.0

SSTL15

10.0

7.0

–10.0

–7.0

SSTL18_I

MIPI_DPHY_ DCI_LP⁶

0.01

–0.01

Notes:

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide

(UG571).

3. POD10 and POD12 DC input and output levels are shown in Table 16, Table 21, and Table 22.

4. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks.

5. Supported drive strengths of 2, 4, 6, 8, or 12 mA in HP I/O banks.

6. Low-power option for MIPI_DPHY_DCI.

Table 16: DC Input Levels for Single-ended POD10 and POD12 I/O Standards

V_IL

V_IH

I/O Standard^{1, 2}

V, Min

V, Max

V, Min

V, Max

POD10

–0.300

V_REF– 0.068

V_REF+ 0.068

V_CCO+ 0.300

POD12

Notes:

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide

(UG571).

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17

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 17: Differential SelectIO DC Input and Output Levels

3

V_ICM(V)¹

V_ID(V)²

V_ILHS

Min

V_IHHS

Max

V_OCM(V)⁴

V_OD(V)⁵

I/O Standard

Min Typ Max Min Typ Max

SUB_LVDS⁸

LVPECL

0.500 0.900 1.300 0.070

–

0.700 0.900 1.100 0.100 0.150 0.200

0.300 1.200 1.425 0.100 0.350 0.600

–

SLVS_400_18

SLVS_400_25

0.070 0.200 0.330 0.140

–

0.450

–

MIPI_DPHY_

DCI_HS⁹

0.070

–

0.330 0.070

–0.040

0.460

0.150 0.200 0.250 0.140 0.200 0.270

Notes:

1. V_ICMis the input common mode voltage.

2. V_IDis the input differential voltage (Q – Q).

3. V_IHHSand V_ILHSare the single-ended input high and low voltages, respectively.

4. V_OCMis the output common mode voltage.

5.

V_ODis the output differential voltage (Q – Q).

6. LVDS_25 is specified in Table 23.

7. LVDS is specified in Table 24.

8. Only the SUB_LVDS receiver is supported in HD I/O banks.

9. High-speed option for MIPI_DPHY_DCI. The V_IDmaximum is aligned with the standard’s specification. A higher V_IDis acceptable as long

as the V_INspecification is also met.

Table 18: Complementary Differential SelectIO DC Input and Output Levels for HD I/O Banks

V_ICM(V)¹

Typ

V_ID(V)²

V_OL(V)³

Max

V_OH(V)⁴

Min

I_OL

I_OH

mA

I/O Standard

Min

Max

Min

Max

mA

DIFF_HSTL_I

0.300

0.750

0.900

0.600

0.675

0.750

0.900

1.125

1.425

0.850

1.000

1.125

1.425

0.100

–

0.400

V_CCO– 0.400

8.0

–8.0

DIFF_HSTL_I_18

DIFF_HSUL_12

DIFF_SSTL12

DIFF_SSTL135

DIFF_SSTL135_II

DIFF_SSTL15

DIFF_SSTL15_II

DIFF_SSTL18_I

DIFF_SSTL18_II

Notes:

0.400

20% V_CCO

80% V_CCO

0.1

–0.1

(V_CCO/2) – 0.150

(V_CCO/2) – 0.175

(V_CCO/2) – 0.470

(V_CCO/2) – 0.600

(V_CCO/2) + 0.150

(V_CCO/2) + 0.175

(V_CCO/2) + 0.470

(V_CCO/2) + 0.600

14.25

8.9

–14.25

–8.9

13.0

8.9

–13.0

–8.9

13.0

8.0

–13.0

–8.0

13.4

–13.4

1. V_ICMis the input common mode voltage.

2. V_IDis the input differential voltage.

3. V_OLis the single-ended low-output voltage.

4. V_OHis the single-ended high-output voltage.

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18

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 19: Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks

V_ICM(V)²

Typ

V_ID(V)³

V_OL(V)⁴

Max

V_OH(V)⁵

Min

I_OLI_OH

mA mA

I/O Standard¹

Min

Max

Min Max

DIFF_HSTL_I

DIFF_HSTL_I_12

DIFF_HSTL_I_18

DIFF_HSUL_12

DIFF_SSTL12

DIFF_SSTL135

DIFF_SSTL15

DIFF_SSTL18_I

Notes:

0.680

V_CCO/2

(V_CCO/2) + 0.150

0.600 x V_CCO

0.100

–

0.400

V_CCO– 0.400

0.750 x V_CCO

5.8

4.1

6.2

0.1

8.0

9.0

–5.8

–4.1

–6.2

–0.1

–8.0

–9.0

0.400 x V_CCO

0.250 x V_CCO

0.400

(V_CCO/2) – 0.175

(V_CCO/2) – 0.120

(V_CCO/2) – 0.150

(V_CCO/2) – 0.175

(V_CCO/2) + 0.175

(V_CCO/2) + 0.120

(V_CCO/2) + 0.150

(V_CCO/2) + 0.175

V_CCO– 0.400

20% V_CCO

80% V_CCO

(V_CCO/2) – 0.150

(V_CCO/2) – 0.175

(V_CCO/2) – 0.470

(V_CCO/2) + 0.150

(V_CCO/2) + 0.175

(V_CCO/2) + 0.470

10.0 –10.0

7.0

–7.0

1. DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown in Table 20, Table 21, Table 22.

2. V_ICMis the input common mode voltage.

3. V_IDis the input differential voltage.

4. V_OLis the single-ended low-output voltage.

5.

V_OHis the single-ended high-output voltage.

Table 20: DC Input Levels for Differential POD10 and POD12 I/O Standards

V_ICM(V)

V_ID(V)

I/O Standard^{1, 2}

Min

Typ

Max

Min

Max

DIFF_POD10

DIFF_POD12

Notes:

0.63

0.76

0.70

0.84

0.77

0.92

0.14

0.16

–

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide

(UG571).

Table 21: DC Output Levels for Single-ended and Differential POD10 and POD12 Standards

Symbol

Description^{1, 2}

V_OUT

Min

Typ

Max

Units

R_OL

Pull-down resistance

Pull-up resistance

V_{OM_DC}(as described in Table 22)

36

40

44

Ω

R_OH

Notes:

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide

(UG571).

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19

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 22: Definitions for DC Output Levels for Single-ended and Differential POD10 and POD12

Standards

Symbol

Description

All Speed Grades

Units

V_{OM_DC}

DC output Mid measurement level (for IV curve linearity)

0.8 x V_CCO

V

LVDS DC Specifications (LVDS_25)

The LVDS_25 standard is available in the HD I/O banks. See the UltraScale Architecture SelectIO Resources User

Guide (UG571) for more informaꢀon.

Table 23: LVDS_25 DC Specifications

Symbol

DC Parameter

Min

Typ

Max

Units

1

V_CCO

Supply voltage

2.375

100

2.500

350

2.625

600²

V

V_IDIFF

Differential input voltage:

(Q – Q), Q = High

mV

(Q – Q), Q = High

V_ICM

Input common-mode voltage

0.300

1.200

1.425

V

Notes:

1. LVDS_25 in HD I/O banks supports inputs only. LVDS_25 inputs without internal termination have no V_CCOrequirements. Any V_CCOcan be

chosen as long as the input voltage levels do not violate the Recommended Operating Condition (Table 2) specification for the V_INI/O pin

voltage.

2. Maximum V_IDIFFvalue is specified for the maximum V_ICMspecification. With a lower V_ICM, a higher V_DIFFis tolerated only when the

recommended operating conditions and overshoot/undershoot V_INspecifications are maintained.

LVDS DC Specifications (LVDS)

The LVDS standard is available in the HP I/O banks. See the UltraScale Architecture SelectIO Resources User Guide

(UG571) for more informaꢀon.

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20

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 24: LVDS DC Specifications

Symbol

DC Parameter

Conditions

Min

Typ

Max

Units

1

V_CCO

Supply voltage

1.710

247

1.800

350

1.890

454

V

2

V_ODIFF

Differential output voltage:

(Q – Q), Q = High

R_T= 100Ω across Q and Q signals

mV

(Q – Q), Q = High

2

V_OCM

Output common-mode voltage

R_T= 100Ω across Q and Q signals

1.000

100

1.250

350

1.425

600³

V

3

V_IDIFF

Differential output voltage:

(Q – Q), Q = High

mV

(Q – Q), Q = High

4

V_{ICM_DC}

Input common-mode voltage (DC coupling)

Input common-mode voltage (AC coupling)

0.300

0.600

1.200

–

1.425

1.100

V

5

V_{ICM_AC}

Notes:

1. In HP I/O banks, when LVDS is used with input-only functionality, it can be placed in a bank where the V_CCOlevels are different from the

specified level only if internal differential termination is not used. In this scenario, V_CCOmust be chosen to ensure the input pin voltage

levels do not violate the Recommended Operating Condition (Table 2) specification for the V_INI/O pin voltage.

2. V_OCMand V_ODIFFvalues are for LVDS_PRE_EMPHASIS = FALSE.

3. Maximum V_IDIFFvalue is specified for the maximum V_ICMspecification. With a lower V_ICM, a higher V_DIFFis tolerated only when the

recommended operating conditions and overshoot/undershoot V_INspecifications are maintained.

4. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).

5. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2,

EQ_LEVEL3, EQ_LEVEL4.

AC Switching Characteristics

All values represented in this data sheet are based on the speed speciꢁcaꢀons in the Vivado^®Design Suite as

outlined in the following table.

Table 25: Speed Specification Version By Device

2017.4.1

Device

1.18

XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XCZU4CG, XCZU4EG, XCZU4EV, XCZU5CG, XCZU5EG, XCZU5EV, XCZU6CG,

XCZU6EG, XCZU7CG, XCZU7EG, XCZU7EV, XCZU9CG, XCZU9EG, XCZU11EG, XCZU15EG, XCZU17EG, XCZU19EG

XAZU2EG, XAZU3EG, XAZU4EV, XAZU5EV

Switching characterisꢀcs are speciꢁed on a per-speed-grade basis and can be designated as Advance,

Preliminary, or Producꢀon. Each designaꢀon is deꢁned as follows:

• Advance Product Speciꢀcaꢁon: These speciꢁcaꢀons are based on simulaꢀons only and are typically available

soon aꢂer device design speciꢁcaꢀons are frozen. Although speed grades with this designaꢀon are

considered relaꢀvely stable and conservaꢀve, some under-reporꢀng might sꢀll occur.

• Preliminary Product Speciꢀcaꢁon: These speciꢁcaꢀons are based on complete ES (engineering sample)

silicon characterizaꢀon. Devices and speed grades with this designaꢀon are intended to give a beꢃer

indicaꢀon of the expected performance of producꢀon silicon. The probability of under-reporꢀng delays is

greatly reduced as compared to Advance data.

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

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21

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

• Product Speciꢀcaꢁon: These speciꢁcaꢀons are released once enough producꢀon silicon of a parꢀcular

device family member has been characterized to provide full correlaꢀon between speciꢁcaꢀons and devices

over numerous producꢀon lots. There is no under-reporꢀng of delays, and customers receive formal

noꢀꢁcaꢀon of any subsequent changes. Typically, the slowest speed grades transiꢀon to producꢀon before

faster speed grades.

Testing of AC Switching Characteristics

Internal ꢀming parameters are derived from measuring internal test paꢃerns. All AC switching characterisꢀcs

are representaꢀve of worst-case supply voltage and juncꢀon temperature condiꢀons.

For more speciꢁc, more precise, and worst-case guaranteed data, use the values reported by the staꢀc ꢀming

analyzer and back-annotate to the simulaꢀon net list. Unless otherwise noted, values apply to all Zynq

UltraScale+ MPSoCs.

Speed Grade Designations

Since individual family members are produced at diﬀerent ꢀmes, the migraꢀon from one category to another

depends completely on the status of the fabricaꢀon process for each device. Table 26 correlates the current

status of the Zynq UltraScale+ MPSoC on a per speed grade basis. See Table 3 for operaꢀng voltages listed by

speed grade.

Table 26: Speed Grade Designations by Device

Speed Grade, Temperature Ranges, and V_CCINTOperating Voltages¹

Device

Advance

Preliminary

Production

XCZU2CG

XCZU2EG

XCZU3CG

XCZU3EG

XCZU4CG

XCZU4EG

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-3E (V_CCINT= 0.90V)

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

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22

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 26: Speed Grade Designations by Device (cont'd)

Speed Grade, Temperature Ranges, and V_CCINTOperating Voltages¹

Device

Advance

Preliminary

Production

XCZU4EV

-3E (V_CCINT= 0.90V)

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

XCZU5CG

XCZU5EG

XCZU5EV

XCZU6CG

XCZU6EG

XCZU7CG

XCZU7EG

XCZU7EV

XCZU9CG

XCZU9EG

XCZU11EG

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-3E (V_CCINT= 0.90V)

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-3E (V_CCINT= 0.90V)

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-3E (V_CCINT= 0.90V)

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-3E (V_CCINT= 0.90V)

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

DS925 (v1.10) February 07, 2018

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23

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 26: Speed Grade Designations by Device (cont'd)

Speed Grade, Temperature Ranges, and V_CCINTOperating Voltages¹

Device

Advance

Preliminary

Production

XCZU15EG

-3E (V_CCINT= 0.90V)

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

XCZU17EG

XCZU19EG

-3E (V_CCINT= 0.90V)

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

-2E (V_CCINT= 0.85V), -2I (V_CCINT= 0.85V)

-1E (V_CCINT= 0.85V), -1I (V_CCINT= 0.85V)

-2LE (V_CCINT= 0.85V), -2LE (V_CCINT= 0.72V)¹

-1LI (V_CCINT= 0.85V), -1LI (V_CCINT= 0.72V)¹

XAZU2EG

XAZU3EG

-1I (V_CCINT= 0.85V)

-1Q (V_CCINT= 0.85V)

-1LI (V_CCINT= 0.72V)¹

-1I (V_CCINT= 0.85V)

-1Q (V_CCINT= 0.85V)

-1LI (V_CCINT= 0.72V)¹

XAZU4EV

XAZU5EV

Notes:

-1Q (V_CCINT= 0.85V)

-1I (V_CCINT= 0.85V)

-1LI (V_CCINT= 0.72V)¹

-1I (V_CCINT= 0.85V)

-1LI (V_CCINT= 0.72V)¹

1. The lowest power -1L and -2L devices, where V_CCINT= 0.72V, are listed in the Vivado Design Suite as -1LV and -2LV respectively.

Production Silicon and Software Status

In some cases, a parꢀcular family member (and speed grade) is released to producꢀon before a speed

speciꢁcaꢀon is released with the correct label (Advance, Preliminary, Producꢀon). Any labeling discrepancies are

corrected in subsequent speed speciꢁcaꢀon releases.

Table 27 lists the producꢀon released Zynq UltraScale+ MPSoC, speed grade, and the minimum corresponding

supported speed speciꢁcaꢀon version and Vivado soꢂware revisions. The Vivado soꢂware and speed

speciꢁcaꢀons listed are the minimum releases required for producꢀon. All subsequent releases of soꢂware and

speed speciꢁcaꢀons are valid.

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

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24

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 27: Zynq UltraScale+ MPSoC Device Production Software and Speed Specification Release

Speed Grade and V_CCINTOperating Voltages

Device

0.90V

-3

0.85V

-1Q

0.72V

-2

-1

-2L

-1L

-2L

-1L

XCZU2CG

N/A

Vivado tools 2017.1 v1.10

Vivado tools 2017.4 v1.17

Vivado tools 2017.1 v1.10

Vivado tools 2017.4 v1.17

Vivado tools 2017.1 v1.10

Vivado tools 2017.3 v1.15

Vivado tools 2017.2 v1.12

Vivado tools 2017.2.1 v1.13

N/A

Vivado tools 2017.3.1 v1.16

Vivado tools 2017.4.1 v1.18

Vivado tools 2017.3.1 v1.16

Vivado tools 2017.4.1 v1.18

Vivado tools 2017.3.1 v1.16

Vivado tools 2017.4.1 v1.18

Vivado tools 2017.3.1 v1.16

Vivado tools 2017.4 v1.17

XCZU2EG

XCZU3CG

XCZU3EG

XCZU4CG

XCZU4EG

XCZU4EV

XCZU5CG

XCZU5EG

XCZU5EV

XCZU6CG

XCZU6EG

XCZU7CG

XCZU7EG

XCZU7EV

XCZU9CG

XCZU9EG

XCZU11EG

XCZU15EG

XCZU17EG

XCZU19EG

XAZU2EG

N/A

Vivado tools 2017.3 v1.15

N/A

Vivado tools

2017.3.1

v1.16

XAZU3EG

XAZU4EV

XAZU5EV

Notes:

Vivado tools 2017.3 v1.15

Vivado tools

2017.3.1

v1.16

Vivado tools

2017.4 v1.17

Vivado tools

2017.4.1

v1.18

Vivado tools

2017.4 v1.17

Vivado tools

2017.4.1

v1.18

1. See Table 3 for the complete list of operating voltages by speed grade.

2. Blank entries indicate a device and/or speed grade in Advance or Preliminary status.

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Processor System (PS) Performance Characteristics

Table 28: Processor Performance

Speed Grade

Symbol

Description

Units

-3

-2

-1

F_APUMAX

F_RPUMAX

F_GPUMAX

Maximum APU clock frequency

1500

600

1333

533

1200

500

MHz

Maximum RPU clock frequency

Maximum GPU clock frequency

667

600

Table 29: Configuration and Security Unit Performance

Speed Grade

Symbol

Description

Units

-3

-2

-1

F_CSUCIBMAX

Maximum CSU crypto interface block frequency

400

MHz

Table 30: PS DDR Performance

Speed Grade

-2

Memory

Package

Standard

DRAM Type

-3

-1

Units

Min Max Min Max Min Max

DDR4⁴

All FFV packages, FBVB900,

and SFVC784

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

664

2400

2133

1866

2133

1866

1600

1066

2400

2133

1866

1066

664

2400

2133

1866

2133

1866

1600

1066

2400

2133

1866

1066

664

2400

2133

1866

2133

1866

1600

1066

2400

2133

1866

1066

Mb/s

SFVA625

SBVA484

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

Single die package⁷

Dual die package^{6, 7}

Single die package⁷

Dual die package^{6, 7}

Single die package⁷

Dual die package^{6, 7}

LPDDR4⁵

All FFV packages, FBVB900

and SFVC784

SFVA625

SBVA484

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26

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 30: PS DDR Performance (cont'd)

Speed Grade

-2

Memory

Standard

Package

DRAM Type

-3

-1

Units

Min Max Min Max Min Max

DDR3

All FFV packages, FBVB900

and SFVC784

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

664

2133

1866

1600

1866

1600

1333

1066

1866

1600

1333

1600

1333

1066

1600

1333

1066

664

2133

1866

1600

1866

1600

1333

1066

1866

1600

1333

1600

1333

1066

1600

1333

1066

664

2133

1866

1600

1866

1600

1333

1066

1866

1600

1333

1600

1333

1066

1600

1333

1066

Mb/s

SFVA625

SBVA484

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

DDR3L

All FFV packages, FBVB900

and SFVC784

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

SFVA625

SBVA484

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

Single rank component

1 rank DIMM^{1, 2}

2 rank DIMM^{1, 3}

Single die package⁸

Dual die package⁸

Single die package⁸

Dual die package⁸

Single die package⁸

Dual die package⁸

LPDDR3

All FFV packages, FBVB900

and SFVC784

SFVA625

SBVA484

Notes:

1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, and UDIMM.

2. Includes: 1 rank 1 slot, dual-die package 2 rank.

3. Includes: 2 rank 1 slot.

4. The JEDEC JESD79-4B standard for DDR4 SDRAM limits the maximum t_CKto 1.6 ns. Because of this limitation, Xilinx recommends working

with your DRAM vendor to verify support for data rates at or less than 1066 Mb/s.

5. Byte-mode LPDDR4 devices are not supported.

6. Dual die package includes single die with ECC.

7. LPDDR4 support is only available as a 32-bit interface.

8. 64-bit LPDDR3 interface performance values are defined without ECC support.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 31: PS NAND NV-DDR Synchronous Performance

Speed Grade

Memory Standard

Mode

-3

-2

-1

Units

Max

NV-DDR¹

5

4

3

2

1

0

200

166.6

133.3

100

200

166.6

133.3

100

200

166.6

133.3

100

Mb/s

66.6

40

66.6

40

66.6

40

Notes:

1. The PS NAND memory controller interface for NV-DDR switching characteristics meets the requirements of the ONFI 3.1 specification.

Table 32: PS NAND SDR Asynchronous Performance

Speed Grade

Memory Standard

Mode

-3

-2

-1

Units

Max

SDR^{1, 2}

5

4

3

2

1

0

50

40

50

40

50

40

Mb/s

33.3

28.5

20

33.3

28.5

20

33.3

28.5

20

10

Notes:

1. The PS NAND memory controller interface for SDR switching characteristics meets the requirements of the ONFI 3.1 specification.

2. The NAND controller reference clock frequency maximum is 83 MHz.

Table 33: PS-PL Interface Performance

Symbol

Description

Min

Max

Units

F_EMIOGEMCLK

EMIO gigabit Ethernet controller maximum frequency

EMIO SD controller maximum frequency

–

125

25

MHz

F_EMIOSDCLK

F_EMIOSPICLK

F_EMIOTRACECLK

F_FCIDMACLK

F_AXICLK

EMIO SPI controller maximum frequency

25

EMIO trace controller maximum frequency

Flow control interface DMA maximum frequency

Maximum AXI interface performance

125

333

300

F_DPLIVEVIDEO

DisplayPort controller live video interface maximum frequency

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28

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

PS Switching Characteristics

PS Clocks

Table 34: PS Reference Clock Requirements

Symbol

Description¹

Min

Typ

Max

Units

T_RMSJPSCLK

PS_REF_CLK input RMS clock jitter

–

3

ps

T_PJPSCLK

PS_REF_CLK input period jitter (peak-to-peak)

Number of clock cycles = 10,000

50

T_DCPSCLK

T_RFPSCLK

F_PSCLK

PS_REF_CLK duty cycle

45

–

55

2.22

60

%

ns

PS_REF_CLK rise time (20%–80%) and fall time (80%–20%)

PS_REF_CLK frequency

27

MHz

Notes:

1. The values in this table are applicable to alternative PS reference clock inputs ALT_REF_CLK, AUX_REF_CLK, and VIDEO_CLK.

Table 35: PS RTC Crystal Requirements

Symbol

Description¹

Min

Typ

Max

Units

F_XTAL

Parallel resonance crystal frequency

Frequency tolerance

–

–20

–

32.8

–

20

–

KHz

ppm

pF

T_FTXTAL

C_XTAL

Load capacitance for crystal parallel resonance

Crystal ESR (16.8 and 19.2 MHz)

Crystal shunt capacitance

12.5

70

R_ESR

–

KΩ

C_SHUNT

–

1.4

–

pF

Notes:

1. Required board components: Feedback resistor = 4.7 MΩ, PCB and pad capacitance = 1.5 pF, C₁and C₂capacitance = 21 pF.

Table 36: PS PLL Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-2

-1

T_LOCKPSPLL

PLL maximum lock time

100

1600

750

100

1600

750

100

1600

750

µs

F_PSPLLMAX

PLL maximum output frequency

PLL minimum output frequency

PLL maximum VCO frequency

PLL minimum VCO frequency

MHz

F_PSPLLMIN

F_PSPLLVCOMAX

F_PSPLLVCOMIN

3000

1500

3000

1500

3000

1500

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29

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 37: PS Reset Assertion Timing Requirements

Symbol

Description

Min

Typ

Max

Units

T_PSPOR

T_PSRST

Notes:

Required PS_POR_B assertion time¹

10

3

–

µs

Required PS_SRST_B assertion time

PS_REF_CLK Clock Cycles

1. PS_POR_B must be asserted Low at power-up and continue to be asserted for a duration of T_PSPORafter all the PS supply voltages reach

minimum levels. PS_POR_B must be asserted Low for the duration of T_PORwhen the PS and PL power-up at the same time and the

application uses both the PS and PL after power-up.

Table 38: PS Clocks Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-2

-1

F_{TOPSW_MAINMAX}

FPD AXI interconnect clock maximum

frequency

600

533

MHz

F_{TOPSW_LSBUSMAX}

F_GDMAMAX

FPD APB bus clock maximum frequency

100

600

100

600

100

600

MHz

FPD-DMA controller clock maximum frequency

F_DPDMAMAX

DisplayPort controller clock maximum

frequency

F_{LPD_SWITCH_CTRLMAX}

LPD AXI interconnect clock maximum

frequency

600

500

MHz

F_{LPD_LSBUS_CTRLMAX}

F_ADMAMAX

LPD APB bus clock maximum frequency

LPD-DMA maximum frequency

100

600

533

100

500

533

100

500

533

MHz

F_{APLL_TO_LPDMAX}

F_{DPLL_TO_LPDMAX}

F_{VPLL_TO_LPDMAX}

F_{IOPLL_TO_LPDMAX}

F_{RPLL_TO_FPDMAX}

APLL_TO_LPD maximum frequency

DPLL_TO_LPD maximum frequency

VPLL_TO_LPD maximum frequency

IOPLL_TO_LPD maximum frequency

RPLL_TO_FPD maximum frequency

PS Configuration

Table 39: Processor Configuration Access Port Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

F_PCAPCK

Maximum processor configuration access port (PCAP)

frequency

200

150

MHz

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 40: Boundary-Scan Port Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

F_TCK

T_TAPTCK/T_TCKTAP

T_TCKTDO

JTAG clock maximum frequency

TMS and TDI setup and hold

TCK falling edge to TDO output

25

15

5.0/2.0

24

MHz

4.0/2.0

16.1

4.0/2.0

16.1

4.0/2.0

16.1

5.0/2.0

24

ns, Min

ns, Max

Notes:

1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength.

PS Interface Specifications

PS Quad-SPI Controller Interface

Table 41: Generic Quad-SPI Interface

Symbol

Description¹

Load Conditions²

Min

Max

Units

Quad-SPI device clock frequency operating at 150 MHz. Loopback enabled. LVCMOS 1.8V or LVCMOS 3.3V I/O standard.

T_DCQSPICLK1

T_QSPISSSCLK1

T_QSPISCLKSS1

T_QSPICKO1

Quad-SPI clock duty cycle

15 pF

45

5.0

2.9

0.9

1.0

–

55

–

%

ns

Slave select asserted to next clock edge

Clock edge to slave select deasserted

Clock to output delay, all outputs

Setup time, all inputs

–

ns

4.5

–

ns

T_QSPIDCK1

ns

T_QSPICKD1

Hold time, all inputs

–

ns

F_QSPICLK1

Quad-SPI device clock frequency

Quad-SPI reference clock frequency

150

300

MHz

F_QSPIREFCLK1

–

Quad-SPI device clock frequency operating at 100 MHz. Loopback enabled. LVCMOS 1.8V or LVCMOS 3.3V I/O standard.

T_DCQSPICLK2

T_QSPISSSCLK2

T_QSPISCLKSS2

T_QSPICKO2

T_QSPIDCK2

T_QSPICKD2

F_QSPICLK2

Quad-SPI clock duty cycle

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

45

55

–

%

Slave select asserted to next clock edge

Clock edge to slave select deasserted

Clock to output delay, all outputs

Setup time, all inputs

5.0

3.2

2.3

0.0

–

ns

–

ns

–

ns

–

ns

7.4

–

ns

–

ns

Hold time, all inputs

–

ns

–

ns

Quad-SPI device clock frequency

100

MHz

–

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 41: Generic Quad-SPI Interface (cont'd)

Symbol

Description¹

Load Conditions²

Min

Max

Units

F_QSPIREFCLK2

Quad-SPI reference clock frequency

15 pF

30 pF

–

200

MHz

Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 1.8V I/O standard.

T_DCQSPICLK3

T_QSPISSSCLK3

T_QSPISCLKSS3

T_QSPICKO3

Quad-SPI clock duty cycle

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

45

55

–

%

Slave select asserted to next clock edge³

Clock edge to slave select deasserted

Clock to output delay, all outputs

Setup time, all inputs

7.0

5.2

13.4

14.1

0.0

–

ns

–

ns

–

ns

–

ns

14.8

–

ns

T_QSPIDCK3

ns

–

ns

T_QSPICKD3

Hold time, all inputs

–

ns

–

ns

F_QSPIREFCLK3

Quad-SPI reference clock frequency

Quad-SPI clock frequency

160

40

MHz

–

F_QSPICLK3

–

Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 3.3V I/O standard.

T_DCQSPICLK4

T_QSPISSSCLK4

T_QSPISCLKSS4

T_QSPICKO4

T_QSPIDCK4

T_QSPICKD4

F_QSPIREFCLK4

F_QSPICLK4

Quad-SPI clock duty cycle

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

45

55

–

%

Slave select asserted to next clock edge³

Clock edge to slave select deasserted

Clock to output delay, all outputs

Setup time, all inputs

7.0

5.2

13.9

14.9

0.0

–

ns

–

ns

–

ns

–

ns

14.8

–

ns

–

ns

Hold time, all inputs

–

ns

–

ns

Quad-SPI reference clock frequency

Quad-SPI clock frequency

160

40

MHz

–

Notes:

1. The test conditions are configured for the generic Quad-SPI interface at 150/100 MHz with a 12 mA drive strength and fast slew rate.

2. 30 pF loads are for dual-parallel stacked or stacked modes.

3. T_QSPISSSCLK3and T_QSPISSSCLK4are only valid when two reference clock cycles are programmed between the chip select and clock.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 42: Linear Quad-SPI Interface

Symbol

Description¹

Load Conditions²

Min

Max

Units

Quad-SPI device clock frequency operating at 100 MHz. Loopback enabled. LVCMOS 1.8V or LVCMOS 3.3V I/O standard.

T_DCQSPICLK5

T_QSPISSSCLK5

T_QSPISCLKSS5

T_QSPICKO5

Quad-SPI clock duty cycle

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

45

5.0

3.2

2.4

0.0

–

55

–

%

Slave select asserted to next clock edge³

Clock edge to slave select deasserted

Clock to output delay, all outputs

Setup time, all inputs

ns

–

ns

–

ns

–

ns

7.4

–

ns

T_QSPIDCK5

ns

–

ns

T_QSPICKD5

Hold time, all inputs

–

ns

–

ns

F_QSPIREFCLK5

Quad-SPI reference clock frequency

Quad-SPI device clock frequency

200

100

MHz

–

F_QSPICLK5

–

Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 1.8V I/O standard.

T_DCQSPICLK6

T_QSPISSSCLK6

T_QSPISCLKSS6

T_QSPICKO6

Quad-SPI clock duty cycle

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

45

55

–

%

Slave select asserted to next clock edge

Clock edge to slave select deasserted

Clock to output delay, all outputs

Setup time, all inputs

7.0

5.2

13.4

0.0

–

ns

–

ns

–

ns

–

ns

14.8

–

ns

T_QSPIDCK6

ns

–

ns

T_QSPICKD6

Hold time, all inputs

–

ns

–

ns

F_QSPIREFCLK6

Quad-SPI reference clock frequency

Quad-SPI device clock frequency

160

40

MHz

–

F_QSPICLK6

–

Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 3.3V I/O standard.

T_DCQSPICLK7

T_QSPISSSCLK7

T_QSPISCLKSS7

Quad-SPI clock duty cycle

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

45

55

–

%

Slave select asserted to next clock edge

Clock edge to slave select deasserted

7.0

ns

–

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 42: Linear Quad-SPI Interface (cont'd)

Symbol

Description¹

Load Conditions²

Min

Max

Units

T_QSPICKO7

Clock to output delay, all outputs

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

5.2

14.0

0.0

–

14.8

–

ns

T_QSPIDCK7

T_QSPICKD7

F_QSPIREFCLK7

F_QSPICLK7

Notes:

Setup time, all inputs

ns

–

ns

Hold time, all inputs

–

ns

–

ns

Quad-SPI reference clock frequency

Quad-SPI device clock frequency

160

40

MHz

–

1. The test conditions are configured for the linear Quad-SPI interface at 100 MHz with a 12 mA drive strength and fast slew rate.

2. 30 pF loads are for stacked modes.

3. T_QSPISSSCLK5is only valid when two reference clock cycles are programmed between chip select and clock.

PS USB Interface

Table 43: ULPI Interface

Symbol

Description¹

Min

Max

Units

T_ULPIDCK

Input setup to ULPI clock, all inputs

4.5

0

–

ns

T_ULPICKD

T_ULPICKO

F_ULPICLK

Notes:

Input hold to ULPI clock, all inputs

ULPI clock to output valid, all outputs

ULPI reference clock frequency

2.0

–

8.86

60

ns

MHz

1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

PS Gigabit Ethernet Controller Interface

Table 44: RGMII Interface

Symbol

Description¹

Min

Max

Units

T_DCGEMTXCLK

T_GEMTXCKO

T_GEMRXDCK

T_GEMRXCKD

T_MDIOCLK

T_MDIOCKL

T_MDIOCKH

T_MDIODCK

T_MDIOCKD

T_MDIOCKO

F_GETXCLK

Transmit clock duty cycle

TXD output clock to out time

45

–0.5

0.8

400

160

80

55

0.5

–

%

ns

RXD input setup time

ns

RXD input hold time

–

ns

MDC output clock period

MDC low time

–

ns

–

ns

MDC high time

–

ns

MDIO input data setup time

MDIO input data hold time

MDIO output data delay time

RGMII_TX_CLK transmit clock frequency

RGMII_RX_CLK receive clock frequency

Ethernet reference clock frequency

–

ns

0.0

–1.0

–

ns

15

125

ns

MHz

F_GERXCLK

–

F_{ENET_REF_CLK}

Notes:

–

1. The test conditions are configured to the LVCMOS 2.5V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.

PS SD/SDIO Controller Interface

Table 45: SD/SDIO Interface

Symbol

Description¹

Min

Max

Units

SD/SDIO Interface DDR50 Mode

T_DCDDRCLK

T_SDDDRCKO1

T_SDDDRIVW

T_SDDDRDCK2

T_SDDDRCKD2

T_SDDDRCKO2

F_SDDDRCLK

SD device clock duty cycle

Clock to output delay, data²

Input valid data window³

45

1.0

3.5

4.7

1.5

1.0

–

55

6.8

–

%

ns

Input setup time, command

–

ns

Input hold time, command

–

ns

Clock to output delay, command

High-speed mode SD device clock frequency

13.8

50

ns

MHz

SD/SDIO Interface SDR104

T_DCSDHSCLK1

T_SDSDRCKO1

T_SDSDR1IVW

F_SDSDRCLK1

SD device clock duty cycle

40

1.0

0.5

–

60

3.2

–

%

ns

Clock to output delay, all output²

Input valid data window³

UI

SDR104 mode device clock frequency

200

MHz

SD/SDIO Interface SDR50/25

T_DCSDHSCLK2

T_SDSDRCKO2

T_SDSDR2IVW

SD device clock duty cycle

40

1.0

0.3

60

6.8

–

%

ns

UI

Clock to output delay, all outputs²

Input valid data window³

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35

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 45: SD/SDIO Interface (cont'd)

Symbol

Description¹

Min

Max

Units

F_SDSDRCLK2

SDR50 mode device clock frequency

SDR25 mode device clock frequency

SD/SDIO Interface SDR12

–

100

50

MHz

T_DCSDHSCLK3

T_SDSDRCKO3

T_SDSDRDCK3

T_SDSDRCKD3

F_SDSDRCLK3

SD device clock duty cycle

40

1.0

10.0

1.5

–

60

36.8

–

%

ns

Clock to output delay, all outputs

Input setup time, all inputs

ns

Input hold time, all inputs

–

ns

SDR12 mode device clock frequency

25

MHz

SD/SDIO Interface High-Speed Mode

T_DCSDHSCLK

T_SDHSCKO

T_SDHSDIVW

F_SDHSCLK

SD device clock duty cycle

47

2.2

0.35

–

53

13.8

–

%

ns

Clock to output delay, all outputs²

Input valid data window³

UI

High-speed mode SD device clock frequency

50

MHz

SD/SDIO Interface Standard Mode

T_DCSDSCLK

T_SDSCKO

T_SDSDCK

T_SDSCKD

F_SDIDCLK

F_SDSCLK

Notes:

SD device clock duty cycle

45

–2.0

2.0

–

55

4.5

–

%

ns

Clock to output delay, all outputs

Input setup time, all inputs

ns

Input hold time, all inputs

–

ns

Clock frequency in identification mode

Standard SD device clock frequency

400

19

KHz

MHz

–

1. The test conditions SD/SDIO standard mode (default speed mode) use an 8 mA drive strength, fast slew rate, and a 30 pF load. For SD/

SDIO high-speed mode, the test conditions use a 12 mA drive strength, fast slew rate, and a 30 pF load. For other SD/SDIO modes, the

test conditions use a 12 mA drive strength, fast slew rate, and a 15 pF load.

2. This specification is achieved using pre-determined DLL tuning.

3. This specification is required for capturing input data using DLL tuning.

PS eMMC Standard Interface

Table 46: eMMC Standard Interface

Symbol

Description¹

Min

Max

Units

eMMC Standard Interface

T_DCEMMCHSCLK

T_EMMCHSCKO

T_EMMCHSDCK

T_EMMCHSCKD

F_EMMCHSCLK

eMMC clock duty cycle

Clock to output delay, all outputs

45

–2.0

2.0

–

55

4.5

–

%

ns

Input setup time, all inputs

Input hold time, all inputs

eMMC clock frequency

ns

–

ns

25

MHz

eMMC High-Speed SDR Interface

T_DCEMMCHSCLK

T_EMMCHSCKO

T_EMMCHSDIVW

eMMC high-speed SDR clock duty cycle

45

3.2

0.4

55

16.8

–

%

ns

UI

Clock to output delay, all outputs²

Input valid data window³

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 46: eMMC Standard Interface (cont'd)

Symbol

Description¹

Min

Max

Units

F_EMMCHSCLK

eMMC high speed SDR clock frequency

–

50

MHz

eMMC High-Speed DDR Interface

T_DCEMMCDDRCLK

T_EMMCDDRSCKO1

T_EMMCDDRIVW

eMMC high-speed DDR clock duty cycle

45

2.7

3.5

3.2

3.9

2.5

–

55

7.3

–

%

ns

Data clock to output delay²

Input valid data window³

ns

T_EMMCDDRSCKO2

T_EMMCDDRDCK2

T_EMMCDDRCKD2

F_EMMCDDRCLK

Command clock to output delay

Command input setup time

Command input hold time

16

–

ns

–

ns

eMMC high-speed DDR clock frequency

50

MHz

eMMC HS200 Interface

T_{DCEMMCHS200CLK}

T_EMMCHS200CKO

T_EMMCSDR1IVW

F_EMMCHS200CLK

Notes:

eMMC HS200 clock duty cycle

Clock to output delay, all outputs²

Input valid data window³

40

1.0

0.4

–

60

3.4

–

%

ns

UI

eMMC HS200 clock frequency

200

MHz

1. The test conditions for eMMC standard mode use an 8 mA drive strength, fast slew rate, and a 30 pF load. For eMMC high-speed mode,

the test conditions use a 12 mA drive strength, fast slew rate, and a 30 pF load. For other eMMC modes, the test conditions use a 12 mA

drive strength, fast slew rate, and a 15 pF load.

2. This specification is achieved using pre-determined DLL tuning.

3. This specification is required for capturing input data using DLL tuning.

PS I2C Controller Interface

Table 47: I2C Interface

Symbol

Description¹

Min

Max

Units

I2C Fast-mode Interface

T_I2CFCKL

T_I2CFCKH

T_I2CFCKO

T_I2CFDCK

F_I2CFCLK

SCL Low time

1.3

0.6

–

µs

SCL High time

SDA clock to out delay

SDA input setup time

SCL clock frequency

900

–

ns

100

–

ns

400

KHz

I2C Standard-mode Interface

T_I2CSCKL

T_I2CSCKH

T_I2CSCKO

T_I2CSDCK

F_I2CSCLK

Notes:

SCL Low time

4.7

4.0

–

µs

SCL High time

SDA clock to out delay

SDA input setup time

SCL clock frequency

3450

–

ns

250

–

ns

100

KHz

1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

PS SPI Controller Interface

Table 48: SPI Interfaces

Symbol

Description¹

Min

Max

Units

SPI Master Interface

T_DCMSPICLK

T_MSPISSSCLK

T_MSPISCLKSS

T_MSPIDCK

SPI master mode clock duty cycle

45

1²

55

–

%

Slave select asserted to first active clock edge

Last active clock edge to slave select deasserted

Input setup time for MISO

F_{SPI_REF_CLK}cycles

–

F_{SPI_REF_CLK}cycles

–2.0

0.3

–2.0

–

ns

F_MSPICLKcycles

ns

T_MSPICKD

Input hold time for MISO

–

T_MSPICKO

MOSI and slave select clock to out delay

SPI master device clock frequency

SPI reference clock frequency

5.0

50

200

F_MSPICLK

MHz

F_{SPI_REF_CLK}

SPI Slave Interface

T_SSPISSSCLK

T_SSPISCLKSS

T_SSPIDCK

–

MHz

Slave select asserted to first active clock edge

Last active clock edge to slave select deasserted

Input setup time for MOSI

2

–

F_{SPI_REF_CLK}cycles

5.0

1

–

ns

T_SSPICKD

Input hold time for MOSI

–

F_{SPI_REF_CLK}cycles

T_SSPICKO

MISO clock to out delay

0.0

–

13.0

25

200

ns

F_SSPICLK

SPI slave mode device clock frequency

SPI reference clock frequency

MHz

F_{SPI_REF_CLK}

Notes:

–

1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 30 pF load.

2. Valid when two SPI_REF_CLK delays are programmed between CS and CLK for T_MSPISSSCLK, and between CLK and CS for T_MSPISCLKSSin the

SPI delay_reg0 register.

PS CAN Controller Interface

Table 49: CAN Interface

Symbol

Description¹

Min

Max

Units

T_PWCANRX

Receive pulse width

Transmit pulse width

1.0

–

µs

T_PWCANTX

F_{CAN_REF_CLK}

Internally sourced CAN reference clock frequency

Externally sourced CAN reference clock frequency

100

40

MHz

–

Notes:

1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

PS DAP Interface

Table 50: DAP Interface

Symbol

Description^{1, 2}

Min

Max

Units

T_PDAPDCK

T_PDAPCKD

T_PDAPCKO

F_PDAPCLK

Notes:

PS DAP input setup time

PS DAP input hold time

3.0

2.0

–

ns

PS DAP clock to out delay

PS DAP clock frequency

10.86

44

ns

–

MHz

1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.

2. PS DAP interface signals connect to MIO pins.

PS UART Interface

Table 51: UART Interface

Symbol

Description¹

Min

Max

Units

BAUD_TXMAX

Transmit baud rate

Receive baud rate

–

6.25

100

Mb/s

MHz

BAUD_RXMAX

F_{UART_REF_CLK}

Notes:

UART reference clock frequency

1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.

PS General Purpose I/O Interface

Table 52: General Purpose I/O (GPIO) Interface

Symbol

Description

Min

Max

Units

T_PWGPIOH

T_PWGPIOL

Input High pulse width

Input Low pulse width

10 x 1/F_{LPD_LSBUS_CTRLMAX}

–

µs

PS Trace Interface

Table 53: Trace Interface

Symbol

Description¹

Min

Max

Units

T_TCECKO

T_DCTCECLK

F_TCECLK

Trace clock to output delay, all outputs

Trace clock duty cycle

–0.5

45

–

0.5

55

ns

%

Trace clock frequency

125

MHz

Notes:

1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

PS Triple-timer Counter Interface

Table 54: Triple-timer Counter Interface

Symbol

Description

Min

Max

Units

T_PWTTCOCLK

Triple-timer counter output clock pulse width

Triple-timer counter output clock frequency

Triple-timer counter input clock high pulse width

Triple-timer counter input clock low pulse width

Triple-timer counter input clock frequency

60.4

–

ns

MHz

ns

F_TTCOCLK

T_TTCICLKL

T_TTCICLKH

F_TTCICLK

Notes:

–

16.5

1.5 x 1/F_{LPD_LSBUS_CTRLMAX}

–

ns

F_{LPD_LSBUS_CTRLMAX}/3

MHz

1. All timing values assume an ideal external input clock. Your actual timing budget must account for additional external clock jitter.

PS Watchdog Timer Interface

Table 55: Watchdog Timer Interface

Symbol

Description

Min

Max

Units

F_WDTCLK

Watchdog timer input clock frequency

–

100

MHz

PS-GTR Transceiver

Table 56: PS-GTR Transceiver DC Specifications

Symbol

DC Parameter

Conditions

Min

Typ

Max

Units

DV_PPIN

V_IN

Differential peak-to-peak input voltage (external AC coupled)

100

75

–

1200

mV

Single-ended input voltage. Voltage measured at the pin referenced to

GND

V_{PS_MGTRAVCC}

V_CMIN

Common mode input voltage

Differential peak-to-peak output voltage¹

–

0

–

mV

D_VPPOUT

Transmitter output swing is

set to maximum value

800

V_CMOUTAC

R_IN

Common mode output voltage: AC coupled (equation based)

Differential input resistance

V_{PS_MGTRAVCC}– D_VPPOUT/2

mV

Ω

–

100

500

–

R_OUT

Differential output resistance

–

Ω

R_MGTRREF

T_OSKEW

C_EXT

Resistor value between calibration resistor pin to GND

Transmitter output pair (TXP and TXN) intra-pair skew (All packages)

Recommended external AC coupling capacitor²

497.5

502.5

20

–

Ω

–

ps

nF

100

Notes:

1. The output swing and pre-emphasis levels are programmable using the attributes discussed in the Zynq UltraScale+ Device Technical

Reference Manual (UG1085), and can result in values lower than reported in this table.

2. Other values can be used as appropriate to conform to specific protocols and standards.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 57: PS-GTR Transceiver Clock DC Input Level Specification

Symbol

DC Parameter

Min

Typ

Max

Units

V_IDIFF

R_IN

Differential peak-to-peak input voltage

250

–

2000

mV

Ω

Differential input resistance

100

10

–

C_EXT

Required external AC coupling capacitor

–

nF

Table 58: PS-GTR Transceiver Performance

Speed Grade

-2

Symbol

Description

Units

-3

-1

F_GTRMAX

F_GTRMIN

PS-GTR maximum line rate

PS-GTR minimum line rate

6.0

Gb/s

1.25

Table 59: PS-GTR Transceiver PLL/Lock Time Adaptation

Symbol

Description

Min

Typ

Max

Units

T_LOCK

T_DLOCK

Initial PLL lock

Clock recovery phase acquisition and adaptation time

–

0.11

24 x 10⁶

ms

UI

Table 60: PS-GTR Transceiver Reference Clock Switching Characteristics

All Speed Grades

Typ

Symbol

Description

Conditions

Units

Min

Max

F_GCLK

Reference clock frequencies supported

PCI Express

100 MHz

SATA

125 MHz or 150 MHz

26 MHz, 52 MHz, or 100 MHz

27 MHz, 108 MHz, or 135 MHz

125 MHz

USB 3.0

DisplayPort

SGMII

T_RCLK

T_FCLK

T_DCREF

Reference clock rise time

Reference clock fall time

Reference clock duty cycle

20% – 80%

80% – 20%

Transceiver PLL only.

–

200

–

ps

%

40

47.5

60

52.5

USB 3.0 with reference clock

<40 MHz.

–

%

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 61: PS-GTR Transceiver Reference Clock Oscillator Selection Phase Noise Mask

Offset

Frequency

Symbol

Description¹

Min

Typ

Max

Units

PLL_REFCLKMASK

PLL reference clock select phase noise mask at

REFCLK frequency = 25 MHz

100

–

–102

–124

–132

–139

–152

–154

–96

dBc/Hz

1 KHz

10 KHz

100 KHz

1 MHz

10 MHz

100

PLL reference clock select phase noise mask at

REFCLK frequency = 50 MHz

dBc/Hz

1 KHz

–118

–126

–133

–146

–148

–90

10 KHz

100 KHz

1 MHz

10 MHz

100

PLL reference clock select phase noise mask at

REFCLK frequency = 100 MHz

1 KHz

–112

–120

–127

–140

–142

–88

10 KHz

100 KHz

1 MHz

10 MHz

100

PLL reference clock select phase noise mask at

REFCLK frequency = 125 MHz

1 KHz

–110

–118

–125

–138

–140

–86

10 KHz

100 KHz

1 MHz

10 MHz

100

PLL reference clock select phase noise mask at

REFCLK frequency = 150 MHz

1 KHz

–108

–116

–123

–136

–138

10 KHz

100 KHz

1 MHz

10 MHz

Notes:

1. For reference clock frequencies not in this table, use the phase noise mask for the nearest reference clock frequency.

Table 62: PS-GTR Transceiver Transmitter Switching Characteristics

Symbol

Description

Condition

Min

Typ

Max

Units

F_GTRTX

T_RTX

Serial data rate range

TX rise time

1.25

–

6.0

–

Gb/s

ps

20%–80%

80%–20%

–

65

T_FTX

TX fall time

–

ps

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 63: PS-GTR Transceiver Receiver Switching Characteristics

Symbol

Description

Condition

Min

Typ

Max

Units

F_GTRRX

RX_SST

Serial data rate

1.25

–

6

0

Gb/s

ppm

Receiver spread-spectrum

tracking

Modulated at 33 KHz

All data rates

–5000

RX_PPMTOL

Data/REFCLK PPM offset

tolerance

–350

–

350

ppm

Table 64: PCI Express Protocol Characteristics (PS-GTR Transceivers)

Standard

Description¹

Line Rate (Mb/s)

Min

Max

Units

PCI Express Transmitter Jitter Generation

PCI Express Gen 1

PCI Express Gen 2

Total transmitter jitter

2500

5000

–

0.25

UI

PCI Express Receiver High Frequency Jitter Tolerance

PCI Express Gen 1

PCI Express Gen 2²

Total receiver jitter tolerance

Receiver inherent timing error

2500

5000

0.65

0.4

–

UI

Receiver inherent deterministic timing

error

0.3

Notes:

1. Tested per card electromechanical (CEM) methodology.

2. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade.

Table 65: Serial ATA (SATA) Protocol Characteristics (PS-GTR Transceivers)

Standard

Description

Line Rate (Mb/s)

Min

Max

Units

Serial ATA Transmitter Jitter Generation

SATA Gen 1

SATA Gen 2

SATA Gen 3

Total transmitter jitter

1500

3000

6000

–

0.37

0.52

UI

Total transmitter jitter

Serial ATA Receiver High Frequency Jitter Tolerance

SATA Gen 1

SATA Gen 2

SATA Gen 3

Total receiver jitter tolerance

1500

3000

6000

0.27

0.16

–

UI

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 66: DisplayPort Protocol Characteristics (PS-GTR Transceivers)

Standard

Description¹

Line Rate (Mb/s)

Min

Max

Units

DisplayPort Transmitter Jitter Generation

RBR

Total transmitter jitter

1620

2700

5400

–

0.42

0.40

0.58

UI

HBR

Total transmitter jitter

HBR2 D10.2

HBR2 CPAT

Notes:

1. Only the transmitter is supported.

Table 67: USB 3.0 Protocol Characteristics (PS-GTR Transceivers)

Standard

Description

Line Rate (Mb/s)

Min

Max

Units

USB 3.0 Transmitter Jitter Generation

USB 3.0

USB 3.0 Receiver High Frequency Jitter Tolerance

USB 3.0 Total receiver jitter tolerance

Total transmitter jitter

5000

–

0.66

–

UI

0.2

Table 68: Serial-GMII Protocol Characteristics (PS-GTR Transceivers)

Standard

Description

Line Rate (Mb/s)

Min

Max

Units

Serial-GMII Transmitter Jitter Generation

SGMII

Deterministic transmitter jitter

1250

–

0.25

–

UI

Serial-GMII Receiver High Frequency Jitter Tolerance

SGMII

Total receiver jitter tolerance

0.25

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

PS System Monitor Specifications

Table 69: PS SYSMON Specifications

Parameter

Comments

Conditions

Min

Typ

Max

Units

V_{CC_PSADC}= 1.8V ±3%, T_j= –40°C to 100°C, typical values at T_j= 40°C

ADC Accuracy (T_j= –55°C to 125°C) ¹

Resolution

10

–

1

–

1

–

Bits

MS/s

LSBs

Sample rate

RMS code noise

On-chip reference

–

On-Chip Sensor Accuracy

Temperature sensor error

T_j= –55°C to 110°C

T_j= 110°C to 125°C

T_j= –40°C to 125°C

–

±3.5

±5

°C

%

Supply sensor error²

Supply voltages less than or electrically

connected to V_{CC_PSADC}

±1

Supply voltages nominally at 1.8V but with the

potential to go above V_{CC_PSADC}

T_j= –40°C to 125°C

–

±1.5

±2.5

%

Supply voltages nominally in the 2.0V to 3.3V

range

Notes:

1. ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is

enabled.

2. Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified

for when this feature is enabled.

Programmable Logic (PL) Performance Characteristics

This secꢀon provides the performance characterisꢀcs of some common funcꢀons and designs implemented in

the Zynq UltraScale+ MPSoCs. These values are subject to the same guidelines as the AC Switching

Characterisꢀcs secꢀon. In each table, the I/O bank type is either high performance (HP) or high density (HD).

Table 70: LVDS Component Mode Performance

Speed Grade and V_CCINTOperating Voltages

I/O

Bank

Type

0.90V

-3

0.85V

0.72V

Description

Units

-2

-1

-2

-1

Min Max Min Max Min Max Min Max Min Max

LVDS TX DDR (OSERDES 4:1, 8:1)

LVDS TX SDR (OSERDES 2:1, 4:1)

LVDS RX DDR (ISERDES 1:4, 1:8)¹

LVDS RX DDR

HP

HD

HP

HD

0

1250

625

0

1250

625

0

1250

625

0

1250

625

0

1250

625

Mb/s

1250

250

1250

250

1250

250

1250

250

1250

250

LVDS RX SDR (ISERDES 1:2, 1:4)¹

625

LVDS RX SDR

125

Notes:

1. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and

should be removed through PCB routing.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 71: LVDS Native Mode Performance

Speed Grade and V_CCINTOperating Voltages

0.85V 0.72V

I/O

Bank

Type

0.90V

-3³

Description^{1, 2}

DATA_WIDTH

Units

-2³

-1

-2³

-1

Min Max Min Max Min Max Min Max Min Max

LVDS TX DDR

(TX_BITSLICE)

4

8

4

8

4

8

4

8

HP

375

1600

800

375

1600

800

375

1260

630

375

1400

1600

700

375

1260

630

Mb/s

LVDS TX SDR

(TX_BITSLICE)

187.5

375

187.5

375

187.5

375

187.5

375

187.5

375

800

630

800

630

LVDS RX DDR

1600

800

1600

800

1260

630

1400

1600

700

1260

630

(RX_BITSLICE)⁴

375

LVDS RX SDR

187.5

(RX_BITSLICE)⁴

800

630

800

630

Notes:

1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. The performance

values assume a source-synchronous interface.

2. PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the

minimum frequency is PLL_F_VCOMIN/2.

3. In the SBVA484 package, the maximum data rate is 1260 Mb/s for DDR interfaces and 630 Mb/s for SDR interfaces.

4. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and

should be removed through PCB routing.

Table 72: MIPI D-PHY Performance

Speed Grade and V_CCINTOperating Voltages

I/O

Description

Bank

Type

0.90V

-3¹

0.85V

0.72V

Units

-2¹

-1

-2

-1

MIPI D-PHY transmitter or receiver

HP

1500

1260

Mb/s

Notes:

1. In the SBVA484 package, the data rate is 1260 Mb/s.

Table 73: LVDS Native-Mode 1000BASE-X Support

Speed Grade and V_CCINTOperating Voltages

0.85V 0.72V

Description¹

I/O Bank Type

0.90V

-3

-2

-1

-2

-1

1000BASE-X

HP

Yes

Notes:

1. 1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE Std 802.3-2008).

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

The following table provides the maximum data rates for applicable memory standards using the Zynq

UltraScale+ MPSoC memory PHY. Refer to Memory Interfaces for the complete list of memory interface

standards supported and detailed speciꢁcaꢀons. The ꢁnal performance of the memory interface is determined

through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale

Architecture PCB Design User Guide (UG583), electrical analysis, and characterizaꢀon of the system.

Table 74: Maximum Physical Interface (PHY) Rate for Memory Interfaces

Speed Grade and V_CCINTOperating Voltages

Memory

Package¹

DRAM Type

0.90V

-3

0.85V

0.72V

Units

Standard

-2

-1

-2

-1

DDR4

All FFV packages

and FBVB900

Single rank component

1 rank DIMM^{2, 3, 4}

2 rank DIMM^{2, 5}

2666

2400

2133

1600

2400

2133

1866

2133

1866

1600

1066

1866

1600

1066

1866

1600

1333

800

2666

2400

2133

1600

2400

2133

1866

2133

1866

1600

1066

1866

1600

1066

1866

1600

1333

800

2400

2133

1866

1333

2133

1866

1600

2133

1866

1600

1066

1866

1600

1066

1866

1600

1333

800

2400

2133

1866

1333

2133

1866

1600

2133

1866

1600

1066

1866

1600

1066

1866

1600

1333

800

2133

1866

1600

N/A

Mb/s

MHz

4 rank DIMM^{2, 6}

SFVC784

Single rank component

1 rank DIMM^{2, 3}

2 rank DIMM^{2, 5}

1866

1600

1866

1600

1333

800

DDR3

All FFV packages

and FBVB900

Single rank component

1 rank DIMM^{2, 3}

2 rank DIMM^{2, 5}

4 rank DIMM^{2, 6}

SFVC784

Single rank component

1 rank DIMM^{2, 3}

2 rank DIMM^{2, 5}

1600

1333

800

4 rank DIMM^{2, 6}

DDR3L

All FFV packages

and FBVB900

Single rank component

1 rank DIMM^{2, 3}

2 rank DIMM^{2, 5}

1600

1333

1066

606

4 rank DIMM^{2, 6}

SFVC784

Single rank component

1 rank DIMM^{2, 3}

2 rank DIMM^{2, 5}

4 rank DIMM^{2, 6}

Single rank component⁷

1600

1333

800

1600

1333

800

1600

1333

800

1600

1333

800

1600

1333

1066

606

QDR II+

All

633

600

550

RLDRAM 3

All FFV packages

and FBVB900

Single rank component

1200

1066

933

MHz

SFVC784

All

Single rank component

1066

933

800

933

MHz

QDR IV XP

1066

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

www.xilinx.com

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47

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 74: Maximum Physical Interface (PHY) Rate for Memory Interfaces (cont'd)

Speed Grade and V_CCINTOperating Voltages

Memory

Standard

Package¹

DRAM Type

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

LPDDR3

All

Single rank component

1600

Mb/s

Notes:

1. The SBVA484 and SFVA625 packages do not support the PL memory interfaces.

2. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.

3. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.

4. For the DDR4 DDP components at -3 and -2 (V_CCINT= 0.85V) speed grades, the maximum data rate is 2133 Mb/s for six or more DDP

devices. For five or less DDP devices, use the single rank DIMM data rates for the -3 and -2 (V_CCINT= 0.85V) speed grades.

5. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.

6. Includes: 2 rank 2 slot, 4 rank 1 slot.

7. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.

Programmable Logic (PL) Switching Characteristics

Table 75 (IOB high-density (HD)) and Table 76 (IOB high-performance (HP)) summarize the values of standard-

speciꢁc data input delay adjustments, output delays terminaꢀng at pads (based on standard) and 3-state delays.

• T_{INBUF_DELAY_PAD_I}is the delay from IOB pad through the input buﬀer to the I-pin of an IOB pad. The delay

varies depending on the capability of the SelectIO input buﬀer.

• T_{OUTBUF_DELAY_O_PAD}is the delay from the O pin to the IOB pad through the output buﬀer of an IOB pad.

The delay varies depending on the capability of the SelectIO output buﬀer.

• T_{OUTBUF_DELAY_TD_PAD}is the delay from the T pin to the IOB pad through the output buﬀer of an IOB pad,

when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buﬀer. In HP

I/O banks, the internal DCI terminaꢀon turn-on ꢀme is always faster than T_{OUTBUF_DELAY_TD_PAD}when the

DCITERMDISABLE pin is used. In HD I/O banks, the on-die terminaꢀon turn-on ꢀme is always faster than

T_{OUTBUF_DELAY_TD_PAD}when the INTERMDISABLE pin is used.

IOB High Density (HD) Switching Characteristics

Table 75: IOB High Density (HD) Switching Characteristics

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards 0.90V

-3

Units

DIFF_HSTL_I_18_F

DIFF_HSTL_I_18_S

DIFF_HSTL_I_F

0.873 0.978 1.058 0.978 1.058 1.510 1.574 1.718 1.966 2.101 1.160 1.160 1.271 1.515 1.544

0.873 0.978 1.058 0.978 1.058 1.742 1.805 1.950 2.197 2.333 1.748 1.748 1.867 2.103 2.104

0.873 0.978 1.058 0.978 1.058 1.563 1.611 1.762 2.003 2.145 1.313 1.313 1.417 1.668 1.668

0.873 0.978 1.058 0.978 1.058 1.696 1.798 1.913 2.190 2.296 1.630 1.630 1.780 1.985 1.986

0.796 0.911 0.977 0.911 0.977 1.493 1.573 1.703 1.965 2.086 1.222 1.222 1.335 1.577 1.578

0.796 0.911 0.977 0.911 0.977 1.653 1.711 1.864 2.103 2.247 1.536 1.536 1.665 1.891 1.891

0.796 0.906 0.977 0.906 0.977 1.577 1.643 1.792 2.035 2.175 1.285 1.285 1.423 1.640 1.640

ns

DIFF_HSTL_I_S

DIFF_HSUL_12_F

DIFF_HSUL_12_S

DIFF_SSTL12_F

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

www.xilinx.com

[placeholder placeholder place]

48

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 75: IOB High Density (HD) Switching Characteristics (cont'd)

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards 0.90V

-3

Units

DIFF_SSTL12_S

DIFF_SSTL135_F

DIFF_SSTL135_II_F

DIFF_SSTL135_II_S

DIFF_SSTL135_S

DIFF_SSTL15_F

DIFF_SSTL15_II_F

DIFF_SSTL15_II_S

DIFF_SSTL15_S

DIFF_SSTL18_II_F

DIFF_SSTL18_II_S

DIFF_SSTL18_I_F

DIFF_SSTL18_I_S

HSTL_I_18_F

0.796 0.906 0.977 0.906 0.977 1.726 1.784 1.948 2.176 2.331 1.567 1.567 1.706 1.922 1.922

0.807 0.927 0.995 0.927 0.995 1.558 1.625 1.765 2.017 2.148 1.341 1.341 1.458 1.696 1.696

0.807 0.927 0.995 0.927 0.995 1.560 1.623 1.770 2.015 2.153 1.325 1.325 1.470 1.680 1.689

0.807 0.927 0.995 0.927 0.995 1.694 1.768 1.916 2.160 2.299 1.722 1.722 1.911 2.077 2.078

0.807 0.927 0.995 0.927 0.995 1.796 1.869 2.025 2.261 2.408 1.814 1.814 1.976 2.169 2.169

0.840 0.928 1.020 0.928 1.020 1.559 1.628 1.771 2.020 2.154 1.374 1.374 1.483 1.729 1.729

0.840 0.928 1.020 0.928 1.020 1.574 1.622 1.778 2.014 2.161 1.356 1.356 1.442 1.711 1.712

0.840 0.928 1.020 0.928 1.020 1.769 1.821 1.987 2.213 2.370 1.895 1.895 2.047 2.250 2.250

0.840 0.928 1.020 0.928 1.020 1.752 1.824 1.977 2.216 2.360 1.743 1.743 1.907 2.098 2.098

0.873 0.961 1.038 0.961 1.038 1.672 1.729 1.880 2.121 2.263 1.377 1.377 1.492 1.732 1.732

0.873 0.961 1.038 0.961 1.038 1.748 1.796 1.965 2.188 2.348 1.616 1.616 1.800 1.971 1.972

0.873 0.961 1.038 0.961 1.038 1.539 1.609 1.755 2.001 2.138 1.220 1.220 1.313 1.575 1.575

0.873 0.961 1.038 0.961 1.038 1.728 1.786 1.942 2.178 2.325 1.677 1.677 1.836 2.032 2.033

0.854 0.947 1.021 0.947 1.021 1.510 1.574 1.718 1.966 2.101 1.160 1.160 1.271 1.515 1.544

0.854 0.947 1.021 0.947 1.021 1.742 1.805 1.950 2.197 2.333 1.748 1.748 1.867 2.103 2.104

0.748 0.856 0.900 0.856 0.900 1.563 1.611 1.762 2.003 2.145 1.313 1.313 1.417 1.668 1.668

0.748 0.856 0.900 0.856 0.900 1.696 1.798 1.913 2.190 2.296 1.630 1.630 1.780 1.985 1.986

0.712 0.780 0.867 0.780 0.867 1.493 1.573 1.703 1.965 2.086 1.222 1.222 1.335 1.577 1.578

0.712 0.780 0.867 0.780 0.867 1.653 1.711 1.864 2.103 2.247 1.536 1.536 1.665 1.891 1.891

0.761 0.918 0.976 0.918 0.976 1.652 1.689 1.856 2.081 2.239 1.202 1.202 1.317 1.557 1.557

0.761 0.918 0.976 0.918 0.976 1.714 1.742 1.922 2.134 2.305 1.353 1.353 1.478 1.708 1.708

0.761 0.918 0.976 0.918 0.976 1.668 1.714 1.879 2.106 2.262 1.292 1.292 1.432 1.647 1.647

0.761 0.918 0.976 0.918 0.976 2.019 2.073 2.247 2.465 2.630 1.581 1.581 1.717 1.936 1.937

0.761 0.918 0.976 0.918 0.976 1.979 1.979 2.182 2.371 2.565 1.633 1.633 1.772 1.988 1.989

0.761 0.918 0.976 0.918 0.976 2.132 2.205 2.406 2.597 2.789 1.767 1.767 1.928 2.122 2.123

0.775 0.905 0.958 0.905 0.958 1.691 1.713 1.892 2.105 2.275 1.275 1.275 1.428 1.630 1.630

0.775 0.905 0.958 0.905 0.958 1.665 1.722 1.881 2.114 2.264 1.260 1.260 1.407 1.615 1.615

0.775 0.905 0.958 0.905 0.958 1.747 1.825 1.959 2.217 2.342 1.453 1.453 1.557 1.808 1.809

0.775 0.905 0.958 0.905 0.958 1.721 1.778 1.930 2.170 2.313 1.378 1.378 1.458 1.733 1.733

0.775 0.905 0.958 0.905 0.958 1.936 1.991 2.139 2.383 2.522 1.516 1.516 1.648 1.871 1.871

0.775 0.905 0.958 0.905 0.958 2.172 2.172 2.389 2.564 2.772 1.707 1.707 1.888 2.062 2.062

0.775 0.905 0.958 0.905 0.958 2.274 2.313 2.483 2.705 2.866 1.952 1.952 2.123 2.307 2.307

0.775 0.905 0.958 0.905 0.958 2.170 2.170 2.400 2.562 2.783 1.817 1.817 1.984 2.172 2.173

0.810 0.915 0.958 0.915 0.958 1.741 1.805 1.962 2.197 2.345 1.383 1.383 1.471 1.738 1.738

0.810 0.915 0.958 0.915 0.958 1.698 1.785 1.917 2.177 2.300 1.338 1.338 1.446 1.693 1.693

0.810 0.915 0.958 0.915 0.958 1.815 1.868 2.013 2.260 2.396 1.472 1.472 1.599 1.827 1.832

0.810 0.915 0.958 0.915 0.958 1.785 1.797 1.979 2.189 2.362 1.384 1.384 1.487 1.739 1.739

0.810 0.915 0.958 0.915 0.958 2.163 2.201 2.408 2.593 2.791 1.762 1.762 1.894 2.117 2.118

0.810 0.915 0.958 0.915 0.958 2.102 2.173 2.362 2.565 2.745 1.702 1.702 1.834 2.057 2.057

ns

HSTL_I_18_S

HSTL_I_F

HSTL_I_S

HSUL_12_F

HSUL_12_S

LVCMOS12_F_12

LVCMOS12_F_4

LVCMOS12_F_8

LVCMOS12_S_12

LVCMOS12_S_4

LVCMOS12_S_8

LVCMOS15_F_12

LVCMOS15_F_16

LVCMOS15_F_4

LVCMOS15_F_8

LVCMOS15_S_12

LVCMOS15_S_16

LVCMOS15_S_4

LVCMOS15_S_8

LVCMOS18_F_12

LVCMOS18_F_16

LVCMOS18_F_4

LVCMOS18_F_8

LVCMOS18_S_12

LVCMOS18_S_16

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

www.xilinx.com

[placeholder placeholder place]

49

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 75: IOB High Density (HD) Switching Characteristics (cont'd)

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards 0.90V

-3

Units

LVCMOS18_S_4

LVCMOS18_S_8

LVCMOS25_F_12

LVCMOS25_F_16

LVCMOS25_F_4

LVCMOS25_F_8

LVCMOS25_S_12

LVCMOS25_S_16

LVCMOS25_S_4

LVCMOS25_S_8

LVCMOS33_F_12

LVCMOS33_F_16

LVCMOS33_F_4

LVCMOS33_F_8

LVCMOS33_S_12

LVCMOS33_S_16

LVCMOS33_S_4

LVCMOS33_S_8

LVDS_25

0.810 0.915 0.958 0.915 0.958 2.342 2.346 2.567 2.738 2.950 1.951 1.951 2.092 2.306 2.306

0.810 0.915 0.958 0.915 0.958 2.275 2.292 2.511 2.684 2.894 1.848 1.848 2.008 2.203 2.204

0.963 0.988 1.042 0.988 1.042 2.153 2.153 2.453 2.545 2.836 1.692 1.692 1.856 2.047 2.047

0.963 0.988 1.042 0.988 1.042 2.105 2.105 2.406 2.497 2.789 1.623 1.623 1.786 1.978 1.979

0.963 0.988 1.042 0.988 1.042 2.317 2.344 2.554 2.736 2.937 1.842 1.842 2.039 2.197 2.197

0.963 0.988 1.042 0.988 1.042 2.184 2.184 2.516 2.576 2.899 1.726 1.726 1.910 2.081 2.081

0.963 0.988 1.042 0.988 1.042 2.550 2.558 2.840 2.950 3.223 1.971 1.971 2.194 2.326 2.327

0.963 0.988 1.042 0.988 1.042 2.449 2.449 2.740 2.841 3.123 1.852 1.852 2.063 2.207 2.207

0.963 0.988 1.042 0.988 1.042 2.770 2.770 3.066 3.162 3.449 2.224 2.224 2.458 2.579 2.579

0.963 0.988 1.042 0.988 1.042 2.663 2.663 2.963 3.055 3.346 2.091 2.091 2.373 2.446 2.446

1.154 1.154 1.213 1.154 1.213 2.415 2.415 2.651 2.807 3.034 1.754 1.754 1.915 2.109 2.109

1.154 1.154 1.213 1.154 1.213 2.381 2.383 2.603 2.775 2.986 1.734 1.734 1.869 2.089 2.089

1.154 1.154 1.213 1.154 1.213 2.541 2.541 2.765 2.933 3.148 1.932 1.932 2.135 2.287 2.287

1.154 1.154 1.213 1.154 1.213 2.603 2.603 2.822 2.995 3.205 1.937 1.937 2.130 2.292 2.294

1.154 1.154 1.213 1.154 1.213 2.705 2.705 3.047 3.097 3.430 2.049 2.049 2.318 2.404 2.404

1.154 1.154 1.213 1.154 1.213 2.714 2.714 3.024 3.106 3.407 2.028 2.028 2.232 2.383 2.383

1.154 1.154 1.213 1.154 1.213 2.999 2.999 3.340 3.391 3.723 2.320 2.320 2.610 2.675 2.675

1.154 1.154 1.213 1.154 1.213 2.929 2.929 3.260 3.321 3.643 2.260 2.260 2.532 2.615 2.616

ns

0.980 1.003 1.116 1.003 1.116

N/A

LVPECL

LVTTL_F_12

1.164 1.164 1.223 1.164 1.223 2.415 2.415 2.651 2.807 3.034 1.754 1.754 1.915 2.109 2.109

1.164 1.164 1.223 1.164 1.223 2.464 2.464 2.732 2.856 3.115 1.750 1.750 1.986 2.105 2.117

1.164 1.164 1.223 1.164 1.223 2.541 2.541 2.765 2.933 3.148 1.932 1.932 2.135 2.287 2.287

1.164 1.164 1.223 1.164 1.223 2.582 2.582 2.787 2.974 3.170 1.910 1.910 2.063 2.265 2.265

1.164 1.164 1.223 1.164 1.223 2.731 2.731 3.075 3.123 3.458 2.072 2.072 2.343 2.427 2.427

1.164 1.164 1.223 1.164 1.223 2.714 2.714 3.024 3.106 3.407 2.028 2.028 2.232 2.383 2.383

1.164 1.164 1.223 1.164 1.223 2.999 2.999 3.340 3.391 3.723 2.320 2.320 2.610 2.675 2.675

1.164 1.164 1.223 1.164 1.223 2.929 2.929 3.260 3.321 3.643 2.260 2.260 2.532 2.615 2.616

LVTTL_F_16

LVTTL_F_4

LVTTL_F_8

LVTTL_S_12

LVTTL_S_16

LVTTL_S_4

LVTTL_S_8

SLVS_400_25

SSTL12_F

0.998 1.020 1.136 1.020 1.136

N/A

0.712 0.780 0.867 0.780 0.867 1.577 1.643 1.792 2.035 2.175 1.285 1.285 1.423 1.640 1.640

0.712 0.780 0.867 0.780 0.867 1.726 1.784 1.948 2.176 2.331 1.567 1.567 1.706 1.922 1.922

0.731 0.798 0.881 0.798 0.881 1.558 1.625 1.765 2.017 2.148 1.341 1.341 1.458 1.696 1.696

0.731 0.798 0.881 0.798 0.881 1.574 1.623 1.770 2.015 2.153 1.325 1.325 1.470 1.680 1.689

0.731 0.798 0.881 0.798 0.881 1.694 1.768 1.916 2.160 2.299 1.722 1.722 1.911 2.077 2.078

0.731 0.798 0.881 0.798 0.881 1.796 1.869 2.025 2.261 2.408 1.814 1.814 1.976 2.169 2.169

0.731 0.838 0.880 0.838 0.880 1.544 1.612 1.754 2.004 2.137 1.357 1.357 1.464 1.712 1.713

0.731 0.838 0.880 0.838 0.880 1.588 1.622 1.778 2.014 2.161 1.356 1.356 1.442 1.711 1.712

0.731 0.838 0.880 0.838 0.880 1.769 1.821 1.987 2.213 2.370 1.895 1.895 2.047 2.250 2.250

0.731 0.838 0.880 0.838 0.880 1.752 1.824 1.977 2.216 2.360 1.743 1.743 1.907 2.098 2.098

SSTL12_S

SSTL135_F

SSTL135_II_F

SSTL135_II_S

SSTL135_S

SSTL15_F

SSTL15_II_F

SSTL15_II_S

SSTL15_S

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

www.xilinx.com

[placeholder placeholder place]

50

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 75: IOB High Density (HD) Switching Characteristics (cont'd)

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards 0.90V

-3

Units

SSTL18_II_F

SSTL18_II_S

SSTL18_I_F

SSTL18_I_S

SUB_LVDS

0.854 0.947 1.021 0.947 1.021 1.699 1.729 1.880 2.121 2.263 1.377 1.377 1.492 1.732 1.732

0.854 0.947 1.021 0.947 1.021 1.748 1.796 1.965 2.188 2.348 1.616 1.616 1.800 1.971 1.972

0.854 0.947 1.021 0.947 1.021 1.566 1.609 1.755 2.001 2.138 1.220 1.220 1.313 1.575 1.575

0.854 0.947 1.021 0.947 1.021 1.745 1.786 1.942 2.178 2.325 1.677 1.677 1.836 2.032 2.033

ns

0.871 1.002 1.036 1.002 1.036

N/A

IOB High Performance (HP) Switching Characteristics

Table 76: IOB High Performance (HP) Switching Characteristics

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards

0.90V

-3

Units

DIFF_HSTL_I_12_F

DIFF_HSTL_I_12_M

DIFF_HSTL_I_12_S

DIFF_HSTL_I_18_F

DIFF_HSTL_I_18_M

DIFF_HSTL_I_18_S

DIFF_HSTL_I_DCI_12_F

0.288 0.394 0.402 0.394 0.402 0.410 0.423 0.443 0.423 0.443 0.514 0.553 0.582 0.553 0.582

0.288 0.394 0.402 0.394 0.402 0.552 0.552 0.583 0.552 0.583 0.632 0.641 0.679 0.641 0.679

0.288 0.394 0.402 0.394 0.402 0.752 0.752 0.800 0.752 0.800 0.813 0.813 0.868 0.813 0.868

0.259 0.319 0.339 0.319 0.339 0.439 0.456 0.474 0.456 0.474 0.549 0.576 0.606 0.576 0.606

0.259 0.319 0.339 0.319 0.339 0.563 0.570 0.603 0.570 0.603 0.636 0.653 0.692 0.653 0.692

0.259 0.319 0.339 0.319 0.339 0.782 0.782 0.834 0.782 0.834 0.816 0.816 0.871 0.816 0.871

0.288 0.394 0.402 0.394 0.402 0.393 0.406 0.429 0.406 0.429 0.502 0.534 0.564 0.534 0.564

ns

DIFF_HSTL_I_DCI_12_M 0.288 0.394 0.402 0.394 0.402 0.546 0.557 0.587 0.557 0.587 0.636 0.653 0.694 0.653 0.694

DIFF_HSTL_I_DCI_12_S

DIFF_HSTL_I_DCI_18_F

0.288 0.394 0.402 0.394 0.402 0.755 0.755 0.806 0.755 0.806 0.842 0.842 0.907 0.842 0.907

0.259 0.323 0.339 0.323 0.339 0.422 0.445 0.461 0.445 0.461 0.509 0.566 0.595 0.566 0.595

DIFF_HSTL_I_DCI_18_M 0.259 0.323 0.339 0.323 0.339 0.546 0.555 0.586 0.555 0.586 0.626 0.643 0.684 0.643 0.684

DIFF_HSTL_I_DCI_18_S

DIFF_HSTL_I_DCI_F

DIFF_HSTL_I_DCI_M

DIFF_HSTL_I_DCI_S

DIFF_HSTL_I_F

0.259 0.323 0.339 0.323 0.339 0.762 0.762 0.818 0.762 0.818 0.836 0.836 0.900 0.836 0.900

0.335 0.397 0.417 0.397 0.417 0.407 0.431 0.445 0.431 0.445 0.517 0.555 0.575 0.555 0.575

0.335 0.397 0.417 0.397 0.417 0.549 0.553 0.583 0.553 0.583 0.634 0.644 0.684 0.644 0.684

0.335 0.397 0.417 0.397 0.417 0.767 0.767 0.823 0.767 0.823 0.848 0.848 0.912 0.848 0.912

0.304 0.404 0.417 0.404 0.417 0.409 0.423 0.443 0.423 0.443 0.514 0.549 0.581 0.549 0.581

0.304 0.404 0.417 0.404 0.417 0.549 0.555 0.586 0.555 0.586 0.624 0.640 0.677 0.640 0.677

0.304 0.404 0.417 0.404 0.417 0.767 0.767 0.818 0.767 0.818 0.811 0.811 0.866 0.811 0.866

0.320 0.381 0.400 0.381 0.400 0.411 0.425 0.443 0.425 0.443 0.520 0.558 0.586 0.558 0.586

0.320 0.381 0.400 0.381 0.400 0.546 0.557 0.587 0.557 0.587 0.636 0.653 0.694 0.653 0.694

0.320 0.381 0.400 0.381 0.400 0.737 0.737 0.787 0.737 0.787 0.822 0.822 0.885 0.822 0.885

0.322 0.394 0.402 0.394 0.402 0.394 0.412 0.430 0.412 0.430 0.494 0.538 0.566 0.538 0.566

0.322 0.394 0.402 0.394 0.402 0.552 0.552 0.583 0.552 0.583 0.632 0.641 0.679 0.641 0.679

0.322 0.394 0.402 0.394 0.402 0.752 0.752 0.800 0.752 0.800 0.813 0.813 0.868 0.813 0.868

DIFF_HSTL_I_M

DIFF_HSTL_I_S

DIFF_HSUL_12_DCI_F

DIFF_HSUL_12_DCI_M

DIFF_HSUL_12_DCI_S

DIFF_HSUL_12_F

DIFF_HSUL_12_M

DIFF_HSUL_12_S

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

www.xilinx.com

[placeholder placeholder place]

51

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 76: IOB High Performance (HP) Switching Characteristics (cont'd)

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards

0.90V

-3

Units

DIFF_POD10_DCI_F

DIFF_POD10_DCI_M

DIFF_POD10_DCI_S

DIFF_POD10_F

0.289 0.411 0.430 0.411 0.430 0.407 0.425 0.444 0.425 0.444 0.512 0.555 0.584 0.555 0.584

0.289 0.411 0.430 0.411 0.430 0.533 0.542 0.571 0.542 0.571 0.618 0.640 0.681 0.640 0.681

0.289 0.411 0.430 0.411 0.430 0.754 0.754 0.815 0.754 0.815 0.850 0.850 0.917 0.850 0.917

0.288 0.411 0.433 0.411 0.433 0.425 0.438 0.459 0.438 0.459 0.531 0.569 0.601 0.569 0.601

0.288 0.411 0.433 0.411 0.433 0.519 0.538 0.568 0.538 0.568 0.589 0.630 0.667 0.630 0.667

0.288 0.411 0.433 0.411 0.433 0.752 0.766 0.821 0.766 0.821 0.821 0.836 0.894 0.836 0.894

0.320 0.407 0.432 0.407 0.432 0.411 0.425 0.443 0.425 0.443 0.519 0.558 0.586 0.558 0.586

0.320 0.407 0.432 0.407 0.432 0.516 0.543 0.572 0.543 0.572 0.602 0.638 0.678 0.638 0.678

0.320 0.407 0.432 0.407 0.432 0.740 0.772 0.822 0.772 0.822 0.833 0.862 0.929 0.862 0.929

0.305 0.409 0.430 0.409 0.430 0.438 0.455 0.476 0.455 0.476 0.549 0.595 0.626 0.595 0.626

0.305 0.409 0.430 0.409 0.430 0.551 0.551 0.582 0.551 0.582 0.632 0.641 0.679 0.641 0.679

0.305 0.409 0.430 0.409 0.430 0.749 0.767 0.817 0.767 0.817 0.818 0.832 0.889 0.832 0.889

0.303 0.381 0.400 0.381 0.400 0.411 0.425 0.443 0.425 0.443 0.520 0.558 0.586 0.558 0.586

0.303 0.381 0.400 0.381 0.400 0.549 0.557 0.587 0.557 0.587 0.643 0.654 0.694 0.654 0.694

0.303 0.381 0.400 0.381 0.400 0.754 0.754 0.803 0.754 0.803 0.842 0.842 0.908 0.842 0.908

0.288 0.394 0.402 0.394 0.402 0.394 0.412 0.430 0.412 0.430 0.494 0.538 0.566 0.538 0.566

0.288 0.394 0.402 0.394 0.402 0.550 0.553 0.584 0.553 0.584 0.630 0.641 0.676 0.641 0.676

0.288 0.394 0.402 0.394 0.402 0.758 0.758 0.808 0.758 0.808 0.823 0.823 0.879 0.823 0.879

0.303 0.371 0.402 0.371 0.402 0.392 0.411 0.428 0.411 0.428 0.494 0.537 0.565 0.537 0.565

0.303 0.371 0.402 0.371 0.402 0.551 0.551 0.582 0.551 0.582 0.643 0.645 0.685 0.645 0.685

0.303 0.371 0.402 0.371 0.402 0.746 0.746 0.799 0.746 0.799 0.829 0.829 0.893 0.829 0.893

0.289 0.375 0.402 0.375 0.402 0.393 0.408 0.428 0.408 0.428 0.491 0.528 0.561 0.528 0.561

0.289 0.375 0.402 0.375 0.402 0.548 0.555 0.585 0.555 0.585 0.621 0.641 0.679 0.641 0.679

0.289 0.375 0.402 0.375 0.402 0.772 0.772 0.823 0.772 0.823 0.827 0.827 0.878 0.827 0.878

0.335 0.397 0.417 0.397 0.417 0.394 0.412 0.429 0.412 0.429 0.497 0.531 0.563 0.531 0.563

0.335 0.397 0.417 0.397 0.417 0.549 0.553 0.583 0.553 0.583 0.632 0.645 0.685 0.645 0.685

0.335 0.397 0.417 0.397 0.417 0.768 0.768 0.822 0.768 0.822 0.847 0.847 0.912 0.847 0.912

0.304 0.404 0.417 0.404 0.417 0.409 0.424 0.445 0.424 0.445 0.513 0.551 0.577 0.551 0.577

0.304 0.404 0.417 0.404 0.417 0.547 0.554 0.585 0.554 0.585 0.624 0.639 0.677 0.639 0.677

0.304 0.404 0.417 0.404 0.417 0.767 0.767 0.817 0.767 0.817 0.813 0.813 0.867 0.813 0.867

0.256 0.320 0.336 0.320 0.336 0.422 0.445 0.461 0.445 0.461 0.540 0.566 0.595 0.566 0.595

0.256 0.320 0.336 0.320 0.336 0.552 0.554 0.585 0.554 0.585 0.629 0.644 0.683 0.644 0.683

0.256 0.320 0.336 0.320 0.336 0.762 0.762 0.818 0.762 0.818 0.837 0.837 0.899 0.837 0.899

0.256 0.316 0.336 0.316 0.336 0.439 0.454 0.476 0.454 0.476 0.549 0.578 0.608 0.578 0.608

0.256 0.316 0.336 0.316 0.336 0.567 0.571 0.603 0.571 0.603 0.535 0.652 0.692 0.652 0.692

0.256 0.316 0.336 0.316 0.336 0.782 0.782 0.835 0.782 0.835 0.816 0.816 0.870 0.816 0.870

0.336 0.393 0.415 0.393 0.415 0.407 0.425 0.443 0.425 0.443 0.513 0.548 0.579 0.548 0.579

0.336 0.393 0.415 0.393 0.415 0.548 0.552 0.581 0.552 0.581 0.635 0.644 0.684 0.644 0.684

ns

DIFF_POD10_M

DIFF_POD10_S

DIFF_POD12_DCI_F

DIFF_POD12_DCI_M

DIFF_POD12_DCI_S

DIFF_POD12_F

DIFF_POD12_M

DIFF_POD12_S

DIFF_SSTL12_DCI_F

DIFF_SSTL12_DCI_M

DIFF_SSTL12_DCI_S

DIFF_SSTL12_F

DIFF_SSTL12_M

DIFF_SSTL12_S

DIFF_SSTL135_DCI_F

DIFF_SSTL135_DCI_M

DIFF_SSTL135_DCI_S

DIFF_SSTL135_F

DIFF_SSTL135_M

DIFF_SSTL135_S

DIFF_SSTL15_DCI_F

DIFF_SSTL15_DCI_M

DIFF_SSTL15_DCI_S

DIFF_SSTL15_F

DIFF_SSTL15_M

DIFF_SSTL15_S

DIFF_SSTL18_I_DCI_F

DIFF_SSTL18_I_DCI_M

DIFF_SSTL18_I_DCI_S

DIFF_SSTL18_I_F

DIFF_SSTL18_I_M

DIFF_SSTL18_I_S

HSLVDCI_15_F

HSLVDCI_15_M

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

www.xilinx.com

[placeholder placeholder place]

52

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 76: IOB High Performance (HP) Switching Characteristics (cont'd)

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards

0.90V

-3

Units

HSLVDCI_15_S

HSLVDCI_18_F

HSLVDCI_18_M

HSLVDCI_18_S

HSTL_I_12_F

0.336 0.393 0.415 0.393 0.415 0.748 0.748 0.802 0.748 0.802 0.827 0.827 0.890 0.827 0.890

0.367 0.424 0.447 0.424 0.447 0.424 0.445 0.461 0.445 0.461 0.541 0.566 0.595 0.566 0.595

0.367 0.424 0.447 0.424 0.447 0.563 0.567 0.598 0.567 0.598 0.647 0.658 0.699 0.658 0.699

0.367 0.424 0.447 0.424 0.447 0.761 0.761 0.817 0.761 0.817 0.836 0.836 0.900 0.836 0.900

0.322 0.378 0.399 0.378 0.399 0.410 0.423 0.443 0.423 0.443 0.514 0.553 0.582 0.553 0.582

0.322 0.378 0.399 0.378 0.399 0.551 0.551 0.582 0.551 0.582 0.632 0.642 0.679 0.642 0.679

0.322 0.378 0.399 0.378 0.399 0.750 0.750 0.799 0.750 0.799 0.813 0.813 0.868 0.813 0.868

0.258 0.322 0.339 0.322 0.339 0.439 0.456 0.474 0.456 0.474 0.549 0.576 0.606 0.576 0.606

0.258 0.322 0.339 0.322 0.339 0.562 0.569 0.602 0.569 0.602 0.637 0.653 0.692 0.653 0.692

0.258 0.322 0.339 0.322 0.339 0.781 0.781 0.833 0.781 0.833 0.816 0.816 0.871 0.816 0.871

0.322 0.378 0.399 0.378 0.399 0.393 0.406 0.429 0.406 0.429 0.502 0.534 0.564 0.534 0.564

0.322 0.378 0.399 0.378 0.399 0.551 0.556 0.586 0.556 0.586 0.644 0.654 0.694 0.654 0.694

0.322 0.378 0.399 0.378 0.399 0.754 0.754 0.803 0.754 0.803 0.842 0.842 0.907 0.842 0.907

0.258 0.321 0.339 0.321 0.339 0.422 0.445 0.461 0.445 0.461 0.509 0.566 0.595 0.566 0.595

0.258 0.321 0.339 0.321 0.339 0.551 0.554 0.585 0.554 0.585 0.634 0.643 0.684 0.643 0.684

0.258 0.321 0.339 0.321 0.339 0.761 0.761 0.817 0.761 0.817 0.836 0.836 0.900 0.836 0.900

0.288 0.393 0.415 0.393 0.415 0.407 0.431 0.445 0.431 0.445 0.517 0.555 0.575 0.555 0.575

0.288 0.393 0.415 0.393 0.415 0.548 0.552 0.581 0.552 0.581 0.635 0.644 0.684 0.644 0.684

0.288 0.393 0.415 0.393 0.415 0.766 0.766 0.821 0.766 0.821 0.847 0.847 0.912 0.847 0.912

0.322 0.378 0.399 0.378 0.399 0.409 0.423 0.443 0.423 0.443 0.514 0.549 0.581 0.549 0.581

0.322 0.378 0.399 0.378 0.399 0.548 0.554 0.585 0.554 0.585 0.624 0.640 0.677 0.640 0.677

0.322 0.378 0.399 0.378 0.399 0.766 0.766 0.816 0.766 0.816 0.811 0.811 0.866 0.811 0.866

0.319 0.378 0.399 0.378 0.399 0.411 0.425 0.443 0.425 0.443 0.520 0.558 0.586 0.558 0.586

0.319 0.378 0.399 0.378 0.399 0.551 0.556 0.586 0.556 0.586 0.644 0.654 0.694 0.654 0.694

0.319 0.378 0.399 0.378 0.399 0.736 0.736 0.784 0.736 0.784 0.821 0.821 0.886 0.821 0.886

0.305 0.378 0.399 0.378 0.399 0.394 0.412 0.430 0.412 0.430 0.494 0.538 0.566 0.538 0.566

0.305 0.378 0.399 0.378 0.399 0.551 0.551 0.582 0.551 0.582 0.632 0.642 0.679 0.642 0.679

0.305 0.378 0.399 0.378 0.399 0.750 0.750 0.799 0.750 0.799 0.813 0.813 0.868 0.813 0.868

0.443 0.512 0.555 0.512 0.555 0.657 0.672 0.692 0.672 0.692 0.862 0.898 0.922 0.898 0.922

0.443 0.512 0.555 0.512 0.555 0.486 0.504 0.521 0.504 0.521 0.645 0.664 0.693 0.664 0.693

0.443 0.512 0.555 0.512 0.555 0.469 0.485 0.507 0.485 0.507 0.585 0.634 0.669 0.634 0.669

0.443 0.512 0.555 0.512 0.555 0.457 0.465 0.489 0.465 0.489 0.592 0.611 0.666 0.611 0.666

0.443 0.512 0.555 0.512 0.555 0.687 0.708 0.727 0.708 0.727 0.889 0.916 0.945 0.916 0.945

0.443 0.512 0.555 0.512 0.555 0.533 0.550 0.573 0.550 0.573 0.629 0.664 0.690 0.664 0.690

0.443 0.512 0.555 0.512 0.555 0.520 0.527 0.554 0.527 0.554 0.608 0.622 0.652 0.622 0.652

0.443 0.512 0.555 0.512 0.555 0.532 0.540 0.571 0.540 0.571 0.606 0.614 0.649 0.614 0.649

0.443 0.512 0.555 0.512 0.555 0.767 0.767 0.803 0.767 0.803 0.981 0.990 1.024 0.990 1.024

0.443 0.512 0.555 0.512 0.555 0.666 0.666 0.704 0.666 0.704 0.803 0.803 0.848 0.803 0.848

ns

HSTL_I_12_M

HSTL_I_12_S

HSTL_I_18_F

HSTL_I_18_M

HSTL_I_18_S

HSTL_I_DCI_12_F

HSTL_I_DCI_12_M

HSTL_I_DCI_12_S

HSTL_I_DCI_18_F

HSTL_I_DCI_18_M

HSTL_I_DCI_18_S

HSTL_I_DCI_F

HSTL_I_DCI_M

HSTL_I_DCI_S

HSTL_I_F

HSTL_I_M

HSTL_I_S

HSUL_12_DCI_F

HSUL_12_DCI_M

HSUL_12_DCI_S

HSUL_12_F

HSUL_12_M

HSUL_12_S

LVCMOS12_F_2

LVCMOS12_F_4

LVCMOS12_F_6

LVCMOS12_F_8

LVCMOS12_M_2

LVCMOS12_M_4

LVCMOS12_M_6

LVCMOS12_M_8

LVCMOS12_S_2

LVCMOS12_S_4

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

www.xilinx.com

[placeholder placeholder place]

53

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 76: IOB High Performance (HP) Switching Characteristics (cont'd)

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards

0.90V

-3

Units

LVCMOS12_S_6

LVCMOS12_S_8

LVCMOS15_F_12

LVCMOS15_F_2

LVCMOS15_F_4

LVCMOS15_F_6

LVCMOS15_F_8

LVCMOS15_M_12

LVCMOS15_M_2

LVCMOS15_M_4

LVCMOS15_M_6

LVCMOS15_M_8

LVCMOS15_S_12

LVCMOS15_S_2

LVCMOS15_S_4

LVCMOS15_S_6

LVCMOS15_S_8

LVCMOS18_F_12

LVCMOS18_F_2

LVCMOS18_F_4

LVCMOS18_F_6

LVCMOS18_F_8

LVCMOS18_M_12

LVCMOS18_M_2

LVCMOS18_M_4

LVCMOS18_M_6

LVCMOS18_M_8

LVCMOS18_S_12

LVCMOS18_S_2

LVCMOS18_S_4

LVCMOS18_S_6

LVCMOS18_S_8

LVDCI_15_F

0.443 0.512 0.555 0.512 0.555 0.657 0.657 0.695 0.657 0.695 0.732 0.732 0.774 0.732 0.774

0.443 0.512 0.555 0.512 0.555 0.708 0.708 0.761 0.708 0.761 0.745 0.745 0.790 0.745 0.790

0.368 0.414 0.445 0.414 0.445 0.485 0.500 0.522 0.500 0.522 0.584 0.647 0.682 0.647 0.682

0.368 0.414 0.445 0.414 0.445 0.686 0.702 0.722 0.702 0.722 0.893 0.919 0.940 0.919 0.940

0.368 0.414 0.445 0.414 0.445 0.567 0.579 0.601 0.579 0.601 0.727 0.755 0.781 0.755 0.781

0.368 0.414 0.445 0.414 0.445 0.533 0.547 0.569 0.547 0.569 0.684 0.711 0.742 0.711 0.742

0.368 0.414 0.445 0.414 0.445 0.500 0.518 0.538 0.518 0.538 0.635 0.686 0.703 0.686 0.703

0.368 0.414 0.445 0.414 0.445 0.607 0.607 0.644 0.607 0.644 0.637 0.637 0.676 0.637 0.676

0.368 0.414 0.445 0.414 0.445 0.736 0.741 0.770 0.741 0.770 0.929 0.938 0.962 0.938 0.962

0.368 0.414 0.445 0.414 0.445 0.610 0.625 0.651 0.625 0.651 0.733 0.754 0.786 0.754 0.786

0.368 0.414 0.445 0.414 0.445 0.564 0.576 0.604 0.576 0.604 0.655 0.674 0.710 0.674 0.710

0.368 0.414 0.445 0.414 0.445 0.565 0.568 0.601 0.568 0.601 0.634 0.639 0.681 0.639 0.681

0.368 0.414 0.445 0.414 0.445 0.788 0.788 0.855 0.788 0.855 0.695 0.695 0.733 0.695 0.733

0.368 0.414 0.445 0.414 0.445 0.829 0.829 0.864 0.829 0.864 1.038 1.039 1.079 1.039 1.079

0.368 0.414 0.445 0.414 0.445 0.687 0.687 0.725 0.687 0.725 0.813 0.813 0.851 0.813 0.851

0.368 0.414 0.445 0.414 0.445 0.671 0.671 0.710 0.671 0.710 0.726 0.726 0.763 0.726 0.763

0.368 0.414 0.445 0.414 0.445 0.704 0.704 0.755 0.704 0.755 0.721 0.721 0.758 0.721 0.758

0.352 0.418 0.445 0.418 0.445 0.564 0.573 0.601 0.573 0.601 0.696 0.731 0.769 0.731 0.769

0.352 0.418 0.445 0.418 0.445 0.723 0.739 0.760 0.739 0.760 0.918 0.945 0.971 0.945 0.971

0.352 0.418 0.445 0.418 0.445 0.598 0.609 0.630 0.609 0.630 0.749 0.778 0.802 0.778 0.802

0.352 0.418 0.445 0.418 0.445 0.598 0.603 0.633 0.603 0.633 0.781 0.781 0.808 0.781 0.808

0.352 0.418 0.445 0.418 0.445 0.567 0.573 0.600 0.573 0.600 0.712 0.733 0.767 0.733 0.767

0.352 0.418 0.445 0.418 0.445 0.640 0.640 0.678 0.640 0.678 0.670 0.670 0.709 0.670 0.709

0.352 0.418 0.445 0.418 0.445 0.785 0.798 0.822 0.798 0.822 0.986 0.991 1.016 0.991 1.016

0.352 0.418 0.445 0.418 0.445 0.658 0.664 0.693 0.664 0.693 0.786 0.798 0.836 0.798 0.836

0.352 0.418 0.445 0.418 0.445 0.625 0.629 0.663 0.629 0.663 0.727 0.735 0.775 0.735 0.775

0.352 0.418 0.445 0.418 0.445 0.626 0.626 0.661 0.626 0.661 0.705 0.705 0.746 0.705 0.746

0.352 0.418 0.445 0.418 0.445 0.795 0.795 0.861 0.795 0.861 0.683 0.683 0.721 0.683 0.721

0.352 0.418 0.445 0.418 0.445 0.861 0.862 0.897 0.862 0.897 1.061 1.076 1.098 1.076 1.098

0.352 0.418 0.445 0.418 0.445 0.716 0.716 0.758 0.716 0.758 0.829 0.829 0.872 0.829 0.872

0.352 0.418 0.445 0.418 0.445 0.682 0.682 0.724 0.682 0.724 0.724 0.724 0.762 0.724 0.762

0.352 0.418 0.445 0.418 0.445 0.707 0.707 0.760 0.707 0.760 0.709 0.709 0.745 0.709 0.745

0.369 0.425 0.462 0.425 0.462 0.407 0.426 0.443 0.426 0.443 0.514 0.548 0.581 0.548 0.581

0.369 0.425 0.462 0.425 0.462 0.549 0.553 0.582 0.553 0.582 0.632 0.645 0.685 0.645 0.685

0.369 0.425 0.462 0.425 0.462 0.749 0.749 0.803 0.749 0.803 0.821 0.821 0.890 0.821 0.890

0.367 0.414 0.447 0.414 0.447 0.422 0.441 0.459 0.441 0.459 0.541 0.560 0.589 0.560 0.589

0.367 0.414 0.447 0.414 0.447 0.546 0.554 0.585 0.554 0.585 0.622 0.644 0.683 0.644 0.683

0.367 0.414 0.447 0.414 0.447 0.760 0.760 0.818 0.760 0.818 0.837 0.837 0.899 0.837 0.899

ns

LVDCI_15_M

LVDCI_15_S

LVDCI_18_F

LVDCI_18_M

LVDCI_18_S

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 76: IOB High Performance (HP) Switching Characteristics (cont'd)

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

I/O Standards

0.90V

-3

Units

-3

-2

-1

-2

-1

LVDS

0.508 0.539 0.620 0.539 0.620 0.626 0.626 0.662 0.626 0.662

0.305 0.386 0.415 0.386 0.415 0.489 0.502 0.522 0.502 0.522

8.438 8.438 8.792 8.438 8.792 0.895 0.914 0.937 0.914 0.937

960.447

N/A

ns

MIPI_DPHY_DCI_HS

MIPI_DPHY_DCI_LP

POD10_DCI_F

POD10_DCI_M

POD10_DCI_S

POD10_F

N/A

0.336 0.408 0.430 0.408 0.430 0.407 0.425 0.444 0.425 0.444 0.512 0.555 0.584 0.555 0.584

0.336 0.408 0.430 0.408 0.430 0.533 0.542 0.571 0.542 0.571 0.618 0.640 0.681 0.640 0.681

0.336 0.408 0.430 0.408 0.430 0.724 0.754 0.815 0.754 0.815 0.815 0.850 0.917 0.850 0.917

0.336 0.407 0.430 0.407 0.430 0.425 0.438 0.459 0.438 0.459 0.531 0.569 0.601 0.569 0.601

0.336 0.407 0.430 0.407 0.430 0.519 0.538 0.568 0.538 0.568 0.589 0.630 0.667 0.630 0.667

0.336 0.407 0.430 0.407 0.430 0.752 0.766 0.821 0.766 0.821 0.821 0.836 0.894 0.836 0.894

0.336 0.409 0.431 0.409 0.431 0.411 0.425 0.443 0.425 0.443 0.519 0.558 0.586 0.558 0.586

0.336 0.409 0.431 0.409 0.431 0.516 0.543 0.572 0.543 0.572 0.602 0.638 0.678 0.638 0.678

0.336 0.409 0.431 0.409 0.431 0.740 0.772 0.822 0.772 0.822 0.833 0.862 0.929 0.862 0.929

0.336 0.409 0.431 0.409 0.431 0.438 0.455 0.476 0.455 0.476 0.549 0.595 0.626 0.595 0.626

0.336 0.409 0.431 0.409 0.431 0.551 0.551 0.582 0.551 0.582 0.632 0.641 0.679 0.641 0.679

0.336 0.409 0.431 0.409 0.431 0.749 0.767 0.817 0.767 0.817 0.818 0.832 0.889 0.832 0.889

POD10_M

POD10_S

POD12_DCI_F

POD12_DCI_M

POD12_DCI_S

POD12_F

POD12_M

POD12_S

SLVS_400_18

SSTL12_DCI_F

SSTL12_DCI_M

SSTL12_DCI_S

SSTL12_F

0.492 0.539 0.620 0.539 0.620

N/A

0.331 0.381 0.399 0.381 0.399 0.411 0.425 0.443 0.425 0.443 0.520 0.558 0.586 0.558 0.586

0.331 0.381 0.399 0.381 0.399 0.549 0.557 0.587 0.557 0.587 0.643 0.654 0.694 0.654 0.694

0.331 0.381 0.399 0.381 0.399 0.754 0.754 0.803 0.754 0.803 0.842 0.842 0.908 0.842 0.908

0.320 0.403 0.403 0.403 0.403 0.394 0.412 0.430 0.412 0.430 0.494 0.538 0.566 0.538 0.566

0.320 0.403 0.403 0.403 0.403 0.550 0.553 0.584 0.553 0.584 0.630 0.641 0.676 0.641 0.676

0.320 0.403 0.403 0.403 0.403 0.758 0.758 0.808 0.758 0.808 0.823 0.823 0.879 0.823 0.879

0.341 0.366 0.399 0.366 0.399 0.392 0.411 0.428 0.411 0.428 0.494 0.537 0.565 0.537 0.565

0.341 0.366 0.399 0.366 0.399 0.551 0.551 0.582 0.551 0.582 0.643 0.645 0.685 0.645 0.685

0.341 0.366 0.399 0.366 0.399 0.746 0.746 0.799 0.746 0.799 0.829 0.829 0.893 0.829 0.893

0.321 0.378 0.399 0.378 0.399 0.393 0.408 0.428 0.408 0.428 0.491 0.528 0.561 0.528 0.561

0.321 0.378 0.399 0.378 0.399 0.548 0.555 0.585 0.555 0.585 0.621 0.641 0.679 0.641 0.679

0.321 0.378 0.399 0.378 0.399 0.772 0.772 0.823 0.772 0.823 0.827 0.827 0.878 0.827 0.878

0.319 0.402 0.417 0.402 0.417 0.394 0.412 0.429 0.412 0.429 0.497 0.531 0.563 0.531 0.563

0.319 0.402 0.417 0.402 0.417 0.549 0.553 0.583 0.553 0.583 0.632 0.645 0.685 0.645 0.685

0.319 0.402 0.417 0.402 0.417 0.768 0.768 0.822 0.768 0.822 0.847 0.847 0.912 0.847 0.912

0.320 0.371 0.400 0.371 0.400 0.393 0.408 0.428 0.408 0.428 0.494 0.530 0.556 0.530 0.556

0.320 0.371 0.400 0.371 0.400 0.547 0.554 0.585 0.554 0.585 0.624 0.639 0.677 0.639 0.677

0.320 0.371 0.400 0.371 0.400 0.767 0.767 0.817 0.767 0.817 0.813 0.813 0.867 0.813 0.867

0.256 0.329 0.336 0.329 0.336 0.422 0.445 0.461 0.445 0.461 0.540 0.566 0.595 0.566 0.595

0.256 0.329 0.336 0.329 0.336 0.552 0.554 0.585 0.554 0.585 0.629 0.644 0.683 0.644 0.683

0.256 0.329 0.336 0.329 0.336 0.762 0.762 0.818 0.762 0.818 0.837 0.837 0.899 0.837 0.899

0.259 0.316 0.337 0.316 0.337 0.439 0.454 0.476 0.454 0.476 0.549 0.578 0.608 0.578 0.608

SSTL12_M

SSTL12_S

SSTL135_DCI_F

SSTL135_DCI_M

SSTL135_DCI_S

SSTL135_F

SSTL135_M

SSTL135_S

SSTL15_DCI_F

SSTL15_DCI_M

SSTL15_DCI_S

SSTL15_F

SSTL15_M

SSTL15_S

SSTL18_I_DCI_F

SSTL18_I_DCI_M

SSTL18_I_DCI_S

SSTL18_I_F

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55

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 76: IOB High Performance (HP) Switching Characteristics (cont'd)

T_{INBUF_DELAY_PAD_I}

0.85V 0.72V

-2 -1 -2 -1

T_{OUTBUF_DELAY_O_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

T_{OUTBUF_DELAY_TD_PAD}

0.90V 0.85V 0.72V

-3 -2 -1 -2 -1

I/O Standards

0.90V

-3

Units

SSTL18_I_M

SSTL18_I_S

SUB_LVDS

0.259 0.316 0.337 0.316 0.337 0.567 0.571 0.603 0.571 0.603 0.535 0.652 0.692 0.652 0.692

0.259 0.316 0.337 0.316 0.337 0.782 0.782 0.835 0.782 0.835 0.816 0.816 0.870 0.816 0.870

ns

0.508 0.539 0.620 0.539 0.620 0.658 0.660 0.692 0.660 0.692 907.4

969.863

IOB 3-state Output Switching Characteristics

Table 77 speciꢁes the values of T_{OUTBUF_DELAY_TE_PAD}and T_{INBUF_DELAY_IBUFDIS_O}

.

• T_{OUTBUF_DELAY_TE_PAD}is the delay from the T pin to the IOB pad through the output buﬀer of an IOB pad,

when 3-state is enabled (i.e., a high impedance state).

• T_{INBUF_DELAY_IBUFDIS_O}is the IOB delay from IBUFDISABLE to O output.

• In HP I/O banks, the internal DCI terminaꢀon turn-oﬀ ꢀme is always faster than T_{OUTBUF_DELAY_TE_PAD}when

the DCITERMDISABLE pin is used.

• In HD I/O banks, the internal IN_TERM terminaꢀon turn-oﬀ ꢀme is always faster than T_{OUTBUF_DELAY_TE_PAD}

when the INTERMDISABLE pin is used.

Table 77: IOB 3-state Output Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

T_{OUTBUF_DELAY_TE_PAD}

T input to pad high-impedance for HD I/O

banks

6.167

6.318

6.369

6.699

6.752

ns

T input to pad high-impedance for HP I/O

banks

5.330

2.266

0.873

5.330

2.266

0.936

5.341

2.430

1.037

5.330

2.266

0.936

5.341

2.430

1.037

T_{INBUF_DELAY_IBUFDIS_O}

IBUF turn-on time from IBUFDISABLE to O

output for HD I/O banks

IBUF turn-on time from IBUFDISABLE to O

output for HP I/O banks

Input Delay Measurement Methodology

The following table shows the test setup parameters used for measuring input delay.

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56

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 78: Input Delay Measurement Methodology

I/O Standard

Attribute

1, 2

1, 4

1, 3, 5

Description

V_L

V_H

V_MEAS

V_REF

LVCMOS, 1.2V

LVCMOS12

0.1

1.1

0.6

–

LVCMOS, LVDCI, HSLVDCI, 1.5V

LVCMOS15, LVDCI_15,

HSLVDCI_15

0.1

1.4

0.75

–

LVCMOS, LVDCI, HSLVDCI, 1.8V

LVCMOS18, LVDCI_18,

HSLVDCI_18

0.1

1.7

0.9

–

LVCMOS, 2.5V

LVCMOS25

LVCMOS33

LVTTL

0.1

2.4

1.25

1.65

V_REF

0⁶

–

LVCMOS, 3.3V

0.1

3.2

LVTTL, 3.3V

0.1

3.2

–

HSTL (high-speed transceiver logic), class I, 1.2V

HSTL, class I, 1.5V

HSTL_I_12

V_REF– 0.25

V_REF– 0.325

V_REF– 0.4

V_REF– 0.25

V_REF– 0.2875

V_REF– 0.325

V_REF– 0.4

V_REF– 0.2

V_REF– 0.24

0.6 – 0.25

0.75 – 0.325

0.9 – 0.4

V_REF+ 0.25

V_REF+ 0.325

V_REF+ 0.4

V_REF+ 0.25

V_REF+ 0.2875

V_REF+ 0.325

V_REF+ 0.4

V_REF+ 0.2

V_REF+ 0.24

0.6 + 0.25

0.75 + 0.325

0.9 + 0.4

0.6

0.75

0.9

0.6

0.675

0.75

0.9

0.7

0.84

–

HSTL_I

HSTL, class I, 1.8V

HSTL_I_18

HSUL (high-speed unterminated logic), 1.2V

SSTL12 (stub series terminated logic), 1.2V

SSTL135 and SSTL135 class II, 1.35V

SSTL15 and SSTL15 class II, 1.5V

SSTL18, class I and II, 1.8V

POD10, 1.0V

HSUL_12

SSTL12

SSTL135, SSTL135_II

SSTL15, SSTL15_II

SSTL18_I, SSTL18_II

POD10

POD12, 1.2V

POD12

DIFF_HSTL, class I, 1.2V

DIFF_HSTL, class I, 1.5V

DIFF_HSTL, class I, 1.8V

DIFF_HSUL, 1.2V

DIFF_HSTL_I_12

DIFF_HSTL_I

DIFF_HSTL_I_18

DIFF_HSUL_12

DIFF_SSTL12

0⁶

–

0.6 – 0.25

0.675 – 0.2875

0.6 + 0.25

0.675 + 0.2875

–

DIFF_SSTL, 1.2V

–

DIFF_SSTL135 and DIFF_SSTL135 class II, 1.35V

DIFF_SSTL135,

DIFF_SSTL135_II

0⁶

–

DIFF_SSTL15 and DIFF_SSTL15 class II, 1.5V

DIFF_SSTL18_I, DIFF_SSTL18_II, 1.8V

DIFF_SSTL15,

0.75 – 0.325

0.9 – 0.4

0.75 + 0.325

0.9 + 0.4

0⁶

–

DIFF_SSTL15_II

DIFF_SSTL18_I,

DIFF_SSTL18_II

DIFF_POD10, 1.0V

DIFF_POD12, 1.2V

LVDS (low-voltage differential signaling), 1.8V

LVDS_25, 2.5V

DIFF_POD10

DIFF_POD12

LVDS

0.5 – 0.2

0.6 – 0.25

0.5 + 0.2

0.6 + 0.25

0⁶

–

0.9 – 0.125

1.25 – 0.125

0.9 – 0.125

1.25 – 0.125

0.2 – 0.125

0.9 + 0.125

1.25 + 0.125

0.9 + 0.125

1.25 + 0.125

0.2 + 0.125

LVDS_25

SUB_LVDS, 1.8V

SUB_LVDS

SLVS_400_18

SLVS_400_25

LVPECL

SLVS, 1.8V

SLVS, 2.5V

LVPECL, 2.5V

MIPI D-PHY (high speed) 1.2V

MIPI_DPHY_DCI_HS

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57

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 78: Input Delay Measurement Methodology (cont'd)

I/O Standard

Attribute

1, 2

1, 4

1, 3, 5

Description

V_L

V_H

V_MEAS

V_REF

MIPI D-PHY (low power) 1.2V

Notes:

MIPI_DPHY_DCI_LP

0.715 – 0.2

0.715 + 0.2

0⁶

–

1. The input delay measurement methodology parameters for LVDCI/HSLVDCI are the same for LVCMOS standards of the same voltage.

Parameters for all other DCI standards are the same for the corresponding non-DCI standards.

2. Input waveform switches between V_Land V_H.

3. Measurements are made at typical, minimum, and maximum V_REFvalues. Reported delays reflect worst case of these measurements.

V_REFvalues listed are typical.

4. Input voltage level from which measurement starts.

5. This is an input voltage reference that bears no relation to the V_REF/V_MEASparameters found in IBIS models and/or noted in Figure 1.

6. The value given is the differential input voltage.

Output Delay Measurement Methodology

Output delays are measured with short output traces. Standard terminaꢀon was used for all tesꢀng. The

propagaꢀon delay of the trace is characterized separately and subtracted from the ꢁnal measurement, and is

therefore not included in the generalized test setups shown in Figure 1 and Figure 2.

Figure 1: Single-Ended Test Setup

V

REF

R

REF

Output

V

MEAS

(voltage level when taking delay measurement)

C

(probe capacitance)

REF

X16654-072117

Figure 2: Differential Test Setup

Output

+

REF

C

REF

R

V

MEAS

–

X16640-072117

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58

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Parameters V_REF, R_REF, C_REF, and V_MEASfully describe the test condiꢀons for each I/O standard. The most

accurate predicꢀon of propagaꢀon delay in any given applicaꢀon can be obtained through IBIS simulaꢀon, using

this method:

1. Simulate the output driver of choice into the generalized test setup using values from Table 79.

2. Record the ꢀme to V_MEAS

.

3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or

capacitance value to represent the load.

4. Record the ꢀme to V_MEAS

.

5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagaꢀon

delay of the PCB trace.

Table 79: Output Delay Measurement Methodology

1

R_REF

(Ω)

C_REF

(pF)

V_MEAS

(V)

V_REF

(V)

Description

I/O Standard Attribute

LVCMOS, 1.2V

LVCMOS12

1M

50

100

0

0.6

0

LVCMOS, 1.5V

LVCMOS15

0.75

0.9

LVCMOS, 1.8V

LVCMOS18

0

LVCMOS, 2.5V

LVCMOS25

1.25

1.65

V_REF

0²

0

LVCMOS, 3.3V

LVCMOS33

0

LVTTL, 3.3V

LVTTL

0

LVDCI, HSLVDCI, 1.5V

LVDCI, HSLVDCI, 1.8V

LVDCI_15, HSLVDCI_15

LVDCI_15, HSLVDCI_18

HSTL_I_12

0.75

0.9

0.6

0.75

0.9

0.6

0.675

0.75

0.9

1.0

1.2

0.6

0.75

0.9

0.6

0.675

0.75

0.9

1.0

1.2

0

HSTL (high-speed transceiver logic), class I, 1.2V

HSTL, class I, 1.5V

HSTL_I

HSTL, class I, 1.8V

HSTL_I_18

HSUL (high-speed unterminated logic), 1.2V

SSTL12 (stub series terminated logic), 1.2V

SSTL135 and SSTL135 class II, 1.35V

SSTL15 and SSTL15 class II, 1.5V

SSTL18, class I and class II, 1.8V

POD10, 1.0V

HSUL_12

SSTL12

SSTL135, SSTL135_II

SSTL15, SSTL15_II

SSTL18_I, SSTL18_II

POD10

POD12, 1.2V

POD12

DIFF_HSTL, class I, 1.2V

DIFF_HSTL_I_12

DIFF_HSTL_I

DIFF_HSTL, class I, 1.5V

DIFF_HSTL, class I, 1.8V

DIFF_HSTL_I_18

DIFF_HSUL_12

DIFF_SSTL12

DIFF_HSUL, 1.2V

DIFF_SSTL12, 1.2V

DIFF_SSTL135 and DIFF_SSTL135 class II, 1.35V

DIFF_SSTL15 and DIFF_SSTL15 class II, 1.5V

DIFF_SSTL18, class I and II, 1.8V

DIFF_POD10, 1.0V

DIFF_SSTL135, DIFF_SSTL135_II

DIFF_SSTL15, DIFF_SSTL15_II

DIFF_SSTL18_I, DIFF_SSTL18_II

DIFF_POD10

DIFF_POD12, 1.2V

DIFF_POD12

LVDS (low-voltage differential signaling), 1.8V

LVDS

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59

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 79: Output Delay Measurement Methodology (cont'd)

1

R_REF

(Ω)

C_REF

V_MEAS

(V)

V_REF

(V)

Description

I/O Standard Attribute

(pF)

SUB_LVDS, 1.8V

SUB_LVDS

100

1M

0

0²

0

MIPI D-PHY (high speed) 1.2V

MIPI D-PHY (low power) 1.2V

MIPI_DPHY_DCI_HS

MIPI_DPHY_DCI_LP

0.6

Notes:

1. C_REFis the capacitance of the probe, nominally 0 pF.

2. The value given is the differential output voltage.

Block RAM and FIFO Switching Characteristics

Table 80: Block RAM and FIFO Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

Maximum Frequency

F_{MAX_WF_NC}

F_{MAX_RF}

F_{MAX_FIFO}

F_{MAX_ECC}

Block RAM (WRITE_FIRST and NO_CHANGE modes)

Block RAM (READ_FIRST mode)

825

718

825

718

738

637

738

637

645

575

645

575

585

510

585

510

516

460

516

460

MHz

FIFO in all modes without ECC

Block RAM and FIFO in ECC configuration without

PIPELINE

Block RAM and FIFO in ECC configuration with

PIPELINE and Block RAM in WRITE_FIRST or

NO_CHANGE mode

825

495

738

542

645

543

585

577

516

578

MHz

ps

1

T_PW

Minimum pulse width

Block RAM and FIFO Clock-to-Out Delays

T_{RCKO_DO}

T_{RCKO_DO_REG}

Notes:

Clock CLK to DOUT output (without output register)

Clock CLK to DOUT output (with output register)

0.91

0.27

1.02

0.29

1.11

0.30

1.46

0.42

1.53

0.44

ns, Max

1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.

UltraRAM Switching Characteristics

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Zynq UltraScale+ MPSoCs that

include this memory.

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60

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 81: UltraRAM Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

Maximum Frequency

F_MAX

UltraRAM maximum frequency with

OREG_B = True

650

435

528

650

600

400

500

700

575

386

478

730

500

312

404

800

481

303

389

832

MHz

ps

F_{MAX_ECC_NOPIPELINE}

F_{MAX_NOPIPELINE}

UltraRAM maximum frequency with

OREG_B = False and EN_ECC_RD_B = True

UltraRAM maximum frequency with

OREG_B = False and EN_ECC_RD_B = False

1

T_PW

Minimum pulse width

T_RSTPW

Asynchronous reset minimum pulse width. One

cycle required

1 clock cycle

Notes:

1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.

Input/Output Delay Switching Characteristics

Table 82: Input/Output Delay Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

F_REFCLK

Reference clock frequency for IDELAYCTRL

(component mode)

300 to 800

MHz

Reference clock frequency when using

BITSLICE_CONTROL with REFCLK (in native

mode (for RX_BITSLICE only))

300 to 800

Reference clock frequency for

BITSLICE_CONTROL with PLL_CLK (in native

mode)¹

300 to

2666.67

300 to

2666.67

300 to

2400

300 to

2400

300 to

2133

MHz

T_{MINPER_CLK}

Minimum period for IODELAY clock

Minimum reset pulse width

3.195

52.00

3.195

ns

ps

T_{MINPER_RST}

T_{IDELAY_RESOLUTION}

T_{ODELAY_RESOLUTION}

/

IDELAY/ODELAY chain resolution

2.1 to 12

Notes:

1. PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY_MODE = VCO_HALF, the

minimum frequency is PLL_F_VCOMIN/2.

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61

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

DSP48 Slice Switching Characteristics

Table 83: DSP48 Slice Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V¹

Units

-2

-1

-2

-1

Maximum Frequency

F_MAX

With all registers used

891

794

635

577

775

687

544

492

645

571

456

410

644

562

440

395

600

524

413

371

MHz

F_{MAX_PATDET}

With pattern detector

F_{MAX_MULT_NOMREG}

F_{MAX_MULT_NOMREG_PATDET}

Two register multiply without MREG

with pattern detect

F_{MAX_PREADD_NOADREG}

F_{MAX_NOPIPELINEREG}

Without ADREG

655

483

565

410

468

338

453

323

423

304

MHz

Without pipeline registers (MREG,

ADREG)

F_{MAX_NOPIPELINEREG_PATDET}

Without pipeline registers (MREG,

ADREG) with pattern detect

448

379

314

299

280

MHz

Notes:

1. For devices operating at the lower power V_CCINT= 0.72V voltages, DSP cascades that cross clock region boundaries might operate below

the specified F_MAX

.

Clock Buffers and Networks

Table 84: Clock Buffers Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

Global Clock Switching Characteristics (Including BUFGCTRL)

F_MAXMaximum frequency of a global clock tree (BUFG)

Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)

891

775

667

725

667

MHz

F_MAX

Maximum frequency of a global clock buffer with input

divide capability (BUFGCE_DIV)

Global Clock Buffer with Clock Enable (BUFGCE)

F_MAXMaximum frequency of a global clock buffer with clock

891

775

667

512

725

512

667

512

MHz

enable (BUFGCE)

Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)

F_MAX

Maximum frequency of a leaf clock buffer with clock

enable (BUFCE_LEAF)

GTH or GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)

F_MAX

Maximum frequency of a serial transceiver clock buffer

with clock enable and clock input divide capability

512

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62

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

MMCM Switching Characteristics

Table 85: MMCM Specification

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

MMCM_F_INMAX

MMCM_F_INMIN

MMCM_F_INJITTER

MMCM_F_INDUTY

Maximum input clock frequency

1066

10

933

10

800

10

933

10

800

10

MHz

Minimum input clock frequency

Maximum input clock period jitter

Input duty cycle range: 10–49 MHz

Input duty cycle range: 50–199 MHz

Input duty cycle range: 200–399 MHz

Input duty cycle range: 400–499 MHz

Input duty cycle range: >500 MHz

Minimum dynamic phase shift clock frequency

< 20% of clock input period or 1 ns Max

25–75

30–70

35–65

40–60

45–55

%

MMCM_F_{MIN_PSCLK}

MMCM_F_{MAX_PSCLK}

0.01

550

0.01

500

0.01

450

0.01

500

0.01

450

MHz

Maximum dynamic phase shift clock

frequency

MMCM_F_VCOMIN

MMCM_F_VCOMAX

MMCM_F_BANDWIDTH

Minimum MMCM VCO frequency

Maximum MMCM VCO frequency

Low MMCM bandwidth at typical¹

High MMCM bandwidth at typical¹

Static phase offset of the MMCM outputs²

MMCM output jitter.

800

1600

1.00

4.00

0.12

800

1600

1.00

4.00

0.12

800

1600

1.00

4.00

0.12

800

1600

1.00

4.00

0.12

800

1600

1.00

4.00

0.12

MHz

ns

MMCM_T_{STATPHAOFFSET}

MMCM_T_OUTJITTER

MMCM_T_OUTDUTY

MMCM_T_LOCKMAX

Note 3

MMCM output clock duty cycle precision⁴

0.165

100

0.20

100

0.20

100

0.20

100

0.20

100

ns

µs

MMCM maximum lock time for

MMCM_F_PFDMIN

MMCM_F_OUTMAX

MMCM_F_OUTMIN

MMCM_T_EXTFDVAR

MMCM_RST_MINPULSE

MMCM_F_PFDMAX

MMCM maximum output frequency

MMCM minimum output frequency^{4, 5}

External clock feedback variation

Minimum reset pulse width

891

775

667

725

667

MHz

6.25

< 20% of clock input period or 1 ns Max

5.00

550

5.00

500

5.00

450

5.00

500

5.00

450

ns

Maximum frequency at the phase frequency

detector

MHz

MMCM_F_PFDMIN

Minimum frequency at the phase frequency

detector

10

MHz

MMCM_T_FBDELAY

MMCM_F_{DPRCLK_MAX}

Notes:

Maximum delay in the feedback path

Maximum DRP clock frequency

5 ns Max or one clock cycle

250 250

250

MHz

1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2. The static offset is measured between any MMCM outputs with identical phase.

3. Values for this parameter are available in the Clocking Wizard.

4. Includes global clock buffer.

5. Calculated as F_VCO/128 assuming output duty cycle is 50%.

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63

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

PLL Switching Characteristics

Table 86: PLL Specification

Speed Grade and V_CCINTOperating Voltages

Symbol

Description¹

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

PLL_F_INMAX

PLL_F_INMIN

PLL_F_INJITTER

PLL_F_INDUTY

Maximum input clock frequency

Minimum input clock frequency

Maximum input clock period jitter

Input duty cycle range: 70–399 MHz

Input duty cycle range: 400–499 MHz

Input duty cycle range: >500 MHz

Minimum PLL VCO frequency

Maximum PLL VCO frequency

Static phase offset of the PLL outputs²

PLL output jitter.

1066

70

933

70

800

70

933

70

800

70

MHz

< 20% of clock input period or 1 ns Max

35–65

40–60

45–55

%

PLL_F_VCOMIN

750

1500

0.12

750

1500

0.12

750

1500

0.12

750

1500

0.12

750

1500

0.12

MHz

ns

PLL_F_VCOMAX

PLL_T_{STATPHAOFFSET}

PLL_T_OUTJITTER

PLL_T_OUTDUTY

Note 3

PLL CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B

duty-cycle precision⁴

0.165

0.20

ns

PLL_T_LOCKMAX

PLL_F_OUTMAX

PLL maximum lock time

100

667

µs

PLL maximum output frequency at CLKOUT0,

CLKOUT0B, CLKOUT1, CLKOUT1B

891

775

725

667

MHz

PLL maximum output frequency at CLKOUTPHY

2667

5.86

2667

5.86

2400

5.86

2400

5.86

2133

5.86

MHz

PLL_F_OUTMIN

PLL minimum output frequency at CLKOUT0,

CLKOUT0B, CLKOUT1, CLKOUT1B⁵

PLL minimum output frequency at CLKOUTPHY

2 x VCO mode: 1500, 1 x VCO mode: 750, 0.5 x VCO mode:

375

MHz

PLL_RST_MINPULSE

PLL_F_PFDMAX

Minimum reset pulse width

5.00

ns

Maximum frequency at the phase frequency

detector

667.5

MHz

PLL_F_PFDMIN

Minimum frequency at the phase frequency

detector

70

MHz

PLL_F_BANDWIDTH

PLL_F_{DPRCLK_MAX}

Notes:

PLL bandwidth at typical

14

MHz

Maximum DRP clock frequency

250

1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.

2. The static offset is measured between any PLL outputs with identical phase.

3. Values for this parameter are available in the Clocking Wizard.

4. Includes global clock buffer.

5. Calculated as F_VCO/128 assuming output duty cycle is 50%.

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

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64

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Device Pin-to-Pin Output Parameter Guidelines

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the

device. The actual pin-to-pin values will vary if the root placement selected is diﬀerent. Consult the Vivado

Design Suite ꢀming report for the actual pin-to-pin values.

Table 87: Global Clock Input to Output Delay Without MMCM (Near Clock Region)

Speed Grade and V_CCINTOperating

Voltages

Symbol

Description¹

Device

Units

0.90V

-3

0.85V

0.72V

-2

-1

-2

-1

SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM

T_ICKOF

Global clock input and output flip-flop

without MMCM (near clock region)

XCZU2

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

N/A

5.05

5.42

5.96

5.42

5.92

5.58

6.29

N/A

4.90

5.53

5.91

6.54

5.91

6.49

6.09

6.90

N/A

5.28

5.95

6.35

7.01

6.35

6.96

6.55

7.40

5.28

5.95

6.08

6.90

7.48

8.17

7.48

8.16

7.75

8.68

N/A

6.51

7.49

8.03

8.76

8.03

8.91

8.33

9.32

6.51

7.49

ns

Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible I/O and CLB flip-flops are clocked by the global clock net.

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

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65

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 88: Global Clock Input to Output Delay Without MMCM (Far Clock Region)

Speed Grade and V_CCINTOperating Voltages

Symbol

Description¹

Device

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM

T_{ICKOF_FAR}

Global clock input and output flip-flop

without MMCM (far clock region)

XCZU2

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

N/A

5.24

5.91

5.96

5.91

6.29

5.90

6.84

N/A

5.27

5.73

6.49

6.54

6.49

6.91

6.49

7.53

N/A

5.68

6.17

6.97

7.01

6.97

7.41

6.96

8.07

5.68

6.17

6.59

7.17

8.16

8.17

8.16

8.72

8.16

9.52

N/A

7.06

7.79

8.76

9.52

8.77

10.23

7.06

7.79

ns

Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible I/O and CLB flip-flops are clocked by the global clock net.

DS925 (v1.10) February 07, 2018

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66

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 89: Global Clock Input to Output Delay With MMCM

Speed Grade and V_CCINTOperating

Voltages

Symbol

Description^{1, 2}

Device

Units

0.90V

-3

0.85V

0.72V

-2

-1

-2

-1

SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM

T_ICKOFMMCMCC

Global clock input and output flip-flop with

MMCM

XCZU2

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

N/A

1.90

1.83

1.98

1.83

1.96

1.85

2.08

N/A

2.22

2.24

2.15

2.32

2.15

2.30

2.18

2.44

N/A

2.43

2.47

2.36

2.55

2.36

2.51

2.38

2.66

2.43

2.47

2.87

2.90

2.80

3.00

2.80

2.99

2.82

3.15

N/A

3.00

3.08

2.95

3.15

2.95

3.20

2.98

3.33

3.00

3.08

ns

Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible I/O and CLB flip-flops are clocked by the global clock net.

2. MMCM output jitter is already included in the timing calculation.

Device Pin-to-Pin Input Parameter Guidelines

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the

device. The actual pin-to-pin values will vary if the root placement selected is diﬀerent. Consult the Vivado

Design Suite ꢀming report for the actual pin-to-pin values.

DS925 (v1.10) February 07, 2018

Preliminary Product Specification

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67

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 90: Global Clock Input Setup and Hold With 3.3V HD I/O Without MMCM

Speed Grade and V_CCINTOperating

Voltages

Symbol

Description

Device

Units

0.90V

-3

0.85V

0.72V

-2

-1

-2

-1

Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^{1, 2, 3}

T_{PSFD_ZU2}

T_{PHFD_ZU2}

T_{PSFD_ZU3}

T_{PHFD_ZU3}

T_{PSFD_ZU4}

T_{PHFD_ZU4}

T_{PSFD_ZU5}

T_{PHFD_ZU5}

T_{PSFD_ZU6}

T_{PHFD_ZU6}

T_{PSFD_ZU7}

T_{PHFD_ZU7}

T_{PSFD_ZU9}

T_{PHFD_ZU9}

T_{PSFD_ZU11}

T_{PHFD_ZU11}

T_{PSFD_ZU15}

T_{PHFD_ZU15}

T_{PSFD_ZU17}

T_{PHFD_ZU17}

T_{PSFD_ZU19}

T_{PHFD_ZU19}

T_{PSFD_XAZU2}

T_{PHFD_XAZU2}

T_{PSFD_XAZU3}

T_{PHFD_XAZU3}

T_{PSFD_XAZU4}

T_{PHFD_XAZU4}

T_{PSFD_XAZU5}

T_{PHFD_XAZU5}

Notes:

Global clock input and input

flip-flop (or latch) without

MMCM

Setup

Hold

XCZU2

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

N/A

2.27

–0.36

2.27

–0.36

2.30

–0.37

2.30

–0.37

1.79

–0.05

2.32

–0.40

1.79

–0.05

2.28

–0.38

1.79

–0.04

2.29

–0.38

2.29

–0.38

N/A

2.37

3.54

3.82

–1.03

3.82

ns

–0.36

2.37

–1.03

3.54

–1.03

3.56

–1.05

3.56

–1.05

2.85

–0.60

3.59

–1.10

2.85

–0.60

3.54

–1.05

2.84

–0.60

3.56

–1.08

3.56

–1.08

N/A

Setup

Hold

–0.36

2.39

–1.03

3.81

Setup

Hold

2.00

–0.37

2.00

–0.37

1.51

–0.05

2.02

–0.40

1.51

–0.05

1.99

–0.38

1.51

–0.04

2.00

–0.38

2.00

–0.38

N/A

–0.37

2.39

–1.05

3.81

Setup

Hold

–0.37

1.86

–1.05

3.06

Setup

Hold

–0.05

2.42

–0.60

3.87

Setup

Hold

–0.40

1.86

–1.10

3.06

Setup

Hold

–0.05

2.38

–0.60

3.79

Setup

Hold

–0.38

1.85

–1.05

3.05

Setup

Hold

–0.04

2.38

–0.60

3.83

Setup

Hold

–0.38

2.38

–1.08

3.83

Setup

Hold

–0.38

2.37

–1.08

3.82

Setup

Hold

N/A

–0.36

2.37

N/A

–1.03

3.82

Setup

Hold

N/A

–0.36

2.39

N/A

–1.03

3.81

Setup

Hold

N/A

–0.37

2.39

N/A

–1.03

3.81

Setup

Hold

N/A

–0.37

N/A

–1.05

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the

global clock input signal using the fastest process, fastest temperature, and fastest voltage.

2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible I/O and CLB flip-flops are clocked by the global clock net.

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

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68

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 91: Global Clock Input Setup and Hold With MMCM

Speed Grade and V_CCINTOperating

Voltages

Symbol

Description

Device

Units

0.90V

-3

0.85V

0.72V

-2

-1

-2

-1

Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^{1, 2, 3}

T_{PSMMCMCC_ZU2}

T_{PHMMCMCC_ZU2}

T_{PSMMCMCC_ZU3}

T_{PHMMCMCC_ZU3}

T_{PSMMCMCC_ZU4}

T_{PHMMCMCC_ZU4}

T_{PSMMCMCC_ZU5}

T_{PHMMCMCC_ZU5}

T_{PSMMCMCC_ZU6}

T_{PHMMCMCC_ZU6}

T_{PSMMCMCC_ZU7}

T_{PHMMCMCC_ZU7}

T_{PSMMCMCC_ZU9}

T_{PHMMCMCC_ZU9}

T_{PSMMCMCC_ZU11}

T_{PHMMCMCC_ZU11}

T_{PSMMCMCC_ZU15}

T_{PHMMCMCC_ZU15}

T_{PSMMCMCC_ZU17}

T_{PHMMCMCC_ZU17}

T_{PSMMCMCC_ZU19}

T_{PHMMCMCC_ZU19}

T_{PSMMCMCC_XAZU2}

T_{PHMMCMCC_XAZU2}

T_{PSMMCMCC_XAZU3}

T_{PHMMCMCC_XAZU3}

T_{PSMMCMCC_XAZU4}

T_{PHMMCMCC_XAZU4}

T_{PSMMCMCC_XAZU5}

T_{PHMMCMCC_XAZU5}

Notes:

Global clock input and input

flip-flop (or latch) with MMCM

Setup

Hold

XCZU2

XCZU3

XCZU4

XCZU5

XCZU6

XCZU7

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2

XAZU3

XAZU4

XAZU5

N/A

1.83

–0.19

1.83

–0.19

1.82

–0.16

1.82

–0.16

2.00

–0.11

1.91

–0.14

2.00

–0.11

1.89

–0.20

1.99

–0.10

1.89

–0.16

1.89

–0.16

N/A

1.96

1.83

1.96

–0.24

1.96

ns

–0.19

1.96

–0.24

1.83

–0.24

1.82

–0.25

1.82

–0.25

2.00

–0.18

1.91

–0.18

2.00

–0.18

1.89

–0.25

1.99

–0.16

1.89

–0.23

1.89

–0.23

N/A

Setup

Hold

–0.19

1.94

–0.24

1.94

Setup

Hold

1.82

–0.16

1.82

–0.16

2.00

–0.11

1.89

–0.14

2.00

–0.11

1.89

–0.20

1.99

–0.10

1.89

–0.16

1.89

–0.16

N/A

–0.16

1.94

–0.25

1.94

Setup

Hold

–0.16

2.12

–0.25

2.12

Setup

Hold

–0.11

2.02

–0.18

2.02

Setup

Hold

–0.14

2.12

–0.18

2.12

Setup

Hold

–0.11

2.02

–0.18

2.02

Setup

Hold

–0.20

2.12

–0.25

2.12

Setup

Hold

–0.10

2.03

–0.16

2.03

Setup

Hold

–0.16

2.03

–0.23

2.03

Setup

Hold

–0.16

1.96

–0.23

1.96

Setup

Hold

N/A

–0.19

1.96

N/A

–0.24

1.96

Setup

Hold

N/A

–0.19

1.94

N/A

–0.24

1.94

Setup

Hold

N/A

–0.16

1.94

N/A

–0.25

1.94

Setup

Hold

N/A

–0.16

N/A

–0.25

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the

global clock input signal using the fastest process, fastest temperature, and fastest voltage.

2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible I/O and CLB flip-flops are clocked by the global clock net.

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

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69

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Table 92: Sampling Window

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

1

T_{SAMP_BUFG}

510

100

60

610

100

60

610

125

85

610

125

85

610

150

110

ps

T_{SAMP_NATIVE_DPA}

T_{SAMP_NATIVE_BISC}

Notes:

1. This parameter indicates the total sampling error of the Zynq UltraScale+ MPSoC DDR input registers, measured across voltage,

temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation.

These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These

measurements do not include package or clock tree skew.

Package Parameter Guidelines

The parameters in this secꢀon provide the necessary values for calculaꢀng ꢀming budgets for clock transmiꢃer

and receiver data-valid windows.

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70

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 93: Package Skew

Symbol

Description

Device

Package

Value

Units

PKGSKEW

Package Skew^{1, 2}

XCZU2

SBVA484

105

108

93

ps

SFVA625

SFVC784

SBVA484

SFVA625

SFVC784

FBVB900

SFVC784

FBVB900

FFVC900

FFVB1156

FBVB900

FFVC1156

FFVF1517

FFVC900

FFVB1156

FFVC1156

FFVB1517

FFVF1517

FFVC1760

FFVC900

FFVB1156

FFVB1517

FFVC1760

FFVD1760

FFVE1924

FFVB1517

FFVC1760

FFVD1760

FFVE1924

SBVA484

SFVA625

SFVC784

SBVA484

SFVA625

SFVC784

XCZU3

105

108

93

XCZU4

XCZU5

XCZU6

XCZU7

133

159

133

159

119

134

141

175

305

119

134

170

176

186

215

118

132

221

226

178

174

221

226

178

174

105

108

93

XCZU9

XCZU11

XCZU15

XCZU17

XCZU19

XAZU2EG

XAZU3EG

105

108

93

XAZU4EV

XAZU5EV

133

Notes:

1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die

pad to ball.

2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.

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71

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

GTH Transceiver Specifications

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Zynq UltraScale+ MPSoCs that

include the GTH transceivers.

GTH Transceiver DC Input and Output Levels

The following table summarizes the DC speciꢁcaꢀons of the GTH transceivers in Zynq UltraScale+ MPSoCs.

Consult the UltraScale Architecture GTH Transceivers User Guide (UG576) for further details.

Table 94: GTH Transceiver DC Specifications

Symbol

DC Parameter

Conditions

Min

Typ

Max

Units

DV_PPIN

Differential peak-to-peak input voltage

(external AC coupled)

>10.3125 Gb/s

150

–

1250

mV

6.6 Gb/s to 10.3125 Gb/s

≤ 6.6 Gb/s

150

2000

V_IN

Single-ended input voltage. Voltage

measured at the pin referenced to GND

DC coupled V_MGTAVTT= 1.2V

–400

V_MGTAVTT

V_CMIN

Common mode input voltage

DC coupled V_MGTAVTT= 1.2V

–

2/3 V_MGTAVTT

–

mV

D_VPPOUT

Differential peak-to-peak output

voltage¹

Transmitter output swing is set

to 11111

800

V_CMOUTDC

Common mode output voltage: DC

coupled (equation based)

When remote RX is terminated

to GND

V_MGTAVTT/2 – D_VPPOUT/4

V_MGTAVTT– D_VPPOUT/2

mV

When remote RX termination

is floating

When remote RX is terminated

2

to V_{RX_TERM}

V_CMOUTAC

R_IN

Common mode output voltage: AC coupled (equation based)

Differential input resistance

V_MGTAVTT– D_VPPOUT/2

mV

Ω

–

100

–

R_OUT

Differential output resistance

Ω

T_OSKEW

C_EXT

Transmitter output pair (TXP and TXN) intra-pair skew (all packages)

Recommended external AC coupling capacitor³

10

–

ps

nF

100

Notes:

1. The output swing and pre-emphasis levels are programmable using the attributes discussed in the UltraScale Architecture GTH

Transceivers User Guide (UG576), and can result in values lower than reported in this table.

2. V_{RX_TERM}is the remote RX termination voltage.

3. Other values can be used as appropriate to conform to specific protocols and standards.

Figure 3: Single-Ended Peak-to-Peak Voltage

+V

0

P

Single-Ended

Peak-to-Peak

Voltage

N

X16653-072117

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72

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Figure 4: Differential Peak-to-Peak Voltage

+V

0

Differential

Peak-to-Peak

Voltage

P–N

–V

Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2

X16639-072117

Table 95 and Table 96 summarize the DC speciꢁcaꢀons of the GTH transceivers input and output clocks in Zynq

UltraScale+ MPSoCs. Consult the UltraScale Architecture GTH Transceivers User Guide (UG576) for further details.

Table 95: GTH Transceiver Clock Input Level Specification

Symbol

DC Parameter

Min

Typ

Max

Units

V_IDIFF

R_IN

Differential peak-to-peak input voltage

250

–

2000

mV

Ω

Differential input resistance

100

10

–

C_EXT

Required external AC coupling capacitor

–

nF

Table 96: GTH Transceiver Clock Output Level Specification

Symbol

Description

Conditions

Min

Typ

Max

Units

V_OL

Output Low voltage for P and N

Output High voltage for P and N

R_T= 100Ω across P and N signals

100

500

300

–

330

700

430

mV

V_OH

V_DDOUT

Differential output voltage (P–N), P =

High (N–P), N = High

V_CMOUT

Common mode voltage

R_T= 100Ω across P and N signals

300

–

500

mV

GTH Transceiver Switching Characteristics

Consult the UltraScale Architecture GTH Transceivers User Guide (UG576) for further informaꢀon.

Table 97: GTH Transceiver Performance

Speed Grade and V_CCINTOperating Voltages

Output

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

Divider

-2

-1

-2

-1

F_GTHMAX

F_GTHMIN

GTH maximum line rate

GTH minimum line rate

16.375¹

12.5

0.5

12.5

0.5

10.3125

0.5

Gb/s

0.5

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73

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 97: GTH Transceiver Performance (cont'd)

Speed Grade and V_CCINTOperating Voltages

0.85V 0.72V

Output

Divider

Symbol

Description

0.90V

-3

Units

-2

-1

-2

-1

Min

Max

12.5

Min

4

Max

Min

4

Max

8.5

Min

4

Max

8.5

Min

4

Max

8.5

F_GTHCRANGE

CPLL line rate

range²

1

2

4

2

12.5

6.25

Gb/s

6.25

2

4.25

2

4.25

2

4.25

4

1

3.125

1.5625

1

3.125

1.5625

1

2.125

1.0625

1

2.125

1.0625

1

2.125

1.0625

8

0.5

16

N/A

Max

Min

9.8

Max

Min

9.8

Max

Min

9.8

Min

9.8

Max

12.5

Min

9.8

Max

F_GTHQRANGE1

QPLL0 line rate

range³

1

2

16.375

8.1875

4.0938

16.375

8.1875

4.0938

12.5

8.15

10.3125

8.15

Gb/s

4.9

8.1875

4.0938

4.9

4

2.45

4.075

2.45

4.075

8

1.225 2.0469 1.225 2.0469 1.225 2.0375 1.225 2.0469 1.225

2.0375

16

0.6125 1.0234 0.6125 1.0234 0.6125 1.0188 0.6125 1.0234 0.6125 1.0188

Min

8.0

4.0

2.0

1.0

0.5

Min

2

Max

13.0

Min

8.0

4.0

2.0

1.0

0.5

Min

2

Max

13.0

Min

8.0

4.0

2.0

1.0

0.5

Min

2

Max

12.5

Min

8.0

4.0

2.0

1.0

0.5

Min

2

Max

12.5

Min

8.0

4.0

2.0

1.0

0.5

Min

2

Max

10.3125

6.5

F_GTHQRANGE2

QPLL1 line rate

range⁴

1

2

Gb/s

6.5

4

3.25

8

1.625

0.8125

Max

6.25

1.625

0.8125

Max

6.25

1.625

0.8125

Max

4.25

1.625

0.8125

Max

4.25

1.625

0.8125

Max

16

F_CPLLRANGE

F_QPLL0RANGE

F_QPLL1RANGE

Notes:

CPLL frequency range

QPLL0 frequency range

QPLL1 frequency range

4.25

GHz

9.8

8

16.375

13

9.8

8

16.375

13

9.8

8

16.375

13

9.8

8

16.375

13

9.8

8

16.375

13

1. GTH transceiver line rates in the SFVC784 package support data rates up to 12.5 Gb/s.

2. The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider.

3. The values listed are the rounded results of the calculated equation (QPLL0_Frequency)/Output_Divider.

4. The values listed are the rounded results of the calculated equation (QPLL1_Frequency)/Output_Divider.

Table 98: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics

Symbol

Description

All Speed Grades

Units

F_GTHDRPCLK

GTHDRPCLK maximum frequency

250

MHz

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74

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 99: GTH Transceiver Reference Clock Switching Characteristics

All Speed Grades

Typ

Symbol

Description

Conditions

Units

Min

Max

F_GCLK

Reference clock frequency range

Reference clock rise time

Reference clock fall time

60

–

820

–

MHz

ps

T_RCLK

T_FCLK

T_DCREF

20% – 80%

200

50

80% – 20%

–

ps

Reference clock duty cycle

Transceiver PLL only

40

60

%

Table 100: GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask

Offset

Frequency

Symbol

Description

Min

Typ

Max

Units

1, 2

QPLL_REFCLKMASK

QPLL0/QPLL1 reference clock select phase noise

mask at REFCLK frequency = 312.5 MHz

10 kHz

100 kHz

1 MHz

–

–105

–124

–130

–105

–124

–130

–140

dBc/Hz

1, 2

CPLL_REFCLKMASK

CPLL reference clock select phase noise mask at

REFCLK frequency = 312.5 MHz

10 kHz

100 kHz

1 MHz

dBc/Hz

50 MHz

Notes:

1. For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 × Log(N/312.5) where N is the new

reference clock frequency in MHz.

2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol,

e.g., PCIe.

Table 101: GTH Transceiver PLL/Lock Time Adaptation

All Speed Grades

Symbol

Description

Conditions

Units

Min

Typ

Max

T_LOCK

T_DLOCK

Initial PLL lock

–

1

ms

UI

Clock recovery phase acquisition and

adaptation time for decision feedback

equalizer (DFE)

After the PLL is locked to the

reference clock, this is the time

it takes to lock the clock data

recovery (CDR) to the data

present at the input.

50,000

37 x 10⁶

Clock recovery phase acquisition and

adaptation time for low-power mode (LPM)

when the DFE is disabled

–

50,000

2.3 x 10⁶

UI

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75

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 102: GTH Transceiver User Clock Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Data Width Conditions

(Bit)

0.90V

-3²

0.85V

0.72V

Symbol

Description¹

Units

Internal Interconnect

-2^{2, 3}

-1^{4, 5}

-2³

-1⁵

Logic

F_TXOUTPMA

TXOUTCLK maximum frequency sourced from

OUTCLKPMA

511.719

390.625

511.719

322.266

MHz

F_RXOUTPMA

F_TXOUTPROGDIV

F_RXOUTPROGDIV

F_TXIN

RXOUTCLK maximum frequency sourced from

OUTCLKPMA

511.719

390.625

511.719

322.266

511.719

TXOUTCLK maximum frequency sourced from

TXPROGDIVCLK

RXOUTCLK maximum frequency sourced from

RXPROGDIVCLK

TXUSRCLK⁶

maximum

frequency

16

32

20

40

16

32

20

40

16

32

20

40

16

32

20

40

16, 32

32, 64

20, 40

40, 80

16, 32

32, 64

20, 40

40, 80

16

511.719

409.375

511.719

409.375

511.719

255.859

511.719

255.859

409.375

204.688

409.375

204.688

511.719

255.859

511.719

255.859

409.375

204.688

409.375

204.688

511.719

409.375

511.719

409.375

511.719

255.859

511.719

255.859

409.375

204.688

409.375

204.688

511.719

255.859

511.719

255.859

409.375

204.688

409.375

204.688

390.625

312.500

390.625

312.500

390.625

195.313

390.625

195.313

312.500

156.250

312.500

156.250

390.625

195.313

390.625

195.313

312.500

156.250

312.500

156.250

390.625

312.500

390.625

312.500

390.625

195.313

390.625

195.313

312.500

156.250

312.500

156.250

390.625

195.313

390.625

195.313

312.500

156.250

312.500

156.250

322.266

257.813

322.266

257.813

322.266

161.133

322.266

161.133

257.813

128.906

257.813

128.906

322.266

161.133

322.266

161.133

257.813

128.906

257.813

128.906

MHz

F_RXIN

RXUSRCLK⁶

maximum

frequency

F_TXIN2

TXUSRCLK2⁶

maximum

frequency

32

64

20

40

80

F_RXIN2

RXUSRCLK2⁶

maximum

frequency

16

32

64

20

40

80

Notes:

1. Clocking must be implemented as described in UltraScale Architecture GTH Transceivers User Guide (UG576).

2. For speed grades -3E, -2E, and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.

3. For speed grade -2LE, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s when V_CCINT= 0.85V or

6.25 Gb/s when V_CCINT= 0.72V.

4. For speed grades -1E and -1I, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s.

5. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when V_CCINT= 0.85V or

5.15625 Gb/s when V_CCINT= 0.72V.

6. When the gearbox is used, these maximums refer to the XCLK. For more information, see the UltraScale Architecture GTH Transceivers User

Guide (UG576).

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76

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 103: GTH Transceiver Transmitter Switching Characteristics

Symbol

Description

Condition

Min

Typ

Max

Units

F_GTHTX

T_RTX

Serial data rate range

0.500

–

21

–

F_GTHMAX

–

Gb/s

ps

UI

TX rise time

20%–80%

80%–20%

T_FTX

TX fall time

–

T_LLSKEW

T_J16.375

D_J16.375

T_J15.0

TX lane-to-lane skew¹

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

500.00

0.28

0.17

0.28

0.17

0.28

0.17

0.28

0.17

0.28

0.17

0.28

0.17

0.33

0.17

0.28

0.17

0.28

0.17

0.33

0.17

0.28

0.17

0.33

0.17

0.32

0.17

0.30

0.15

0.30

0.15

0.30

0.15

0.32

0.16

0.20

0.10

0.20

0.10

16.375 Gb/s

15.0 Gb/s

14.1 Gb/s

14.025 Gb/s

13.1 Gb/s

12.5 Gb/s

11.3 Gb/s

10.3125 Gb/s

9.953 Gb/s

8.0 Gb/s

D_J15.0

T_J14.1

D_J14.1

T_J14.1

D_J14.1

T_J13.1

D_J13.1

T_{J12.5_QPLL}

D_{J12.5_QPLL}

T_{J12.5_CPLL}

D_{J12.5_CPLL}

T_{J11.3_QPLL}

D_{J11.3_QPLL}

T_{J10.3125_QPLL}

D_{J10.3125_QPLL}

T_{J10.3125_CPLL}

D_{J10.3125_CPLL}

T_{J9.953_QPLL}

D_{J9.953_QPLL}

T_{J9.953_CPLL}

D_{J9.953_CPLL}

T_J8.0

D_J8.0

T_J6.6

6.6 Gb/s

D_J6.6

T_J5.0

5.0 Gb/s

D_J5.0

T_J4.25

4.25 Gb/s

4.0 Gb/s

D_J4.25

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

T_J4.0

D_J4.0

T_J3.20

3.20 Gb/s⁵

2.5 Gb/s⁶

D_J3.20

T_J2.5

D_J2.5

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77

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 103: GTH Transceiver Transmitter Switching Characteristics (cont'd)

Symbol

Description

Condition

Min

Typ

Max

Units

T_J1.25

D_J1.25

T_J500

D_J500

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

1.25 Gb/s7

–

0.15

0.06

0.10

0.03

UI

500 Mb/s⁸

Deterministic jitter^{3, 4}

Notes:

1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTH Quad) at

the maximum line rate.

2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.

3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.

4. All jitter values are based on a bit-error ratio of 10^–12

5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.

6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.

7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.

8. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.

.

Table 104: GTH Transceiver Receiver Switching Characteristics

Symbol

Description

Condition

Min

Typ

Max

Units

F_GTHRX

Serial data rate

Receiver spread-spectrum tracking¹

0.500

–5000

–

F_GTHMAX

0

Gb/s

ppm

UI

R_XSST

Modulated at 33 kHz

R_XRL

Run length (CID)

256

R_XPPMTOL

Data/REFCLK PPM offset tolerance

Bit rates ≤ 6.6 Gb/s

–1250

–700

1250

700

ppm

Bit rates > 6.6 Gb/s and

≤ 8.0 Gb/s

Bit rates > 8.0 Gb/s

–200

–

200

ppm

SJ Jitter Tolerance²

J_{T_SJ16.375}

J_{T_SJ15.0}

Sinusoidal jitter (QPLL)³

Sinusoidal jitter (CPLL)³

Sinusoidal jitter (QPLL)³

Sinusoidal jitter (CPLL)³

Sinusoidal jitter (QPLL)³

Sinusoidal jitter (CPLL)³

16.375 Gb/s

15.0 Gb/s

14.1 Gb/s

13.1 Gb/s

12.5 Gb/s

11.3 Gb/s

10.32 Gb/s

9.953 Gb/s

8.0 Gb/s

0.30

0.42

0.44

0.45

0.30

–

UI

J_{T_SJ14.1}

J_{T_SJ13.1}

J_{T_SJ12.5}

J_{T_SJ11.3}

J_{T_SJ10.32_QPLL}

J_{T_SJ10.32_CPLL}

J_{T_SJ9.953_QPLL}

J_{T_SJ9.953_CPLL}

J_{T_SJ8.0}

J_{T_SJ6.6_CPLL}

J_{T_SJ5.0}

6.6 Gb/s

5.0 Gb/s

J_{T_SJ4.25}

4.25 Gb/s

3.2 Gb/s⁴

2.5 Gb/s⁵

1.25 Gb/s⁶

J_{T_SJ3.2}

J_{T_SJ2.5}

J_{T_SJ1.25}

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 104: GTH Transceiver Receiver Switching Characteristics (cont'd)

Symbol

Description

Condition

Min

Typ

Max

Units

J_{T_SJ500}

SJ Jitter Tolerance with Stressed Eye²

Sinusoidal jitter (CPLL)³

500 Mb/s⁷

0.30

–

UI

J_{T_TJSE3.2}

J_{T_TJSE6.6}

J_{T_SJSE3.2}

J_{T_SJSE6.6}

Notes:

Total jitter with stressed eye⁸

3.2 Gb/s

6.6 Gb/s

3.2 Gb/s

6.6 Gb/s

0.70

0.10

–

UI

Sinusoidal jitter with stressed eye⁸

1. Using RXOUT_DIV = 1, 2, and 4.

2. All jitter values are based on a bit error ratio of 10^–12

.

3. The frequency of the injected sinusoidal jitter is 80 MHz.

4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.

5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.

6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.

7. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.

8. Composite jitter with RX equalizer enabled. DFE disabled.

GTH Transceiver Electrical Compliance

The UltraScale Architecture GTH Transceivers User Guide (UG576)) contains recommended use modes that ensure

compliance for the protocols listed in the following table. The transceiver wizard provides the recommended

seꢄngs for those use cases and for protocol speciꢁc characterisꢀcs.

Table 105: GTH Transceiver Protocol List

Electrical

Compliance

Protocol

Specification

Serial Rate (Gb/s)

CAUI-10

nPPI

10GBASE-KR¹

40GBASE-KR

SFP+

IEEE 802.3-2012

10.3125

Compliant

10.3125

9.95328–11.10

10.3125

6.25

SFF-8431 (SR and LR)

INF-8077i, revision 4.5

CEI-6G-SR

XFP

RXAUI

XAUI

IEEE 802.3-2012

IEEE 802.3bx (PAR)

IEEE 802.3-2012

ITU G.8251

3.125

1000BASE-X

5.0G Ethernet

2.5G Ethernet

1.25

5

2.5

HiGig, HiGig+, HiGig2

OTU2

3.74, 6.6

10.709225

11.180997

0.1555–9.956

2.488

OTU4 (OTL4.10)

OC-3/12/48/192

TFI-5

OIF-CEI-11G-SR

GR-253-CORE

OIF-TFI5-0.1.0

Interlaken

OIF-CEI-6G, OIF-CEI-11G-SR

4.25–12.5

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 105: GTH Transceiver Protocol List (cont'd)

Electrical

Compliance

Protocol

Specification

Serial Rate (Gb/s)

PCIe Gen1, 2, 3

SDI²

UHD-SDI²

PCI Express base 3.0

2.5, 5.0, and 8.0

0.27–2.97

Compliant

SMPTE 424M-2006

SMPTE ST-2081 6G, SMPTE ST-2082 12G

HMC-15G-SR

6 and 12

Hybrid memory cube (HMC)

MoSys Bandwidth Engine

CPRI

10, 12.5, and 15.0

10.3125, 15.5

0.6144–12.165

All

CEI-11-SR and CEI-11-SR (overclocked)

CPRI_v_6_1_2014-07-01

HDMI 2.0

HDMI²

Passive optical network (PON)

10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G- 0.155–10.3125

PON

JESD204a/b

Serial RapidIO

DisplayPort²

Fibre channel

SATA Gen1, 2, 3

SAS Gen1, 2, 3

SFI-5

OIF-CEI-6G, OIF-CEI-11G

RapidIO specification 3.1

DP 1.2B CTS

3.125–12.5

Compliant

1.25–10.3125

1.62–5.4

FC-PI-4

1.0625–14.025

1.5, 3.0, and 6.0

3.0, 6.0, and 12.0

0.625–12.5

Serial ATA revision 3.0 specification

T10/BSR INCITS 519

OIF-SFI5-01.0

Aurora

CEI-6G, CEI-11G-LR

up to 11.180997

Notes:

1. The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification.

2. This protocol requires external circuitry to achieve compliance.

GTY Transceiver Specifications

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Zynq UltraScale+ MPSoCs that

include the GTY transceivers.

GTY Transceiver DC Input and Output Levels

Table 106 summarizes the DC speciꢁcaꢀons of the GTY transceivers in Zynq UltraScale+ MPSoCs. Consult the

UltraScale Architecture GTY Transceivers User Guide (UG578) for further details.

Table 106: GTY Transceiver DC Specifications

Symbol

DC Parameter

Conditions

Min

Typ

Max

Units

DV_PPIN

Differential peak-to-peak input voltage

(external AC coupled)

>10.3125 Gb/s

150

–

1250

mV

6.6 Gb/s to 10.3125 Gb/s

≤ 6.6 Gb/s

150

2000

V_IN

Single-ended input voltage. Voltage

measured at the pin referenced to GND.

DC coupled V_MGTAVTT= 1.2V

–400

V_MGTAVTT

V_CMIN

Common mode input voltage

DC coupled V_MGTAVTT= 1.2V

–

2/3 V_MGTAVTT

–

mV

D_VPPOUT

Differential peak-to-peak output

voltage¹

Transmitter output swing is

set to 11111

800

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 106: GTY Transceiver DC Specifications (cont'd)

Symbol

DC Parameter

Conditions

Min

Typ

Max

Units

V_CMOUTDC

Common mode output voltage: DC

coupled (equation based)

When remote RX is terminated

to GND

V_MGTAVTT/2 – D_VPPOUT/4

mV

When remote RX termination

is floating

V_MGTAVTT– D_VPPOUT/2

mV

When remote RX is terminated

2

to V_{RX_TERM}

V_CMOUTAC

Common mode output voltage: AC

coupled

Equation based

V_MGTAVTT– D_VPPOUT/2

mV

R_IN

Differential input resistance

Differential output resistance

–

100

–

Ω

R_OUT

T_OSKEW

C_EXT

Transmitter output pair (TXP and TXN) intra-pair skew

Recommended external AC coupling capacitor³

10

–

ps

nF

100

Notes:

1. The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes discussed in the UltraScale Architecture

GTY Transceivers User Guide (UG578) and can result in values lower than reported in this table.

2. V_{RX_TERM}is the remote RX termination voltage.

3. Other values can be used as appropriate to conform to specific protocols and standards.

Figure 5: Single-Ended Peak-to-Peak Voltage

+V

0

P

Single-Ended

Peak-to-Peak

Voltage

N

X16653-072117

Figure 6: Differential Peak-to-Peak Voltage

+V

0

Differential

Peak-to-Peak

Voltage

P–N

–V

Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2

X16639-072117

The following tables summarize the DC speciꢁcaꢀons of the clock input/output levels of the GTY transceivers in

Zynq UltraScale+ MPSoCs. Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further

details.

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81

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 107: GTY Transceiver Clock DC Input Level Specification

Symbol

DC Parameter

Min

Typ

Max

Units

V_IDIFF

R_IN

Differential peak-to-peak input voltage

250

–

2000

mV

Ω

Differential input resistance

100

10

–

C_EXT

Required external AC coupling capacitor

–

nF

Table 108: GTY Transceiver Clock Output Level Specification

Symbol

Description

Conditions

Min

Typ

Max

Units

V_OL

Output Low voltage for P and N

Output High voltage for P and N

R_T= 100Ω across P and N signals

100

500

300

–

330

700

430

mV

V_OH

V_DDOUT

Differential output voltage (P–N), P =

High (N–P), N = High

V_CMOUT

Common mode voltage

R_T= 100Ω across P and N signals

300

–

500

mV

GTY Transceiver Switching Characteristics

Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further informaꢀon.

Table 109: GTY Transceiver Performance

Speed Grade and V_CCINTOperating Voltages

Output

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

Divider

-2

-1

-2

-1

F_GTYMAX

GTY maximum line rate

GTY minimum line rate

32.75

0.5

28.21

0.5

25.7813

0.5

28.21

0.5

12.5

0.5

Gb/s

F_GTYMIN

Min

Max

12.5

Min

4.0

2.0

1.0

0.5

Max

Min

Max

8.5

Min

4.0

2.0

1.0

0.5

Max

Min

4.0

2.0

1.0

0.5

Max

8.5

F_GTYCRANGE

CPLL line rate

range¹

1

2

4.0

2.0

1.0

0.5

12.5

6.25

4.0

2.0

1.0

0.5

12.5

6.25

Gb/s

6.25

4.25

4

3.125

1.5625

3.125

1.5625

2.125

1.0625

3.125

1.5625

2.125

8

1.0625

16

32

N/A

Min

19.6

9.8

Max

Min

19.6

9.8

Max

Min

19.6

9.8

Max

Min

19.6

9.8

Max

Min

Max

F_GTYQRANGE1

QPLL0 line rate

range²

1

32.75

28.21

25.7813

12.5

28.21

N/A

Gb/s

16.375

8.1875

4.0938

2.0469

16.375

8.1875

4.0938

2.0469

16.375

8.1875

4.0938

2.0469

9.8

4.9

12.5

2

4.9

8.1875

4.0938

2.0469

4.9

8.1875

4.0938

2.0469

4

2.45

1.225

2.45

1.225

2.45

1.225

2.45

1.225

2.45

1.225

8

16

0.6125 1.0234 0.6125 1.0234 0.6125 1.0234 0.6125 1.0234 0.6125 1.0234

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 109: GTY Transceiver Performance (cont'd)

Speed Grade and V_CCINTOperating Voltages

0.85V 0.72V

Output

Divider

Symbol

Description

0.90V

-3

Units

-2

-1

-2

-1

Min

Max

26.0

Min

16.0

8.0

Max

Min

16.0

8.0

Max

Min

16.0

8.0

Max

26.0

13.0

6.5

Min

Max

F_GTYQRANGE2

QPLL1 line rate

range³

1

16.0

8.0

4.0

2.0

1.0

0.5

Min

2.0

9.8

8.0

26.0

13.0

6.5

25.7813

12.5

N/A

Gb/s

13.0

8.0

4.0

2.0

1.0

0.5

Min

2.0

9.8

8.0

12.5

6.5

2

6.5

4.0

6.5

4.0

4

3.25

2.0

3.25

1.625

2.0

3.25

2.0

3.25

1.625

3.25

8

1.625

0.8125

Max

6.25

1.0

1.625

0.8125

Max

4.25

1.0

1.625

0.8125

Max

16

0.5

0.8125

Max

0.5

0.8125

Max

Min

2.0

Min

2.0

Min

2.0

F_CPLLRANGE

F_QPLL0RANGE

F_QPLL1RANGE

Notes:

CPLL frequency range

QPLL0 frequency range

QPLL1 frequency range

6.25

4.25

GHz

16.375

13.0

9.8

16.375

13.0

9.8

16.375

13.0

9.8

16.375

13.0

16.375

13.0

8.0

1. The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider.

2. The values listed are the rounded results of the calculated equation (2 × QPLL0_Frequency)/Output_Divider.

3. The values listed are the rounded results of the calculated equation (2 × QPLL1_Frequency)/Output_Divider.

Table 110: GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics

Symbol

Description

All Speed Grades

Units

F_GTYDRPCLK

GTYDRPCLK maximum frequency

250

MHz

Table 111: GTY Transceiver Reference Clock Switching Characteristics

All Speed Grades

Typ

Symbol

Description

Conditions

Units

Min

Max

F_GCLK

Reference clock frequency range

Reference clock rise time

Reference clock fall time

60

–

820

–

MHz

ps

T_RCLK

T_FCLK

T_DCREF

20% – 80%

200

50

80% – 20%

–

ps

Reference clock duty cycle

Transceiver PLL only

40

60

%

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 112: GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask

Offset

Frequency

Symbol

Description^{1, 2}

Min

Typ

Max

Units

QPLL_REFCLKMASK

QPLL0/QPLL1 reference clock select phase noise

mask at REFCLK frequency = 156.25 MHz

10 kHz

100 kHz

1 MHz

–

–112

–128

–145

–103

–123

–143

–98

dBc/Hz

QPLL0/QPLL1 reference clock select phase noise

mask at REFCLK frequency = 312.5 MHz

10 kHz

100 kHz

1 MHz

dBc/Hz

QPLL0/QPLL1 reference clock select phase noise

mask at REFCLK frequency = 625 MHz

10 kHz

100 kHz

1 MHz

–117

–140

–112

–128

–145

–103

–123

–143

–145

–98

CPLL_REFCLKMASK

CPLL reference clock select phase noise mask at

REFCLK frequency = 156.25 MHz

10 kHz

100 kHz

1 MHz

50 MHz

10 kHz

100 kHz

1 MHz

CPLL reference clock select phase noise mask at

REFCLK frequency = 312.5 MHz

dBc/Hz

50 MHz

10 kHz

100 kHz

1 MHz

CPLL reference clock select phase noise mask at

REFCLK frequency = 625 MHz

–117

–140

–144

50 MHz

Notes:

1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.

2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol,

e.g., PCIe.

Table 113: GTY Transceiver PLL/Lock Time Adaptation

All Speed Grades

Symbol

Description

Conditions

Units

Min

Typ

Max

T_LOCK

T_DLOCK

Initial PLL lock.

–

1

ms

UI

Clock recovery phase acquisition and

adaptation time for decision feedback

equalizer (DFE)

After the PLL is locked to the

reference clock, this is the

time it takes to lock the clock

data recovery (CDR) to the

data present at the input.

50,000

37 x 10⁶

Clock recovery phase acquisition and

adaptation time for low-power mode (LPM)

when the DFE is disabled

–

50,000

2.3 x 10⁶

UI

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 114: GTY Transceiver User Clock Switching Characteristics

Speed Grade and V_CCINTOperating Voltages

Data Width Conditions

(Bit)

0.90V

-3²

0.85V

0.72V

Symbol

Description¹

Units

Internal Interconnect

-2^{2, 3}

-1^{4, 5}

-2³

-1⁵

Logic

F_TXOUTPMA

TXOUTCLK maximum frequency sourced from

OUTCLKPMA

511.719

402.832

511.719

322.266

MHz

F_RXOUTPMA

F_TXOUTPROGDIV

F_RXOUTPROGDIV

F_TXIN

RXOUTCLK maximum frequency sourced from

OUTCLKPMA

511.719

402.832

511.719

322.266

511.719

TXOUTCLK maximum frequency sourced from

TXPROGDIVCLK

RXOUTCLK maximum frequency sourced from

RXPROGDIVCLK

TXUSRCLK⁶

maximum

frequency

16

32

64

20

40

80

16

32

64

20

40

80

16

32

64

20

40

80

16, 32

32, 64

64, 128

20, 40

40, 80

80, 160

16, 32

32, 64

64, 128

20, 40

40, 80

80, 160

16

511.719

409.375

511.719

409.375

511.719

255.859

511.719

255.859

511.719

255.859

409.375

204.688

409.375

204.688

409.375

204.688

511.719

440.781

409.375

352.625

511.719

440.781

409.375

352.625

511.719

255.859

511.719

255.859

440.781

220.391

409.375

204.688

409.375

204.688

352.625

176.313

390.625

402.832

312.500

322.266

390.625

402.832

312.500

322.266

390.625

195.313

390.625

195.313

402.832

201.416

312.500

156.250

312.500

156.250

322.266

161.133

390.625

402.832

312.500

350.000

352.625

390.625

402.832

312.500

350.000

352.625

390.625

195.313

390.625

195.313

402.832

201.416

312.500

156.250

350.000

175.000

352.625

176.313

322.266

195.313

257.813

156.250

322.266

195.313

257.813

156.250

322.266

161.133

322.266

161.133

195.313

97.656

MHz

F_RXIN

RXUSRCLK⁶

maximum

frequency

F_TXIN2

TXUSRCLK2⁶

maximum

frequency

32

64

128

20

257.813

128.906

257.813

128.906

156.250

78.125

40

80

160

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 114: GTY Transceiver User Clock Switching Characteristics (cont'd)

Speed Grade and V_CCINTOperating Voltages

Data Width Conditions

(Bit)

0.90V

-3²

0.85V

0.72V

Symbol

Description¹

Units

Internal Interconnect

-2^{2, 3}

-1^{4, 5}

-2³

-1⁵

Logic

F_RXIN2

RXUSRCLK2⁶

maximum

frequency

16

32

64

20

40

80

16

32

511.719

255.859

511.719

255.859

511.719

255.859

409.375

204.688

409.375

204.688

409.375

204.688

511.719

255.859

511.719

255.859

440.781

220.391

409.375

204.688

409.375

204.688

352.625

176.313

390.625

195.313

390.625

195.313

402.832

201.416

312.500

156.250

312.500

156.250

322.266

161.133

390.625

195.313

390.625

195.313

402.832

201.416

312.500

156.250

350.000

175.000

352.625

176.313

322.266

161.133

322.266

161.133

195.313

97.656

MHz

32

64

128

20

257.813

128.906

257.813

128.906

156.250

78.125

40

80

160

Notes:

1. Clocking must be implemented as described in the UltraScale Architecture GTY Transceivers User Guide (UG578).

2. For speed grades -3E, -2E, and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.

3. For speed grade -2LE, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s when V_CCINT= 0.85V or

6.25 Gb/s when V_CCINT= 0.72V.

4. For speed grades -1E and -1I, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s.

5. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when V_CCINT= 0.85V or

5.15625 Gb/s when V_CCINT= 0.72V.

6. When the gearbox is used, these maximums refer to the XCLK. For more information, see the Valid Data Width Combinations for TX

Asynchronous Gearbox table in the UltraScale Architecture GTY Transceivers User Guide (UG578).

Table 115: GTY Transceiver Transmitter Switching Characteristics

Symbol

Description

Condition

Min

Typ

Max

Units

F_GTYTX

T_RTX

Serial data rate range

0.500

–

21

–

F_GTYMAX

–

Gb/s

ps

UI

TX rise time

20%–80%

80%–20%

–

T_FTX

TX fall time

–

T_LLSKEW

T_J32.75

D_J32.75

T_J28.21

D_J28.21

T_J16.375

D_J16.375

T_J15.0

TX lane-to-lane skew¹

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

500.00

0.35

0.19

0.28

0.17

0.28

0.17

0.28

0.17

0.28

0.17

32.75 Gb/s

28.21 Gb/s

16.375 Gb/s

15.0 Gb/s

–

D_J15.0

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

–

T_J14.1

14.1 Gb/s

–

D_J14.1

–

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 115: GTY Transceiver Transmitter Switching Characteristics (cont'd)

Symbol

Description

Condition

Min

Typ

Max

Units

T_J14.1

D_J14.1

T_J13.1

D_J13.1

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{2, 4}

Deterministic jitter^{2, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

Total jitter^{3, 4}

14.025 Gb/s

–

0.28

0.17

0.28

0.17

0.28

0.17

0.33

0.17

0.28

0.17

0.28

0.17

0.33

0.17

0.28

0.17

0.33

0.17

0.32

0.17

0.30

0.15

0.30

0.15

0.30

0.15

0.20

0.10

0.20

0.10

0.15

0.06

UI

13.1 Gb/s

12.5 Gb/s

11.3 Gb/s

10.3125 Gb/s

9.953 Gb/s

8.0 Gb/s

T_{J12.5_QPLL}

D_{J12.5_QPLL}

T_{J12.5_CPLL}

D_{J12.5_CPLL}

T_{J11.3_QPLL}

D_{J11.3_QPLL}

T_{J10.3125_QPLL}

D_{J10.3125_QPLL}

T_{J10.3125_CPLL}

D_{J10.3125_CPLL}

T_{J9.953_QPLL}

D_{J9.953_QPLL}

T_{J9.953_CPLL}

D_{J9.953_CPLL}

T_J8.0

D_J8.0

T_J6.6

6.6 Gb/s

D_J6.6

T_J5.0

5.0 Gb/s

D_J5.0

T_J4.25

4.25 Gb/s

3.20 Gb/s⁵

2.5 Gb/s⁶

1.25 Gb/s⁷

D_J4.25

T_J3.20

D_J3.20

T_J2.5

D_J2.5

T_J1.25

D_J1.25

Deterministic jitter^{3, 4}

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 115: GTY Transceiver Transmitter Switching Characteristics (cont'd)

Symbol

Description

Condition

Min

Typ

Max

Units

T_J500

D_J500

Total jitter^{3, 4}

Deterministic jitter^{3, 4}

500 Mb/s⁸

–

0.10

0.03

UI

Notes:

1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTY Quad) at

maximum line rate.

2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.

3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.

4. All jitter values are based on a bit-error ratio of 10^–12

5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.

6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.

7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.

8. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.

.

Table 116: GTY Transceiver Receiver Switching Characteristics

Symbol

Description

Condition

Min

Typ

Max

Units

F_GTYRX

Serial data rate

Receiver spread-spectrum tracking¹

0.500

–5000

–

F_GTYMAX

0

Gb/s

ppm

UI

R_XSST

Modulated at 33 kHz

R_XRL

Run length (CID)

256

R_XPPMTOL

Data/REFCLK PPM offset tolerance

Bit rates ≤ 6.6 Gb/s

–1250

–700

1250

700

ppm

Bit rates > 6.6 Gb/s and

≤ 8.0 Gb/s

Bit rates > 8.0 Gb/s

–200

–

200

ppm

SJ Jitter Tolerance²

J_{T_SJ32.75}

Sinusoidal jitter (QPLL)³

Sinusoidal jitter (CPLL)³

Sinusoidal jitter (QPLL)³

Sinusoidal jitter (CPLL)³

32.75 Gb/s

28.21 Gb/s

16.375 Gb/s

15.0 Gb/s

14.1 Gb/s

13.1 Gb/s

12.5 Gb/s

11.3 Gb/s

10.32 Gb/s

9.953 Gb/s

8.0 Gb/s

0.25

0.30

0.42

0.44

0.45

0.30

–

UI

J_{T_SJ28.21}

J_{T_SJ16.375}

J_{T_SJ15.0}

J_{T_SJ14.1}

J_{T_SJ13.1}

J_{T_SJ12.5}

J_{T_SJ11.3}

J_{T_SJ10.32_QPLL}

J_{T_SJ10.32_CPLL}

J_{T_SJ9.953_QPLL}

J_{T_SJ9.953_CPLL}

J_{T_SJ8.0}

J_{T_SJ6.6}

6.6 Gb/s

J_{T_SJ5.0}

5.0 Gb/s

J_{T_SJ4.25}

4.25 Gb/s

3.2 Gb/s⁴

2.5 Gb/s⁵

1.25 Gb/s⁶

J_{T_SJ3.2}

J_{T_SJ2.5}

J_{T_SJ1.25}

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 116: GTY Transceiver Receiver Switching Characteristics (cont'd)

Symbol

Description

Condition

Min

Typ

Max

Units

J_{T_SJ500}

SJ Jitter Tolerance with Stressed Eye²

Sinusoidal jitter (CPLL)³

500 Mb/s⁷

0.30

–

UI

J_{T_TJSE3.2}

J_{T_TJSE6.6}

J_{T_SJSE3.2}

J_{T_SJSE6.6}

Notes:

Total jitter with stressed eye⁸

3.2 Gb/s

6.6 Gb/s

3.2 Gb/s

6.6 Gb/s

0.70

0.10

–

UI

Sinusoidal jitter with stressed eye⁸

1. Using RXOUT_DIV = 1, 2, and 4.

2. All jitter values are based on a bit error ratio of 10^–12

.

3. The frequency of the injected sinusoidal jitter is 80 MHz.

4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.

5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.

6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.

7. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.

8. Composite jitter with RX equalizer enabled. DFE disabled.

GTY Transceiver Electrical Compliance

The UltraScale Architecture GTY Transceivers User Guide (UG578) contains recommended use modes that ensure

compliance for the protocols listed in the following table. The transceiver wizard provides the recommended

seꢄngs for those use cases and for protocol speciꢁc characterisꢀcs.

Table 117: GTY Transceiver Protocol List

Electrical

Compliance

Protocol

Specification

Serial Rate (Gb/s)

CAUI-4

IEEE 802.3-2012

CEI-25G-LR

25.78125

25–28.05

4.25–25.78125

25.78125

27.952493–32.75

11.18–13.1

10.3125

Compliant

Compliant¹

Compliant

28 Gb/s backplane

Interlaken

OIF-CEI-6G, OIF-CEI-11GSR, OIF-CEI-28G-MR

IEEE 802.3bj-2014, CEI-25G-LR

IEEE 802.3by-2014, CEI-25G-LR

OIF-CEI-28G-VSR

100GBASE-KR4

100GBASE-CR4

50GBASE-KR4

50GBASE-CR4

25GBASE-KR4

25GBASE-CR4

OTU4 (OTL4.4) CFP2

OTU4 (OTL4.4) CFP

CAUI-10

OIF-CEI-11G-MR

IEEE 802.3-2012

nPPI

10GBASE-KR²

IEEE 802.3-2012

10.3125

IEEE 802.3-2012

10.3125

SFP+

SFF-8431 (SR and LR)

9.95328–11.10

10.3125

XFP

INF-8077i, revision 4.5

CEI-6G-SR

RXAUI

6.25

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 117: GTY Transceiver Protocol List (cont'd)

Electrical

Compliance

Protocol

Specification

Serial Rate (Gb/s)

XAUI

IEEE 802.3-2012

IEEE 802.3bx (PAR)

IEEE 802.3-2012

3.125

Compliant

Compliant³

Compliant

1000BASE-X

5.0G Ethernet

2.5G Ethernet

1.25

5

2.5

HiGig, HiGig+, HiGig2

QSGMII

3.74, 6.6

QSGMII v1.2 (Cisco System, ENG-46158)

ITU G.8251

5

OTU2

10.709225

11.180997

0.1555–9.956

2.5, 5.0, and 8.0

0.27–2.97

6 and 12

10, 12.5, and 15.0

10.3125, 15.5

0.6144–12.165

OTU4 (OTL4.10)

OC-3/12/48/192

PCIe Gen1, 2, 3

SDI³

OIF-CEI-11G-SR

GR-253-CORE

PCI Express base 3.0

SMPTE 424M-2006

UHD-SDI³

SMPTE ST-2081 6G, SMPTE ST-2082 12G

HMC-15G-SR

Hybrid memory cube (HMC)

MoSys bandwidth engine

CPRI

CEI-11-SR and CEI-11-SR (overclocked)

CPRI_v_6_1_2014-07-01

Passive optical network (PON)

JESD204a/b

10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G-PON 0.155–10.3125

OIF-CEI-6G, OIF-CEI-11G

RapidIO specification 3.1

DP 1.2B CTS

3.125–12.5

Serial RapidIO

DisplayPort

1.25–10.3125

1.62–5.4

Fibre channel

SATA Gen1, 2, 3

SAS Gen1, 2, 3

SFI-5

FC-PI-4

1.0625–14.025

1.5, 3.0, and 6.0

3.0, 6.0, and 12.0

0.625 - 12.5

All rates

Serial ATA revision 3.0 specification

T10/BSR INCITS 519

OIF-SFI5-01.0

Aurora

CEI-6G, CEI-11G-LR

Notes:

1. 25 dB loss at Nyquist without FEC.

2. The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification.

3. This protocol requires external circuitry to achieve compliance.

Integrated Interface Block for Interlaken

More informaꢀon and documentaꢀon on soluꢀons using the integrated interface block for Interlaken can be

found at UltraScale+ Interlaken. The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how

many blocks are in each Zynq UltraScale+ MPSoC. This secꢀon describes the following Interlaken

conꢁguraꢀons.

• 12 x 12.5 Gb/s protocol and lane logic mode (Table 118).

• 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s protocol and lane logic mode (Table 119).

• 12 x 25.78125 Gb/s lane logic only mode (Table 120).

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Zynq UltraScale+ MPSoCs in the SFVC784 package are only supported using the 12 x 12.5 Gb/s Interlaken

conꢁguraꢀon. See the F_GTYMAXmaximum line rates.

Table 118: Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode

Designs

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

F_{RX_SERDES_CLK}

F_{TX_SERDES_CLK}

F_{DRP_CLK}

Receive serializer/

deserializer clock

195.32

MHz

Transmit serializer/

deserializer clock

195.32

250.00

195.32

250.00

195.32

250.00

195.32

250.00

195.32

250.00

Dynamic

reconfiguration port

clock

Min¹

Max

Min¹

Max

Min¹

Max

Min¹

Max

Min¹

Max

F_{CORE_CLK}

F_{LBUS_CLK}

Interlaken core clock

300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27

MHz

Interlaken local bus

clock

Notes:

1. These are the minimum clock frequencies at the maximum lane performance.

Table 119: Maximum Performance for Interlaken 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s Protocol and

Lane Logic Mode Designs

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3¹

0.85V

0.72V

Units

-2¹

-1

-2

-1

F_{RX_SERDES_CLK}

F_{TX_SERDES_CLK}

F_{DRP_CLK}

Receive serializer/

deserializer clock

440.79

N/A

402.84

N/A

MHz

Transmit serializer/

deserializer clock

440.79

250.00

440.79

250.00

N/A

402.84

250.00

N/A

Dynamic reconfiguration

port clock

Min²

412.50³

300.00⁴

Max

Min²

412.50³

300.00⁴

Max

Min Max

N/A

Min²

Max

Min Max

N/A

F_{CORE_CLK}

F_{LBUS_CLK}

Notes:

Interlaken core clock

479.20

349.52

479.20

349.52

412.50

300.00

429.69

349.52

MHz

Interlaken local bus clock

N/A

1. 6 x 28.21 mode is only supported in the -2 (V_CCINT= 0.85V) and -3 (V_CCINT= 0.90V) speed grades.

2. These are the minimum clock frequencies at the maximum lane performance.

3. The minimum value for CORE_CLK is 451.36 MHz for the 6 x 28.21 Gb/s protocol.

4. The minimum value for LBUS_CLK is 330.00 MHz for the 6 x 28.21 Gb/s protocol.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 120: Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode

Designs

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

F_{RX_SERDES_CLK}

F_{TX_SERDES_CLK}

F_{DRP_CLK}

Receive serializer/

402.84

N/A

MHz

deserializer clock

Transmit serializer/

deserializer clock

402.84

250.00

402.84

250.00

N/A

Dynamic reconfiguration port

clock

F_{CORE_CLK}

F_{LBUS_CLK}

Interlaken core clock

412.50

349.52

412.50

349.52

N/A

MHz

Interlaken local bus clock

Integrated Interface Block for 100G Ethernet MAC and

PCS

More informaꢀon and documentaꢀon on soluꢀons using the integrated 100 Gb/s Ethernet block can be found

at UltraScale+ Integrated 100G Ethernet MAC/PCS. The UltraScale Architecture and Product Data Sheet:

Overview (DS890) lists how many blocks are in each Zynq UltraScale+ MPSoC.

Table 121: Maximum Performance for 100G Ethernet Designs

Speed Grade and V_CCINTOperating Voltages

Symbol

Description

0.90V

-3

0.85V

0.72V

Units

-2¹

-1

-2

-1²

F_{TX_CLK}

Transmit clock

Receive clock

390.625

250.00

390.625

250.00

322.223

250.00

322.223

250.00

322.223

250.00

MHz

F_{RX_CLK}

F_{RX_SERDES_CLK}

F_{DRP_CLK}

Receive serializer/deserializer clock

Dynamic reconfiguration port clock

Notes:

1. The maximum clock frequency of 390.625 MHz only applies to the CAUI-10 interface. The maximum clock frequency for the CAUI-4

interface is 322.223 MHz.

2. The CAUI-4 interface is not supported by -1L speed grade devices where V_CCINT= 0.72V.

Integrated Interface Block for PCI Express Designs

More informaꢀon and documentaꢀon on soluꢀons for PCI Express designs can be found at PCI Express. The

UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each Zynq

UltraScale+ MPSoC.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 122: Maximum Performance for PCI Express Designs

Speed Grade and V_CCINTOperating Voltages

0.85V

0.72V³

Symbol

Description^{1, 2}

0.90V

-3

Units

-2

-1

-2

-1

F_PIPECLK

Pipe clock maximum frequency

Core clock maximum frequency

DRP clock maximum frequency

MCAP clock maximum frequency

250.00

500.00

250.00

125.00

250.00

500.00

250.00

125.00

250.00

500.00

250.00

125.00

250.00

125.00

250.00

125.00

MHz

F_CORECLK

F_DRPCLK

F_MCAPCLK

Notes:

1. PCI Express Gen4 operation is supported for x1, x2, x4, and x8 widths.

2. PCI Express Gen4 operation is supported in -3E, -2E, and -2I speed grades.

3. PCI Express Gen3 x16 operation is not supported when V_CCINT= 0.72V.

Video Codec Performance

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Zynq UltraScale+ MPSoC EV

devices that include the Video Codec unit (VCU).

Table 123: VCU Performance

Speed Grade and V_CCINTOperating Voltages¹

Description

0.90V

-3

0.85V

0.72V

Units

-2

-1

-2

-1

Video Codec decoder block maximum frequency

(H.264/5 10-bit 4:2:2)

667

MHz

Notes:

1. The supply voltage for the VCU (V_{CCINT_VCU}) is specified in Table 2.

PL System Monitor Specifications

Table 124: PL SYSMON Specifications

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

V_CCADC= 1.8V ±3%, V_REFP= 1.25V, V_REFN= 0V, ADCCLK = 5.2 MHz, T_j= –40°C to 100°C, typical values at T_j= 40°C

ADC Accuracy¹

Resolution

10

–

Bits

LSBs

%

Integral nonlinearity²

Differential nonlinearity

Offset error

INL

±1.5

±1

DNL

No missing codes, guaranteed monotonic

Offset calibration enabled

–

±2

Gain error

–

±0.4

0.2

Sample rate

–

MS/s

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 124: PL SYSMON Specifications (cont'd)

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

RMS code noise

External 1.25V reference

–

1

–

LSBs

On-chip reference

1

ADC Accuracy at Extended Temperatures

Resolution

Integral nonlinearity²

T_j= –55°C to 125°C

10

–

Bits

INL

±1.5

±1

LSBs

Differential nonlinearity

DNL

No missing codes, guaranteed monotonic

T_j= –55°C to 125°C

–

Analog Inputs²

ADC input ranges

Unipolar operation

0

–

1

V

Bipolar operation

–0.5

0

+0.5

Unipolar common mode range (FS input)

Bipolar common mode range (FS input)

+0.5

–0.1

+0.6

Maximum external channel input ranges

Adjacent channels set within these ranges should

not corrupt measurements on adjacent channels

V_CCADC

On-Chip Sensor Accuracy

Temperature sensor error^{1, 3}

T_j= –55°C to 125°C (with external REF)

T_j= –55°C to 110°C (with internal REF)

T_j= 110°C to 125°C (with internal REF)

–

±3

±3.5

±5

°C

%

Supply sensor error⁴

Supply voltages 0.72V to 1.2V,

±0.5

T_j= –40°C to 100°C (with external REF)

Supply voltages 0.72V to 1.2V,

T_j= –55°C to 125°C (with external REF)

–

±1.0

±2.0

±1.0

±2.0

±1.5

±2.5

%

All other supply voltages,

T_j= –40°C to 100°C (with external REF)

All other supply voltages,

T_j= –55°C to 125°C (with external REF)

Supply voltages 0.72V to 1.2V,

T_j= –40°C to 100°C (with internal REF)

Supply voltages 0.72V to 1.2V,

T_j= –55°C to 125°C (with internal REF)

All other supply voltages,

T_j= –40°C to 100°C (with internal REF)

All other supply voltages,

T_j= –55°C to 125°C (with internal REF)

Conversion Rate⁵

Conversion time—continuous t_CONV

Number of ADCCLK cycles

DRP clock frequency

26

–

32

21

Cycles

MHz

%

Conversion time—event

DRP clock frequency

ADC clock frequency

DCLK duty cycle

t_CONV

DCLK

8

250

5.2

60

ADCCLK

Derived from DCLK

1

40

SYSMON Reference⁶

External reference

V_REFP

Externally supplied reference voltage

1.20

1.25

1.30

V

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Table 124: PL SYSMON Specifications (cont'd)

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

On-chip reference

Ground V_REFPpin to AGND, T_j= –40°C to 100°C

Ground V_REFPpin to AGND, T_j= –55°C to 125°C

1.2375

1.225

1.25

1.2625

1.275

V

Notes:

1. ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is

enabled.

2. See the Analog Input section in the UltraScale Architecture System Monitor User Guide (UG580).

3. When reading temperature values directly from the PMBus interface, the SYSMON has a +4°C offset due to the transfer function used by

the PMBus application. For example, the external REF temperature sensor error’s range of ±3°C becomes +1°C to +7°C when the

temperature is read through the PMBus interface.

4. Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified

for when this feature is enabled.

5. See the Adjusting the Acquisition Settling Time section in the UltraScale Architecture System Monitor User Guide (UG580).

6. Any variation in the reference voltage from the nominal V_REFP= 1.25V and V_REFN= 0V will result in a deviation from the ideal transfer

function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for

external ratiometric type applications allowing reference to vary by ±4% is permitted.

PL SYSMON I2C/PMBus Interfaces

Table 125: PL SYSMON I2C Fast Mode Interface Switching Characteristics

Symbol

Description¹

Min

Max

Units

T_SMFCKL

SCL Low time

1.3

0.6

–

µs

T_SMFCKH

T_SMFCKO

T_SMFDCK

F_SMFCLK

Notes:

SCL High time

SDAO clock-to-out delay

SDAI setup time

SCL clock frequency

900

–

ns

100

–

ns

400

kHz

1. The test conditions are configured to the LVCMOS 1.8V I/O standard.

Table 126: PL SYSMON I2C Standard Mode Interface Switching Characteristics

Symbol

Description¹

Min

Max

Units

T_SMSCKL

SCL Low time

4.7

4.0

–

µs

T_SMSCKH

T_SMSCKO

T_SMSDCK

F_SMSCLK

Notes:

SCL High time

SDAO clock-to-out delay

SDAI setup time

SCL clock frequency

3450

–

ns

250

–

ns

100

kHz

1. The test conditions are configured to the LVCMOS 1.8V I/O standard.

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95

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Configuration Switching Characteristics

Table 127: Configuration Switching Characteristics

Speed Grade and V_CCINTOperating

Voltages

Symbol

Description

Units

0.90V

-3

0.85V

0.72V

-2

-1

-2

-1

PL Power-up Timing Characteristics

T_PL

PS_PROG_B PL latency

7.5

65

0

7.5

65

0

7.5

65

0

7.5

65

0

7.5

65

0

ms, Max

ms, Min

ms, Max

ms, Min

T_POR

Power-on reset from PL power-on to PL ready to

configure (40 ms ramp rate time)

Power-on reset from PL power-on to PL ready to

configure with POR override (2 ms ramp rate

time)

15

5

15

5

15

5

15

5

15

5

T_{PS_PROG_B}

PL program pulse width

250

200

250

200

250

200

250

150

175

250

150

175

ns, Min

Internal Configuration Access Port

F_ICAPCK

Internal configuration access port (ICAPE3)

MHz, Max

DNA Port Switching

F_DNACK

DNA port frequency (DNA_PORT)

STARTUPE3 Ports

F_CFGMCLK

STARTUPE3 CFGMCLK output frequency

50.00

±15

50.00

±15

50.00

±15

50.00

±15

50.00

±15

MHz, Typ

%, Max

F_CFGMCLKTOL

STARTUPE3 CFGMCLK output frequency

tolerance

T_{DCI_MATCH}

Specifies a stall in the startup cycle until the

digitally controlled impedance (DCI) match

signals are asserted

4

ms, Max

Revision History

Date

Version

Description of Revisions

02/07/2018

1.10

Added the XAZU4EV and XAZU5EV devices to many tables.

In Table 2, revised the V_{CCINT_VCU}specifications, added automotive (Q) temperature to T_J, and updated

Note 5.

Added the -1Q note to Table 6, Table 7, and Table 8

Updated Table 25, Table 26, and Table 27 to production for the following devices/speed/temperature

grades in Vivado Design Suite 2017.4.1 v1.18.

XCZU4CG/XCZU4EG/XCZU4EV: -2LE and -1LI

XCZU5CG/XCZU5EG/XCZU5EV: -2LE and -1LI

XCZU7CG/XCZU7EG/XCZU7EV: -2LE and -1LI

XCZU11EG: -2LE and -1LI

XCZU4EV and XAZU5EV: -1LI

In Vivado Design Suite 2017.4 v1.17, the XAZU4EV and XAZU5EV devices in the -1I speed/temperature

grade were production released.

Revised some of the -3E speed files in Table 75, Table 87, Table 88, Table 89, Table 90, and Table 91.

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96

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Description of Revisions

Date

Version

11/28/2017

1.9

Updated Table 25, Table 26, and Table 27 to production for the following devices/speed/temperature

grades in Vivado Design Suite 2017.4 v1.17.

XCZU4CG/XCZU4EG/XCZU4EV: -2E, -2I, -1E, -1I

XCZU5CG/XCZU5EG/XCZU5EV: -2E, -2I, -1E, -1I

XCZU7CG/XCZU7EG/XCZU7EV: -2E, -2I, -1E, -1I

XCZU17EG: -2LE and -1LI

XCZU19EG: -2LE and -1LI

Revised the F_REFCLKdescriptions in Table 82. Added values to Table 93. Revised the F_GTYQRANGE2-1 speed

grade minimum in Table 109.

10/26/2017

1.8

In Table 1, corrected the minimum voltage for the PL System Monitor section. Added Note 4 to Table 2.

Added Note 1 to Table 5.

Updated Table 25, Table 26, and Table 27 to production for the following devices/speed/temperature

grades in Vivado Design Suite 2017.3.1 v1.16.

XCZU2CG/XCZU2EG: -2LE and -1LI

XCZU3CG/XCZU3EG: -2LE and -1LI

XCZU6CG/XCZU6EG: -2LE and -1LI

XCZU9CG/XCZU9EG: -2LE and -1LI

XCZU15EG: -2LE and -1LI

XAZU2EG/XAZU3EG: -1LI

Also updated speed file data for this release in Table 87, Table 88, Table 89, Table 90, and Table 91.

Added specifications for Quad-SPI device clock frequency operating at 40 MHz with loopback disabled to

Table 41 and Table 42.

10/05/2017

10/03/2017

1.7

1.6

Corrected the speed file version in Table 25 and Table 27 for production release of XAZU2EG and

XAZU3EG with -1I and -1Q speed/temperature ranges and the XCZU11EG: -2E, -2I, -1E, -1I to Vivado

Design Suite 2017.3 v1.15.

In Table 1, because the voltages are covered in Table 6, removed the note on V_INfor I/O input voltage for

HD I/O banks. Updated T_SOLby package in Table 1. In Table 2, updated V_{CCINT_VCU}. Added Note 2 to Table

6 and Table 8.

Added the XAZU2EG and XAZU3EG production devices in -1I and -1Q speed/temperature ranges using

Vivado Design Suite 2017.3 v1.14.

In Table 25, Table 26, and Table 27, updated the XCZU11EG: -2E, -2I, -1E, -1I to production in Vivado

Design Suite 2017.3 v1.14. Also updated speed file data for this release in Table 87, Table 88, Table 89,

Table 90, and Table 91.

09/01/2017

1.5

Updated Table 25, Table 26, and Table 27 to production release for the following devices/speed/

temperature grades in Vivado Design Suite 2017.2.1.

XCZU17EG: -2E, -2I, -1E, -1I

XCZU19EG: -2E, -2I, -1E, -1I

In Table 45, revised the minimum T_SDSDRDCK3value. In Table 76, revised the T_{OUTBUF_DELAY_O_PAD}-2 (V_CCINT

= 0.85V) values for DIFF_SSTL135_S, DIFF_SSTL15_DCI_S, DIFF_SSTL15_S, DIFF_SSTL18_I_DCI_S, and

DIFF_SSTL18_I_S.

Revised some of the -3E and -1LI/-2LE (V_CCINT= 0.72V) speed files in Table 75, Table 76, Table 77, Table 87,

Table 88, Table 89, Table 90, and Table 91.

Revised the Integrated Interface Block for Interlaken section.

06/28/2017

1.4

Updated Table 25, Table 26, and Table 27 to production release for the following devices/speed/

temperature grades in Vivado Design Suite 2017.2.

XCZU15EG: -2E, -2I, -1E, -1I

Updated Note 15 in Table 2 for clarity. Updated Table 14 to remove Note 3, Note 6, and the

MIPI_DPHY_DCI_LP row. These changes are because the DCI and POD standards are not supported in

HD I/O banks.

Added Note 5 to Table 30. Updated descriptions in Table 38. Revised the -3E and -1LI/-2LE (V_CCINT= 0.72V)

speed files in Table 75, Table 76, Table 77, Table 87, Table 88, Table 89, Table 90, and Table 91. Updated

the F_MAXsymbol names and values in Table 81. Added Note 1 to Table 83. Added Note 3 to Table 122.

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97

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Description of Revisions

Date

Version

04/20/2017

1.3

Updated Table 25, Table 26, and Table 27 to production release for the following

devices/speed/temperature grades in Vivado Design Suite 2017.1.

XCZU2CG and XCZU2EG: –2E, -2I, -1E, -1I

XCZU3CG and XCZU3EG: –2E, -2I, -1E, -1I

XCZU6CG and XCZU6EG: –2E, -2I, -1E, -1I

XCZU9CG and XCZU9EG: –2E, -2I, -1E, -1I

Added -2E (V_CCINT= 0.85V) speed grade where applicable. Removed -3E speed grade from the XCZU2 and

XCZU3 devices in Table 26 and where applicable.

In Table 1, updated values and Note 2. In Table 2, added or updated many of the notes. Updated Table 4

including the notes and added Note 6. Moved and updated Table 5. Added Table 8. Updated Table 9 and

added Note 4. Updated Table 10 and added Note 1.

Revised V_ICMin Table 23. Updated Table 30 and removed Note 1. Added Table 31 and Table 32. Updated

Table 33 and removed F_FTMCLK. Updated T_RFPSCLKin Table 34. Updated Note 1 in Table 37. Updated Table

39. Removed the PS NAND Memory Controller Interface section. Significant changes to Table 41 and

removed Note 3. Significant changes to Table 42 and updated Note 1. Removed F_{TSU_REF_CLK}from Table

44. Revised Table 45 and added Note 2 and Note 3. Revised Table 46 and added Note 2 and Note 3.

Updated Table 48. Updated Table 51 and removed Note 2. Revised Table 52. Revised many of the tables

in the PS-GTR Transceiver section. Revised Table 70 and Table 71. Removed Note 8 from Table 74.

Updated the values in Table 75, Table 76, Table 77, Table 80 Table 87, Table 88, Table 89, Table 90, and

Table 91 to the Vivado Design Suite 2017.1 speed specifications.

Updated the values in Table 81 and Table 82. Added values to Table 92. Updated Table 93. Revised

D_VPPOUTin Table 94. Update the values in Table 96. Added Note 6 to Table 102. Updated Table 103 and

Table 104. Revised D_VPPOUTin Table 106. Updated the values in Table 108. In Table 109 updated the -1

(0.85V) specifications and removed Note 1. In Table 114 updated the -1 (0.85V) specifications and added

Note 6. In Table 115 and Table 116, added the 28.21 jitter tolerance values and revised the notes. Revised

the Integrated Interface Block for Interlaken and Integrated Interface Block for 100G Ethernet MAC and

PCS sections. Revised the Configuration Switching Characteristics section. Removed the eFUSE

Programming Conditions table and added the specifications to Table 2 and Table 3.

02/10/2017

1.2

Updated some of the maximum voltages in the Processor System (PS) section and other specifications in

the Programmable Logic (PL) and GTH or GTY Transceiver sections of Table 1. Updated Table 2, Table 4,

Table 6, Table 8, and Table 9. Revised the Power Supply Sequencing section including Table 10. Added PS

and VCU ramp times to Table 11. Revised V_ODIFFin Table 24. Updated Table 25. Added Note 1 to Table 26.

Table 27 replaces the previous three PS memory performance tables. Added values to Table 34,Table 37,

and Table 38. Deleted the waveforms in the PS Switching Characteristics section (Figures 1-16 and

Figures 25-26). Revised values in the PS NAND Memory Controller Interface section. Added and updated

data in Table 40. Added Note 3 to Table 41. Added Note 3 to Table 42. Added Note 1 to Table 45. Updated

Table 48 and removed Note 3. Added data to Table 56. Updated Table 60. Added Table 61. Updated Table

63. Revised Table 69. Added data to Table 70. Added Note 2 to Table 71. Updated Table 74 and added

Note 4. Updated V_Land V_Hvalues in Table 78. Added T_{MINPER_CLK}, revised F_REFCLK, and Note 1 to Table 82.

Added MMCM_F_{DPRCLK_MAX}to Table 85 and PLL_F_{DPRCLK_MAX}to Table 86. Added data to Table 94,Table 96,

Table 98, Table 101, and updated the note references in Table 102. Updated Table 103 and added Note 8.

Updated Table 104 and added Note 7. Added more protocols, Note 1 and Note 2 to Table 105. Removed

the GTH Transceiver Protocol Jitter Characteristics section because it is covered in Table 105. Added Note

1 to Table 109. Added data to Table 106, Table 108, Table 110, Table 113. Added Note 2 to Table 112.

Added note references in Table 114. Updated Table 115 and added Note 8. Updated Table 116 and added

Note 7. Added more protocols and Note 3 to Table 117. Removed the GTY Transceiver Protocol Jitter

Characteristics section because it is covered in Table 117. Revised Table 124. Added T_PORand updated

F_ICAPCKin Table 127. Updated the Automotive Applications Disclaimer.

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98

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

Description of Revisions

Date

Version

06/20/2016

1.1

Updated the Summary description. In Table 1, revised V_INfor HP I/O banks and added clarifications to

some descriptions and symbols. Added I_RPU, I_RPD, and Note 4 to Table 2 and updated V_{PS_MGTRAVCC}, the PL

System Monitor section, and Note 3 and Note 5. Updated Note 5 in Table 4. Updated thePS Power-

On/Off Power Supply Sequencing section including all the voltage supply names. Added MIPI_DPHY_DCI

to Table 14, Table 15, and Table 17. Updated Table 23, including removing the V_CCOspecification and

adding Note 1. Added Note 1 to Table 24. Updated Table 25 speed specifications for Vivado Design Suite

2016.1. Added values to Table 28. Updated the -2 value in Table 29. Added F_DPLIVEVIDEOand updated

F_FCIDMACLKin Table 33. Added VCO frequencies to Table 36. Added the T_PSPORminimum to Table 37 and

updated Note 1. Added Table 38. Added value delineation over V_CCINToperating voltages in Table 39.

Revised values for F_TCKand T_TAPTCK/T_TCKTAPin Table 40 and added value delineation over V_CCINToperating

voltages. Updated the PS NAND Memory Controller Interface section. Revised some units and Note 1 in

Table 41 and Table 42. Removed Figure 6: Quad-SPI Interface (Feedback Clock Disabled) Timing.

Updated Note 1 of Table 43. Added F_{TSI_REF_CLK}to Table 44 and updated Note 1. In Table 45, revised

T_DCSDHSCLK1, T_DCSDHSCLK2, and T_DCSDHSCLK3and Note 1. In Table 46, revised Note 1. In Table 47, revised

Note 1. Revised Table 48, including Note 1, and added Note 2 and Note 3. In Table 50, Table 49, Table 51,

and Table 53, revised Note 1. Updated Table 71. Replaced Table 74. Updated Table 75 and Table 76.

Updated Table 78 and Table 79. In Table 80, added the Block RAM and FIFO Clock-to-Out Delays section.

Updated the R_INand C_EXTvalues in Table 57 and Table 95. Updated the -2 (0.72V) and -1 (0.72V) values

and added Note 1 to Table 97. Added Table 100 and Table 112. Added Note 2 toTable 106. Revised data in

Table 109. Revised Table 114. Revised data and added notes in the Integrated Interface Block for

Interlaken section and Table 121. Moved Table 123. Revised INL in Table 124. Added notes to Table 125

and Table 126. In the eFUSE and Programming Conditions table, updated the I_PSFSdescription.

11/24/2015

1.0

Initial Xilinx release.

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Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics

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100


型号：	XCZU7EV-1FFVF1517I
厂家：	XILINX, INC
描述：	Microprocessor Circuit, CMOS, PBGA1517, FLIPCHIP-1517 PC
文件：	总100页 (文件大小：1637K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XCZU7EV-1FFVF1517I [XILINX]

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