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XQ4013EX-4CB191N [XILINX]

QML High-Reliability FPGAs; QML高可靠性的FPGA
XQ4013EX-4CB191N
型号： XQ4013EX-4CB191N
厂家： XILINX, INC    XILINX, INC
描述：

QML High-Reliability FPGAs
QML高可靠性的FPGA
文件： 总36页 (文件大小：300K)
中文：  中文翻译
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0
R
QPRO XQ4000E/EX  
QML High-Reliability FPGAs  
0
2
DS021 (v2.2) June 25, 2000  
Product Specification  
Product Features  
•
Certified to MIL-PRF-38535, appendix A QML  
(Qualified Manufacturers Listing)  
•
•
Configured by Loading Binary File  
Unlimited reprogrammability  
Readback Capability  
-
•
Also available under the following Standard Microcircuit  
Drawings (SMD)  
-
-
Program verification  
Internal node observability  
-
-
-
-
-
XC4005E  
XC4010E  
XC4013E  
XC4025E  
XC4028EX  
5962-97522  
5962-97523  
5962-97524  
5962-97525  
5962-98509  
•
•
Backward Compatible with XC4000 Devices  
Development System runs on most common computer  
platforms  
-
-
-
Interfaces to popular design environments  
Fully automatic mapping, placement and routing  
Interactive design editor for design optimization  
•
•
For more information contact the Defense Supply  
Center Columbus (DSCC)  
http://www.dscc.dla.mis/v/va/smd/smdsrch.html  
•
Available Speed Grades:  
System featured Field-Programmable Gate Arrays  
-
-
-
XQ4000E  
-3 for plastic packages only  
-4 for ceramic packages only  
TM  
-
Select-RAM memory: on-chip ultra-fast RAM with  
·
Synchronous write option  
XQ4028EX -4 for all packages  
·
Dual-port RAM option  
-
-
-
-
-
-
-
Abundant flip-flops  
More Information  
Flexible function generators  
Dedicated high-speed carry logic  
Wide edge decoders on each edge  
Hierarchy of interconnect lines  
Internal 3-state bus capability  
Eight global low-skew clock or signal distribution  
networks  
For more information refer to Xilinx XC4000E and XC4000X  
series Field Programmable Gate Arrays product specifica-  
tion. This data sheet contains pinout tables for XQ4010E  
only. Refer to Xilinx web site for pinout tables for other  
devices. (Pinouts for XQ4000E/EX are identical to  
XC4000E/EX.)  
(http://www.xilinx.com/partinfo/databook.htm)  
•
•
•
•
System Performance beyond 60 MHz  
Flexible Array Architecture  
Low Power Segmented Routing Architecture  
Systems-Oriented Features  
-
IEEE 1149.1-compatible boundary scan logic  
support  
-
-
-
Individually programmable output slew rate  
Programmable input pull-up or pull-down resistors  
12 mA sink current per XQ4000E/EX output  
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
1
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
Table 1: XQ4000E/EX Field Programmable Gate Arrays  
Max.  
Logic  
Gates  
Max.  
RAM Bits  
(No  
Typical  
Max.  
Decode  
Inputs  
Gate Range  
(Logic and  
Number  
of  
Max.  
User  
I/O  
CLB  
Total  
(1)  
Device  
(No RAM)  
Logic)  
RAM)  
Matrix CLBs Flip-Flops per Side  
Packages  
XQ4005E  
5,000  
6,272  
3,000 - 9,000 14 x 14  
7,000 - 20,000 20 x 20  
196  
400  
616  
42  
60  
112  
PG156,  
CB164  
XQ4010E  
XQ4013E  
10,000  
12,800  
1,120  
160  
PG191,  
CB196,  
HQ208  
13,000  
18,432  
10,000 - 30,000 24 x 24  
576  
1,536  
72  
192  
PG223,  
CB228,  
HQ240  
XQ4025E  
25,000  
28,000  
32,768  
32,768  
15,000 - 45,000 32 x 32 1,024  
18,000 - 50,000 32 x 32 1,024  
2,560  
2,560  
96  
96  
256  
256  
PG299,  
CB228  
XQ4028EX  
PG299,  
CB228,  
HQ240,  
BG352  
Notes:  
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.  
XQ4000E Switching Characteristics  
XQ4000E Absolute Maximum Ratings(1)  
Symbol  
Description  
Units  
V
Supply voltage relative to GND  
–0.5 to +7.0  
V
CC  
(2)  
V
Input voltage relative to GND  
–0.5 to V + 0.5  
V
IN  
CC  
(2)  
V
Voltage applied to High-Z output  
Storage temperature (ambient)  
–0.5 to V + 0.5  
V
TS  
CC  
T
T
–65 to +150  
+260  
°C  
°C  
°C  
°C  
STG  
SOL  
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)  
T
Junction temperature  
Ceramic package  
Plastic package  
+150  
J
+125  
Notes:  
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress  
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions  
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.  
2. Maximum DC excursion above V or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During  
CC  
transitions, the device pins may undershoot to –2.0V or overshoot to V + 2.0V, provided this over or undershoot lasts less than  
CC  
10 ns and with the forcing current being limited to 200 mA.  
2
www.xilinx.com  
DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E Recommended Operating Conditions(1,2)  
Symbol  
Description  
Min  
4.5  
4.5  
2.0  
70%  
0
Max  
5.5  
Units  
V
Supply voltage relative to GND, T = –55°C to +125°C Plastic  
V
V
V
CC  
J
Supply voltage relative to GND, T = –55°C to +125°C Ceramic  
5.5  
C
V
V
High-Level Input Voltage  
Low-Level Input Voltage  
Input signal transition time  
TTL inputs  
V
CC  
IH  
IL  
CMOS inputs  
TTL inputs  
100%  
0.8  
V
CC  
V
CMOS inputs  
0
20%  
250  
V
CC  
T
-
ns  
IN  
Notes:  
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.  
2. Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS.  
XQ4000E DC Characteristics Over Recommended Operating Conditions  
Symbol  
Description  
High-level output voltage @ I = –4.0 mA, V min  
Min  
Max  
-
Units  
V
V
TTL outputs  
2.4  
OH  
OH  
CC  
High-level output voltage @ I = –1.0 mA, V min  
CMOS outputs  
TTL outputs  
V – 0.5  
CC  
-
V
OH  
CC  
(1)  
V
Low-level output voltage @ I = 12.0 mA, V min  
-
0.4  
0.4  
50  
V
OL  
OL  
CC  
CMOS outputs  
-
-
V
(2)  
I
Quiescent FPGA supply current  
Input or output leakage current  
mA  
µA  
pF  
mA  
mA  
CCO  
I
–10  
-
+10  
16  
L
C
Input capacitance (sample tested)  
Pad pull-up (when selected) at V = 0V (sample tested)  
IN  
(3)  
(3)  
I
–0.02  
0.2  
–0.25  
2.5  
RIN  
RLL  
IN  
I
Horizontal longline pull-up (when selected) at logic Low  
Notes:  
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.  
2. With no output current loads, no active input or Longline pull-up resistors, all package pins at V or GND, and the FPGA configured  
CC  
with the development system Tie option.  
3. Characterized Only.  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
3
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E Switching Characteristic Guidelines  
Testing of the switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values where one global clock input  
drives one vertical clock line in each accessible column, and  
where all accessible IOB and CLB flip-flops are clocked by  
the global clock net.  
data, reflecting the actual routing structure, use the values  
provided by the static timing analyzer (TRCE in the Xilinx  
Development System) and back-annotated to the simulation  
netlist. These path delays, provided as a guideline, have  
been extracted from the static timing analyzer report. All  
timing parameters assume worst-case operating conditions  
(supply voltage and junction temperature).  
Note: -3 Speed Grade only applies to XQ4010E and  
XQ4013E Plastic Package options only. -4 Speed Grade  
applies to all XQ devices and is only available in  
Ceramic Packages only.  
When fewer vertical clock lines are connected, the clock dis-  
tribution is faster; when multiple clock lines per column are  
driven from the same global clock, the delay is longer. For  
more specific, more precise, and worst-case guaranteed  
XQ4000E Global Buffer Switching Characteristics  
(1)  
(2)  
-3  
-4  
Symbol  
Description  
Device  
Max  
-
Max  
7.0  
Units  
ns  
T
From pad through primary buffer, to any clock K  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
PG  
6.3  
6.8  
-
11.0  
11.5  
12.5  
7.5  
ns  
ns  
ns  
T
From pad through secondary buffer, to any clock K  
-
ns  
SG  
6.8  
7.3  
-
11.5  
12.0  
13.0  
ns  
ns  
ns  
Notes:  
1. For plastic package options only.  
2. For ceramic package options only.  
4
www.xilinx.com  
DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E Horizontal Longline Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
These path delays, provided as a guideline, have been  
extracted from the static timing analyzer report. All timing  
parameters assume worst-case operating conditions (sup-  
ply voltage and junction temperature). Values apply to all  
XQ4000E devices unless otherwise noted.  
The following guidelines reflect worst-case values over the  
recommended operating conditions.  
-3  
-4  
Symbol  
Description  
Device  
Max  
Max  
Units  
TBUF Driving a Horizontal Longline (LL):  
T
T
I going High or Low to LL going High or Low, while T is Low.  
Buffer is constantly active.  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
6.4  
7.2  
-
5.0  
8.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
IO1  
IO2  
(1)  
9.0  
11.0  
6.0  
I going Low to LL going from resistive pull-up High to active Low.  
-
(1)  
TBUF configured as open-drain.  
6.9  
7.7  
-
10.5  
11.0  
12.0  
7.0  
T
T going Low to LL going from resistive pull-up or floating High to  
active Low. TBUF configured as open-drain or active buffer with  
-
ON  
7.3  
7.5  
-
8.5  
(1)  
I = Low.  
8.7  
11.0  
1.8  
T
T
T
T going High to TBUF going inactive, not driving LL.  
-
OFF  
PUS  
PUF  
1.5  
1.5  
-
1.8  
1.8  
1.8  
T going High to LL going from Low to High, pulled up by a single  
-
23.0  
29.0  
32.0  
42.0  
10.0  
13.5  
15.0  
18.0  
(1)  
resistor.  
22.0  
26.0  
-
T going High to LL going from Low to High, pulled up by two  
-
(1)  
resistors.  
11.0  
13.0  
-
Notes:  
1. These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
5
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E Wide Decoder Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
These path delays, provided as a guideline, have been  
extracted from the static timing analyzer report. All timing  
parameters assume worst-case operating conditions (sup-  
ply voltage and junction temperature). Values apply to all  
XQ4000E devices unless otherwise noted.  
The following guidelines reflect worst-case values over the  
recommended operating conditions.  
-3  
-4  
(1,2)  
Symbol  
Description  
Device  
Max  
Max  
9.5  
Units  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
T
Full length, both pull-ups, inputs from IOB I-pins  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
WAF  
9.0  
15.0  
16.0  
18.0  
12.5  
18.0  
19.0  
21.0  
10.5  
16.0  
17.0  
19.0  
12.5  
18.0  
19.0  
21.0  
11.0  
-
T
Full length, both pull-ups, inputs from internal logic  
Half length, one pull-up, inputs from IOB I-pins  
Half length, one pull-up, inputs from internal logic  
-
11.0  
13.0  
-
WAFL  
T
-
WAO  
10.0  
12.0  
-
T
-
WAOL  
12.0  
14.0  
-
Notes:  
1. These delays are specified from the decoder input to the decoder output.  
2. Fewer than the specified number of pull-up resistors can be used, if desired. Using fewer pull-ups reduces power consumption but  
increases delays. Use the static timing analyzer to determine delays if fewer pull-ups are used.  
6
www.xilinx.com  
DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E CLB Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
These path delays, provided as a guideline, have been  
extracted from the static timing analyzer report. All timing  
parameters assume worst-case operating conditions (sup-  
ply voltage and junction temperature). Values apply to all  
XQ4000E devices unless otherwise noted.  
-3  
-4  
Symbol  
Description  
Min  
Max  
Min  
Max  
Units  
Combinatorial Delays  
T
F/G inputs to X/Y outputs  
-
-
-
-
-
2.01  
4.3  
3.3  
3.6  
3.6  
-
-
-
-
-
2.7  
4.7  
4.1  
3.7  
4.5  
ns  
ns  
ns  
ns  
ns  
ILO  
T
F/G inputs via H to X/Y outputs  
C inputs via SR through H to X/Y outputs  
C inputs via H to X/Y outputs  
IHO  
T
T
T
HH0O  
HH1O  
HH2O  
C inputs via D through H to X/Y outputs  
IN  
CLB Fast Carry Logic  
Operand inputs (F1, F2, G1, G4) to C  
T
-
-
-
-
-
2.6  
4.4  
1.7  
3.3  
0.7  
-
-
-
-
-
3.2  
5.5  
1.7  
3.8  
1.0  
ns  
ns  
ns  
ns  
ns  
OPCY  
OUT  
T
Add/Subtract input (F3) to C  
OUT  
ASCY  
T
Initialization inputs (F1, F3) to C  
OUT  
INCY  
T
C
C
through function generators to X/Y outputs  
SUM  
IN  
IN  
T
to C  
, bypass function generators  
OUT  
BYP  
Sequential Delays  
Clock K to outputs Q  
Setup Time before Clock K  
T
-
2.8  
-
3.7  
ns  
CKO  
T
F/G inputs  
3.0  
4.6  
3.6  
4.1  
3.8  
2.4  
3.0  
4.0  
2.1  
3.5  
-
-
-
-
-
-
-
-
-
-
4.0  
6.1  
4.5  
5.0  
4.8  
3.0  
4.0  
4.2  
2.5  
4.2  
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ICK  
T
F/G inputs via H  
IHCK  
T
T
T
C inputs via H0 through H  
C inputs via H1 through H  
C inputs via H2 through H  
HH0CK  
HH1CK  
HH2CK  
T
C inputs via D  
IN  
DICK  
T
C inputs via EC  
ECCK  
T
C inputs via S/R, going Low (inactive)  
RCK  
CCK  
T
C
C
input via F/G  
IN  
IN  
T
input via F/G and H  
CHCK  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
7
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E CLB Switching Characteristic Guidelines (continued)  
-3  
-4  
Symbol  
Description  
Min  
Max  
Min  
Max  
Units  
Hold Time after Clock K  
T
F/G inputs  
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CKI  
T
F/G inputs via H  
CKIH  
T
T
T
C inputs via H0 through H  
C inputs via H1 through H  
C inputs via H2 through H  
C inputs via DIN/H2  
CKHH0  
CKHH1  
CKHH2  
T
CKDI  
T
C inputs via EC  
CKEC  
T
C inputs via SR, going Low (inactive)  
CKR  
Clock  
T
Clock High time  
Clock Low time  
4.0  
4.0  
-
-
4.5  
4.5  
-
-
ns  
ns  
CH  
T
CL  
Set/Reset Direct  
T
Width (High)  
4.0  
-
-
5.5  
-
-
ns  
ns  
RPW  
T
Delay from C inputs via S/R, going High to Q  
4.0  
6.5  
RIO  
(1)  
Master Set/Reset  
T
Width (High or Low)  
11.5  
-
13.0  
-
ns  
ns  
MRW  
T
Delay from Global Set/Reset net to Q  
Global Set/Reset inactive to first active clock K edge  
-
-
-
18.7  
18.7  
125  
-
-
-
23.0  
23.0  
111  
MRQ  
T
ns  
MRK  
TOG  
(2)  
F
Toggle Frequency  
MHz  
Notes:  
1. Timing is based on the XC4005E. For other devices see the static timing analyzer.  
2. Export Control Max. flip-flop toggle rate.  
8
www.xilinx.com  
DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all XQ4000E/EX devices unless otherwise noted.  
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics  
-3  
-4  
Symbol  
Write Operation Description  
Size  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
Min  
14.4  
14.4  
7.2  
7.2  
2.4  
2.4  
0
Max  
Min  
15.0  
15.0  
7.5  
7.5  
2.8  
2.8  
0
Max  
Units  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
T
Address write cycle time (clock K period)  
-
-
WCS  
T
T
-
-
WCTS  
T
Clock K pulse width (active edge)  
Address setup time before clock K  
Address hold time after clock K  
1 ms  
1 ms  
WPS  
1 ms  
1 ms  
WPTS  
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ASS  
T
-
ASTS  
T
-
AHS  
T
0
0
-
AHTS  
T
D
D
setup time before clock K  
hold time after clock K  
3.2  
1.9  
0
3.5  
2.5  
0
-
DSS  
IN  
IN  
T
-
DSTS  
T
-
DHS  
T
0
0
-
DHTS  
T
WE setup time before clock K  
WE hold time after clock K  
Data valid after clock K  
2.0  
2.0  
0
2.2  
2.2  
0
-
WSS  
T
T
T
-
-
WSTS  
T
WHS  
0
0
-
WHTS  
T
8.8  
10.3  
-
10.3  
11.6  
WOS  
-
WOTS  
Notes:  
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.  
2. Applicable Read timing specifications are identical to Level-Sensitive Read timing.  
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics  
-3  
-4  
(1)  
Symbol  
Write Operation Description  
Address write cycle time (clock K period)  
Clock K pulse width (active edge)  
Address setup time before clock K  
Address hold time after clock K  
Size  
16x1  
16x1  
16x1  
16x1  
16x1  
16x1  
16x1  
16x1  
16x1  
Min  
14.4  
7.2  
2.5  
0
Max  
Min  
15.0  
7.5  
2.8  
0
Max  
Units  
ns  
T
T
WCDS  
WPDS  
1 ms  
1 ms  
ns  
T
-
-
ns  
ASDS  
T
-
-
ns  
AHDS  
T
T
D
D
setup time before clock K  
hold time after clock K  
2.5  
0
-
2.2  
0
-
ns  
DSDS  
DHDS  
WSDS  
WHDS  
WODS  
IN  
IN  
-
-
-
ns  
T
T
T
WE setup time before clock K  
WE hold time after clock K  
Data valid after clock K  
1.8  
0
2.2  
0.3  
-
-
-
ns  
-
ns  
-
7.8  
10.0  
ns  
Notes:  
1. Applicable Read timing specifications are identical to Level-Sensitive Read timing.  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
9
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform  
TWPS  
WCLK (K)  
TWSS  
TWHS  
TDHS  
TAHS  
WE  
TDSS  
DATA IN  
TASS  
ADDRESS  
TILO  
TILO  
TWOS  
DATA OUT  
OLD  
NEW  
DS021_01_060100  
XQ4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform  
TWPDS  
WCLK (K)  
TWSS  
TWHS  
WE  
TDHDS  
TDSDS  
DATA IN  
TAHDS  
TASDS  
ADDRESS  
DATA OUT  
TILO  
TILO  
TWODS  
OLD  
NEW  
DS021_02_060100  
10  
www.xilinx.com  
DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all XQ4000E devices unless otherwise noted.  
-3  
-4  
Symbol  
Single Port RAM  
Size  
Min  
Max  
Min  
Max  
Units  
Write Operation  
T
Address write cycle time  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
8.0  
8.0  
4.0  
4.0  
2.0  
2.0  
2.0  
2.0  
2.2  
2.2  
2.0  
2.0  
-
-
-
-
-
-
-
-
-
-
-
-
8.0  
8.0  
4.0  
4.0  
2.0  
2.0  
2.5  
2.0  
4.0  
5.0  
2.0  
2.0  
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
T
WCT  
T
Write Enable pulse width (High)  
Address setup time before WE  
Address hold time after end of WE  
WP  
T
WPT  
T
AS  
T
AST  
T
AH  
T
AHT  
T
D
D
setup time before end of WE  
hold time after end of WE  
DS  
IN  
IN  
T
T
DST  
T
DH  
DHT  
Read Operation  
T
Address read cycle time  
16x2  
32x1  
16x2  
32x1  
3.1  
5.5  
-
-
4.5  
6.5  
-
-
ns  
ns  
ns  
ns  
RC  
T
-
-
RCT  
T
Data valid after address change (no Write Enable)  
1.8  
3.2  
2.7  
4.7  
ILO  
T
-
-
IHO  
Read Operation, Clocking Data into Flip-Flop  
Address setup time before clock K  
T
16x2  
32x1  
3.0  
4.6  
-
-
4.0  
6.1  
-
-
ns  
ns  
ICK  
T
IHCK  
Read During Write  
Data valid after WE goes active (D stable before WE)  
T
16x2  
32x1  
16x2  
32x1  
-
-
-
-
6.0  
7.3  
6.6  
7.6  
-
-
-
-
10.0  
12.0  
9.0  
ns  
ns  
ns  
ns  
WO  
IN  
T
WOT  
T
Data valid after D (D changes during WE)  
IN IN  
DO  
T
11.0  
DOT  
Read During Write, Clocking Data into Flip-Flop  
T
WE setup time before clock K  
16x2  
32x1  
16x2  
32x1  
6.0  
6.8  
5.2  
6.2  
-
-
-
-
8.0  
9.6  
7.0  
8.0  
-
-
-
-
ns  
ns  
ns  
ns  
WCK  
T
WCKT  
T
Data setup time before clock K  
DCK  
T
DOCK  
Notes:  
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.  
DS021 (v2.2) June 25, 2000  
Product Specification  
www.xilinx.com  
1-800-255-7778  
11  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E CLB Level-Sensitive RAM Timing Characteristics  
WRITE  
TWC  
ADDRESS  
TAS  
TWP  
TAH  
WE  
TDS  
TDH  
DATA IN  
REQUIRED  
READ WITHOUT WRITE  
TILO  
X,Y OUTPUTS  
VALID  
VALID  
READ, CLOCKING DATA INTO FLIP-FLOP  
TICK  
TCH  
CLOCK  
TCKO  
XQ,YQ OUTPUTS  
VALID (OLD)  
VALID (NEW)  
READ DURING WRITE  
TWP  
WRITE ENABLE  
TDH  
DATA IN  
(stable during WE)  
TWO  
X,Y OUTPUTS  
VALID  
VALID  
NEW  
DATA IN  
(changing during WE)  
OLD  
TWO  
TDO  
VALID  
(PREVIOUS)  
VALID  
(OLD)  
VALID  
(NEW)  
X,Y OUTPUTS  
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP  
TWP  
WRITE ENABLE  
TWCK  
TDCK  
DATA IN  
CLOCK  
TCKO  
XQ,YQ OUTPUTS  
DS021_03_060100  
12  
www.xilinx.com  
DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Pin-to-pin timing parameters are  
derived from measuring external and internal test patterns  
and are guaranteed over worst-case operating conditions  
(supply voltage and junction temperature). Listed below are  
representative values for typical pin locations and normal  
clock loading. For more specific, more precise, and  
worst-case guaranteed data, reflecting the actual routing  
structure, use the values provided by the static timing ana-  
lyzer (TRCE in the Xilinx Development System) and  
back-annotated to the simulation netlist. These path delays,  
provided as a guideline, have been extracted from the static  
timing analyzer report. Values apply to all XQ4000E devices  
unless otherwise noted.  
Symbol  
Description  
Device  
-3  
-
-4  
Units  
ns  
T
Global clock to output (fast) using OFF  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
14.0  
16.0  
16.5  
17.0  
ICKOF  
10.9  
11.0  
-
ns  
(Max)  
TPG  
OFF  
ns  
ns  
Global Clock-to-Output Delay  
DS021_04_060100  
T
Global clock to output (slew-limited) using OFF  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
18.0  
20.0  
20.5  
21.0  
ns  
ns  
ns  
ns  
ICKO  
14.9  
15.0  
-
(Max)  
TPG  
OFF  
Global Clock-to-Output Delay  
DS021_04_060100  
T
Input setup time, using IFF (no delay)  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
0.2  
0
2.0  
1.0  
0.5  
0
ns  
ns  
ns  
ns  
PSUF  
(Min)  
D
Input  
Setup  
and Hold  
Time  
IFF  
TPG  
-
DS021_05_060100  
T
Input hold time, using IFF (no delay)  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
4.6  
6.0  
7.0  
8.0  
ns  
ns  
ns  
ns  
PHF  
5.5  
6.5  
-
(Min)  
D
Input  
Setup  
IFF  
TPG  
and Hold  
Time  
DS021_05_060100  
T
Input setup time, using IFF (with delay)  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
8.5  
8.5  
8.5  
9.5  
ns  
ns  
ns  
ns  
PSU  
7.0  
7.0  
-
(Min)  
D
Input  
Setup  
and Hold  
Time  
IFF  
TPG  
DS021_05_060100  
T
Input hold time, using IFF (with delay)  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
0
0
-
0
0
0
0
ns  
ns  
ns  
ns  
PH  
(Min)  
D
Input  
Setup  
and Hold  
IFF  
TPG  
Time  
DS021_05_060100  
Notes:  
1. OFF = Output Flip-Flop  
2. IFF = Input Flip-Flop or Latch  
DS021 (v2.2) June 25, 2000  
Product Specification  
www.xilinx.com  
1-800-255-7778  
13  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E IOB Input Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Pin-to-pin timing parameters are  
derived from measuring external and internal test patterns  
and are guaranteed over worst-case operating conditions  
(supply voltage and junction temperature). Listed below are  
representative values for typical pin locations and normal  
clock loading. For more specific, more precise, and  
worst-case guaranteed data, reflecting the actual routing  
structure, use the values provided by the static timing ana-  
lyzer (TRCE in the Xilinx Development System) and  
back-annotated to the simulation netlist. These path delays,  
provided as a guideline, have been extracted from the static  
timing analyzer report. Values apply to all XQ4000E devices  
unless otherwise noted.  
-3  
-4  
Symbol  
Description  
Device  
Min  
Max  
Min  
Max  
Units  
Propagation Delays (TTL Inputs)(1)  
T
Pad to I1, I2  
All devices  
All devices  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
-
-
-
-
-
2.5  
3.6  
-
-
-
-
-
-
-
3.0  
4.8  
ns  
ns  
ns  
ns  
ns  
ns  
PID  
T
Pad to I1, I2 via transparent input latch, no delay  
PLI  
T
Pad to I1, I2 via transparent FCL and input latch,  
with delay  
10.8  
11.0  
11.4  
13.8  
PDLI  
10.8  
11.2  
-
Propagation Delays (CMOS Inputs)(1)  
T
Pad to I1, I2  
All devices  
All devices  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
-
-
-
-
-
-
4.1  
8.8  
-
-
-
-
-
-
-
5.5  
6.8  
ns  
ns  
ns  
ns  
ns  
ns  
PIDC  
T
Pad to I1, I2 via transparent input latch, no delay  
PLIC  
T
Pad to I1, I2 via transparent FCL and input latch,  
with delay  
16.5  
17.5  
18.0  
20.8  
PDLIC  
14.0  
14.4  
-
Propagation Delays (TTL Inputs)  
T
Clock (IK) to I1, I2 (flip-flop)  
All devices  
All devices  
-
-
2.8  
4.0  
-
-
5.6  
6.2  
ns  
ns  
IKRI  
T
Clock (IK) to I1, I2 (latch enable, active Low)  
IKLI  
Hold Times(2)  
T
Pad to clock (IK), no delay  
All devices  
All devices  
All devices  
All devices  
0
0
-
-
-
-
0
0
-
-
-
-
ns  
ns  
ns  
ns  
IKPI  
T
Pad to clock (IK), with delay  
IKPID  
T
Clock enable (EC) to clock (K), no delay  
Clock enable (EC) to clock (K), with delay  
1.5  
0
1.5  
0
IKEC  
T
IKECD  
Notes:  
1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock  
input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.  
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up  
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.  
14  
www.xilinx.com  
DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E IOB Input Switching Characteristic Guidelines (continued)  
-3  
-4  
Symbol  
Description  
Device  
Min  
Max  
Min  
Max  
Units  
Setup Times (TTL Inputs)(1,2)  
T
Pad to clock (IK), no delay  
Pad to clock (IK), with delay  
All devices  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
2.6  
-
-
-
-
-
-
4.0  
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
PICK  
T
10.9  
11.3  
11.8  
14.0  
PICKD  
9.8  
10.2  
-
Setup Times (CMOS Inputs)(1,2)  
T
Pad to clock (IK), no delay  
Pad to clock (IK), with delay  
All devices  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
3.3  
-
-
-
-
-
-
6.0  
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
PICKC  
T
12.0  
13.0  
13.5  
16.0  
PICKDC  
10.5  
10.9  
-
(TTL or CMOS)  
T
Clock enable (EC) to clock (IK), no delay  
Clock enable (EC) to clock (IK), with delay  
All devices  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
2.5  
-
-
-
-
-
-
3.5  
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ECIK  
T
10.4  
10.7  
11.1  
14.0  
ECIKD  
9.7  
10.1  
-
Global Set/Reset(3)  
T
Delay from GSR net through Q to I1, I2  
GSR width  
All devices  
All devices  
All devices  
-
7.8  
-
12.0  
ns  
ns  
ns  
RRI  
T
11.5  
11.5  
-
-
13.0  
13.0  
-
-
MRW  
T
GSR inactive to first active clock (IK) edge  
MRI  
Notes:  
1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock  
input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.  
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up  
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.  
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
15  
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4000E IOB Output Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
These path delays, provided as a guideline, have been  
extracted from the static timing analyzer report. All timing  
parameters assume worst-case operating conditions (sup-  
ply voltage and junction temperature). For Propagation  
Delays, slew-rate = fast unless otherwise noted. Values  
apply to all XQ4000E devices unless otherwise noted.  
-3  
-4  
Symbol  
Description  
Min  
Max  
Min  
Max  
Units  
Propagation Delays (TTL Output Levels)  
T
T
Clock (OK) to pad, fast  
-
-
-
-
-
-
-
6.5  
9.5  
5.5  
8.6  
4.2  
8.1  
11.1  
-
-
-
-
-
-
-
7.5  
11.5  
8.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
OKPOF  
Clock (OK) to pad, slew-rate limited  
Output (O) to pad, fast  
OKPOS  
T
T
OPF  
Output (O) to pad, slew-rate limited  
3-state to pad High-Z, slew-rate independent  
3-state to pad active and valid, fast  
3-state to pad active and valid, slew-rate limited  
12.0  
10.0  
10.0  
13.7  
OPS  
T
TSHZ  
TSONF  
TSONS  
T
T
Propagation Delays (CMOS Output Levels)  
T
T
Clock (OK) to pad, fast  
-
-
-
-
-
-
-
7.8  
11.6  
9.7  
-
-
-
-
-
-
-
9.5  
13.5  
10.0  
14.0  
5.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
OKPOFC  
OKPOSC  
Clock (OK) to pad, slew-rate limited  
Output (O) to pad, fast  
T
T
OPFC  
Output (O) to pad, slew-rate limited  
3-state to pad High-Z, slew-rate independent  
3-state to pad active and valid, fast  
3-state to pad active and valid, slew-rate limited  
13.4  
4.3  
OPSC  
T
TSHZC  
TSONFC  
TSONSC  
T
T
7.6  
9.1  
11.4  
13.1  
Setup and Hold Times  
T
Output (O) to clock (OK) setup time  
Output (O) to clock (OK) hold time  
Clock enable (EC) to clock (OK) setup  
Clock enable (EC) to clock (OK) hold  
4.6  
0
-
-
-
-
5.0  
0
-
-
-
-
ns  
ns  
ns  
ns  
OOK  
T
OKO  
T
T
3.5  
1.2  
4.8  
1.2  
ECOK  
OKEC  
Clock  
T
Clock High  
Clock Low  
4.0  
4.0  
-
-
4.5  
4.5  
-
-
ns  
ns  
CH  
T
CL  
Global Set/Reset(3)  
T
Delay from GSR net to pad  
GSR width  
-
11.8  
-
15.0  
ns  
ns  
ns  
RRO  
T
11.5  
11.5  
-
-
13.0  
13.0  
-
-
MRW  
T
GSR inactive to first active clock (OK) edge  
MRO  
Notes:  
1. Output timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall  
times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the  
“Additional XC4000 Data” section on the Xilinx web site, www.xilinx.com/partinfo/databook.htm.  
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up  
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.  
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.  
16  
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Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines  
Testing of the switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are not  
measured directly. They are derived from benchmark timing  
patterns that are taken at device introduction, prior to any  
process improvements. For more detailed, more precise,  
and more up-to-date information, use the values provided  
by the XACT timing calculator and used in the simulator.  
These values can be printed in tabular format by running  
LCA2XNF-S.  
The following guidelines reflect worst-case values over the  
recommended operating conditions. They are expressed in  
units of nanoseconds and apply to all XC4000E devices  
unless otherwise noted.  
-3  
-4  
Symbol  
Description  
Min  
Max  
Min  
Max  
Units  
Setup Times  
T
Input (TDI) to clock (TCK)  
30.0  
15.0  
30.0  
15.0  
ns  
ns  
TDITCK  
T
Input (TMS) to clock (TCK)  
TMSTCK  
Hold Times  
T
Input (TDI) to clock (TCK)  
Input (TMS) to clock (TCK)  
0
0
0
0
ns  
ns  
TCKTDI  
T
TCKTMS  
Propagation Delay  
T
Clock (TCK) to pad (TDO)  
30.0  
15.0  
30.0  
15.0  
ns  
TCKPO  
Clock  
T
Clock (TCK) High  
Clock (TCK) Low  
Frequency  
5.0  
5.0  
5.0  
5.0  
ns  
ns  
TCKH  
T
TCKL  
F
MHz  
MAX  
Notes:  
1. Input setup and hold times and clock-to-pad times are specified with respect to external signal pins.  
2. Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall  
times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the  
“Additional XC4000 Data” section of the Programmable Logic Data Book.  
3. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up  
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.  
DS021 (v2.2) June 25, 2000  
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17  
Product Specification  
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R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX Switching Characteristics  
Definition of Terms  
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as  
follows:  
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families.  
Values are subject to change. Use as estimates, not for production.  
Preliminary: Based on preliminary characterization. Further changes are not expected.  
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.  
Except for pin-to-pin input and output parameters, the A.C. parameter delay specifications included in this document are  
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction  
temperature conditions.  
All specifications subject to change without notice.  
XQ4028EX Absolute Maximum Ratings(1)  
Symbol  
Description  
Units  
V
V
Supply voltage relative to GND  
–0.5 to +7.0  
–0.5 to V + 0.5  
CC  
(2)  
V
Input voltage relative to GND  
V
IN  
TS  
CC  
(2)  
V
Voltage applied to High-Z output  
–0.5 to V + 0.5  
V
CC  
V
T
Longest supply voltage rise time from 1V to 4V  
Storage temperature (ambient)  
50  
–65 to +150  
+260  
ms  
°C  
°C  
°C  
°C  
CCt  
STG  
SOL  
T
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)  
T
Junction temperature  
Ceramic package  
Plastic package  
+150  
J
+125  
Notes:  
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress  
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions  
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.  
2. Maximum DC excursion above V or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve.  
CC  
Maximum total combined current on all dedicated inputs and Tri-state outputs must not exceed 200 mA. During transitions, the  
device pins may undershoot to –2.0V or overshoot toV +2.0V, provided this over or undershoot lasts less than 10 ns and with the  
CC  
forcing current being limited to 200 mA.  
18  
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DS021 (v2.2) June 25, 2000  
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Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX Recommended Operating Conditions(1)  
Symbol  
Descriptiont  
Min  
4.5  
4.5  
2.0  
70%  
0
Max  
5.5  
Units  
V
Supply voltage relative to GND, T = –55°C to +125°C Plastic  
V
V
V
CC  
J
Supply voltage relative to GND, T = –55°C to +125°C Ceramic  
5.5  
C
(2)  
V
High-level input voltage  
Low-level input voltage  
Input signal transition time  
TTL inputs  
V
CC  
IH  
CMOS inputs  
TTL inputs  
100%  
0.8  
V
CC  
V
V
IL  
CMOS inputs  
0
20%  
250  
V
CC  
T
-
ns  
IN  
Notes:  
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.  
2. Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS.  
XQ4028EX DC Characteristics Over Recommended Operating Conditions  
Symbol  
Description  
Min  
Max  
-
Units  
V
V
High-level output voltage at I  
High-level output voltage at I  
= –4 mA, V min  
TTL outputs  
2.4  
OH  
OH  
OH  
CC  
= –1 mA  
CMOS outputs  
TTL outputs  
V
– 0.5  
-
V
CC  
(1)  
V
Low-level output voltage at I = 12 mA, V min  
-
-
0.4  
0.4  
-
V
OL  
OL  
CC  
CMOS outputs  
V
V
Data retention supply voltage (below which configuration data may be lost)  
3.0  
-
V
DR  
(2)  
I
Quiescent FPGA supply current  
25  
10  
10  
16  
0.25  
0.25  
2.0  
mA  
µA  
V
CCO  
I
Input or output leakage current  
–10  
-
L
C
Input capacitance (sample tested)  
Plastic packages  
IN  
Ceramic packages  
-
V
I
I
Pad pull-up (when selected) at V = 0V (sample tested)  
0.02  
0.02  
0.3  
mA  
mA  
mA  
RPU  
RPD  
IN  
Pad pull-down (when selected) at V = 5.5V (sample tested)  
IN  
(3)  
I
Horizontal longline pull-up (when selected) at logic Low  
RLL  
Notes:  
1. With up to 64 pins simultaneously sinking 12 mA.  
2. With no output current loads, no active input or Longline pull-up resistors, all package pins at V or GND.  
CC  
DS021 (v2.2) June 25, 2000  
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19  
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX Switching Characteristic Guidelines  
Testing of the switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values where one global clock input  
drives one vertical clock line in each accessible column, and  
where all accessible IOB and CLB flip-flops are clocked by  
the global clock net.  
driven from the same global clock, the delay is longer. For  
more specific, more precise, and worst-case guaranteed  
data, reflecting the actual routing structure, use the values  
provided by the static timing analyzer (TRCE in the Xilinx  
Development System) and back-annotated to the simulation  
netlist. These path delays, provided as a guideline, have  
been extracted from the static timing analyzer report. All  
timing parameters assume worst-case operating conditions  
(supply voltage and junction temperature)  
When fewer vertical clock lines are connected, the clock dis-  
tribution is faster; when multiple clock lines per column are  
Global Buffer Switching Characteristics.  
-4  
Symbol  
Description  
Max  
9.2  
Units  
ns  
T
From pad through Global Low Skew buffer, to any clock K  
GLS  
T
From pad through Global Early buffer, to any clock K in same quadrant  
5.7  
ns  
GE  
XQ4028EX Horizontal Longline Switching Characteristic Guidelines  
-4  
Symbol  
Description  
Max  
Units  
TBUF Driving a Horizontal Longline  
T
I going High or Low to horizontal longline going High or Low, while T is Low. Buffer is  
constantly active.  
13.7  
14.7  
ns  
ns  
IO1  
T
T going Low to horizontal longline going from resistive pull-up or floating High to active Low.  
TBUF configured as open-drain or active buffer with I = Low.  
ON  
TBUF Driving Half a Horizontal Longline  
T
I going High or Low to half of a horizontal longline going High or Low, while T is Low. Buffer  
is constantly active.  
6.3  
7.2  
ns  
ns  
HIO1  
T
T going Low to half of a horizontal longline going from resistive pull-up or floating High to  
active Low. TBUF configured as open-drain or active buffer with I = Low.  
HON  
Notes:  
1. These values include a minimum load of one output, spaced as far as possible from the activated pull-up(s). Use the static timing  
analyzer to determine the delay for each destination.  
20  
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DS021 (v2.2) June 25, 2000  
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Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX CLB Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all XQ4000EX devices unless otherwise noted.  
CLB Switching Characteristics  
-4  
Symbol  
Description  
Min  
Max  
Units  
Combinatorial Delays  
T
F/G inputs to X/Y outputs  
-
-
-
-
-
-
-
2.2  
3.8  
3.2  
3.6  
3.0  
3.6  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ILO  
T
F/G inputs via H’ to X/Y outputs  
IHO  
T
F/G inputs via transparent latch to Q outputs  
C inputs via SR/H0 via H to X/Y outputs  
C inputs via H1 via H to X/Y outputs  
ITO  
T
HH0O  
HH1O  
HH2O  
CBYP  
T
T
T
C inputs via DIN/H2 via H to X/Y outputs  
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)  
CLB Fast Carry Logic  
Operand inputs (F1, F2, G1, G4) to C  
T
-
-
-
-
-
-
2.5  
4.1  
ns  
ns  
ns  
ns  
ns  
ns  
OPCY  
OUT  
T
Add/Subtract input (F3) to C  
OUT  
ASCY  
T
Initialization inputs (F1, F3) to C  
1.9  
INCY  
OUT  
T
C
C
through function generators to X/Y outputs  
3.0  
SUM  
IN  
IN  
T
T
to C  
, bypass function generators  
OUT  
0.60  
0.18  
BYP  
Carry net selay, C  
to C  
IN  
NET  
OUT  
Sequential Delays  
T
Clock K to flip-flop outputs Q  
Clock K to latch outputs Q  
-
-
2.2  
2.2  
ns  
ns  
CKO  
T
CKLO  
Setup Time before Clock K  
T
F/G inputs  
1.3  
3.0  
2.8  
2.2  
2.8  
1.2  
1.2  
0.8  
2.2  
3.9  
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ICK  
T
F/G inputs via H  
IHCK  
T
T
T
C inputs via H0 through H  
C inputs via H1 through H  
C inputs via H2 through H  
C inputs via DIN  
HH0CK  
HH1CK  
HH2CK  
T
DICK  
T
C inputs via EC  
ECCK  
T
C inputs via S/R, going Low (inactive)  
CIN input via F/G  
RCK  
T
CCK  
T
CIN input via F/G and H  
CHCK  
Hold Time after Clock K  
F/G inputs  
T
0
-
ns  
CKI  
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Product Specification  
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QPRO XQ4000E/EX QML High-Reliability FPGAs  
CLB Switching Characteristics (Continued)  
-4  
Symbol  
Description  
Min  
0
Max  
Units  
ns  
T
F/G inputs via H  
-
-
-
-
-
-
-
CKIH  
T
T
T
C inputs via SR/H0 through H  
C inputs via H1 through H  
C inputs via DIN/H2 through H  
C inputs via DIN/H2  
0
ns  
CKHH0  
CKHH1  
CKHH2  
0
ns  
0
ns  
T
0
ns  
CKDI  
T
C inputs via EC  
0
ns  
CKEC  
T
C inputs via SR, going Low (inactive)  
0
ns  
CKR  
Clock  
T
Clock High time  
Clock Low time  
3.5  
3.5  
-
-
ns  
ns  
CH  
T
CL  
Set/Reset Direct  
T
Width (High)  
3.5  
-
-
ns  
ns  
RPW  
T
Delay from C inputs via S/R, going High to Q  
4.5  
RIO  
Global Set/Reset  
T
Minimum GSR pulse width  
-
-
-
13.0  
22.8  
143  
ns  
MRW  
T
Delay from GSR input to any Q  
Toggle frequency (MHz) (for export control)  
MRQ  
F
MHz  
TOG  
22  
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Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all XQ4000EX devices unless otherwise noted.  
-4  
Symbol  
Single Port RAM  
Size  
Min  
Max  
Units  
Write Operation  
T
Address write cycle time (clock K period)  
Clock K pulse width (active edge)  
Address setup time before clock K  
Address hold time after clock K  
DIN setup time before clock K  
DIN hold time after clock K  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
11.0  
11.0  
5.5  
5.5  
2.7  
2.6  
0
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WCS  
T
-
WCTS  
T
-
WPS  
T
-
WPTS  
T
-
ASS  
T
-
ASTS  
T
-
AHS  
T
0
-
AHTS  
T
2.4  
2.9  
0
-
DSS  
T
-
DSTS  
T
-
DHS  
T
0
-
DHTS  
T
WE setup time before clock K  
WE hold time after clock K  
2.3  
2.1  
0
-
WSS  
T
T
T
-
-
WSTS  
T
WHS  
0
-
WHTS  
T
Data valid after clock K  
-
8.2  
10.1  
WOS  
-
WOTS  
Notes:  
1. Applicable Read timing specifications are identical to Level-Sensitive Read timing.  
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics  
-4  
(1)  
Symbol  
Dual Port RAM  
Size  
Min  
Max Units  
Write Operation  
T
T
Address write cycle time (clock K period)  
Clock K pulse width (active edge)  
Address setup time before clock K  
Address hold time after clock K  
DIN setup time before clock K  
DIN hold time after clock K  
16x1  
16x1  
16x1  
16x1  
16x1  
16x1  
16x1  
16x1  
16x1  
11.0  
5.5  
3.1  
0
ns  
WCDS  
WPDS  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
T
-
ASDS  
T
-
AHDS  
T
T
2.9  
0
-
DSDS  
DHDS  
WSDS  
WHDS  
WODS  
-
-
T
T
T
WE setup time before clock K  
WE hold time after clock K  
2.1  
0
-
Data valid after clock K  
-
9.4  
Notes:  
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.  
2. Applicable Read timing specifications are identical to Level-Sensitive Read timing.  
DS021 (v2.2) June 25, 2000  
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23  
Product Specification  
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R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform  
TWPS  
WCLK (K)  
TWSS  
TWHS  
TDHS  
TAHS  
WE  
TDSS  
DATA IN  
TASS  
ADDRESS  
TILO  
TILO  
TWOS  
DATA OUT  
OLD  
NEW  
DS021_01_060100  
XQ4028EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform  
TWPDS  
WCLK (K)  
TWSS  
TWHS  
WE  
TDHDS  
TDSDS  
DATA IN  
TAHDS  
TASDS  
ADDRESS  
DATA OUT  
TILO  
TILO  
TWODS  
OLD  
NEW  
DS021_02_060100  
24  
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DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all XQ4000EX devices unless otherwise noted.  
-4  
Symbol  
Single Port RAM  
Size  
Min  
Max  
Units  
Write Operation  
T
Address write cycle time  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
10.6  
10.6  
5.3  
5.3  
2.8  
2.8  
1.7  
1.7  
1.1  
1.1  
6.6  
6.6  
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
T
WCT  
T
Write Enable pulse width (High)  
Address setup time before WE  
Address hold time after end of WE  
DIN setup time before end of WE  
DIN hold time after end of WE  
WP  
T
WPT  
T
AS  
T
AST  
T
AH  
T
AHT  
T
DS  
T
T
DST  
T
DH  
DHT  
Read Operation  
T
Address read cycle time  
16x2  
32x1  
16x2  
32x1  
4.5  
6.5  
-
-
ns  
ns  
ns  
ns  
RC  
T
-
RCT  
T
Data valid after address change (no Write Enable)  
2.2  
3.8  
ILO  
T
-
IHO  
Read Operation, Clocking Data into Flip-Flop  
Address setup time before clock K  
T
16x2  
32x1  
1.5  
3.2  
-
-
ns  
ns  
ICK  
T
IHCK  
Read During Write  
T
Data valid after WE goes active (DIN stable before WE)  
16x2  
32x1  
16x2  
32x1  
-
-
-
-
6.5  
7.4  
7.7  
8.2  
ns  
ns  
ns  
ns  
WO  
T
WOT  
T
Data valid after DIN (DIN changes during WE)  
DO  
T
DOT  
Read During Write, Clocking Data into Flip-Flop  
T
WE setup time before clock K  
16x2  
32x1  
16x2  
32x1  
7.1  
9.2  
5.9  
8.4  
-
-
-
-
ns  
ns  
ns  
ns  
WCK  
T
WCKT  
T
Data setup time before clock K  
DCK  
T
DOCK  
Notes:  
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.  
DS021 (v2.2) June 25, 2000  
Product Specification  
www.xilinx.com  
1-800-255-7778  
25  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX CLB Level-Sensitive RAM Timing Waveforms  
WRITE  
TWC  
ADDRESS  
WE  
TAS  
TWP  
TAH  
TDS  
TDH  
DATA IN  
REQUIRED  
READ WITHOUT WRITE  
TILO  
X,Y OUTPUTS  
VALID  
VALID  
READ, CLOCKING DATA INTO FLIP-FLOP  
TICK  
TCH  
CLOCK  
TCKO  
XQ,YQ OUTPUTS  
VALID (OLD)  
VALID (NEW)  
READ DURING WRITE  
TWP  
WRITE ENABLE  
TDH  
DATA IN  
(stable during WE)  
TWO  
X,Y OUTPUTS  
VALID  
VALID  
NEW  
DATA IN  
(changing during WE)  
OLD  
TWO  
TDO  
VALID  
(PREVIOUS)  
VALID  
(OLD)  
VALID  
(NEW)  
X,Y OUTPUTS  
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP  
TWP  
WRITE ENABLE  
TWCK  
TDCK  
DATA IN  
CLOCK  
TCKO  
XQ,YQ OUTPUTS  
DS021_03_060100  
Figure 1:  
26  
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DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX Pin-to-Pin Output Parameter Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Pin-to-pin timing parameters are  
derived from measuring external and internal test patterns  
and are guaranteed over worst-case operating conditions  
(supply voltage and junction temperature). Listed below are  
representative values for typical pin locations and normal  
clock loading. For more specific, more precise, and  
worst-case guaranteed data, reflecting the actual routing  
structure, use the values provided by the static timing ana-  
lyzer (TRCE in the Xilinx Development System) and  
back-annotated to the simulation netlist. These path delays,  
provided as a guideline, have been extracted from the static  
timing analyzer report. Values apply to all XQ4000EX  
devices unless otherwise noted.  
XQ4028EX Output Flip-Flop, Clock to Out(1,2)  
-4  
Symbol  
Description  
Max  
16.6  
13.1  
Units  
ns  
(3)  
T
Global low skew clock to output using OFF  
ICKOF  
(3)  
T
Global early clock to output using OFF  
ns  
ICKEOF  
Notes:  
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and  
where all accessible IOB and CLB flip-flops are clocked by the global clock net.  
2. Output timing is measured at TTL threshold with 50 pF external capacitive load.  
3. OFF = Output Flip-Flop  
XQ4028EX Output Mux, Clock to Out(1,2)  
-4  
Symbol  
Description  
Max  
15.9  
12.4  
Units  
ns  
3)  
T
Global low skew clock to TTL output (fast) using OMUX  
PFPF  
(3)  
T
Global early clock to TTL output (fast) using OMUXF  
ns  
PEFPF  
Notes:  
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and  
where all accessible IOB and CLB flip-flops are clocked by the global clock net.  
2. Output timing is measured at ~50% V threshold with 50 pF external capacitive load. For different loads, see graph below.  
CC  
3. OMUX = Output MUX  
XQ4028EX Output Level and Slew Rate Adjustments  
The following table must be used to adjust output parameters and output switching characteristics.  
-4  
Symbol  
Description  
Max  
0
Units  
ns  
T
For TTL output FAST add  
For TTL output SLOW add  
For CMOS FAST output add  
For CMOS SLOW output add  
TTLOF  
T
2.9  
1.0  
3.6  
ns  
TTLO  
T
ns  
CMOSOF  
T
ns  
CMOSO  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
27  
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX Pin-to-Pin Input Parameter Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Pin-to-pin timing parameters are  
derived from measuring external and internal test patterns  
and are guaranteed over worst-case operating conditions  
(supply voltage and junction temperature). Listed below are  
representative values for typical pin locations and normal  
clock loading. For more specific, more precise, and  
worst-case guaranteed data, reflecting the actual routing  
structure, use the values provided by the static timing ana-  
lyzer (TRCE in the Xilinx Development System) and  
back-annotated to the simulation netlist. These path delays,  
provided as a guideline, have been extracted from the static  
timing analyzer report. Values apply to all XQ4000EX  
devices unless otherwise noted  
XQ4028EX Global Low Skew Clock, Setup and Hold  
-4  
Min  
8.0  
0
Symbol  
Description  
Units  
ns  
T
Input setup time, using Global Low Skew clock and IFF (full delay)  
Input hold time, using Global Low Skew clock and IFF (full delay)  
PSD  
PHD  
T
ns  
Notes:  
1. IFF = Flip-Flop or Latch  
XQ4028EX Global Early Clock, Setup and Hold for IFF  
-4  
(2)  
Symbol  
Description  
Min  
Units  
ns  
T
Input setup time, using Global Early clock and IFF (full delay)  
Input hold time, using Global Early clock and IFF (full delay)  
6.5  
0
PSEP  
PHEP  
T
ns  
Notes:  
1. IFF = Flip-Flop or Latch  
2. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6.  
XQ4028EX Global Early Clock, Setup and Hold for FCL  
-4  
(2)  
Symbol  
Description  
Min  
3.4  
0
Units  
ns  
T
Input setup time, using Global Early clock and FCL (partial delay)  
Input hold time, using Global Early clock and FCL (partial delay)  
PFSEP  
PFHEP  
T
ns  
Notes:  
1. FCL = Fast Capture Latch  
2. For CMOS input levels, see the XQ4028EX Input Threshold Adjustments.  
3. Setup time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time under  
given design conditions.  
4. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer  
to determine the setup and hold times under given design conditions.  
5. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6.  
XQ4028EX Input Threshold Adjustments  
The following table must be used to adjust input parameters and input switching characteristics.  
-4  
Symbol  
Description  
Max  
0
Units  
ns  
T
For TTL input add  
TTLI  
T
For CMOS input add  
0.3  
ns  
CMOSI  
28  
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DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX IOB Input Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
These path delays, provided as a guideline, have been  
extracted from the static timing analyzer report. All timing  
parameters assume worst-case operating conditions (sup-  
ply voltage and junction temperature). Values apply to all  
XQ4000EX devices unless otherwise noted.  
-4  
Symbol  
Clocks  
Description  
Min  
Units  
T
Delay from FCL enable (OK) active to IFF clock (IK) active edge  
3.2  
ns  
OKIK  
Propagation Delays  
T
Pad to I1, I2  
2.2  
3.8  
ns  
ns  
ns  
ns  
ns  
ns  
PID  
T
Pad to I1, I2 via transparent input latch, no delay  
Pad to I1, I2 via transparent input latch, partial delay  
Pad to I1, I2 via transparent input latch, full delay  
Pad to I1, I2 via transparent FCL and input latch, no delay  
Pad to I1, I2 via transparent FCL and input latch, partial delay  
PLI  
T
T
13.3  
18.2  
5.3  
PPLI  
PDLI  
T
PFLI  
T
13.6  
PPFLI  
Propagation Delays (TTL Inputs)  
T
Clock (IK) to I1, I2 (flip-flop)  
3.0  
3.2  
6.2  
ns  
ns  
ns  
IKRI  
T
Clock (IK) to I1, I2 (latch enable, active Low)  
IKLI  
T
FCL enable (OK) active edge to I1, I2 (via transparent standard input latch)  
OKLI  
Global Set/Reset  
T
Minimum GSR pulse width  
13.0  
22.8  
ns  
ns  
MRW  
T
Delay from GSR input to any Q  
RRI  
Notes:  
1. FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch  
2. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.  
3. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold  
tables on page 28.  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
29  
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)  
-4  
Symbol  
Description  
Min  
Units  
Setup Times  
T
Pad to Clock (IK), no delay  
Pad to Clock (IK), partial delay  
Pad to Clock (IK), full delay  
2.5  
10.8  
15.7  
3.9  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PICK  
T
T
PICKP  
PICKD  
T
Pad to Clock (IK), via transparent Fast Capture Latch, no delay  
Pad to Clock (IK), via transparent Fast Capture Latch, partial delay  
Pad to Fast Capture Latch Enable (OK), no delay  
PICKF  
T
12.3  
0.8  
PICKFP  
T
POCK  
T
Pad to Fast Capture Latch Enable (OK), partial delay  
9.1  
POCKP  
Setup Times (TTL or CMOS Inputs)  
T
Clock Enable (EC) to Clock (IK)  
0.3  
ns  
ECIK  
Hold Times  
T
Pad to Clock (IK), no delay  
0
0
0
0
0
0
0
0
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
IKPI  
T
T
T
Pad to Clock (IK), partial delay  
IKPIP  
IKPID  
IKPIF  
Pad to Clock (IK), full delay  
Pad to Clock (IK) via transparent Fast Capture Latch, no delay  
Pad to Clock (IK) via transparent Fast Capture Latch, partial delay  
Pad to Clock (IK) via transparent Fast Capture Latch, full delay  
Clock Enable (EC) to Clock (IK), no delay  
T
T
IKFPIP  
IKFPID  
T
IKEC  
IKECP  
IKECD  
T
T
Clock Enable (EC) to Clock (IK), partial delay  
Clock Enable (EC) to Clock (IK), full delay  
T
Pad to Fast Capture Latch Enable (OK), no delay  
Pad to Fast Capture Latch Enable (OK), partial delay  
OKPI  
T
OKPIP  
Notes:  
1. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.  
2. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold  
tables on page 28.  
30  
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DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
FXQ4028EX IOB Output Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
These path delays, provided as a guideline, have been  
extracted from the static timing analyzer report. All timing  
parameters assume worst-case operating conditions (sup-  
ply voltage and junction temperature). For Propagation  
Delays, slew-rate = fast unless otherwise noted. Values  
apply to all XQ4000EX devices unless otherwise noted.  
-4  
Symbol  
Description  
Min  
Max  
Units  
Propagation Delays (TTL Output Levels)  
T
Clock (OK) to pad, fast  
Output (O) to pad, fast  
-
-
-
-
-
-
-
7.4  
6.2  
4.9  
6.2  
6.7  
6.2  
7.3  
ns  
ns  
ns  
ns  
ns  
OKPOF  
T
OPF  
T
3-state to pad High-Z, slew-rate independent  
3-state to pad active and valid, fast  
TSHZ  
TSONF  
OKFPF  
CEFPF  
T
T
T
Output MUX select (OK) to pad  
Fast path output MUX input (EC) to pad  
Slowest path output MUX input (EC) to pad  
T
OFPF  
Setup and Hold Times  
T
Output (O) to clock (OK) setup time  
Output (O) to clock (OK) hold time  
Clock enable (EC) to clock (OK) setup  
Clock enable (EC) to clock (OK) hold  
0.6  
0
-
-
-
-
ns  
ns  
ns  
ns  
OOK  
T
OKO  
T
T
0
ECOK  
OKEC  
0
Clocks  
T
Clock High  
Clock Low  
3.5  
3.5  
-
-
ns  
ns  
CH  
T
CL  
Global Set/Reset  
T
Minimum GSR pulse width  
13.0  
30.2  
-
-
ns  
ns  
MRW  
T
Delay from GSR input to any pad  
RRI  
Notes:  
1. Output timing is measured at TTL threshold, with 35 pF external capacitive loads.  
2. For CMOS output levels, see the "XQ4028EX Output Level and Slew Rate Adjustments" on page 27.  
DS021 (v2.2) June 25, 2000  
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31  
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
CB191/196 Package for XQ4010E  
Bound  
Scan  
Pin Description  
PG191 CB196  
Bound  
Scan  
I/O  
B12  
A13  
C12  
B13  
A14  
A15  
C13  
B14  
A16  
B15  
C14  
A17  
B16  
C15  
D15  
A18  
D16  
C16  
B17  
E16  
-
P34  
P35  
P36  
P37  
P38  
P39  
P40  
P41  
P42  
P43  
P44  
P45  
P46  
P47  
P48  
P49  
P50  
P51  
P52  
P53  
206  
209  
-
Pin Description  
PG191 CB196  
I/O  
GND  
D4  
C3  
C4  
B3  
P1  
P2  
P3  
P4  
-
GND  
PGCK1_(A16*I/0)  
122  
125  
128  
-
I/O  
212  
215  
218  
221  
224  
227  
230  
233  
236  
239  
242  
-
I/O_(A17)  
I/0  
I/O  
I/O  
(1)  
-
-
P5  
I/O  
I/O  
C5  
A2  
P6  
131  
134  
137  
140  
143  
146  
149  
-
I/O  
I/O_(TDI)  
I/O_(TCK)  
I/O  
P7  
I/O  
B4  
P8  
I/O  
C6  
A3  
P9  
I/O  
I/O  
P10  
P11  
P12  
P13  
P14  
P15  
P16  
P17  
P18  
P19  
P20  
P21  
P22  
P23  
P24  
P25  
P26  
P27  
P28  
P29  
P30  
P31  
P32  
P33  
I/O  
I/O  
B5  
SCGK2_(I/O)  
I/O  
B6  
M1  
GND  
I/O  
C7  
A4  
GND  
152  
155  
158  
161  
164  
167  
170  
173  
176  
179  
-
(2)  
M0  
245  
I/O  
A5  
VCC  
-
I/O_(TMS)  
I/O  
B7  
(2)  
M2  
246  
A6  
PGCK2_(I/O)  
247  
250  
-
I/O  
C8  
A7  
I/O_(HDC)  
I/O  
(1)  
-
I/O  
P54  
I/O  
B8  
C17  
D17  
B18  
E17  
F16  
C18  
D18  
F17  
G16  
E18  
F18  
G17  
G18  
P55  
P56  
P57  
P58  
P59  
P60  
P61  
P62  
P63  
P64  
P65  
P66  
P67  
253  
256  
259  
262  
265  
268  
271  
274  
-
I/O  
A8  
I/0  
I/O  
B9  
I/O  
I/O  
C9  
D9  
D10  
C10  
B10  
A9  
I/O_(LDC)  
I/O  
GND  
VCC  
I/O  
-
I/O  
182  
185  
-
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
A10  
A11  
C11  
B11  
A12  
191  
194  
197  
200  
203  
277  
280  
283  
286  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Notes:  
1. Indicates unconnected package pins.  
2. Contributes only one bit (.I) to the boundary scan register.  
Boundary Scan Bit 0 = TD0.T  
Notes:  
1. Indicates unconnected package pins.  
2. Contributes only one bit (.I) to the boundary scan register.  
Boundary Scan Bit 0 = TD0.T  
Boundary Scan Bit 1 = TD0.0  
Boundary Scan Bit 487 = BSCAN.UPD  
Boundary Scan Bit 1 = TD0.0  
Boundary Scan Bit 487 = BSCAN.UPD  
32  
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DS021 (v2.2) June 25, 2000  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
Bound  
Bound  
Scan  
Pin Description  
PG191 CB196  
Pin Description  
PG191 CB196  
Scan  
370  
-
I/O  
H16  
H17  
H18  
J18  
P68  
P69  
P70  
P71  
P72  
P73  
P74  
P75  
P76  
P77  
P78  
P79  
P80  
P81  
P82  
P83  
P84  
P85  
P86  
P87  
P88  
P89  
P90  
P91  
P92  
P93  
P94  
P95  
P96  
P97  
P98  
P99  
P100  
P101  
286  
291  
295  
298  
301  
304  
-
PGCK3_(I/O)  
-
U16  
-
P102  
(1)  
I/O  
P103  
P104  
P105  
P106  
P107  
P108  
P109  
P110  
P111  
P112  
P113  
P114  
P115  
P116  
P117  
P118  
P119  
P120  
P121  
P122  
P123  
P124  
P125  
P126  
P127  
P128  
P129  
P130  
P131  
P132  
P133  
P134  
P135  
I/O  
I/O  
T14  
U15  
V17  
V16  
T13  
U14  
V15  
V14  
T12  
U13  
V13  
U12  
V12  
T11  
U11  
V11  
V1  
376  
376  
379  
382  
385  
388  
391  
394  
-
I/O  
I/O  
I/O  
J17  
I/O_(D6)  
I/O  
I/O_(/ERR_/INIT)  
J16  
VCC  
GND  
I/O  
J15  
I/O  
K15  
K16  
K17  
K18  
L18  
L17  
L16  
M18  
M17  
N18  
P18  
M16  
N17  
R18  
T18  
P17  
N16  
T17  
R17  
P16  
U18  
T16  
R16  
U17  
R15  
V18  
T15  
-
I/O  
307  
310  
313  
316  
319  
322  
325  
328  
331  
334  
-
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
397  
400  
403  
406  
409  
412  
415  
418  
421  
424  
-
I/O  
I/O  
I/O  
I/O_(D5)  
I/O_(/CSO)  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
337  
340  
343  
349  
349  
352  
355  
358  
361  
364  
-
I/O_(D4)  
I/O  
U10  
T10  
R10  
R9  
I/O  
I/O  
VCC  
GND  
I/O_(D3)  
I/O_(/RS)  
I/O  
I/O  
-
I/O  
T9  
427  
430  
433  
436  
439  
442  
445  
448  
451  
454  
-
I/O  
U9  
I/O  
V9  
I/O  
I/O  
V8  
I/O  
I/O  
U8  
SGCK3_(I/O)  
GND  
DONE  
VCC  
/PROG  
I/O_(D7)  
I/O  
T8  
I/O_(D2)  
I/O  
V7  
-
U7  
-
I/O  
V6  
-
I/O  
U6  
367  
GND  
T7  
Notes:  
1. Indicates unconnected package pins.  
Notes:  
1. Indicates unconnected package pins.  
2. Contributes only one bit (.I) to the boundary scan register.  
Boundary Scan Bit 0 = TD0.T  
2. Contributes only one bit (.I) to the boundary scan register.  
Boundary Scan Bit 0 = TD0.T  
Boundary Scan Bit 1 = TD0.0  
Boundary Scan Bit 1 = TD0.0  
Boundary Scan Bit 487 = BSCAN.UPD  
Boundary Scan Bit 487 = BSCAN.UPD  
DS021 (v2.2) June 25, 2000  
Product Specification  
www.xilinx.com  
1-800-255-7778  
33  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
Bound  
Bound  
Scan  
Pin Description  
PG191 CB196  
Scan  
457  
460  
463  
446  
469  
472  
475  
478  
481  
484  
-
Pin Description  
PG191 CB196  
I/O  
V5  
V4  
U5  
T6  
V3  
V2  
U4  
T5  
U3  
T4  
V1  
R4  
U2  
R3  
T3  
U1  
-
P136  
P137  
P138  
T139  
P140  
P141  
P142  
P143  
P144  
P145  
P146  
P147  
P148  
P149  
P150  
P151  
I/O  
I/O_(A6)  
I/O_(A7)  
GND  
K1  
K2  
K3  
K4  
J4  
P169  
P170  
P171  
P172  
P173  
P174  
P175  
P176  
P177  
P178  
P179  
P180  
P181  
P182  
P183  
P184  
P185  
P186  
P187  
P188  
P189  
P190  
53  
56  
59  
-
I/O  
I/O  
I/O  
I/O_(D1)  
VCC  
-
I/O_(RCLK-/BUSY/RDY)  
I/O_(A8)  
I/O_(A9)  
I/O  
J3  
62  
65  
68  
71  
74  
77  
80  
83  
86  
89  
-
I/O  
J2  
I/O  
J1  
I/O_(D0*_DIN)  
I/O  
H1  
H2  
H3  
G1  
G2  
F1  
E1  
G3  
F2  
D1  
C1  
E2  
F3  
D2  
-
SGCK4_(DOUT*_I/O)  
I/O  
CCLK  
I/O  
VCC  
-
I/O_(A10)  
I/O_(A11)  
I/O  
TDO  
-
GND  
-
I/O_(A0*_WS)  
2
I/O  
PGCK4_(I/O*_A1)  
5
GND  
(1)  
-
P152  
P153  
P154  
P155  
P156  
P157  
P158  
P159  
P160  
P161  
P162  
P163  
P164  
P165  
P166  
P167  
P168  
-
I/O  
92  
96  
98  
101  
104  
107  
-
I/O  
P3  
R2  
T2  
N3  
P2  
T1  
R1  
N2  
M3  
P1  
N1  
M2  
M1  
L3  
L2  
L1  
8
I/O  
I/O  
I/O_(CS1*_A2)  
I/O_(A3)  
I/O  
11  
14  
17  
20  
23  
26  
29  
-
I/O  
I/O  
I/O_(A12)  
I/O_(A13  
-
(1)  
I/O  
P192  
P193  
P194  
P195  
P196  
I/O  
I/O  
E3  
C2  
B2  
D3  
113  
116  
119  
-
I/O  
I/O_(A14)  
SGCK1(A15*I/O)  
VCC  
GND  
I/O  
32  
35  
38  
41  
44  
47  
50  
Notes:  
1. Indicates unconnected package pins.  
I/O  
I/O_(A4)  
I/O_(A5)  
I/O  
2. Contributes only one bit (.I) to the boundary scan register.  
Boundary Scan Bit 0 = TD0.T  
Boundary Scan Bit 1 = TD0.0  
Boundary Scan Bit 487 = BSCAN.UPD  
I/O  
Additional XQ4010E Package Pins  
I/O  
CB196  
Notes:  
1. Indicates unconnected package pins.  
No Connect Pins  
2. Contributes only one bit (.I) to the boundary scan register.  
Boundary Scan Bit 0 = TD0.T  
P5  
P54  
-
P103  
-
P152  
-
Boundary Scan Bit 1 = TD0.0  
P192  
Boundary Scan Bit 487 = BSCAN.UPD  
34  
www.xilinx.com  
1-800-255-7778  
DS021 (v2.2) June 25, 2000  
Product Specification  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
Ordering Information  
XQ 4010E -4 PG 191 M  
Temperature Range  
M = Ceramic (T = –55°C to +125°C)  
MIL-PRF-38535  
(QML) Processing  
C
N = Plastic (T = –55°C to +125°C)  
J
Device Type  
XQ4005E  
XQ4010E  
XQ4013E  
XQ4025E  
XQ4028EX  
Number of Pins  
Package Type  
CB = Top Brazed Ceramic Quad Flat Pack  
PG = Ceramic Pin Grid Array  
HQ = Plastic Quad Flat Pack  
Speed Grade  
-3  
-4  
BG = Plastic Ball Grid Array  
Revision History  
The following table shows the revision history for this document  
Date  
Version  
2.1  
Description  
05/19/98  
06/25/00  
Updates.  
2.2  
Updated timing specifications to match with commercial data sheet. Updated format.  
DS021 (v2.2) June 25, 2000  
www.xilinx.com  
35  
Product Specification  
1-800-255-7778  
R
QPRO XQ4000E/EX QML High-Reliability FPGAs  
36  
www.xilinx.com  
DS021 (v2.2) June 25, 2000  
1-800-255-7778  
Product Specification  

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