XQ4036XL-1CB432M [XILINX]
QML High-Reliability FPGAs; QML高可靠性的FPGA
| 型号： | XQ4036XL-1CB432M |
| 厂家： | 
XILINX, INC |
| 描述： | QML High-Reliability FPGAs |
| 文件： | 总22页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
QPRO XQ4000XL Series QML
High-Reliability FPGAs
0
2
DS029 (v1.3) June 25, 2000
Product Specification
•
Development system runs on most common computer
platforms
XQ4000X Series Features
•
Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing)
-
-
-
Interfaces to popular design environments
Fully automatic mapping, placement and routing
Interactive design editor for design optimization
•
•
Ceramic and plastic packages
Also available under the following standard microcircuit
drawings (SMD)
•
•
Highest capacity—over 180,000 usable gates
Additional routing over XQ4000E
-
-
-
-
XQ4013XL 5962-98513
XQ4036XL 5962-98510
XQ4062XL 5962-98511
XQ4085XL 5962-99575
-
Almost twice the routing capacity for high-density
designs
•
•
•
Buffered Interconnect for maximum speed
New latch capability in configurable logic blocks
•
For more information contact the Defense Supply
Center Columbus (DSCC)
Improved VersaRing™ I/O interconnect for better Fixed
pinout flexibility
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
-
Virtually unlimited number of clock signals
•
•
Available in -3 speed
•
Optional multiplexer or 2-input function generator on
device outputs
System featured Field-Programmable Gate Arrays
-
SelectRAM™ memory: on-chip ultra-fast RAM with
•
•
5V tolerant I/Os
·
·
synchronous write option
dual-port RAM option
0.35 µm SRAM process
-
-
-
-
-
-
-
Abundant flip-flops
Introduction
Flexible function generators
Dedicated high-speed carry logic
Wide edge decoders on each edge
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
networks
The QPRO™ XQ4000XL Series high-performance,
high-capacity Field Programmable Gate Arrays (FPGAs)
provide the benefits of custom CMOS VLSI, while avoiding
the initial cost, long development cycle, and inherent risk of
a conventional masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
•
•
•
•
System performance beyond 50 MHz
Flexible array architecture
Low power segmented routing architecture
Systems-oriented features
-
IEEE 1149.1-compatible boundary scan logic
support
Refer to the complete Commercial XC4000XL Series Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)
-
-
-
Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
12 mA sink current per XQ4000XL output
•
•
Configured by loading binary file
Unlimited reprogrammability
Readback capability
-
-
-
Program verification
Internal node observability
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS029 (v1.3) June 25, 2000
www.xilinx.com
1
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Table 1: XQ4000XL Series High Reliability Field Progammable Gate Arrays
Max
Logic
Gates
(No
Max.
RAM
Bits(No
Logic)
Typical Gate
Range
Number
of
Matrix CLBs Flip-Flops
Max.
User
I/O
Logic
(Logic and
CLB
Total
(1)
(1)
Device
Cells RAM)
RAM)
Packages
XQ4013XL
2432
3078
5472
7448
13,000
36,000
62,000
18,432
41,472
73,728
10,000-30,000
22,000-65,000
24x24
36x36
576
1,536
3,168
5,376
7,168
192 PG223, CB228,
PQ240, BG256
XQ4036XL
XQ4062XL
XQ4085XL
Notes:
1,296
2,304
3,136
288 PG411, CB228,
HQ240, BG352
40,000-130,000 48x48
384 PG475, CB228,
HQ240, BG432
85,000 100,352 55,000-180,000 56x56
448 PG475, CB228,
HQ240, BG432
1. Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM.
2
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c.
parameter delay specifications included in this document
are derived from measuring internal test patterns. All speci-
fications are representative of worst-case supply voltage
and junction temperature conditions. The parameters
included are common to popular designs and typical appli-
cations. For design considerations requiring more detailed
timing information, see the appropriate family AC supple-
ments available on the Xilinx web site at:
http://www.xilinx.com/partinfo/databook.htm.
Absolute Maximum Ratings(1)
Symbol
Description
Units
V
Supply voltage relative to GND
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
50
V
V
CC
(2)
V
Input voltage relative to GND
IN
(2)
V
Voltage applied to High-Z output
V
TS
V
T
Longest supply voltage rise time from 1V to 3V
Storage temperature (ambient)
ms
°C
°C
°C
°C
CCt
–65 to +150
+260
STG
SOL
T
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
T
Junction temperature
Ceramic package
Plastic package
+150
J
+125
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC overshoot or undershoot above V or below GND must be limited to either 0.5V or 10 mA, whichever is easier to
CC
achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to V + 2.0V, provided this over- or undershoot
CC
lasts less than 10 ns and with the forcing current being limited to 200 mA.
Recommended Operating Conditions(1)
Symbol
Description
Min
Max
3.6
Units
V
Supply voltage relative to GND, T = –55°C to +125°C Plastic
3.0
V
V
CC
J
Supply voltage relative to GND, T = –55°C to +125°C Ceramic
3.0
3.6
C
(2)
V
High-level input voltage
50% of V
5.5
V
IH
CC
V
Low-level input voltage
0
-
30% of V
250
V
IL
CC
T
Input signal transition time
ns
IN
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Input and output measurement threshold is ~50% of V
.
CC
DS029 (v1.3) June 25, 2000
www.xilinx.com
3
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
Max
Units
V
V
High-level output voltage at I
High-level output voltage at I
= –4 mA, V min (LVTTL)
2.4
-
-
OH
OH
OH
CC
= –500 µA, (LVCMOS)
90% V
V
CC
(1)
V
Low-level output voltage at I = 12 mA, V min (LVTTL)
-
0.4
V
OL
DR
OL
CC
Low-level output voltage at I = 1500 µA, (LVCMOS)
-
2.5
-
10% V
V
OL
CC
V
Data retention supply voltage (below which configuration data may be lost)
-
V
(2)
I
Quiescent FPGA supply current
5
mA
µA
pF
pF
mA
mA
mA
CCO
I
Input or output leakage current
–10
-
+10
10
L
C
Input capacitance (sample tested)
BGA, PQ, HQ, packages
PGA packages
IN
-
16
I
I
Pad pull-up (when selected) at V = 0V (sample tested)
0.02
0.02
0.3
0.25
0.15
2.0
RPU
RPD
IN
Pad pull-down (when selected) at V = 3.6V (sample tested)
IN
I
Horizontal longline pull-up (when selected) at logic Low
RLL
Notes:
1. With up to 64 pins simultaneously sinking 12 mA.
2. With no output current loads, no active input or Longline pull-up resistors, all I/O pins in a High-Z state and floating.
Power-On Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current
capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast
ramp-up time requires more current than a slow ramp-up
time. The slowest ramp-up time is 50 ms. Current capacity
is not specified for a ramp-up time faster than 2 ms. The cur-
rent capacity varies linealy with ramp-up time, e.g., an
XQ4036XL with a ramp-up time of 25 ms would require a
capacity predicted by the point on the straight line drawn
from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time
mark. This point is approximately 750 mA .
Ramp-up Time
Product
XQ4013 - 36XL
XC4062XL
Description
Minimum required current supply
Minimum required current supply
Minimum required current supply
Fast (120 µs)
Slow (50 ms)
500 mA
1A
2A
500 mA
(1)
(1)
XC4085XL
2A
500 mA
Notes:
1. The XC4085XL fast ramp-up time is 5 ms.
2. Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a
larger initialization current.
3. This specification applies to Commercial and Industrial grade products only.
4. Ramp-up Time is measured from 0V to 3.6V . Peak current required lasts less than 3 ms, and occurs near the internal power
DC
DC
on reset threshold voltage. After initialization and before configuration, I max is less than 10 mA.
CC
4
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL AC Switching Characteristic
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
Global Buffer Switching Characteristics
-3
Max
3.6
4.8
6.3
-
-1
All
Min
Symbol
Description
Device
Max
Units
ns
T
Delay from pad through Global Low Skew buffer, to any
clock K
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
0.6
1.1
1.4
1.6
-
-
GLS
ns
-
ns
5.7
ns
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
-3
Max
2.4
3.1
4.9
-
-1
All
Min
Symbol
Description
Device
Max
Units
ns
T
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6.
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
0.4
0.3
0.3
0.4
-
-
GE
ns
-
ns
4.7
ns
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
-3
Max
2.4
4.7
5.9
-
-1
All
Min
Symbol
Description
Device
Max
Units
ns
T
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8.
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
0.7
0.9
1.2
1.3
-
-
GE
ns
-
ns
5.5
ns
DS029 (v1.3) June 25, 2000
www.xilinx.com
5
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000XL devices and expressed in nanosec-
onds unless otherwise noted.
CLB Switching Characteristics
-3
-1
Symbol
Description
Min
Max
Min
Max
Units
Combinatorial Delays
T
F/G inputs to X/Y outputs
-
-
-
-
-
-
-
1.6
2.7
2.9
2.5
2.4
2.5
1.5
-
-
-
-
-
-
-
1.3
2.2
2.2
2.0
1.9
2.0
1.1
ns
ns
ns
ns
ns
ns
ns
ILO
IHO
T
F/G inputs via H’ to X/Y outputs
T
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
ITO
T
HH0O
HH1O
HH2O
CBYP
T
T
T
C inputs via D /H2 via H to X/Y outputs
IN
C inputs via EC, D /H2 to YQ, XQ output (bypass)
IN
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
T
-
-
-
-
-
-
2.7
3.3
-
-
-
-
-
-
2.0
2.5
ns
ns
ns
ns
ns
ns
OPCY
OUT
T
Add/subtract input (F3) to C
OUT
ASCY
T
Initialization inputs (F1, F3) to C
2.0
1.5
INCY
OUT
T
C
C
through function generators to X/Y outputs
2.8
2.4
SUM
IN
IN
T
T
to C
, bypass function generators
OUT
0.26
0.32
0.20
0.25
BYP
NET
Carry net delay, C
to C
IN
OUT
Sequential Delays
T
Clock K to flip-flop outputs Q
Clock K to latch outputs Q
-
-
2.1
2.1
-
-
1.6
1.6
ns
ns
CKO
T
CKLO
Setup Time Before Clock K
T
F/G inputs
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
-
-
-
-
-
-
-
-
-
-
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ICK
T
F/G inputs via H
IHCK
T
T
T
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
HH0CK
HH1CK
HH2CK
T
C inputs via D
IN
DICK
T
C inputs via EC
ECCK
T
C inputs via S/R, going Low (inactive)
RCK
CCK
T
C
C
input via F/G
IN
IN
T
input via F/G and H
CHCK
6
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
CLB Switching Characteristics (Continued)
-3
-1
Symbol
Description
Min
Max
Min
Max
Units
Hold Time After Clock K
T
F/G inputs
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CKI
T
F/G inputs via H
CKIH
T
T
T
C inputs via SR/H0 through H
C inputs via H1 through H
CKHH0
CKHH1
CKHH2
C inputs via D /H2 through H
IN
T
C inputs via D /H2
CKDI
IN
T
C inputs via EC
CKEC
T
C inputs via SR, going Low (inactive)
CKR
Clock
T
Clock High time
Clock Low time
3.0
3.0
-
-
2.5
2.5
-
-
ns
ns
CH
T
CL
Set/Reset Direct
T
Width (High)
3.0
-
-
2.5
-
-
ns
ns
RPW
T
Delay from C inputs via S/R, going High to Q
3.7
2.8
RIO
Global Set/Reset
T
Minimum GSR pulse width
-
19.8
-
15.0
ns
MRW
T
Delay from GSR input to any Q
Toggle frequency (MHz) (for export control)
See page 17 for T
values per device.
RRI
MRQ
F
-
166
-
200
MHz
TOG
DS029 (v1.3) June 25, 2000
www.xilinx.com
7
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000XL devices and are expressed in nano-
seconds unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3
-1
Symbol
Single Port RAM
Size
Min
Max
Min
Max
Units
Write Operation
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
9.0
9.0
4.5
4.5
2.2
2.2
0
-
7.7
7.7
3.9
3.9
1.7
1.7
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCS
T
-
-
WCTS
T
-
-
WPS
T
-
-
WPTS
T
-
-
ASS
T
-
-
ASTS
T
-
-
AHS
T
0
-
0
-
AHTS
T
D
D
setup time before clock K
hold time after clock K
2.0
2.5
0
-
1.7
2.1
0
-
DSS
IN
IN
T
-
-
DSTS
T
-
-
DHS
T
0
-
0
-
DHTS
T
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
2.0
1.8
0
-
-
1.6
1.5
0
-
-
WSS
T
T
T
WSTS
T
-
-
WHS
0
-
0
-
WHTS
T
-
6.8
8.1
-
5.8
6.9
WOS
-
-
WOTS
Read Operation
T
Address read cycle time
16x2
32x1
16x2
32x1
16x2
32x1
4.5
6.5
-
-
-
2.6
3.8
-
-
-
ns
ns
ns
ns
ns
ns
RC
T
RCT
T
Data valid after address change (no Write Enable)
Address setup time before clock K
1.6
2.7
-
1.3
2.2
-
ILO
IHO
ICK
T
T
-
-
1.1
2.2
0.9
1.7
T
-
-
IHCK
8
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3
-1
(1)
Symbol
Dual Port RAM
Size
Min Max Min Max Units
Write Operation
T
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
9.0
4.5
2.5
0
7.7
3.9
1.7
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCDS
WPDS
-
-
T
-
-
ASDS
T
-
-
AHDS
T
T
D
D
setup time before clock K
hold time after clock K
2.5
0
-
2.0
0
-
DSDS
DHDS
WSDS
WHDS
WODS
IN
IN
-
-
-
-
T
T
T
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
1.8
0
1.6
0
-
-
-
7.8
-
6.7
DS029 (v1.3) June 25, 2000
www.xilinx.com
9
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL CLB Single-Port RAM Synchronous (Edge-Triggered) Write Timing
TWPS
WCLK (K)
TWSS
TWHS
TDHS
TAHS
WE
TDSS
DATA IN
TASS
ADDRESS
TILO
TILO
TWOS
DATA OUT
OLD
NEW
DS029_01_011300
XQ4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
TWPDS
WCLK (K)
TWSS
TWHS
WE
TDHDS
TDSDS
DATA IN
TAHDS
TASDS
ADDRESS
DATA OUT
TILO
TILO
TWODS
OLD
NEW
DS029_02_011300
10
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Output Flip-Flop, Clock to Out(1,2,3)
-3
Max
8.6
9.8
11.3
-
-1
Max
-
All
Min
Symbol
Description
Device
Units
ns
(4)
T
Global low skew clock to output using OFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
All Devices
1.5
2.0
2.3
2.5
3.0
ICKOF
-
ns
-
ns
9.5
3.0
ns
T
For output SLOW option add
3.0
ns
SLOW
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
3. Output timing is measured at ~50% V threshold with 50 pF external capacitive load.
CC
4. OFF = Output Flip-Flop
Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6
-3
Max
7.4
8.1
9.9
-
-1
All
Min
Symbol
Description
Device
Max
Units
ns
T
Global early clock to output using OFF
Values are for BUFGEs 1, 2, 5, and 6.
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.3
1.2
1.2
1.3
-
-
ICKEOF
ns
-
ns
8.5
ns
Notes:
1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
2. Output timing is measured at ~50% V threshold with 50 pF external capacitive load.
CC
DS029 (v1.3) June 25, 2000
www.xilinx.com
11
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Output Flip-Flop, Clock to Out, BUFGEs 3, 4, 7, and 8
-3
Max
8.8
9.7
10.9
-
-1
All
Min
Symbol
Description
Device
Max
Units
ns
T
Global early clock to output using OFF
Values are for BUFGEs 3, 4, 7, and 8.
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.8
1.8
2.0
2.2
-
-
ICKEOF
ns
-
ns
9.3
ns
Notes:
1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
2. Output timing is measured at ~50% V threshold with 50 pF external capacitive load.
CC
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
3
2
and load capacitance. It allows a user to adjust the specified
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2.5 ns to the specified delay. If the load capacitance is
20 pF, subtract 0.8 ns from the specified output delay.
1
Figure 1 is usable over the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
0
-1
-2
0
20
40
60
80
100
120
140
Capacitance (pF)
DS029_03_011300
Figure 1: Delay Factor at Various Capacitive Loads
12
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Global Low Skew Clock, Input Setup and Hold Times(1,2)
-3
-1
(1)
Symbol
No Delay
/T
Description
Device
Min
Min
Units
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 3.2
1.2 / 5.5
1.2 / 7.0
-
-
ns
ns
ns
ns
PSN PHN
(4)
Global early clock and FCL
-
-
0.9 / 7.1
Partial Delay
/T
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.1 / 0.0
6.4 / 1.0
6.7 / 1.2
-
-
ns
ns
ns
ns
PSP PHP
(4)
Global early clock and FCL
-
-
9.8 / 1.2
Full Delay
/T
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.4 / 0.0
6.6 / 0.0
6.8 / 0.0
-
-
ns
ns
ns
ns
PSD PHD
-
-
9.6 / 0.0
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
DS029 (v1.3) June 25, 2000
www.xilinx.com
13
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL(1,2)
-3
-1
Symbol
No Delay
Description
Device
Min
Min
(3)
T
/T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
-
-
PSEN PHEN
(4)
T
/T
Global early clock and FCL
-
PFSEN PFHEN
-
0.9 / 6.6
Partial Delay
(3)
T
/T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.4 / 0.0
7.0 / 0.8
9.0 / 0.8
-
-
PSEPN PHEP
(4)
T
/T
Global early clock and FCL
-
PFSEP PFHEP
-
11.0 / 0.0
Full Delay
/T
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
12.0 / 0.0
13.8 / 0.0
13.1 / 0.0
-
-
PSEPD PHED
-
-
13.6 / 0.0
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
14
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Global Early Clock BUFEs 3, 4, 7, and 8 Setup and Hold for IFF and FCL(1,2)
-3
-1
Symbol
No Delay
Description
Device
Min
Min
(3)
T
/T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
-
-
PSEN PHEN
(4)
T
/T
Global early clock and FCL
-
PFSEN PFHEN
-
0.9 / 6.6
Partial Delay
(3)
T
/T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
5.4 / 0.0
6.4 / 0.8
8.4 / 1.5
-
-
PSEPN PHEP
(4)
T
/T
Global early clock and FCL
-
PFSEP PFHEP
-
11.0 / 0.0
Full Delay
/T
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
10.0 / 0.0
12.2 / 0.0
13.1 / 0.0
-
-
PSEPD PHED
-
-
13.6 / 0.0
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
DS029 (v1.3) June 25, 2000
www.xilinx.com
15
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature).
-3
-1
Symbol
Clocks
Description
Device
Min
Max
Min
Max
Units
T
T
Clock enable (EC) to clock (IK)
All devices
All devices
0.1
2.2
-
-
0.1
1.6
-
-
ns
ns
ECIK
OKIK
Delay from FCL enable (OK) active edge to IFF
clock (IK) active edge
Setup Times
Pad to clock (IK), no delay
T
All devices
1.7
2.3
-
-
1.3
1.8
-
-
ns
ns
PICK
T
Pad to clock (IK), via transparent fast capture latch, All devices
no delay
PICKF
T
Pad to fast capture latch enable (OK), no delay
Hold Times
All Hold Times
Global Set/Reset
All devices
1.2
0
-
-
0.9
0
-
-
ns
ns
POCK
All devices
T
Minimum GSR pulse width
All devices
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
-
-
-
-
-
19.8
15.9
22.5
29.1
-
-
-
-
-
-
15.0
ns
ns
ns
ns
ns
MRW
(2)
T
Delay from GSR input to any Q
-
RRI
-
-
26.0
Propagation Delays
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
T
All devices
All devices
-
-
-
1.6
3.1
3.7
-
-
-
1.7
2.4
2.8
ns
ns
ns
PID
T
PLI
T
Pad to I1, I2 via transparent FCL and input latch, no All devices
delay
PFLI
T
Clock (IK) to I1, I2 (flip-flop)
All devices
All devices
All devices
-
-
-
1.7
1.8
3.6
-
-
-
1.3
1.4
2.7
ns
ns
ns
IKRI
T
Clock (IK) to I1, I2 (latch enable, active Low)
IKLI
T
FCL enable (OK) active edge to I1, I2
(via transparent standard input latch)
OKLI
Notes:
1. IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
2. Indicates Minimum Amount of Time to Assure Valid Data.
16
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values are
expressed in nanoseconds unless otherwise noted.
-3
-1
Symbol
Clocks
Description
Min
Max
Min
Max
Units
T
Clock High
Clock Low
3.0
3.0
-
-
2.5
2.5
-
-
ns
ns
CH
T
CL
Propagation Delays
T
Clock (OK) to pad
Output (O) to pad
-
-
-
-
-
-
5.0
4.1
4.4
4.1
5.5
5.1
-
-
-
-
-
-
3.8
3.1
3.0
3.3
4.2
3.9
ns
ns
ns
ns
ns
ns
OKPOF
T
OPF
T
High-Z to pad High-Z (slew-rate independent)
High-Z to pad active and valid
TSHZ
T
TSONF
T
Output (O) to pad via fast output MUX
Select (OK) to pad via fast MUX
OFPF
T
OKFPF
Setup and Hold Times
T
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
0.5
0
-
-
-
-
0.3
0
-
-
-
-
ns
ns
ns
ns
OOK
T
OKO
T
T
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
0
0
ECOK
OKEC
0.3
0.1
Global Set/Reset
T
Minimum GSR pulse width
Delay from GSR input to any pad
XQ4013XL
19.8
-
15.0
-
ns
MRW
(2)
T
RPO
-
-
-
-
20.5
27.1
33.7
-
-
-
-
-
ns
ns
ns
ns
XQ4036XL
-
-
XQ4062XL
XQ4085XL
29.5
Slew Rate Adjustment
For output SLOW option add
T
-
3.0
-
2.0
ns
SLOW
Notes:
1. Output timing is measured at ~50% V threshold, with 50 pF external capacitive loads.
CC
2. Indicates Minimum Amount of Time to Assure Valid Data.
DS029 (v1.3) June 25, 2000
www.xilinx.com
17
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228
CB228 Pinouts
Table 2: CB228 Package Pinouts
IO
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
Pin Name
CB228
IO
VTT
IO_FCLK2
GND
P1
P2
GND
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BUFGP_TL_A16_GCK1_IO
A17_IO
P3
IO
P4
IO
P5
TDI_IO
P6
TCK_IO
P7
IO
P8
IO
P9
IO
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
IO
IO
IO
BUFGS_BL_GCK2_IO
GND
M1
IO_FCLK1
GND
M0
IO
TMS_IO
IO
V
CC
M2
IO
BUFGP_BL_GCK3_IO
IO
HDC_IO
IO
IO
IO
IO
IO
IO
IO
LDC_IO
IO
IO
IO
IO
GND
IO
V
CC
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
V
CC
IO
IO
18
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Table 2: CB228 Package Pinouts (Continued)
Table 2: CB228 Package Pinouts (Continued)
Pin Name
CB228
Pin Name
CB228
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
IO
IO
IO
IO
IO
P79
P80
IO
IO
P81
IO
P82
IO
P83
D6_IO
IO
/ERR_INIT_IO
P84
V
P85
IO
CC
GND
IO
P86
IO
P87
IO
IO
P88
IO
IO
P89
GND
IO
IO
P90
IO
P91
IO
IO
P92
IO_FCLK3
IO
IO
P93
IO
P94
D5_IO
/CS0_IO
IO
V
P95
CC
IO
P96
IO
P97
IO
IO
P98
IO
IO
P99
IO
GND
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
D4_IO
IO
IO
IO
V
CC
IO
GND
D3_IO
/RS_IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D2_IO
IO
IO
BUFGS_BR_GCK4_IO
V
CC
GND
IO
DONE
IO_FCLK4
V
IO
CC
/PROGRAM
IO
D7_IO
GND
IO
BUFGP_BR_GCK5_IO
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
19
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Table 2: CB228 Package Pinouts (Continued)
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228
Pin Name
CB228
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
IO
A7_IO
GND
P199
P200
P201
P202
P203
P204
P205
P206
P207
P208
P209
P210
P211
P212
P213
P214
P215
P216
P217
P218
P219
P220
P221
P222
P223
P224
P225
P226
P227
P228
IO
IO
V
CC
IO
A8_IO
A9_IO
A19_IO
A18_IO
IO
IO
D1_IO
BUSY_/RDY_RCLK_IO
IO
IO
IO
D0_DIN_IO
A10_IO
A11_IO
BUFGS_TR_GCK6_DOUT_IO
CCLK
V
CC
V
IO
CC
TDO
IO
GND
IO
A0_/WS_IO
IO
BUFGP_TR_GCK7_A1_IO
GND
IO
IO
IO
IO
CSI_A2_IO
IO
A3_IO
IO
IO
A12_IO
A13_IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
IO
A14_IO
BUFGS_TL_GCK8_A15_IO
IO
V
CC
IO
IO
V
CC
A4_IO
A5_IO
IO
IO
A21_IO
A20_IO
A6_IO
20
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Ordering Information
Example for QPRO™ military temperature part:
XQ 4062XL -3 PG 475 M
Mil-PRF-38535
(QML) Processed
Temperature Range
o
o
M = Military Ceramic (T = –55 C to +125 C)
C
N = Military Plastic (T = –55°C to +125°C)
J
Device Type
XQ4085XL
XQ4062XL
XQ4036XL
XQ4013XL
Number of Pins
Speed Grade
Package Type
CB = Top Brazed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
PQ/HQ = Plastic Quad Flat Back
BG = Plastic Ball Grid Array
-3
-1 (XQ4085XL only)
Example for SMD part:
5962 98511 01 Q X C
Generic Standard
Microcircuit Drawing (SMD)
Prefix
Lead Finish
C = Gold
B = Solder
Device Type
XQ4013XL = 98513
XQ4036XL = 98510
XQ4062XL = 98511
XQ4085XL = 99575
Package Type
X = Pin Grid
Y = Ceramic Quad Flat Pack (Base Mark)
Z = Ceramic Quad Flat Pack (Lid Mark)
T = Plastic Quad Flat Pack
U = Plastic Ball Grid
Speed Grade
01 = -3 for XQ4103XL/4036XL/4062XL
01 = -1 for XQ4085XL
Q = QML Certified
N = QML Plastic (N - Grade)
Revision History
The following table shows the revision history for this document
Date
Version
1.0
Description
05/01/98
01/01/99
02/09/00
06/25/00
Original document release.
1.1
Addition of new packages, clarification of parameters.
1.2
Addition of XQ4085XL-1 speed grade part.
1.3
Updated timing specifications to match with commercial data sheet. Updated format.
DS029 (v1.3) June 25, 2000
www.xilinx.com
21
Product Specification
1-800-255-7778
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
22
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
相关型号：
XQ4036XL-1CB432N
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1CB475M
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1CB475N
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1HQ228M
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1HQ228N
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1HQ240M
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1HQ240N
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1HQ432M
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1HQ432N
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1HQ475M
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1HQ475N
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XQ4036XL-1PG228M
QML High-Reliability FPGAsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
©2020 ICPDF网 联系我们和版权申明