XQC1000-4PQ240M_技术文档

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QPro Virtex 2.5V QML

High-Reliability FPGAs

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2

DS002 (v1.5) December 5, 2001

Preliminary Product Specification

•

0.22 µm 5-layer metal process

100% factory tested

Features

•

Certified to MIL-PRF-38535 (Qualified Manufacturer

Listing)

Available to Standard Microcircuit Drawings

-

5962-99572 for XQV300

5962-99573 for XQV600

5962-99574 for XQV1000

•

Guaranteed over the full military temperature range

(–55°C to +125°C)

•

Ceramic and Plastic Packages

Fast, high-density Field-Programmable Gate Arrays

Contact Defense Supply Center Columbus (DSCC)

for more information at http://www.dscc.dla.mil

-

Densities from 100K to 1M system gates

System performance up to 200 MHz

Hot-swappable for Compact PCI

Description

The QPro™ Virtex™ FPGA family delivers high-perfor-

mance, high-capacity programmable logic solutions. Dra-

matic increases in silicon efficiency result from optimizing

the new architecture for place-and-route efficiency and

exploiting an aggressive 5-layer-metal 0.22 µm CMOS pro-

cess. These advances make QPro Virtex FPGAs powerful

and flexible alternatives to mask-programmed gate arrays.

The Virtex family comprises the four members shown in

Table 1.

•

Multi-standard SelectI/O™ interfaces

-

16 high-performance interface standards

Connects directly to ZBTRAM devices

Built-in clock-management circuitry

-

Four dedicated delay-locked loops (DLLs) for

advanced clock control

-

Four primary low-skew global clock distribution

nets, plus 24 secondary global nets

Building on experience gained from previous generations of

FPGAs, the Virtex family represents a revolutionary step

forward in programmable logic design. Combining a wide

variety of programmable system features, a rich hierarchy of

fast, flexible interconnect resources, and advanced process

technology, the QPro Virtex family delivers a high-speed

and high-capacity programmable logic solution that

enhances design flexibility while reducing time-to-market.

•

Hierarchical memory system

-

LUTs configurable as 16-bit RAM, 32-bit RAM,

16-bit dual-ported RAM, or 16-bit Shift Register

Configurable synchronous dual-ported 4K-bit

RAMs

Fast interfaces to external high-performance RAMs

Flexible architecture that balances speed and density

Refer to the “Virtex™ 2.5V Field Programmable Gate

Arrays” commercial data sheet for more information on

device architecture and timing specifications.

-

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

-

Internal 3-state bussing

IEEE 1149.1 boundary-scan logic

Die-temperature sensing device

•

Supported by FPGA Foundation™ and Alliance

Development Systems

-

Complete support for Unified Libraries, Relationally

Placed Macros, and Design Manager

-

Wide selection of PC and workstation platforms

SRAM-based in-system configuration

-

Unlimited reprogrammability

Four programming modes

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

Table 1: QPro Virtex Field-Programmable Gate Array Family Members

Maximum

Available I/O

Max Select

RAM Bits

Device

XQV100

XQV300

XQV600

XQV1000

System Gates CLB Array

Logic Cells

2,700

Block RAM Bits

40,960

108,904

322,970

661,111

1,124,022

20 x 30

32 x 48

48 x 72

64 x 96

180

316

404

38,400

98,304

6,912

65,536

15,552

27,648

98,304

221,184

393,216

131,072

Virtex Electrical Characteristics

Based on preliminary characterization. Further changes are not expected.

All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters

included are common to popular designs and typical applications. Contact the factory for design considerations requiring

more detailed information.

Virtex DC Characteristics

Absolute Maximum Ratings

Symbol

V_CCINT

V_CCO

Description

Min/Max

–0.5 to 3.0

–0.5 to 4.0

–0.5 to 3.6

–0.5 to 5.5

50

Units

V

Supply voltage relative to GND

Input reference Voltage

V

V_REF

V

(3)

V_IN

Input voltage relative to GND

Using V_REF

V

Internal threshold

V

V_TS

V_CC

T_STG

T_J

Voltage applied to 3-state output

V

Longest supply voltage rise time from 1V to 2.375V

Storage temperature (ambient)

ms

°C

–65 to +150

+150

Junction temperature

Ceramic packages

Plastic packages

+125

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

2. Power supplies may turn on in any order.

3. For protracted periods (e.g., longer than a day), V_INshould not exceed V_CCOby more that 3.6V.

2

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DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

Recommended Operating Conditions

Symbol

Description

Min

Max

Units

V

V_CCINTSupply voltage relative to GND, T_C= –55°C to +125°C Ceramic packages

Supply voltage relative to GND, T_J= –55°C to +125°C Plastic packages

2.5 – 5% 2.5 + 5%

V

V_CCO

Supply voltage relative to GND, T_C= –55°C to +125°C Ceramic packages

Supply voltage relative to GND, T_J= –55°C to +125°C Plastic packages

Input signal transition time

1.2

-

3.6

V

3.6

V

T_IN

T_IC

250

ns

°C

Initialization Temperature Range⁽⁴⁾

XQVR300

XQVR600

XQVR1000

XQVR300

XQVR600

XQVR1000

–55

–40

–55

+125

T_OC

Operational Temperature Range⁽⁵⁾

Notes:

1. Correct operation is guaranteed with a minimum V_CCINTof 2.25V (Nominal V_CCINT– 10%). Below the minimum value stated above,

all delay parameters increase by 3% for each 50 mV reduction in V_CCINTbelow the specified range.

2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.

3. Input and output measurement threshold is ~50% of V_CC

.

4. Initialization occurs from the moment of V_CCramp-up to the rising transition of the INIT pin.

5. The device is operational after the INIT pin has transitioned high.

DC Characteristics Over Recommended Operating Conditions

Symbol

V_DRINTData retention V_CCINTvoltage

(below which configuration data may be lost)

Data retention V_CCOvoltage

(below which configuration data may be lost)

I_CCINTQQuiescent V_CCINTsupply current⁽¹⁾

Description

Device

Min

Max

Units

All

2.0

-

V

V_DRIO

All

1.2

-

V

XQV100

-

50

75

100

2

mA

µA

XQV300

-

XQV600

-

XQV1000

-

I_CCOQ

Quiescent V_CCINTsupply current⁽¹⁾

XQV100

-

XQV300

-

2

XQV600

-

2

XQV1000

-

2

I_REF

I_L

V_REFcurrent per V_REFpin

-

20

+10

8

Input or output leakage current

–10

µA

C_IN

I_RPU

I_RPD

Input capacitance (sample tested)

-

pF

(2)

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 3.3V (sample tested)

Pad pull-down (when selected) at V_IN= 3.6V (sample tested)

0.25

0.15

mA

(2)

Notes:

1. With no output current loads, no active input pull-up resistors, all I/O pins in a High-Z state and floating.

2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors

do not guarantee valid logic levels when input pins are connected to other circuits.

DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

DC Input and Output Levels

Values for V_ILand V_IHare recommended input voltages.

Values for I_OLand I_OHare guaranteed output currents over

the recommended operating conditions at the V_OLand V_OH

test points. Only selected standards are tested. These are

chosen to ensure that all standards meet their specifica-

tions. The selected standards are tested at minimum V_CCO

with the respective V_OLand V_OHvoltage levels shown.

Other standards are sample tested.

V_IL

V, max

V_IH

V_OL

V, max

0.4

V_OH

V, min

I_OL

mA

24

I_OH

mA

–24

Input/Output

Standard

V, min

–0.5

V, min

2.0

V, max

5.5

LVTTL⁽¹⁾

LVCMOS2

PCI, 3.3V

PCI, 5.0V

GTL

0.8

0.7

2.4

1.7

5.5

0.4

1.9

12

–12

(2)

44% V_CCINT60% V_CCINTV_CCO+ 0.5 10% V_CCO

90% V_CCO

2.4

(2)

0.8

2.0

5.5

3.6

0.55

0.4

V_REF– 0.05 V_REF+ 0.05

n/a

40

36

8

n/a

-8

GTL+

V

_REF– 0.1

_REF– 0.2

V_REF+ 0.1

V_REF+ 0.2

0.6

n/a

HSTL I

HSTL III

HSTL IV

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

CTT

0.4

V_CCO– 0.4

V_REF+ 0.6

V_REF+ 0.8

0.4

24

48

8

–8

0.4

–8

V_REF– 0.6

V_REF– 0.8

–8

16

7.6

15.2

–16

–7.6

–15.2

V_REF– 0.65 V_REF+ 0.65

V_REF– 0.80 V_REF+ 0.80

V_REF– 0.4

V_REF+ 0.4

90% V_CCO

8

–8

(2)

AGP

10% V_CCO

Notes:

1.

V_OLand V_OHfor lower drive currents are sample tested.

2. Tested according to the relevant specifications.

4

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DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

Virtex Switching Characteristics

Testing of switching parameters is modeled after testing

methods specified by MIL-M-38510/605. All devices are

100% functionally tested. Internal timing parameters are

derived from measuring internal test patterns. Listed below

are representative values. For more specific, more precise,

and worst-case guaranteed data, use the values reported

by the static timing analyzer (TRCE in the Xilinx Develop-

ment System) and back-annotated to the simulation netlist.

All timing parameters assume worst-case operating condi-

tions (supply voltage and junction temperature). Values

apply to all Virtex devices unless otherwise noted.

IOB Input Switching Characteristics

Input delays associated with the pad are specified for

LVTTL levels. For other standards, adjust the delays with

the values shown in "IOB Input Switching Characteristics

Standard Adjustments" on page 6.

Speed Grade

-4

Symbol

Propagation Delays

T_IOPI

Description

Device

Min

Max

Units

Pad to I output, no delay

All

-

1.0

1.9

2.3

2.7

2.0

ns

T_IOPID

Pad to I output, with delay

XQV100

XQV300

XQV600

XQV1000

All

T_IOPLI

Pad to output IQ via transparent latch, no

delay

T_IOPLID

Pad to output IQ via transparent latch, with

delay

XQV100

XQV300

XQV600

XQV1000

-

4.8

5.1

5.5

5.9

ns

Sequential Delays

T_IOCKIQ

Clock CLK to output IQ

All

-

0.8

ns

Setup and Hold Times with Respect to Clock CLK

Setup Time / Hold Time

T_IOPICK/ T_IOICKP

Pad, no delay

All

2.0 / 0

5.0 / 0

1.0 / 0

1.3 / 0

-

ns

T

_IOPICKD/ T_IOICKPD

_IOICECK/ T_IOCKICE

_IOSRCKI/ T_IOCKISR

Pad, with delay

ICE input

T

SR input (IFF, synchronous)

Set/Reset Delays

T_IOSRIQ

SR input to IQ (asynchronous)

GSR to output IQ

All

-

1.8

ns

T_GSRQ

12.5

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”,

but if a “0” is listed, there is no positive hold time.

DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

IOB Input Switching Characteristics Standard Adjustments

Speed Grade

-4

Symbol

Description

Standard

Units

Data Input Delay Adjustments

T_ILVTTL

T_ILVCMOS2

T_{IPCI33_3}

T_{IPCI33_5}

T_IGTL

Standard-specific data input delay adjustments

LVTTL

LVCMOS2

PCI, 33 MHz, 3.3V

PCI, 33 MHz, 5.0V

GTL

0.0

ns

–0.05

–0.14

0.33

0.26

T_IGTLP

GTL+

0.14

T_IHSTL

HSTL

0.04

T_ISSTL2

T_ISSTL3

T_ICTT

SSTL2

–0.10

–0.06

0.02

SSTL3

CTT

T_IAGP

AGP

–0.08

6

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DS002 (v1.5) December 5, 2001

Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

IOB Output Switching Characteristics

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays with the values shown in "IOB Output Switching Characteristics Standard Adjustments" on page 8.

Speed Grade

-4

Symbol

Propagation Delays

T_IOOP

Description

Min

Max

Units

O input to pad

-

3.5

4.0

ns

T_IOOLP

O input to pad via transparent latch

3-State Delays

T_IOTHZ

T input to pad high-impedance⁽¹⁾

-

2.4

3.7

3.0

4.2

6.3

ns

T_IOTON

T input to valid data on pad

T_IOTLPHZ

T input to pad high-impedance via transparent latch⁽¹⁾

T input to valid data on pad via transparent latch

GTS to pad high-impedance⁽¹⁾

T_IOTLPON

T_GTS

Sequential Delays

T_IOCKP

Clock CLK to pad

-

3.5

2.9

4.1

ns

T_IOCKHZ

Clock CLK to pad high-impedance (synchronous)⁽¹⁾

Clock CLK to valid data on pad (synchronous)

T_IOCKON

ns

(2)

Setup and Hold Times before/after Clock CLK

T_IOOCK/T_IOCKOO input

Setup Time / Hold Time

1.3 / 0

1.0 / 0

1.4 / 0

0.9 / 0

1.1 / 0

1.3 / 0

-

ns

T

_IOOCECK/T_IOCKOCEOCE input

T

_IOSRCKO/T_IOCKOSRSR input (OFF)

T

_IOTCK/T_IOCKT

_IOTCECK/T_IOCKTCE

_IOSRCKT/T_IOCKTSR

3-state setup times, T input

T

3-state setup times, TCE input

3-state setup times, SR input (TFF)

Set/Reset Delays

T_IOSRP

SR input to pad (asynchronous)

4.6

3.9

5.1

-

ns

T_IOSRHZ

SR input to pad high-impedance (asynchronous)⁽¹⁾

SR input to valid data on pad (asynchronous)

T_IOSRON

Notes:

1. High-impedance turn-off delays should not be adjusted.

2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

IOB Output Switching Characteristics Standard Adjustments

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays by the values shown.

Speed Grade

Symbol

Description

Standard

-4

Units

Output Delay Adjustments

T_{OLVTTL_S2}Standard-specific adjustments for output delays

LVTTL, slow

2 mA

4 mA

17.0

8.6

ns

terminating at pads (based on standard capacitive

load, C_sl)

T_{OLVTTL_S4}

T_{OLVTTL_S6}

T_{OLVTTL_S8}

T_{OLVTTL_S12}

T_{OLVTTL_S16}

T_{OLVTTL_S24}

T_{OLVTTL_F2}

T_{OLVTTL_F4}

T_{OLVTTL_F6}

T_{OLVTTL_F8}

T_{OLVTTL_F12}

T_{OLVTTL_F16}

T_{OLVTTL_F24}

T_OLVCMOS2

T_{OPCI33_3}

T_{OPCI33_5}

T_OGTL

6 mA

5.6

8 mA

3.5

12 mA

16 mA

24 mA

2 mA

2.2

2.0

1.6

LVTTL, fast

15.1

6.1

4 mA

6 mA

3.6

8 mA

1.2

12 mA

16 mA

24 mA

0.0

–0.05

–0.23

0.12

2.7

LVCMOS2

PCI, 33 MHz, 3.3V

PCI, 33 MHz, 5.0V

GTL

3.3

0.6

T_OGTLP

GTL+

1.0

T_{OHSTL_I}

HSTL I

–0.5

–1.0

–1.1

–0.5

–1.0

–0.5

–1.1

–0.6

–1.0

T_{OHSTL_III}

T_{OHSTL_IV}

T_{OSSTL2_I}

T_{OSSTL2_II}

T_{OSSTL3_I}

T_{OSSTL3_II}

T_OCTT

HSTL III

HSTL IV

SSTL2 I

SSTL2 II

SSTL3 I

SSTL3 II

CTT

T_OAGP

AGP

8

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

Calculation of T

as a Function of Capacitance

ioop

The values for T_ioopwere based on the standard capacitive

load (Csl) for each I/O standard as listed in Table 2.

Table 2: Constants for Use in Calculation of T_op

Standard

LVCMOS2

C_sl(pF)

35

50

10

0

fl (ns/pF)

0.041

0.050

0.014

0.017

0.022

0.016

0.014

0.028

0.016

0.029

0.016

0.035

0.037

For other capacitive loads, use the formulas below to calcu-

late the corresponding T_ioop

:

PCI 33 MHz 5V

PCI 33 MHZ 3.3V

GTL

T_ioop= T_ioopl+ T_opadjust+ (C_load- C_sl) * fl

Where:

_opadjustis reported above in the Output Delay

Adjustment section.

_loadis the capacitive load for the design.

Table 2: Constants for Use in Calculation of T_op

T

GTL+

0

HSTL Class I

HSTL Class III

HSTL Class IV

SSTL2 Class I

SSTL2 Class II

SSTL3 Class 1

SSTL3 Class II

CTT

20

30

20

10

C

Standard

C_sl(pF)

35

fl (ns/pF)

0.41

LVTTL slow 2 mA drive

slew rate

4 mA drive

35

0.20

6 mA drive

8 mA drive

12 mA drive

16 mA drive

24 mA drive

35

0.100

0.086

0.058

0.050

0.048

0.41

35

AGP

35

LVTTL fast

slew rate

2 mA drive

4 mA drive

6 mA drive

8 mA drive

12 mA drive

16 mA drive

24 mA drive

35

0.20

35

0.13

35

0.079

0.044

0.043

0.033

35

Clock Distribution Guidelines and Switching Characteristics

Speed Grade

-4

Symbol

Description

Device

Min

Max

Units

Global Clock Skew

T_GSKEWIOB

Global clock skew between IOB flip-flops

XQV100

XQV300

XQV600

XQV1000

All

-

0.15

0.18

0.17

0.25

0.9

ns

T_GPIO

T_GIO

Notes:

Global clock PAD to output

Global clock buffer I input to O output

All

0.9

1. These clock-distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under

worst-case conditions. Precise values for a particular design are provided by the timing analyzer.

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CLB Switching Characteristics

Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise

values are provided by the timing analyzer.

Speed Grade

-4

Symbol

Description

Min

Max

Units

Combinatorial Delays

T_ILO

T_IF5

4-input function: F/G inputs to X/Y outputs

5-input function: F/G inputs to F5 output

5-input function: F/G inputs to X output

-

0.8

0.9

1.0

1.2

0.5

0.8

0.7

ns

T_IF5X

T_IF6Y

6-input function: F/G inputs to Y output via F6 MUX

6-input function: F5IN input to Y output

T_F5INY

T_IFNCTL

T_BYYB

Incremental delay routing through transparent latch to XQ/YQ outputs

BY input to YB output

Sequential Delays

T_CKO

FF clock CLK to XQ/YQ outputs

Latch clock CLK to XQ/YQ outputs

-

1.4

1.6

ns

T_CKLO

Setup and Hold Times before/after Clock CLK

Setup Time / Hold Time

T_ICK/T_CKI

4-input function: F/G Inputs

5-input function: F/G inputs

6-input function: F5IN input

6-input function: F/G inputs via F6 MUX

BX/BY inputs

1.5 / 0

1.7 / 0

1.2 / 0

1.9 / 0

0.8 / 0

1.0 / 0

0.9 / 0

-

ns

T

_IF5CK/T_CKIF5

T

_F5INCK/T_CKF5IN

_IF6CK/T_CKIF6

T

_DICK/T_CKDI

T

_CECK/T_CKCE

CE input

T

_RCKT_CKR

SR/BY inputs (synchronous)

Clock CLK

T_CH

Minimum pulse width, High

Minimum pulse width, Low

2.0

-

ns

T_CL

Set/Reset

T_RPW

Minimum pulse width, SR/BY inputs

3.3

-

ns

T_RQ

Delay from SR/BY inputs to XQ/YQ outputs (asynchronous)

Delay from GSR to XQ/YQ outputs

-

1.4

12.5

T_IOGSRQ

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

10

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DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

CLB Arithmetic Switching Characteristics

Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment

listed. Precise values are provided by the timing analyzer.

Speed Grade

-4

Symbol

Description

Min

Max

Units

Combinatorial Delays

T_OPX

T_OPXB

F operand inputs to X via XOR

F operand input to XB output

-

1.0

1.4

2.0

1.5

1.2

2.1

1.6

1.1

0.6

0.1

0.6

0.2

ns

T_OPY

F operand input to Y via XOR

F operand input to YB output

F operand input to COUT output

G operand inputs to Y via XOR

G operand input to YB output

G operand input to COUT output

BX initialization input to COUT

CIN input to X output via XOR

CIN input to XB

T_OPYB

T_OPCYF

T_OPGY

T_OPGYB

T_OPCYG

T_BXCY

T_CINX

T_CINXB

T_CINY

CIN input to Y via XOR

T_CINYB

CIN input to YB

T_BYP

CIN input to COUT output

Multiplier Operation

T_FANDXB

T_FANDYB

T_FANDCY

T_GANDYB

T_GANDCY

F1/2 operand inputs to XB output via AND

F1/2 operand inputs to YB output via AND

F1/2 operand inputs to COUT output via AND

G1/2 operand inputs to YB output via AND

G1/2 operand inputs to COUT output via AND

-

0.5

1.1

0.6

0.7

0.2

ns

Setup and Hold Times before/after Clock CLK

Setup Time / Hold Time

T_CCKX/T_CKCX

_CCKY/T_CKCY

Notes:

CIN input to FFX

CIN input to FFY

1.3 / 0

1.4 / 0

-

ns

T

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if

a “0” is listed, there is no positive hold time.

DS002 (v1.5) December 5, 2001

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11

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QPro Virtex 2.5V QML High-Reliability FPGAs

CLB SelectRAM Switching Characteristics

Speed Grade

-4

Symbol

Sequential Delays

T_SHCKO

Description

Min

Max

Units

ns

Clock CLK to X/Y outputs (WE active)

Clock CLK to X/Y outputs

-

3.0

Shift-Register Mode

T_SHCKO

3.0

ns

Setup Times before Clock CLK

Setup Time / Hold Time

T_AS/T_AH

T_DS/T_DH

F/G address inputs

0.7 / 0

0.9 / 0

1.0 / 0

-

ns

BX/BY data inputs (DIN)

CE input (WE)

T

_WS/T_WH

Shift-Register Mode

T_SHDICK

BX/BY data inputs (DIN)

CE input (WS)

0.9

1.0

-

ns

T_SHCECK

Clock CLK

T_WPH

Minimum pulse width, High

3.1

6.2

-

ns

T_WPL

Minimum pulse width, Low

T_WC

Minimum clock period to meet address write cycle time

Shift-Register Mode

T_SRPH

Minimum pulse width, High

Minimum pulse width, Low

3.1

-

ns

T_SRPL

BLOCKRAM Switching Characteristics

Speed Grade

-4

Symbol

Description

Min

Max

Units

Sequential Delays

T_BCKO

Clock CLK to DOUT output

-

4.1

ns

Setup Times Before Clock Clk

T_BACK/T_BCKA

_BDCK/T_BCKD

T_BECK/T_BCKE

_BRCK/T_BCKR

_BWCK/T_BCKW

ADDR inputs

DIN inputs

EN input

1.5 / 0

3.4 / 0

3.2 / 0

3.0 / 0

-

ns

T

RST input

WEN input

T

Clock CLK

T_BPWH

Minimum pulse width, High

Minimum pulse width, Low

2.0

4.0

-

ns

T_BPWL

T_BCCS

CLKA -> CLKB setup time for different ports

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

12

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Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

TBUF Switching Characteristics

Speed Grade

-4

Symbol

Description

Min

Max

Units

Combinatorial Delays

T_IO

T_OFF

T_ON

IN input to OUT output

-

0.0

0.2

ns

TRI input to OUT output high-impedance

Tri input to valid data on OUT output

JTAG Test Access Port Switching Characteristics

Speed Grade

-4

Symbol

T_TAPTCK

T_TCKTAP

T_TCKTDO

F_TCK

Description

TMS and TDI setup times before TCK

Min

4.0

2.0

-

Max

-

Units

ns

TMS and TDI hold times after TCK

Output delay from clock TCK to output TDO

Maximum TCK clock frequency

-

ns

11.0

33

ns

-

MHz

Virtex Pin-to-Pin Output Parameter Guidelines

Testing of switching parameters is modeled after testing

methods specified by MIL-M-38510/605. All devices are

100% functionally tested. Listed below are representative

values for typical pin locations and normal clock loading.

Values are expressed in nanoseconds unless otherwise

noted.

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL

Speed Grade

-4

Symbol

Description

Device

XQV100

XQV300

XQV600

XQV1000

Min

Max

3.6

Units

ns

LVTTL Global Clock Input to Output Delay using Output Flip-flop,

12 mA, Fast Slew Rate, with DLL. For data output with different

standards, adjust the delays with the values shown in "IOB Output

Switching Characteristics Standard Adjustments" on page 8.

-

ns

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and

where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2. Output timing is measured at 50% V_CCthreshold with 35 pF external capacitive load. For different loads, see Table 2.

3. DLL output jitter is already included in the timing calculation.

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL

Speed Grade

-4

Symbol

Description

Device

XQV100

XQV300

XQV600

XQV1000

Min

Max

5.7

5.9

6.0

6.3

Units

ns

LVTTL Global Clock Input to Output Delay using Output Flip-flop,

12 mA, Fast Slew Rate, without DLL. For data output with different

standards, adjust the delays with the values shown in "IOB Output

Switching Characteristics Standard Adjustments" on page 8.

-

ns

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and

where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2. Output timing is measured at 50% V_CCthreshold with 35 pF external capacitive load. For different loads, see Table 2.

DS002 (v1.5) December 5, 2001

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13

Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

Minimum Clock to Out for Virtex Devices

With DLL

Without DLL

V600

6.1

I/O Standard

LVTTL_S2⁽¹⁾

All Devices

5.2

3.5

2.8

2.2

2.0

1.9

1.8

2.9

1.7

1.2

1.1

1.0

0.9

1.1

1.5

1.4

1.6

1.7

1.1

0.9

0.8

0.9

0.8

0.7

1.0

V100

6.0

4.3

3.6

3.1

2.9

2.8

2.6

3.8

2.6

2.0

1.9

1.8

1.7

1.9

2.4

2.2

2.5

1.9

1.7

1.6

1.7

1.6

1.7

1.5

1.8

V300

6.1

4.4

3.7

3.1

2.9

2.8

2.7

3.8

2.6

2.1

2.0

1.9

1.8

2.0

2.4

2.3

2.5

2.6

2.0

1.8

1.7

1.8

1.7

1.6

1.9

V1000

6.1

4.4

3.7

3.2

3.0

2.9

2.8

3.9

2.7

2.2

2.0

1.9

2.1

2.5

2.4

2.6

2.7

2.0

1.9

1.8

1.7

1.8

1.7

2.0

Units

ns

LVTTL_S4⁽¹⁾

LVTTL_S6⁽¹⁾

LVTTL_S8⁽¹⁾

LVTTL_S12⁽¹⁾

LVTTL_S16⁽¹⁾

LVTTL_S24⁽¹⁾

LVTTL_F2⁽¹⁾

LVTTL_F4⁽¹⁾

LVTTL_F6⁽¹⁾

LVTTL_F8⁽¹⁾

LVTTL_F12⁽¹⁾

LVTTL_F16⁽¹⁾

LVTTL_F24⁽¹⁾

LVCMOS2

PCI33_3

4.4

3.7

3.2

3.0

2.9

2.7

3.9

2.7

2.1

2.0

1.9

1.8

2.0

2.5

PCI33_5

2.3

GTL

2.6

GTL+

2.6

HSTL I

2.0

HSTL III

1.8

HSTL IV

1.7

SSTL2 I

1.8

SSTL2 II

1.7

SSTL3 I

1.7

SSTL3 II

1.6

CTT

1.9

AGP

1.9

Notes:

1. S = Slow Slew Rate, F = Fast Slew Rate

2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column. and

where all accessible IOB and CLB flip-flops are clocked by the global clock net.

3. Output timing is measured at 50% V_CCthreshold with 8 pF external capacitive load.

14

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DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Virtex Pin-to-Pin Input Parameter Guidelines

Testing of switching parameters is modeled after testing

methods specified by MIL-M-38510/605. All devices are

100% functionally tested. Listed below are representative

values for typical pin locations and normal clock loading.

Values are expressed in nanoseconds unless otherwise

noted

Global Clock Setup and Hold for LVTTL Standard, with DLL

Speed Grade

-4

Symbol

Description

Device

Min

Max

Units

Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different

standards, adjust the setup time delay by the values shown in Input Delay Adjustments.

No Delay

T_PSDLL/T_PHDLL

XQV100

XQV300

XQV600

XQV1000

2.1 / –0.4

-

ns

Global clock and IFF, with DLL

Notes:

1. IFF = Input Flip-Flop or Latch

2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured

relative to the Global Clock input signal with the slowest route and heaviest load.

3. DLL output jitter is already included in the timing calculation.

Global Clock Setup and Hold for LVTTL Standard, without DLL

Speed Grade

-4

Symbol

Description

Device

Min

Max

Units

Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different

standards, adjust the setup time delay by the values shown in Input Delay Adjustments.

Full Delay

T

_PSFD/T_PHFD

XQV100

XQV300

XQV600

XQV1000

3.0 / 0.0

3.1 / 0.0

3.3 / 0.0

3.6 / 0.0

-

ns

Global clock and IFF, without DLL

Notes:

1. IFF = Input Flip-Flop or Latch

2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured

relative to the Global Clock input signal with the slowest route and heaviest load.

3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

DS002 (v1.5) December 5, 2001

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15

Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

DLL Timing Parameters

Switching parameters testing is modeled after testing meth-

ods specified by MIL-M-38510/605; all devices are 100 per-

cent functionally tested. Because of the difficulty in directly

measuring many internal timing parameters, those parame-

ters are derived from benchmark timing patterns. The fol-

lowing guidelines reflect worst-case values across the

recommended operating conditions.

Speed Grade -4

Symbol

F_CLKINHF

F_CLKINLF

T_DLLPWHF

T_DLLPWLF

Description

Input clock frequency (CLKDLLHF)

Min

60

Max

180

90

-

Units

MHz

ns

Inputclock frequency (CLKDLL)

Input clock pulse width (CLKDLLHF)

Input clock pulse width (CLKDLL)

25

2.4

3.0

-

ns

Notes:

1. All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).

CLKDLLHF

Min Max

1.0

CLKDLL

Symbol

T_IPTOL

T_IJITCC

T_LOCK

Description

Input clock period tolerance

Min

Max

1.0

Units

ns

-

Input clock jitter cycle to cycle

Time required for DLL to acquire Lock

F_CLKIN

-

±150

±300

ps

> 60 MHz

50-60 MHz

40-50 MHz

30-40 MHz

25-30 MHz

-

20

-

20

25

µs

ps

-

50

90

-

120

±150

±100

±60

T_SKEW

DLL output skew (between any DLL output)

±150

±100

±60

T_OPHASEDLL output long term phase differential

T_OJITCCDLL output ditter cycle to cycle

Notes:

1. All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).

Period Tolerance: the allowed input clock period change in nanoseconds.

+ T

_

T

IPTOL

CLKIN

Clock Jitter: the difference between an ideal reference clock edgfe and the actual design.

_

+

DS002_01_060100

T

OJITCC

Figure 1: Frequency Tolerance and Clock Jitter

16

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DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

QPro Virtex Pinouts

Pinout Tables

See the Xilinx WebLINX web site (http://www.xil-

inx.com/partinfo/databook.htm) for updates or additional

pinout information. For convenience, Table 3, Table 4 and

Table 5 list the locations of special-purpose and power-sup-

ply pins. Pins not listed are user I/Os.

Table 3: Virtex QFP Package Pinout Information

Pin Name

Device

All

PQ/HQ240

92

GCK0

GCK1

GCK2

GCK3

M0

89

210

213

60

M1

58

M2

62

CCLK

PROGRAM

DONE

INIT

179

122

120

123

178

177

167

163

156

145

138

134

124

185

184

183

181

2

BUSY/DOUT

D0/DIN

D1

D2

D3

D4

D5

D6

D7

WRITE

CS

TDI

TDO

TMS

TCK

239

V_CCINT

16, 32, 43, 77, 88, 104,

137, 148, 164, 198, 214,

225

V_CCO

All

15, 30, 44, 61, 76, 90,

105, 121, 136, 150, 165,

180, 197, 212, 226, 240

(The V_CCOfor the PQ/HQ240 package is common to all eight I/O

banks. Different output standards per I/O bank that require different

V_CCOvalues cannot be supported.)

DS002 (v1.5) December 5, 2001

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17

Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

Table 3: Virtex QFP Package Pinout Information (Continued)

Pin Name

Device

XQV100

XQV300

XQV600

PQ/HQ240

... + 229

... + 236

... + 230

V_REF, Bank 0

(V_REFpins are listed incrementally. Connect all pins listed for both

the required device and all smaller devices listed in the same

package.)

Within each bank, if input reference voltage is not required, all V_REF

pins are general I/O.

V_REF, Bank 1

XQV100

XQV300

XQV600

... + 194

... + 187

... + 193

(V_REFpins are listed incrementally. Connect all pins listed for both

the required device and all smaller devices listed in the same

package.)

Within each bank, if input reference voltage is not required, all V_REF

pins are general I/O.

V_REF, Bank 2

XQV100

XQV300

XQV600

... + 168

... + 175

... + 169

(V_REFpins are listed incrementally. Connect all pins listed for both

the required device and all smaller devices listed in the same

package.)

Within each bank, if input reference voltage is not required, all V_REF

pins are general I/O.

V_REF, Bank 3

XQV100

XQV300

XQV600

... + 133

... + 126

... + 132

(V_REFpins are listed incrementally. Connect all pins listed for both

the required device and all smaller devices listed in the same

package.)

Within each bank, if input reference voltage is not required, all V_REF

pins are general I/O.

V_REF, Bank 4

XQV100

XQV300

XQV600

... + 108

... + 115

... + 109

(V_REFpins are listed incrementally. Connect all pins listed for both

the required device and all smaller devices listed in the same

package.)

Within each bank, if input reference voltage is not required, all V_REF

pins are general I/O.

V_REF, Bank 5

XQV100

XQV300

XQV600

... + 73

... + 66

... + 72

(V_REFpins are listed incrementally. Connect all pins listed for both

the required device and all smaller devices listed in the same

package.)

Within each bank, if input reference voltage is not required, all V_REF

pins are general I/O.

V_REF, Bank 6

XQV100

XQV300

XQV600

... + 47

... + 54

... + 48

(V_REFpins are listed incrementally. Connect all pins listed for both

the required device and all smaller devices listed in the same

package.)

Within each bank, if input reference voltage is not required, all V_REF

pins are general I/O.

18

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DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Table 3: Virtex QFP Package Pinout Information (Continued)

Pin Name

Device

XQV100

XQV300

XQV600

PQ/HQ240

... + 12

V_REF, Bank 7 (V_REFpins are listed incrementally. Connect all pins

listed for both the required device and all smaller devices listed in the

same package.)

... + 5

... + 11

Within each bank, if input reference voltage is not required, all V_REF

pins are general I/O.

GND

All

1, 8, 14, 22, 29, 37, 45, 51,

59, 69, 75, 83, 91, 98,

106, 112, 119, 129, 135,

143, 151, 158, 166, 172,

182, 190, 196, 204, 211,

219, 227, 233

Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information

Pin Name

Device

All

BG256

Y11

Y10

A10

B10

Y1

BG352

AE13

AF14

B14

D14

AD24

AB23

AC23

C3

BG432

BG560/CG560

AL17

AJ17

D17

A17

AJ29

AK30

AN32

C4

GCK0

GCK1

GCK2

GCK3

M0

AL16

AK16

A16

D17

AH28

AH29

AJ28

D4

M1

U3

M2

W2

CCLK

PROGRAM

DONE

INIT

B19

Y20

W19

U18

D18

C19

E20

G19

J19

M19

P19

T20

V19

A19

B18

C17

A20

D3

AC4

AD3

AD2

E4

AH3

AH4

AJ2

D3

AM1

AJ5

AH5

D4

BUSY/DOUT

D0/DIN

D1

D3

C2

E4

G1

K4

K3

D2

J3

K2

L4

D3

M3

P4

P3

D4

R3

V4

W4

D5

U4

AB1

AB3

AG4

B4

AB5

AC4

AJ4

D6

V3

D7

AC3

D5

WRITE

CS

C4

D5

A2

TDI

B3

D5

TDO

TMS

TCK

D4

C4

E6

D23

C24

AD23

D29

D28

AH27

B33

E29

AK29

A1

DXN

W3

DS002 (v1.5) December 5, 2001

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19

Preliminary Product Specification

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QPro Virtex 2.5V QML High-Reliability FPGAs

Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information (Continued)

Pin Name

Device

BG256

BG352

AE24

-

BG432

AK29

-

BG560/CG560

DXP

All

V4

AJ28

-

V_CCINT

XQV100 C10,D6,D15,

F4, F17, L3,

(V_CCINTpins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

L18, R4, R17,

U6, U15, V10

devices listed in the same package.)

XQV300

-

A20, B16,

C14, D10,

D12, J24, K4,

L1, L25, P2,

P25, R23, T1,

V24, W2,

AC10, AE14,

AE19, AF11,

AF16,

A10, A17, B23,

C14, C19, K3,

K29, N2, N29,

T1, T29, W2,

W31, AB2,

AB30, AJ10,

AJ16, AK13,

AK19, AK22

-

XQV600

-

... + B26, C7,

F1, F30, AE29,

AF1, AH8,

AH24

-

XQV1000

-

A21, B12, B14,

B18, B28, C22,

C24, E9, E12, F2,

H30, J1, K32, M3,

N1, N29, N33,

U5, U30, Y2,

Y31, AB2, AB32,

AD2, AD32, AG3,

AG31, AJ13,

AK8, AK11,

AK17, AK20,

AL14, AL22,

AL27, AN25

V_CCO, Bank 0

V_CCO, Bank 1

V_CCO, Bank 2

V_CCO, Bank 3

V_CCO, Bank 4

V_CCO, Bank 5

All

D7, D8

D13, D14

G17, H17

N17, P17

U13, U14

U7, U8

A17, B25,

D19

A21, C29, D21

A1, A11, D11

C3, L1, L4

A22, A26, A30,

B19, B32

A10, D7, D13

B2, H4, K1

P4, U1, Y4

A10, A16, B13,

C3, E5

B2, D1, H1, M1,

R2

AA1, AA4, AJ3

V1, AA2, AD1,

AK1, AL2

AC8, AE2,

AF10

AH11, AL1,

AL11

AM2, AM15,

AN4, AN8, AN12

AC14, AC20,

AF17

AH21, AJ29,

AL21

AL31, AM21,

AN18, AN24,

AN30

V

_CCO, Bank 6

_CCO, Bank 7

All

N4, P4

G4, H4

U26, W23,

AE25

AA28, AA31,

AL31

W32, AB33,

AF33, AK33,

AM32

V

G23, K26,

N23

A31, L28, L31

C32, D33, K33,

N32, T33

20

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DS002 (v1.5) December 5, 2001

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Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information (Continued)

Pin Name

Device

XQV100

XQV300

BG256

A4, A8, B4

-

BG352

BG432

BG560/CG560

V_REF, Bank 0

-

(VREF pins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

A16, C19,

C21, D21

B19, D22, D24,

D26

XQV600

-

... + C18, C24

-

devices listed in the same package.)

XQV1000

A19, D20, D26,

D29, E21, E23,

E24, E27,

Within each bank, if input reference

voltage is not required, all V_REFpins

are general I/O.

V_REF, Bank 1

XQV100

XQV300

A17, B12,

B15

-

(VREF pins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

-

B6, C9, C12,

D6

A13, B7, C6,

C10

devices listed in the same package.)

XQV600

-

... + B15, D10

-

Within each bank, if input reference

voltage is not required, all V_REFpins

are general I/O.

XQV1000

A6, D7, D10,

D11, D13, D16,

E7, E15

V_REF, Bank 2

XQV100 C20, F19, J18

-

(V_REFpins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

XQV300

-

D2, E2, H2,

M4

E2, G3, J2, N1

XQV600

-

... + H1, R3

-

devices listed in the same package.)

XQV1000

B3, G5, H4, K5,

L5, N5, P4, R1

Within each bank, if input reference

voltage is not required, all V_REFpins

are general I/O.

V_REF, Bank 3

XQV100

XQV300

M18, R19,

V20

-

(V_REFpins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

-

R4, V4, Y3,

AC2

V2, AB4, AD4,

AF3

devices listed in the same package.)

XQV600

-

... + U2, AC3

-

Within each bank, if input reference

voltage is not required, all V_REFpins

are general I/O.

XQV1000

V4, W5, AA4,

AD3, AE5, AF1,

AH4, AK2

DS002 (v1.5) December 5, 2001

www.xilinx.com

21

Preliminary Product Specification

1-800-255-7778

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information (Continued)

Pin Name

Device

BG256

BG352

BG432

BG560/CG560

V_REF, Bank 4

XQV100

V12, W15,

Y18

-

(V_REFpins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

XQV300

-

AC12, AE4,

AE5, AE8

AJ7, AL4, AL8,

AL13

-

devices listed in the same package.)

XQV600

-

... + AK8, AK15

-

Within each bank, if input reference

voltage is not required, all V_REFpins

are general I/O.

XQV1000

AK13, AL7, AL9,

AL10, AL16,

AM4, AM14,AN3

V_REF, Bank 5

XQV100

XQV300

V9, W6, Y3

-

(V_REFpins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

AC15, AC18,

AD20, AE23

AJ18, AJ25,

AK23, AK27

XQV600

-

... + AJ17,

AL24

-

devices listed in the same package.)

Within each bank, if input reference

voltage is not required, all V_REFpins

are general I/O.

XQV1000

-

AJ18, AJ25,

AK28, AL20,

AL24, AL29,

AM26, AN23

V_REF, Bank 6

XQV100

XQV300

M2, R3, T1

-

(V_REFpins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

R24, Y26,

AA25, AD26

V28, AB28,

AE30, AF28

XQV600

-

... + U28, AC28

-

devices listed in the same package.)

XQV1000

V29, Y32,

AA30,AD31,

AE29, AK32,

AE31, AH30

Within each bank, if input reference

voltage is not required, all V_REFpins

are general I/O.

V_REF, Bank 7

XQV100

XQV300

D1, G3, H1

-

(V_REFpins are listed incrementally.

Connect all pins listed for both the

required device and all smaller

D26, E24,

G26, L26

F28, F31, J30,

N30

XQV600

-

... + J28, R31

-

devices listed in the same package.)

XQV1000

D31, E31, G31,

H32, K31, P31,

T31, L33

Within each bank, if input reference

voltage is not required, all V_REFpins

are general I/O.

22

www.xilinx.com

DS002 (v1.5) December 5, 2001

1-800-255-7778

Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information (Continued)

Pin Name

Device

BG256

BG352

BG432

BG560/CG560

GND

All

C3, C18, D4,

A1, A2, A5,

A2, A3, A7, A9, A1, A7, A12, A14,

D5, D9, D10, A8, A14, A19, A14, A18, A23,

A18, A20, A24,

A29, A32, A33,

B1, B6, B9, B15,

B23, B27, B31,

D11, D12,

D16, D17. E4, A26, B1, B26,

E17, J4, J17, E1, E26, H1,

A22, A25,

A25, A29, A30,

B1, B2, B30,

B31, C1, C31,

K4, K17, L4, H26, N1, P26, D16, G1, G31, C2, E1, F32, G2,

L17, M4, M9,

M10, M17,

T4, T17, U4,

U5, U9, U10,

U11, U12,

W1, W26,

AB1, AB26,

AE1, AE26,

AF1, AF2,

AF5, AF8,

J1, J31, P1,

P31, T4, T28,

V1, V31, AC1,

AC31, AE1,

AE31, AH16,

AJ1, AJ31,

G33, J32, K1, L2,

M33, P1, P33,

R32, T1, V33,

W2, Y1, Y33,

AB1, AC32,

U16, U17, V3, AF13, AF19,

AD33, AE2, AG1,

AG32, AH2,

V18

AF22, AF25,

AF26

AK1, AK2,

AK30, AK31,

AL2, AL3, AL7,

AL9, AL14,

AL18, AL23,

AL25, AL29,

AL30

AJ33, AL32,

AM3, AM7,

AM11, AM19,

AM25, AM28,

AM33, AN1, AN2,

AN5, AN10,

AN14, AN16,

AN20, AN22,

AN27, AN33

GND⁽¹⁾

All

J9, J10, J11,

J12, K9, K10,

K11, K12, L9,

L10, L11,

L12, M9,

M10,

M11,M12

-

No Connect

-

C31, AC2, AK4,

AL3

Notes:

1. 16 extra balls (grounded) at package center.

DS002 (v1.5) December 5, 2001

www.xilinx.com

23

Preliminary Product Specification

1-800-255-7778

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Table 5: CQFP Package (CB228) (Continued)

Ceramic Quad Flat Package (CB228) Pinout

Information

Function

Pin No.

IO

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

Table 5: CQFP Package (CB228)

IO

Function

Pin No.

1

VCCINT

GND

TMS

2

IO

3

IO_VREF_6

IO

4

IO

IO_VREF_7

5

IO

6

IO_VREF_6

IO

7

GND

8

IO

9

IO

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

IO_VREF_6

IO

IO_VREF_7

IO

GND

VCCINT

IO

M1

GND

M0

IO

VCCO

IO

M2

IO

IO_VREF_7

IO

IO_VREF_5

IO

GND

IO_VREF_5

IO

IO_IRDY

GND

VCCO

IO_TRDY

VCCINT

IO

IO_VREF5

IO

GND

VCCINT

IO

IO_VREF_6

IO

VCCO

IO

VCCO

IO

24

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DS002 (v1.5) December 5, 2001

1-800-255-7778

Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Table 5: CQFP Package (CB228) (Continued)

Function

Pin No.

Function

IO

Pin No.

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

IO_VREF_5

79

80

IO

IO_VREF_3

IO

81

IO

82

IO

VCCINT

GCK1

VCCO

GND

GCKO

IO

83

GND

84

IO_VREF_3

IO

85

86

IO

87

IO_VREF_3

IO_D6

GND

88

IO

89

IO

90

VCCINT

IO_D5

IO

91

IO_VREF_4

IO

92

93

VCCO

IO

94

VCCO

IO

95

IO

96

IO_VREF_3

IO_D4

IO

97

IO

98

VCCINT

GND

IO

99

IO

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

VCCINT

IO_TRDY

VCCO

GND

IO_VREF_4

IO

IO_IRDY

IO

IO_VREF_4

GND

IO

IO_D3

IO_VREF_2

IO

IO_VREF_4

IO

VCCO

IO

GND

DONE

VCCO

PROGRAM

IO_INIT

IO_D7

IO

IO_D2

VCCINT

GND

IO_D1

DS002 (v1.5) December 5, 2001

www.xilinx.com

25

Preliminary Product Specification

1-800-255-7778

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Table 5: CQFP Package (CB228) (Continued)

Function

Pin No.

Function

Pin No.

IO_VREF_2

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

GCK2

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

IO

GND

IO

VCCO

IO_VREF_2

GCK3

GND

VCCINT

IO

IO_VREF_2

IO

IO_VREF_0

IO_DIN_D0

IO

IO_DOUT_BUSY

IO

CCLK

VCCO

IO

TDO

IO

GND

IO

VCCINT

GND

TDI

IO_CS

IO_WRITE

IO

IO_VREF_0

IO

IO_VREF_1

IO

GND

IO_VREF_0

GND

IO_VREF_1

IO

IO_VREF_1

IO_VREF_0

IO

GND

IO

VCCINT

TCK

IO

VCCO

GND

IO

1, 8, 14, 27, 42, 48,

56, 66, 72, 86, 100,

106, 113, 123, 129,

143, 157, 163, 173,

180, 186, 200, 215,

221

IO

VCCO

IO

VCCINT

VCCO

15, 30, 41, 73, 83, 99,

130, 140, 156, 187,

203, 214

IO_VREF_1

IO

18, 28, 37, 58, 76, 85,

95, 115, 133, 142,

152, 171, 191, 201,

210, 228

26

www.xilinx.com

DS002 (v1.5) December 5, 2001

1-800-255-7778

Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Table 6: Pinout Diagram Symbols

Pinout Diagrams

Symbol

Pin Function

M0, M1, M2

The following diagrams illustrate the locations of spe-

cial-purpose pins on Virtex FPGAs. Table 6 lists the sym-

bols used in these diagrams. The diagrams also show

I/O-bank boundaries.

❿, ❿,❿❿

❿, ❿, ❿, ❿, D0/DIN, D1, D2, D3, D4, D5, D6, D7

❿, ❿, ❿, ❿

Table 6: Pinout Diagram Symbols

B

D

P

I

DOUT/BUSY

Symbol

Pin Function

General I/O

DONE

S

d

PROGRAM

Device-dependent general I/O, n/c on

smaller devices

INIT

V

v

V_CCINT

K

W

S

T

+

–

CCLK

Device-dependent V_CCINT, n/c on smaller

devices

WRITE

CS

O

R

r

V_CCO

V_REF

Boundary-scan test aAccess port

Temperature diode, anode

Temperature diode, cathode

No connect

Device-dependent V_REF, remains I/O on

smaller devices

G

Ground

n

Ø, 1, 2, 3

Global Clocks

DS002 (v1.5) December 5, 2001

www.xilinx.com

27

Preliminary Product Specification

1-800-255-7778

R

QPro Virtex 2.5V QML High-Reliability FPGAs

CG560 Pin Function Diagram

❿ ❿ ❿

❿ ❿

❿

❿ ❿

G V

❿

G O

A

B

G S

R G

G

O

G

O 3 G R G V O

G

O

G G

A

B

❿ ❿ ❿ ❿ ❿ ❿

❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿

❿ ❿

G O r

G

v O V G

V O

G

G O T

❿

O

G

❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿

❿

❿ ❿ ❿ ❿ ❿ ❿

❿

n O

C

D

E

G O K

❿ ❿

❿ ❿ ❿

v

V

C

D

E

❿ ❿

❿

❿ ❿

❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿

❿

O

B T W R

r R

r

R 2

R

❿ ❿

r

T

r

❿

❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿

❿

❿ ❿

O T r

V

R

r

R r

R

❿

O

❿ ❿ ❿

❿

G

❿

F

G

H

J

V

G

❿

r

F

G

H

J

Bank 1

Bank 0

❿ ❿

R

❿ ❿

❿

R

V

❿ ❿ ❿ ❿

❿ ❿ ❿

V

G

❿ ❿ ❿

❿ ❿

R V O

K

L

M

G

❿

O

r

R

K

L

M

Bank 2

Bank 7

❿ ❿

❿ ❿ ❿ ❿

G

r

G

❿

❿ ❿

v

❿ ❿ ❿

❿ ❿

O V

N

V

r

v

N

❿ ❿

❿

❿ ❿

❿ ❿ ❿

❿ ❿

❿

G

❿

P

R

T

G

R

G

❿

O

P

R

T

❿ ❿ ❿

R O

CG560

❿ ❿ ❿ ❿

(Top View)

G

R

❿ ❿ ❿ ❿

❿

❿ ❿ ❿

V

U

V

U

❿ ❿

❿

❿ ❿ ❿

V

O

R

G

V

❿

G V

❿ ❿

❿ ❿ ❿

❿ ❿

V R G

❿

W

Y

G

R

O

W

Y

❿

G v

❿

O V R

❿

r

G

❿

❿ ❿ ❿

❿

❿ ❿ ❿

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

O

r

AA

❿ ❿ ❿

Bank 6

v O AB

❿

AC

n

G

Bank 3

❿ ❿

R V G AD

R

❿ ❿ ❿ ❿

O AF

❿ ❿

❿ ❿ ❿ ❿

❿

❿ ❿

r AE

G

R

❿

G

❿ ❿

❿

V G

❿ ❿ ❿

V

❿

AG

AH

Bank 4

Bank 5

❿

r

I

D

❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿

O R

❿

P O G R

G G r O G

❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿

v

r

1 R

V

R

+

G AJ

❿

O n

❿ ❿ ❿ ❿ ❿

❿

❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿

❿ ❿

r – R O AK

n

V

❿ ❿ ❿

❿

❿ ❿ ❿

❿

R O

❿ ❿

❿

O

❿

❿ ❿

❿

G

❿

R

r R

V

R Ø

R

❿

G

v

R

V

❿

G

R

O G

AL

❿ ❿ ❿ ❿ ❿ ❿ ❿

❿ ❿ ❿

G

❿

G

❿

G r

O G AM

❿ ❿

❿

❿ ❿ ❿ ❿

O G AN

O

G

O

G

O

G r O V

28

www.xilinx.com

1-800-255-7778

DS002 (v1.5) December 5, 2001

Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Package Drawing CG560 Ceramic Column Grid

CG560 Ceramic Column Grid Package

DS002 (v1.5) December 5, 2001

www.xilinx.com

29

Preliminary Product Specification

1-800-255-7778

R

QPro Virtex 2.5V QML High-Reliability FPGAs

Device/Package Combinations and Maximum I/O

Maximum User I/O (Excluding dedicated clock pins.)

Package

PQ240

HQ240

BG256

BG352

BG432

BG560

CB228

CG560

XQV100

XQV300

XQV600

XQV1000

166

-

166

-

180

-

316

-

316

-

162

-

404

-

162

-

162

-

404

Ordering Information

Example:

XQV300 -4 CB 228 M

Device Type

Temperature Range/Grade

Speed Grade⁽¹⁾

Number of Pins

Package Type

Device Ordering Options

Temperature

Device Type

XQV100

Package

Grade

PQ240 240-pin Plastic Quad Flat Package

HQ240 240-pin High Heat Dissipation QFP Package

BG256 256-ball Plastic BGA Package

BG352 352-ball Plastic BGA Package

BG432 432-ball Plastic BGA Package

BG560 560-ball Plastic BGA Package

Military Ceramic

T_C= –55°C to +125°C

M

N

Q

XQV300

Military Plastic

T_J= –55°C to +125°C

MIL-PRF-38535⁽²⁾T_C= –55°C to +125°C

XQV600

XQV1000

CB228

228-pin Ceramic Quad Flat Package

CG560 560-column Ceramic Column Grid Package

Notes:

1. -4 only supported speed grade.

2. Class Q must be ordered with SMD number.

Valid Ordering Combinations

M Grade

N Grade

XQV100-4PQ240N

XQV100-4CB228M

XQV300-4CB228M

XQV600-4CB228M

XQV1000-4CG560M

XQV300-4BG432N

XQV600-4HQ240N

XQV600-4BG432N

XQV1000-4BG560N

XQV100-4BG256N

XQV300-4PQ240N

XQV300-4BG352N

30

www.xilinx.com

DS002 (v1.5) December 5, 2001

1-800-255-7778

Preliminary Product Specification

R

QPro Virtex 2.5V QML High-Reliability FPGAs

SMD (Class Q) Odering Options

5962 9957201 Q Y C

Generic Standard

Microcircuit Drawing (SMD)

Lead Finish

Package Type

QML Certified MIL-PRF-38535⁽¹⁾

Device Type

Valid SMD Combinations

SMD Number

Device

Pkg Markings

Lead Finish

Gold Plate

5962-9957201QYC

5962-9957201QZC

5962-9957201NTB

5962-9957201NNA

5962-9957201NUA

5962-9957301QYC

5962-9957301QZC

5962-9957301NTB

5962-9957301NUA

5962-9957401QXC

5962-9957401NUA

XQV300-4CB228Q

XQV300-4PQ240N

XQV300-4BG352N

XQV300-4BG432N

XQV600-4CB228Q

XQV600-4HQ240N

XQV600-4BG432N

XQV1000-4CG560Q

XQV1000-4BG560N

Lid

Base

Gold Plate

-

Solder Plate

Solder Ball

Gold Plate

-

Lid

Base

Gold Plate

-

Solder Plate

Solder Ball

Solder Column

Solder Ball

Notes:

1. Type N designates QML Plastic.

Revision History

The following table shows the revision history for this document

Date

Version

1.0

Revision

10/04/99

06/01/00

02/13/01

11/05/01

11/15/01

12/05/01

Initial Xilinx release.

1.1

Upated format.

1.2

Updated Temperature Specifications.

1.3

Changed V600 Power-up temp min to –55°C. Added L33 as Bank 7 V_REF. Updated format.

Fixed boken links. Added note for VCCO banking rules for PQ240 package.

Corrected Table 5 pin description for pin 9 and pin 39.

1.4

1.5

DS002 (v1.5) December 5, 2001

www.xilinx.com

31

Preliminary Product Specification

1-800-255-7778


型号：	XQC1000-4PQ240M
厂家：	XILINX, INC
描述：	QPro Virtex 2.5V QML High-Reliability FPGAs QPro的Virtex 2.5V QML高可靠性的FPGA
文件：	总31页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XQC1000-4PQ240M [XILINX]

相关型号：

XQC1000-4PQ240N

XQC1000-4PQ240Q

XQC300-4BG256M

XQC300-4BG256N

XQC300-4BG256Q

XQC300-4BG352M

XQC300-4BG352N

XQC300-4BG352Q

XQC300-4BG432M

XQC300-4BG432N

XQC300-4BG432Q

XQC300-4BG560M