XQV2000E-6FGG1156N_技术文档

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QPro Virtex-E 1.8V QML

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Features

•

Certified to MIL-PRF-38535 (Qualified Manufacturer

Listing)

-

200 Mb/s DDR SDRAMs

Supported by free Synthesizable reference design

•

Guaranteed over the full military temperature range

(–55°C to +125°C)

•

High-Performance Built-In Clock Management Circuitry

-

Eight fully digital Delay-Locked Loops (DLLs)

Digitally-Synthesized 50% duty cycle for Double

Data Rate (DDR) Applications

•

Ceramic and Plastic Packages

Fast, High-Density 1.8V FPGA Family

-

Densities from 600K to 2M system gates

130 MHz internal performance (four LUT levels)

Designed for low-power operation

-

Clock Multiply and Divide

Zero-delay conversion of high-speed LVPECL/LVDS

clocks to any I/O standard

Flexible Architecture Balances Speed and Density

PCI compliant 3.3V, 32-bit, 33 MHz

-

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input function

Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

•

Highly Flexible SelectIO™+ Technology

-

Supports 20 high-performance interface standards

Up to 804 singled-ended I/Os or 344 differential I/O

pairs for an aggregate bandwidth of > 100 Gb/s

Differential Signalling Support

-

Internal 3-state bussing

IEEE 1149.1 boundary-scan logic

Die-temperature sensor diode

-

LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

Differential I/O signals can be input, output, or I/O

Compatible with standard differential devices

LVPECL and LVDS clock inputs for 300+ MHz

clocks

•

Supported by Xilinx Foundation™ and Alliance Series™

Development Systems

-

Further compile time reduction of 50%

Internet Team Design (ITD) tool ideal for

million-plus gate density designs

•

Proprietary High-Performance SelectLink Technology

-

Double Data Rate (DDR) to Virtex™-E link

Web-based HDL generation methodology

-

Wide selection of PC and workstation platforms

Sophisticated SelectRAM+™ Memory Hierarchy

•

SRAM-Based In-System Configuration

Unlimited reprogrammability

Advanced Packaging Options

-

600 Kb of internal configurable distributed RAM

Up to 640 Kb of synchronous internal block RAM

Dual port block RAM capability

Memory bandwidth up to 1.66 Tb/s (equivalent

bandwidth of over 100 RAMBUS channels)

-

1.0 mm BGA

1.27 mm BGA

•

0.18 µm 6-Layer Metal Process

100% Factory Tested

-

Designed for high-performance Interfaces to

External Memories

200 MHz ZBT* SRAMs

100% Factory Tested

* ZBT is a trademark of Integrated Device Technology, Inc.

Table 1: Virtex-E Field-Programmable Gate Array Family Members

System

Gates

Logic

Gates

CLB

Array

Logic

Cells

Differential

I/O Pairs

User

I/O

Block

RAM Bits

Distributed

RAM Bits

Device

XQV600E

XQV1000E

XQV2000E

985,882

1,569,178

2,541,952

186,624

331,776

518,400

48 x 72

64 x 96

80 x 120

15,552

27,648

43,200

247

281

344

316

404

804

294,912

393,216

655,360

221,184

393,216

614,400

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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natives to mask-programmed gate arrays. The QPro Vir-

tex-E family includes the three members in Table 1.

Virtex-E Compared to Virtex Devices

The Virtex-E family offers up to 43,200 logic cells in devices

up to 30% faster than the Virtex family.

Building on experience gained from Virtex FPGAs, the

Virtex-E family is an evolutionary step forward in program-

mable logic design. Combining a wide variety of program-

mable system features, a rich hierarchy of fast, flexible

interconnect resources, and advanced process technology,

the Virtex-E family delivers a high-speed and high-capacity

programmable logic solution that enhances design flexibility

while reducing time-to-market.

I/O performance is increased to 622 Mb/s using Source

Synchronous data transmission architectures and synchro-

nous system performance up to 240 MHz using sin-

gled-ended SelectIO technology. Additional I/O standards

are supported, notably LVPECL, LVDS, and BLVDS, which

use two pins per signal. Almost all signal pins can be used

for these new standards.

Virtex-E devices have up to 640 Kb of faster (250 MHz)

block SelectRAM, but the individual RAMs are the same

size and structure as in the Virtex family. They also have

eight DLLs instead of the four in Virtex devices. Each indi-

vidual DLL is slightly improved with easier clock mirroring

and 4x frequency multiplication.

Virtex-E Architecture

Virtex-E devices feature a flexible, regular architecture that

comprises an array of configurable logic blocks (CLBs) sur-

rounded by programmable input/output blocks (IOBs), all

interconnected by a rich hierarchy of fast, versatile routing

resources. The abundance of routing resources permits the

Virtex-E family to accommodate even the largest and most

complex designs.

V

, the supply voltage for the internal logic and mem-

CCINT

ory, is 1.8V, instead of 2.5V for Virtex devices. Advanced

processing and 0.18 µm design rules have resulted in

smaller dice, faster speed, and lower power consumption.

Virtex-E FPGAs are SRAM-based, and are customized by

loading configuration data into internal memory cells. Con-

figuration data can be read from an external SPROM (mas-

ter serial mode), or can be written into the FPGA

(SelectMAP™, slave serial, and JTAG modes).

I/O pins are 3V tolerant, and can be 5V tolerant with an

external 100Ω resistor. PCI 5V is not supported. With the

addition of appropriate external resistors, any pin can toler-

ate any voltage desired.

The standard Xilinx Foundation Series and Alliance Series

Development systems deliver complete design support for

Virtex-E, covering every aspect from behavioral and sche-

matic entry, through simulation, automatic design transla-

tion and implementation, to the creation and downloading of

a configuration bit stream.

Banking rules are different. With Virtex devices, all input

buffers are powered by V

. With Virtex-E devices, the

CCINT

LVTTL, LVCMOS2, and PCI input buffers are powered by

the I/O supply voltage V

.

CCO

The Virtex-E family is not bitstream-compatible with the Vir-

tex family, but Virtex designs can be compiled into equiva-

lent Virtex-E devices.

Higher Performance

Virtex-E devices provide better performance than previous

generations of FPGAs. Designs can achieve synchronous

system clock rates up to 240 MHz including I/O or 622 Mb/s

using Source Synchronous data transmission architech-

tures. Virtex-E I/Os comply fully with 3.3V PCI specifica-

tions, and interfaces can be implemented that operate at

33 MHz or 66 MHz.

The same device in the same package for the Virtex-E and

Virtex families are pin-compatible with some minor excep-

tions. See the data sheet pinout section for details.

General Description

The Virtex-E FPGA family delivers high-performance,

high-capacity programmable logic solutions. Dramatic

increases in silicon efficiency result from optimizing the new

architecture for place-and-route efficiency and exploiting an

aggressive 6-layer metal 0.18 µm CMOS process. These

advances make Virtex-E FPGAs powerful and flexible alter-

While performance is design-dependent, many designs

operate internally at speeds in excess of 133 MHz and can

achieve over 311 MHz.

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Virtex-E Device/Package Combinations and Maximum I/O

Table 2: Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)

XQV600E

XQV1000E

XQV2000E

BG432

BG560

CG560

FG1156

316

-

404

-

404

-

804

Virtex-E Ordering Information

Example:

XQV600E -6 BG 432 M

Device Type

Temperature Range/Grade

Number of Pins

(1)

Speed Grade

Package Type

Device Ordering Options

Temperature

Device Type

XQV600E

Package

BG432 432-ball Plastic BGA Package

Grade

Military Ceramic

Military Plastic

T_C= –55°C to +125°C

T_J= –55°C to +125°C

M

N

XQV1000E

XQV2000E

BG560 560-ball Plastic BGA Package

FG1156 1156-ball Plastic Fine Pitch BGA Package

CG560 560-column Ceramic Column Grid Package

Notes:

1. -6 only supported speed grade.

Valid Ordering Combinations

M Grade

N Grade

XQV1000E-6CG560M

XQV600E-6BG432N

XQV1000E-6BG560N

XQV2000E-6BG560N

XQV2000E-6FG1156N

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Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

05/19/03

07/29/04

Initial Xilinx release.

1.1

•

Device/Package Availability and Ordering Information tables on page 3: Removed

references to devices in CB228 and HQ240 packages (not offered).

Device Ordering Options table on page 3: Removed Footnote (2) referring to Class Q

order codes (not offered).

Table 1: Corrected number of available User I/Os to conform to numbers in Table 2.

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Architectural Description

Virtex-E Array

The Virtex™-E user-programmable gate array, shown in

Figure 1, comprises two major configurable elements: con-

figurable logic blocks (CLBs) and input/output blocks (IOBs).

Values stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memory cells on power-up, and can reload if

necessary to change the function of the device.

•

CLBs provide the functional elements for constructing

logic

Input/Output Block

The Virtex-E IOB, Figure 2, features SelectIO™+ inputs and

outputs that support a wide variety of I/O signalling stan-

dards, see Table 1.

•

IOBs provide the interface between the package pins

and the CLBs

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a VersaBlock that also provides local

routing resources to connect the CLB to the GRM.

Q

D

CE

T

TCE

Weak

Keeper

SR

DLLDLL

PAD

O

Q

D

CE

OCE

OBUFT

VersaRing

SR

I

IQ

Programmable

Delay

Q

D

CE

IBUF

Vref

SR

CLK

ICE

ds022_02_091300

Figure 2: Virtex-E Input/Output Block (IOB)

The three IOB storage elements function either as edge-

triggered D-type flip-flops or as level-sensitive latches. Each

IOB has a clock signal (CLK) shared by the three flip-flops

and independent clock enable signals for each flip-flop.

VersaRing

DLLDLL

ds022_01_121099

In addition to the CLK and CE control signals, the three flip-

flops share a Set/Reset (SR). For each flip-flop, this signal

can be independently configured as a synchronous Set, a

synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

Figure 1: Virtex-E Architecture Overview

The VersaRing™ I/O interface provides additional routing

resources around the periphery of the device. This routing

improves I/O routability and facilitates pin locking.

The output buffer and all of the IOB control signals have

independent polarity controls.

The Virtex-E architecture also includes the following circuits

that connect to the GRM.

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. After

•

Dedicated block memories of 4096 bits each

Clock DLLs for clock-distribution delay compensation

and clock domain control

3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing

resources

configuration, clamping diodes are connected to V

with

CCO

the exception of LVCMOS18, LVCMOS25, GTL, GTL+,

LVDS, and LVPECL.

•

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Each input buffer can be configured to conform to any of the

low-voltage signalling standards supported. In some of

these standards the input buffer utilizes a user-supplied

Table 1: Supported I/O Standards

Board

Output Input Input Termination

I/O

threshold voltage, V . The need to supply V

imposes

REF

Standard

V

Voltage (V

N/A

)

TT

constraints on which standards can be used in close prox-

imity to each other. See "I/O Banking" on page 2.

CCO

REF

LVTTL

LVCMOS2

LVCMOS18

SSTL3 I & II

SSTL2 I & II

GTL

3.3

2.5

1.8

3.3

2.5

N/A

1.5

3.3

2.5

3.3

2.5

N/A

1.50

1.25

0.80

1.0

There are optional pull-up and pull-down resistors at each

user I/O input for use after configuration. Their value is in

the range 50-100 kΩ.

N/A

1.8

N/A

Output Path

N/A

3.3

1.50

1.25

1.20

1.50

0.75

1.50

N/A

The output path includes a 3-state output buffer that drives

the output signal onto the pad. The output signal can be

routed to the buffer directly from the internal logic or through

an optional IOB output flip-flop.

GTL+

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

HSTL I

0.75

0.90

1.50

1.32

N/A

HSTL III & IV

CTT

Each output driver can be individually programmed for a

wide range of low-voltage signalling standards. Each output

buffer can source up to 24 mA and sink up to 48 mA. Drive

strength and slew rate controls minimize bus transients.

AGP-2X

PCI33_3

PCI66_3

BLVDS & LVDS

LVPECL

N/A

In most signalling standards, the output High voltage

3.3

N/A

depends on an externally supplied V

voltage. The need

CCO

N/A

to supply V

imposes constraints on which standards

CCO

can be used in close proximity to each other. See "I/O Bank-

ing" on page 2.

N/A

Optional pull-up, pull-down and weak-keeper circuits are

attached to each pad. Prior to configuration all outputs not

involved in configuration are forced into their high-imped-

ance state. The pull-down resistors and the weak-keeper

circuits are inactive, but I/Os can optionally be pulled up.

An optional weak-keeper circuit is connected to each out-

put. When selected, the circuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way eliminates bus chatter.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins are in a

high-impedance state. Consequently, external pull-up or

pull-down resistors must be provided on pins required to be

at a well-defined logic level prior to configuration.

Since the weak-keeper circuit uses the IOB input buffer to

monitor the input level, an appropriate V

voltage must be

REF

provided if the signalling standard requires one. The provi-

sion of this voltage must comply with the I/O banking rules.

All Virtex-E IOBs support IEEE 1149.1-compatible bound-

ary scan testing.

I/O Banking

Some of the I/O standards described above require V

CCO

Input Path

and/or V

voltages. These voltages are externally sup-

REF

plied and connected to device pins that serve groups of

IOBs, called banks. Consequently, restrictions exist about

which I/O standards can be combined within a given bank.

The Virtex-E IOB input path routes the input signal directly

to internal logic and/ or through an optional input flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is zero.

Eight I/O banks result from separating each edge of the

FPGA into two banks, as shown in Figure 3. Each bank has

multiple V

pins, all of which must be connected to the

CCO

same voltage. This voltage is determined by the output

standards in use.

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V

rather than V

. For these standards, only input

CCINT

CCO

and output buffers that have the same V

together.

can be mixed

CCO

Bank 0

Bank 1

GCLK3 GCLK2

The V

and V

pins for each bank appear in the device

REF

CCO

pin-out tables and diagrams. The diagrams also show the

bank affiliation of each I/O.

VirtexE

Device

Within a given package, the number of V

and V

pins

CCO

REF

can vary depending on the size of device. In larger devices,

more I/O pins convert to V pins. Since these are always

REF

a super set of the V

pins used for smaller devices, it is

GCLK1 GCLK0

REF

possible to design a PCB that permits migration to a larger

device if necessary. All the V pins for the largest device

Bank 5

Bank 4

REF

anticipated must be connected to the V

used for I/O.

voltage, and not

REF

ds022_03_121799

Figure 3: Virtex-E I/O Banks

In smaller devices, some V

pins used in larger devices

CCO

do not connect within the package. These unconnected pins

can be left unconnected externally, or can be connected to

Within a bank, output standards can be mixed only if they

use the same V . Compatible standards are shown in

Table 2. GTL and GTL+ appear under all voltages because

CCO

the V

voltage to permit migration to a larger device if

CCO

necessary.

their open-drain outputs do not depend on V

.

CCO

Configurable Logic Blocks

Table 2: Compatible Output Standards

The basic building block of the Virtex-E CLB is the logic cell

(LC). An LC includes a 4-input function generator, carry

logic, and a storage element. The output from the function

generator in each LC drives both the CLB output and the D

input of the flip-flop. Each Virtex-E CLB contains four LCs,

organized in two similar slices, as shown in Figure 4.

Figure 5 shows a more detailed view of a single slice.

V

Compatible Standards

CCO

3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+, LVPECL

2.5V

SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,

BLVDS, LVDS

1.8V

1.5V

LVCMOS18, GTL, GTL+

In addition to the four basic LCs, the Virtex-E CLB contains

logic that combines function generators to provide functions

of five or six inputs. Consequently, when estimating the

number of system gates provided by a given device, each

CLB counts as 4.5 LCs.

HSTL I, HSTL III, HSTL IV, GTL, GTL+

Some input standards require a user-supplied threshold

voltage, V . In this case, certain user-I/O pins are auto-

REF

matically configured as inputs for the V

imately one in six of the I/O pins in the bank assume this

role.

voltage. Approx-

REF

Look-Up Tables

Virtex-E function generators are implemented as 4-input

look-up tables (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16 x 1-bit dual-port synchronous RAM.

The V

pins within a bank are interconnected internally

REF

and consequently only one V

voltage can be used within

REF

each bank. All V

pins in the bank, however, must be con-

REF

nected to the external voltage source for correct operation.

Within a bank, inputs that require V can be mixed with

REF

The Virtex-E LUT can also provide a 16-bit shift register that

is ideal for capturing high-speed or burst-mode data. This

mode can also be used to store data in applications such as

Digital Signal Processing.

those that do not. However, only one V

used within a bank.

voltage can be

REF

In Virtex-E, input buffers with LVTTL, LVCMOS2,

LVCMOS18, PCI33_3, PCI66_3 standards are supplied by

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COUT

YB

Y

YB

Y

G4

G3

G2

SP

Q

G3

G2

G1

Carry &

Control

Carry &

Control

LUT

D

YQ

D

Q

YQ

CE

G1

BY

F4

RC

BY

XB

X

XB

X

F4

F3

F2

F1

SP

F3

F2

LUT

Carry &

Control

Carry &

Control

D

Q

D

Q

XQ

CE

F1

RC

Slice 0

RC

Slice 1

BX

CIN

ds022_04_121799

Figure 4: 2-Slice Virtex-E CLB

COUT

CY

YB

Y

G4

I3

O

G3

G2

G1

I2

I1

I0

LUT

INIT

D Q

CE

YQ

DI

WE

0

1

REV

BY

XB

F5IN

F6

CY

F5

X

F5

BY DG

CK WSO

WE

BX

WSH

A4

DI

INIT

D Q

CE

XQ

BX

DI

WE

I3

I2

I1

I0

F4

F3

F2

F1

REV

O

LUT

0

1

SR

CLK

CE

ds022_05_092000

CIN

Figure 5: Detailed View of Virtex-E Slice

function generators within the slice or directly from slice

inputs, bypassing the function generators.

Storage Elements

The storage elements in the Virtex-E slice can be config-

ured either as edge-triggered D-type flip-flops or as level-

sensitive latches. The D inputs can be driven either by the

In addition to Clock and Clock Enable signals, each Slice

has synchronous set and reset signals (SR and BY). SR

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forces a storage element into the initialization state speci-

fied for it in the configuration. BY forces it into the opposite

state. Alternatively, these signals can be configured to oper-

ate asynchronously. All of the control signals are indepen-

dently invertible, and are shared by the two flip-flops within

the slice.

Table 3: CLB/Block RAM Column Locations

Column Number

XQ

Device

V600E

0

√

12 24 36 48 60 72 84 96 108 120

√

V1000E

V2000E

√

Additional Logic

√

The F5 multiplexer in each slice combines the function gen-

erator outputs. This combination provides either a function

generator that can implement any 5-input function, a 4:1

multiplexer, or selected functions of up to nine inputs.

Table 4 shows the amount of block SelectRAM memory that

is available in each Virtex-E device.

Table 4: Virtex-E Block SelectRAM Amounts

Similarly, the F6 multiplexer combines the outputs of all four

function generators in the CLB by selecting one of the F5-

multiplexer outputs. This permits the implementation of any

6-input function, an 8:1 multiplexer, or selected functions of

up to 19 inputs.

Virtex-E Device # of Blocks Block SelectRAM Bits

XQV600E

XQV1000E

XQV2000E

72

96

294,912

393,216

655,360

Each CLB has four direct feedthrough paths, two per slice.

These paths provide extra data input lines or additional local

routing that does not consume logic resources.

160

As illustrated in Figure 6, each block SelectRAM cell is a

fully synchronous dual-ported (True Dual Port) 4096-bit

RAM with independent control signals for each port. The

data widths of the two ports can be configured indepen-

dently, providing built-in bus-width conversion.

Arithmetic Logic

Dedicated carry logic provides fast arithmetic carry capabil-

ity for high-speed arithmetic functions. The Virtex-E CLB

supports two separate carry chains, one per Slice. The

height of the carry chains is two bits per CLB.

RAMB4_S#_S#

The arithmetic logic includes an XOR gate that allows a 2-

bit full adder to be implemented within a slice. In addition, a

dedicated AND gate improves the efficiency of multiplier

implementation. The dedicated carry path can also be used

to cascade function generators for implementing wide logic

functions.

WEA

ENA

RSTA

DOA[#:0]

CLKA

ADDRA[#:0]

DIA[#:0]

BUFTs

WEB

ENB

Each Virtex-E CLB contains two 3-state drivers (BUFTs)

that can drive on-chip busses. See "Dedicated Routing" on

page 6. Each Virtex-E BUFT has an independent 3-state

control pin and an independent input pin.

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

DOB[#:0]

ds022_06_121699

Block SelectRAM

Figure 6: Dual-Port Block SelectRAM

Virtex-E FPGAs incorporate large block SelectRAM memo-

ries. These complement the Distributed SelectRAM memo-

ries that provide shallow RAM structures implemented in

CLBs.

Table 5 shows the depth and width aspect ratios for the

block SelectRAM. The Virtex-E block SelectRAM also

includes dedicated routing to provide an efficient interface

with both CLBs and other block SelectRAMs. Refer to

XAPP130 for block SelectRAM timing waveforms.

Block SelectRAM memory blocks are organized in columns,

starting at the left (column 0) and right outside edges and

inserted every 12 CLB columns (see notes for smaller

devices). Each memory block is four CLBs high, and each

memory column extends the full height of the chip, immedi-

ately adjacent (to the right, except for column 0) of the CLB

column locations indicated in Table 3.

Table 5: Block SelectRAM Port Aspect Ratios

Width

Depth

4096

2048

ADDR Bus

ADDR<11:0>

ADDR<10:0>

Data Bus

DATA<0>

1

2

DATA<1:0>

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Table 5: Block SelectRAM Port Aspect Ratios

resources are associated with this level of the routing hier-

archy. General-purpose routing resources are located in

horizontal and vertical routing channels associated with the

CLB rows and columns and are as follows:

Width

Depth

1024

512

ADDR Bus

ADDR<9:0>

ADDR<8:0>

ADDR<7:0>

Data Bus

DATA<3:0>

DATA<7:0>

DATA<15:0>

4

8

•

Adjacent to each CLB is a General Routing Matrix

(GRM). The GRM is the switch matrix through which

horizontal and vertical routing resources connect, and

is also the means by which the CLB gains access to

the general purpose routing.

16

256

Programmable Routing Matrix

•

24 single-length lines route GRM signals to adjacent

GRMs in each of the four directions.

It is the longest delay path that limits the speed of any worst-

case design. Consequently, the Virtex-E routing architec-

ture and its place-and-route software were defined in a joint

optimization process. This joint optimization minimizes

long-path delays, and consequently, yields the best system

performance.

72 buffered Hex lines route GRM signals to another

GRMs six-blocks away in each one of the four

directions. Organized in a staggered pattern, Hex lines

are driven only at their endpoints. Hex-line signals can

be accessed either at the endpoints or at the midpoint

(three blocks from the source). One third of the Hex

lines are bidirectional, while the remaining ones are

uni-directional.

12 Longlines are buffered, bidirectional wires that

distribute signals across the device quickly and

efficiently. Vertical Longlines span the full height of the

device, and horizontal ones span the full width of the

device.

The joint optimization also reduces design compilation

times because the architecture is software-friendly. Design

cycles are correspondingly reduced due to shorter design

iteration times.

•

Local Routing

The VersaBlock provides local routing resources (see

Figure 7), providing three types of connections:

•

Interconnections among the LUTs, flip-flops, and GRM

I/O Routing

Internal CLB feedback paths that provide high-speed

connections to LUTs within the same CLB, chaining

them together with minimal routing delay

Virtex-E devices have additional routing resources around

their periphery that form an interface between the CLB array

and the IOBs. This additional routing, called the

VersaRing, facilitates pin-swapping and pin-locking, such

that logic redesigns can adapt to existing PCB layouts.

Time-to-market is reduced, since PCBs and other system

components can be manufactured while the logic design is

still in progress.

•

Direct paths that provide high-speed connections

between horizontally adjacent CLBs, eliminating the

delay of the GRM.

To Adjacent

GRM

To

Adjacent

GRM

Dedicated Routing

To Adjacent

GRM

Some classes of signal require dedicated routing resources to

maximize performance. In the Virtex-E architecture, dedi-

cated routing resources are provided for two classes of signal.

To Adjacent

GRM

•

Horizontal routing resources are provided for on-chip 3-

state busses. Four partitionable bus lines are provided

per CLB row, permitting multiple busses within a row,

as shown in Figure 8.

Direct

Direct Connection

To Adjacent

CLB

Connection

To Adjacent

CLB

XCVE_ds_007

Figure 7: Virtex-E Local Routing

•

Two dedicated nets per CLB propagate carry signals

vertically to the adjacent CLB.Global Clock Distribution

Network

General Purpose Routing

Most Virtex-E signals are routed on the general purpose

routing, and consequently, the majority of interconnect

DLL Location

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RAM clock pins. The global nets can be driven only by

global buffers. There are four global buffers, one for

each global net.

The local clock routing resources consist of 24

backbone lines, 12 across the top of the chip and 12

across bottom. From these lines, up to 12 unique

signals per column can be distributed via the 12

longlines in the column. These local resources are

more flexible than the global resources since they are

not restricted to routing only to clock pins.

Clock Routing

Clock Routing resources distribute clocks and other signals

with very high fanout throughout the device. Virtex-E

devices include two tiers of clock routing resources referred

to as global and local clock routing resources.

•

The global routing resources are four dedicated global

nets with dedicated input pins that are designed to

distribute high-fanout clock signals with minimal skew.

Each global clock net can drive all CLB, IOB, and block

Tri-State

Lines

CLB

buft_c.eps

Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes

selected either from these pads or from signals in the gen-

eral purpose routing.

Global Clock Distribution

Virtex-E provides high-speed, low-skew clock distribution

through the global routing resources described above. A

typical clock distribution net is shown in Figure 9.

Digital Delay-Locked Loops

There are eight DLLs (Delay-Locked Loops) per device,

with four located at the top and four at the bottom,

Figure 10. The DLLs can be used to eliminate skew

between the clock input pad and the internal clock input pins

throughout the device. Each DLL can drive two global clock

networks.The DLL monitors the input clock and the distrib-

uted clock, and automatically adjusts a clock delay element.

Additional delay is introduced such that clock edges arrive

at internal flip-flops synchronized with clock edges arriving

at the input.

GCLKPAD3

GCLKBUF3

GCLKPAD2

GCLKBUF2

Global Clock Column

Global Clock Rows

In addition to eliminating clock-distribution delay, the DLL

provides advanced control of multiple clock domains. The

DLL provides four quadrature phases of the source clock,

and can double the clock or divide the clock by 1.5, 2, 2.5, 3,

4, 5, 8, or 16.

The DLL also operates as a clock mirror. By driving the out-

put from a DLL off-chip and then back on again, the DLL can

be used to de-skew a board level clock among multiple

devices.

GCLKBUF1

GCLKPAD1

GCLKBUF0

GCLKPAD0

XCVE_009

Figure 9: Global Clock Distribution Network

Four global buffers are provided, two at the top center of the

device and two at the bottom center. These drive the four

global nets that in turn drive any clock pin.

To guarantee that the system clock is operating correctly

prior to the FPGA starting up after configuration, the DLL

can delay the completion of the configuration process until

after it has achieved lock. For more information about DLL

functionality, see the Design Consideration section of the

data sheet.

Four dedicated clock pads are provided, one adjacent to

each of the global buffers. The input to the global buffer is

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V

in bank 2, and for proper operation of LVTTL 3.3V lev-

CCO

DLLDLL

els, the bank should be supplied with 3.3V.

Boundary-scan operation is independent of individual IOB

configurations, and unaffected by package type. All IOBs,

including un-bonded ones, are treated as independent 3-

state bidirectional pins in a single scan chain. Retention of

the bidirectional test capability after configuration facilitates

the testing of external interconnections.

Primary DLLs

Table 6 lists the boundary-scan instructions supported in

Virtex-E FPGAs. Internal signals can be captured during

EXTEST by connecting them to un-bonded or unused IOBs.

They can also be connected to the unused outputs of IOBs

defined as unidirectional input pins.

DLLDLL

XCVE_0010

Before the device is configured, all instructions except

USER1 and USER2 are available. After configuration, all

instructions are available. During configuration, it is recom-

mended that those operations using the boundary-scan

register (SAMPLE/PRELOAD, INTEST, EXTEST) not be

performed.

Figure 10: DLL Locations

Boundary Scan

Virtex-E devices support all the mandatory boundary-scan

instructions specified in the IEEE standard 1149.1. A Test

Access Port (TAP) and registers are provided that imple-

ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions. The TAP

also supports two internal scan chains and configura-

tion/readback of the device.

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FPGA, and also to read back the configuration data.

Figure 11 is a diagram of the Virtex-E Series boundary scan

logic. It includes three bits of Data Register per IOB, the

IEEE 1149.1 Test Access Port controller, and the Instruction

Register with decodes.

The JTAG input pins (TDI, TMS, TCK) do not have a V

requirement and operate with either 2.5V or 3.3V input sig-

nalling levels. The output pin (TDO) is sourced from the

CCO

DATA IN

IOB.T

0

1

0

sd

1

D

Q

D

Q

LE

IOB

sd

1

0

D

Q

D

Q

LE

1

0

IOB.I

1

sd

D

Q

D

Q

0

LE

1

0

IOB.Q

IOB.T

BYPASS

REGISTER

0

1

M

U

X

TDO

1

sd

INSTRUCTION REGISTER

TDI

D

Q

D

Q

0

LE

1

sd

D

Q

D

Q

0

LE

1

0

IOB.I

DATAOUT

SHIFT/

CAPTURE

UPDATE

EXTEST

CLOCK DATA

REGISTER

X9016

Figure 11: Virtex-E Family Boundary Scan Logic

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Each EXTEST CAPTURED-OR state captures all In, Out,

and 3-state pins.

Instruction Set

The Virtex-E Series boundary scan instruction set also

includes instructions to configure the device and read back

configuration data (CFG_IN, CFG_OUT, and JSTART). The

complete instruction set is coded as shown in Table 6..

The other standard data register is the single flip-flop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

Table 6: Boundary Scan Instructions

The FPGA supports up to two additional internal scan

chains that can be specified using the BSCAN macro. The

macro provides two user pins (SEL1 and SEL2) which are

decodes of the USER1 and USER2 instructions respec-

tively. For these instructions, two corresponding pins (T

DO1 and TDO2) allow user scan data to be shifted out of

TDO.

Boundary-Scan

Command

Binary

Code(4:0)

Description

EXTEST

00000

00001

Enables boundary-scan

EXTEST operation

SAMPLE/

PRELOAD

Enables boundary-scan

SAMPLE/PRELOAD

operation

Likewise, there are individual clock pins (DRCK1 and

DRCK2) for each user register. There is a common input pin

(TDI) and shared output pins that represent the state of the

TAP controller (RESET, SHIFT, and UPDATE).

USER1

00010

00011

00100

Access user-defined

register 1

Bit Sequence

USER2

Access user-defined

register 2

The order within each IOB is: In, Out, 3-State. The input-

only pins contribute only the In bit to the boundary scan I/O

data register, while the output-only pins contributes all three

bits.

CFG_OUT

Access the

configuration bus for

read operations.

From a cavity-up view of the chip (as shown in EPIC), start-

ing in the upper right chip corner, the boundary scan data-

register bits are ordered as shown in Figure 12.

CFG_IN

00101

Access the

configuration bus for

write operations.

Right half of top-edge IOBs (Right to Left)

Bit 0 ( TDO end)

Bit 1

Bit 2

INTEST

00111

01000

01001

01010

Enables boundary-scan

INTEST operation

GCLK2

GCLK3

USERCODE

IDCODE

HIGHZ

Enables shifting out

USER code

Left half of top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

M1

M0

M2

Enables shifting out of

ID Code

Left half of bottom-edge IOBs (Left to Right)

3-states output pins

while enabling the

Bypass Register

GCLK1

GCLK0

Right half of bottom-edge IOBs (Left to Right)

JSTART

01100

Clock the start-up

sequence when

StartupClk is TCK

DONE

PROG

Right-edge IOBs (Bottom to Top)

(TDI end)

CCLK

BYPASS

11111

Enables BYPASS

990602001

RESERVED

All other

codes

Xilinx reserved

instructions

Figure 12: Boundary Scan Bit Sequence

BSDL (Boundary Scan Description Language) files for Vir-

tex-E Series devices are available on the Xilinx web site in

the File Download area.

Data Registers

The primary data register is the boundary scan register. For

each IOB pin in the FPGA, bonded or not, it includes three

bits for In, Out, and 3-State Control. Non-IOB pins have

appropriate partial bit population if input-only or output-only.

Identification Registers

The IDCODE register is supported. By using the IDCODE,

the device connected to the JTAG port can be determined.

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The IDCODE register has the following binary format:

vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1

where

location constraints to guide their placement. They help

ensure optimal implementation of common functions.

For HDL design entry, the Xilinx FPGA Foundation develop-

ment system provides interfaces to the following synthesis

design environments.

v = the die version number

f = the family code (05 for Virtex-E family)

a = the number of CLB rows (ranges from 48 for

XQV600E to 80 for XQV2000E)

•

Synopsys (FPGA Compiler, FPGA Express)

Exemplar (Spectrum)

Synplicity (Synplify)

c = the company code (49h for Xilinx)

For schematic design entry, the Xilinx FPGA Foundation

and Alliance development system provides interfaces to the

following schematic-capture design environments.

The USERCODE register is supported. By using the USER-

CODE, a user-programmable identification code can be

loaded and shifted out for examination. The identification

code (see Table 7) is embedded in the bitstream during bit-

stream generation and is valid only after configuration.

•

Mentor Graphics V8 (Design Architect, QuickSim II)

Viewlogic Systems (Viewdraw)

Third-party vendors support many other environments.

Table 7: IDCODEs Assigned to Virtex-E FPGAs

A standard interface-file specification, Electronic Design

Interchange Format (EDIF), simplifies file transfers into and

out of the development system.

FPGA

IDCODE

XCV600E

XCV1000E

XCV2000E

v0A30093h

v0A40093h

v0A50093h

Virtex-E FPGAs are supported by a unified library of stan-

dard functions. This library contains over 400 primitives and

macros, ranging from 2-input AND gates to 16-bit accumu-

lators, and includes arithmetic functions, comparators,

counters, data registers, decoders, encoders, I/O functions,

latches, Boolean functions, multiplexers, shift registers, and

barrel shifters.

Note:

Attempting to load an incorrect bitstream causes

configuration to fail and can damage the device.

The "soft macro" portion of the library contains detailed

descriptions of common logic functions, but does not con-

tain any partitioning or placement information. The perfor-

mance of these macros depends, therefore, on the

partitioning and placement obtained during implementation.

Including Boundary Scan in a Design

Since the boundary scan pins are dedicated, no special ele-

ment needs to be added to the design unless an internal

data register (USER1 or USER2) is desired.

If an internal data register is used, insert the boundary scan

symbol and connect the necessary pins as appropriate.

RPMs, on the other hand, do contain predetermined parti-

tioning and placement information that permits optimal

implementation of these functions. Users can create their

own library of soft macros or RPMs based on the macros

and primitives in the standard library.

Development System

Virtex-E FPGAs are supported by the Xilinx Foundation and

Alliance Series CAE tools. The basic methodology for Vir-

tex-E design consists of three interrelated steps: design

entry, implementation, and verification. Industry-standard

tools are used for design entry and simulation (for example,

Synopsys FPGA Express), while Xilinx provides proprietary

architecture-specific tools for implementation.

The design environment supports hierarchical design entry,

with high-level schematics that comprise major functional

blocks, while lower-level schematics define the logic in

these blocks. These hierarchical design elements are auto-

matically combined by the implementation tools. Different

design entry tools can be combined within a hierarchical

design, thus allowing the most convenient entry method to

be used for each portion of the design.

The Xilinx development system is integrated under the Xil-

inx Design Manager (XDM™) software, providing designers

with a common user interface regardless of their choice of

entry and verification tools. The XDM software simplifies the

selection of implementation options with pull-down menus

and on-line help.

Design Implementation

The place-and-route tools (PAR) automatically provide the

implementation flow described in this section. The parti-

tioner takes the EDIF net list for the design and maps the

logic into the architectural resources of the FPGA (CLBs

and IOBs, for example). The placer then determines the

best locations for these blocks based on their interconnec-

tions and the desired performance. Finally, the router inter-

connects the blocks.

Application programs ranging from schematic capture to

Placement and Routing (PAR) can be accessed through the

XDM software. The program command sequence is gener-

ated prior to execution, and stored for documentation.

Several advanced software features facilitate Virtex-E design.

RPMs, for example, are schematic-based macros with relative

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The PAR algorithms support fully automatic implementation

of most designs. For demanding applications, however, the

user can exercise various degrees of control over the pro-

cess. User partitioning, placement, and routing information

is optionally specified during the design-entry process. The

implementation of highly structured designs can benefit

greatly from basic floor planning.

Design Verification

In addition to conventional software simulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

devices are infinitely reprogrammable, designs can be veri-

fied in real time without the need for extensive sets of soft-

ware simulation vectors.

The development system supports both software simulation

and in-circuit debugging techniques. For simulation, the

system extracts the post-layout timing information from the

design database, and back-annotates this information into

the net list for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

®

The implementation software incorporates Timing Wizard

timing-driven placement and routing. Designers specify tim-

ing requirements along entire paths during design entry.

The timing path analysis routines in PAR then recognize

these user-specified requirements and accommodate them.

®

Timing requirements are entered on a schematic in a form

directly relating to the system requirements, such as the tar-

geted clock frequency, or the maximum allowable delay

between two registers. In this way, the overall performance

of the system along entire signal paths is automatically tai-

lored to user-generated specifications. Specific timing infor-

mation for individual nets is unnecessary.

TRCE static timing analyzer.

For in-circuit debugging, an optional download and read-

back cable is available. This cable connects the FPGA in the

target system to a PC or workstation. After downloading the

design into the FPGA, the designer can single-step the

logic, readback the contents of the flip-flops, and so observe

the internal logic state. Simple modifications can be down-

loaded into the system in a matter of minutes.

Configuration

Virtex-E devices are configured by loading configuration

data into the internal configuration memory. Note that

attempting to load an incorrect bitstream causes configura-

tion to fail and can damage the device.

Note that some configuration pins can act as outputs. For

correct operation, these pins require a V

of 3.3 V or

CCO

2.5 V. At 3.3 V the pins operate as LVTTL, and at 2.5 V they

operate as LVCMOS. All affected pins fall in banks 2 or 3.

The configuration pins needed for SelectMap (CS, Write)

are located in bank 1.

Some of the pins used for configuration are dedicated pins,

while others can be re-used as general purpose inputs and

outputs once configuration is complete.

Configuration Modes

Virtex-E supports the following four configuration modes.

The following are dedicated pins:

•

Mode pins (M2, M1, M0)

Configuration clock pin (CCLK)

PROGRAM pin

•

Slave-serial mode

Master-serial mode

SelectMAP mode

DONE pin

Boundary-scan mode (JTAG)

Boundary-scan pins (TDI, TDO, TMS, TCK)

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Table 8.

Depending on the configuration mode chosen, CCLK can

be an output generated by the FPGA, or can be generated

externally and provided to the FPGA as an input. The

PROGRAM pin must be pulled High prior to reconfiguration.

Table 8: Configuration Codes

Configuration Mode

Master-serial mode

Boundary-scan mode

SelectMAP mode

M2 M1 M0 CCLK Direction Data Width Serial D

Configuration Pull-ups

out

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Out

N/A

In

1

8

1

8

1

Yes

No

Slave-serial mode

Master-serial mode

Boundary-scan mode

SelectMAP mode

In

Yes

No

Out

N/A

In

Yes

No

Slave-serial mode

In

Yes

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Configuration through the boundary-scan port is always

available, independent of the mode selection. Selecting the

boundary-scan mode simply turns off the other modes. The

three mode pins have internal pull-up resistors, and default

to a logic High if left unconnected. However, it is recom-

mended to drive the configuration mode pins externally.

Multiple FPGAs can be daisy-chained for configuration from

a single source. After a particular FPGA has been config-

ured, the data for the next device is routed to the DOUT pin.

The data on the DOUT pin changes on the rising edge of

CCLK.

The change of DOUT on the rising edge of CCLK differs

from previous families, but does not cause a problem for

mixed configuration chains. This change was made to

improve serial configuration rates for Virtex and Virtex-E

only chains.

Table 9 lists the total number of bits required to configure

each device.

Table 9: Virtex-E Bitstream Lengths

Device

# of Configuration Bits

3,961,632

Figure 13 shows a full master/slave system. A Virtex-E

device in slave-serial mode should be connected as shown

in the right-most device.

XQV600E

XQV1000E

XQV2000E

6,587,520

Slave-serial mode is selected by applying <111>or <011>

to the mode pins (M2, M1, M0). A weak pull-up on the mode

pins makes slave serial the default mode if the pins are left

unconnected. However, it is recommended to drive the con-

figuration mode pins externally. Figure 14 shows slave-

serial mode programming switching characteristics.

10,159,648

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data

in bit-serial form from a serial PROM or other source of

serial configuration data. The serial bitstream must be set

up at the DIN input pin a short time before each rising edge

of an externally generated CCLK.

Table 10 provides more detail about the characteristics

shown in Figure 14. Configuration must be delayed until the

INIT pins of all daisy-chained FPGAs are High.

For more detailed information on serial PROMs, see the

PROM data sheet at http://www.xilinx.com/bvdocs/publi-

cations/ds082.pdf.

Table 10: Master/Slave Serial Mode Programming Switching

Values

Figure

Description

DIN setup/hold, slave mode

References

Symbol

min

max

Units

ns

1/2

3

T

/ T

5.0 / 0.0

-

DCC

CCD

DIN setup/hold, master mode

T

/ T

ns

DSCK

CKDS

DOUT

T

12.0

-

ns

CCO

CCH

High time

CCLK

4

5.0

-

ns

Low time

5

T

-

ns

CCL

Maximum Frequency

-

F

66

+45

MHz

%

CC

Frequency Tolerance, master mode with respect to nominal

-

–30

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.

N/C

3.3V

330 Ω

M0 M1

M2

M0 M1

M2

N/C

DOUT

VIRTEX-E

DIN

DOUT

CCLK

MASTER

SERIAL

VIRTEX-E,

XC4000XL,

SLAVE

XC1701L

CLK

CCLK

DIN

DATA

CE

Optional Pull-up

Resistor on Done

1

PROGRAM

DONE

PROGRAM

DONE

CEO

INIT

RESET/OE

(Low Reset Option Used)

PROGRAM

Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor

of 330 Ω should be added to the common DONE line. (For Spartan-XL devices, add a 4.7K Ω

pull-up resistor.) This pull-up is not needed if the DriveDONE attribute is set. If used,

DriveDONE should be selected only for the last device in the configuration chain.

XCVE_ds_013_050103

Figure 13: Master/Slave Serial Mode Circuit Diagram

DIN

1

2

5

T

DCC

T

CCD

CCL

CCLK

4

T

CCH

3

T

CCO

DOUT

(Output)

X5379_a

Figure 14: Slave-Serial Mode Programming Switching Characteristics

quency that can be selected is 60 MHz. When selecting a

Master-Serial Mode

CCLK frequency, ensure that the serial PROM and any

daisy-chained FPGAs are fast enough to support the clock

rate.

In master-serial mode, the CCLK output of the FPGA drives

a Xilinx Serial PROM that feeds bit-serial data to the DIN

input. The FPGA accepts this data on each rising CCLK

edge. After the FPGA has been loaded, the data for the next

device in a daisy-chain is presented on the DOUT pin after

the rising CCLK edge.

On power-up, the CCLK frequency is approximately

2.5 MHz. This frequency is used until the ConfigRate bits

have been loaded when the frequency changes to the

selected ConfigRate. Unless a different frequency is speci-

fied in the design, the default ConfigRate is 4 MHz.

The interface is identical to slave-serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK, which always starts at a slow default frequency. Con-

figuration bits then switch CCLK to a higher frequency for

the remainder of the configuration. Switching to a lower fre-

quency is prohibited.

In a full master/slave system (Figure 13), the left-most

device operates in master-serial mode. The remaining

devices operate in slave-serial mode. The SPROM RESET

pin is driven by INIT, and the CE input is driven by DONE.

There is the potential for contention on the DONE pin,

depending on the start-up sequence options chosen.

The CCLK frequency is set using the ConfigRate option in

the bitstream generation software. The maximum CCLK fre-

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The sequence of operations necessary to configure a

Virtex-E FPGA serially appears in Figure 15.

Apply Power

FPGA starts to clear

configuration memory.

Set PROGRAM = High

FPGA makes a final

clearing pass and releases

If used to delay

Release INIT

INIT when finished.

configuration

Low

INIT?

High

Load a Configuration Bit

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

No

End of

Bitstream?

If no CRC errors found,

FPGA enters start-up phase

causing DONE to go High.

Yes

Configuration Completed

ds009_15_111799

Figure 15: Serial Configuration Flowchart

Figure 16 shows the timing of master-serial configuration. Master-serial mode is selected by a <000> or <100> on the mode

pins (M2, M1, M0). Table 10 shows the timing information for Figure 16.

CCLK

(Output)

T

2

CKDS

T

1

DSCK

Serial Data In

Serial DOUT

(Output)

DS022_44_071201

Figure 16: Master-Serial Mode Programming Switching Characteristics

At power-up, V

than 50 ms, otherwise delay configuration by pulling PRO-

GRAM Low until V is valid.

must rise from 1.0 V to V

Min in less

Retention of the SelectMAP port is selectable on a design-

by-design basis when the bitstream is generated. If reten-

tion is selected, PROHIBIT constraints are required to pre-

vent the SelectMAP-port pins from being used as user I/O.

CC

SelectMAP Mode

Multiple Virtex-E FPGAs can be configured using the

SelectMAP mode, and be made to start-up simultaneously.

To configure multiple devices in this way, wire the individual

CCLK, Data, WRITE, and BUSY pins of all the devices in

parallel. The individual devices are loaded separately by

asserting the CS pin of each device in turn and writing the

appropriate data. See Table 11 for SelectMAP Write Timing

Characteristics.

The SelectMAP mode is the fastest configuration option.

Byte-wide data is written into the FPGA with a BUSY flag

controlling the flow of data.

An external data source provides a byte stream, CCLK, a

Chip Select (CS) signal and a Write signal (WRITE). If

BUSY is asserted (High) by the FPGA, the data must be

held until BUSY goes Low.

Data can also be read using the SelectMAP mode. If

WRITE is not asserted, configuration data is read out of the

FPGA as part of a readback operation.

Write

Write operations send packets of configuration data into the

FPGA. The sequence of operations for a multi-cycle write

operation is shown below. Note that a configuration packet

can be split into many such sequences. The packet does

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained to permit high-speed 8-bit readback.

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not have to complete within one assertion of CS, illustrated

in Figure 17.

and WRITE is High. Similarly, while WRITE is High, no

more that one CS should be asserted.

3. At the rising edge of CCLK: If BUSY is Low, the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance instead

occurs on the first clock after BUSY goes Low, and the

data must be held until this has happened.

1. Assert WRITE and CS Low. Note that when CS is

asserted on successive CCLKs, WRITE must remain

either asserted or de-asserted. Otherwise, an abort is

initiated, as described below.

2. Drive data onto D[7:0]. Note that to avoid contention,

the data source should not be enabled while CS is Low

4. Repeat steps 2 and 3 until all the data has been sent.

5. De-assert CS and WRITE.

Table 11: SelectMAP Write Timing Characteristics

Description

Symbol

/T

SMDCC SMCCD

Units

ns, min

D

Setup/Hold

1/2

3/4

5/6

7

T

5.0 / 1.7

7.0 / 1.7

12.0

0-7

CS Setup/Hold

T

/T

ns, min

SMCSCC SMCCCS

WRITE Setup/Hold

T

/T

ns, min

SMCCW SMWCC

CCLK

BUSY Propagation Delay

Maximum Frequency

T

ns, max

MHz, max

SMCKBY

F

66

CC

Maximum Frequency with no handshake

F

50

CCNH

CCLK

3

4

CS

5

6

WRITE

1

2

DATA[0:7]

BUSY

7

No Write

Write

No Write

Write

DS022_45_071702

Figure 17: Write Operations

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A flowchart for the write operation is shown in Figure 18.

Apply Power

Note that if CCLK is slower than f

, the FPGA never

CCNH

FPGA starts to clear

configuration memory.

asserts BUSY, In this case, the above handshake is unnec-

essary, and data can simply be entered into the FPGA every

CCLK cycle.

PROGRAM

from Low

to High

No

Abort

FPGA makes a final

clearing pass and releases

INIT when finished.

Yes

If used to delay

Release INIT

During a given assertion of CS, the user cannot switch from

a write to a read, or vice-versa. This action causes the cur-

rent packet command to be aborted. The device remains

BUSY until the aborted operation has completed. Following

an abort, data is assumed to be unaligned to word bound-

aries, and the FPGA requires a new synchronization word

prior to accepting any new packets.

configuration

Low

INIT?

High

Set WRITE = Low

Enter Data Source

Sequence A

On first FPGA

To initiate an abort during a write operation, de-assert

WRITE. At the rising edge of CCLK, an abort is initiated, as

shown in Figure 19.

Set CS = Low

Apply Configuration Byte

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

High

Busy?

Low

No

End of Data?

Yes

If no errors,

first FPGAs enter start-up phase

releasing DONE.

On first FPGA

Set CS = High

If no errors,

later FPGAs enter start-up phase

releasing DONE.

For any other FPGAs

Repeat Sequence A

Disable Data Source

Set WRITE = High

When all DONE pins

are released, DONE goes High

and start-up sequences complete.

Configuration Completed

ds003_17_090602

Figure 18: SelectMAP Flowchart for Write Operations

CCLK

CS

WRITE

DATA[0:7]

BUSY

Abort

DS022_46_071702

Figure 19: SelectMAP Write Abort Waveforms

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7. Clock TCK through the startup sequence.

8. Return to RTI.

Boundary-Scan Mode

In the boundary-scan mode, configuration is done through

the IEEE 1149.1 Test Access Port. Note that the PROGRAM

pin must be pulled High prior to reconfiguration. A Low on

the PROGRAM pin resets the TAP controller and no JTAG

operations can be performed.

Configuration and readback via the TAP is always available.

The boundary-scan mode is selected by a <101>or <001>

on the mode pins (M2, M1, M0). For details on TAP charac-

teristics, refer to XAPP139.

Configuration through the TAP uses the CFG_IN instruc-

tion. This instruction allows data input on TDI to be con-

verted into data packets for the internal configuration bus.

Configuration Sequence

The configuration of Virtex-E devices is a three-phase pro-

cess. First, the configuration memory is cleared. Next, con-

figuration data is loaded into the memory, and finally, the

logic is activated by a start-up process.

The following steps are required to configure the FPGA

through the boundary-scan port (when using TCK as a

start-up clock).

Configuration is automatically initiated on power-up unless

it is delayed by the user, as described below. The configura-

tion process can also be initiated by asserting PROGRAM.

The end of the memory-clearing phase is signalled by INIT

going High, and the completion of the entire process is sig-

nalled by DONE going High.

1. Load the CFG_IN instruction into the boundary-scan

instruction register (IR).

2. Enter the Shift-DR (SDR) state.

3. Shift a configuration bitstream into TDI.

4. Return to Run-Test-Idle (RTI).

5. Load the JSTART instruction into IR.

6. Enter the SDR state.

The power-up timing of configuration signals is shown in

Figure 20.

Vcc

TPOR

PROGRAM

TPL

INIT

TICCK

CCLK OUTPUT or INPUT

M0, M1, M2

(Required)

VALI

ds022_020_071201

Figure 20: Power-Up Timing Configuration Signals

The corresponding timing characteristics are listed in Table 12.

Table 12: Power-up Timing Characteristics

Value

min

Figure

Reference

Description

Symbol

max

2.0

Units

ms

µs

1

Power-on Reset

20

-

T

-

POR

Program Latency

CCLK (output) Delay

Program Pulse Width

T

100.0

4.0

PL

T

0.5

300

µs

ICCK

T

-

ns

PROGRAM

Notes:

1. T_PORdelay is the initialization time required after V_CCINTand V_CCOin Bank 2 reach the recommended operating

voltage.

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released. This permits device outputs to turn on as neces-

sary.

Delaying Configuration

INIT can be held Low using an open-drain driver. An open-

drain is required since INIT is a bidirectional open-drain pin

that is held Low by the FPGA while the configuration mem-

ory is being cleared. Extending the time that the pin is Low

causes the configuration sequencer to wait. Thus, configu-

ration is delayed by preventing entry into the phase where

data is loaded.

One CCLK cycle later, the Global Set/Reset (GSR) and Glo-

bal Write Enable (GWE) signals are released. This permits

the internal storage elements to begin changing state in

response to the logic and the user clock.

The relative timing of these events can be changed. In addi-

tion, the GTS, GSR, and GWE events can be made depen-

dent on the DONE pins of multiple devices all going High,

forcing the devices to start synchronously. The sequence

can also be paused at any stage until lock has been

achieved on any or all DLLs.

Start-Up Sequence

The default Start-up sequence is that one CCLK cycle after

DONE goes High, the global 3-state signal (GTS) is

Readback

The configuration data stored in the Virtex-E configuration

memory can be readback for verification. Along with the

configuration data it is possible to readback the contents all

flip-flops/latches, LUT RAMs, and block RAMs. This capa-

bility is used for real-time debugging. For more detailed

information, see application note XAPP138 "Virtex FPGA

Series Configuration and Readback".

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Design Considerations

This section contains more detailed design information on

the following features.

In order to guarantee the system clock establishes prior to

the device "waking up," the DLL can delay the completion of

the device configuration process until after the DLL

achieves lock.

•

Delay-Locked Loop . . . see page 19

BlockRAM . . . see page 23

SelectIO . . . see page 30

By taking advantage of the DLL to remove on-chip clock

delay, the designer can greatly simplify and improve system

level design involving high-fanout, high-performance clocks.

Using DLLs

The Virtex-E FPGA series provides up to eight fully digital

dedicated on-chip Delay-Locked Loop (DLL) circuits which

provide zero propagation delay, low clock skew between

output clock signals distributed throughout the device, and

advanced clock domain control. These dedicated DLLs can

be used to implement several circuits which improve and

simplify system level design.

Library DLL Symbols

Figure 21 shows the simplified Xilinx library DLL macro

symbol, BUFGDLL. This macro delivers a quick and effi-

cient way to provide a system clock with zero propagation

delay throughout the device. Figure 22 and Figure 23 show

the two library DLL primitives. These symbols provide

access to the complete set of DLL features when imple-

menting more complex applications.

Introduction

As FPGAs grow in size, quality on-chip clock distribution

becomes increasingly important. Clock skew and clock

delay impact device performance and the task of managing

clock skew and clock delay with conventional clock trees

becomes more difficult in large devices. The Virtex-E series

of devices resolve this potential problem by providing up to

eight fully digital dedicated on-chip DLL circuits, which pro-

vide zero propagation delay and low clock skew between

output clock signals distributed throughout the device.

I

O

0ns

ds022_25_121099

Figure 21: Simplified DLL Macro Symbol BUFGDLL

CLKDLL

Each DLL can drive up to two global clock routing networks

within the device. The global clock distribution network min-

imizes clock skews due to loading differences. By monitor-

ing a sample of the DLL output clock, the DLL can

compensate for the delay on the routing network, effectively

eliminating the delay from the external input port to the indi-

vidual clock loads within the device.

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

RST

In addition to providing zero delay with respect to a user

source clock, the DLL can provide multiple phases of the

source clock. The DLL can also act as a clock doubler or it

can divide the user source clock by up to 16.

ds022_26_121099

Figure 22: Standard DLL Symbol CLKDLL

Clock multiplication gives the designer a number of design

alternatives. For instance, a 50 MHz source clock doubled

by the DLL can drive an FPGA design operating at 100

MHz. This technique can simplify board design because the

clock path on the board no longer distributes such a high-

speed signal. A multiplied clock also provides designers the

option of time-domain-multiplexing, using one circuit twice

per clock cycle, consuming less area than two copies of the

same circuit. Two DLLs in can be connected in series to

increase the effective clock multiplication factor to four.

CLKDLLHF

CLKIN

CLKFB

CLK0

CLK180

CLKDV

RST

LOCKED

ds022_027_121099

The DLL can also act as a clock mirror. By driving the DLL

output off-chip and then back in again, the DLL can be used

to de-skew a board level clock between multiple devices.

Figure 23: High Frequency DLL Symbol CLKDLLHF

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DLLs. This makes a total of eight usable input pins for DLLs

in the Virtex-E family.

BUFGDLL Pin Descriptions

Use the BUFGDLL macro as the simplest way to provide

zero propagation delay for a high-fanout on-chip clock from

an external input. This macro uses the IBUFG, CLKDLL and

BUFG primitives to implement the most basic DLL applica-

tion as shown in Figure 24.

Feedback Clock Input — CLKFB

The DLL requires a reference or feedback signal to provide

the delay-compensated output. Connect only the CLK0 or

CLK2X DLL outputs to the feedback clock input (CLKFB)

pin to provide the necessary feedback to the DLL. The feed-

back clock input can also be provided through one of the fol-

lowing pins.

IBUFG

BUFG

CLKDLL

I

O

I

O

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

IBUFG - Global Clock Input Pad

CLK2X

IO_LVDS_DLL - the pin adjacent to IBUF

CLKDV

LOCKED

RST

If an IBUFG sources the CLKFB pin, the following special

rules apply.

ds022_28_121099

1. An external input port must source the signal that drives

the IBUFG I pin.

Figure 24: BUFGDLL Schematic

This symbol does not provide access to the advanced clock

domain controls or to the clock multiplication or clock divi-

sion features of the DLL. This symbol also does not provide

access to the RST, or LOCKED pins of the DLL. For access

to these features, a designer must use the library DLL prim-

itives described in the following sections.

2. The CLK2X output must feedback to the device if both

the CLK0 and CLK2X outputs are driving off chip

devices.

3. That signal must directly drive only OBUFs and nothing

else.

These rules enable the software determine which DLL clock

output sources the CLKFB pin.

Source Clock Input — I

The I pin provides the user source clock, the clock signal on

which the DLL operates, to the BUFGDLL. For the BUF-

GDLL macro the source clock frequency must fall in the low

frequency range as specified in the data sheet. The BUF-

GDLL requires an external signal source clock. Therefore,

only an external input port can source the signal that drives

the BUFGDLL I pin.

Reset Input — RST

When the reset pin RST activates the LOCKED signal deac-

tivates within four source clock cycles. The RST pin, active

High, must either connect to a dynamic signal or tied to

ground. As the DLL delay taps reset to zero, glitches can

occur on the DLL clock output pins. Activation of the RST

pin can also severely affect the duty cycle of the clock out-

put pins. Furthermore, the DLL output clocks no longer de-

skew with respect to one another. For these reasons, rarely

use the reset pin unless re-configuring the device or chang-

ing the input frequency.

Clock Output — O

The clock output pin O represents a delay-compensated

version of the source clock (I) signal. This signal, sourced by

a global clock buffer BUFG symbol, takes advantage of the

dedicated global clock routing resources of the device.

2x Clock Output — CLK2X

The output clock has a 50-50 duty cycle unless you deacti-

vate the duty cycle correction property.

The output pin CLK2X provides a frequency-doubled clock

with an automatic 50/50 duty-cycle correction. Until the

CLKDLL has achieved lock, the CLK2X output appears as a

1x version of the input clock with a 25/75 duty cycle. This

behavior allows the DLL to lock on the correct edge with

respect to source clock. This pin is not available on the

CLKDLLHF primitive.

CLKDLL Primitive Pin Descriptions

The library CLKDLL primitives provide access to the com-

plete set of DLL features needed when implementing more

complex applications with the DLL.

Source Clock Input — CLKIN

Clock Divide Output — CLKDV

The CLKIN pin provides the user source clock (the clock

signal on which the DLL operates) to the DLL. The CLKIN

frequency must fall in the ranges specified in the data sheet.

A global clock buffer (BUFG) driven from another CLKDLL,

one of the global clock input buffers (IBUFG), or an

IO_LVDS_DLL pin on the same edge of the device (top or

bottom) must source this clock signal. There are four

IO_LVDS_DLL input pins that can be used as inputs to the

The clock divide output pin CLKDV provides a lower fre-

quency version of the source clock. The CLKDV_DIVIDE

property controls CLKDV such that the source clock is

divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.

This feature provides automatic duty cycle correction such

that the CLKDV output pin always has a 50/50 duty cycle,

with the exception of noninteger divides in HF mode, where

the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.

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The DLL clock outputs can drive an OBUF, a BUFG, or they

can route directly to destination clock pins. The DLL clock

outputs can only drive the BUFGs that reside on the same

edge (top or bottom).

1x Clock Outputs — CLK[0|90|180|270]

The 1x clock output pin CLK0 represents a delay-compen-

sated version of the source clock (CLKIN) signal. The

CLKDLL primitive provides three phase-shifted versions of

the CLK0 signal while CLKDLLHF provides only the 180

phase-shifted version. The relationship between phase shift

and the corresponding period shift appears in Table 13.

Locked Output — LOCKED

To achieve lock, the DLL might need to sample several thou-

sand clock cycles. After the DLL achieves lock, the

LOCKED signal activates. The DLL timing parameter sec-

tion of the data sheet provides estimates for locking times.

Table 13: Relationship of Phase-Shifted Output Clock

to Period Shift

To guarantee that the system clock is established prior to

the device "waking up," the DLL can delay the completion of

the device configuration process until after the DLL locks.

The STARTUP_WAIT property activates this feature.

Phase (degrees)

Period Shift (percent)

0

0%

90

25%

50%

75%

Until the LOCKED signal activates, the DLL output clocks

are not valid and can exhibit glitches, spikes, or other spuri-

ous movement. In particular the CLK2X output appears as a

1x clock with a 25/75 duty cycle.

180

270

The timing diagrams in Figure 25 illustrate the DLL clock

output characteristics.

DLL Properties

Properties provide access to some of the Virtex-E series

DLL features, (for example, clock division and duty cycle

correction).

0

90 180 270

0

90 180 270

t

Duty Cycle Correction Property

CLKIN

CLK2X

The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,

use the duty-cycle corrected default, exhibiting a 50/50 duty

cycle. The DUTY_CYCLE_CORRECTION property (by

default TRUE) controls this feature. To deactivate the DLL

duty-cycle correction for the 1x clock outputs, attach the

DUTY_CYCLE_CORRECTION=FALSE property to the

DLL symbol.

CLKDV_DIVIDE=2

CLKDV

DUTY_CYCLE_CORRECTION=FALSE

CLK0

Clock Divide Property

CLK90

CLK180

CLK270

The CLKDV_DIVIDE property specifies how the signal on

the CLKDV pin is frequency divided with respect to the

CLK0 pin. The values allowed for this property are 1.5, 2,

2.5, 3, 4, 5, 8, or 16; the default value is 2.

DUTY_CYCLE_CORRECTION=TRUE

Startup Delay Property

CLK0

This property, STARTUP_WAIT, takes on a value of TRUE

or FALSE (the default value). When TRUE the device con-

figuration DONE signal waits until the DLL locks before

going to High.

CLK90

CLK180

CLK270

Virtex-E DLL Location Constraints

ds022_29_121099

As shown in Figure 26, there are four additional DLLs in the

Virtex-E devices, for a total of eight per Virtex-E device.

These DLLs are located in silicon, at the top and bottom of

the two innermost block SelectRAM columns. The location

constraint LOC, attached to the DLL symbol with the identi-

fier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,

or DLL3P, controls the DLL location.

Figure 25: DLL Output Characteristics

The DLL provides duty cycle correction on all 1x clock out-

puts such that all 1x clock outputs by default have a 50/50

duty cycle. The DUTY_CYCLE_CORRECTION property

(TRUE by default), controls this feature. In order to deacti-

vate the DLL duty cycle correction, attach the

DUTY_CYCLE_CORRECTION=FALSE property to the

DLL symbol. When duty cycle correction deactivates, the

output clock has the same duty cycle as the source clock.

The LOC property uses the following form:

LOC = DLL0P

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In a similar manner, a phase shift of the input clock is also

possible. The phase shift propagates to the output one to

four clocks after the original shift, with no disruption to the

CLKDLL control.

DLL-3S DLL-3P

DLL-2P DLL-2S

B

R

A

B

R

A

B

R

A

B

R

A

Output Clocks

M

As mentioned earlier in the DLL pin descriptions, some

restrictions apply regarding the connectivity of the output

pins. The DLL clock outputs can drive an OBUF, a global

clock buffer BUFG, or they can route directly to destination

clock pins. The only BUFGs that the DLL clock outputs can

drive are the two on the same edge of the device (top or bot-

tom). In addition, the CLK2X output of the secondary DLL

can connect directly to the CLKIN of the primary DLL in the

same quadrant.

Bottom Right

Half Edge

DLL-1S DLL-1P

DLL-0P DLL-0S

x132_14_100799

Figure 26: Virtex Series DLLs

Design Factors

Use the following design considerations to avoid pitfalls and

improve success designing with Xilinx devices.

Do not use the DLL output clock signals until after activation

of the LOCKED signal. Prior to the activation of the

LOCKED signal, the DLL output clocks are not valid and

can exhibit glitches, spikes, or other spurious movement.

Input Clock

The output clock signal of a DLL, essentially a delayed ver-

sion of the input clock signal, reflects any instability on the

input clock in the output waveform. For this reason the qual-

ity of the DLL input clock relates directly to the quality of the

output clock waveforms generated by the DLL. The DLL

input clock requirements are specified in the data sheet.

Useful Application Examples

The Virtex-E DLL can be used in a variety of creative and

useful applications. The following examples show some of

the more common applications. The Verilog and VHDL

example files are available at:

In most systems a crystal oscillator generates the system

clock. The DLL can be used with any commercially available

quartz crystal oscillator. For example, most crystal oscilla-

tors produce an output waveform with a frequency tolerance

of 100 PPM, meaning 0.01 percent change in the clock

period. The DLL operates reliably on an input waveform with

a frequency drift of up to 1 ns — orders of magnitude in

excess of that needed to support any crystal oscillator in the

industry. However, the cycle-to-cycle jitter must be kept to

less than 300 ps in the low frequencies and 150 ps for the

high frequencies.

ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip

Standard Usage

The circuit shown in Figure 27 resembles the BUFGDLL

macro implemented to provide access to the RST and

LOCKED pins of the CLKDLL.

CLKDLL

IBUFG

BUFG

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

Input Clock Changes

CLK2X

Changing the period of the input clock beyond the maximum

drift amount requires a manual reset of the CLKDLL. Failure

to reset the DLL produces an unreliable lock signal and out-

put clock.

CLKDV

LOCKED

OBUF

IBUF

RST

ds022_028_121099

Figure 27: Standard DLL Implementation

It is possible to stop the input clock with little impact to the

DLL. Stopping the clock should be limited to less than

100 µs to keep device cooling to a minimum. The clock

should be stopped during a Low phase, and when restored

the full High period should be seen. During this time,

LOCKED stays High and remains High when the clock is

restored.

Board Level De-skew of Multiple Non-Virtex-E

Devices

The circuit shown in Figure 28 can be used to de-skew a

system clock between a Virtex-E chip and other non-Virtex-

E chips on the same board. This application is commonly

used when the Virtex-E device is used in conjunction with

other standard products such as SRAM or DRAM devices.

While designing the board level route, ensure that the return

net delay to the source equals the delay to the other chips

involved.

When the clock is stopped, one to four more clocks are still

observed as the delay line is flushed. When the clock is

restarted, the output clocks are not observed for one to four

clocks as the delay line is filled. The most common case is

two or three clocks.

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Because any single DLL can access only two BUFGs at

most, any additional output clock signals must be routed

from the DLL in this example on the high speed backbone

routing.

Virtex-E Device

IBUFG

CLKDLL

OBUF

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

The dll_2x files in the xapp132.zip file show the VHDL and

Verilog implementation of this circuit.

IBUFG

CLK2X

Virtex-E 4x Clock

CLKDV

LOCKED

Two DLLs located in the same half-edge (top-left, top-right,

bottom-right, bottom-left) can be connected together, with-

out using a BUFG between the CLKDLLs, to generate a 4x

clock as shown in Figure 30. Virtex-E devices, like the Virtex

devices, have four clock networks that are available for inter-

nal de-skewing of the clock. Each of the eight DLLs have

access to two of the four clock networks. Although all the

DLLs can be used for internal de-skewing, the presence of

two GCLKBUFs on the top and two on the bottom indicate

that only two of the four DLLs on the top (and two of the four

DLLs on the bottom) can be used for this purpose.

RST

CLKDLL

BUFG

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

RST

Non-Virtex-E Chip

CLKDLL-S

IBUFG

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

Other Non_Virtex-E Chips

ds022_029_121099

CLK2X

CLKDV

Figure 28: DLL De-skew of Board Level Clock

INV

RST

LOCKED

Board-level de-skew is not required for low-fanout clock net-

works. It is recommended for systems that have fanout lim-

itations on the clock network, or if the clock distribution chip

cannot handle the load.

CLKDLL-P

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

Do not use the DLL output clock signals until after activation

of the LOCKED signal. Prior to the activation of the

LOCKED signal, the DLL output clocks are not valid and

can exhibit glitches, spikes, or other spurious movement.

BUFG

OBUF

CLK2X

CLKDV

RST

LOCKED

The dll_mirror_1 files in the xapp132.zip file show the

VHDL and Verilog implementation of this circuit.

ds022_031_041901

De-Skew of Clock and Its 2x Multiple

Figure 30: DLL Generation of 4x Clock in Virtex-E

The circuit shown in Figure 29 implements a 2x clock multi-

plier and also uses the CLK0 clock output with a zero ns

skew between registers on the same chip. Alternatively, a

clock divider circuit can be implemented using similar con-

nections.

Devices

The dll_4xe files in the xapp132.zip file show the DLL imple-

mentation in Verilog for Virtex-E devices. These files can be

found at:

ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip

CLKDLL

IBUFG

BUFG

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

Using Block SelectRAM+ Features

BUFG

OBUF

CLK2X

The Virtex FPGA Series provides dedicated blocks of on-

chip, true dual-read/write port synchronous RAM, with 4096

memory cells. Each port of the block SelectRAM+ memory

can be independently configured as a read/write port, a

read port, a write port, and can be configured to a specific

data width. The block SelectRAM+ memory offers new

capabilities allowing the FPGA designer to simplify designs.

CLKDV

LOCKED

IBUF

RST

ds022_030_121099

Figure 29: DLL De-skew of Clock and 2x Multiple

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Operating Modes

VIrtex-E block SelectRAM+ memory supports two operating

modes:

RAMB4_S#_S#

WEA

ENA

RSTA

CLKA

•

Read Through

Write Back

DOA[#:0]

ADDRA[#:0]

DIA[#:0]

Read Through (one clock edge)

The read address is registered on the read port clock edge

and data appears on the output after the RAM access time.

Some memories might place the latch/register at the out-

puts, depending on whether a faster clock-to-out versus set-

up time is desired. This is generally considered to be an

inferior solution, since it changes the read operation to an

asynchronous function with the possibility of missing an

address/control line transition during the generation of the

read pulse clock.

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

DOB[#:0]

ds022_032_121399

Figure 31: Dual-Port Block SelectRAM+ Memory

Write Back (one clock edge)

RAMB4_S#

The write address is registered on the write port clock edge

and the data input is written to the memory and mirrored on

the output.

WE

EN

RST

CLK

DO[#:0]

ADDR[#:0]

DI[#:0]

Block SelectRAM+ Characteristics

•

All inputs are registered with the port clock and have a

set-up to clock timing specification.

ds022_033_121399

Figure 32: Single-Port Block SelectRAM+ Memory

Table 14: Available Library Primitives

•

All outputs have a read through or write back function

depending on the state of the port WE pin. The outputs

relative to the port clock are available after the clock-to-

out timing specification.

The block SelectRAMs are true SRAM memories and

do not have a combinatorial path from the address to

the output. The LUT SelectRAM+ cells in the CLBs are

still available with this function.

Primitive

RAMB4_S1

Port A Width

Port B Width

•

N/A

1

RAMB4_S1_S1

RAMB4_S1_S2

RAMB4_S1_S4

RAMB4_S1_S8

RAMB4_S1_S16

2

4

1

The ports are completely independent from each other

(i.e., clocking, control, address, read/write function, and

data width) without arbitration.

8

16

•

A write operation requires only one clock edge.

A read operation requires only one clock edge.

RAMB4_S2

N/A

2

4

RAMB4_S2_S2

RAMB4_S2_S4

RAMB4_S2_S8

RAMB4_S2_S16

The output ports are latched with a self timed circuit to guar-

antee a glitch free read. The state of the output port does

not change until the port executes another read or write

operation.

2

4

8

16

RAMB4_S4

N/A

4

8

Library Primitives

Figure 31 and Figure 32 show the two generic library block

SelectRAM+ primitives. Table 14 describes all of the avail-

able primitives for synthesis and simulation.

RAMB4_S4_S4

RAMB4_S4_S8

RAMB4_S4_S16

16

RAMB4_S8

RAMB4_S8_S8

RAMB4_S8_S16

N/A

8

16

8

RAMB4_S16

N/A

16

RAMB4_S16_S16

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Data Output Bus—DO[A|B]<#:0>

Port Signals

The data out bus reflects the contents of the memory cells

referenced by the address bus at the last active clock edge.

During a write operation, the data out bus reflects the data

in bus. The width of this bus equals the width of the port.

The allowed widths appear in Table 15.

Each block SelectRAM+ port operates independently of the

others while accessing the same set of 4096 memory cells.

Table 15 describes the depth and width aspect ratios for the

block SelectRAM+ memory.

Table 15: Block SelectRAM+ Port Aspect Ratios

Inverting Control Pins

The four control pins (CLK, EN, WE and RST) for each port

have independent inversion control as a configuration

option.

Width

Depth

4096

2048

1024

512

ADDR Bus

ADDR<11:0>

ADDR<10:0>

ADDR<9:0>

ADDR<8:0>

ADDR<7:0>

Data Bus

DATA<0>

1

2

DATA<1:0>

DATA<3:0>

DATA<7:0>

DATA<15:0>

4

Address Mapping

Each port accesses the same set of 4096 memory cells

using an addressing scheme dependent on the width of the

port.

8

16

256

The physical RAM location addressed for a particular width

are described in the following formula (of interest only when

the two ports use different aspect ratios).

Clock—CLK[A|B]

Each port is fully synchronous with independent clock pins.

All port input pins have setup time referenced to the port

CLK pin. The data output bus has a clock-to-out time refer-

enced to the CLK pin.

Start = ((ADDR

+1) * Width ) –1

port

End = ADDR

* Width

port

Table 16 shows low order address mapping for each port

width.

Enable—EN[A|B]

The enable pin affects the read, write and reset functionality

of the port. Ports with an inactive enable pin keep the output

pins in the previous state and do not write data to the mem-

ory cells.

Table 16: Port Address Mapping

Port

Width

Addresses

Write Enable—WE[A|B]

1

4095...

1

5

1

4

1

3

1

2

1

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Activating the write enable pin allows the port to write to the

memory cells. When active, the contents of the data input

bus are written to the RAM at the address pointed to by the

address bus, and the new data also reflects on the data out

bus. When inactive, a read operation occurs and the con-

tents of the memory cells referenced by the address bus

reflect on the data out bus.

2

4

2047...

1023...

511...

07

06

05

04

03

02

01

00

03

02

01

00

8

01

00

16

255...

00

Creating Larger RAM Structures

Reset—RST[A|B]

The block SelectRAM+ columns have specialized routing to

allow cascading blocks together with minimal routing delays.

This achieves wider or deeper RAM structures with a smaller

timing penalty than when using normal routing channels.

The reset pin forces the data output bus latches to zero syn-

chronously. This does not affect the memory cells of the

RAM and does not disturb a write operation on the other

port.

Location Constraints

Address Bus—ADDR[A|B]<#:0>

Block SelectRAM+ instances can have LOC properties

attached to them to constrain the placement. The block

SelectRAM+ placement locations are separate from the

CLB location naming convention, allowing the LOC proper-

ties to transfer easily from array to array.

The address bus selects the memory cells for read or write.

The width of the port determines the required width of this

bus as shown in Table 15.

Data In Bus—DI[A|B]<#:0>

The data in bus provides the new data value to be written

into the RAM. This bus and the port have the same width, as

shown in Table 15.

The LOC properties use the following form.

LOC = RAMB4_R#C#

RAMB4_R0C0 is the upper left RAMB4 location on the

device.

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Dual Port Timing

Conflict Resolution

Figure 34 shows a timing diagram for a true dual-port

read/write block SelectRAM+ memory. The clock on port A

has a longer period than the clock on Port B. The timing

The block SelectRAM+ memory is a true dual-read/write

port RAM that allows simultaneous access of the same

memory cell from both ports. When one port writes to a

given memory cell, the other port must not address that

memory cell (for a write or a read) within the clock-to-clock

setup window. The following lists specifics of port and mem-

ory cell write conflict resolution.

parameter T

, (clock-to-clock set-up) is shown on this

BCCS

diagram. The parameter, T

is violated once in the dia-

BCCS

gram. All other timing parameters are identical to the single

port version shown in Figure 33.

T

is only of importance when the address of both ports

•

If both ports write to the same memory cell

simultaneously, violating the clock-to-clock setup

requirement, consider the data stored as invalid.

If one port attempts a read of the same memory cell

the other simultaneously writes, violating the clock-to-

clock setup requirement, the following occurs.

BCCS

are the same and at least one port is performing a write

operation. When the clock-to-clock set-up parameter is vio-

lated for a WRITE-WRITE condition, the contents of the

memory at that location are invalid. When the clock-to-clock

set-up parameter is violated for a WRITE-READ condition,

the contents of the memory are correct, but the read port

has invalid data.

•

-

The write succeeds

The data out on the writing port accurately reflects

the data written.

At the first rising edge of the CLKA, memory location 0x00 is

to be written with the value 0xAAAA and is mirrored on the

DOA bus. The last operation of Port B was a read to the

same memory location 0x00. The DOB bus of Port B does

not change with the new value on Port A, and retains the

last read value. A short time later, Port B executes another

read to memory location 0x00, and the DOB bus now

reflects the new memory value written by Port A.

-

The data out on the reading port is invalid.

Conflicts do not cause any physical damage.

Single Port Timing

Figure 33 shows a timing diagram for a single port of a block

SelectRAM+ memory. The block SelectRAM+ AC switching

characteristics are specified in the data sheet. The block

SelectRAM+ memory is initially disabled.

At the second rising edge of CLKA, memory location 0x7E

is written with the value 0x9999 and is mirrored on the DOA

bus. Port B then executes a read operation to the same

memory location without violating the T

the DOB reflects the new memory values written by Port A.

At the first rising edge of the CLK pin, the ADDR, DI, EN,

WE, and RST pins are sampled. The EN pin is High and the

WE pin is Low indicating a read operation. The DO bus con-

tains the contents of the memory location, 0x00, as indi-

cated by the ADDR bus.

parameter and

BCCS

At the third rising edge of CLKA, the T parameter is

BCCS

violated with two writes to memory location 0x0F. The DOA

and DOB busses reflect the contents of the DIA and DIB

busses, but the stored value at 0x0F is invalid.

At the second rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN and WE pins

are High indicating a write operation. The DO bus mirrors the

DI bus. The DI bus is written to the memory location 0x0F.

At the fourth rising edge of CLKA, a read operation is per-

formed at memory location 0x0F and invalid data is present

on the DOA bus. Port B also executes a read operation to

memory location 0x0F and also reads invalid data.

At the third rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN pin is High

and the WE pin is Low indicating a read operation. The DO

bus contains the contents of the memory location 0x7E as

indicated by the ADDR bus.

At the fifth rising edge of CLKA a read operation is per-

formed that does not violate the T

parameter to the

BCCS

previous write of 0x7E by Port B. THe DOA bus reflects the

recently written value by Port B.

At the fourth rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN pin is Low

indicating that the block SelectRAM+ memory is now dis-

abled. The DO bus retains the last value.

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T

BPWL

BPWH

CLK

T

BACK

ADDR

00

0F

7E

8F

BDCK

DDDD

CCCC

BBBB

2222

DIN

DOUT

EN

T

BCKO

MEM (00)

CCCC

MEM (7E)

T

BECK

RST

WE

T

BWCK

DISABLED

READ

WRITE

READ

DISABLED

ds022_0343_121399

Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory

T

BCCS

VIOLATION

CLK_A

ADDR_A

00

7E

0F

7E

EN_A

WE_A

DI_A

T

BCCS

T

BCCS

AAAA

9999

AAAA

0000

1111

AAAA

9999

AAAA

UNKNOWN

2222

DO_A

CLK_B

ADDR_B

00

7E

0F

7E

1A

EN_B

WE_B

DI_B

1111

BBBB

1111

2222

FFFF

DO_B

MEM (00)

AAAA

9999

BBBB

UNKNOWN

2222

FFFF

ds022_035_121399

Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory

Initialization

The block SelectRAM+ memory can initialize during the

device configuration sequence. The 16 initialization properties

of 64 hex values each (a total of 4096 bits) set the initialization

of each RAM. These properties appear in Table 17. Any initial-

ization properties not explicitly set configure as zeros. Partial

initialization strings pad with zeros. Initialization strings

greater than 64 hex values generate an error. The RAMs can

be simulated with the initialization values using generics in

VHDL simulators and parameters in Verilog simulators.

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bit wide RAM to be created using a single block

SelectRAM+ cell as shown in Figure 35.

Initialization in VHDL and Synopsys

The block SelectRAM+ structures can be initialized in VHDL

for both simulation and synthesis for inclusion in the EDIF

output file. The simulation of the VHDL code uses a generic

to pass the initialization. Synopsys FPGA compiler does not

presently support generics. The initialization values instead

attach as attributes to the RAM by a built-in Synopsys

dc_script. The translate_off statement stops synthesis

translation of the generic statements. The following code

illustrates a module that employs these techniques.

RAMB4_S16_S16

WE

WEA

ENA

RSTA

CLKA

EN

RST

CLK

DOA[15:0]

DO[31:16]

ADDR[6:0], V

ADDRA[7:0]

DIA[15:0]

CC

DI[31:16]

WE

WEB

ENB

RSTB

EN

RST

DOB[15:0]

DO[15:0]

CLK

CLKB

ADDR[6:0], GND

ADDRB[7:0]

DIB[15:0]

Table 17: RAM Initialization Properties

DI[15:0]

Property

INIT_00

INIT_01

INIT_02

INIT_03

INIT_04

INIT_05

INIT_06

INIT_07

INIT_08

INIT_09

INIT_0a

INIT_0b

INIT_0c

INIT_0d

INIT_0e

INIT_0f

Memory Cells

255 to 0

ds022_036_121399

Figure 35: Single Port 128 x 32 RAM

Interleaving the memory space, setting the LSB of the

address bus of Port A to 1 (V ), and the LSB of the

address bus of Port B to 0 (GND), allows a 32-bit wide sin-

gle port RAM to be created.

511 to 256

767 to 512

CC

1023 to 768

1279 to 1024

1535 to 1280

1791 to 2047

2047 to 1792

2303 to 2048

2559 to 2304

2815 to 2560

3071 to 2816

3327 to 3072

3583 to 3328

3839 to 3584

4095 to 3840

Creating Two Single-Port RAMs

The true dual-read/write port functionality of the block

SelectRAM+ memory allows a single RAM to be split into

two single port memories of 2K bits each as shown in

Figure 36.

RAMB4_S4_S16

WE1

EN1

RST1

WEA

ENA

RSTA

CLKA

ADDRA[9:0]

DIA[3:0]

DOA[3:0]

DO1[3:0]

CLK1

V

, ADDR1[8:0]

DI1[3:0]

CC

WE2

EN2

RST2

CLK2

WEB

ENB

RSTB

CLKB

ADDRB[7:0]

DIB[15:0]

DOB[15:0]

DO2[15:0]

GND, ADDR2[6:0]

DI2[15:0]

ds022_037_121399

Initialization in Verilog and Synopsys

The block SelectRAM+ structures can be initialized in Verilog

for both simulation and synthesis for inclusion in the EDIF

output file. The simulation of the Verilog code uses a def-

param to pass the initialization. The Synopsys FPGA com-

piler does not presently support defparam. The initialization

values instead attach as attributes to the RAM by a built-in

Synopsys dc_script. The translate_off statement stops syn-

thesis translation of the defparam statements. The following

code illustrates a module that employs these techniques.

Figure 36: 512 x 4 RAM and 128 x 16 RAM

In this example, a 512K x 4 RAM (Port A) and a 128 x 16

RAM (Port B) are created out of a single block SelectRAM+.

The address space for the RAM is split by fixing the MSB of

Port A to 1 (V ) for the upper 2K bits and the MSB of Port

CC

B to 0 (GND) for the lower 2K bits.

Block Memory Generation

The CoreGen program generates memory structures using

the block SelectRAM+ features. This program outputs

VHDL or Verilog simulation code templates and an EDIF file

for inclusion in a design.

Design Examples

Creating a 32-bit Single-Port RAM

The true dual-read/write port functionality of the block

SelectRAM+ memory allows a single port, 128 deep by 32-

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VHDL Initialization Example

library IEEE;

use IEEE.std_logic_1164.all;

entity MYMEM is

port (CLK, WE:in std_logic;

ADDR: in std_logic_vector(8 downto 0);

DIN: in std_logic_vector(7 downto 0);

DOUT: out std_logic_vector(7 downto 0));

end MYMEM;

architecture BEHAVE of MYMEM is

signal logic0, logic1: std_logic;

component RAMB4_S8

--synopsys translate_off

generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,

INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255

downto 0)

:= X"0000000000000000000000000000000000000000000000000000000000000000");

--synopsys translate_on

port (WE, EN, RST, CLK: in STD_LOGIC;

ADDR: in STD_LOGIC_VECTOR(8 downto 0);

DI: in STD_LOGIC_VECTOR(7 downto 0);

DO: out STD_LOGIC_VECTOR(7 downto 0));

end component;

--synopsys dc_script_begin

--set_attribute ram0 INIT_00

"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string

--set_attribute ram0 INIT_01

"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string

--synopsys dc_script_end

begin

logic0 <=’0’;

logic1 <=’1’;

ram0: RAMB4_S8

--synopsys translate_off

generic map (

INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",

INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")

--synopsys translate_on

port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT);

end BEHAVE;

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Verilog Initialization Example

module MYMEM (CLK, WE, ADDR, DIN, DOUT);

input CLK, WE;

input [8:0] ADDR;

input [7:0] DIN;

output [7:0] DOUT;

wire logic0, logic1;

//synopsys dc_script_begin

//set_attribute ram0 INIT_00

"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string

//set_attribute ram0 INIT_01

"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string

//synopsys dc_script_end

assign logic0 = 1’b0;

assign logic1 = 1’b1;

RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),

.DO(DOUT));

//synopsys translate_off

defparam ram0.INIT_00 =

256h’0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;

defparam ram0.INIT_01 =

256h’FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;

//synopsys translate_on

endmodule

Using SelectIO

The Virtex-E FPGA series includes a highly configurable,

high-performance I/O resource, called SelectIO to provide

support for a wide variety of I/O standards. The SelectIO

resource is a robust set of features including programmable

control of output drive strength, slew rate, and input delay

and hold time. Taking advantage of the flexibility and Selec-

tIO features and the design considerations described in this

document can improve and simplify system level design.

Each SelectIO block can support up to 20 I/O standards.

Supporting such a variety of I/O standards allows the sup-

port of a wide variety of applications, from general purpose

standard applications to high-speed low-voltage memory

busses.

SelectIO blocks also provide selectable output drive

strengths and programmable slew rates for the LVTTL out-

put buffers, as well as an optional, programmable weak pull-

up, weak pull-down, or weak "keeper" circuit ideal for use in

external bussing applications.

Introduction

As FPGAs continue to grow in size and capacity, the larger

and more complex systems designed for them demand an

increased variety of I/O standards. Furthermore, as system

clock speeds continue to increase, the need for high perfor-

mance I/O becomes more important.

Each Input/Output Block (IOB) includes three registers, one

each for the input, output, and 3-state signals within the

IOB. These registers are optionally configurable as either a

D-type flip-flop or as a level sensitive latch.

The input buffer has an optional delay element used to guar-

antee a zero hold time requirement for input signals regis-

tered within the IOB.

While chip-to-chip delays have an increasingly substantial

impact on overall system speed, the task of achieving the

desired system performance becomes more difficult with

the proliferation of low-voltage I/O standards. SelectIO, the

revolutionary input/output resources of Virtex-E devices,

resolve this potential problem by providing a highly config-

urable, high-performance alternative to the I/O resources of

more conventional programmable devices. Virtex-E SelectIO

features combine the flexibility and time-to-market advan-

tages of programmable logic with the high performance pre-

viously available only with ASICs and custom ICs.

The Virtex-E SelectIO features also provide dedicated

resources for input reference voltage (V

) and output

REF

source voltage (V

), along with a convenient banking

CCO

system that simplifies board design.

By taking advantage of the built-in features and wide variety

of I/O standards supported by the SelectIO features, sys-

tem-level design and board design can be greatly simplified

and improved.

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Fundamentals

Overview of Supported I/O Standards

Modern bus applications, pioneered by the largest and most

influential companies in the digital electronics industry, are

commonly introduced with a new I/O standard tailored spe-

cifically to the needs of that application. The bus I/O stan-

dards provide specifications to other vendors who create

products designed to interface with these applications.

Each standard often has its own specifications for current,

voltage, I/O buffering, and termination techniques.

This section provides a brief overview of the I/O standards

supported by all Virtex-E devices.

While most I/O standards specify a range of allowed volt-

ages, this document records typical voltage values only.

Detailed information on each specification can be found on

the Electronic Industry Alliance Jedec website at:

http://www.jedec.org

LVTTL — Low-Voltage TTL

The ability to provide the flexibility and time-to-market

advantages of programmable logic is increasingly depen-

dent on the capability of the programmable logic device to

support an ever increasing variety of I/O standards

The Low-Voltage TTL, or LVTTL standard is a general pur-

pose EIA/JESDSA standard for 3.3V applications that uses

an LVTTL input buffer and a Push-Pull output buffer. This

The SelectIO resources feature highly configurable input

and output buffers which provide support for a wide variety

of I/O standards. As shown in Table 18, each buffer type can

support a variety of voltage requirements.

standard requires a 3.3V output source voltage (V

does not require the use of a reference voltage (V

), but

) or a

CCO

REF

termination voltage (V ).

TT

LVCMOS2 — Low-Voltage CMOS for 2.5V

Table 18: Virtex-E Supported I/O Standards

The Low-Voltage CMOS for 2.5V or lower, or LVCMOS2

standard is an extension of the LVCMOS standard (JESD 8-

5) used for general purpose 2.5V applications. This stan-

Board

Termination

dard requires a 2.5V output source voltage (V

), but

) or a

Output Input Input

Voltage

(V

CCO

does not require the use of a reference voltage (V

I/O Standard

LVTTL

V

)

TT

REF

CCO

REF

board termination voltage (V ).

TT

3.3

2.5

1.8

3.3

2.5

N/A

1.5

3.3

2.5

3.3

2.5

N/A

1.50

1.25

0.80

1.0

N/A

LVCMOS18 — 1.8V Low Voltage CMOS

LVCMOS2

LVCMOS18

SSTL3 I & II

SSTL2 I & II

GTL

This standard is an extension of the LVCMOS standard. It is

used in general purpose 1.8V applications. The use of a ref-

1.8

erence voltage (V

is not required.

) or a board termination voltage (V )

REF

TT

N/A

3.3

1.50

1.25

1.20

1.50

0.75

1.50

N/A

PCI — Peripheral Component Interface

The Peripheral Component Interface, or PCI standard spec-

ifies support for both 33 MHz and 66 MHz PCI bus applica-

tions. It uses a LVTTL input buffer and a Push-Pull output

buffer. This standard does not require the use of a reference

GTL+

voltage (V

) or a board termination voltage (V ), how-

REF

TT

HSTL I

0.75

0.90

1.50

1.32

N/A

ever, it does require a 3.3V output source voltage (V

).

CCO

GTL — Gunning Transceiver Logic Terminated

HSTL III & IV

CTT

The Gunning Transceiver Logic, or GTL standard is a high-

speed bus standard (JESD 8.3) invented by Xerox. Xilinx

has implemented the terminated variation for this standard.

This standard requires a differential amplifier input buffer

and a Open Drain output buffer.

AGP-2X

PCI33_3

PCI66_3

BLVDS & LVDS

LVPECL

GTL+ — Gunning Transceiver Logic Plus

3.3

The Gunning Transceiver Logic Plus, or GTL+ standard is a

high-speed bus standard (JESD 8.3) first used by the Pen-

tium Pro processor.

N/A

HSTL — High-Speed Transceiver Logic

The High-Speed Transceiver Logic, or HSTL standard is a

general purpose high-speed, 1.5V bus standard sponsored

by IBM (EIA/JESD 8-6). This standard has four variations or

classes. SelectIO devices support Class I, III, and IV. This

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standard requires a Differential Amplifier input buffer and a

Push-Pull output buffer.

Library Symbols

The Xilinx library includes an extensive list of symbols

designed to provide support for the variety of SelectIO fea-

tures. Most of these symbols represent variations of the five

generic SelectIO symbols.

SSTL3 — Stub Series Terminated Logic for 3.3V

The Stub Series Terminated Logic for 3.3V, or SSTL3 stan-

dard is a general purpose 3.3V memory bus standard also

sponsored by Hitachi and IBM (JESD 8-8). This standard

has two classes, I and II. SelectIO devices support both

classes for the SSTL3 standard. This standard requires a

Differential Amplifier input buffer and an Push-Pull output

buffer.

•

IBUF (input buffer)

IBUFG (global clock input buffer)

OBUF (output buffer)

OBUFT (3-state output buffer)

IOBUF (input/output buffer)

SSTL2 — Stub Series Terminated Logic for 2.5V

IBUF

The Stub Series Terminated Logic for 2.5V, or SSTL2 stan-

dard is a general purpose 2.5V memory bus standard spon-

sored by Hitachi and IBM (JESD 8-9). This standard has

two classes, I and II. SelectIO devices support both classes

for the SSTL2 standard. This standard requires a Differen-

tial Amplifier input buffer and an Push-Pull output buffer.

Signals used as inputs to the Virtex-E device must source

an input buffer (IBUF) via an external input port. The generic

Virtex-E IBUF symbol appears in Figure 37. The extension

IBUF

I

O

CTT — Center Tap Terminated

The Center Tap Terminated, or CTT standard is a 3.3V

memory bus standard sponsored by Fujitsu (JESD 8-4).

This standard requires a Differential Amplifier input buffer

and a Push-Pull output buffer.

x133_01_111699

Figure 37: Input Buffer (IBUF) Symbols

AGP-2X — Advanced Graphics Port

to the base name defines which I/O standard the IBUF

uses. The assumed standard is LVTTL when the generic

IBUF has no specified extension.

The Intel AGP standard is a 3.3V Advanced Graphics Port-

2X bus standard used with the Pentium II processor for

graphics applications. This standard requires a Push-Pull

output buffer and a Differential Amplifier input buffer.

The following list details the variations of the IBUF symbol:

•

IBUF

LVDS — Low Voltage Differential Signal

IBUF_LVCMOS2

IBUF_PCI33_3

IBUF_PCI66_3

IBUF_GTL

LVDS is a differential I/O standard. It requires that one data

bit is carried through two signal lines. As with all differential

signaling standards, LVDS has an inherent noise immunity

over single-ended I/O standards. The voltage swing

between two signal lines is approximately 350 mV. The use

IBUF_GTLP

IBUF_HSTL_I

IBUF_HSTL_III

IBUF_HSTL_IV

IBUF_SSTL3_I

IBUF_SSTL3_II

IBUF_SSTL2_I

IBUF_SSTL2_II

IBUF_CTT

of a reference voltage (V

) or a board termination voltage

REF

(V ) is not required. LVDS requires the use of two pins per

TT

input or output. LVDS requires external resistor termination.

BLVDS — Bus LVDS

This standard allows for bidirectional LVDS communication

between two or more devices. The external resistor termi-

nation is different than the one for standard LVDS.

LVPECL — Low Voltage Positive Emitter Coupled

Logic

IBUF_AGP

IBUF_LVCMOS18

IBUF_LVDS

LVPECL is another differential I/O standard. It requires two

signal lines for transmitting one data bit. This standard

specifies two pins per input or output. The voltage swing

between these two signal lines is approximately 850 mV.

IBUF_LVPECL

When the IBUF symbol supports an I/O standard that

requires a V , the IBUF automatically configures as a dif-

ferential amplifier input buffer. The V

supplied on the V

and BLVDS, V

REF

The use of a reference voltage (V

) or a board termina-

REF

voltage must be

pins. In the case of LVDS, LVPECL,

REF

tion voltage (V ) is not required. The LVPECL standard

TT

REF

requires external resistor termination.

is not required.

REF

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The voltage reference signal is "banked" within the Virtex-E

device on a half-edge basis such that for all packages there

CLKDLLHF, or BUFG symbol. The generic Virtex-E IBUFG

symbol appears in Figure 39.

are eight independent V

banks internally. See Figure 38

REF

for a representation of the Virtex-E I/O banks. Within each

bank approximately one of every six I/O pins is automati-

IBUFG

I

O

cally configured as a V

input. After placing a differential

REF

amplifier input signal within a given V

bank, the same

REF

external source must drive all I/O pins configured as a V

input.

REF

x133_03_111699

Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)

IBUF placement restrictions require that any differential

amplifier input signals within a bank be of the same stan-

dard. How to specify a specific location for the IBUF via the

LOC property is described below. Table 19 summarizes the

Virtex-E input standards compatibility requirements.

Symbol

The extension to the base name determines which I/O stan-

dard is used by the IBUFG. With no extension specified for

the generic IBUFG symbol, the assumed standard is

LVTTL.

An optional delay element is associated with each IBUF.

When the IBUF drives a flip-flop within the IOB, the delay

element by default activates to ensure a zero hold-time

requirement. The NODELAY=TRUE property overrides this

default.

The following list details variations of the IBUFG symbol.

•

IBUFG

IBUFG_LVCMOS2

IBUFG_PCI33_3

IBUFG_PCI66_3

IBUFG_GTL

When the IBUF does not drive a flip-flop within the IOB, the

delay element de-activates by default to provide higher per-

formance. To delay the input signal, activate the delay ele-

ment with the DELAY=TRUE property.

IBUFG_GTLP

IBUFG_HSTL_I

IBUFG_HSTL_III

IBUFG_HSTL_IV

IBUFG_SSTL3_I

IBUFG_SSTL3_II

IBUFG_SSTL2_I

IBUFG_SSTL2_II

IBUFG_CTT

Table 19: Xilinx Input Standards Compatibility

Requirements

Rule 1 Standards with the same input V

, output V

,

CCO

and V

can be placed within the same bank.

REF

IBUFG_AGP

IBUFG_LVCMOS18

IBUFG_LVDS

Bank 0

Bank 1

GCLK3 GCLK2

IBUFG_LVPECL

Virtex-E

Device

When the IBUFG symbol supports an I/O standard that

requires a differential amplifier input, the IBUFG automati-

cally configures as a differential amplifier input buffer. The

low-voltage I/O standards with a differential amplifier input

GCLK1 GCLK0

require an external reference voltage input V

.

REF

Bank 5

Bank 4

The voltage reference signal is "banked" within the Virtex-E

device on a half-edge basis such that for all packages there

are eight independent V

banks internally. See Figure 38

ds022_42_012100

REF

for a representation of the Virtex-E I/O banks. Within each

bank approximately one of every six I/O pins is automati-

Figure 38: Virtex-E I/O Banks

cally configured as a V

amplifier input signal within a given V

input. After placing a differential

REF

IBUFG

bank, the same

REF

Signals used as high fanout clock inputs to the Virtex-E

device should drive a global clock input buffer (IBUFG) via

an external input port in order to take advantage of one of

the four dedicated global clock distribution networks. The

output of the IBUFG symbol can drive only a CLKDLL,

external source must drive all I/O pins configured as a V

input.

REF

IBUFG placement restrictions require any differential ampli-

fier input signals within a bank be of the same standard. The

LOC property can specify a location for the IBUFG.

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As an added convenience, the BUFGP can be used to

instantiate a high fanout clock input. The BUFGP symbol

represents a combination of the LVTTL IBUFG and BUFG

symbols, such that the output of the BUFGP can connect

directly to the clock pins throughout the design.

•

OBUF_LVCMOS2

OBUF_PCI33_3

OBUF_PCI66_3

OBUF_GTL

OBUF_GTLP

Unlike previous architectures, the Virtex-E BUFGP symbol

can only be placed in a global clock pad location. The LOC

property can specify a location for the BUFGP.

OBUF_HSTL_I

OBUF_HSTL_III

OBUF_HSTL_IV

OBUF_SSTL3_I

OBUF_SSTL3_II

OBUF_SSTL2_I

OBUF_SSTL2_II

OBUF_CTT

OBUF

An OBUF must drive outputs through an external output

port. The generic output buffer (OBUF) symbol appears in

Figure 40.

The extension to the base name defines which I/O standard

the OBUF uses. With no extension specified for the generic

OBUF symbol, the assumed standard is slew rate limited

LVTTL with 12 mA drive strength.

OBUF_AGP

OBUF_LVCMOS18

OBUF_LVDS

OBUF_LVPECL

OBUF

The Virtex-E series supports eight banks for the HQ pack-

ages. The CB packages support one V banks.

I

O

CCO

OBUF placement restrictions require that within a given

bank each OBUF share the same output source drive

V

x133_04_111699

CCO

voltage. Input buffers of any type and output buffers that do

not require V can be placed within any V bank.

Table 20 summarizes the Virtex-E output compatibility

requirements. The LOC property can specify a location for

the OBUF.

Figure 40: Virtex-E Output Buffer (OBUF) Symbol

CCO

The LVTTL OBUF additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

Table 20: Output Standards Compatibility

Requirements

LVTTL output buffers have selectable drive strengths.

The format for LVTTL OBUF symbol names is as follows:

Rule 1 Only outputs with standards that share compatible

V_CCOcan be used within the same bank.

OBUF_<slew_rate>_<drive_strength>

where <slew_rate> is either F (Fast) or S (Slow), and

<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

Rule 2 There are no placement restrictions for outputs

with standards that do not require a V_CCO

.

V_CCO

3.3

Compatible Standards

The following list details variations of the OBUF symbol.

LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,

GTL+, PCI33_3, PCI66_3

•

OBUF

OBUF_S_2

OBUF_S_4

OBUF_S_6

OBUF_S_8

OBUF_S_12

OBUF_S_16

OBUF_S_24

OBUF_F_2

OBUF_F_4

OBUF_F_6

OBUF_F_8

OBUF_F_12

OBUF_F_16

OBUF_F_24

2.5

1.5

SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+

HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+

OBUFT

The generic 3-state output buffer OBUFT (see Figure 41)

typically implements 3-state outputs or bidirectional I/O.

The extension to the base name defines which I/O standard

OBUFT uses. With no extension specified for the generic

OBUFT symbol, the assumed standard is slew rate limited

LVTTL with 12 mA drive strength.

The LVTTL OBUFT additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

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LVTTL 3-state output buffers have selectable drive

strengths.

The Virtex-E series supports eight banks for the HQ pack-

age. The CB package supports one V

bank.

CCO

The format for LVTTL OBUFT symbol names is as follows:

The SelectIO OBUFT placement restrictions require that

within a given V bank each OBUFT share the same out-

CCO

OBUFT_<slew_rate>_<drive_strength>

put source drive voltage. Input buffers of any type and out-

put buffers that do not require V can be placed within

where <slew_rate> is either F (Fast) or S (Slow), and

<drive_strength> is specified in mA (2, 4, 6, 8, 12, 16, 24).

CCO

the same V

bank.

CCO

The LOC property can specify a location for the OBUFT.

3-state output buffers and bidirectional buffers can have

either a weak pull-up resistor, a weak pull-down resistor, or

a weak "keeper" circuit. Control this feature by adding the

appropriate symbol to the output net of the OBUFT (PUL-

LUP, PULLDOWN, or KEEPER).

OBUFT

T

O

I

The weak "keeper" circuit requires the input buffer within the

IOB to sample the I/O signal. So, OBUFTs programmed for

x133_05_111699

Figure 41: 3-State Output Buffer Symbol (OBUFT)

an I/O standard that requires a V

have automatic place-

REF

ment of a V

in the bank with an OBUFT configured with

The following list details variations of the OBUFT symbol.

REF

a weak "keeper" circuit. This restriction does not affect most

circuit design as applications using an OBUFT configured

with a weak "keeper" typically implement a bidirectional I/O.

•

OBUFT

OBUFT_S_2

OBUFT_S_4

OBUFT_S_6

In this case the IBUF (and the corresponding V

explicitly placed.

) are

REF

OBUFT_S_8

The LOC property can specify a location for the OBUFT.

OBUFT_S_12

OBUFT_S_16

OBUFT_S_24

OBUFT_F_2

OBUFT_F_4

OBUFT_F_6

IOBUF

Use the IOBUF symbol for bidirectional signals that require

both an input buffer and a 3-state output buffer with an

active high 3-state pin. The generic input/output buffer

IOBUF appears in Figure 42.

The extension to the base name defines which I/O standard

the IOBUF uses. With no extension specified for the generic

IOBUF symbol, the assumed standard is LVTTL input buffer

and slew rate limited LVTTL with 12 mA drive strength for

the output buffer.

OBUFT_F_8

OBUFT_F_12

OBUFT_F_16

OBUFT_F_24

OBUFT_LVCMOS2

OBUFT_PCI33_3

OBUFT_PCI66_3

OBUFT_GTL

OBUFT_GTLP

OBUFT_HSTL_I

OBUFT_HSTL_III

OBUFT_HSTL_IV

OBUFT_SSTL3_I

OBUFT_SSTL3_II

OBUFT_SSTL2_I

OBUFT_SSTL2_II

OBUFT_CTT

The LVTTL IOBUF additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

LVTTL bidirectional buffers have selectable output drive

strengths.

The format for LVTTL IOBUF symbol names is as follows:

IOBUF_<slew_rate>_<drive_strength>

where <slew_rate> is either F (Fast) or S (Slow), and

<drive_strength> is specified in mA (2, 4, 6, 8, 12, 16, 24).

IOBUF

T

I

IO

OBUFT_AGP

OBUFT_LVCMOS18

OBUFT_LVDS

OBUFT_LVPECL

O

x133_06_111699

Figure 42: Input/Output Buffer Symbol (IOBUF)

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The following list details variations of the IOBUF symbol.

The Virtex-E series supports eight banks for the HQ pack-

age. The CB package supports one V

bank.

CCO

•

IOBUF

IOBUF_S_2

IOBUF_S_4

IOBUF_S_6

Additional restrictions on the Virtex-E SelectIO IOBUF

placement require that within a given V bank each

IOBUF must share the same output source drive voltage.

Input buffers of any type and output buffers that do not

CCO

IOBUF_S_8

require V

can be placed within the same V

bank.

CCO

IOBUF_S_12

IOBUF_S_16

IOBUF_S_24

IOBUF_F_2

IOBUF_F_4

IOBUF_F_6

The LOC property can specify a location for the IOBUF.

An optional delay element is associated with the input path

in each IOBUF. When the IOBUF drives an input flip-flop

within the IOB, the delay element activates by default to

ensure a zero hold-time requirement. Override this default

with the NODELAY=TRUE property.

IOBUF_F_8

In the case when the IOBUF does not drive an input flip-flop

within the IOB, the delay element de-activates by default to

provide higher performance. To delay the input signal, acti-

vate the delay element with the DELAY=TRUE property.

IOBUF_F_12

IOBUF_F_16

IOBUF_F_24

IOBUF_LVCMOS2

IOBUF_PCI33_3

IOBUF_PCI66_3

IOBUF_GTL

IOBUF_GTLP

IOBUF_HSTL_I

IOBUF_HSTL_III

IOBUF_HSTL_IV

IOBUF_SSTL3_I

IOBUF_SSTL3_II

IOBUF_SSTL2_I

IOBUF_SSTL2_II

IOBUF_CTT

3-state output buffers and bidirectional buffers can have

either a weak pull-up resistor, a weak pull-down resistor, or

a weak "keeper" circuit. Control this feature by adding the

appropriate symbol to the output net of the IOBUF (PUL-

LUP, PULLDOWN, or KEEPER).

SelectIO Properties

Access to some of the SelectIO features (for example, loca-

tion constraints, input delay, output drive strength, and slew

rate) is available through properties associated with these

features.

Input Delay Properties

An optional delay element is associated with each IBUF.

When the IBUF drives a flip-flop within the IOB, the delay

element activates by default to ensure a zero hold-time

requirement. Use the NODELAY=TRUE property to over-

ride this default.

IOBUF_AGP

IOBUF_LVCMOS18

IOBUF_LVDS

IOBUF_LVPECL

In the case when the IBUF does not drive a flip-flop within

the IOB, the delay element by default de-activates to pro-

vide higher performance. To delay the input signal, activate

the delay element with the DELAY=TRUE property.

When the IOBUF symbol used supports an I/O standard

that requires a differential amplifier input, the IOBUF auto-

matically configures with a differential amplifier input buffer.

The low-voltage I/O standards with a differential amplifier

IOB Flip-Flop/Latch Property

input require an external reference voltage input V

.

REF

The Virtex-E series I/O Block (IOB) includes an optional

register on the input path, an optional register on the output

path, and an optional register on the 3-state control pin. The

design implementation software automatically takes advan-

tage of these registers when the following option for the Map

program is specified.

The voltage reference signal is "banked" within the Virtex-E

device on a half-edge basis such that for all packages there

are eight independent V

banks internally. See Figure 38,

REF

page 33 for a representation of the Virtex-E I/O banks.

Within each bank approximately one of every six I/O pins is

automatically configured as a V

input. After placing a dif-

REF

map –pr b <filename>

ferential amplifier input signal within a given V

bank, the

REF

same external source must drive all I/O pins configured as a

input.

Alternatively, the IOB = TRUE property can be placed on a

register to force the mapper to place the register in an IOB.

V

REF

IOBUF placement restrictions require any differential ampli-

fier input signals within a bank be of the same standard.

Location Constraints

Specify the location of each SelectIO symbol with the loca-

tion constraint LOC attached to the SelectIO symbol. The

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external port identifier indicates the value of the location

constrain. The format of the port identifier depends on the

package chosen for the specific design.

figured as a V

input signal within a given V

source must drive all I/O pins configured as a V

input. After placing a differential amplifier

REF

bank, the same external

REF

input.

REF

The LOC properties use the following form:

LOC=A42

Within each V

bank, any input buffers that require a

REF

V

signal must be of the same type. Output buffers of any

REF

type and input buffers can be placed without requiring a ref-

erence voltage within the same V bank.

LOC=P37

REF

Output Slew Rate Property

Output Drive Source Voltage (V_CCO) Pins

As mentioned above, a variety of symbol names provide the

option of choosing the desired slew rate for the output buff-

ers. In the case of the LVTTL output buffers (OBUF, OBUFT,

and IOBUF), slew rate control can be alternatively pro-

gramed with the SLEW= property. By default, the slew rate

for each output buffer is reduced to minimize power bus

transients when switching non-critical signals. The SLEW=

property has one of the two following values.

Many of the low voltage I/O standards supported by Selec-

tIO devices require a different output drive source voltage

(V

). As a result each device can often have to support

CCO

multiple output drive source voltages.

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS package supports four V

banks.

CCO

Output buffers within a given V

bank must share the

CCO

same output drive source voltage. Input buffers for LVTTL,

LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the

SLEW=SLOW

V

voltage for Input V

voltage.

CCO

SLEW=FAST

Transmission Line Effects

Output Drive Strength Property

The delay of an electrical signal along a wire is dominated

by the rise and fall times when the signal travels a short dis-

tance. Transmission line delays vary with inductance and

capacitance, but a well-designed board can experience

delays of approximately 180 ps per inch.

The desired output drive strength can be additionally speci-

fied by choosing the appropriate library symbol. The Xilinx

library also provides an alternative method for specifying

this feature. For the LVTTL output buffers (OBUF, OBUFT,

and IOBUF, the desired drive strength can be specified with

the DRIVE= property. This property could have one of the

following seven values.

Transmission line effects, or reflections, typically start at

1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-

tent) termination or changes in the transmission line imped-

ance cause these reflections and can cause additional

delay in longer traces. As system speeds continue to

increase, the effect of I/O delays can become a limiting fac-

tor and therefore transmission line termination becomes

increasingly more important.

DRIVE=2

DRIVE=4

DRIVE=6

DRIVE=8

DRIVE=12 (Default)

DRIVE=16

DRIVE=24

Termination Techniques

A variety of termination techniques reduce the impact of

transmission line effects.

Design Considerations

The following are output termination techniques:

Reference Voltage (V_REF) Pins

•

None

Series

Low-voltage I/O standards with a differential amplifier input

buffer require an input reference voltage (V

). Provide the

REF

Parallel (Shunt)

Series and Parallel (Series-Shunt)

V

as an external signal to the device.

REF

The voltage reference signal is "banked" within the device on

a half-edge basis such that for all packages there are eight

Input termination techniques include the following.

independent V

banks internally. See Figure 38 for a rep-

•

None

Parallel (Shunt)

REF

resentation of the Virtex-E I/O banks. Within each bank

approximately one of every six I/O pins is automatically con-

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These termination techniques can be applied in any combi-

nation. A generic example of each combination of termina-

tion methods appears in Figure 43.

Table 21: Guidelines for Max Number of

Simultaneously Switching Outputs per Power/Ground

Pair (Continued)

Standard

LVTTL Slow Slew Rate, 12 mA drive

LVTTL Slow Slew Rate, 16 mA drive

LVTTL Slow Slew Rate, 24 mA drive

LVTTL Fast Slew Rate, 2 mA drive

LVTTL Fast Slew Rate, 4 mA drive

LVTTL Fast Slew Rate, 6 mA drive

LVTTL Fast Slew Rate, 8 mA drive

LVTTL Fast Slew Rate, 12 mA drive

LVTTL Fast Slew Rate, 16 mA drive

LVTTL Fast Slew Rate, 24 mA drive

LVCMOS2

Outputs

Double Parallel Terminated

Unterminated

Z=50

V_TT

17

14

9

Z=50

V_REF

Unterminated Output Driving

a Parallel Terminated Input

Series Terminated Output Driving

a Parallel Terminated Input

V_TT

40

24

17

13

10

8

Z=50

V_REF

Z=50

V_REF

Series-Parallel Terminated Output

Driving a Parallel Terminated Input

V_TT

Series Terminated Output

Z=50

V_REF

Z=50

V_REF

x133_07_111699

Figure 43: Overview of Standard Input and Output

Termination Methods

5

10

8

Simultaneous Switching Guidelines

PCI

Ground bounce can occur with high-speed digital ICs when

multiple outputs change states simultaneously, causing

undesired transient behavior on an output, or in the internal

logic. This problem is also referred to as the Simultaneous

Switching Output (SSO) problem.

GTL

4

GTL+

4

HSTL Class I

18

9

Ground bounce is primarily due to current changes in the

combined inductance of ground pins, bond wires, and

ground metallization. The IC internal ground level deviates

from the external system ground level for a short duration (a

few nanoseconds) after multiple outputs change state

simultaneously.

HSTL Class III

HSTL Class IV

5

SSTL2 Class I

15

10

11

7

SSTL2 Class II

Ground bounce affects stable Low outputs and all inputs

because they interpret the incoming signal by comparing it

to the internal ground. If the ground bounce amplitude

exceeds the actual instantaneous noise margin, then a non-

changing input can be interpreted as a short pulse with a

polarity opposite to the ground bounce.

SSTL3 Class I

SSTL3 Class II

CTT

14

9

AGP

Notes:

Table 21 provides guidelines for the maximum number of

simultaneously switching outputs allowed per output

power/ground pair to avoid the effects of ground bounce. See

Table 22 for the number of effective output power/ground pairs

for each Virtex-E device and package combination.

1. This analysis assumes a 35 pF load for each output.

Table 22: Virtex-E Equivalent Power/Ground Pairs

Pkg/Part

CB228

BG432

BG560

CG560

FG1156

XQV600E XQV1000E XQV2000E

Table 21: Guidelines for Max Number of

Simultaneously Switching Outputs per Power/Ground

Pair

27

40

-

Standard

Outputs

56

-

60

-

LVTTL Slow Slew Rate, 2 mA drive

LVTTL Slow Slew Rate, 4 mA drive

LVTTL Slow Slew Rate, 6 mA drive

LVTTL Slow Slew Rate, 8 mA drive

68

41

29

22

-

120

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GTL+

Application Examples

A sample circuit illustrating a valid termination technique for

GTL+ appears in Figure 45. DC voltage specifications

appear in Table 24.

Creating a design with the SelectIO features requires the

instantiation of the desired library symbol within the design

code. At the board level, designers need to know the termi-

nation techniques required for each I/O standard.

GTL+

This section describes some common application examples

illustrating the termination techniques recommended by

each of the standards supported by the SelectIO features.

= 1.5V

V_TT

50Ω

V

= N/A

Termination Examples

CCO

Z = 50

Circuit examples involving typical termination techniques for

each of the SelectIO standards follow. For a full range of

accepted values for the DC voltage specifications for each

standard, refer to the table associated with each figure.

V_REF= 1.0V

x133_09_012400

Figure 45: Terminated GTL+

The resistors used in each termination technique example

and the transmission lines depicted represent board level

components and are not meant to represent components

on the device.

Table 24: GTL+ Voltage Specifications

Parameter

Min

Typ

-

Max

V

-

0.88

1.35

0.98

-

1.12

1.65

-

CCO

REF

TT

GTL

(1)

= N × V

1.0

1.5

1.1

0.9

-

TT

A sample circuit illustrating a valid termination technique for

GTL is shown in Figure 44.

= V

+ 0.1

– 0.1

IH

REF

V = V

1.02

-

IL

REF

GTL

V

-

OH

OL

V_TT= 1.2V V_TT= 1.2V

0.3

-

0.45

-

0.6

-

50Ω

Z = 50

I

at V (mA)

OH

V_CCO= N/A

at V (mA) at 0.6V

36

-

OL

V_REF= 0.8V

at V (mA) at 0.3V

-

48

OL

x133_08_111699

Notes:

1. N must be greater than or equal to 0.653 and less than or

Figure 44: Terminated GTL

equal to 0.68.

Table 23 lists DC voltage specifications.

Table 23: GTL Voltage Specifications

Parameter

Min

Typ

N/A

0.8

1.2

0.85

0.75

-

Max

V

-

0.86

1.26

-

CCO

REF

TT

(1)

= N × V

0.74

TT

1.14

= V

+ 0.05

– 0.05

0.79

IH

REF

V = V

-

0.81

-

IL

REF

V

OH

OL

V

-

0.2

-

0.4

-

I

at V (mA)

-

OH

at V (mA) at 0.4V

32

-

OL

at V (mA) at 0.2V

-

40

OL

Notes:

1. N must be greater than or equal to 0.653 and less than or

equal to 0.68.

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HSTL

A sample circuit illustrating a valid termination technique for

HSTL_I appears in Figure 46. A sample circuit illustrating a

valid termination technique for HSTL_III appears in

Figure 47.

HSTL Class III

V_CCO= 1.5V

V_TT= 1.5V

50Ω

Z = 50

Table 25: HSTL Class I Voltage Specification

V_REF= 0.9V

Parameter

Min

1.40

0.68

-

Typ

1.50

0.75

Max

1.60

0.90

-

x133_11_111699

V

CCO

Figure 47: Terminated HSTL Class III

REF

TT

IH

A sample circuit illustrating a valid termination technique for

HSTL_IV appears in Figure 48.

V

× 0.5

CCO

V

+ 0.1

-

REF

Table 27: HSTL Class IV Voltage Specification

-

V

– 0.1

REF

IL

Parameter

Min

Typ

1.50

0.90

Max

– 0.4

CCO

-

0.4

-

OH

OL

V

1.40

1.60

CCO

-

REF

TT

IH

I

at V (mA)

−8

-

OH

V

CCO

at V (mA)

8

-

OL

V

+ 0.1

-

REF

-

V

– 0.1

REF

IL

HSTL Class I

= 1.5V

V

– 0.4

CCO

-

0.4

-

OH

OL

V

= 0.75V

TT

V

-

CCO

50Ω

Z = 50

I

at V (mA)

−8

OH

at V (mA)

48

-

OL

V

= 0.75V

REF

x133_10_111699

Notes:

1. Per EIA/JESD8-6, "The value of V_REFis to be selected by the

user to provide optimum noise margin in the use conditions

specified by the user.

Figure 46: Terminated HSTL Class I

Table 26: HSTL Class III Voltage Specification

Parameter

Min

Typ

1.50

0.90

Max

HSTL Class IV

V

1.40

1.60

CCO

V_TT= 1.5V V_TT= 1.5V

V_CCO= 1.5V

(1)

-

REF

TT

IH

50Ω

V

CCO

Z = 50

V_REF= 0.9V

V

+ 0.1

-

REF

x133_12_111699

-

V

– 0.1

REF

IL

Figure 48: Terminated HSTL Class IV

V

– 0.4

CCO

-

0.4

-

OH

OL

-

I

at V (mA)

−8

OH

I

at V (mA)

24

-

OL

Notes:

1. Per EIA/JESD8-6, "The value of V_REFis to be selected by the

user to provide optimum noise margin in the use conditions

specified by the user."

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SSTL3_I

Table 29: SSTL3_II Voltage Specifications

A sample circuit illustrating a valid termination technique for

SSTL3_I appears in Figure 49. DC voltage specifications

appear in Table 28.

Parameter

Min

3.0

1.3

1.5

Typ

3.3

1.5

1.7

1.3

-

Max

3.6

V

CCO

REF

= 0.45 × V

1.7

CCO

SSTL3 Class I

= V

1.7

TT

IH

REF

V

_TT= 1.5V

V

_CCO= 3.3V

(1)

= V

+ 0.2

3.9

REF

50Ω

25Ω

(2)

V = V

– 0.2

REF

−0.3

2.1

-

1.5

IL

Z = 50

V_REF= 1.5V

V

= V

+ 0.8

REF

-

0.9

-

OH

OL

x133_13_111699

= V

– 0.8

-

REF

Figure 49: Terminated SSTL3 Class I

I

at V (mA)

−16

16

-

OH

at V (mA)

-

OL

Table 28: SSTL3_I Voltage Specifications

Notes:

1. _IHmaximum is V_CCO+ 0.3

Parameter

Min

3.0

1.3

1.5

Typ

3.3

1.5

1.7

1.3

-

Max

3.6

1.7

V

2. V_ILminimum does not conform to the formula

V

CCO

REF

TT

= 0.45 × V

SSTL2_I

CCO

= V

A sample circuit illustrating a valid termination technique for

SSTL2_I appears in Figure 51. DC voltage specifications

appear in Table 30.

REF

(1)

= V

+ 0.2

– 0.2

+ 0.6

3.9

IH

(2)

V = V

−0.3

1.9

-

1.5

IL

V

= V

-

1.1

-

SSTL2 Class I

OH

OL

REF

V

= 1.25V

TT

V

= V

– 0.6

-

V

= 2.5V

CCO

50Ω

I

at V (mA)

−8

8

-

OH

25Ω

Z = 50

at V (mA)

-

OL

V

= 1.25V

REF

Notes:

xap133_15_011000

1. V_IHmaximum is V_CCO+ 0.3

2. V_ILminimum does not conform to the formula

Figure 51: Terminated SSTL2 Class I

SSTL3_II

Table 30: SSTL2_I Voltage Specifications

A sample circuit illustrating a valid termination technique for

SSTL3_II appears in Figure 50. DC voltage specifications

appear in Table 29.

Parameter

Min

2.3

Typ

2.5

1.25

1.43

1.07

-

Max

2.7

V

CCO

REF

= 0.5 × V

1.15

1.11

1.33

1.35

1.39

CCO

(1)

SSTL3 Class II

= V

+ N

TT

IH

REF

V_TT= 1.5V V_TT= 1.5V

(2)

= V

+ 0.18

– 0.18

3.0

V_CCO= 3.3V

(3)

50Ω

Z = 50

V = V

−0.3

1.17

-

IL

25Ω

V

= V

+ 0.61

REF

1.76

-

OH

V_REF= 1.5V

V

= V

– 0.61

REF

-

0.74

OL

x133_14_111699

Figure 50: Terminated SSTL3 Class II

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Table 30: SSTL2_I Voltage Specifications

Parameter

at V (mA)

Min

−7.6

7.6

Typ

Max

CTT

I

-

OH

V_TT= 1.5V

V_CCO= 3.3V

at V (mA)

OL

50Ω

Notes:

Z = 50

1. N must be greater than or equal to −0.04 and less than or

V_REF= 1.5V

equal to 0.04.

2. V_IHmaximum is V_CCO+ 0.3.

x133_17_111699

3. V_ILminimum does not conform to the formula.

Figure 53: Terminated CTT

SSTL2_II

A sample circuit illustrating a valid termination technique for

SSTL2_II appears in Figure 52. DC voltage specifications

appear in Table 31.

Table 32: CTT Voltage Specifications

Parameter

Min

Typ

3.3

1.5

1.7

1.3

1.9

1.1

-

Max

3.6

1.65

-

(1)

V

2.05

1.35

CCO

REF

TT

SSTL2 Class II

1.35

1.55

-

V_TT= 1.25V V_TT= 1.25V

V

_CCO= 2.5V

= V

+ 0.2

– 0.2

IH

REF

50Ω

25Ω

Z = 50

V = V

1.45

-

IL

REF

V_REF= 1.25V

V

= V

+ 0.4

REF

1.75

-

OH

x133_16_111699

= V

– 0.4

REF

1.25

-

OL

Figure 52: Terminated SSTL2 Class II

I

at V (mA)

−8

8

OH

Table 31: SSTL2_II Voltage Specifications

at V (mA)

-

OL

Parameter

Min

2.3

Typ

2.5

1.25

1.43

1.07

-

Max

2.7

Notes:

1. Timing delays are calculated based on V_CCOmin of 3.0V.

V

CCO

REF

= 0.5 × V

1.15

1.11

1.33

1.35

1.39

CCO

(1)

PCI33_3 & PCI66_3

= V

+ N

TT

IH

REF

PCI33_3 or PCI66_3 require no termination. DC voltage

specifications appear in Table 33.

(2)

= V

+ 0.18

– 0.18

3.0

(3)

V = V

−0.3

1.17

IL

Table 33: PCI33_3 and PCI66_3 Voltage Specifications

V

= V

+ 0.8

– 0.8

1.95

-

OH

OL

REF

Parameter

Min

3.0

Typ

Max

V

= V

-

0.55

V

3.3

3.6

CCO

REF

TT

I

at V (mA)

−15.2

15.2

-

OH

-

at V (mA)

-

OL

-

Notes:

1. N must be greater than or equal to -0.04 and less than or

= 0.5 × V

1.5

1.65

V

+ 0.5

CCO

IH

CCO

equal to 0.04.

2. V_IHmaximum is V_CCO+ 0.3.

3. V_ILminimum does not conform to the formula.

V = 0.3 × V

−0.5

2.7

0.99

1.08

IL

CCO

V

I

= 0.9 × V

-

OH

CCO

= 0.1 × V

-

0.36

OL

CCO

CTT

at V (mA)

Note 1

-

A sample circuit illustrating a valid termination technique for

CTT appear in Figure 53. DC voltage specifications appear

in Table 32.

OH

I

at V (mA)

OL

Notes:

1. Tested according to the relevant specification.

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LVTTL

LVCMOS18

LVTTL requires no termination. DC voltage specifications

appears in Table 34.

LVCMOS18 does not require termination. Table 36 lists DC

voltage specifications.

Table 34: LVTTL Voltage Specifications

Table 36: LVCMOS18 Voltage Specifications

Parameter

Min

3.0

-

Typ

Max

Parameter

Min

Typ

Max

1.90

-

V

3.3

3.6

V

1.70

1.80

CCO

REF

TT

CCO

-

REF

TT

IH

-

2.0

−0.5

2.4

-

3.6

0.8

-

0.65 x V

1.95

IH

CCO

– 0.5

V – 0.4

CCO

0.2 x V

CCO

IL

-

0.4

-

OH

OL

OH

OL

0.4

-

I

at V (mA)

−24

24

I

at V (mA)

–8

8

OH

I

at V (mA)

-

at V (mA)

-

OL

Notes:

1. Note: V_OLand V_OHfor lower drive currents sample tested.

AGP-2X

The specification for the AGP-2X standard does not docu-

ment a recommended termination technique. DC voltage

specifications appear in Table 37.

LVCMOS2

LVCMOS2 requires no termination. DC voltage specifica-

tions appear in Table 35.

Table 37: AGP-2X Voltage Specifications

Parameter

Min

3.0

Typ

3.3

1.32

-

Max

Table 35: LVCMOS2 Voltage Specifications

V

3.6

CCO

REF

TT

Parameter

Min

2.3

-

Typ

Max

(1)

= N × V

1.17

-

1.48

CCO

V

2.5

2.7

CCO

REF

TT

-

= V

+ 0.2

– 0.2

1.37

-

1.52

1.12

3.0

0.33

-

IH

REF

-

V = V

1.28

IL

REF

1.7

−0.5

1.9

-

3.6

0.7

-

IH

V

= 0.9 × V

2.7

-

OH

OL

CCO

IL

V

= 0.1 × V

-

0.36

OH

OL

I

at V (mA)

Note 2

-

OH

0.4

-

at V (mA)

-

OL

I

at V (mA)

−12

12

OH

Notes:

I

at V (mA)

-

OL

1. N must be greater than or equal to 0.39 and less than or

equal to 0.41.

2. Tested according to the relevant specification.

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LVDS

LVPECL

Depending on whether the device is transmitting or receiv-

ing an LVPECL signal, two different circuits are used for

LVPECL termination. A sample circuit illustrating a valid ter-

mination technique for transmitting LVPECL signals

appears in Figure 56. A sample circuit illustrating a valid ter-

mination for receiving LVPECL signals appears in

Figure 57. Table 39 lists DC voltage specifications. Further

information on the specific termination resistor packs shown

can be found on Table 40.

Depending on whether the device is transmitting an LVDS

signal or receiving an LVDS signal, there are two different

circuits used for LVDS termination. A sample circuit illustrat-

ing a valid termination technique for transmitting LVDS sig-

nals appears in Figure 54. A sample circuit illustrating a

valid termination for receiving LVDS signals appears in

Figure 55. Table 38 lists DC voltage specifications. Further

information on the specific termination resistor packs shown

can be found on Table 40.

Table 39: LVPECL Voltage Specifications

1/4 of Bourns

Parameter

Min

3.0

-

Typ

Max

3.6

-

Part Number

Virtex-E

CAT16-LV4F12

FPGA

R_S

Z

= 50Ω

0

V

3.3

Q

CCO

REF

TT

to LVDS Receiver

2.5V

165

R

-

DIV

140

DATA

Transmit

R_S

-

Q

165

1.49

0.86

1.8

-

2.72

2.125

-

V

_CCO= 2.5V

LVDS

Output

IH

x133_19_122799

IL

Figure 54: Transmitting LVDS Signal Circuit

OH

OL

1.57

Notes:

VIRTEX-E

FPGA

Z

= 50Ω

1. For more detailed information, see LVPECL DC

0

LVDS_IN

Q

Specifications (Module 2).

+

–

from

LVDS

Driver

R

T

100Ω

DATA

Receive

1/4 of Bourns

Part Number

LVDS_IN

Virtex-E

CAT16-PC4F12

FPGA

R_S

Z

= 50Ω

0

LVPECL_OUT

Q

to LVPECL Receiver

3.3V

x133_29_122799

100

R

DIV

187

DATA

Transmit

R_S

0

Figure 55: Receiving LVDS Signal Circuit

Table 38: LVDS Voltage Specifications

to LVPECL Receiver

Q

100

x133_20_122799

Parameter

Min

2.375

0.2

Typ

2.5

1.25

0.35

-

Max

2.625

2.2

Figure 56: Transmitting LVPECL Signal Circuit

V

CCO

(2)

ICM

VIRTEX-E

FPGA

(1)

Z

= 50Ω

0

Q

LVPECL_IN

1.125

0.1

1.375

-

OCM

+

–

from

LVPECL

Driver

(1)

R

T

100Ω

DATA

Receive

IDIFF

Z

(1)

0.25

1.25

-

0.45

-

ODIFF

LVPECL_IN

(1)

OH

x133_21_122799

(1)

-

1.25

OL

Figure 57: Receiving LVPECL Signal Circuit

Notes:

1. Measured with a 100Ω resistor across Q and Q.

2. Measured with a differential input voltage = ± 350 mV.

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Termination Resistor Packs

Creating LVDS Global Clock Input Buffers

Resistor packs are available with the values and the config-

uration required for LVDS and LVPECL termination from

Bourns, Inc., as listed in Table. For pricing and availability,

please contact Bourns directly at http://www.bourns.com.

Global clock input buffers can be combined with adjacent

IOBs to form LVDS clock input buffers. P-side is the GCLK-

PAD location; N-side is the adjacent IO_LVDS_DLL site.

Table 41: Global Clock Input Buffer Pair Locations

Table 40: Bourns LVDS/LVPECL Resistor Packs

GCLK 3

GCLK 2

GCLK 1

GCLK 0

Term.

for:

Pairs/

Pack Pins

Pkg

P

N

P

N

P

N

P

N

Part Number

CAT16−LV2F6

CAT16−LV4F12

CAT16−PC2F6

CAT16−PC4F12

CAT16−PT2F2

CAT16−PT4F4

I/O Standard

LVDS

CB228

-

199

198

-

87

88

Driver

2

4

2

4

2

4

8

16

8

BG432 D17

BG560 A17

CG560 A17

FG1156 E17

C17

C18

C17

A16 B16 AK16 AL17 AL16 AH15

D17 E17 AJ17 AM18 AL17 AM17

LVDS

LVPECL

16

8

D17

J18

Al19

AL17 AH18 AM18

LVDS/LVPECL Receiver

16

HDL Instantiation

Only one global clock input buffer is required to be instanti-

ated in the design and placed on the correct GCLKPAD

location. The N-side of the buffer is reserved and no other

IOB is allowed to be placed on this location.

LVDS Design Guide

The SelectIO library elements have been expanded for Vir-

tex-E devices to include new LVDS variants. At this time all

of the cells might not be included in the Synthesis libraries.

The 2.1i-Service Pack 2 update for Alliance and Foundation

software includes these cells in the VHDL and Verilog librar-

ies. It is necessary to combine these cells to create the P-

side (positive) and N-side (negative) as described in the

input, output, 3-state and bidirectional sections.

In the physical device, a configuration option is enabled that

routes the pad wire to the differential input buffer located in

the GCLKIOB. The output of this buffer then drives the out-

put of the GCLKIOB cell. In EPIC it appears that the second

buffer is unused. Any attempt to use this location for another

purpose leads to a DRC error in the software.

VHDL Instantiation

IBUF_LVDS

OBUF_LVDS

IOBUF_LVDS

T

gclk0_p : IBUFG_LVDS port map

(I=>clk_external, O=>clk_internal);

I

O

I

O

I

IO

Verilog Instantiation

IBUFG_LVDS

OBUFT_LVDS

T

O

IBUFG_LVDS gclk0_p (.I(clk_external),

.O(clk_internal));

I

O

I

O

x133_22_122299

Location constraints

Figure 58: LVDS elements

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the .ucf or .ncf file.

NET clk_external LOC = GCLKPAD3;

GCLKPAD3 can also be replaced with the package pin

name such as D17 for the BG432 package.

Optional N-side

Some designers might prefer to also instantiate the N-side

buffer for the global clock buffer. This allows the top-level net

list to include net connections for both PCB layout and sys-

tem-level integration. In this case, only the output P-side

IBUFG connection has a net connected to it. Since the N-

side IBUFG does not have a connection in the EDIF net list,

it is trimmed from the design in MAP.

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VHDL Instantiation

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the input buffers this can be done with the following con-

straint in the .ucf or .ncf file.

gclk0_p : IBUFG_LVDS port map

(I=>clk_p_external, O=>clk_internal);

gclk0_n : IBUFG_LVDS port map

(I=>clk_n_external, O=>clk_internal);

NET data<0> LOC = D28; # IO_L0P

Optional N-side

Verilog Instantiation

Some designers might prefer to also instantiate the N-side

buffer for the input buffer. This allows the top-level net list to

include net connections for both PCB layout and system-

level integration. In this case, only the output P-side IBUF

connection has a net connected to it. Since the N-side IBUF

does not have a connection in the EDIF net list, it is trimmed

from the design in MAP.

IBUFG_LVDS gclk0_p (.I(clk_p_external),

.O(clk_internal));

IBUFG_LVDS gclk0_n (.I(clk_n_external),

.O(clk_internal));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the .ucf or .ncf file.

VHDL Instantiation

data0_p : IBUF_LVDS port map

(I=>data_p(0), O=>data_int(0));

NET clk_p_external LOC = GCLKPAD3;

NET clk_n_external LOC = C17;

data0_n : IBUF_LVDS port map

(I=>data_n(0), O=>open);

GCLKPAD3 can also be replaced with the package pin

name, such as D17 for the BG432 package.

Verilog Instantiation

IBUF_LVDS data0_p (.I(data_p[0]),

.O(data_int[0]));

Creating LVDS Input Buffers

An LVDS input buffer can be placed in a wide number of IOB

locations. The exact location is dependent on the package

that is used. The Virtex-E package information lists the pos-

sible locations as IO_L#P for the P-side and IO_L#N for the

N-side where # is the pair number.

IBUF_LVDS data0_n (.I(data_n[0]), .O());

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the .ucf or .ncf file.

HDL Instantiation

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Adding an Input Register

Only one input buffer is required to be instantiated in the

design and placed on the correct IO_L#P location. The N-

side of the buffer is reserved and no other IOB is allowed to

be placed on this location. In the physical device, a configu-

ration option is enabled that routes the pad wire from the

IO_L#N IOB to the differential input buffer located in the

IO_L#P IOB. The output of this buffer then drives the output

of the IO_L#P cell or the input register in the IO_L#P IOB. In

EPIC it appears that the second buffer is unused. Any

attempt to use this location for another purpose leads to a

DRC error in the software.

All LVDS buffers can have an input register in the IOB. The

input register is in the P-side IOB only. All the normal IOB

register options are available (FD, FDE, FDC, FDCE, FDP,

FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,

LDP, LDPE). The register elements can be inferred or

explicitly instantiated in the HDL code.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the "map

-pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b"

is both inputs and outputs.

VHDL Instantiation

data0_p : IBUF_LVDS port map (I=>data(0),

O=>data_int(0));

To improve design coding times VHDL and Verilog synthesis

macro libraries available to explicitly create these structures.

The input library macros are listed in Table 42. The I and IB

inputs to the macros are the external net connections.

Verilog Instantiation

IBUF_LVDS data0_p (.I(data[0]),

.O(data_int[0]));

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Verilog Instantiation

OBUF_LVDS data0_p

.O(data_p[0]));

INV data0_inv (.I(data_int[0],

Table 42: Input Library Macros

(.I(data_int[0]),

Name

Inputs

Outputs

IBUFDS_FD_LVDS

IBUFDS_FDE_LVDS

IBUFDS_FDC_LVDS

IBUFDS_FDCE_LVDS

IBUFDS_FDP_LVDS

IBUFDS_FDPE_LVDS

IBUFDS_FDR_LVDS

IBUFDS_FDRE_LVDS

IBUFDS_FDS_LVDS

IBUFDS_FDSE_LVDS

IBUFDS_LD_LVDS

IBUFDS_LDE_LVDS

IBUFDS_LDC_LVDS

IBUFDS_LDCE_LVDS

IBUFDS_LDP_LVDS

IBUFDS_LDPE_LVDS

I, IB, C

I, IB, CE, C

Q

.O(data_n_int[0]);

I, IB, C, CLR

I, IB, CE, C, CLR

I, IB, C, PRE

I, IB, CE, C, PRE

I, IB, C, R

OBUF_LVDS data0_n

.O(data_n[0]));

(.I(data_n_int[0]),

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the .ucf or .ncf file.

I, IB, CE, C, R

I, IB, C, S

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous Outputs

I, IB, CE, C, S

I, IB, G

If the outputs are synchronous (registered in the IOB) then

any IO_L#P|N pair can be used. If the outputs are asynchro-

nous (no output register), then they must use one of the

pairs that are part of the same IOB group at the end of a

ROW or COLUMN in the device.

I, IB, GE, G

I, IB, G, CLR

I, IB, GE, G, CLR

I, IB, G, PRE

I, IB, GE, G, PRE

The LVDS pairs that can be used as asynchronous outputs

are listed in the Virtex-E pinout tables. Some pairs are

marked as asynchronous-capable for all devices in that

package, and others are marked as available only for that

device in the package. If the device size might change at

some point in the product lifetime, then only the common

pairs for all packages should be used.

Creating LVDS Output Buffers

LVDS output buffers can be placed in a wide number of IOB

locations. The exact locations are dependent on the pack-

age used. The Virtex-E package information lists the possi-

ble locations as IO_L#P for the P-side and IO_L#N for the

N-side, where # is the pair number.

Adding an Output Register

All LVDS buffers can have an output register in the IOB. The

output registers must be in both the P-side and N-side IOBs.

All the normal IOB register options are available (FD, FDE,

FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,

LDE, LDC, LDCE, LDP, LDPE). The register elements can

be inferred or explicitly instantiated in the HDL code.

HDL Instantiation

Both output buffers are required to be instantiated in the

design and placed on the correct IO_L#P and IO_L#N loca-

tions. The IOB must have the same net source the following

pins, clock (C), set/reset (SR), output (O), output clock

enable (OCE). In addition, the output (O) pins must be

inverted with respect to each other, and if output registers

are used, the INIT states must be opposite values (one

HIGH and one LOW). Failure to follow these rules leads to

DRC errors in software.

Special care must be taken to insure that the D pins of the

registers are inverted and that the INIT states of the regis-

ters are opposite. The clock pin (C), clock enable (CE) and

set/reset (CLR/PRE or S/R) pins must connect to the same

source. Failure to do this leads to a DRC error in the soft-

ware.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the "map

-pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b"

is both inputs and outputs.

VHDL Instantiation

data0_p : OBUF_LVDS port map

(I=>data_int(0),

O=>data_p(0));

data0_inv: INV

(I=>data_int(0),

port map

O=>data_n_int(0));

To improve design coding times VHDL and Verilog synthe-

sis macro libraries have been developed to explicitly create

these structures. The output library macros are listed in

Table 43. The O and OB inputs to the macros are the exter-

nal net connections.

data0_n : OBUF_LVDS port map

(I=>data_n_int(0), O=>data_n(0));

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VHDL Instantiation

Table 43: Output Library Macros

data0_p:

(I=>data_int(0), T=>data_tri,

O=>data_p(0));

OBUFT_LVDS port map

Name

Inputs

D, C

Outputs

O, OB

OBUFDS_FD_LVDS

OBUFDS_FDE_LVDS

OBUFDS_FDC_LVDS

OBUFDS_FDCE_LVDS

OBUFDS_FDP_LVDS

OBUFDS_FDPE_LVDS

OBUFDS_FDR_LVDS

OBUFDS_FDRE_LVDS

OBUFDS_FDS_LVDS

OBUFDS_FDSE_LVDS

OBUFDS_LD_LVDS

OBUFDS_LDE_LVDS

OBUFDS_LDC_LVDS

OBUFDS_LDCE_LVDS

OBUFDS_LDP_LVDS

OBUFDS_LDPE_LVDS

DD, CE, C

D, C, CLR

D, CE, C, CLR

D, C, PRE

D, CE, C, PRE

D, C, R

data0_inv: INV port map

(I=>data_int(0), O=>data_n_int(0));

data0_n:

(I=>data_n_int(0), T=>data_tri,

O=>data_n(0));

OBUFT_LVDS port map

Verilog Instantiation

OBUFT_LVDS data0_p

.T(data_tri), .O(data_p[0]));

(.I(data_int[0]),

D, CE, C, R

D, C, S

INV

data0_inv (.I(data_int[0],

.O(data_n_int[0]);

OBUFT_LVDS data0_n

.T(data_tri), .O(data_n[0]));

(.I(data_n_int[0]),

D, CE, C, S

D, G

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the .ucf or .ncf file.

D, GE, G

D, G, CLR

D, GE, G, CLR

D, G, PRE

D, GE, G, PRE

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous 3-State Outputs

If the outputs are synchronous (registered in the IOB), then

any IO_L#P|N pair can be used. If the outputs are asynchro-

nous (no output register), then they must use one of the

pairs that are part of the same IOB group at the end of a

ROW or COLUMN in the device. This applies for either the

3-state pin or the data out pin.

Creating LVDS Output 3-State Buffers

LVDS output 3-state buffers can be placed in a wide number

of IOB locations. The exact locations are dependent on the

package used. The Virtex-E package information lists the

possible locations as IO_L#P for the P-side and IO_L#N for

the N-side, where # is the pair number.

LVDS pairs that can be used as asynchronous outputs are

listed in the Virtex-E pinout tables. Some pairs are marked

as "asynchronous capable" for all devices in that package,

and others are marked as available only for that device in

the package. If the device size might be changed at some

point in the product lifetime, then only the common pairs for

all packages should be used.

HDL Instantiation

Both output 3-state buffers are required to be instantiated in

the design and placed on the correct IO_L#P and IO_L#N

locations. The IOB must have the same net source the fol-

lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state

clock enable (TCE), output (O), output clock enable (OCE).

In addition, the output (O) pins must be inverted with

respect to each other, and if output registers are used, the

INIT states must be opposite values (one High and one

Low). If 3-state registers are used, they must be initialized to

the same state. Failure to follow these rules leads to DRC

errors in the software.

Adding Output and 3-State Registers

All LVDS buffers can have an output register in the IOB. The

output registers must be in both the P-side and N-side IOBs.

All the normal IOB register options are available (FD, FDE,

FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,

LDE, LDC, LDCE, LDP, LDPE). The register elements can

be inferred or explicitly instantiated in the HDL code.

Special care must be taken to insure that the D pins of the

registers are inverted and that the INIT states of the regis-

ters are opposite. The 3-state (T), 3-state clock enable

(CE), clock pin (C), output clock enable (CE) and set/reset

(CLR/PRE or S/R) pins must connect to the same source.

Failure to do this leads to a DRC error in the software.

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The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the "map

-pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b"

is both inputs and outputs.

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the .ucf or .ncf file.

To improve design coding times VHDL and Verilog synthe-

sis macro libraries have been developed to explicitly create

these structures. The input library macros are listed below.

The 3-state is configured to be 3-stated at GSR and when

the PRE,CLR,S or R is asserted and shares its clock enable

with the output register. If this is not desirable then the

library can be updated by the user for the desired function-

ality. The O and OB inputs to the macros are the external

net connections.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous Bidirectional

Buffers

If the output side of the bidirectional buffers are synchro-

nous (registered in the IOB), then any IO_L#P|N pair can be

used. If the output side of the bidirectional buffers are asyn-

chronous (no output register), then they must use one of the

pairs that is a part of the asynchronous LVDS IOB group.

This applies for either the 3-state pin or the data out pin.

Creating a LVDS Bidirectional Buffer

LVDS bidirectional buffers can be placed in a wide number

of IOB locations. The exact locations are dependent on the

package used. The Virtex-E package information lists the

possible locations as IO_L#P for the P-side and IO_L#N for

the N-side, where # is the pair number.

The LVDS pairs that can be used as asynchronous bidirec-

tional buffers are listed in the Virtex-E pinout tables. Some

pairs are marked as asynchronous capable for all devices in

that package, and others are marked as available only for

that device in the package. If the device size might change

at some point in the product’s lifetime, then only the com-

mon pairs for all packages should be used.

HDL Instantiation

Both bidirectional buffers are required to be instantiated in

the design and placed on the correct IO_L#P and IO_L#N

locations. The IOB must have the same net source the fol-

lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state

clock enable (TCE), output (O), output clock enable (OCE).

In addition, the output (O) pins must be inverted with

respect to each other, and if output registers are used, the

INIT states must be opposite values (one HIGH and one

LOW). If 3-state registers are used, they must be initialized

to the same state. Failure to follow these rules leads to DRC

errors in the software.

Adding Output and 3-State Registers

All LVDS buffers can have an output and input registers in

the IOB. The output registers must be in both the P-side and

N-side IOBs, the input register is only in the P-side. All the

normal IOB register options are available (FD, FDE, FDC,

FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,

LDC, LDCE, LDP, LDPE). The register elements can be

inferred or explicitly instantiated in the HDL code. Special

care must be taken to insure that the D pins of the registers

are inverted and that the INIT states of the registers are

opposite. The 3-state (T), 3-state clock enable (CE), clock

pin (C), output clock enable (CE), and set/reset (CLR/PRE

or S/R) pins must connect to the same source. Failure to do

this leads to a DRC error in the software.

VHDL Instantiation

data0_p:

IOBUF_LVDS port map

(I=>data_out(0), T=>data_tri,

IO=>data_p(0), O=>data_int(0));

data0_inv: INV

port map

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the "map

-pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b"

is both inputs and outputs. To improve design coding times

VHDL and Verilog synthesis macro libraries have been

developed to explicitly create these structures. The bidirec-

tional I/O library macros are listed in Table 44. The 3-state is

configured to be 3-stated at GSR and when the PRE,CLR,S

or R is asserted and shares its clock enable with the output

and input register. If this is not desirable then the library can

be updated be the user for the desired functionality. The I/O

and IOB inputs to the macros are the external net connec-

tions.

(I=>data_out(0),

O=>data_n_out(0));

data0_n : IOBUF_LVDS port map

(I=>data_n_out(0), T=>data_tri,

IO=>data_n(0), O=>open);

Verilog Instantiation

IOBUF_LVDS data0_p(.I(data_out[0]),

.T(data_tri), .IO(data_p[0]),

.O(data_int[0]);

INV

data0_inv (.I(data_out[0],

.O(data_n_out[0]);

IOBUF_LVDS

data0_n(.I(data_n_out[0]),.T(data_tri),.

IO(data_n[0]).O());

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Table 44: Bidirectional I/O Library Macros

Name

Inputs

D, T, C

Bidirectional

IO, IOB

Outputs

IOBUFDS_FD_LVDS

IOBUFDS_FDE_LVDS

IOBUFDS_FDC_LVDS

IOBUFDS_FDCE_LVDS

IOBUFDS_FDP_LVDS

IOBUFDS_FDPE_LVDS

IOBUFDS_FDR_LVDS

IOBUFDS_FDRE_LVDS

IOBUFDS_FDS_LVDS

IOBUFDS_FDSE_LVDS

IOBUFDS_LD_LVDS

IOBUFDS_LDE_LVDS

IOBUFDS_LDC_LVDS

IOBUFDS_LDCE_LVDS

IOBUFDS_LDP_LVDS

IOBUFDS_LDPE_LVDS

Q

D, T, CE, C

D, T, C, CLR

D, T, CE, C, CLR

D, T, C, PRE

D, T, CE, C, PRE

D, T, C, R

D, T, CE, C, R

D, T, C, S

D, T, CE, C, S

D, T, G

D, T, GE, G

D, T, G, CLR

D, T, GE, G, CLR

D, T, G, PRE

D, T, GE, G, PRE

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

05/19/03

07/29/04

Initial Xilinx release.

1.1

•

Section Input/Output Block, page 1: Last paragraph, excepted certain I/O standards

from automatic addition of clamping diodes at the inputs.

Section Input Path, page 2: Last paragraph, qualified the presence of optional pull-

up/pull-down resistors on all inputs to "all user I/O inputs."

•

Section Block SelectRAM, page 5: Last paragraph, added reference to XAPP130.

Section Configuration, page 11: Added updated information regarding the optional

special use of certain pins.

•

Section Configuration Modes: On page 12 (two places), added recommendation to

actively drive configuration mode pins rather than leave tem floating.

•

Figure 18, page 16: Updated flowchart.

Section Boundary-Scan Mode, page 17: Added information about required control of

PROGRAM pin, and added a reference to XAPP139.

•

Section Duty Cycle Correction Property, page 21: Removed the statement that

when duty-cycle correction deactivates, the output clock has the same duty cycle as

the source clock.

Table 36, page 43: Correct V Min from 0.7 x V

to 0.65 x V

.

CCO

IH

CCO

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0

DS098-3 (v1.1) July 29, 2004

Advance Product Specification

QPro Virtex-E Electrical Characteristics

Based on preliminary characterization. Further changes are not expected.

All guaranteed specifications are representative of worst-case supply voltage and junction temperature conditions. Some

specifications also include best-case timing predictions. Best-case timing specifications are for design guidance and are not

guaranteed.

DC Characteristics

Absolute Maximum Ratings

(1)

Symbol

Description

Internal Supply voltage relative to GND

Supply voltage relative to GND

Units

V

–0.5 to 2.0

–0.5 to 4.0

CCINT

V

CCO

V

Input Reference Voltage

V

REF

(3)

IN

V

Input voltage relative to GND

–0.5 to V

+ 0.5

V

CCO

V

Voltage applied to 3-state output

Longest Supply Voltage Rise Time from 0 V - 1.71 V

–0.5 to 4.0

V

TS

V

50

–65 to +150

+125

ms

°C

CC

T

Storage temperature (ambient)

STG

(2)

T

Junction temperature

Plastic packages

Ceramic packages

J

+150

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.

2. For soldering guidelines and thermal considerations, see the Device Packaging infomation on the Xilinx website.

3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the

device is not PCI compliant.

Recommended Operating Conditions

Symbol

Description

Internal Supply voltage relative to GND, T = –55°C to +125°C

Min

1.71

1.2

-

Max

1.89

3.6

Units

V

Military

CCINT

J

V

Supply voltage relative to GND, T = –55°C to +125°C

V

CCO

J

T

Input signal transition time

250

ns

IN

T

Operating Temperature Range

XQV600E

XQV1000E

XQV2000E

–55

–40

+125

°C

C

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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DC Characteristics Over Recommended Operating Conditions

Symbol

Description

Voltage

Device

Min

Max Units

V

Data Retention V

CCINT

DRINT

All

1.5

-

V

(below which configuration data might be lost)

Data Retention V Voltage

V

DRIO

CCO

All

1.2

(below which configuration data might be lost)

(1)

I

Quiescent V

supply current

CCINT

XQV600E

-

400

500

1100

2

mA

µA

CCINTQ

XQV1000E

-

XQV2000E

-

(1)

I

Quiescent V

supply current

CCO

All

-

–10

-

CCOQ

I

Input or output leakage current

+10

8

L

C

Input capacitance (sample tested)

pF

IN

I

Pad pull-up (when selected) @ V = 0V, V = 3.3V (sample tested)

CCO

Note 2 0.25

mA

RPU

RPD

in

I

Pad pull-down (when selected) @ V = 3.6V (sample tested)

in

Notes:

1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.

2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors

do not guarantee valid logic levels when input pins are connected to other circuits.

Power-On Power Supply Requirements

Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual

current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal

1

power supply voltage of the device from 0 V. The fastest ramp rate is 0V to nominal voltage in 2 ms, and the slowest allowed

ramp rate is 0V to nominal voltage in 50 ms. For more details on power supply requirements, see XAPP158.

2

3

Description

Temperature

T = 0°C to +125 °C

Min

1

Units

Minimum required current supply

A

J

T = –40°C to 0°C

2

J

T = –55°C to –40°C

2.5

J

Notes:

1. Ramp rate used for this specification is from 0-1.8V DC. Peak current occurs on or near the internal power-on reset threshold and

lasts for less than 3 ms.

2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.

3. Larger currents might result if ramp rates are forced to be faster.

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DC Input and Output Levels

Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended

OH

IL

IH

OL

operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that

OL

OH

all standards meet their specifications. The selected standards are tested at minimum V

with the respective V and

CCO

OL

V

voltage levels shown. Other standards are sample tested.

OH

V

I

OH

IL

IH

OL

OH

OL

Input/Output

Standard

V, Min

– 0.5

V, Max

V, Min

2.0

V, Max

3.6

V, Max

0.4

V, Min

2.4

mA

24

mA

– 24

– 12

– 8

(1)

LVTTL

0.8

0.7

LVCMOS2

LVCMOS18

PCI, 3.3V

GTL

1.7

2.7

0.4

1.9

12

35% V

30% V

65% V

1.95

0.4

V – 0.4

CCO

8

CCO

50% V

V

+ 0.5 10% V

90% V

CCO

Note 2

40

Note 2

n/a

CCO

V

– 0.05

– 0.1

– 0.2

V

+ 0.05

+ 0.1

+ 0.2

3.6

0.4

0.6

0.4

n/a

REF

GTL+

V

3.6

36

n/a

REF

HSTL I

V

– 0.4

8

–8

CCO

HSTL III

HSTL IV

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

CTT

V

– 0.4

24

–8

48

–8

V

– 0.6

V

+ 0.6

+ 0.8

+ 0.61

+ 0.80

+ 0.4

8

–8

REF

– 0.8

– 0.61

– 0.80

– 0.4

16

–16

–7.6

–15.2

–8

REF

V

7.6

15.2

8

REF

V

REF

AGP

10% V

90% V

Note 2

CCO

Notes:

1. V_OLand V_OHfor lower drive currents are sample tested.

2. Tested according to the relevant specifications.

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LVDS DC Specifications

Symbol

DC Parameter

Supply Voltage

Conditions

Min

Typ

Max Units

V

2.375

2.5

2.625

1.6

V

CCO

V

Output High Voltage for Q and Q

Output Low Voltage for Q and Q

R = 100Ω across Q and Q signals

1.25 1.425

OH

T

V

R = 100Ω across Q and Q signals

0.9

1.075 1.25

OL

T

Differential Output Voltage (Q – Q),

Q = High (Q – Q), Q = High

V

R = 100Ω across Q and Q signals

250

350 450

mV

V

ODIFF

T

V

Output Common-Mode Voltage

R = 100Ω across Q and Q signals

1.125 1.25 1.375

OCM

IDIFF

T

Differential Input Voltage (Q – Q),

Q = High (Q – Q), Q = High

V

Common-mode input voltage = 1.25V 100

Differential input voltage = ±350 mV 0.2

350

NA

2.2

mV

V

Input Common-Mode Voltage

1.25

ICM

Notes:

1. Refer to the Design Consideration section for termination schematics.

LVPECL DC Specifications

These values are valid at the output of the source termination pack shown under LVPECL (Module 2), with a 100Ω

differential load only. The V levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of

OH

lower common-mode ranges. The following table summarizes the DC output specifications of LVPECL.

DC Parameter

Min

Max

Min

Max

Min

Max

Units

V

3.0

3.3

3.6

V

CCO

V

1.8

0.96

1.49

0.86

0.3

2.11

1.27

2.72

2.125

-

1.92

1.06

1.49

0.86

0.3

2.28

1.43

2.72

2.125

-

2.13

1.30

1.49

0.86

0.3

2.41

1.57

2.72

2.125

-

OH

V

OL

V

IH

V

IL

Differential Input Voltage

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Virtex-E Switching Characteristics

Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are

representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the

static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing

parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex-E

devices unless otherwise noted.

IOB Input Switching Characteristics

Input delays associated with the pad are specified below for LVTTL levels. For other standards, adjust the delays with the

values shown in IOB Input Switching Characteristics Standard Adjustments, page 6.

(3)

Best Case

Min

Worst Case

Units

(2)

Symbol

Description

Device

Max

Min

Max

Propagation Delays

T

Pad to I output, no delay

Pad to I output, with delay

All

0.43

0.51

0.55

-

0.8

1.0

1.1

ns

IOPI

T

XQV600E

XQV1000E

XQV2000E

IOPID

Pad to output IQ via transparent

latch, no delay

T

All

0.8

1.6

IOPLI

T

Pad to output IQ via transparent

latch, with delay

XQV600E

XQV1000E

XQV2000E

1.55

1.59

-

3.7

3.8

ns

IOPLID

Sequential Delays, Clock CLK

T

Minimum Pulse Width, High

Minimum Pulse Width, Low

Clock CLK to output IQ

0.56

0.18

1.4

0.7

ns

CH

T

All

CL

T

-

IOCKIQ

Setup and Hold Times with respect to Clock at IOB Input Register

T

/

Pad, no delay

ns

IOPICK

All

0.69 / 0

1.5 / 0

-

IOICKP

T

/

Pad, with delay

XQV600E

XQV1000E

XQV2000E

All

1.49 / 0

-

3.5 / 0

-

ns

IOPICKD

IOICKPD

1.53 / 0

3.6 / 0

T

/

ICE input

0.28 / 0.01

0.7 / 0.01

IOICECK

T

IOCKICE

T

SR input (IFF, synchronous)

All

0.38

-

1.0

-

ns

IOSRCKI

Set/Reset Delays

T

SR input to IQ (asynchronous)

GSR to output IQ

All

0.54

3.88

-

1.4

9.7

ns

IOSRIQ

T

GSRQ

Notes:

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

2. Input timing i for LVTTL is measured at 1.4V. For other I/O standards, see Table 2.

3. Best Case numbers are Advance specification numbers. See DC Characteristics, page 1 for a description.

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IOB Input Switching Characteristics Standard Adjustments

(1)

(2)

Symbol

Description

Standard

Min

Max

Units

Data Input Delay Adjustments

T

Standard-specific data input delay

adjustments

LVTTL

0.0

ns

ILVTTL

T

LVCMOS2

LVCMOS18

LVDS

–0.02

0.12

0.0

ILVCMOS2

T

+0.20

+0.15

+0.08

–0.11

+0.14

+0.04

+0.10

+0.04

ILVCMOS18

T

0.00

ILVDS

T

LVPECL

PCI, 33 MHz, 3.3V

PCI, 66 MHz, 3.3V

GTL

0.00

ILVPECL

IPCI33_3

IPCI66_3

T

–0.05

+0.10

+0.06

+0.02

–0.04

–0.02

+0.01

–0.03

T

IGTL

IGTLPLUS

T

GTL+

T

HSTL

IHSTL

T

SSTL2

ISSTL2

ISSTL3

SSTL3

T

CTT

ICTT

T

AGP

IAGP

Notes:

1. Input timing i for LVTTL is measured at 1.4V. For other I/O standards, see Table 2.

2. Best Case Numbers are Advance product specification numbers. See DC Characteristics, page 1 for a description.

Q

D

CE

T

TCE

Weak

Keeper

SR

PAD

O

Q

D

CE

OCE

OBUFT

SR

I

IQ

Programmable

Delay

Q

D

CE

IBUF

Vref

SR

CLK

ICE

ds022_02_091300

Figure 1: Virtex-E Input/Output Block (IOB)

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IOB Output Switching Characteristics, Figure 1

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 8.

(1)

Best Case

Worst Case

(2)

(3)

Symbol

Description

Min

Max

Min

Max

Units

Propagation Delays

T_IOOP

T_IOOLP

O input to Pad

1.04

-

2.9

3.4

ns

O input to Pad via transparent latch

1.24

3-State Delays

T_IOTHZ

T input to Pad high-impedance⁽²⁾

0.73

1.13

0.86

1.26

1.94

-

1.9

3.1

2.2

3.4

4.9

ns

T_IOTON

T input to valid data on Pad

T_IOTLPHZ

T_IOTLPON

T_GTS

T input to Pad high-impedance via transparent latch ⁽²⁾

T input to valid data on Pad via transparent latch

GTS to Pad high impedance⁽²⁾

Sequential Delays, Clock CLK

T_CH

T_CL

Minimum Pulse Width, High

0.56

0.97

0.77

1.17

1.4

2.9

2.2

3.4

ns

Minimum Pulse Width, Low

T_IOCKP

T_IOCKHZ

T_IOCKON

Clock CLK to Pad

-

Clock CLK to Pad high-impedance (synchronous)⁽²⁾

Clock CLK to valid data on Pad (synchronous)

Setup and Hold Times before/after Clock CLK

T_IOOCK

T_IOCKO

/

O input

0.43 / 0

0.28 / 0

0.40 / 0

0.26 / 0

0.30 / 0

0.38 / 0

-

1.1 / 0

0.7 / 0

1.0 / 0

0.7 / 0

0.8 / 0

1.0 / 0

-

ns

T_IOOCECK

T_IOCKOCE

/

OCE input

T_IOSRCKO

T_IOCKOSR

/

SR input (OFF)

T_IOTCK

T_IOCKT

/

3-State Setup Times, T input

3-State Setup Times, T_CEinput

3-State Setup Times, SR input (T_FF

T_IOTCECK

T_IOCKTCE

/

T_IOSRCKT

T_IOCKTSR

/

)

Set/Reset Delays

T_IOSRP

T_IOSRHZ

T_IOSRON

T_IOGSRQ

SR input to Pad (asynchronous)

1.30

1.08

1.48

3.88

-

3.5

2.7

3.9

9.7

ns

SR input to Pad high-impedance (asynchronous)⁽²⁾

SR input to valid data on Pad (asynchronous)

GSR to Pad

Notes:

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

2. 3-state turn-off delays should not be adjusted.

3. Best Case Numbers are Advance product specification numbers. See DC Characteristics, page 1 for a description.

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IOB Output Switching Characteristics Standard Adjustments

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays by the values shown.

Symbol

Description

Standard

Min⁽¹⁾

Max

Units

Output Delay Adjustments

T_{OLVTTL_S2}

T_{OLVTTL_S4}

T_{OLVTTL_S6}

T_{OLVTTL_S8}

T_{OLVTTL_S12}

T_{OLVTTL_S16}

T_{OLVTTL_S24}

T_{OLVTTL_F2}

T_{OLVTTL_F4}

T_{OLVTTL_F6}

T_{OLVTTL_F8}

T_{OLVTTL_F12}

T_{OLVTTL_F16}

T_{OLVTTL_F24}

T_{OLVCMOS_2}

T_{OLVCMOS_18}

T_OLVDS

Standard-specific adjustments for output delays terminating at

pads (based on standard capacitive load, Csl)

LVTTL, Slow, 2 mA

4 mA

4.2

2.5

+14.7

+7.5

ns

6 mA

1.8

+4.8

8 mA

1.2

+3.0

12 mA

1.0

+1.9

16 mA

0.9

+1.7

24 mA

0.8

+1.3

LVTTL, Fast, 2 mA

4 mA

1.9

+13.1

+5.3

0.7

6 mA

0.20

0.10

0.0

+3.1

8 mA

+1.0

12 mA

0.0

16 mA

–0.10

0.10

–0.39

–0.20

0.50

0.10

0.6

–0.05

–0.20

+0.09

+0.7

24 mA

LVCMOS2

LVCMOS18

LVDS

–1.2

T_OLVPECL

T_{OPCI33_3}

T_{OPCI66_3}

T_OGTL

LVPECL

PCI, 33 MHz, 3.3V

PCI, 66 MHz, 3.3V

GTL

–0.41

+2.3

–0.41

+0.49

+0.8

T_OGTLP

GTL+

0.7

T_{OHSTL_I}

HSTL I

0.10

–0.10

–0.20

–0.10

–0.20

–0.30

0.0

–0.51

–0.91

–1.01

–0.51

–0.91

–0.51

–1.01

–0.61

–0.91

T_{OHSTL_III}

T_{OHSTL_IV}

T_{OSSTL2_I}

T_{OSSTL2_II}

T_{OSSTL3_I}

T_{OSSTL3_II}

T_OCTT

HSTL III

HSTL IV

SSTL2 I

SSTL2 II

SSTL3 I

SSTL3 II

CTT

T_OAGP

AGP

–0.1

Notes:

1. The numbers for Min are Best Case Advance product specification numbers. See DC Characteristics, page 1 for a description.

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Calculation of T

as a Function of Capacitance

ioop

T

is the propagation delay from the O Input of the IOB to

For other capacitive loads, use the formulas below to calcu-

ioop

the pad. The values for T

are based on the standard

late the corresponding T

:

ioop

capacitive load (C ) for each I/O standard as listed in

Table 1.

sl

T

= T

+ T

+ (C

– C ) * fl

load sl

ioop

opadjust

where:

Table 1: Constants for Use in Calculation of T

ioop

T

is reported above in the Output Delay

Adjustment section.

opadjust

Standard

LVTTL Fast Slew Rate, 2 mA drive

LVTTL Fast Slew Rate, 4 mA drive

LVTTL Fast Slew Rate, 6 mA drive

LVTTL Fast Slew Rate, 8 mA drive

LVTTL Fast Slew Rate, 12 mA drive

LVTTL Fast Slew Rate, 16 mA drive

LVTTL Fast Slew Rate, 24 mA drive

LVTTL Slow Slew Rate, 2 mA drive

LVTTL Slow Slew Rate, 4 mA drive

LVTTL Slow Slew Rate, 6 mA drive

LVTTL Slow Slew Rate, 8 mA drive

LVTTL Slow Slew Rate, 12 mA drive

LVTTL Slow Slew Rate, 16 mA drive

LVTTL Slow Slew Rate, 24 mA drive

LVCMOS2

C_sl(pF) fl (ns/pF)

35

10

0

0.41

0.20

C

is the capacitive load for the design.

load

Table 2: Delay Measurement Methodology

0.13

Meas.

Point

V_REF

V_L

V_H

(Typ)⁽²⁾

(1)

Standard

LVTTL

0.079

0.044

0.043

0.033

0.41

0

3

1.4

-

LVCMOS2

PCI33_3

PCI66_3

GTL

0

2.5

1.125

-

Per PCI Spec

-

0.20

V

_REF– 0.2 V_REF+ 0.2

V_REF

0.80

1.0

0.75

0.90

1.5

1.25

1.5

0.10

GTL+

V_REF+ 0.2

V_REF+ 0.5

V_REF+ 1.0

V_REF+ 0.75

V_REF+ 0.2

V_REF– 0.2

V_REF– 0.5

V_REF– 1.0

V_REF– 0.75

V_REF– 0.2

0.086

0.058

0.050

0.048

0.041

0.050

0.033

0.014

0.017

0.022

0.016

0.014

0.028

0.016

0.029

0.016

0.035

0.037

HSTL Class I

HSTL Class III

HSTL Class IV

SSTL3 I & II

SSTL2 I & II

CTT

LVCMOS18

PCI 33 MHZ 3.3V

AGP

V_REF

+

Per

AGP

Spec

V_REF

–

PCI 66 MHz 3.3V

(0.2xV_CCO

)

(0.2xV_CCO

)

GTL

LVDS

1.2 + 0.125

1.6 + 0.3

1.2

1.6

1.2 – 0.125

1.6 – 0.3

GTL+

0

LVPECL

HSTL Class I

20

30

20

10

Notes:

HSTL Class III

1. Input waveform switches between V_Land V_H.

HSTL Class IV

2. Measurements are made at V_REF(Typ), Maximum, and

Minimum. Worst-case values are reported.

SSTL2 Class I

I/O parameter measurements are made with the capacitance

values shown in Table 14. See the Application Examples

(Module 2) for appropriate terminations.

SSTL2 Class II

SSTL3 Class I

I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

SSTL3 Class II

CTT

AGP

Notes:

1. I/O parameter measurements are made with the capacitance

values shown above. See the Application Examples

(Module 2) for appropriate terminations.

2. I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

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Clock Distribution Switching Characteristics

(1)

Symbol

Description

Min

Max

Units

GCLK IOB and Buffer

T

Global Clock PAD to output.

0.38

0.11

0.7

ns

GPIO

T

Global Clock Buffer I input to O output

0.50

GIO

Notes:

1. The numbers for Min are Best Case Advance product specification numbers. See DC Characteristics, page 1 for a description.

I/O Standard Global Clock Input Adjustments

(1)

(2)

Symbol

Data Input Delay Adjustments

Description

Standard

Min

Max

Units

T

Standard-specific global clock input delay

adjustments

LVTTL

LVCMOS2

LVCMOS18

LVDS

0.0

–0.02

0.12

0.23

–0.05

0.20

0.18

0.21

0.18

0.22

0.21

0.0

ns

GPLVTTL

T

GPLVCMOS2

T

0.20

0.38

0.08

–0.11

0.37

0.27

0.33

0.27

GPLVCMOS18

T

GLVDS

T

LVPECL

PCI, 33 MHz, 3.3V

PCI, 66 MHz, 3.3V

GTL

GLVPECL

GPPCI33_3

GPPCI66_3

T

GPGTL

T

GTL+

GPGTLP

GPHSTL

T

HSTL

T

SSTL2

GPSSTL2

GPSSTL3

SSTL3

T

CTT

GPCTT

T

AGP

GPAGP

Notes:

1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see Table 2.

2. The numbers for Min are Best Case Advance product specification numbers. See DC Characteristics, page 1 for a description.

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CLB Switching Characteristics

Delays originating at F/G inputs vary slightly according to the input used, see Figure 2. The values listed below are

worst-case. Precise values are provided by the timing analyzer.

Best Case⁽¹⁾

Min Max

Worst Case⁽²⁾

Description

Symbol

Min

Max

Units

Combinatorial Delays

T_ILO

T_IF5

4-input function: F/G inputs to X/Y outputs

5-input function: F/G inputs to F5 output

5-input function: F/G inputs to X output

6-input function: F/G inputs to Y output via F6 MUX

6-input function: F5IN input to Y output

0.19

0.36

0.35

0.04

-

0.47

0.9

ns

T_IF5X

T_IF6Y

T_F5INY

0.9

1.0

0.22

Incremental delay routing through transparent latch to

XQ/YQ outputs

T_IFNCTL

T_BYYB

0.27

0.19

-

0.8

ns

BY input to YB output

0.51

Sequential Delays

T_CKO

FF Clock CLK to XQ/YQ outputs

Latch Clock CLK to XQ/YQ outputs

0.34

0.40

-

1.0

ns

T_CKLO

Setup and Hold Times before/after Clock CLK

T_ICK/ T_CKI4-input function: F/G Inputs

0.39 / 0

0.55 / 0

-

1.1 / 0

1.5 / 0

-

ns

T_IF5CK

T_CKIF5

/

5-input function: F/G inputs

6-input function: F5IN input

6-input function: F/G inputs via F6 MUX

BX/BY inputs

T_F5INCK

T_CKF5IN

/

0.27 / 0

0.58 / 0

0.25 / 0

0.28 / 0

0.24 / 0

-

0.8 / 0

1.6 / 0

0.8 / 0

0.7 / 0

0.6 / 0

-

ns

T_IF6CK

T_CKIF6

/

T_DICK

/

T_CKDI

T_CECK

/

CE input

T_CKCE

T_{RCK /}

T_CKR

SR/BY inputs (synchronous)

Clock CLK

T_CH

Minimum Pulse Width, High

Minimum Pulse Width, Low

1.4

-

1.4

-

ns

T_CL

Set/Reset

T_RPW

Minimum Pulse Width, SR/BY inputs

0.94

0.39

-

2.4

-

ns

T_RQ

Delay from SR/BY inputs to XQ/YQ outputs (asynchronous)

Toggle Frequency (MHz) (for export control)

-

1.0

F_TOG

357.2

MHz

Notes:

1. Best Case Numbers are Advance product specification numbers. See DC Characteristics, page 1 for a description.

2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

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COUT

CY

YB

Y

G4

G3

G2

G1

I3

I2

I1

I0

O

LUT

WE

INIT

D Q

CE

YQ

DI

0

1

REV

BY

XB

F5IN

F6

CY

F5

X

F5

BY DG

CK WSO

WE

BX

WSH

A4

DI

INIT

D Q

CE

XQ

BX

DI

WE

I3

I2

I1

I0

F4

F3

F2

F1

REV

O

LUT

0

1

SR

CLK

CE

ds022_05_092000

CIN

Figure 2: Detailed View of Virtex-E Slice

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CLB Arithmetic Switching Characteristics

Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment

listed. Precise values are provided by the timing analyzer.

(1)

(2)

Best Case

Worst Case

Symbol

Description

Min

Max

Min

Max

Units

Combinatorial Delays

T

F operand inputs to X via XOR

F operand input to XB output

F operand input to Y via XOR

F operand input to YB output

F operand input to COUT output

G operand inputs to Y via XOR

G operand input to YB output

G operand input to COUT output

BX initialization input to COUT

CIN input to X output via XOR

CIN input to XB

0.32

0.35

0.59

0.48

0.37

0.34

0.47

0.36

0.19

0.27

0.02

0.26

0.16

0.05

-

0.8

0.9

ns

OPX

T

OPXB

T

1.5

OPY

T

1.3

OPYB

T

1.0

OPCYF

T

0.9

OPGY

OPGYB

OPCYG

T

1.3

T

1.0

T

0.57

0.7

BXCY

T

CINX

T

0.08

0.7

CINXB

T

CIN input to Y via XOR

CINY

T

CIN input to YB

0.43

0.15

CINYB

T

CIN input to COUT output

BYP

Multiplier Operation

T

F1/2 operand inputs to XB output via AND

F1/2 operand inputs to YB output via AND

F1/2 operand inputs to COUT output via AND

G1/2 operand inputs to YB output via AND

G1/2 operand inputs to COUT output via AND

0.10

0.28

0.17

0.20

0.09

-

0.39

0.8

ns

FANDXB

T

FANDYB

FANDCY

GANDYB

GANDCY

T

0.51

0.7

T

0.34

Setup and Hold Times before/after Clock CLK

T

/T

CIN input to FFX

CIN input to FFY

0.47 / 0

0.49 / 0

-

1.3 / 0

-

ns

CCKX CKCX

/T

CCKY CKCY

Notes:

1. Best Case Numbers are Advance product specification numbers. See DC Characteristics, page 1 for a description.

2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

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CLB Distributed RAM Switching Characteristics

(1)

Best Case

Worst Case

(2)

Description

Symbol

Min

Max

Min

Max

Units

Sequential Delays

T

Clock CLK to X/Y outputs (WE active) 16 x 1 mode

Clock CLK to X/Y outputs (WE active) 32 x 1 mode

0.67

0.84

-

1.7

2.1

ns

SHCKO16

SHCKO32

Shift-Register Mode

Clock CLK to X/Y outputs

Setup and Hold Times before/after Clock CLK

T

1.25

-

3.2

ns

REG

T

/T

F/G address inputs

BX/BY data inputs (DIN)

CE input (WE)

0.19 / 0

0.24 / 0

0.29 / 0

-

0.47 / 0

0.6 / 0

0.8 / 0

-

ns

AS AH

T

/T

DS DH

T

/T

WS WH

Shift-Register Mode

T

BX/BY data inputs (DIN)

CE input (WS)

0.24 / 0

0.29 / 0

-

0.6 / 0

0.8 / 0

-

ns

SHDICK

T

SHCECK

Clock CLK

T

Minimum Pulse Width, High

0.96

1.92

-

2.4

4.8

-

ns

WPH

T

Minimum Pulse Width, Low

WPL

T

Minimum clock period to meet address write cycle time

WC

Shift-Register Mode

T

Minimum Pulse Width, High

Minimum Pulse Width, Low

1.0

-

2.4

-

ns

SRPH

T

SRPL

Notes:

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

2. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description.

RAMB4_S#_S#

WEA

ENA

RSTA

DOA[#:0]

CLKA

ADDRA[#:0]

DIA[#:0]

WEB

ENB

RSTB

DOB[#:0]

CLKB

ADDRB[#:0]

DIB[#:0]

ds022_06_121699

Figure 3: Dual-Port Block SelectRAM

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Block RAM Switching Characteristics

(1)

Best Case

Worst Case

(2)

Description

Symbol

Min

Max

Min

Max

Units

Sequential Delays

T

Clock CLK to DOUT output

0.63

-

3.5

ns

BCKO

Setup and Hold Times before Clock CLK

T

/T

ADDR inputs

DIN inputs

EN input

0.42 / 0

0.97 / 0

0.9 / 0

-

1.1 / 0

2.5 / 0

2.3 / 0

2.2 / 0

-

ns

BACK BCKA

T

/T

BDCK BCKD

T

/T

BECK BCKE

T

/T

RST input

WEN input

BRCK BCKR

T

/T

0.86 / 0

BWCK BCKW

Clock CLK

T

Minimum Pulse Width, High

0.6

1.2

-

1.5

3.0

-

ns

BPWH

T

Minimum Pulse Width, Low

BPWL

BCCS

T

CLKA -> CLKB setup time for different ports

Notes:

1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but

if a "0" is listed, there is no positive hold time.

2. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description.

TBUF Switching Characteristics

Best Case

Worst Case

(1)

Description

Symbol

Min

Max

Min

Max

Units

Combinatorial Delays

T

IN input to OUT output

0.0

-

0 .0

0.11

ns

IO

T

TRI input to OUT output high-impedance

TRI input to valid data on OUT output

0.05

OFF

T

ON

Notes:

1. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description.

JTAG Test Access Port Switching Characteristics

Symbol

Description

TMS and TDI Setup times before TCK

TMS and TDI Hold times after TCK

Output delay from clock TCK to output TDO

Maximum TCK clock frequency

Min

4.0

2.0

-

Max

-

Units

ns

T

TAPTK

T

-

ns

TCKTAP

TCKTDO

T

11.0

33

ns

F

-

MHz

TCK

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Virtex-E Pin-to-Pin Output Parameter Guidelines

Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are

expressed in nanoseconds unless otherwise noted.

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL

Best Case

Worst Case

(1)

(4)

Symbol

Description

Device

Min

Max

Min

Max

3.1

Units

ns

T

LVTTL Global Clock Input to Output Delay using

Output Flip-flop, 12 mA, Fast Slew Rate, with

DLL. For data output with different standards,

adjust the delays with the values shown in IOB

Output Switching Characteristics Standard

Adjustments, page 8.

XQV600E

XQV1000E

XQV2000E

1.0

-

ICKOFDLL

3.1

ns

3.1

ns

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and

where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2. Output timing is measured at 50% V_CCthreshold with 35 pF external capacitive load. For other I/O standards and different loads, see

Table 1 and Table 2.

3. DLL output jitter is already included in the timing calculation.

4. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description.

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL

Best Case

Worst Case

1

(4)

Symbol

Description

Device

Min

Max

Min

Max

4.9

Units

ns

T

LVTTL Global Clock Input to Output Delay using

Output Flip-flop, 12 mA, Fast Slew Rate, without

DLL. For data output with different standards,

adjust the delays with the values shown in IOB

Output Switching Characteristics Standard

Adjustments, page 8.

XQV600E

XQV1000E

XQV2000E

1.6

1.7

1.8

-

ICKOF

5.0

5.2

ns

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and

where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2. Output timing is measured at 50% V_CCthreshold with 35 pF external capacitive load. For other I/O standards and different loads, see

Table 1 and Table 2.

3. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description.

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Virtex-E Pin-to-Pin Input Parameter Guidelines

Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are

expressed in nanoseconds unless otherwise noted.

Global Clock Set-Up and Hold for LVTTL Standard, with DLL

Best Case

Worst Case

(1)

(4)

Symbol

/T

Description

Device

Min

Max

Min

Max

Units

ns

T

No Delay. Global Clock and IFF, with

DLL.

XQV600E

1.5 / –0.4

-

1.7 / –0.4

PSDLL PHDLL

XQV1000E 1.5 / –0.4

XQV2000E 1.5 / –0.4

ns

Input Setup and Hold Time Relative to

Global Clock Input Signal for LVTTL

Standard. For data input with different

standards, adjust the setup time delay

by the values shown in IOB Input

Switching Characteristics Standard

Adjustments, page 6.

ns

Notes:

1. IFF = Input Flip-Flop or Latch.

2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured

relative to the Global Clock input signal with the slowest route and heaviest load.

3. DLL output jitter is already included in the timing calculation.

4. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description.

Global Clock Set-Up and Hold for LVTTL Standard, without DLL

Best Case

Worst Case

(1)

(4)

Symbol

/T

Description

Device

Min

Max

Min

Max

Units

ns

T

Full Delay

XQV600E

XQV1000E

XQV2000E

2.1 / 0

2.3 / 0

2.5 / 0

-

2.1 / 0

2.3 / 0

2.5 / 0

PSFD PHFD

Global Clock and IFF, without DLL

ns

Input Setup and Hold Time Relative to

Global Clock Input Signal for LVTTL

Standard. For data input with different

standards, adjust the setup time delay

by the values shown in IOB Input

Switching Characteristics Standard

Adjustments, page 6.

ns

Notes:

1. IFF = Input Flip-Flop or Latch.

2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured

relative to the Global Clock input signal with the slowest route and heaviest load.

3. DLL output jitter is already included in the timing calculation.

4. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description.

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DLL Timing Parameters

Switching parameters testing is modeled after testing methods specified by MIL-M-38510/605; all devices are 100 percent

functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are

derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended

operating conditions.

Description

Symbol

FCLKINHF

FCLKINLF

F_CLKIN

Min

60

Max

Units

MHz

ns

Input Clock Frequency (CLKDLLHF)

Input Clock Frequency (CLKDLL)

Input Clock Low/High Pulse Width

275

25

135

T

≥ 25 MHz

≥ 50 MHz

≥100 MHz

≥ 150 MHz

≥ 200 MHz

≥ 250 MHz

≥ 300 MHz

5.0

3.0

2.4

2.0

1.8

1.5

NA

-

DLLPW

ns

Notes:

1. All specifications correspond to Military Operating Temperatures (-55°C to +125°C).

Period Tolerance: the allowed input clock period change in nanoseconds.

+ T

_

IPTOL

T

CLKIN

Output Jitter: the difference between an ideal

reference clock edge and the actual design.

Phase Offset and Maximum Phase Difference

Ideal Period

Actual Period

+/- Jitter

+ Maximum

Phase Difference

+ Phase Offset

ds022_24_091200

Figure 4: DLL Timing Waveforms

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DLL Clock Tolerance, Jitter, and Phase Information

All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock

mirror configuration and matched drivers.

CLKDLLHF

CLKDLL

Min Max Units

Symbol

T_IPTOL

T_IJITCC

T_LOCK

Description

Input Clock Period Tolerance

F_CLKIN

Min

Max

1.0

-

1.0

± 300

20

ns

ps

µs

ps

Input Clock Jitter Tolerance (Cycle to Cycle)

Time Required for DLL to Acquire Lock

± 150

20

-

> 60 MHz

50 - 60 MHz

40 - 50 MHz

30 - 40 MHz

25 - 30 MHz

-

25

-

50

-

90

-

120

T_OJITCCOutput Jitter (cycle-to-cycle) for any DLL Clock Output⁽¹⁾

± 60

± 100

± 140

± 160

± 200

± 60

± 100

± 140

± 160

± 200

T_PHIO

Phase Offset between CLKIN and CLKO⁽²⁾

T_PHOO

Phase Offset between Clock Outputs on the DLL⁽³⁾

T_PHIOMMaximum Phase Difference between CLKIN and CLKO⁽⁴⁾

T_PHOOMMaximum Phase Difference between Clock Outputs on the DLL⁽⁵⁾

Notes:

1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.

2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,

excluding Output Jitter and input clock jitter.

3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL

outputs, excluding Output Jitter and input clock jitter.

4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,

or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).

5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL

clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).

6. All specifications correspond to Military Operating Temperatures (-55°C to +125°C).

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

05/19/03

07/29/04

Initial Xilinx release.

1.1

•

Table Absolute Maximum Ratings, page 1:

-

Revised V from "–0.5 to 4.0" to "–0.5 to V

Removed Footnote (2) regarding power-up sequencing. Former Footnote (3) is

now Footnote (2).

+ 0.5".

IN

CCO

-

Added new Footnote (3) regarding PCI standard compliance.

•

Table DC Characteristics Over Recommended Operating Conditions, page 2:

Revised I for XQV2000E device from 500 mA to 1100 mA.

CCINTQ

•

Section Power-On Power Supply Requirements, page 2: Added reference to

XAPP158 regarding power supply requirements.

Table IOB Input Switching Characteristics, page 5, and IOB Output Switching

Characteristics, Figure 1, page 7: Added T and T pulse width parameters for

CH

CL

clock CLK.

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High-Reliability FPGAs

0

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

Virtex-E Pin Definitions

Pin Name

Dedicated Pin

Direction

Description

GCK0, GCK1,

GCK2, GCK3

Yes

Input

Clock input pins that connect to Global Clock Buffers.

Mode pins are used to specify the configuration mode.

M0, M1, M2

CCLK

Yes

Input

Input or

Output

The configuration Clock I/O pin: it is an input for SelectMAP and

slave-serial modes, and output in master-serial mode. After

configuration, it is input only, logic level = Don’t Care.

PROGRAM

DONE

Yes

Input

Initiates a configuration sequence when asserted Low.

Bidirectional Indicates that configuration loading is complete, and that the start-up

sequence is in progress. The output can be open drain.

INIT

No

Bidirectional When Low, indicates that the configuration memory is being cleared.

(Open-drain) The pin becomes a user I/O after configuration.

BUSY/DOUT

Output

In SelectMAP mode, BUSY controls the rate at which configuration

data is loaded. The pin becomes a user I/O after configuration unless

the SelectMAP port is retained.

In bit-serial modes, DOUT provides preamble and configuration data

to downstream devices in a daisy-chain. The pin becomes a user I/O

after configuration.

D0/DIN, D1,

D2, D3, D4, D5,

D6, D7

No

Input or

Output

In SelectMAP mode, D0-D7 are configuration data pins. These pins

become user I/Os after configuration unless the SelectMAP port is

retained.

In bit-serial modes, DIN is the single data input. This pin becomes a

user I/O after configuration.

WRITE

CS

No

Input

Mixed

In SelectMAP mode, the active-low Write Enable signal. The pin

becomes a user I/O after configuration unless the SelectMAP port is

retained.

In SelectMAP mode, the active-low Chip Select signal. The pin

becomes a user I/O after configuration unless the SelectMAP port is

retained.

TDI, TDO,

TMS, TCK

Yes

Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.

DXN, DXP

Yes

No

N/A

Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)

Power-supply pins for the internal core logic.

V

Input

CCINT

V

Power-supply pins for the output drivers (subject to banking rules)

CCO

V

Input threshold voltage pins. Become user I/Os when an external

threshold voltage is not needed (subject to banking rules).

REF

GND

Yes

Input

Ground

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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QPro Virtex-E 1.8V QML High-Reliability FPGAs

Low Voltage Differential Signals

The Virtex-E family incorporates low-voltage signalling

(LVDS and LVPECL). Two pins are utilized for these signals

to be connected to a Virtex-E device. These are known as

differential pin pairs. Each differential pin pair has a Positive

(P) and a Negative (N) pin. These pairs are labeled in the

following manner.

an additional table summarizing information specific to dif-

ferential pin pairs for all devices provided in that package.

Table 1: LVDS Pin Pairs

Pin Name

IO_L#[P/N]

Description

Represents a general IO or a

synchronous input/output

differential signal. When used

as a differential signal, N

means Negative I/O and P

means Positive I/O.

IO_L#[P/N]

where

Example: IO_L22N

L = LVDS or LVPECL pin

# = Pin Pair Number

P = Positive

IO_L#[P/N]_Y

Represents a general IO or a

synchronous input/output

differential signal, or a

part-dependent asynchronous

output differential signal.

N = Negative

I/O pins for differential signals can either be synchronous or

asynchronous, input or output. The pin pairs can be used for

synchronous input and output signals as well as asynchro-

nous input signals. However, only some of the low-voltage

pairs can be used for asynchronous output signals.

Example: IO_L22N_Y

IO_L#[P/N]_YY

Represents a general IO or a

synchronous input/output

differential signal, or an

asynchronous output

DIfferential signals require the pins of a pair to switch almost

simultaneously. If the signals driving the pins are from IOB

flip-flops, they are synchronous. If the signals driving the

pins are from internal logic, they are asynchronous. Table 1

defines the names and function of the different types of

low-voltage pin pairs in the Virtex-E family.

Example: O_L22N_YY

differential signal.

IO_LVDS_DLL_L#[P/N] Represents a general IO or a

synchronous input/output

differential signal, a differential

clock input signal, or a DLL

Example:

Virtex-E Package Pinouts

IO_LVDS_DLL_L16N

input. When used as a

differential clock input, this pin

is paired with the adjacent

GCK pin. The GCK pin is

always the positive input in the

differential clock input

The QPro Virtex-E family of FPGAs is available in three

popular packages, including plastic ball grid, fine-pitch plas-

tic ball grid, and hermetic ceramic column grid arrays. Fam-

ily members have footprint compatibility across devices

provided in the same package. The pinout tables in this sec-

tion indicate function, pin, and bank information for each

package/device combination. Following each pinout table is

configuration.

Module 4 of 4

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QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 2: BG432 — XQV600E

BG432 Ball Grid Array Packages

Bank

Pin Description

IO_VREF_L13N_YY

IO_L13P_YY

Pin #

B19

A19

B18

D18

C18

B17

C17

XQV600E devices are available in the BG432 Ball Grid

Array package and supports output banking. See Table 2 for

pinout information. Immediately following Table 2, see

Table 3 for Differential Pair information.

0

IO_L14N_Y

Table 2: BG432 — XQV600E

IO_L14P_Y

Bank

0

Pin Description

GCK3

Pin #

D17

A22

A26

B20

C23

C28

B29

D27

B28

C27

D26

A28

B27

C26

D25

A27

D24

C25

B25

D23

C24

B24

D22

A24

C22

B22

C21

D20

B21

C20

A20

D19

IO_VREF_L15N_Y

IO_L15P_Y

0

IO

IO_LVDS_DLL_L16N

0

IO

0

IO

1

GCK2

IO

A16

A12

B9

0

IO

0

IO

0

IO_L0N_Y

IO_L0P_Y

IO_L1N_YY

IO_L1P_YY

IO_VREF_L2N_YY

IO_L2P_YY

IO_L3N_Y

IO_L3P_Y

IO_L4N_YY

IO_L4P_YY

IO_VREF_L5N_YY

IO_L5P_YY

IO_L6N_Y

IO_L6P_Y

IO_VREF_L7N_Y

IO_L7P_Y

IO_VREF_L8N_YY

IO_L8P_YY

IO_L9N_YY

IO_L9P_YY

IO_L10N_YY

IO_L10P_YY

IO_L11N_YY

IO_L11P_YY

IO_L12N_YY

IO_L12P_YY

IO

B11

C16

D9

0

IO

0

IO

0

IO_LVDS_DLL_L16P

IO_L17N_Y

IO_VREF_L17P_Y

IO_L18N_Y

IO_L18P_Y

IO_L19N_YY

IO_VREF_L19P_YY

IO_L20N_YY

IO_L20P_YY

IO_L21N_YY

IO_L21P_YY

IO_L22N_YY

IO_L22P_YY

IO_L23N_YY

IO_L23P_YY

IO_L24N_YY

IO_VREF_L24P_YY

IO_L25N_Y

IO_VREF_L25P_Y

IO_L26N_Y

IO_L26P_Y

IO_L27N_YY

B16

A15

B15

C15

D15

B14

A13

B13

D14

C13

B12

D13

C12

D12

C11

B10

C10

C9

0

D10

A8

0

B8

0

C8

0

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Table 2: BG432 — XQV600E

Bank

Pin Description

IO_VREF_L27P_YY

IO_L28N_YY

Pin #

B7

D8

A6

B6

D7

A5

C6

B5

D6

A4

C5

B4

D5

Bank

2

Pin Description

Pin #

J4

1

IO_L42N_Y

IO_VREF_L43P_YY

IO_D1_L43N_YY

IO_D2_L44P_YY

IO_L44N_YY

IO_L45P_Y

2

J2

IO_L28P_YY

2

K4

K2

K1

L2

IO_L29N_Y

2

IO_L29P_Y

2

IO_L30N_YY

2

IO_VREF_L30P_YY

IO_L31N_YY

2

IO_L45N_Y

M4

M3

M2

N4

N3

N1

P4

P3

P2

R3

R4

R1

T3

2

IO_L46P_Y

IO_L31P_YY

2

IO_L46N_Y

IO_L32N_Y

2

IO_L47P_Y

IO_L32P_Y

2

IO_L47N_Y

IO_WRITE_L33N_YY

IO_CS_L33P_YY

2

IO_VREF_L48P_YY

IO_D3_L48N_YY

IO_L49P_Y

2

IO

H4

J3

2

IO_L49N_Y

2

IO_VREF_L50P_Y

IO_L50N_Y

IO

L3

2

IO

M1

R2

D3

C2

D2

E4

D1

E3

E2

F4

E1

F3

F2

G4

G3

G2

H3

H2

H1

2

IO_L51P_YY

IO_L51N_YY

IO

2

IO_DOUT_BUSY_L34P_YY

IO_DIN_D0_L34N_YY

IO_L35P

3

IO

AA2

AC2

AE2

U3

IO_L35N

IO

IO_L36P_Y

IO_L36N_Y

IO_VREF_L37P_Y

IO_L37N_Y

IO_L38P

IO

W1

U4

IO_L52P_Y

IO_VREF_L52N_Y

IO_L53P_Y

IO_L53N_Y

IO_D4_L54P_YY

IO_VREF_L54N_YY

IO_L55P_Y

IO_L55N_Y

IO_L56P_Y

IO_L56N_Y

IO_L57P_Y

2

U2

U1

V3

V4

V2

W3

W4

Y1

Y3

Y4

IO_L38N

IO_L39P_Y

IO_L39N_Y

IO_VREF_L40P_YY

IO_L40N_YY

IO_L41P_Y

IO_L41N_Y

IO_VREF_L42P_Y

Module 4 of 4

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QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 2: BG432 — XQV600E

Bank

3

Pin Description

Pin #

Y2

Bank

4

Pin Description

IO_L71N_YY

IO_VREF_L72P_YY

IO_L72N_YY

IO_L73P_Y

Pin #

AH6

AL4

AK5

AJ6

AH7

AL5

AK6

AJ7

AL6

AH9

AJ8

IO_L57N_Y

IO_L58P_YY

IO_D5_L58N_YY

IO_D6_L59P_YY

IO_VREF_L59N_YY

IO_L60P_Y

3

AA3

AB1

AB3

AB4

AD1

AC3

AC4

AD2

AD3

AD4

AF2

AE3

AE4

AG1

AG2

AF3

AF4

AH1

AH2

AG3

AG4

AJ2

T2

4

3

4

3

4

3

4

IO_L73N_Y

3

4

IO_L74P_YY

3

IO_VREF_L60N_Y

IO_L61P_Y

4

IO_L74N_YY

IO_VREF_L75P_YY

IO_L75N_YY

IO_L76P_Y

3

4

3

IO_L61N_Y

4

3

IO_L62P_YY

IO_VREF_L62N_YY

IO_L63P_Y

4

3

4

IO_L76N_Y

1

3

4

IO_VREF_L77P_Y

IO_L77N_Y

AK8

3

IO_L63N_Y

4

AJ9

AL8

3

IO_L64P

4

IO_VREF_L78P_YY

IO_L78N_YY

IO_L79P_YY

3

IO_L64N

4

AK9

3

IO_L65P_Y

4

AK10

AL10

AH12

AK11

AJ12

AK12

AH13

AJ13

AL13

AK14

AH14

AJ14

3

IO_VREF_L65N_Y

IO_L66P_Y

4

IO_L79N_YY

IO_L80P_YY

3

4

3

IO_L66N_Y

4

IO_L80N_YY

IO_L81P_YY

3

IO_L67P

4

3

IO_L67N

4

IO_L81N_YY

IO_L82P_YY

3

IO_D7_L68P_YY

IO_INIT_L68N_YY

IO

4

3

4

IO_L82N_YY

IO_VREF_L83P_YY

IO_L83N_YY

IO_L84P_Y

3

4

GCK0

IO

AL16

AH10

AJ11

AK7

4

IO_L84N_Y

2

IO

4

IO_VREF_L85P_Y

IO_L85N_Y

AK15

AJ15

AH15

IO

4

IO

AL12

AL15

AJ4

4

IO_LVDS_DLL_L86P

IO

IO_L69P_YY

IO_L69N_YY

IO_L70P_Y

IO_L70N_Y

IO_L71P_YY

5

GCK1

IO

AK16

AH20

AJ19

AJ23

AJ24

AK3

AH5

AK4

IO

AJ5

IO

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QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 2: BG432 — XQV600E

Pin Description

Bank

5

Pin Description

IO_LVDS_DLL_L86N

IO_L87P_Y

Pin #

AL17

AK17

Bank

6

Pin #

AD29

U31

IO

5

IO

2

5

IO_VREF_L87N_Y

IO_L88P_Y

AJ17

AH17

AK18

AL19

AJ18

AH18

AL20

AK20

AH19

AJ20

AK21

AJ21

AL22

AJ22

AK23

AH22

IO

W28

5

IO_L103N_YY

IO_L103P_YY

IO_L104N

AJ30

AH30

AG28

AH31

AG29

AG30

AF28

AG31

AF29

AF30

AE28

AF31

AE30

AD28

AD30

AD31

5

IO_L88N_Y

5

IO_L89P_YY

5

IO_VREF_L89N_YY

IO_L90P_YY

IO_L104P

5

IO_L105N_Y

IO_L105P_Y

IO_VREF_L106N_Y

IO_L106P_Y

IO_L107N

5

IO_L90N_YY

IO_L91P_YY

5

IO_L91N_YY

5

IO_L92P_YY

5

IO_L92N_YY

IO_L93P_YY

IO_L107P

5

IO_L108N_Y

IO_L108P_Y

IO_VREF_L109N_YY

IO_L109P_YY

IO_L110N_Y

IO_L110P_Y

IO_VREF_L111N_Y

IO_L111P_Y

IO_VREF_L112N_YY

IO_L112P_YY

IO_L113N_YY

IO_L113P_YY

IO_L114N_Y

IO_L114P_Y

IO_L115N_Y

IO_L115P_Y

IO_L116N_Y

IO_L116P_Y

IO_VREF_L117N_YY

IO_L117P_YY

IO_L118N_Y

IO_L118P_Y

IO_VREF_L119N_Y

5

IO_L93N_YY

IO_L94P_YY

5

IO_VREF_L94N_YY

IO_L95P_Y

5

1

5

IO_VREF_L95N_Y

IO_L96P_Y

AL24

AK24

AH23

AK25

AJ25

AL26

AK26

AH25

AL27

AJ26

AK27

AH26

AL28

AJ27

AK28

1

5

AC28

AC29

AB28

AB29

AB31

AA29

Y28

5

IO_L96N_Y

5

IO_L97P_YY

5

IO_VREF_L97N_YY

IO_L98P_YY

5

IO_L98N_YY

IO_L99P_Y

5

IO_L99N_Y

Y29

5

IO_L100P_YY

IO_VREF_L100N_YY

IO_L101P_YY

IO_L101N_YY

IO_L102P_Y

Y30

5

Y31

5

W29

W30

V28

5

IO_L102N_Y

V29

V30

6

IO

AA30

AC30

U29

U28

Module 4 of 4

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QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 2: BG432 — XQV600E

Bank

Pin Description

Pin #

U30

T30

Bank

Pin Description

IO_L133P

Pin #

E30

F29

F28

D31

D30

E29

E28

6

IO_L119P_Y

IO

7

IO_L134N_Y

IO_VREF_L134P_Y

IO_L135N_Y

IO_L135P_Y

IO_L136N

7

IO

C30

H29

H31

L29

M31

R28

T31

R29

R30

R31

P29

P28

P30

N30

N28

N31

M29

M28

M30

L30

K31

K30

K28

J30

IO

IO_L136P

IO

2

CCLK

DONE

DXN

D4

AH4

AH27

AK29

AH28

AH29

AJ28

AH3

D28

B3

IO_L120N_YY

IO_L120P_YY

IO_L121N_Y

IO_VREF_L121P_Y

IO_L122N_Y

IO_L122P_Y

IO_L123N_YY

IO_VREF_L123P_YY

IO_L124N_Y

IO_L124P_Y

IO_L125N_Y

IO_L125P_Y

IO_L126N_Y

IO_L126P_Y

IO_L127N_YY

IO_L127P_YY

IO_L128N_YY

IO_VREF_L128P_YY

IO_L129N_Y

IO_VREF_L129P_Y

IO_L130N_Y

IO_L130P_Y

IO_L131N_YY

IO_VREF_L131P_YY

IO_L132N_Y

IO_L132P_Y

IO_L133N

3

NA

2

DXP

M0

M1

M2

PROGRAM

TCK

TDI

TDO

C4

NA

TMS

D29

NA

VCCINT

A10

A17

B23

B26

C7

C14

C19

F1

J29

1

J28

H30

G30

H28

F31

G29

G28

E31

F30

K3

K29

N2

N29

T1

T29

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Table 2: BG432 — XQV600E

Bank

NA

Pin Description

VCCINT

Pin #

W2

Bank

Pin Description

Pin #

L28

7

VCCO

W31

AB2

L31

AB30

AE29

AF1

NA

GND

A2

A3

A7

AH8

A9

AH24

AJ10

AJ16

AK22

AK13

AK19

A14

A18

A23

A25

A29

A30

B1

0

1

2

3

4

5

6

7

VCCO

A21

C29

D21

A1

B2

B30

B31

C1

A11

D11

C3

C31

D16

G1

L4

G31

J1

L1

AA1

AA4

AJ3

J31

P1

P31

T4

AH11

AL1

AL11

AH21

AL21

AJ29

AA28

AA31

AL31

A31

T28

V1

V31

AC1

AC31

AE1

AE31

AH16

AJ1

Module 4 of 4

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QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 2: BG432 — XQV600E

Table 3: BG432 Differential Pin Pair Summary

XQV600E

Bank

NA

Pin Description

Pin #

AJ31

AK1

Pair Bank

P

N

AO

Other

GND

Functions

3

0

1

2

C26

A27

C25

D23

B24

A24

B22

D20

C20

D19

A19

D18

B17

B16

B15

D15

A13

D14

B12

C12

C11

C10

D10

B8

B27

D25

D24

B25

C24

D22

C22

C21

B21

A20

B19

B18

C18

C17

A15

C15

B14

B13

C13

D13

D12

B10

C9

NA

√

-

AK2

4

-

AK30

AK31

AL2

5

√

VREF

6

√

-

7

√

VREF

AL3

8

√

VREF

AL7

9

√

-

AL9

AL14

AL18

AL23

AL25

AL29

AL30

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

√

-

√

-

√

-

√

VREF

√

-

√

VREF

NA

√

IO_LVDS_DLL

BG432 Differential Pin Pairs

VREF

Virtex-E devices have differential pin pairs that can also Vir-

tex-E devices have differential pin pairs that can also pro-

vide other functions when not used as a differential pair. A √

in the AO column indicates that the pin pair can be used as

an asynchronous output. The Other Functions column indi-

cates alternative function(s) not available when the pair is

used as a differential pair or differential clock.

√

-

√

VREF

√

-

√

-

√

-

Table 3: BG432 Differential Pin Pair Summary

XQV600E

√

-

Pair Bank

P

N

AO

Other

√

VREF

Functions

√

VREF

Global Differential Clock

A8

√

-

0

1

2

3

4

5

1

0

AL16

AK16

A16

AH15

AL17

B16

NA

IO_DLL_L86P

IO_DLL_L86N

IO_DLL_L16P

IO_DLL_L16N

B7

C8

√

VREF

A6

D8

√

-

D7

B6

NA

√

-

D17

C17

C6

A5

VREF

IO LVDS

D6

B5

√

-

Total Outputs: 137, Asynchronous Output Pairs: 63

C5

A4

√

-

0

1

2

0

D27

C27

A28

B29

B28

D26

√

-

D5

B4

√

CS, WRITE

DIN, D0, BUSY

D3

C2

√

VREF

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

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1-800-255-7778

Module 4 of 4

9

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 3: BG432 Differential Pin Pair Summary

XQV600E

Pair Bank

P

N

AO

Other

Pair Bank

P

N

AO

Other

Functions

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

2

3

D2

D1

E4

E3

√

NA

√

-

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

3

4

5

AH2

AG4

AG3

AJ2

√

-

INIT

E2

F4

VREF

AJ4

AK3

√

-

E1

F3

√

-

AH5

AK4

√

-

F2

G4

G2

H2

√

-

AJ5

AH6

√

-

G3

H3

√

VREF

AL4

AK5

√

VREF

NA

√

-

AJ6

AH7

NA

√

-

H1

J4

VREF

AL5

AK6

-

J2

K4

√

D1

AJ7

AL6

√

VREF

K2

K1

√

D2

AH9

AJ8

√

-

L2

M4

M2

N3

4

-

AK8

AJ9

√

VREF

M3

N4

√

-

AL8

AK9

√

VREF

√

-

AK10

AH12

AJ12

AH13

AL13

AH14

AK15

AH15

AK17

AH17

AL19

AH18

AK20

AJ20

AJ21

AJ22

AH22

AK24

AK25

AL26

AL10

AK11

AK12

AJ13

AK14

AJ14

AJ15

AL17

AJ17

AK18

AJ18

AL20

AH19

AK21

AL22

AK23

AL24

AH23

AJ25

AK26

√

-

N1

P4

√

D3

√

-

P3

P2

NA

√

-

√

-

R3

R4

VREF

√

-

R1

T3

√

-

√

VREF

U4

U2

√

VREF

√

-

U1

V3

NA

√

-

√

VREF

V4

V2

VREF

NA

√

IO_LVDS_DLL

W3

Y1

W4

Y3

√

-

VREF

√

-

√

-

Y4

Y2

NA

√

-

√

VREF

AA3

AB3

AD1

AC4

AD3

AF2

AE4

AG2

AF4

AB1

AB4

AC3

AD2

AD4

AE3

AG1

AF3

AH1

D5

√

-

√

VREF

√

-

√

VREF

√

-

NA

√

-

√

-

VREF

√

VREF

-

√

-

√

-

VREF

-

√

VREF

-

NA

√

Module 4 of 4

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DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 3: BG432 Differential Pin Pair Summary

XQV600E

Pair Bank

P

N

AO

Other

Pair Bank

P

N

AO

Other

Functions

99

5

6

7

AH25

AJ26

AH26

AJ27

AH30

AH31

AG30

AG31

AF30

AF31

AD28

AD31

AC29

AB29

AA29

Y29

AL27

AK27

AL28

AK28

AJ30

AG28

AG29

AF28

AF29

AE28

AE30

AD30

AC28

AB28

AB31

Y28

NA

√

-

131

132

133

134

135

136

7

F31

G28

E30

F28

D30

E28

H28

G29

E31

F29

D31

E29

√

VREF

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

VREF

-

√

-

√

-

√

-

√

VREF

√

-

NA

√

-

√

-

NA

√

-

VREF

√

-

√

-

√

VREF

NA

√

-

VREF

√

VREF

√

-

NA

√

-

Y31

Y30

-

W30

V29

W29

V28

√

-

√

VREF

U29

V30

NA

√

-

U30

U28

VREF

R29

T31

√

-

R31

R30

√

VREF

P28

P29

NA

√

-

N30

P30

VREF

N31

N28

√

-

M28

L30

M29

M30

K31

√

-

NA

√

-

K30

-

J30

K28

√

VREF

-

J28

J29

√

G30

H30

NA

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

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1-800-255-7778

Module 4 of 4

11

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

BG560 Plastic Ball Grid and CG560 Ceramic

Column Grid Array Packages

Bank

0

Pin Description

IO_L10P_YY

IO_L11N_YY

IO_L11P_YY

IO_L12N_Y

Pin#

A25

D23

B24

E22

C23

A23

D22

E21

B22

D21

C21

B21

E20

D20

C20

B20

E19

D19

C19

A19

D18

C18

E18

See Note

XQV1000E is the only Virtex-E device available in the

CG560 Hermetic Ceramic Column Grid Array package.

XQV1000E and XQV2000E devices are both available in

BG560 Ball Grid Array packages and have footprint compat-

ibility. Pins labeled I0_VREF can be used as either in all

parts unless device-dependent as indicated in the foot-

0

notes. If the pin is not used as V , it can be used as gen-

REF

0

IO_L12P_Y

eral I/O. Immediately following Table 4, see Table 5 for

Differential Pair information.

0

IO_L13N_YY

IO_L13P_YY

IO_VREF_L14N_YY

IO_L14P_YY

IO_L15N_Y

0

Table 4: BG560/CG560 — XQV1000E, XQV2000E

0

Bank

0

Pin Description

GCK3

Pin#

A17

A27

B25

C28

C30

D30

E28

D29

D28

A31

E27

C29

B30

D27

E26

B29

D26

C27

E25

A28

D25

C26

E24

B26

C25

D24

E23

See Note

0

IO

0

IO_L15P_Y

0

IO

0

IO_L16N_YY

IO_L16P_YY

IO_VREF_L17N_YY

IO_L17P_YY

IO_L18N_Y

0

IO

0

IO

0

IO

0

IO_L0N

0

IO_VREF_L0P

IO_L1N_YY

IO_L1P_YY

IO_VREF_L2N_YY

IO_L2P_YY

IO_L3N_Y

IO_L3P_Y

IO_L4N_YY

IO_L4P_YY

IO_VREF_L5N_YY

IO_L5P_YY

IO_L6N_Y

IO_VREF_L6P_Y

IO_L7N_Y

IO_L7P_Y

IO_VREF_L8N_Y

IO_L8P_Y

IO_L9N_Y

IO_L9P_Y

IO_VREF_L10N_YY

0

IO_L18P_Y

0

IO_L19N_Y

0

IO_L19P_Y

0

IO_VREF_L20N_Y

IO_L20P_Y

0

IO_LVDS_DLL_L21N

IO_VREF

0

1

0

1

GCK2

IO

D17

A3

0

IO

D9

0

IO

E8

0

1

IO

E11

E17

C17

B17

B16

D16

E16

C16

0

IO_LVDS_DLL_L21P

IO_VREF_L22N_Y

IO_L22P_Y

IO_L23N_Y

IO_VREF_L23P_Y

IO_L24N_Y

IO_L24P_Y

0

1

0

Module 4 of 4

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

Bank

1

Pin Description

IO_L25N_Y

Pin#

A15

C15

D15

E15

C14

D14

A13

E14

C13

D13

C12

E13

A11

D12

B11

C11

B10

D11

C10

A9

See Note

Bank

Pin Description

IO_L43N_Y

Pin#

C5

E7

See Note

1

IO_L25P_Y

IO_VREF_L43P_Y

IO_WRITE_L44N_YY

IO_CS_L44P_YY

IO_L26N_YY

IO_VREF_L26P_YY

IO_L27N_YY

IO_L27P_YY

IO_L28N_Y

D6

A2

2

IO

D3

F3

G1

J2

IO_L28P_Y

IO

IO_L29N_YY

IO_VREF_L29P_YY

IO_L30N_YY

IO_L30P_YY

IO_L31N_Y

IO

IO_DOUT_BUSY_L45P_YY

IO_DIN_D0_L45N_YY

IO_L46P_Y

D4

E4

F5

B3

F4

C1

G5

E3

D2

G4

H5

E2

H4

G3

J5

IO_VREF_L46N_Y

IO_L47P_Y

IO_L31P_Y

IO_L32N_YY

IO_L32P_YY

IO_L33N_YY

IO_VREF_L33P_YY

IO_L34N_Y

IO_L47N_Y

IO_VREF_L48P_Y

IO_L48N_Y

IO_L49P_Y

IO_L49N_Y

IO_L34P_Y

IO_L50P_Y

IO_L35N_Y

C9

IO_L50N_Y

IO_VREF_L35P_Y

IO_L36N_Y

D10

A8

IO_VREF_L51P_YY

IO_L51N_YY

IO_L52P_Y

IO_L36P_Y

B8

IO_L37N_Y

E10

C8

IO_VREF_L52N_Y

IO_L53P_Y

F1

J4

1

IO_VREF_L37P_Y

IO_L38N_YY

IO_VREF_L38P_YY

IO_L39N_YY

IO_L39P_YY

IO_L40N_Y

1

B7

IO_L53N_Y

H3

K5

H2

J3

A6

IO_VREF_L54P_Y

IO_L54N_Y

C7

D8

IO_L55P_Y

A5

IO_L55N_Y

K4

L5

IO_L40P_Y

B5

IO_VREF_L56P_YY

IO_D1_L56N_YY

IO_D2_L57P_YY

IO_L57N_YY

IO_L58P_Y

IO_L41N_YY

IO_VREF_L41P_YY

IO_L42N_YY

IO_L42P_YY

C6

K3

L4

D7

A4

K2

M5

B4

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

13

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

Bank

2

Pin Description

IO_L58N_Y

Pin#

L3

See Note

Bank

3

Pin Description

IO_L74P_Y

Pin#

Y3

See Note

2

IO_L59P_Y

L1

IO_L74N_Y

Y4

2

IO_L59N_Y

M4

N5

M2

N4

N3

N2

P5

P4

P3

P2

R5

R4

R3

R1

T4

T5

T3

T2

U3

IO_L75P_Y

AA1

Y5

2

IO_VREF_L60P_Y

IO_L60N_Y

IO_L75N_Y

2

IO_L76P_Y

AA3

AA4

AB3

AA5

AC1

AB4

AC3

AB5

AC4

AD3

AE1

AC5

AD4

AF1

AF2

AD5

AG2

AE4

AH1

AE5

AF4

AJ1

AJ2

AF5

AG4

AK2

AJ3

AG5

AL1

AH4

AJ4

AH5

2

IO_L61P_Y

IO_VREF_L76N_Y

IO_L77P_Y

2

IO_L61N_Y

2

IO_L62P_Y

IO_L77N_Y

2

IO_L62N_Y

IO_L78P_Y

2

IO_VREF_L63P_YY

IO_D3_L63N_YY

IO_L64P_Y

IO_L78N_Y

2

IO_L79P_YY

IO_D5_L79N_YY

IO_D6_L80P_YY

IO_VREF_L80N_YY

IO_L81P_Y

2

IO_L64N_Y

2

IO_L65P_Y

2

IO_L65N_Y

2

IO_VREF_L66P_Y

IO_L66N_Y

IO_L81N_Y

2

IO_L82P_Y

2

IO_L67P_Y

IO_VREF_L82N_Y

IO_L83P_Y

2

IO_VREF_L67N_Y

IO_L68P_YY

IO_L68N_YY

1

2

IO_L83N_Y

2

IO_L84P_Y

IO_VREF_L84N_Y

IO_L85P_YY

IO_VREF_L85N_YY

IO_L86P_Y

1

3

IO

AE3

AF3

AH3

AK3

U1

IO

IO_L86N_Y

IO_VREF_L69P_Y

IO_L69N_Y

IO_L70P_Y

IO_VREF_L70N_Y

IO_L71P_Y

IO_L71N_Y

IO_L72P_Y

IO_L72N_Y

IO_D4_L73P_YY

IO_VREF_L73N_YY

1

IO_L87P_Y

U2

IO_L87N_Y

V2

IO_L88P_Y

V4

IO_VREF_L88N_Y

IO_L89P_Y

V5

V3

IO_L89N_Y

W1

W3

W4

W5

IO_L90P_Y

IO_VREF_L90N_Y

IO_D7_L91P_YY

IO_INIT_L91N_YY

Module 4 of 4

14

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DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

Bank

Pin Description

Pin#

See Note

Bank

4

Pin Description

IO_L106N_YY

IO_VREF_L107P_YY

IO_L107N_YY

IO_L108P_Y

Pin#

AM12

AK13

AL13

AM13

AN13

AJ14

AK14

AM14

AN15

AJ15

AK15

AL15

AM16

AL16

AJ16

AK16

AN17

AM17

See Note

3

IO

U4

4

GCK0

IO

AL17

AJ8

4

IO

AJ11

AK6

AK9

AL4

4

IO_L108N_Y

IO

4

IO_L109P_YY

IO

4

IO_L109N_YY

IO_VREF_L110P_YY

IO_L110N_YY

IO_L111P_Y

IO_L92P_YY

IO_L92N_YY

IO_L93P_Y

4

AJ6

4

AK5

AN3

AL5

4

IO_VREF_L93N_Y

IO_L94P_YY

IO_L94N_YY

IO_VREF_L95P_YY

IO_L95N_YY

IO_L96P_Y

4

IO_L111N_Y

4

IO_L112P_Y

AJ7

4

IO_L112N_Y

AM4

AM5

AK7

AL6

4

IO_VREF_L113P_Y

IO_L113N_Y

4

IO_L114P_Y

IO_L96N_Y

4

IO_VREF_L114N_Y

IO_LVDS_DLL_L115P

1

IO_L97P_YY

IO_L97N_YY

IO_VREF_L98P_YY

IO_L98N_YY

IO_L99P_Y

AM6

AN6

AL7

4

5

GCK1

IO

AJ17

AL25

AL28

AL30

AN28

AM18

AL18

AK18

AJ18

AN19

AL19

AK19

AM20

AJ19

AL20

AN21

AL21

AJ9

AN7

AL8

IO

IO_VREF_L99N_Y

IO_L100P_Y

IO_L100N_Y

IO_VREF_L101P_Y

IO_L101N_Y

IO_L102P_Y

IO_L102N_Y

IO_VREF_L103P_YY

IO_L103N_YY

IO_L104P_YY

IO_L104N_YY

IO_L105P_Y

IO_L105N_Y

IO_L106P_YY

1

IO

AM8

AJ10

AL9

IO

IO_LVDS_DLL_L115N

IO_VREF

1

AM9

AK10

AN9

AL10

AM10

AL11

AJ12

AN11

AK12

AL12

IO_L116P_Y

IO_VREF_L116N_Y

IO_L117P_Y

IO_L117N_Y

IO_L118P_Y

IO_L118N_Y

IO_L119P_YY

IO_VREF_L119N_YY

IO_L120P_YY

IO_L120N_YY

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

15

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

Bank

5

Pin Description

IO_L121P_Y

Pin#

AJ20

AM22

AK21

AN23

AJ21

AM23

AK22

AM24

AL23

AJ22

AK23

AL24

AN26

AJ23

AK24

AM26

AM27

AJ24

AL26

AK25

AN29

AJ25

AK26

AM29

AM30

AJ26

AK27

AL29

AN31

AJ27

AM31

AK28

See Note

Bank

6

Pin Description

IO

Pin#

See Note

AL33

AH29

AJ30

AK31

AH30

AG29

AJ31

AK32

AG30

AH31

AF29

AH32

AF30

AE29

AH33

AG33

AE30

AD29

AF32

AE31

AD30

AE32

AC29

AD31

AC30

AB29

AC31

AC33

AB30

AB31

AA29

AA30

AA31

AA32

Y29

IO_L121N_Y

IO_L137N_YY

IO_L137P_YY

IO_L138N_Y

IO_L122P_YY

IO_VREF_L122N_YY

IO_L123P_YY

IO_L123N_YY

IO_L124P_Y

IO_VREF_L138P_Y

IO_L139N_Y

IO_L139P_Y

IO_L124N_Y

IO_VREF_L140N_Y

IO_L140P_Y

IO_L125P_YY

IO_L125N_YY

IO_L126P_YY

IO_VREF_L126N_YY

IO_L127P_Y

IO_L141N_Y

IO_L141P_Y

IO_L142N_Y

IO_L142P_Y

IO_L127N_Y

IO_VREF_L143N_YY

IO_L143P_YY

IO_L144N_Y

IO_L128P_Y

IO_VREF_L128N_Y

IO_L129P_Y

IO_VREF_L144P_Y

IO_L145N_Y

1

IO_L129N_Y

IO_L130P_Y

IO_L145P_Y

IO_VREF_L130N_Y

IO_L131P_YY

IO_VREF_L131N_YY

IO_L132P_YY

IO_L132N_YY

IO_L133P_Y

1

IO_VREF_L146N_Y

IO_L146P_Y

IO_L147N_Y

IO_L147P_Y

IO_VREF_L148N_YY

IO_L148P_YY

IO_L149N_YY

IO_L149P_YY

IO_L150N_Y

IO_L133N_Y

IO_L134P_YY

IO_VREF_L134N_YY

IO_L135P_YY

IO_L135N_YY

IO_L136P_Y

IO_L150P_Y

IO_L151N_Y

IO_L151P_Y

IO_VREF_L136N_Y

IO_VREF_L152N_Y

IO_L152P_Y

6

IO

AE33

AF31

AJ32

IO_L153N_Y

IO_L153P_Y

IO_L154N_Y

AA33

Module 4 of 4

16

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DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

Bank

6

Pin Description

IO_L154P_Y

Pin#

Y30

Y32

W29

W30

W31

W33

V30

V29

V31

V32

U33

U29

See Note

Bank

7

Pin Description

IO_L169N_Y

Pin#

M31

L32

M30

L31

M29

J33

See Note

6

IO_VREF_L155N_YY

IO_L155P_YY

IO_L156N_Y

7

IO_L169P_Y

6

7

IO_L170N_Y

6

7

IO_L170P_Y

6

IO_L156P_Y

7

IO_L171N_YY

IO_L171P_YY

IO_L172N_YY

IO_VREF_L172P_YY

IO_L173N_Y

6

IO_L157N_Y

7

6

IO_L157P_Y

7

L30

K31

L29

H33

J31

6

IO_VREF_L158N_Y

IO_L158P_Y

7

6

7

6

IO_L159N_Y

7

IO_L173P_Y

6

IO_VREF_L159P_Y

IO

1

7

IO_L174N_Y

6

7

IO_VREF_L174P_Y

IO_L175N_Y

H32

K29

H31

J30

7

IO

E30

F29

F33

G30

K30

U31

U32

T32

T30

T29

T31

R33

R31

R30

R29

P32

P31

P30

P29

M32

N31

N30

L33

7

IO_L175P_Y

7

IO_L176N_Y

IO

7

IO_VREF_L176P_Y

IO_L177N_YY

IO_VREF_L177P_YY

IO_L178N_Y

G32

J29

1

IO

7

IO

7

G31

E33

E32

H29

F31

D32

E31

G29

C33

F30

D31

IO_L160N_YY

IO_L160P_YY

IO_VREF_L161N_Y

IO_L161P_Y

IO_L162N_Y

IO_VREF_L162P_Y

IO_L163N_Y

IO_L163P_Y

IO_L164N_Y

IO_L164P_Y

IO_L165N_YY

IO_VREF_L165P_YY

IO_L166N_Y

IO_L166P_Y

IO_L167N_Y

IO_L167P_Y

IO_L168N_Y

IO_VREF_L168P_Y

7

IO_L178P_Y

1

7

IO_L179N_Y

7

IO_L179P_Y

7

IO_L180N_Y

7

IO_VREF_L180P_Y

IO_L181N_Y

7

IO_L181P_Y

7

IO_L182N_Y

7

IO_VREF_L182P_Y

2

CCLK

DONE

DXN

DXP

M0

C4

3

AJ5

NA

AK29

AJ28

AJ29

AK30

AN32

M1

M2

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

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Module 4 of 4

17

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

Bank

NA

2

Pin Description

PROGRAM

TCK

Pin#

AM1

E29

D5

See Note

Bank

NA

Pin Description

VCCINT

Pin#

AG3

See Note

AG31

AJ13

AK8

TDI

TDO

E6

NA

TMS

B33

AK11

AK17

AK20

AL14

AL22

AL27

AN25

NA

NC

C31

AC2

AK4

AL3

NA

VCCINT

A21

B12

B14

B18

B28

C22

C24

E9

0

1

2

3

4

VCCO

A22

A26

A30

B19

B32

A10

A16

B13

C3

E12

F2

H30

J1

E5

B2

K32

M3

D1

H1

N1

M1

N29

N33

U5

R2

V1

AA2

AD1

AK1

AL2

AN4

AN8

AN12

AM2

U30

Y2

Y31

AB2

AB32

AD2

AD32

Module 4 of 4

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DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

Bank

4

Pin Description

VCCO

Pin#

AM15

AL31

AM21

AN18

AN24

AN30

W32

AB33

AF33

AK33

AM32

C32

See Note

Bank

NA

Pin Description

GND

Pin#

F32

See Note

5

G2

5

G33

J32

5

K1

5

L2

6

M33

P1

6

P33

6

R32

T1

6

7

V33

7

D33

W2

7

K33

Y1

7

N32

Y33

7

T33

AB1

AC32

AD33

AE2

AG1

AG32

AH2

AJ33

AL32

AM3

AM7

AM11

AM19

AM25

AM28

AM33

AN1

AN2

AN5

AN10

AN14

NA

GND

A1

A7

A12

A14

A18

A20

A24

A29

A32

A33

B1

B6

B9

B15

B23

B27

B31

C2

E1

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

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1-800-255-7778

Module 4 of 4

19

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 4: BG560/CG560 — XQV1000E, XQV2000E

Table 5: BG560/CG560 Differential Pin Pair Summary

XQV1000E, XQV2000E

Bank

NA

Pin Description

GND

Pin#

See Note

P

N

Other

AN16

AN20

AN22

AN27

AN33

Pair Bank

AO

√

Functions

NA

GND

7

0

1

C26

B26

D24

A25

B24

C23

D22

B22

C21

E20

C20

E19

C19

D18

E17

B17

D16

C16

C15

E15

D14

E14

D13

E13

D12

C11

D11

A9

D25

E24

C25

E23

D23

E22

A23

E21

D21

B21

D20

B20

D19

A19

C18

C17

B16

E16

A15

D15

C14

A13

C13

C12

A11

B11

B10

C10

C9

-

NA

GND

8

√

VREF

NA

GND

9

2

-

NA

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

√

VREF

Notes:

1. V_REFor I/O option only in the XQV2000E; otherwise, I/O

√

-

option only.

NA

√

-

BG560 and CG560 Differential Pin Pairs

-

Virtex-E devices have differential pin pairs that can also pro-

vide other functions when not used as a differential pair. A √

in the AO column indicates that the pin pair can be used as

an asynchronous output for all devices provided in this

package. Pairs with a note number in the AO column are

device dependent. They can have asynchronous outputs if

the pin pair are in the same CLB row and column in the

device. Numbers in this column refer to footnotes that indi-

cate which devices have pin pairs than can be asynchro-

nous outputs. The Other Functions column indicates

alternative function(s) not available when the pair is used as

a differential pair or differential clock.

√

VREF

2

-

√

-

√

VREF

NA

√

-

√

VREF

NA IO_LVDS_DLL

Table 5: BG560/CG560 Differential Pin Pair Summary

XQV1000E, XQV2000E

2

√

VREF

P

N

Other

VREF

Pair Bank

AO

Functions

√

-

Global Differential Clock

NA

√

-

0

1

2

3

4

5

1

0

AL17

AJ17

D17

AM17

AM18

E17

NA

IO_DLL_L15P

IO_DLL_L15N

IO_DLL_L21P

IO_DLL_L21N

VREF

√

-

2

-

A17

C18

√

VREF

IO LVDS

√

-

Total Outputs: 183, Asynchronous Outputs: 87

NA

√

-

0

1

2

3

4

5

6

0

D29

A31

C29

D27

B29

C27

A28

E28

D28

E27

B30

E26

D26

E25

NA

√

VREF

-

√

VREF

-

√

VREF

-

√

2

D10

B8

√

VREF

-

√

-

A8

√

VREF

C8

E10

√

VREF

NA

Module 4 of 4

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 5: BG560/CG560 Differential Pin Pair Summary

XQV1000E, XQV2000E

P

N

Other

P

N

Other

Pair Bank

AO

√

1

√

2

1

√

2

√

2

1

√

2

√

2

1

√

2

√

2

1

√

2

√

Functions

Pair Bank

AO

2

Functions

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

1

2

A6

D8

B5

D7

B4

E7

A2

D4

F5

F4

G5

D2

H5

H4

J5

B7

C7

A5

C6

A4

C5

D6

E4

B3

C1

E3

G4

E2

G3

F1

H3

H2

K4

K3

K2

L3

VREF

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

3

4

U1

V2

U2

V4

VREF

-

√

VREF

-

V5

V3

1

-

VREF

W1

W3

2

-

W4

W5

√

VREF

Y3

Y4

√

-

CS

AA1

AA3

AB3

AC1

AC3

AC4

AE1

AD4

AF2

AG2

AH1

AF4

AJ2

AG4

AJ3

AL1

AJ4

AL4

AK5

AL5

AM4

AK7

AM6

AL7

AN7

Y5

2

-

DIN, D0

AA4

AA5

AB4

AB5

AD3

AC5

AF1

AD5

AE4

AE5

AJ1

AF5

AK2

AG5

AH4

AH5

AJ6

AN3

AJ7

AM5

AL6

AN6

AJ9

AL8

√

VREF

1

-

2

-

VREF

√

D5

-

√

VREF

-

1

-

VREF

√

VREF

1

-

J4

-

1

VREF

K5

J3

VREF

√

VREF

-

√

-

L5

L4

M5

L1

N5

N4

N2

P4

P2

R4

R1

T5

T2

D1

1

-

D2

√

VREF

-

1

-

VREF

INIT

-

M4

M2

N3

P5

P3

R5

R3

T4

T3

U3

-

1

VREF

√

-

√

-

NA

√

VREF

-

D3

-

√

VREF

-

2

VREF

-

√

-

√

VREF

NA

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

21

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 5: BG560/CG560 Differential Pin Pair Summary

XQV1000E, XQV2000E

P

N

Other

P

N

Other

Pair Bank

AO

√

Functions

Pair Bank

AO

√

1

√

2

1

√

2

√

2

1

√

2

√

2

1

√

2

√

2

1

√

2

√

2

Functions

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

4

5

AM8

AL9

AJ10

AM9

-

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

5

6

7

AN29

AK26

AM30

AK27

AN31

AM31

AJ30

AH30

AJ31

AG30

AF29

AF30

AH33

AE30

AF32

AD30

AC29

AC30

AC31

AB30

AA29

AA31

Y29

AJ25

AM29

AJ26

AL29

AJ27

AK28

AH29

AK31

AG29

AK32

AH31

AH32

AE29

AG33

AD29

AE31

AE32

AD31

AB29

AC33

AB31

AA30

AA32

AA33

Y32

VREF

√

VREF

-

AK10

AL10

AL11

AN11

AL12

AK13

AM13

AJ14

AM14

AJ15

AL15

AL16

AK16

AN9

2

-

AM10

AJ12

AK12

AM12

AL13

AN13

AK14

AN15

AK15

AM16

AJ16

AN17

√

VREF

√

-

NA

√

-

VREF

-

√

VREF

2

-

√

-

VREF

√

VREF

-

NA

√

-

VREF

√

VREF

2

-

AM17 AM18

NA IO_LVDS_DLL

VREF

AK18

AN19

AK19

AJ19

AN21

AJ20

AK21

AJ21

AK22

AL23

AK23

AN26

AK24

AM27

AL26

AJ18

AL19

AM20

AL20

AL21

AM22

AN23

AM23

AM24

AJ22

AL24

AJ23

AM26

AJ24

AK25

√

VREF

-

VREF

NA

√

-

VREF

-

√

-

2

-

VREF

√

VREF

-

√

-

Y30

-

NA

√

-

W29

VREF

-

W31

W30

-

√

VREF

-

V30

W33

-

1

V31

V29

VREF

-

√

VREF

-

U33

V32

√

U32

U31

√

VREF

T30

T32

VREF

Module 4 of 4

22

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 5: BG560/CG560 Differential Pin Pair Summary

XQV1000E, XQV2000E

P

N

Other

Pair Bank

AO

√

1

2

√

2

√

1

2

√

1

√

1

√

1

√

1

Functions

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

Notes:

7

T31

R31

R29

P31

P29

N31

L33

L32

L31

J33

T29

R33

R30

P32

P30

M32

N30

M31

M30

M29

L30

L29

J31

VREF

-

VREF

-

VREF

-

K31

H33

H32

H31

G32

G31

E32

F31

E31

C33

D31

VREF

-

VREF

K29

J30

-

VREF

J29

VREF

E33

H29

D32

G29

F30

-

VREF

-

VREF

1. AO in the XQV1000E.

2. AO in the XQV2000E.

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

23

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

FG1156 Fine-Pitch Ball Grid Array Package

Bank

0

Pin Description

IO_L8N_Y

Pin #

K12

E8

XQV2000E devices only are available in the FG1156

fine-pitch Ball Grid Array package. See Table 6 for pinout

information. Immediately following Table 6, see Table 7 for

Differential Pair information.

IO_L8P_Y

IO_L9N

B6

Table 6: FG1156 — XQV2000E

IO_L9P

F9

Bank

0

Pin Description

Pin #

E17

B4

IO_L10N_YY

IO_L10P_YY

IO_VREF_L11N_YY

IO_L11P_YY

IO_L12N

G10

C7

GCK3

0

IO

D8

0

IO

B9

B7

0

B10

D9

H11

0

IO

5

IO_L12P

C8

0

IO

D16

E7

IO_L13N_Y

IO_L13P_Y

IO_VREF_L14N_Y

IO_L14P_Y

IO_L15N

E9

B8

0

IO

0

IO

E11

E13

E16

F17

J12

J13

J14

K11

F7

K13

G11

A8

0

IO

0

IO

0

IO

IO_L15P

F10

C9

0

IO

IO_L16N_YY

IO_L16P_YY

IO_VREF_L17N_YY

IO_L17P_YY

IO_L18N_Y

IO_L18P_Y

IO_L19N_Y

IO_L19P_Y

IO_VREF_L20N_YY

IO_L20P_YY

IO_L21N_YY

IO_L21P_YY

IO_L22N_Y

IO_L22P_Y

IO_L23N_Y

IO_L23P_Y

IO_L24N_Y

IO_L24P_Y

IO_L25N_Y

0

IO

H12

D10

A9

0

IO

0

IO

0

IO_L0N_Y

IO_L0P_Y

IO_L1N_Y

IO_L1P_Y

IO_VREF_L2N_Y

IO_L2P_Y

IO_L3N_Y

IO_L3P_Y

IO_L4N_YY

IO_L4P_YY

IO_VREF_L5N_YY

IO_L5P_YY

IO_L6N_YY

IO_L6P_YY

IO_L7N_Y

IO_L7P_Y

F11

A10

K14

C10

H13

G12

A11

B11

E12

D11

G13

C12

K15

A12

B12

0

H9

0

C5

0

J10

E6

0

D6

0

A4

0

G8

0

C6

0

J11

G9

0

F8

0

A5

0

H10

D7

0

B5

Module 4 of 4

24

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

0

Pin Description

IO_L25P_Y

Pin #

H14

D12

F13

A13

B13

J15

Bank

1

Pin Description

Pin #

D17

A18

B18

B24

B25

E22

E23

D18

D19

D25

D26

D28

D29

G23

J23

GCK2

IO_L26N_YY

IO_L26P_YY

IO_VREF_L27N_YY

IO_L27P_YY

IO_L28N_YY

IO_L28P_YY

IO_L29N_Y

IO

G14

C13

F14

H15

D13

A14

K16

E14

B14

G15

D14

J16

IO

IO_L29P_Y

IO

IO_L30N_Y

IO

IO_L30P_Y

IO

IO_L31N

IO

IO_L31P

IO

IO_L32N_YY

IO_L32P_YY

IO_VREF_L33N_YY

IO_L33P_YY

IO_L34N

IO

IO_LVDS_DLL_L42P

IO_L43N_Y

IO_VREF_L43P_Y

IO_L44N_Y

IO_L44P_Y

IO_L45N_YY

IO_VREF_L45P_YY

IO_L46N_YY

IO_L46P_YY

IO_L47N

IO_L47P

IO_L48N_Y

IO_L48P_Y

IO_L49N_Y

IO_L49P_Y

IO_L50N

IO_L50P

IO_L51N_YY

IO_VREF_L51P_YY

IO_L52N_YY

J18

G18

C18

H18

F18

B19

A19

K19

C19

F19

E19

G19

J19

IO_L34P

D15

F15

B15

A15

E15

G16

A16

F16

J17

IO_L35N_Y

IO_L35P_Y

IO_L36N_Y

IO_L36P_Y

IO_L37N

IO_L37P

IO_L38N_YY

IO_L38P_YY

IO_VREF_L39N_YY

IO_L39P_YY

IO_L40N_Y

C16

B16

H17

A17

G17

B17

C17

A20

G20

B20

F20

D20

E20

H20

IO_L40P_Y

IO_VREF_L41N_Y

IO_L41P_Y

IO_LVDS_DLL_L42N

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

25

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

1

Pin Description

IO_L52P_YY

IO_L53N

Pin #

A21

E21

J20

Bank

1

Pin Description

IO_L70N_Y

Pin #

C26

H24

G24

A27

B27

G25

E26

C27

J24

1

IO_VREF_L70P_Y

IO_L71N_Y

IO_L53P

1

IO_L54N_Y

IO_L54P_Y

D21

K20

B21

H21

G21

F21

A22

B22

J21

1

IO_L71P_Y

1

IO_L72N

IO_L55N_Y

IO_L55P_Y

1

IO_L72P

1

IO_L73N_YY

IO_VREF_L73P_YY

IO_L74N_YY

IO_L74P_YY

IO_L75N

IO_L56N_YY

IO_L56P_YY

IO_L57N_YY

IO_VREF_L57P_YY

IO_L58N_YY

IO_L58P_YY

IO_L59N_Y

IO_L59P_Y

1

B28

K24

H25

D27

F26

G26

C28

E27

J25

1

IO_L75P

C22

D22

G22

K21

A23

F22

B23

C23

H22

D23

K22

A24

J22

1

IO_L76N_Y

1

IO_L76P_Y

1

IO_L77N_Y

IO_L60N_Y

IO_L60P_Y

1

IO_L77P_Y

1

IO_L78N_YY

IO_L78P_YY

IO_L79N_YY

IO_VREF_L79P_YY

IO_L80N_YY

IO_L80P_YY

IO_L81N_Y

IO_L61N_Y

IO_L61P_Y

1

A30

H26

G27

B29

F27

C29

E28

F28

L25

B30

B31

E29

A31

D30

IO_L62N_Y

IO_L62P_Y

1

IO_L63N_YY

IO_L63P_YY

IO_L64N_YY

IO_VREF_L64P_YY

IO_L65N_Y

IO_L65P_Y

1

IO_L81P_Y

1

IO_L82N_Y

H23

D24

A25

E24

A26

C25

F24

B26

K23

F25

1

IO_VREF_L82P_Y

IO_L83N_Y

1

IO_L66N_Y

IO_L66P_Y

1

IO_L83P_Y

1

IO_L84N

IO_L67N_YY

IO_VREF_L67P_YY

IO_L68N_YY

IO_L68P_YY

IO_L69N

1

IO_L84P

1

IO_WRITE_L85N_YY

IO_CS_L85P_YY

1

2

IO

F31

J32

IO_L69P

Module 4 of 4

26

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

2

Pin Description

Pin #

K27

K31

L28

L30

M32

N26

N28

P25

U26

U30

U32

U34

M30

D32

J27

Bank

2

Pin Description

IO_L97P_Y

Pin #

M26

E34

H31

G32

N25

J31

IO

IO_L97N_Y

IO

IO_VREF_L98P_YY

IO_L98N_YY

IO_L99P_YY

IO_L99N_YY

IO_L100P_YY

IO_L100N_YY

IO_VREF_L101P_Y

IO_L101N_Y

IO_L102P

IO

J30

IO

G33

H34

J29

IO

M27

H33

K29

J34

IO

IO_L102N

IO_D2

IO_L103P_Y

IO_DOUT_BUSY_L86P_YY

IO_DIN_D0_L86N_YY

IO_L87P_Y

IO_L87N_Y

IO_L88P_Y

IO_L88N_Y

IO_VREF_L89P_Y

IO_L89N_Y

IO_L90P

IO_L103N_Y

IO_VREF_L104P_YY

IO_L104N_YY

IO_L105P_YY

IO_L105N_YY

IO_L106P_Y

L29

J33

E31

F30

G29

F32

E32

G30

M25

G31

L26

D33

D34

H29

J28

M28

K34

N27

L34

K33

P26

R25

M34

L31

L33

P27

M33

M31

R26

N30

P28

N29

N33

T25

IO_L106N_Y

IO_VREF_L107P_YY

IO_D1_L107N_YY

IO_L108P_Y

IO_L90N

IO_L91P_Y

IO_L91N_Y

IO_VREF_L92P_Y

IO_L92N_Y

IO_L93P_YY

IO_L93N_YY

IO_L94P_YY

IO_L94N_YY

IO_L95P_Y

IO_L95N_Y

IO_L96P_Y

IO_L96N_Y

IO_L108N_Y

IO_L109P_Y

IO_L109N_Y

IO_L110P_Y

IO_L110N_Y

IO_L111P

E33

H28

H30

H32

K28

L27

F33

IO_L111N

IO_L112P_Y

IO_L112N_Y

IO_VREF_L113P_Y

IO_L113N_Y

IO_L114P_YY

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

27

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

2

Pin Description

IO_L114N_YY

IO_L115P_YY

IO_L115N_YY

IO_L116P_Y

Pin #

N34

P34

R27

P29

P31

P33

T26

R34

R28

N31

N32

P30

R33

R29

T34

R30

T30

T28

R31

T29

U27

T31

T33

U28

T32

U29

U33

V33

U31

Bank

3

Pin Description

IO

Pin #

AB26

AB31

AC31

AF34

AG31

AG33

AG34

AH29

AJ30

V26

2

IO

2

IO

2

IO

2

IO_L116N_Y

IO

2

IO_L117P_Y

IO

2

IO_L117N_Y

IO

2

IO_L118P_Y

IO

2

IO_L118N_Y

IO

2

IO_VREF_L119P_YY

IO_D3_L119N_YY

IO_L120P_YY

IO_L120N_YY

IO_L121P_YY

IO_L121N_YY

IO_L122P_Y

IO_L129P_Y

IO_VREF_L129N_Y

IO_L130P_YY

IO_L130N_YY

IO_L131P_YY

IO_VREF_L131N_YY

IO_L132P_Y

IO_L132N_Y

IO_L133P

2

V30

2

W34

V28

2

W32

W30

V29

2

IO_L122N_Y

Y34

2

IO_L123P

W29

Y33

2

IO_L123N

IO_L133N

2

IO_L124P_Y

IO_L134P_Y

IO_L134N_Y

IO_L135P_YY

IO_L135N_YY

IO_L136P_YY

IO_L136N_YY

IO_D4_L137P_YY

IO_VREF_L137N_YY

IO_L138P_Y

IO_L138N_Y

IO_L139P_Y

IO_L139N_Y

IO_L140P_Y

IO_L140N_Y

IO_L141P_YY

IO_L141N_YY

W26

W28

Y31

2

IO_L124N_Y

2

IO_VREF_L125P_YY

IO_L125N_YY

IO_L126P_YY

IO_L126N_YY

IO_VREF_L127P_Y

IO_L127N_Y

2

Y30

2

AA34

W31

AA33

Y29

2

IO_L128P_YY

IO_L128N_YY

W25

AB34

Y28

2

3

IO

V27

V31

AB33

AA30

Y26

V32

W33

AB25

Y27

AA31

Module 4 of 4

28

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

3

Pin Description

IO_L142P_YY

IO_L142N_YY

IO_L143P_Y

Pin #

AA27

AA29

AB32

AB29

AA28

AC34

Y25

Bank

3

Pin Description

IO_VREF_L159N_YY

IO_L160P_Y

IO_L160N_Y

IO_L161P_Y

IO_L161N_Y

IO_L162P_Y

IO_L162N_Y

IO_L163P_YY

IO_L163N_YY

IO_L164P_YY

IO_L164N_YY

IO_L165P_Y

IO_VREF_L165N_Y

IO_L166P_Y

IO_L166N_Y

IO_L167P

Pin #

AF30

AC25

AH32

AE28

AL34

AG30

AD27

AF29

AK34

AD25

AE27

AJ33

AH31

AE26

AL33

AF28

AL32

AJ31

AF27

AG29

AJ32

AK33

AH30

AK32

AK31

V34

3

IO_VREF_L143N_Y

IO_L144P_Y

3

IO_L144N_Y

3

IO_L145P

3

IO_L145N

AD34

AB30

AC33

AA26

AC32

AD33

AB28

AE34

AB27

AE33

AC30

AA25

AE32

AE31

AD29

AD31

AF33

AC28

AF31

AC27

AF32

AE29

AD28

AD30

AG32

AC26

AH33

AD26

3

IO_L146P_Y

3

IO_L146N_Y

3

IO_L147P_Y

3

IO_L147N_Y

3

IO_L148P_Y

3

IO_L148N_Y

3

IO_L149P_YY

IO_D5_L149N_YY

IO_D6_L150P_YY

IO_VREF_L150N_YY

IO_L151P_Y

3

IO_L167N

3

IO_L168P_Y

IO_VREF_L168N_Y

IO_L169P_Y

IO_L169N_Y

IO_L170P_Y

IO_L170N_Y

IO_D7_L171P_YY

IO_INIT_L171N_YY

IO

3

IO_L151N_Y

3

IO_L152P_YY

IO_L152N_YY

IO_L153P_YY

IO_VREF_L153N_YY

IO_L154P_Y

3

IO_L154N_Y

3

IO_L155P_Y

IO_L155N_Y

4

GCK0

IO

AH18

AE21

AG18

AG23

AH24

AH25

AJ28

AK18

IO_L156P_Y

IO_VREF_L156N_Y

IO_L157P_YY

IO_L157N_YY

IO_L158P_YY

IO_L158N_YY

IO_L159P_YY

IO

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

29

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

4

Pin Description

IO

Pin #

AK19

AL25

AL27

AL30

AN18

AN22

AN24

AP31

AK29

AP30

AN31

AH27

AN30

AM30

AK28

AG26

AN29

AF25

AM29

AL29

AL28

AE24

AN28

AJ27

AH26

AG25

AK27

AM28

AF24

AJ26

AP27

AK26

AN27

AE23

AM27

Bank

4

Pin Description

IO_L186P_Y

Pin #

AL26

AP26

AN26

AJ25

AG24

AP25

AF23

AM26

AJ24

AN25

AE22

AM25

AK24

AH23

AF22

AP24

AL24

AK23

AG22

AN23

AP23

AM23

AH22

AP22

AL23

AF21

AL22

AJ22

AK22

AM22

AG21

AJ21

AP21

AE20

AH21

IO

IO_L186N_Y

IO

IO_VREF_L187P_Y

IO_L187N_Y

IO

IO_L188P

IO

IO_L188N

IO

IO_L189P_YY

IO_L189N_YY

IO_VREF_L190P_YY

IO_L190N_YY

IO_L191P_Y

IO_L172P_YY

IO_L172N_YY

IO_L173P_Y

IO_L173N_Y

IO_L174P_Y

IO_L174N_Y

IO_VREF_L175P_Y

IO_L175N_Y

IO_L176P_Y

IO_L176N_Y

IO_L177P_YY

IO_L177N_YY

IO_VREF_L178P_YY

IO_L178N_YY

IO_L179P_YY

IO_L179N_YY

IO_L180P_Y

IO_L180N_Y

IO_L181P_Y

IO_L181N_Y

IO_L182P

IO_L191N_Y

IO_L192P_Y

IO_L192N_Y

IO_VREF_L193P_YY

IO_L193N_YY

IO_L194P_YY

IO_L194N_YY

IO_L195P_Y

IO_L195N_Y

IO_L196P_Y

IO_L196N_Y

IO_L197P_Y

IO_L197N_Y

IO_L198P_Y

IO_L198N_Y

IO_L199P_YY

IO_L199N_YY

IO_VREF_L200P_YY

IO_L200N_YY

IO_L201P_YY

IO_L201N_YY

IO_L202P_Y

IO_L182N

IO_L183P_YY

IO_L183N_YY

IO_VREF_L184P_YY

IO_L184N_YY

IO_L185P

IO_L202N_Y

IO_L185N

IO_L203P_Y

Module 4 of 4

30

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

4

Pin Description

IO_L203N_Y

Pin #

AL21

AN21

AF20

AK21

AP20

AE19

AN20

AG20

AL20

AH20

AK20

AN19

AJ20

AF19

AP19

AM19

AH19

AJ19

AP18

AF18

AP17

AJ18

AL18

AM18

Bank

5

Pin Description

IO

Pin #

AN9

4

IO_L204P

IO

AN10

AN16

AN17

AL17

AH17

AM17

AJ17

AG17

AP16

AL16

AJ16

AM16

AK16

AP15

AL15

AH16

AN15

AF16

AP14

AE16

AK15

AJ15

AH15

AN14

AK14

AG15

AM13

AF15

AG14

AP13

AE14

AE15

AN13

AG13

4

IO_L204N

IO

4

IO_L205P_YY

IO_L205N_YY

IO_VREF_L206P_YY

IO_L206N_YY

IO_L207P_Y

IO

4

IO_LVDS_DLL_L215N

IO_L216P_Y

IO_VREF_L216N_Y

IO_L217P_Y

IO_L217N_Y

IO_L218P_YY

IO_VREF_L218N_YY

IO_L219P_YY

IO_L219N_YY

IO_L220P

4

IO_L207N_Y

4

IO_L208P_Y

4

IO_L208N_Y

4

IO_L209P_Y

4

IO_L209N_Y

4

IO_L210P

4

IO_L210N

IO_L220N

4

IO_L211P_YY

IO_L211N_YY

IO_VREF_L212P_YY

IO_L212N_YY

IO_L213P_Y

IO_L221P_Y

IO_L221N_Y

IO_L222P_Y

IO_L222N_Y

IO_L223P_Y

IO_L223N_Y

IO_L224P_YY

IO_VREF_L224N_YY

IO_L225P_YY

IO_L225N_YY

IO_L226P

4

IO_L213N_Y

4

IO_VREF_L214P_Y

IO_L214N_Y

4

IO_LVDS_DLL_L215P

5

GCK1

IO

AL19

AF17

AG12

AH12

AJ10

AJ11

AK7

IO_L226N

IO

IO_L227P_Y

IO_L227N_Y

IO_L228P_Y

IO_L228N_Y

IO_L229P_YY

IO_L229N_YY

IO_L230P_YY

IO_VREF_L230N_YY

IO

AK13

AL13

AM4

IO

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

31

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

5

Pin Description

IO_L231P_YY

IO_L231N_YY

IO_L232P_Y

Pin #

AH14

AP12

AJ14

AL14

AF13

AN12

AF14

AP11

AN11

AH13

AM12

AL12

AJ13

AP10

AK12

AM10

AP9

Bank

5

Pin Description

IO_L248N

Pin #

AJ9

5

IO_L249P_Y

AM7

AL7

5

IO_L249N_Y

IO_L232N_Y

IO_L233P_Y

5

IO_L250P_Y

AG10

AN6

AK8

AH9

AP5

AJ8

5

IO_L250N_Y

IO_L233N_Y

IO_L234P_Y

5

IO_L251P_YY

IO_L251N_YY

IO_L252P_YY

IO_VREF_L252N_YY

IO_L253P_YY

IO_L253N_YY

IO_L254P_Y

5

IO_L234N_Y

IO_L235P_Y

5

IO_L235N_Y

IO_L236P_YY

IO_L236N_YY

IO_L237P_YY

IO_VREF_L237N_YY

IO_L238P_Y

5

AE11

AN5

AF10

AM6

AL6

5

IO_L254N_Y

5

IO_L255P_Y

5

IO_VREF_L255N_Y

IO_L256P_Y

AG9

AH8

AP4

AN4

AJ7

IO_L238N_Y

IO_L239P_Y

5

IO_L256N_Y

IO_L257P_Y

IO_L239N_Y

IO_L240P_YY

IO_VREF_L240N_YY

IO_L241P_YY

IO_L241N_YY

IO_L242P

AK11

AL11

AL10

AE13

AM9

5

IO_L257N_Y

5

IO_L258P_YY

IO_L258N_YY

AM5

AK6

5

AF12

AP8

6

IO

T1

V2

IO_L242N

IO_L243P_Y

AL9

V3

IO_VREF_L243N_Y

IO_L244P_Y

AH11

AF11

AN8

V5

V8

IO_L244N_Y

IO_L245P_Y

AA10

AB5

AB7

AB9

AD7

AD8

AE2

AE4

AM8

IO_L245N_Y

IO_L246P_YY

IO_VREF_L246N_YY

IO_L247P_YY

IO_L247N_YY

IO_L248P

AG11

AL8

AK9

AH10

AN7

AE12

Module 4 of 4

32

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

6

Pin Description

IO

Pin #

AJ4

Bank

6

Pin Description

IO_L275P

Pin #

AF2

AC8

AE1

AD5

AE3

AC7

AD1

AD6

AD2

AB8

AC1

AC5

AC2

AA9

AC3

AC4

AD4

AA8

AB6

AB1

Y10

AB2

AA7

AA4

AA1

Y9

IO

AH5

AH6

AF8

AE9

AK3

AD10

AL2

AL1

AH4

AG6

AK1

AF7

AK2

AJ3

IO_L276N_Y

IO_L276P_Y

IO_VREF_L277N_YY

IO_L277P_YY

IO_L278N_YY

IO_L278P_YY

IO_L279N_Y

IO_L279P_Y

IO_VREF_L280N_YY

IO_L280P_YY

IO_L281N_YY

IO_L281P_YY

IO_L282N_Y

IO_L282P_Y

IO_L283N_Y

IO_L283P_Y

IO_L284N_Y

IO_L284P_Y

IO_L285N

IO_L259N_YY

IO_L259P_YY

IO_L260N_Y

IO_L260P_Y

IO_L261N_Y

IO_L261P_Y

IO_VREF_L262N_Y

IO_L262P_Y

IO_L263N

IO_L263P

IO_L264N_Y

IO_L264P_Y

IO_VREF_L265N_Y

IO_L265P_Y

IO_L266N_YY

IO_L266P_YY

IO_L267N_YY

IO_L267P_YY

IO_L268N_Y

IO_L268P_Y

IO_L269N_Y

IO_L269P_Y

IO_L270N_Y

IO_L270P_Y

IO_VREF_L271N_YY

IO_L271P_YY

IO_L272N_YY

IO_L272P_YY

IO_L273N_YY

IO_L273P_YY

IO_VREF_L274N_Y

IO_L274P_Y

IO_L275N

AG5

AD9

AJ2

AC10

AH2

AH3

AF5

AE8

AG3

AE7

AG2

AF6

AG1

AC9

AG4

AE6

AF3

AF1

AF4

AB10

IO_L285P

IO_L286N_Y

IO_L286P_Y

IO_VREF_L287N_Y

IO_L287P_Y

IO_L288N_YY

IO_L288P_YY

IO_L289N_YY

IO_L289P_YY

IO_L290N_Y

IO_L290P_Y

IO_L291N_Y

IO_L291P_Y

IO_L292N_Y

IO_L292P_Y

AB4

AA2

Y8

AA6

AA5

AB3

Y7

Y1

W10

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

33

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

6

Pin Description

IO_VREF_L293N_YY

IO_L293P_YY

IO_L294N_YY

IO_L294P_YY

IO_L295N_YY

IO_L295P_YY

IO_L296N_Y

Pin #

Y5

Bank

7

Pin Description

IO_L302N_YY

IO_L302P_YY

IO_L303N_Y

Pin #

U9

U4

U7

U5

U3

U6

T3

6

Y2

6

W9

W2

W7

Y4

6

IO_VREF_L303P_Y

IO_L304N_YY

IO_L304P_YY

IO_L305N_YY

IO_VREF_L305P_YY

IO_L306N_Y

6

W1

Y6

6

IO_L296P_Y

T6

6

IO_L297N_Y

W6

W3

V9

T9

6

IO_L297P_Y

IO_L306P_Y

T4

6

IO_L298N_Y

IO_L307N_Y

T5

6

IO_L298P_Y

W4

W5

V1

IO_L307P_Y

R1

R6

T10

R2

R5

P1

P5

R8

P2

R9

N1

P4

R10

P8

N2

P6

P7

M1

N4

N6

N3

P9

M2

N7

6

IO_VREF_L299N_YY

IO_L299P_YY

IO_L300N_YY

IO_L300P_YY

IO_VREF_L301N_Y

IO_L301P_Y

IO_L308N_Y

6

IO_L308P_Y

6

V7

IO_L309N_YY

IO_L309P_YY

IO_L310N_YY

IO_VREF_L310P_YY

IO_L311N_Y

6

U2

6

V6

6

U1

7

IO

F5

G6

H1

H7

K2

IO_L311P_Y

IO_L312N_Y

IO_L312P_Y

IO_L313N_Y

IO_L313P_Y

K4

IO_L314N_YY

IO_L314P_YY

IO_L315N_YY

IO_L315P_YY

IO_L316N_Y

L6

M5

M10

N5

N10

R7

T2

IO_VREF_L316P_Y

IO_L317N_Y

IO_L317P_Y

T7

IO_L318N

U8

IO_L318P

3

V4

IO_L319N_Y

Module 4 of 4

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DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

7

Pin Description

IO_L319P_Y

Pin #

M3

P10

M4

L1

Bank

Pin Description

IO_L337N_YY

IO_L337P_YY

IO_L338N_Y

Pin #

F3

7

IO_L320N_Y

L10

E1

H6

G5

E2

K9

D1

E3

J8

IO_L320P_Y

IO_L321N_Y

IO_VREF_L338P_Y_Y

IO_L339N_Y

IO_L321P_Y

N8

L2

IO_L322N_YY

IO_L322P_YY

IO_L323N_YY

IO_VREF_L323P_YY

IO_L324N_Y

IO_L339P_Y

N9

M7

K1

M8

L4

IO_L340N

IO_L340P

IO_L341N_Y

IO_VREF_L341P_Y

IO_L342N_Y

IO_L324P_Y

E4

D2

F4

IO_L325N_YY

IO_L325P_YY

IO_L326N_YY

IO_VREF_L326P_YY

IO_L327N_Y

J1

IO_L342P_Y

L5

IO_L343N_Y

J2

IO_L343P_Y

D3

K3

L7

2

CCLK

DONE

DXN

C31

AM31

AJ5

AL5

AK4

AG7

AL3

AG28

D5

IO_L327P_Y

J3

3

IO_L328N_Y

M9

NA

2

4

IO_L328P_Y

H2

DXP

IO_L329N_Y

J4

K6

L8

G2

H3

K7

G3

J5

M0

IO_VREF_L329P_Y

IO_L330N_YY

IO_L330P_YY

IO_L331N_YY

IO_L331P_YY

IO_L332N_YY

IO_VREF_L332P_YY

IO_L333N_Y

M1

M2

PROGRAM

TCK

TDI

C30

K26

C4

TDO

NA

TMS

L9

H5

J6

IO_L333P_Y

NA

VCCINT

K10

K17

K18

K25

L11

L24

M12

IO_L334N_Y

IO_L334P_Y

H4

G4

K8

J7

IO_L335N_Y

IO_L335P_Y

IO_L336N_YY

IO_L336P_YY

F2

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

35

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

NA

Pin Description

VCCINT

Pin #

M23

N13

Bank

NA

Pin Description

VCCINT

Pin #

AD24

AD11

AE10

AE17

AE18

AE25

NA

VCCINT

N14

NA

VCCINT

N15

NA

VCCINT

N16

NA

VCCINT

N19

NA

VCCINT

N20

N21

NA

VCCO_0

VCCO_1

M17

L17

L16

E10

C14

A6

N22

P13

P22

R13

R22

T13

M13

M14

M15

M16

L12

L13

L14

L15

M18

L18

L23

E25

C21

A29

M19

M20

M21

M22

L19

L20

L21

L22

T22

U10

U25

V10

V25

W13

W22

Y13

Y22

AA13

AA22

AB13

AB14

AB15

AB16

AB19

AB20

AB21

AB22

AC12

AC23

Module 4 of 4

36

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DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

NA

Pin Description

VCCO_2

VCCO_3

VCCO_4

Pin #

U24

Bank

NA

Pin Description

VCCO_4

VCCO_5

VCCO_6

Pin #

AM21

AK25

AD19

AD20

AD21

AD22

AD23

AC17

AD17

AC13

AC14

AC15

AC16

AP6

U23

N24

M24

K30

F34

T23

T24

R23

R24

P23

P24

P32

N23

V23

AM14

AK10

AD12

AD13

AD14

AD15

AD16

V11

V24

Y23

Y24

W23

W24

AJ34

AE30

AC24

AB23

AB24

AA23

AA24

AA32

AD18

AC18

AC19

AC20

AC21

AC22

AP29

V12

Y11

Y12

W11

W12

AJ1

AE5

AC11

AB11

AB12

AA3

AA11

AA12

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

37

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

NA

Pin Description

VCCO_7

Pin #

U11

U12

N12

M11

K5

Bank

NA

Pin Description

GND

Pin #

AP1

AN2

AM15

AK17

AH34

AC6

AA21

Y21

W20

V20

U21

T21

F1

T11

T12

R11

R12

P3

P11

P12

N11

R20

P20

H16

F23

NA

GND

K32

R4

C3

AN1

AM11

AK5

AH28

AD32

AA20

Y20

W19

V19

U20

T20

R19

P19

H8

B2

A28

AP34

AM3

AL31

AH7

AD3

AA19

Y19

W18

V18

U19

T19

R18

P18

J26

F12

C2

B1

F6

A7

C1

Module 4 of 4

38

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DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

NA

Pin Description

GND

Pin #

C34

A3

Bank

NA

Pin Description

GND

Pin #

H27

E5

AP2

AN3

AM20

AK30

AG8

AC29

Y3

C15

B32

A33

AP7

AN33

AM32

AJ12

AG19

AA15

Y15

Y32

W21

V21

T8

W14

V14

T27

R21

P21

H19

F29

C11

B3

U15

T15

R14

P14

M29

G1

A32

AP3

AN32

AM24

AJ6

AG16

AA14

Y14

W8

E18

C20

B33

A34

AP28

AN34

AM33

AJ23

AG27

AA16

Y16

W27

U14

T14

R3

W15

V15

R32

M6

U16

T16

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

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1-800-255-7778

Module 4 of 4

39

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 6: FG1156 — XQV2000E

Bank

NA

Pin Description

GND

Pin #

R15

P15

L3

Bank

NA

Pin Description

GND

Pin #

T18

R17

P17

J9

GND

G7

GND

E30

C24

B34

AP32

AM1

AM34

AJ29

AF9

AA17

Y17

W16

V16

U17

T17

GND

G34

D31

C33

A2

GND

AB17

AB18

N17

N18

U13

V13

U22

V22

GND

FG1156 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-

vide other functions when not used as a differential pair. The

AO column in Table 7 indicates which pin pairs may be used

as an asynchronous output with a “√.” The “Other Func-

tions” column indicates alternative function(s) that are not

available when the pair is used as a differential pair or differ-

ential clock.

R16

P16

L32

G28

D4

Table 7: FG1156 Differential Pin Pair Summary:

XQV2000E

C32

A1

P

N

Other

Pair Bank

AO

Functions

AP33

AM2

AL4

AH1

AF26

AA18

Y18

W17

V17

U18

GCLK LVDS

3

2

1

0

1

5

4

E17

D17

C17

J18

NA

IO_DLL_L 42N

IO_DLL_L 42P

IO_DLL_L 215N

IO_DLL_L 215P

AL19 AL17

AH18 AM18

IO LVDS

Total Pairs: 344, Asynchronous Output Pairs: 134

0

1

0

H9

F7

C5

NA

-

J10

√

Module 4 of 4

40

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DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 7: FG1156 Differential Pin Pair Summary:

XQV2000E

P

N

Other

P

N

Other

Pair Bank

AO

√

Functions

Pair Bank

AO

√

Functions

2

0

D6

G8

E6

A4

VREF

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

0

1

E15

A16

J17

B16

A17

B17

J18

C18

F18

A19

C19

E19

J19

G20

F20

E20

A21

J20

K20

H21

F21

B22

C22

G22

A23

B23

H22

K22

J22

D24

E24

C25

B26

F25

A15

G16

F16

C16

H17

G17

C17

G18

H18

B19

K19

F19

G19

A20

B20

D20

H20

E21

D21

B21

G21

A22

J21

-

3

NA

√

-

NA

√

-

4

J11

F8

C6

-

5

G9

√

VREF

√

VREF

6

H10

B5

A5

√

-

NA

None

NA

√

-

7

D7

NA

√

-

VREF

8

E8

K12

B6

-

IO_LVDS_DLL

9

F9

-

VREF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

C7

G10

D8

-

B7

√

VREF

C8

H11

E9

NA

√

-

√

-

B8

-

√

-

G11

F10

H12

A9

K13

A8

√

VREF

√

-

NA

√

-

√

-

C9

-

NA

√

-

D10

F11

K14

H13

A11

E12

G13

K15

B12

D12

A13

J15

C13

H15

A14

E14

G15

J16

F15

√

VREF

A10

C10

G12

B11

D11

C12

A12

H14

F13

B13

G14

F14

D13

K16

B14

D14

D15

B15

NA

√

-

√

-

NA

√

-

VREF

-

√

-

NA

√

-

√

VREF

√

-

√

-

NA

√

-

D22

K21

F22

C23

D23

A24

H23

A25

A26

F24

K23

NA

√

-

√

VREF

√

-

√

-

NA

√

-

NA

√

-

√

VREF

-

NA

√

-

√

VREF

NA

√

-

√

-

NA

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

41

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 7: FG1156 Differential Pin Pair Summary:

XQV2000E

P

N

Other

P

N

Other

Pair Bank

AO

√

Functions

Pair Bank

AO

√

Functions

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

1

2

H24

A27

G25

C27

B28

H25

F26

C28

J25

C26

G24

B27

E26

J24

VREF

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

2

3

L29

M28

N27

K33

R25

L31

P27

M31

N30

N29

T25

P34

P29

P33

R34

N31

P30

R29

R30

T28

T29

T31

U28

U29

V33

V26

W34

W32

V29

W29

W26

Y31

J33

K34

L34

P26

M34

L33

M33

R26

P28

N33

N34

R27

P31

T26

R28

N32

R33

T34

T30

R31

U27

T33

T32

U33

U31

V30

V28

W30

Y34

Y33

W28

Y30

VREF

√

-

√

-

NA

√

-

NA

√

-

VREF

D1

√

-

√

-

K24

D27

G26

E27

A30

G27

F27

E28

L25

B31

A31

J27

NA

√

-

√

-

NA

√

-

H26

B29

C29

F28

B30

E29

D30

D32

E31

G29

E32

M25

L26

D34

J28

√

VREF

√

-

√

-

NA

√

-

√

-

VREF

NA

√

-

√

-

NA

√

-

√

-

CS

√

D3

√

DIN, D0

√

-

F30

F32

G30

G31

D33

H29

E33

H30

K28

F33

E34

G32

J31

√

-

√

-

√

-

NA

√

-

NA

√

VREF

-

VREF

√

-

√

-

NA

√

VREF

H28

H32

L27

M26

H31

N25

J30

√

-

NA

√

-

NA

√

VREF

-

√

-

√

VREF

√

VREF

NA

√

-

√

-

G33

J29

√

-

H34

M27

K29

NA

VREF

-

H33

J34

-

AA34 W31

AA33 Y29

√

VREF

Module 4 of 4

42

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1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 7: FG1156 Differential Pin Pair Summary:

XQV2000E

P

N

Other

P

N

Other

Pair Bank

AO

√

Functions

Pair Bank

AO

√

Functions

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

3

W25 AB34

-

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

4

AP31 AK29

AP30 AN31

AH27 AN30

AM30 AK28

AG26 AN29

AF25 AM29

AL29 AL28

AE24 AN28

AJ27 AH26

AG25 AK27

AM28 AF24

AJ26 AP27

AK26 AN27

AE23 AM27

AL26 AP26

AN26 AJ25

AG24 AP25

AF23 AM26

AJ24 AN25

AE22 AM25

AK24 AH23

AF22 AP24

AL24 AK23

AG22 AN23

AP23 AM23

AH22 AP22

AL23 AF21

AL22 AJ22

AK22 AM22

AG21 AJ21

AP21 AE20

AH21 AL21

AN21 AF20

AK21 AP20

-

Y28

AA30

Y27

AB33

Y26

√

-

NA

√

-

NA

√

-

AA31

-

√

VREF

AA27 AA29

AB32 AB29

AA28 AC34

Y25 AD34

AB30 AC33

AA26 AC32

AD33 AB28

AE34 AB27

AE33 AC30

AA25 AE32

AE31 AD29

AD31 AF33

AC28 AF31

AC27 AF32

AE29 AD28

AD30 AG32

AC26 AH33

AD26 AF30

AC25 AH32

AE28 AL34

AG30 AD27

AF29 AK34

AD25 AE27

AJ33 AH31

AE26 AL33

AF28 AL32

AJ31 AF27

AG29 AJ32

AK33 AH30

AK32 AK31

√

-

NA

√

-

√

VREF

-

NA

√

-

√

VREF

-

√

-

NA

√

-

√

-

√

D5

-

√

VREF

√

VREF

NA

√

-

NA

√

-

√

VREF

√

VREF

NA

√

-

NA

√

-

VREF

√

VREF

-

NA

√

-

√

-

√

VREF

√

-

√

-

√

-

NA

√

-

NA

√

-

√

-

√

-

NA

√

-

√

VREF

-

NA

√

-

√

VREF

-

√

-

VREF

NA

√

-

√

INIT

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

43

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 7: FG1156 Differential Pin Pair Summary:

XQV2000E

P

N

Other

P

N

Other

Pair Bank

AO

√

Functions

Pair Bank

AO

√

Functions

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

4

5

AE19 AN20

AG20 AL20

AH20 AK20

AN19 AJ20

AF19 AP19

AM19 AH19

AJ19 AP18

AF18 AP17

AJ18 AL18

AM18 AL17

AH17 AM17

AJ17 AG17

AP16 AL16

AJ16 AM16

AK16 AP15

AL15 AH16

AN15 AF16

AP14 AE16

AK15 AJ15

AH15 AN14

AK14 AG15

AM13 AF15

AG14 AP13

AE14 AE15

AN13 AG13

AH14 AP12

AJ14 AL14

AF13 AN12

AF14 AP11

AN11 AH13

AM12 AL12

AJ13 AP10

AK12 AM10

AP9 AK11

VREF

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

5

6

AL11 AL10

AE13 AM9

AF12 AP8

AL9 AH11

AF11 AN8

AM8 AG11

VREF

NA

√

-

√

-

NA

√

-

√

-

VREF

NA

√

-

√

-

NA

√

-

√

VREF

AL8

AK9

VREF

NA

None

NA

√

-

AH10 AN7

√

-

VREF

AE12

AM7

AJ9

AL7

NA

√

-

IO_LVDS_DLL

-

VREF

AG10 AN6

-

AK8

AP5

AH9

AJ8

-

VREF

√

VREF

√

-

AE11 AN5

AF10 AM6

√

-

NA

√

-

NA

√

-

AL6

AH8

AN4

AM5

AF8

AK3

AG9

AP4

AJ7

AK6

AH6

AE9

VREF

√

-

√

-

NA

√

-

NA

√

-

VREF

-

√

-

√

-

NA

√

-

√

-

AL2 AD10

√

-

AH4

AK1

AK2

AG5

AJ2

AL1

AG6

AF7

AJ3

AD9

NA

√

VREF

-

√

VREF

-

√

-

VREF

NA

√

-

√

-

AH2 AC10

√

-

√

-

AF5

AG3

AG2

AG1

AG4

AF3

AH3

AE8

AE7

AF6

AC9

AE6

NA

√

-

NA

√

-

√

-

√

VREF

√

VREF

NA

-

√

-

√

Module 4 of 4

44

www.xilinx.com

1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 7: FG1156 Differential Pin Pair Summary:

XQV2000E

P

N

Other

P

N

Other

Pair Bank

AO

NA

√

Functions

Pair Bank

AO

NA

√

Functions

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

6

7

AF4

AF1

VREF

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

7

T10

R5

P5

P2

N1

R10

N2

P7

N4

N3

M2

M3

M4

N8

N9

K1

L4

R6

R2

P1

R8

R9

P4

P8

P6

M1

N6

P9

N7

P10

L1

-

AF2 AB10

-

AE1

AE3

AD1

AD2

AC1

AC2

AC3

AD4

AB6

Y10

AA7

AA1

AB4

Y8

AC8

AD5

AC7

AD6

AB8

AC5

AA9

AC4

AA8

AB1

AB2

AA4

Y9

-

√

VREF

√

-

√

-

√

-

NA

√

-

NA

√

-

VREF

-

√

-

√

-

√

-

√

VREF

√

-

NA

√

-

NA

√

-

VREF

√

-

√

-

L2

√

-

AA2

AA6

AB3

Y1

√

-

M7

M8

J1

√

VREF

AA5

Y7

NA

√

-

NA

√

-

L5

-

W10

Y2

√

-

K3

J3

J2

√

VREF

Y5

√

VREF

L7

NA

√

-

W2

Y4

W9

W7

W1

W6

V9

√

-

H2

K6

G2

K7

J5

M9

J4

-

√

-

VREF

Y6

NA

√

-

L8

-

W3

W4

V1

-

H3

G3

L9

√

-

√

VREF

W5

V7

VREF

H5

H4

K8

F2

√

-

U2

√

-

J6

√

-

U1

V6

NA

√

VREF

G4

J7

NA

√

-

U4

U9

-

U5

U7

NA

√

VREF

L10

H6

E2

D1

F3

E1

G5

K9

√

-

U6

U3

-

√

VREF

T6

T3

√

VREF

NA

-

T4

T9

NA

-

R1

T5

DS096-4 (v1.1) July 29, 2004

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 4 of 4

45

R

QPro Virtex-E 1.8V QML High-Reliability FPGAs

Table 7: FG1156 Differential Pin Pair Summary:

XQV2000E

P

N

Other

Pair Bank

AO

NA

√

Functions

341

342

343

7

J8

D2

D3

E3

E4

F4

VREF

-

√

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

05/19/03

07/29/04

Initial Xilinx release.

1.1

•

Removed CB228 and HQ240 package pinout information (not offered).

Added “VREF” to pin description of pin B15 in package BG432 (XQV600E).

Module 4 of 4

46

www.xilinx.com

1-800-255-7778

DS096-4 (v1.1) July 29, 2004

Advance Product Specification


型号：	XQV2000E-6FGG1156N
厂家：	XILINX, INC
描述：	Field Programmable Gate Array, 9600 CLBs, 2541952 Gates, 357.2MHz, CMOS, PBGA1156, PLASTIC, FPBGA-1156 时钟栅可编程逻辑
文件：	总120页 (文件大小：881K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XQV2000E-6FGG1156N [XILINX]

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