223886855338 [YAGEO]
Ceramic Capacitor, Multilayer, Ceramic, 50V, 7.58% +Tol, 7.58% -Tol, C0G, 30ppm/Cel TC, 0.0000033uF, Surface Mount, 0201, CHIP, ROHS COMPLIANT;
| 型号： | 223886855338 |
| 厂家： | 
YAGEO CORPORATION |
| 描述： | Ceramic Capacitor, Multilayer, Ceramic, 50V, 7.58% +Tol, 7.58% -Tol, C0G, 30ppm/Cel TC, 0.0000033uF, Surface Mount, 0201, CHIP, ROHS COMPLIANT 电容器 |
| 文件： | 总13页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SURFACE-MOUNT CERAMIC
MULTILAYER CAPACITORS
Ultra small: NP0/X5R/X7R/Y5V
(
)
Pb Free & RoHS compliant
6.3 V TO 50 V
1 pF to 100 nF
Product specification
2
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
SCOPE
APPLICATIONS
FEATURES
z High capacitance per unit
z Mobile phones
z Digital cameras
z Camcorders
z Tuners
This specification describes ultra
small NP0/X5R/X7R/Y5V series
chip capacitors with lead-free
terminations.
volume
z Supplied in bulk case or in tape
on reel.
ORDERING INFORMATION
Components may be ordered by using either a Phycomp’s unique 12NC or Phycomp clear text code.
PHYCOMP ORDERING CODE
12NC CODE
For NP0 25V / X5R / X7R / Y5V
2 2 X X X X X X X X X X
Carrier type
22 blister
Capacitance value
See conversion table
(1)
38 paper
50 blister Ur ≤ 6.3 V
Tolerance
54 bulk
4
5
6
7
8
2%
5%
10%
20%
55 paper Ur ≤ 6.3 V
Rated voltage
−20/+80%
20 6.3 V
24 10 V
78 16 V
91 25 V
58 50 V
Temperature characteristic
1
3
5
9
NP0 25 V only
X5R
X7R
Y5V
(2)
Size
Packaging
8
0201
1
5
4
reel: ∅180 mm; 7"
SCM043
reel: ∅330 mm; 13"
bulk case
For NP0 50V
2 2 X X X X X X X X X X
Carrier type
38 paper
54 bulk
Capacitance value
See conversion table
(1)
Tolerance
4
0.1 pF for 0.47 pF ≤ C < 5 pF
0.25 pF for 5 pF ≤ C < 10 pF
2% for C ≥ 10 pF
Voltage
86 50 V
0.25 pF for C < 5 pF
5
0.5 pF for 5 pF ≤ C < 10 pF
5% for C ≥ 10 pF
Size
8
Packing
SCM044
0201
reel: ∅180 mm; 7"
1
7
4
reel: ∅330 mm; 13"
bulk case
(1) Refer to “Conversion table of capacitance & last 2/3 digits of 12NC”
(2) Quantity on reel depends on thickness classification; see section “Thickness classification and packing quantities”
www.yageo.com
Apr 19, 2006 V.2
Product specification
3
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
Conversion table of capacitance & last 2/3 digits of 12NC - NP0 25V
CAP.
(nF)
LAST 2 DIGITS
OF 12NC
CAP.
(nF)
LAST 2 DIGITS
OF 12NC
CAP.
(nF)
LAST 2 DIGITS
CAP.
(nF)
LAST 2 DIGITS
OF 12NC
OF 12NC
27
33
39
47
56
68
82
28
29
31
32
33
34
35
36
100
Conversion table of capacitance & last 2/3 digits of 12NC - NP0 50V
CAP.
(nF)
LAST 3 DIGITS OF
12NC
CAP.
(nF)
LAST 3 DIGITS OF
12NC
CAP.
(nF)
LAST 3 DIGITS OF
12NC
1.0
1.2
1.5
1.8
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
10
12
15
18
22
108
128
158
188
228
278
338
398
478
568
688
33
109
129
159
189
229
Conversion table of capacitance & last 2/3 digits of 12NC - X5R/X7R/Y5V
CAP.
(nF)
LAST 2 DIGITS OF
12NC
CAP.
(nF)
LAST 2 DIGITS OF
12NC
CAP.
(nF)
LAST 2 DIGITS OF
12NC
0.047
0.068
0.10
0.15
0.22
0.33
0.47
0.68
1.0
1.5
2.2
3.3
4.7
6.8
10
15
05
07
09
12
14
16
18
21
23
25
27
29
32
34
36
38
41
43
45
47
49
22
33
47
68
100
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Apr 19, 2006 V.2
Product specification
4
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
CTC CODE
Ä Example: 02012R102K8B20D
0201
2R
102
K
8
B
2
0
D
Size
code Char.
Temp.
Capacitance
in pF
Tolerance
Rated Termination
voltage
Packing
Marking
Range
identifier
0201 CG = NP0 102 = 1,000 pF; B = ±0.1 pF
5 = 6.3 V B = NiSn
6 = 10 V
2 = 180 mm; 7” paper 0 = no marking 0 = conv.
the third digit
signifies the
multiplying factor:
C = ±0.25 pF
D = ±0.5 pF
F = ±1%
ceramic
D = BME
L = low
0402 2B = X5R
0603 2R = X7R
0805 2F = Y5V
1206 2E = Z5U
1210
3 = 330 mm; 13” paper
B = 180 mm; 7” blister
F = 330 mm; 13” blister
P = Bulk case
7 = 16 V
8 = 25 V
8 = × 0.01
inductance
G = ±2%
9 = 50 V
9 = × 0.1
M = microwave
J = ±5%
0 = 100 V
B = 200 V
C = 250 V
D = 500 V
E = 1 KV
0 = × 1
K = ±10%
1808
1 = × 10
M = ±20%
Z = –20%~+80%
1812
2 = × 100
0306
3 = × 1,000
4 = × 10,000
5 = × 100,000
6 = × 1000,000
7 = × 10,000,000
0508
0612
F = 2 KV
G = 3 KV
H = 4 KV
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Apr 19, 2006 V.2
Product specification
5
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
CONSTRUCTION
The capacitor consists of a
rectangular block of ceramic
dielectric in which a number of
interleaved metal electrodes are
contained. This structure gives
rise to a high capacitance per
unit volume.
terminations
electrodes
The inner electrodes are
connected to the two end
terminations and finally covered
with a layer of plated tin (NiSn).
The terminations are lead-free. A
cross section of the structure is
shown in Fig.1.
MLB457
ceramic material
Fig. 1 Surface mounted multilayer ceramic capacitor construction
DIMENSION
Table 1
For dimension see Table 1
TYPE
L1 (mm)
W (mm)
T (mm)
L2/L3 (mm)
L4 (mm)
min.
min.
max.
0.20
CC0201
0.6 ±0.03
0.3 ±0.03
0.3 ±0.03
0.10
0.20
W
T
L
L
L
L
3
2
4
1
MBB211
Fig. 2 Surface mounted multilayer
ceramic capacitor dimension
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Apr 19, 2006 V.2
Product specification
6
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS FOR SIZE 0201 OF NP0 25/50 V
Table 2
CAPACITANCE
(pF)
0201
25 V
0201
50 V
1.0
1.2
1.5
1.8
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
10
0.3 ±0.03
12
15
18
22
27
0.3 ±0.03
33
39
47
56
68
82
100
NOTE
1. Values in shaded cells indicate thickness class in mm.
2. Capacitance range < 1 pF is on request.
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Apr 19, 2006 V.2
Product specification
7
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS FOR SIZE 0201 OF X5R/X7R/Y5V/ 6.3/10/16/25/50 V
Table 3
Y5V
CAPACITANCE
(nF)
X5R
X7R
10 V
16 V
25 V
50 V
6.3 V
6.3 V
0.047
0.068
0.10
0.15
0.22
0.33
0.47
0.68
1.0
0.3 ±0.03
0.3 ±0.03
0.3 ±0.03
0.3 ±0.03
1.5
2.2
3.3
4.7
6.8
10
15
22
33
47
68
100
0.3 ±0.03
0.3 ±0.03
NOTE
1. Values in shaded cells indicate thickness class in mm.
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Apr 19, 2006 V.2
Product specification
8
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
THICKNESS CLASSES AND PACKING QUANTITY
Table 4
DESCRIPTION
SIZE
THICKNESS 8 mm TAPE WIDTH/AMOUNT PER REEL 12 mm TAPE WIDTH
AMOUNT
PER
BULK CASE
CODE CLASSIFICATION
(mm)
/AMOUNT PER REEL
Ø180 mm, 7”
Ø330 mm, 13”
Paper
Blister
Paper
Blister Ø180 mm, 7” Blister
0201
0402
0603
0805
0.3 ±0.03
0.5 ±0.05
15,000
10,000
4,000
4,000
4,000
---
---
---
50,000
50,000
15,000
20,000
15,000
---
---
---
---
---
---
50,000
15,000
10,000
8,000
5,000
---
0.8 ±0.07
---
---
---
0.6 ±0.10
---
---
---
0.85 ±0.1
---
---
---
1.25 ±0.10
0.6 ±0.10
3,000
---
10,000
---
---
1206
1210
4,000
4,000
---
20,000
15,000
---
---
0.85 ±0.10
1.00 / 1.15 ±0.10
1.6 ±0.15
---
---
---
---
3,000
2 500
2,000
4,000
4,000
3,000
3,000
2,000
2,000
1,000
---
10,000
10,000
10,000
15,000
10,000
10,000
10,000
---
---
---
---
---
---
---
1.6 ±0.20
---
---
---
---
0.6 / 0.7 ±0.10
0.85 ±0.10
1.15 ±0.10
1.15 ±0.15
1.5 ±0.10
---
---
---
---
---
---
---
---
Discrete
capacitors
---
---
---
---
---
---
---
---
---
---
---
---
1.6 / 1.9 ±0.20
2.5 ±0.20
---
---
---
---
---
---
---
---
---
---
1808
1812
1.15 ±0.15
1.35 ±0.15
1.5 ±0.10
---
---
---
1 500
1,000
1,000
2,000
1,500
1,500
1,000
1,000
1,000
---
---
---
---
---
---
---
---
---
---
---
---
0.6 / 0.85 ±0.10
1.15 ±0.10
1.15 ±0.15
1.35 ±0.15
1.5 ±0.1
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
1.6 ±0.2
---
---
---
---
---
0508
0612
0.6 ±0.10
4,000
4,000
4,000
---
---
---
---
---
0.85 ±0.10
0.8 ±0.10
---
---
---
---
---
Arrays
---
---
---
---
---
1.2 ±0.10
3,000
---
---
---
---
NOTE
1. For bulk case, tape and reel specification/dimensions, please see the special data sheet “Packing” document.
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Apr 19, 2006 V.2
Product specification
9
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
ELECTRICAL CHARACTERISTICS
NP0/X5R/X7R/Y5V DIELECTRIC CAPACITORS; NISN TERMINATIONS
Unless otherwise stated all electrical values apply at an ambient temperature of 20±1 °C, an atmospheric
pressure of 86 to 106 kPa, and a relative humidity of 63 to 67%.
Table 5
VALUE
DESCRIPTION
Capacitance range (1)
:
NP0
X5R/Y5V
X7R
1 pF to 100 pF
100 nF
47 pF to 10 nF
RATED VOLTAGE Ur (DC):
NP0
X5R/Y5V
X7R
25/50 V
6.3 V
10/16/25/50 V
Capacitance tolerance (1)
:
C <10 pF: ±0.25 pF, ±0.50 pF; C ≥10 pF: ±5%
NP0
X5R
X7R
Y5V
±10%
±10%
–20% ~ +80%
Dissipation factor (D.F.) (1) (max.):
30+7C
100×C
C ≤10 pF: D.F.=
or 0.3%; whichever is smallest; C >10 pF: 0.1%
NP0
X5R
X7R
Y5V
10%
10 V: 5%; 16 V: 3.5%; 25/50 V: 2.5%
15%
Insulation resistance after 1 minute at Ur (DC)
Rins ≥ 10 GΩ or Rins × C ≥ 500 seconds whichever is less
Maximum capacitance change as a function of
temperature (temperature
characteristic/coefficient):
±30 ppm/°C
±15%
NP0
X5R/X7R
Y5V
+22% ~ –82%
Operating temperature range:
NP0/X7R
X5R
Y5V
–55 °C to +125 °C
–55 °C to +85 °C
–30 °C to +85 °C
NOTE
1. f=1 KHz for C ≤ 10 µF; measuring at voltage 1 V ; f=120 Hz for C > 10 µF; measuring at voltage 0.5 V
.
rms
rms
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Apr 19, 2006 V.2
Product specification
10
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
TESTS AND REQUIREMENTS
Table 6 Test condition, procedure and requirements
TEST
TEST METHOD
PROCEDURE
REQUIREMENTS
Mounting IEC 60384- 4.3
21/22
The capacitors may be mounted on printed-circuit boards or
ceramic substrates
No visible damage
Visual
4.4
Any applicable method using × 10 magnification
In accordance with
specification
inspection and
dimension
check
Capacitance
4.5.1
NP0:
Within specified tolerance
f = 1 MHz for C ≤ 1 nF, measuring at voltage 1 Vrms at 20 °C;
f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C
X5R/X7R/Y5V:
f = 1 KHz for C ≤ 10 µF, measuring at voltage 1 Vrms at 20 °C
Dissipation
factor (D.F.)
4.5.2
NP0:
In accordance with
specification
f = 1 MHz for C ≤ 1 nF, measuring at voltage 1 Vrms at 20 °C;
f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C
X5R/X7R/Y5V:
f = 1 KHz for C ≤ 10 µF, measuring at voltage 1 Vrms at 20 °C
Insulation
resistance
4.5.3
At Ur (DC) for 1 minute
In accordance with
specification
Voltage proof
4.5.4.2
Test voltage (DC) applied for 1 minute
No breakdown or
flashover
Ur ≤ 100 V: 2.5 × Ur applied to NP0/X5R/X7R/Y5V series
100 V < Ur ≤ 200 V: 1.5 × Ur +100 V applied to NP0/X7R series
200 V < Ur ≤ 500 V: 1.3 × Ur +100 V applied to NP0/X7R series
Ur > 500 V: 1.3 × Ur applied to NP0/X7R series
I: 7.5 mA
Temperature
characteristic
4.6
Between minimum and maximum temperature
NP0: ΔC/C: ±30 ppm/°C
X5R/X7R: ΔC/C: ±15%
Y5V: ΔC/C: +22%~
–82%
Adhesion
4.15
A force applied for 10 seconds to the line joining the terminations
and in a plane parallel to the substrate
No visible damage
for size ≥ 0603: a force of 5 N applied
for size 0402: a force of 2.5 N applied
for size 0201: a force of 1 N applied
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Apr 19, 2006 V.2
Product specification
11
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
Table 6 Test condition, procedure and requirements (continued)
TEST
TEST METHOD
PROCEDURE
REQUIREMENTS
Bond strength IEC 60384- 4.8
Mounting in accordance with IEC 60384-22 paragraph
4.3
No visible damage
21/22
of plating on
end face
Conditions: bending 1 mm at a rate of 1 mm/s, radius jig NP0: lΔC/Cl: ≤ 1% or 0.5 pF
340 mm
whichever is greater
X5R/X7R/Y5V: lΔC/Cl: ≤ 10%
Resistance to
soldering heat
4.9
Precondition: 150 +0/–10 °C for 1 hour, then keep for
24 ±1 hours at room temperature
The termination shall be well tinned
NP0: lΔC/Cl: ≤ 0.5% or 0.5 pF
Preheating: for size ≤ 1206: 120 to 150 °C for 1 minute
whichever is greater
Preheating: for size >1206: 100 to 120 °C for 1 minute
and 170 to 200 °C for 1 minute
X5R/X7R: lΔC/Cl: ≤ 10%
Y5V: lΔC/Cl: ≤ 20%
Solder bath temperature: 260 ±5 °C
Dipping time: 10 ±0.5 seconds
Recovery time: 24 ±2 hours.
D.F.: within initial specified value
Rins: within initial specified value
Solderability
4.10
4.11
Unmounted chips completely immersed in a solder bath
at 235 ±5 °C
The termination shall be well
tinned.
Dipping time: 2 ±0.5 seconds
Depth of immersion: 10 mm
Rapid change
of
temperature
Preconditioning;
150 +0/–10 °C for 1 hour, then keep for 24 ±1 hours at
room temperature
No visual damage
NP0: lΔC/Cl: ≤ 1% or 1 pF
whichever is greater
X5R/X7R: lΔC/Cl: ≤ 15%
Y5V: lΔC/Cl: ≤ 20%
5 cycles with following detail:
30 minutes at lower category temperature;
30 minutes at upper category temperature
D.F.: within initial specified value
Rins: within initial specified value
Recovery time 24 ±2 hours.
Damp heat,
with Ur load
4.13
Initial measurements; after 150 +0/-10 °C for 1 hour,
then keep for 24 ±1 hours at room temperature
NP0: lΔC/Cl: ≤ 2% or 1 pF
whichever is greater
Duration and conditions: 500 ±12 hours at 40 ±2 °C;
90 to 95% RH; Ur applied
X5R/X7R: lΔC/Cl: ≤ 20%
Y5V: lΔC/Cl: ≤ 30%
Final measurement: perform a heat treatment at
150 +0/–10 °C for 1 hour, final measurements shall be
carried out 24 ±1 hours after recovery at room
temperature without load.
NP0/X5R/X7R/Y5V: D.F.: 2 × initial
value max.
NP0: Rins ≥ 2,500 MΩ or Rins × Cr
≥ 25 seconds, whichever is less
X5R/X7R/Y5V: Rins ≥ 500 MΩ or
R
ins × Cr ≥ 25 seconds, whichever
is less
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Apr 19, 2006 V.2
Product specification
12
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
Table 6 Test condition, procedure and requirements (continued)
TEST
TEST METHOD
PROCEDURE
REQUIREMENTS
Endurance IEC 60384- 4.14
21/22
Preconditioning;
Initial measurements; after 150 +0/-10 °C for 1 hour,
then keep for 24 ±1 hours at room temperature
NP0: lΔC/Cl: ≤ 2% or 1 pF whichever
is greater
X5R/X7R: lΔC/Cl: ≤ 20%
Y5V: lΔC/Cl: ≤ 30%
Duration and conditions: 1,000 ±12 hours at upper
category temperature with 1.5 × Ur voltage applied
NP0/X5R/X7R/Y5V: D.F.: 2 × initial
value max.
Final measurement: perform a heat treatment at 150
+0/–10 °C for 1 hour, final measurements shall be
carried out 24 ±1 hours after recovery at room
temperature without load.
NP0: Rins ≥ 4,000 MΩ or Rins × Cr ≥
40 seconds, whichever is less
X5R/X7R/Y5V: Rins ≥ 1,000 MΩ or
R
ins × Cr ≥ 50 seconds, whichever is
less
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Apr 19, 2006 V.2
Product specification
13
13
NP0/X5R/X7R/Y5V 6.3 V to 50 V
Ultra small
Surface-Mount Ceramic Multilayer Capacitors
REVISION HISTORY
REVISION DATE
CHANGE NOTIFICATION DESCRIPTION
Version 2
Apr 19, 2006
-
- New datasheet for ultra small NP0/X5R/X7R/Y5V series chip capacitors
with lead-free terminations
- Test method and procedure updated
Version 1
Version 0
Mar 22, 2004
Mar 18, 2004
-
-
-
-
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Apr 19, 2006 V.2
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