225514611539 [YAGEO]
Array/Network Capacitor, 50V, C0G, 0.00018uF, Surface Mount, CHIP-8, CHIP;型号: | 225514611539 |
厂家: | YAGEO CORPORATION |
描述: | Array/Network Capacitor, 50V, C0G, 0.00018uF, Surface Mount, CHIP-8, CHIP |
文件: | 总11页 (文件大小:119K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SURFACE-MOUNT CERAMIC
MULTILAYER CAPACITORS
C-Array: Class 1, NP0
50 V
size 0612 (4 × 0603)
Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
FEATURES
QUICK REFERENCE DATA
DESCRIPTION
VALUE
• 4 × 0603 capacitors (of the same
capacitance value) per array
Rated voltage UR (DC)
50 V (IEC)
• Less than 50% board space of an
Capacitance range (E12 series) 10 pF to 1 nF
equivalent discrete component
Tolerance on capacitance
Test voltage (DC) for 1 minute
Sectional specifications
±5%, ±10%
2.5 × UR
• High volumetric efficiency
• Dense dielectric layers
• Supplied in tape on reel
IEC 60384-10, second edition 1989-04;
also based on CECC 32 100
• Increased throughput by time
Detailed specification
based on CECC 32 101-801
55/125/56
saved in mounting
Climatic category (IEC 60068)
• Cost savings on manufacturing
time.
APPLICATIONS
• Professional electronics
• High density consumer
electronics
• Automotive.
DESCRIPTION
HBK091
Each capacitor element consists of a
rectangular block of ceramic
dielectric in which a number of
interleaved precious metal
Fig.1 Simplified outline.
electrodes are contained. This
structure gives rise to a high
capacitance per unit volume.
The inner electrodes are connected
to the two terminations, silver dipped
with a barrier layer of plated nickel
and finally covered with a layer of
plated tin (NiSn). An outline of the
structure is shown in Fig.1.
2003 Jul 18 Rev.7
2
www.yageo.com
Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
MECHANICAL DATA
L
W
B
P
A
T
HBK092
For dimensions see Table 1.
Fig.2. Dimensional outline.
Physical dimensions
Table 1 Capacitor dimensions; see Fig.2
CASE SIZE
L
W
T
A
B
P
Dimensions in millimetres
0612
3.2 ±0.15
(4 × 0603)
1.60 ±0.15
0.80 ±0.10
0.40 ±0.10
0.30 ±0.20
0.80 ±0.10
Dimensions in inches
0612
0.126 ±0.006
(4 × 0603)
0.063 ±0.006
0.032 ±0.004
0.016 ±0.004
0.012 ±0.008
0.031 ±0.004
2003 Jul 18 Rev.7
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
DIMENSIONS OF SOLDER LANDS
E
D
B
handbook, 4 columns
A
C
CCC314
solder land
For dimensions see Table 2.
Fig.3 Recommended dimensions of solder lands.
Table 2 Solder land dimensions; see Fig.3
FOOTPRINT DIMENSIONS
(mm)
CASE SIZE
A
B
C
D
E
0612
2.54 ±0.15
(4 × 0603)
0.89 ±0.10
0.76 ±0.10
0.80 ±0.10
0.45 ±0.10
2003 Jul 18 Rev.7
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
SELECTION CHART FOR 50 V
LAST TWO
50 V
C
DIGITS OF
(pF)
0612 (4 × 0603)
12NC
10
12
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
41
42
43
44
45
46
47
48
49
15
18
22
27
33
39
47
56
68
82
100
120
150
180
220
270
330
390
470
560
680
820
1 000
0.8 ±0.1
Note
1. Values in shaded cells indicate thickness class.
Thickness classification and packing quantities
8 mm TAPE WIDTH QUANTITY PER REEL
THICKNESS
CLASSIFICATION
(mm)
∅180 mm; 7"
PAPER
0.8 ±0.1
4 000
2003 Jul 18 Rev.7
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www.yageo.com
Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
ORDERING INFORMATION
Components may be ordered by using either a Phycomp’s unique 12NC or simple 15-digit clear text code.
Ordering code 12NC (preferred)
2 2 X X X X X X 1 X X X
(1)
Carrier type
55
Capacitance value
see selection chart
paper
Voltage
Tolerance
14 50 V
5
6
±5%
±10%
Size
6
Packaging
1 reel: 180 mm; 7"
0612 (4 x 0603)
scm005
(1) Quantity on reel depends on thickness classification, see section “Thickness classification and packing quantities”.
Clear text code
Example: 0612CG102J9B200
Size
Code
Temp.
Char.
Capacitance
Tol.
Vol. Termination
Packing
Marking
Series
0612
(4 × 0603)
CG = NP0 102 = 1000 pF;
the third digit
J = ±5%
9 = 50 V B = NiSn
2 = 180 mm; 7" paper 0 = no marking 0 = conv.
ceramic
K = ±10%
signifies the
multiplying factor:
0 = × 1
1 = × 10
2 = × 100
2003 Jul 18 Rev.7
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
ELECTRICAL CHARACTERISTICS
Class 1 capacitors; NP0 dielectric; NiSn terminations
Unless otherwise stated all electrical values apply at an ambient temperature of 20 ±1 °C, an atmospheric pressure of
86 to 106 kPa, and a relative humidity of 63 to 67%.
DESCRIPTION
VALUE
Capacitance range (E12 series); note 1
Tolerance on capacitance after 1000 hours
Test voltage (DC) for 1 minute
10 pF to 1 nF
±5%; 10%
2.5 × UR
Tan δ; note 1
≤ 0.1%
Insulation resistance after 1 minute at UR (DC):
R
ins ≥100 GΩ
Temperature coefficient
(0 30) 10−6/K
±
×
Note
1. Measured at 1 V, 1 MHz for C ≤ 1000 pF and at 1 V, 1 kHz for C > 1000 pF, using a four-gauge method.
2003 Jul 18 Rev.7
7
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
MEA608
MEA607
10
tan δ
40
4
–
(x 10
)
TC
6
(x10 /K)
7.5
20
0
5
20
40
2.5
0
– 40
0
40
80
120
40
0
40
80
120
T ( C)
o
o
T ( C)
Fig.5 Typical tan δ as a function of temperature.
Fig.4 Typical temperature coefficient as a
function of temperature.
MEA614
15
10
∆C
C
(%)
5
0
Ð 5
Ð 10
Ð 15
0
10
20
30
40
50
(V)
V
DC
Fig.6 Typical capacitance change with respect to
the capacitance at 1 V as a function of DC
voltage.
2003 Jul 18 Rev.7
8
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
TESTS AND REQUIREMENTS
Table 3 Test procedures and requirements
IEC
IEC
60384-10/
CECC 32 100
CLAUSE
60068-2
TEST
METHOD
TEST
PROCEDURE
REQUIREMENTS
4.4
mounting
the capacitors may be
no visible damage
mounted on printed-circuit
boards or ceramic substrates
by applying wave soldering,
reflow soldering (including
vapour phase soldering) or
conductive adhesive
4.5
visual inspection and
dimension check
any applicable method using in accordance with
×10 magnification specification
4.6.1
capacitance (measured
1000 hours after date of
manufacture)
f = 1 kHz; measuring voltage within specified tolerance
1 Vrms at 20 °C
4.6.2
4.6.3
tan δ
f = 1 kHz; measuring voltage in accordance with
1 Vrms at 20 °C
specification
at UR (DC) for 1 minute
insulation resistance
in accordance with
specification
2.5 × UR for 1 minute
4.6.4
4.7.1
voltage proof
no breakdown or flashover
temperature coefficient
between minimum and
maximum temperature
in accordance with
specification
4.8
adhesion
a force of 5 N applied for
10 s to the line joining the
terminations and in a plane
parallel to the substrate
no visible damage
4.9
bond strength of plating
on end face
mounted in accordance with
IEC 60384 10, paragraph 4.4
no visible damage
∆C/C: ≤10%
conditions: bending 1 mm at
a rate of 1 mm/s, radius jig
340 mm
4.10
Tb
resistance to soldering
heat; jig clamps to the
second component in
the longitudinal line
260 ±5 °C for 10 ±0.5 s
in a static solder bath
the terminations shall be
well tinned after recovery
∆C/C: ±10%
resistance to leaching;
jig clamps to the second in a static solder bath
component in the
260 ±5 °C for 30 ±1 s
using visual enlargement
of ×10, dissolution of the
terminations shall not
exceed 10%
longitudinal line
2003 Jul 18 Rev.7
9
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
IEC
IEC
TEST
PROCEDURE
REQUIREMENTS
60384-10/
CECC 32 100
CLAUSE
60068-2
TEST
METHOD
4.11
Ta
solderability; jig zero hour test, and test after
the terminations shall be
well tinned
clamps to the
second
component
along the
storage (20 to 24 months) in
original packing in normal
atmosphere;
unmounted chips completely
longitudinal line immersed for 2 ±0.5 s in a solder
bath at 235 ±5 °C
4.12
4.14
Na
Ca
rapid change of Preconditioning:
no visible damage after
temperature
between minimum and maximum 24 hours recovery;
temperature, 5 cycles
∆°C/C: ≤15%
damp heat
Preconditioning:
after 48 hours recovery:
56 days at 40 °C; 90 to 95% RH;
UR applied
∆°C/C: ±15%
tan δ: 7%
Rins: 1000 MΩ or RiCR ≥ 25 s,
whichever is less
4.15
endurance
Preconditioning:
(thermal treatment)
2 × UR at 125 °C for 1000 hours,
after 48 hours recovery:
∆°C/C: ±20%
tan δ: 7%
recovery 48 ±4 hours at room
temperature
R
ins: 2000 MΩ or RiCR ≥ 25 s,
whichever is less
2003 Jul 18 Rev.7
10
www.yageo.com
Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
C Array: Class 1, NP0 50 V
size 0612 (4 × 0603)
REVISION HISTORY
Revision
Date
Change
Description
Notification
Rev.5
Rev.6
Rev.7
2001 May 30
2003 Mar 04
2003 Jul 18
-
-
-
- Converted to Phycomp brand
- Updated company logo
- Cover page revised
2003 Jul 18 Rev.7
11
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