22552311632 [YAGEO]
Feed Through Capacitor, 1 Function(s), 50V, EIA STD PACKAGE SIZE 1206;
| 型号： | 22552311632 |
| 厂家： | 
YAGEO CORPORATION |
| 描述： | Feed Through Capacitor, 1 Function(s), 50V, EIA STD PACKAGE SIZE 1206 |
| 文件： | 总11页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE CERAMICS
DATA SHEET
Class 1, NP0 50 V
feedthrough
Surface-mount ceramic
multilayer capacitors
Product specification
2001 May 30 Rev.3
Supersedes data of 25th August 1999
Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
FEATURES
QUICK REFERENCE DATA
DESCRIPTION
• High capacitance per unit volume
• Supplied in tape on reel or in bulk
• For high frequency applications
• NiSn terminations.
VALUE
Rated voltage UR (DC)
50 V (IEC)
Capacitance range (E12 series)
Tolerance on capacitance
Test voltage (DC) for 1 minute
Sectional specifications
47 pF to 1 nF
10%; 5%
2.5 × UR
APPLICATIONS
IEC 60384-10, second edition 1989-04;
also based on CECC 32 100
• Consumer electronics
• Telecommunications
• Automotive
Detailed specification
based on CECC 32 101-801
55/125/56
Climatic category (IEC 60068)
• Data processing.
DESCRIPTION
electrodes
handbook, halfpage
The capacitor consists of a
rectangular block of ceramic dielectric
in which a number of interleaved
precious metal electrodes are
contained. This structure gives rise to
a high capacitance per unit volume.
CCC033
The inner electrodes areconnected to
the four terminations, silver dipped
with a barrier layer of plated nickel
and finally covered with a layer of
plated tin (NiSn). A 3D diagram of the
structure is shown in Fig.1.
terminations
Fig.1 Construction of a Feedthrough capacitor.
2001 May 30 Rev.3
2
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
MECHANICAL DATA
a
d
c
f
L
B
A
d
b
e
W
CCB960
C
T
P
a. Outline.
b. Dimensions of solder lands.
For dimensions see Tables 1 and 2.
Fig.2 Physical dimensions.
Physical dimensions
Table 1 Capacitor dimensions in millimetres
CASE SIZE
L
W
T
A
B
C
P
1206
3.2 0.20
1.6 0.20
0.80 0.10
0.50 0.20
0.30 0.15
0.90 0.20
1.60 0.15
Table 2 Dimensions of solder lands in millimetres
a
b
c
d
e
f
4.45 0.20
1.65 0.20
1.00 0.15
0.90 0.20
1.00 0.15
0.70 0.10
2001 May 30 Rev.3
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
SELECTION CHART
50 V
1206
C
(pF)
LAST TWO DIGITS
OF 12NC
47
100
32
36
41
43
45
49
220
0.8 0.1
330
470
1000
Thickness classification and packing quantities
8 mm TAPE WIDTH
QUANTITY PER REEL
THICKNESS
CLASSIFICATION
(mm)
∅180 mm; 7"
PAPER
0.8 0.1
4000
ORDERING INFORMATION
Components may be ordered by using either a simple 15-digit clear text code or Phycomp’s unique 12NC.
Clear text code
EXAMPLE: 1206CG102J9B20F
SIZE
CODE
TEMP.
CHAR.
CAPACITANCE
TOL.
VOLTAGE TERMINATION
9 = 50 V B = NiSn
PACKING
MARKING
SERIES
1206
CG = NP0 102 = 1000 pF;
the third digit
signifies the
J = 5%
2 = 180 mm; 7" paper
A = bulk
0 = no marking F = feedthrough
K = 10%
multiplying factor:
0 = × 1
1 = × 10
2 = × 100
Ordering code 12NC
2 2 X X X X X X 1 X X X
(1)
Carrier type
Capacitance value
55 paper
Tolerance
5
6
5%
10%
Rated voltage - Termination
23 50 V; Ni-barrier
(2)
Packaging
Size
1
1
0
reel: ∅180 mm; 7"
bulk (loose in bag, 1000 units)
1206 Feedthrough
CCC009
(1) Refer to chapter “Selection chart”.
(2) Quantity on reel depends on thickness classification, see section “Thickness classification and packing quantities”.
2001 May 30 Rev.3
4
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
ELECTRICAL CHARACTERISTICS
Class 1 capacitors; NP0 dielectric; NiSn terminations
Unless otherwise stated all electrical values apply at an ambient temperature of 23 3 °C, an atmospheric pressure of
86 to 106 kPa, and a relative humidity of 63 to 67%.
DESCRIPTION
Capacitance range (E12 series)
VALUE
47 pF to 1 nF
10%; 5%
50 V
Tolerance on capacitance
Rated voltage UR (DC)
Test voltage (DC) for 1 minute
Tan δ; note 1
2.5 × UR
≤10 × 10−4
Rins > 105 MΩ
1 Ω max.
Insulation resistance after 1 minute at UR (DC)
Rated DC resistance
Note
1. Measured at 1 V, 1 MHz for C ≤ 1000 pF and 1 V, 1 kHz for C > 1000 pF, using a four-gauge method.
2001 May 30 Rev.3
5
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
MEA608
MEA614
10
15
handbook, halfpage
∆C
tan δ
(x 10
C
(%)
4
–
)
10
7.5
5
0
5
– 5
2.5
0
– 10
– 15
0
10
20
30
40
50
(V)
– 40
0
40
80
120
V
o
DC
T ( C)
Fig.3 Typicalcapacitance changewith respect
to the capacitance at 1 V as a function of
DC voltage.
Fig.4 Typical tan δ as a function of temperature.
MEA607
handbook, halfpage
40
TC
6
(x10 /K)
20
0
20
40
40
0
40
80
120
o
T ( C)
Fig.5 Typical capacitance change as a
function of temperature.
2001 May 30 Rev.3
6
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
CCB961
20
attenuation
(dB)
0
−20
−40
−60
normal CMC
FTC
−80
2
3
4
10
10
10
10
f (Hz)
Fig.6 Insertion loss characteristics.
2001 May 30 Rev.3
7
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
HIGH FREQUENCY BEHAVIOUR OF MULTILAYER CHIP CAPACITORS
Multilayer chip capacitors (MLCCs) are suitable for use at
high frequencies. At frequencies below the series
resonance frequency, the MLCC can be represented by an
equivalent circuit as shown in Fig.7.
At the SRF, the MLCC will appear as a small resistor.
The transmission loss through the MLCC at this series
resonance frequency will be low.
Using the values of C, L = 1 nH and the ESR at a specific
frequency (f), two often used quantities can be derived.
In general, the quantities C, ESR and L are frequency
dependent. For most applications, C and L can be
regarded as frequency independent below 1 GHz.
The impedance (Z) is given by:
1 – (2πf)2LC
Z =
+ ESR
------------------------------------
The equivalent series self-inductance L is:
2jπfC
• Independent of the dielectric material.
The quality factor (Q) is given by:
• Dependent on the size of the capacitor, it increases with
increasing length and decreases with increasing width
or thickness of the product.
1 – (2πf)2LC
Q =
--------------------------------------
2πfESRC
• The value of L is approximately:
– 0.6 nH for case size 0603
– 1 nH for case sizes 0805, 1206 and 1210
– 1.5 nH for case sizes 1812 and 2220.
C
ESR
L
MEA609
These figures are accurate to within 20%.
Because of the inductance L, associated with the MLCC,
there will be a frequency at which the inductive reactance
will be equal to the reactance of the capacitor.
C = capacitance.
ESR = equivalent series resistance which is determined by the
energy dissipation mechanisms (in the dielectric material as well
as in the electrodes).
This is known as the series resonance frequency (SRF)
and is given by:
L = equivalent series self-inductance.
Fig.7 Equivalent series representation of a MLCC.
1
SRF =
-------------------
2π LC
2001 May 30 Rev.3
8
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
CCB962
4
10
Z
(Ω)
3
10
47 pF 100 pF 220 pF
2
10
10
330 pF 470 pF 1 nF
1
−1
10
−2
10
6
7
8
9
10
10
10
10
10
10
f (Hz)
Fig.8 Impedance of FTC as a function of frequency.
Figures 9 and 10 show the comparative inductance of a conventional MLCC and an FTC, when the capacitor is mounted
on a substrate. The high frequency capability of the FTC is better than a conventional MLCC due to the inductance of an
FTC being less than the MLCC.
L1
L2
handbook, halfpage
L3
L3
C1
L3
handbook, halfpage
L1 C1
L2
L3
CCB964
CCB963
Fig.9 Inductance of LMCC.
Fig.10 Inductance of FTC.
The equivalent circuits show parasitic inductances L1, L2 and L3. The resonance frequency (fr) can be determined as
1
follows: fr =
(Lg = inductance between signal through line and GEN).
-------------------------------
2π Lg × C1
L3
2
The inductance of the FTC (LgFTC = L3//L3 =
) is one quarter that of the MLCC (LgCMC = L3 + L3 = L3 × 2).
------
2001 May 30 Rev.3
9
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
TESTS AND REQUIREMENTS
Table 3 Test procedures and requirements
IEC
IEC
60384-10/
CECC 32 100
CLAUSE
60068-2
TEST
METHOD
TEST
PROCEDURE
REQUIREMENTS
4.4
mounting
the capacitors may be mounted
on printed-circuit boards or
no visible damage
ceramic substrates by applying
wave soldering, reflow soldering
(including vapour phase
soldering) or conductive adhesive
4.5
visualinspectionand any applicable method using
in accordance with specification
dimension check
×10 magnification
4.6.1
capacitance
f = 1 MHz; measuring voltage
1 Vrms at 20 °C
within specified tolerance
measured 1000 hours after
date of manufacture
4.6.2
tan δ
f = 1 MHz; measuring voltage
in accordance with specification
1 Vrms at 20 °C
4.6.3
4.6.4
4.7.1
insulation resistance at UR (DC) for 1 minute
in accordance with specification
no breakdown or flashover
voltage proof
2.5 × UR for 1 minute
temperature
coefficient
between minimum and
maximum temperature
in accordance with specification
4.8
adhesion
a force of 5 N applied for 10 s to no visible damage
the line joining the terminations
and in a plane parallel to the
substrate
4.9
bond strength of
plating on end face
mounted in accordance with
CECC 32 100, paragraph 4.4
no visible damage
conditions: bending
1 mm at a rate of 1 mm/s,
radius jig 340 mm
∆C/C: ≤10%
4.10
Tb
resistance to
260 5 °C for 10 0.5 s
in a static solder bath
the terminations shall be well
tinned after recovery
soldering heat; jig
clamps to the
second component
along the
∆C/C: 0.5% or 0.5 pF
whichever is greater
longitudinal line
resistance to
leaching; jig clamps in a static solder bath
to the second
260 5 °C for 30 1 s
using visual enlargement of
×10, dissolution of the
terminations shall not
exceed 10%
component along
the longitudinal line
2001 May 30 Rev.3
10
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Phycomp
Product specification
Surface-mount ceramic
multilayer capacitors
Class 1, NP0 50 V
feedthrough
IEC
IEC
60384-10/
CECC 32 100
CLAUSE
60068-2
TEST
METHOD
TEST
PROCEDURE
REQUIREMENTS
4.11
Ta
solderability; jig
clamps to the
second component
along the
zero hour test, and test after
storage (20 to 24 months) in
original packing in normal
atmosphere;
the terminations shall be well
tinned ≥95%
longitudinal line
unmounted chips completely
immersed for 2 0.5 s in a solder
bath at 235 5 °C
4.12
4.14
Na
Ca
rapid change of
temperature
preconditioning, class 2 only;
5 cycles in the following
sequence:
30 minutes at −55 °C, change
within 30 minutes to +125 °C
no visible damage
after 24 hours recovery:
∆C/C: 1% or 1 pF
damp heat
preconditioning, class 2 only:
56 days at 40 °C;
90 to 95% RH; UR applied;
30 minutes at −55 °C, change
within 30 minutes to +125 °C
no visual damage
after 1 to 2 hours recovery:
∆C/C: 2% or 1 pF,
whichever is greater
tan δ: ≤2 × specified value
Rins: ≥2500 MΩ or RiCR ≥ 25 s,
whichever is less
4.15
endurance
preconditioning, class 2 only
(thermal treatment):
1000 hours at 125 °C and
2 × UR applied
no visual damage
after 1 to 2 hours recovery:
∆C/C: 2% or 1 pF,
whichever is greater
tan δ: ≤2 × specified value
Rins: ≥4000 MΩ or RiCR ≥ 40 s,
whichever is less
2001 May 30 Rev.3
11
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