CC0100BRX5R4BB121 [YAGEO]
SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS;
| 型号： | CC0100BRX5R4BB121 |
| 厂家： | 
YAGEO CORPORATION |
| 描述： | SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS |
| 文件： | 总11页 (文件大小：914K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SURFACE-MOUNT CERAMIC
MULTILAYER CAPACITORS
01005
NP0/X5R/X7R
4 V TO 16 V
0.5 pF to 220 nF
RoHS compliant & Halogen Free
Product specification
2
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
SCOPE
ORDERING INFORMATION -GLOBAL PART NUMBER, PHYCOMP
CTC & 12NC
All part numbers are identified by the series, size, tolerance, TC material,
packing style, voltage, process code, termination and capacitance value.
This specification describes
01005 NP0/X5R series chip
capacitors with lead-free
terminations.
YAGEO BRAND ordering code
(
)
GLOBAL PART NUMBER PREFERRED
APPLICATIONS
Mobile
CC XXXX
X X XXX X B X XXX
(1) (2) (3) (4) (5)
(6) (7)
Module
( )
1 SIZE – INCH BASED (METRIC)
FEATURES
0100(0402)
Supplied in tape on reel
Nickel-barrier end termination
RoHS compliant
( )
2 TOLERANCE
B = ±0.1pF
C = ±0.25pF
D = ±0.5pF
J = ±5%
Halogen Free compliant
K = ±10%
M = ±20%
( )
3 PACKING STYLE
R = Paper/PE taping reel; Reel 7 inch
( )
4 TC MATERIAL
NPO
X5R
X7R
( )
5 RATED VOLTAGE
4 = 4 V
5 = 6.3V
6 = 10 V
7 = 16 V
(6) PROCESS
N = NP0
B = Class 2 MLCC
( )
7 CAPACITANCE VALUE
2 significant digits+number of zeros
The 3rd digit signifies the multiplying factor, and letter R is decimal point
Example: 121 = 12 x 101 = 120 pF
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Jan. 18, 2017 V.9
Product specification
3
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
CONSTRUCTION
The capacitor consists of a
rectangular block of ceramic
dielectric in which a number of
interleaved metal electrodes are
contained. This structure gives
rise to a high capacitance per
unit volume.
The inner electrodes are
connected to the two end
terminations and finally covered
with a layer of plated tin (NiSn).
The terminations are lead-free. A
cross section of the structure is
shown in Fig.1.
Fig. 1 Surface mounted multilayer ceramic capacitor construction
DIMENSION
Table 1 For outlines see fig. 2
OUTLINES
L2 / L3 (mm) L4 (mm)
For dimension see Table 1
TYPE L1 (mm)
W (mm)
T (mm)
min.
max.
min.
01005 0.4 ±0.02
0.2 ±0.02
0.2 ±0.02
0.07
0.14
0.13
Fig. 2 Surface mounted multilayer
ceramic capacitor dimension
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Jan. 18, 2017 V.9
Product specification
4
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS
Table 2 01005 Sizes
NP0
X5R
4V
X7R
CAP.
CAP.
CAP.
10V / 16 V
6.3V
10V
6.3V / 10V
16V
0.5 pF
0.6 pF
0.7 pF
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
100 pF
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
100 pF
150 pF
220 pF
330 pF
470 pF
680 pF
1 000 pF
2.2 nF
4.7 nF
10 nF
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
150 pF
220 pF
330 pF
470 pF
680 pF
1 000 pF
2.2 nF
4.7 nF
10 nF
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.2±0.02
0.75 pF
0.8 pF
0.9 pF
1.0 pF
1.2 pF
1.5 pF
1.8 pF
2.2 pF
2.7 pF
3.3 pF
3.9 pF
4.7 pF
5.6 pF
6.8 pF
8.2 pF
10 pF
12 pF
15 pF
18 pF
22 pF
27 pF
33 pF
39 pF
47 pF
56 pF
68 pF
82 pF
100 pF
22nF
22nF
47 nF
47 nF
100 nF
220 nF
100 nF
220 nF
Tape width
8 mm
Tape width
8 mm
Tape width
8 mm
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Jan. 18, 2017 V.9
Product specification
5
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
THICKNESS CLASSES AND PACKING QUANTITY
Table 3
Ø 180 MM / 7 INCH
Ø 330 MM / 13 INCH
SIZE
CODE
THICKNESS
CLASSIFICATION QUANTITY PER REEL
TAPE WIDTH
QUANTITY
PER BULK CASE
Paper/PE
Blister
---
Paper/
Blister
01005
0.2 ±0.02 mm
8 mm
20,000
---
---
---
ELECTRICAL CHARACTERISTICS
NP0/X5R DIELECTRIC CAPACITORS; NISN TERMINATIONS
Unless otherwise specified, all test and measurements shall be made under standard atmospheric conditions
for testing as given in 5.3 of IEC 60068-1:
- Temperature: 15 °C to 35 °C
- Relative humidity: 25% to 75%
- Air pressure: 86 kPa to 106 kPa
Before the measurements are made, the capacitor shall be stored at the measuring temperature for a time
sufficient to allow the entire capacitor to reach this temperature.
The period as prescribed for recovery at the end of a test is normally sufficient for this purpose.
Table 4
VALUE
DESCRIPTION
Capacitance range
Capacitance tolerance
0.5 pF to 220 nF
C< 10 pF
C ≥ 10 pF
±0.1pF, ±0.25pF, ±0.5pF
±5%, ±10%
NP0
X5R / X7R
±10%, ±20%
Dissipation factor (D.F.)
NP0
C < 30 pF
C ≥ 30 pF
≤ 1 / ( 400 + 20C )
≤ 0.1 %
≤ 10 %
X5R / X7R
Rins ≥ 10 GΩ or Rins × C ≥ 500Ω · F whichever is less
Insulation resistance after 1 minute at Ur (DC)
X5R/X7R > 10nF:
Rins x C ≥ 50Ω· F
Maximum capacitance change as a function of temperature
(temperature characteristic/coefficient):
NP0
±30 ppm/°C
±15%
X5R / X7R
Operating temperature range:
NP0
X5R
X7R
–55 °C to +125 °C
–55 °C to +85 °C
–55 °C to +125 °C
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Jan. 18, 2017 V.9
Product specification
6
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
SOLDERING RECOMMENDATION
Table 5
SOLDERING
METHOD
SIZE
01005
Reflow
Reflow only
---
Reflow/Wave
TESTS AND REQUIREMENTS
Table 6 Test procedures and requirements
TEST
TEST METHOD PROCEDURE
REQUIREMENTS
No visible damage
IEC 60384- 4.3
21/22
The capacitors may be mounted on printed-circuit boards or
ceramic substrates
Mounting
4.4
Any applicable method using × 10 magnification
In accordance with specification
Within specified tolerance
Visual
Inspection and
Dimension
Check
Class 1:
4.5.1
Capacitance
f = 1 MHz for C ≤ 1 nF, measuring at voltage 1 Vrms at 20 °C
f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C
Class 2:
C ≤ 1 nF
f = 1 KHz, measuring at voltage 1 Vrms at 20 °C
C > 1 nF
f = 1 KHz, rated voltage ≤ 6.3 V, measuring at voltage 0.5 Vrms at
20 °C
f = 1 KHz, rated voltage > 10 V, measuring at voltage 1 Vrms at 20 °C
Class 1:
4.5.2
In accordance with specification
Dissipation
f = 1 MHz for C ≤ 1 nF , measuring at voltage 1 Vrms at 20 °C
f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C
Factor (D.F.)
Class 2:
C ≤ 1 nF
f = 1 KHz, measuring at voltage 1 Vrms at 20 °C
C > 1 nF
f = 1 KHz, rated voltage ≤ 6.3 V,
measuring at voltage 0.5 Vrms at 20 °C
f = 1 KHz, rated voltage > 10 V,
measuring at voltage 1 Vrms at 20 °C
4.5.3
At Ur (DC) for 1 minute
In accordance with specification
Insulation
Resistance
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Jan. 18, 2017 V.9
Product specification
7
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD PROCEDURE
REQUIREMENTS
4.6
Capacitance shall be measured by the steps shown ∆C/C
Temperature
coefficient
in the following table.
Class1 (NP0):
±30ppm
The capacitance change should be measured after
5 min at each specified temperature stage.
Class 2: (X7R/X5R):
±15%
Step
Temperature(℃)
25±2
a
b
c
In case of applying voltage, the capacitance
change should be measured after 1 more min.
with applying
Lower temperature±3℃
25±2
voltage in equilibration of each temp. stage.
d
Upper Temperature± 2℃
25±2
e
CC0100MRX5R4(5)BB104(224):
0.2V±0.1Vrms
(1) Class I
Temperature Coefficient shall be calculated from
the formula as below
C2 - C1
Temp, Coefficient =
106 [ppm/℃]
C1xΔT
C1: Capacitance at step c
C2: Capacitance at 125℃
∆T: 100℃(=125℃-25℃)
Measuring Voltage: 0.5 to 5 Vrms
(2) Class II
Capacitance Change shall be calculated from the
formula as below
C2 - C1
∆C =
x 100%
C1
C1: Capacitance at step c
C2: Capacitance at step b or d
IEC 60384- 4.7
21/22
A force applied for 10 seconds to the line joining
the terminations and in a plane parallel to the
substrate
Force
size 01005 : 1N
Adhesion
4.8
Mounting in accordance with IEC 60384-22
paragraph 4.3
No visible damage
Bending
Strength
Conditions: bending 1 mm at a rate of 1 mm/s,
radius jig 5 mm
∆C/C
Class 1 (NP0):
within ±1% or 0.5 pF, whichever is greater
Class2 (X5R/X7R):
±10%
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Jan. 18, 2017 V.9
Product specification
8
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD PROCEDURE
REQUIREMENTS
4.9
Precondition: 150 +0/–10 °C for 1 hour,
then keep for 24 ±1 hours at room
temperature
Dissolution of the end face plating shall not exceed
25% of the length of the edge concerned
Resistance to
Soldering
Heat
∆C/C
Preheating: 120 °C to 150 °C for 1 minute
and 170 °C to 200 °C for 1 minute.
Class 1 (NP0):
within ±0.5% or 0.5 pF, whichever is greater
Solder bath temperature: 260 ±5 °C
Dipping time: 10 ±0.5 seconds
Recovery time: 24 ±2 hours
Class2 (X5R/X7R):
±10%
D.F. within initial specified value
Rins within initial specified value
4.10
Preheated the temperature of 80 °C to 140 The solder should cover over 95% of the critical area
Solderability
°C and maintained for 30 seconds to 60
seconds.
of each termination
Test conditions for leadfree containing
solder alloy
Temperature: 245 ±5 °C
Dipping time: 3 ±0.3 seconds
Depth of immersion: 10 mm
IEC 60384- 4.11
21/22
Preconditioning;
150 +0/–10 °C for 1 hour, then keep for
24 ±1 hours at room temperature
No visual damage
Rapid Change
of
Temperature
∆C/C
Class 1 (NP0):
5 cycles with following detail:
30 minutes at lower category temperature
30 minutes at upper category temperature
within ±2.5% or 0.25 pF, whichever is greater
Class2 (X5R/X7R):
±15%
Recovery time 24 ±2 hours
D.F. meet initial specified value
Rins meet initial specified value
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Jan. 18, 2017 V.9
Product specification
9
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD
PROCEDURE
REQUIREMENTS
with
Ur load
4.13
No visual damage after recovery
Damp Heat
1. Preconditioning, class 2 only:
150 +0/-10 °C /1 hour, then keep for
24 ±1 hour at room temp
Class 1 (NP0):
∆C/C
2. Initial measure:
within ±7.5% or 0.75 pF, whichever is greater
D.F.
≤ 2 x specified value
I.R.
≥ 2,500 MΩ or Rins x Cr ≥ 25Ω· F whichever
is less
Spec: refer initial spec C, D, IR
3. Damp heat test:
500 ±12 hours at 40 ±2 °C;
90 to 95% R.H; 1.0 Ur applied.
4. Recovery:
Class 1: 6 to 24 hours
Class 2: 24 ±2 hours
Class2 (X5R/X7R):
C ≤ 1nF
∆C/C
5. Final measure: C, D, IR
P.S. If the capacitance value is less than the
±15%
minimum value permitted, then after the other
measurements have been made the capacitor shall
be precondition according to “IEC 60384 4.1” and
then the requirement shall be met.
D.F.
≤ 10%
I.R.
≥ 500 MΩ
10nF ≥ C > 1nF
∆C/C
±20%
D.F.
≤ 10%
I.R.
≥ 500 MΩ
C > 10nF
∆C/C
±25%
D.F.
≤ 20%
I.R.
Rins x Cr ≥ 5Ω· F
www.yageo.com
Jan. 18, 2017 V.9
Product specification
10
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD
PROCEDURE
REQUIREMENTS
IEC 60384- 4.14
21/22
No visual damage
Endurance
1. Preconditioning, class 2 only:
150 +0/-10 °C /1 hour, then keep for
24 ±1 hour at room temp
Class 1 (NP0):
∆C/C
2. Initial measure:
within ±3% or 0.3 pF, whichever is greater
D.F.
≤ 2 x specified value
I.R.
≥ 4,000 MΩ or Rins x Cr ≥ 40Ω· F whichever
is less
Spec: refer initial spec C, D, IR
3. Endurance test:
Temperature: NP0: 125 °C
Specified stress voltage applied for 1,000 hours:
Applied 2.0 x Ur for general product
Temperature: X5R: 85°C, X7R: 125°C
Specified stress voltage applied for 1,000 hours:
Applied 1.5 x Ur for general product
Class2 (X5R/X7R):
C ≤ 1nF
∆C/C
4. Recovery time: 24 ±2 hours
5. Final measure: C, D, IR
±15%
D.F.
P.S. If the capacitance value is less than the
minimum value permitted, then after the other
measurements have been made the capacitor shall
be precondition according to “IEC 60384 4.1” and
then the requirement shall be met.
≤ 10%
I.R.
≥ 1GΩ
10nF ≥ C >1nF
∆C/C
±15%
D.F.
≤ 10%
I.R.
≥ 1GΩ
C >10nF
∆C/C
±25%
D.F.
≤ 20%
I.R.
Rins x Cr ≥ 10Ω· F
IEC 60384-1 4.5.4
No breakdown or flashover
Voltage Proof
Specified stress voltage applied for 1~5 seconds
Ur ≤ 100 V: series applied 2.5 Ur
Charge/Discharge current is less than 50 mA
www.yageo.com
Jan. 18, 2017 V.9
Product specification
11
11
NP0/X5RX7R
6.3V to 16V
01005
Surface-Mount Ceramic Multilayer Capacitors
REVISION HISTORY
REVISION DATE
CHANGE NOTIFICATION DESCRIPTION
- Test condition updated
Version 9
Version 8
Version 7
Version 6
Version 5
Version 4
Version 3
Version 2
Version 1
Version 0
Jan. 17, 2017
Jan. 12, 2016
Oct. 31, 2015
Jun. 29, 2015
Jun. 06, 2013
Mar. 27, 2013
Jan. 15, 2013
Oct. 23, 2012
July 03, 2012
Apr 16, 2012
- Capacitance range & thickness update
- Capacitance range & thickness update
- Test procedures and requirements
- Test procedures and requirements
- Change Tolerance
- Change Range
- Change Range
- Change Range
-
- New
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Jan. 18, 2017 V.9
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