CL0204KPX7R7BB121 [YAGEO]

SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS;
CL0204KPX7R7BB121
型号: CL0204KPX7R7BB121
厂家: YAGEO CORPORATION    YAGEO CORPORATION
描述:

SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS

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中文:  中文翻译
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DATA SHEET  
SURFACE-MOUNT CERAMIC  
MULTILAYER CAPACITORS  
Low-Inductance  
X5R / X7R  
6.3 V TO 50 V  
10 nF to 1 uF  
RoHS compliant & Halogen Free  
Product specification  
2
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
SCOPE  
ORDERING INFORMATION -GLOBAL PART NUMBER, PHYCOMP  
CTC  
All part numbers are identified by the series, size, tolerance, TC material,  
packing style, voltage, process code, termination and capacitance value.  
This specification describes Mid-  
voltage X7R series chip capacitors  
with lead-free terminations  
APPLICATIONS  
High speed IC packages  
YAGEO BRAND ordering code  
(
)
GLOBAL PART NUMBER PREFERRED  
Processor package decoupling  
AC noise reduction in multi-chip  
modules.  
CL XXXX  
X
X
XXX  
X
BB XXX  
(1) (2) (3) (4) (5)  
(6)  
( )  
1 SIZE INCH BASED (METRIC)  
FEATURES  
0204(0510)  
0306(0816)  
0508(1220)  
0612(1632)  
Supplied in tape on reel  
Nickel-barrier end termination  
RoHS compliant  
Halogen Free compliant  
( )  
2 TOLERANCE  
K = ±10%  
M = ±20%  
( )  
3 PACKING STYLE  
R = Paper/PE taping reel; Reel 7 inch  
K = Blister taping reel; Reel 7 inch  
P = Paper/PE taping reel; Reel 13 inch  
F = Blister taping reel; Reel 13 inch  
( )  
4 TC MATERIAL  
X5R / X7R  
( )  
5 RATED VOLTAGE  
5 = 6.3 V  
6 = 10 V  
7 = 16 V  
8 = 25 V  
9 = 50 V  
( )  
6 CAPACITANCE VALUE  
2 significant digits+number of zeros  
The 3rd digit signifies the multiplying factor, and letter R is decimal point  
Example: 121 = 12 x 101 = 120 pF  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
3
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
CONSTRUCTION  
The capacitor consists of a  
rectangular block of ceramic  
dielectric in which a number of  
interleaved metal electrodes are  
contained. This structure gives  
rise to a high capacitance per  
unit volume.  
The inner electrodes are  
connected to the two end  
terminations and finally covered  
with a layer of plated tin (NiSn).  
The terminations are lead-free. A  
cross section of the structure is  
shown in Fig.1.  
Fig. 1 Surface mounted multilayer ceramic capacitor construction  
DIMENSION  
OUTLINES  
Table 1 For outlines see fig. 2  
For dimension see Table 1  
L2 / L3 (mm) L4 (mm)  
L1 (mm)  
0.5 ±0.1  
TYPE  
0204  
W (mm)  
1.0 ±0.1  
T (mm)  
min.  
max.  
min.  
0.3 ±0.1  
0.5 ±0.1  
0.1  
0.3  
0.1  
0306  
0508  
0612  
0612*  
0.8 ±0.15  
1.25 ±0.2  
1.6 ±0.2  
1.6 ±0.2  
1.6 ±0.2  
2.0 ±0.2  
3.2 ±0.2  
3.2 ±0.2  
0.1  
0.3  
0.2  
0.85 ±0.1  
0.85 ±0.1  
1.15 ±0.1  
0.13 0.46  
0.13 0.46  
0.13 0.46  
0.38  
0.50  
0.50  
Fig. 2 Surface mounted multilayer  
ceramic capacitor dimension  
0612*: 1uF/16V, 470nF~1uF/25V, 120nF~470nF/50V  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
4
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
CAPACITANCE RANGE & THICKNESS FOR X5R  
Table 2 Sizes from 0204  
CAP.  
0204  
6.3 V / 10V  
10 nF  
0.3 ±0.1  
0.3 ±0.1  
0.3 ±0.1  
0.3 ±0.1  
0.3 ±0.1  
0.3 ±0.1  
0.3 ±0.1  
15 nF  
22 nF  
33 nF  
47 nF  
68 nF  
100 nF  
150 nF  
220 nF  
330 nF  
470 nF  
680 nF  
1 uF  
NOTE  
1. Values in shaded cells indicate thickness class in mm  
2. Capacitance value of non E-6 series is on request  
3. For special ordering code, please contact local sales force before order.  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
5
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
CAPACITANCE RANGE & THICKNESS FOR X7R  
Table 3 Sizes from 0306 to 0508  
CAP.  
0306  
0508  
10 V  
6.3 V / 10V  
16 V  
25 V  
10 nF  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
15 nF  
22 nF  
33 nF  
47 nF  
68 nF  
100 nF  
150 nF  
220 nF  
330 nF  
470 nF  
680 nF  
1 uF  
0.5 ±0.1  
0.5 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
NOTE  
1. Values in shaded cells indicate thickness class in mm  
2. Capacitance value of non E-6 series is on request  
3. For special ordering code, please contact local sales force before order.  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
6
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
CAPACITANCE RANGE & THICKNESS FOR X7R  
Table4  
CAP.  
Sizes from 0612  
0612  
6.3 V  
10 V  
16 V  
25 V  
50 V  
10 nF  
15 nF  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
0.85 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
1.15 ±0.1  
22 nF  
33 nF  
47 nF  
68 nF  
100 nF  
150 nF  
220 nF  
330 nF  
470 nF  
680 nF  
1 uF  
NOTE  
1. Values in shaded cells indicate thickness class in mm  
2. Capacitance value of non E-6 series is on request  
3. For special ordering code, please contact local sales force before order  
THICKNESS CLASSES AND PACKING QUANTITY  
Table 5  
Ø 180 MM / 7 INCH  
Ø 330 MM / 13 INCH  
SIZE  
CODE  
THICKNESS  
CLASSIFICATION QUANTITY PER REEL  
TAPE WIDTH  
QUANTITY  
PER BULK CASE  
Paper  
Blister  
Paper  
Blister  
0204  
0306  
0508  
0612  
0612  
0.3 ±0.1 mm  
0.5 ±0.1 mm  
0.85 ±0.1 mm  
0.85 ±0.1 mm  
1.15 ±0.1 mm  
8 mm  
8 mm  
8 mm  
8 mm  
8 mm  
10,000  
4,000  
4,000  
4,000  
---  
---  
---  
---  
15,000  
15,000  
15,000  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
3,000  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
7
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
ELECTRICAL CHARACTERISTICS  
X7R DIELECTRIC CAPACITORS;  
Unless otherwise specified, all test and measurements shall be made under standard atmospheric conditions  
for testing as given in 5.3 of IEC 60068-1:  
- Temperature: 15 °C to 35 °C  
- Relative humidity: 25% to 75%  
- Air pressure: 86 kPa to 106 kPa  
Before the measurements are made, the capacitor shall be stored at the measuring temperature for a time  
sufficient to allow the entire capacitor to reach this temperature.  
The period as prescribed for recovery at the end of a test is normally sufficient for this purpose.  
Table 6  
VALUE  
DESCRIPTION  
Capacitance range  
10 nF to 1 uF  
Capacitance tolerance  
X5R / X7R  
±10%, ±20%  
Dissipation factor (D.F.)  
X5R / X7R  
5 %  
Insulation resistance after 1 minute at Ur (DC)  
Rins 10 GΩ or Rins × C ≥ 500 seconds whichever is less  
Maximum capacitance change as a function of temperature  
(temperature characteristic/coefficient):  
X5R / X7R  
±15%  
Operating temperature range:  
X5R  
X7R  
55 °C to +85 °C  
55 °C to +125 °C  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
8
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
SOLDERING RECOMMENDATION  
Table 7  
SIZE  
0204  
SOLDERING  
METHOD  
0306  
0508  
0612  
Reflow  
Reflow/Wave  
O
O
O
O
TESTS AND REQUIREMENTS  
Table 8 Test procedures and requirements  
TEST  
TEST  
METHOD  
PROCEDURE  
REQUIREMENTS  
No visible damage  
Mounting  
IEC  
60384-  
21/22  
4.3  
The capacitors may be mounted on printed-circuit boards or  
ceramic substrates  
Visual Inspection  
and Dimension  
Check  
4.4  
Any applicable method using × 10 magnification  
In accordance with specification  
Class 2:  
Capacitance  
4.5.1  
4.5.2  
4.5.3  
Within specified tolerance  
f = 1 KHz, measuring at voltage 1 Vrms at 20 °C  
Dissipation  
Factor (D.F.)  
Class 2:  
In accordance with specification  
In accordance with specification  
f = 1 KHz, measuring at voltage 1 Vrms at 20 °C  
Insulation  
Resistance  
At Ur (DC) for 1 minute  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
9
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
TEST  
TEST  
METHOD  
PROCEDURE  
REQUIREMENTS  
Class2:  
X7R/X5R : C/C : ±15%  
Temperature  
coefficient  
4.6  
Capacitance shall be measured by the steps shown  
in the following table.  
The capacitance change should be measured after  
5 min at each specified temperature stage.  
In case of applying voltage, the capacitance  
change should be measured after 1 more min.  
with applying voltage in equilibration of each  
temp. stage.  
Step  
Temperature()  
25±2  
a
b
c
Lower temperature±3℃  
25±2  
d
e
Upper Temperature± 2℃  
25±2  
Class II  
Capacitance Change shall be calculated from the  
formula as below  
C2 - C1  
C =  
x 100%  
C1  
C1: Capacitance at step c  
C2: Capacitance at step b or d  
Force  
size ≥ 0306: 5N  
size = 0204: 2.5N  
Adhesion  
IEC  
60384-  
21/22  
4.7  
4.8  
A force applied for 10 seconds to the line joining  
the terminations and in a plane parallel to the  
substrate  
Bending  
Strength  
Mounting in accordance with IEC 60384-22  
paragraph 4.3  
No visible damage  
Conditions: bending 1 mm at a rate of 1 mm/s,  
radius jig 5 mm  
C/C  
Class2:  
X7R/X5R : ±10%  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
10  
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
TEST  
TEST  
PROCEDURE  
REQUIREMENTS  
METHOD  
Resistance to  
Soldering Heat  
4.9  
Precondition: 150 +0/10 °C for 1 hour,  
then keep for 24 ±1 hours at room  
temperature  
Dissolution of the end face plating shall not exceed  
25% of the length of the edge concerned  
C/C  
Preheating: 120 °C to 150 °C for 1 minute  
and 170 °C to 200 °C for 1 minute.  
Class2:  
X7R/X5R : ±10%  
Solder bath temperature: 260 ±5 °C  
Dipping time: 10 ±0.5 seconds  
Recovery time: 24 ±2 hours  
D.F. within initial specified value  
Rins within initial specified value  
Solderability  
4.10  
Preheated the temperature of 80 °C to 140 The solder should cover over 95% of the critical area  
°C and maintained for 30 seconds to 60  
seconds.  
of each termination  
Test conditions for leadfree containing  
solder alloy  
Temperature: 245 ±5 °C  
Dipping time: 3 ±0.3 seconds  
Depth of immersion: 10 mm  
Rapid Change  
IEC  
4.11  
Preconditioning;  
No visual damage  
of Temperature  
60384-  
21/22  
150 +0/10 °C for 1 hour, then keep for  
24 ±1 hours at room temperature  
C/C  
Class2:  
5 cycles with following detail:  
30 minutes at lower category temperature  
30 minutes at upper category temperature  
X7R/X5R : ±15%  
Recovery time 24 ±2 hours  
D.F. meet initial specified value  
Rins meet initial specified value  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
11  
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
TEST  
TEST METHOD  
4.13  
PROCEDURE  
REQUIREMENTS  
Damp Heat  
with Ur load  
No visual damage after recovery  
1. Preconditioning, class 2 only:  
150 +0/-10 °C /1 hour, then keep for  
24 ±1 hour at room temp  
C/C  
Class2:  
2. Initial measure:  
Spec: refer initial spec C, D, IR  
X7R/X5R : ±20%  
D.F.  
3. Damp heat test:  
500 ±12 hours at 40 ±2 °C;  
90 to 95% R.H; 1.0 Ur applied.  
Class2:  
X7R/X5R : 2 x specified value  
Rins  
4. Recovery:  
Class 1: 6 to 24 hours  
Class 2: 24 ±2 hours  
Class2:  
X7R/X5R : 500 MΩ or Rins x Cr 25s  
whichever is less  
5. Final measure: C, D, IR  
Δ C/C  
P.S. If the capacitance value is less than the  
minimum value permitted, then after the other  
measurements have been made the capacitor shall  
be precondition according to “IEC 60384 4.1” and  
then the requirement shall be met.  
Class2:  
X7R/X5R : ±25%  
D.F.  
Class2:  
X7R/X5R : 2 x specified value  
Rins  
Rins x Cr 25Ω· F  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
12  
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
TEST  
TEST METHOD  
PROCEDURE  
REQUIREMENTS  
Endurance  
IEC 60384-  
21/22  
4.14  
No visual damage  
1. Preconditioning, class 2 only:  
150 +0/-10 °C /1 hour, then keep for  
24 ±1 hour at room temp  
C/C  
Class2:  
2. Initial measure:  
Spec: refer initial spec C, D, IR  
X7R/X5R : ± 20%  
3. Endurance test:  
D.F.  
Temperature: NP0: 125 °C  
Specified stress voltage applied for 1,000  
hours:  
Class2:  
X7R/X5R : 2x initial value max  
Rins  
Applied 2.0 x Ur for general product  
Class2:  
Temperature: X7R: 125°C Specified stress  
voltage applied for 1,000 hours:  
Recovery time: 24 ±2 hours  
X7R/X5R : 1,000 MΩ or  
Rins x Cr 50s whichever is less  
4. Final measure: C, D, IR  
Δ C/C  
Class2:  
P.S. If the capacitance value is less than the  
minimum value permitted, then after the other  
measurements have been made the capacitor  
shall be precondition according to “IEC 60384  
4.1” and then the requirement shall be met.  
X7R/X5R : ±25%  
D.F.  
Class2:  
X7R/X5R : 2x initial value max  
Rins  
Class2:  
Rins x Cr 50 Ω· F  
Voltage  
Proof  
IEC 60384-1  
4.5.4  
Specified stress voltage applied for 1 to 5  
seconds  
No breakdown or flashover  
Ur 100 V: series applied 2.5 Ur  
Charge/Discharge current less than 50mA  
www.yageo.com  
Nov. 21, 2016 V.1  
Product specification  
13  
13  
Low  
X5R, X7R  
6.3V to 50V  
Surface-Mount Ceramic Multilayer Capacitors  
Inductance  
REVISION HISTORY  
REVISION DATE  
CHANGE NOTIFICATION DESCRIPTION  
Version 1  
Nov. 7, 2016  
-
- Add 13" packing  
- New  
Version 0  
Jun. 26, 2015  
-
www.yageo.com  
Nov. 21, 2016 V.1  

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