YSS940_技术文档

YSS944/943/940

ADAMB

Advanced Digital Audio Multi channel decode processor

Outline

The YSS944 (ADAMB-f)/YSS943 (ADAMB-b)/YSS940 (ADAMB-nd) is an audio decoding digital signal

processor that integrates onto a single chip the various digital signal processing functions required for AV

amplifiers, etc. It includes an advanced 32-bit floating-point DSP and is able to decode a variety of audio

formats.

[Note]

• The contents described in this manual are implemented by downloading boot firmware.

For detailed information about the boot firmware, please contact YAMAHA.

• The YSS943 cannot execute DTS-ES and DTS Neo:6 decoding.

• The YSS940 cannot execute any decoding related to DTS (DTS, DTS-ES, DTS 96/24, and DTS Neo:6).

Features

•

Supports various types of decoding up to 7.1 channels (5.1/6.1/7.1 channels selectable).

5.1-channel decoding of Dolby Digital (AC-3), DTS, AAC.

6.1-channel decoding of Dolby Digital EX, DTS-ES.

DTS 96/24 decoding and audio interface clock division/switching functions.

Dolby Pro Logic IIx and DTS Neo:6 decoding

Tone control and bass management functions

Function modification/expansion by downloading firmware to on-chip memory

Lip-sync function that enables synchronization of voice and video with variable voice delay

Supports sampling frequencies up to 192 kHz during PCM playback.

1/2 down sampling function when two PCM channels are played back

Dolby Digital/DTS/AAC decode information output function (can be read by microprocessor)

High-speed/high-accuracy operation by 32-bit floating-point DSP

Operating frequency: 180 MHz (178.176 MHz)

Data bus width: 32 bits (24-bit mantissa and 8-bit exponent)

Multiplier/adder: 32 bits × 32 bits + 55 bits → 55 bits (47-bit mantissa and 8-bit exponent)

No external memory needed (external memory is used when delay is increased.)

Eight general I/O ports

On-chip PLL for generation of high-speed internal operating clock

Supply voltage: 1.2 V (core block) and 3.3 V (pin block)

Low power consumption: about 210 mW (standard value during Dolby Digital decoding)

Si-gate CMOS process

Lead-free plating LQFP144 package (YSS944-VZ, YSS943-VZ, and YSS940-VZ)

•

[Note]

“Dolby,” ”Dolby Pro Logic IIx,” and “AC-3” are trademarks of Dolby Laboratories.

“DTS,” “DTS-ES,” “DTS 96/24,” and “DTS Neo:6” are trademarks of Digital Theater Systems, Inc.

Applications

•

AV amplifiers for home theaters

Car audio systems

YSS944/943/940 CATALOG

CATALOG No.: LSI-4SS944A31

2005.6

YSS944/943/940

YSS944/943/940 functional comparison

Decoder functional comparison

devise

YSS944

YSS943

YSS940

function

Dolby Digital

Dolby Digital EX

Dolby Pro Logic IIx

AAC

YES

NO

YES

NO

DTS

DTS 96/24

DTS-ES

NO

DTS Neo:6

NO

YSS944/943/940 common functions

Input channel selection

Volume adjustment

Tone Control

Bass Management

User mute

Auto mute

Input delay

Output delay

Stream detection

Noise generation

Impulse generation

General purpose I/O port

2

YSS944/943/940

Block Diagram

Block Name

Function

This is the internal operating clock generation block.

ClkGen

MicomIF

SDI

This block provides the PLL and supplies the clock to each block.

This is an interface block to connect to a microprocessor.

This block controls access to the registers/memory in this LSI.

This is the audio interface block for DIR, ADC, etc.

This block controls the input data format/delay, etc.

This is the audio interface block for DIT, DAC, etc.

This block controls the output data format/delay, etc.

This is the stream detection block.

SDO

Detector

EMC

This block detects the input data encoding format.

This is an interface block to read from and write to external memory.

This block implements delay functions using external memory.

This is an operation processing block.

This decoder includes a 32-bit floating-point DSP and memory (ROM or RAM).

Various functions can be implemented.

Processor

Function modification/expansion by downloading firmware is also supported.

3

YSS944/943/940

Pin Configuration

nMEMCE

MEMA10

nMEMOE

MEMA18

STATUS0

STATUS1

STATUS2

STATUS3

VSS

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

MEMA15

VDD2

VSS

nMEMWE

MEMA11

MEMA9

MEMA8

VDD2

VSS

VDD2

VDD1

MISO

VSS

MISI

VSS

VDD1

MEMA13

MEMA17

IOPORT7

IOPORT6

IOPORT5

IOPORT4

IOPORT3

IOPORT2

VDD2

VSS

IOPORT1

IOPORT0

VDD1

SDO3

SDO2

MISCK

nMICS

VDD2

VSS

nIC

TEST

ZEROFLG

nINT

nMUTE

VDD1

VDD2

VSS

SDO1

SDO0

SDOMCK

SDOWCK

VSS

AVSSR

AVDDR

AHVDD

AHVDDG

< LQFP 144 TOP VIEW >

4

YSS944/943/940

Pin Functions

Type

No.

Pin Name

I/O

Note 1)

-

Function

Power supply

9

VDD1

Power supply pins for pin block (Typ. 3.3 V).

33

45

60

85

100

121

136

5

VDD2

-

Power supply pins for core block (Typ. 1.2 V).

6

15

22

23

36

50

51

63

64

70

71

79

80

88

89

95

107

108

119

120

127

128

137

138

142

AVDDR

AHVDD

AHVDDG

DVDD

-

Power supply pin 1 for PLL analog block (Typ. 3.3 V).

Be sure to insert a 0.1 F capacitor between the AVDDR and AVSSR

µ

pins.

143

144

4

Power supply pin 2 for PLL analog block (Typ. 3.3 V).

Be sure to insert a 0.1 F capacitor between the AHVDD and AHVSS

µ

pins.

Power supply pin 3 for PLL analog block (Typ. 3.3 V).

Be sure to insert a 0.1 F capacitor between the AHVDDG and

µ

AHVSSG pins.

Power supply pin for PLL digital block (Typ. 1.2 V).

Be sure to insert a 0.1 F capacitor between the DVDD and DVSS

µ

pins.

7

VSS

Ground pins

8

14

20

21

35

41

42

48

49

5

YSS944/943/940

Type

Pin Name

I/O

Function

No.

Note 1)

61

62

69

77

78

86

87

93

94

105

106

117

118

123

129

130

139

140

1

AHVSS

AHVSSG

DVSS

Ground pin 2 for PLL analog block.

Be sure to insert a 0.1 F capacitor between the AHVDD and AHVSS

µ

pins.

2

3

Ground pin 3 for PLL analog block.

Be sure to insert a 0.1 F capacitor between the AHVDDG and

µ

AHVSSG pins.

Ground pin for PLL digital block.

Be sure to insert a 0.1 F capacitor between the DVDD and DVSS

µ

pins.

141

AVSSR

Ground pin 1 for PLL analog block.

Be sure to insert a 0.1 F capacitor between the AVDDR and AVSSR

µ

pins.

Initial clear

Clock

131

18

nIC

XI

Is

I

Hardware reset input pin

The LSI is initialized when this pin is at low level.

Clock input pin.

Connect this pin as shown in the circuit example

12.288 MHz crystal oscillator.

of the

Note 2)

If not connected to a crystal oscillator, input a 12.288 MHz clock to

this pin.

19

XO

O

Is

This is the output pin for the crystal oscillator.

Connect this pin as shown in the circuit example

If not connected to a crystal oscillator and inputting directly to the XI

pin, do not connect anything to this pin. Do not use this pin for any

purpose other than clock oscillation.

.

Note 2)

Microprocessor

interface

126

nMICS

This is the microprocessor interface’s chip select input pin.

Input to the MISCK and MISI pins becomes valid when this pin is at

low level.

125

124

MISCK

MISI

Is

I

This is the microprocessor interface’s clock input pin.

This is the microprocessor interface’s address read/write control and

data input pin.

122

32

MISO

Ot

Is

This is the microprocessor interface’s data output pin.

Connect a pull-up resistor.

Audio interface

SDIMCK

This is the master clock input pin for the audio interface’s input side.

The master clock is input from DIR, ADC, etc.

The highest clock frequency that can be input is 25 MHz.

(The clock rate is 512 fs when the input sampling frequency is 48 kHz

or less, 256 fs when the frequency is 96 kHz, and 128 fs when the

frequency is up to 192 kHz.)

31

SDIBCK

Is

This is the bit clock I/O pin for the audio interface’s input side.

6

YSS944/943/940

Type

Pin Name

I/O

Function

No.

Note 1)

It inputs a 64 fs bit clock.

30

26

SDIWCK

SDI3

I

This is the word clock pin for the audio interface’s input side.

This is the audio interface’s serial data input pin 3.

If this pin is not used, connect it to a ground.

27

28

29

SDI2

SDI1

SDI0

I

This is the audio interface’s serial data input pin 2.

If this pin is not used, connect it to a ground.

This is the audio interface’s serial data input pin 1.

If this pin is not used, connect it to a ground.

This is the audio interface’s serial data input pin 0.

Connect digital audio data (various streams or PCM) via IEC60958 to

this pin.

Audio interface

38

SDOMCK

Ot

This is the master clock output pin for the audio interface’s output

side.

It outputs the master clock to DIT, DAC, etc.

The highest clock frequency that can be output is 25 MHz.

This is the bit clock I/O pin for the audio interface’s output side.

It inputs or outputs a 64 fs bit clock.

34

SDOBCK

Is/O

37

44

SDOWCK

SDO3

I/O

O

This is the word clock pin for the audio interface’s output side.

This is the audio interface’s serial data output pin 3.

This is the audio interface’s serial data output pin 2.

This is the audio interface’s serial data output pin 1.

This is the audio interface’s serial data output pin 0.

These are external memory address output pins 18 to 0.

If external memory is not used, these pins should be left unconnected.

43

SDO2

O

40

SDO1

O

39

SDO0

O

External memory

interface

112

58

MEMA18

MEMA17

MEMA16

MEMA15

MEMA14

MEMA13

MEMA12

MEMA11

MEMA10

MEMA9

MEMA8

MEMA7

MEMA6

MEMA5

MEMA4

MEMA3

MEMA2

MEMA1

MEMA0

MEMD7

MEMD6

MEMD5

MEMD4

MEMD3

MEMD2

MEMD1

MEMD0

nMEMCE

O

73

72

74

59

75

67

110

66

65

76

81

82

83

84

90

91

92

104

103

102

101

99

I/O

These are external memory data I/O pins 7 to 0.

If external memory is not used, these pins should be left unconnected.

98

97

96

109

O

This is the external memory chip select output pin.

If external memory is not used, this pin should be left unconnected.

This is the external memory output enable output pin.

If external memory is not used, this pin should be left unconnected.

This is the external memory write enable output pin.

If external memory is not used, this pin should be left unconnected.

This is the interrupt request output pin.

111

68

nMEMOE

nMEMWE

nINT

Status ports

134

7

YSS944/943/940

Type

Pin Name

I/O

Function

No.

Note 1)

135

133

13

nMUTE

ZEROFLG

STATUS7

STATUS6

STATUS5

STATUS4

STATUS3

STATUS2

STATUS1

STATUS0

IOPORT7

IOPORT6

IOPORT5

IOPORT4

IOPORT3

IOPORT2

IOPORT1

IOPORT0

TEST

O

This is the output pin during auto mute periods.

This is the consecutive zero data input detection pin.

These are status output pins 7 to 0.

They are used to confirm firmware operations.

Normally, they should be left unconnected.

12

11

10

116

115

114

113

57

General-purpose

I/O ports

I(+)/O These are general I/O port pins 7 to 0.

Their I/O status can be set via register settings.

I(+)/O These are general I/O port pins 7 to 0.

Their I/O status can be set via register settings.

56

General-purpose

I/O ports

55

54

53

52

47

46

Test

16

Is

Test pins

Connect these pins to a ground.

17

24

25

132

Note 1) I/O symbols

• I:

Input

• Is:

• O:

Schmitt trigger input

Output

• Ot: Tri-state output

• I/O: I/O

• I(+)/O: Pull-up during input, no pull-up during output

Note 2) Example of circuit connected to crystal oscillator

XI

XO

12.288 MHz

* The above resistor and capacitor vary depending on the crystal oscillator. Be sure to comply with the specifications of the

crystal oscillator used.

8

YSS944/943/940

Function Description

Functions of the YSS944/943/940 are follows.

(1) Main Decoder Functions

• Dolby Digital decoding

- Firmware AC3 decoder is included.

- Supports Annex D.

- Supports sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz.

- 5.1-channel decoding.

• DTS decoding

- Firmware DTS decoder is included.

- Supports DTS-ES Discrete 6.1 decoding. (Sampling frequencies of 44.1 kHz and 48 kHz.)

- Supports DTS 96/24 decoding. (Output sampling frequencies of 88.2 kHz and 96 kHz.)

[Note]

- The YSS943 does not support DTS-ES Discrete 6.1 decoding.

- The YSS940 does not support any DTS decoding.

• AAC decoding

- Firmware AAC decoder is included.

- Complies with ARIB digital broadcast standard.

- Supports ADTS.

- Supports LC profile.

- Supported sampling frequencies are 32 kHz, 44.1 kHz, and 48 kHz.

- 5.1-channel decoding

• PCM 2-channel input playback

- Firmware PCM2 player is included.

- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz,

176.4 kHz, and 192 kHz.

- Supports 24-bit word length.

- De-emphasis function.

- Input DC cutoff function.

- 1/2 down sampling function.

• PCM 6-/7-/8-channel input playback

- Firmware PCM8 player is included.

- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz,

176.4 kHz, and 192 kHz.

- Supports 24-bit word length.

- De-emphasis function.

- Input DC cutoff function.

- Audio data input channel control function.

(2) Post Decoder Functions

The following post-decoder function can be applied to the results of main decoder described above.

• Dolby Pro Logic IIx decoding

- Firmware PL2 decoder is included.

- Expands to up to 7 channels from 2 channels of L and R.

- Expands to up to 4 channel from 2 channels of LS and RS (supports Dolby Digital EX with the

combination of Dolby Digital decoding function)

- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 176.4 kHz,

and 192 kHz.

• DTS Neo:6 decoding

- Firmware Neo:6 decoder is included.

- Expands to up to 6 channels from 2 channels of L and R.

9

YSS944/943/940

- Expands to 3 channels from 2 channels of LS and RS (supports ES Matrix processing when combined

with DTS decoding function).

- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, and 96 kHz.

[Note]

- The YSS943 and YSS940 do not support DTS Neo:6 decoding.

(3) Post Processor Functions

The following post-processing function can be applied to the results of main decoder or post decoder.

• Post-processing input channel selection

- Firmware Switcher is included.

- Supports 8 channels.

• Tone control

- Firmware Tone controller is included.

- Adjustable bass and treble for left and right channels

- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz,

176.4 kHz, and 192 kHz.

• Bass Management

- Firmware Bass manager is included.

- Characteristics can be changed by changing the coefficient.

- Up to 7.1-channel input/output.

- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz,

176.4 kHz, and 192 kHz.

• Volume adjustment

- Firmware Scaler is included.

- Adjustable master volume (setting range: -127 dB to +31 dB, in 1 dB units).

- Adjustable volume for up to eight channels (-∞ dB to +12 dB, phase inversion enabled).

(4) Generator Functions

• Noise generation

- Firmware noise generator is included.

- Enables generation of pink noise (“shaped noise” in the Dolby standard) and white noise.

- Supported sampling frequencies are 32 kHz, 44.1 kHz, and 48 kHz.

• Impulse generation

- Firmware impulse generator is included.

- Impulses can be generated.

- Supported sampling frequencies are 32 kHz, 44.1 kHz, and 48 kHz.

(5) Other Functions

• Microprocessor interface

- This is a four-wire serial interface.

- Enables register access and on-chip memory access (firmware download).

• Firmware download

- Instruction code from the microprocessor to this LSI and coefficient data can be downloaded.

- The amount of 6-/7-/8-channel output delay can be changed.

- The filter characteristics of the bass management function can be changed.

- Functions can be expanded for future use.

[Note]

- The boot firmware must be downloaded at initialization.

10

YSS944/943/940

• Audio interface

- Master clock, bit clock, word clock, and four serial data (8ch) for input and output are provided

respectively.

- Various audio interface formats are supported.

- The bit clock rate is fixed to 64 fs.

- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz,

176.4 kHz, and 192 kHz.

- The bit clock and word clock on the output side have switchable input/output, and can therefore be

used as either master or slave.

- A clock divider/switching function is included to enable adjustment of the input/output sampling

frequency for DTS 96/24, etc.

• Audio data output channel control

- Audio output data can be output to any of the channels for the SDO3 to SDO0 pins.

• Bypass

- Output of SDI data to SDO can bypass the internal core logic.

• User mute

- Output channels can be muted via the microprocessor interface.

• External memory interface

- Up to 4 Mb of SRAM can be connected for input delay and/or output delay.

- Access time can be adjusted via register settings.

• Input delay (lip sync)

- Input delay for adjusting synchronization between video and audio can be implemented when using

external memory.

• Output delay

- 3-/4-/5-/6-/7-/8-channel output delay with an output sampling frequency of up to 192 kHz can be

implemented without using external memory (some exceptions).

- 3-/4-/5-/6-/7-/8-channel output delay with an output sampling frequency of up to 96 kHz can be

implemented using external memory.

• Stream detection

- Encoding format detection

- Zero detection

- Input sampling frequency detection

• Auto mute

- All channels are muted automatically by detection of noise generation factor.

• Status ports

- Consecutive-zero data input detection: 1 pin.

- Auto mute period output:

- Interrupt request output:

1 pin.

• General purpose I/O port

- 8 general purpose I/O ports are available.

- Input and output mode can be switched by register setting.

• Internal operating clock generation

- Generates the high-speed internal operating clock by on-chip PLL.

• Power-up/power-down

- Enables power-up/power-down control of the LSI via register settings.

11

YSS944/943/940

Microprocessor Interface

External microprocessor or similar devices use this microprocessor interface (4-wire serial interface) to

perform the following tasks.

•

Access to registers

Firmware download to on-chip memory

(1) Register access

Registers are accessed in 16-bit units via the microprocessor interface. MISI is used to specify the register’s

address (7 bits: A6 to A0) and the read/write option (1 bit:R/W). During a write operation (R/W=L), data (8

bits: D7 to D0) is input to MISI and during a read operation (R/W=H) 8-bit data is output from the MISO pin.

The data to be written is stored in the register at the rising edge of MISCK during the last data bit (D7 in

figure).

The microprocessor interface’s sequence when accessing registers is shown below.

nMICS

MISCK

During

write

Don't care

A0 A1 A2 A3 A4 A5 A6 R/W D0 D1 D2 D3 D4 D5 D6 D7

Don't care

MISI

operation

(R/W = L)

High-Z

MISO

During

read

operation

(R/W = H)

Don't care

A0 A1 A2 A3 A4 A5 A6 R/W

Don't care

High-Z

MISI

High-Z

D0 D1 D2 D3 D4 D5 D6 D7

MISO

[Note]

• MISO is in output mode only when nMICS is at low level and during the data (8 bits) output timing.

Otherwise, it is in high impedance (High-Z) mode and MISCK, MISI, and MISO can be shared for devices

that have a similar interface.

• Registers can be accessed continuously while nMICS remains at low level. There is no need to

repeatedly set nMICS to high level.

• Certain register settings enable nMICS to be shared by multiple LSIs.

• Access to on-chip memory (firmware download) is performed by combining with control of writing to a

register

• Operation during a hardware reset (when nIC is at low level):

During a hardware reset, the microprocessor interface does not function. Also, MISO is fixed at high

impedance (High-Z). When nIC is at low level, nMICS should be initialized to high level.

• Interruption of access:

Access can be interrupted by setting nMICS to high level. The write operation prior to the 16th rising

edge of MISCK (MISI’s D7 data capture clock) described above becomes invalid. The MISO pin is set

to high impedance (High-Z).

12

YSS944/943/940

(2) On-chip memory access (firmware download)

Access to on-chip memory is performed in 32-bit units via the microprocessor interface. Also, on-chip

memory access can be performed concurrently with register access. The two firmware downloading

methods prepared for this LSI are explained below.

(a) Burst transfer mode

When the IA carrier (PRGMOD[1:0] = 11) is used, instruction code/coefficient data firmware can be

downloaded in this mode. By using this mode, a large amount of data can be downloaded at high speeds

when initialization is executed or when the sampling frequency is changed. The features of the burst

transfer mode are as follows.

• During the transfer period, decoding is aborted and data is transferred at high speeds. Muting is

automatically effected during the transfer period.

• Data transferred from the microprocessor can be received without handshaking.

• Both instruction code firmware and coefficient data firmware can be downloaded.

The microprocessor interface’s sequence in firmware downloading burst transfer mode is shown below.

<1>

<2>

<3>

<4>

nMICS

MISCK

Don't care

A

A+1 A+1 A+1 A+1

A+n A+n A+n A+n

D28 D29 D30 D31

D4 D5 D6 D7

MISI

D0 D1 D2 D3

D28 D29 D30 D31 D0 D1 D2 D3

High-Z

MISO

[Access steps and statuses]

<1> Register setting:

The microprocessor interface function change for the on-chip memory access start address (A in

figure) and on-chip memory access is set by register as shown below.

• Set the instruction code firmware download mode (IACNFG = 1)

• Change the firmware program mode to IA carrier (PRGMOD[1:0] = 11).

• Set the on-chip memory access start address IAA[20:0].

• Change the function of the microprocessor interface pin from register access to on-chip memory

access (IA = 1).

Once this setting is made, the microprocessor interface functions in firmware downloading burst

transfer mode until the nMICS pin is set to high level.

<2> Start firmware download:

• The nMICS pin is fixed at low level.

• Data is transferred LSB first, in 32-bit units.

• Data is written to on-chip memory when the rising edge of MISCK occurs for the 32nd bit of data

(D31 in the figure).

<3> Continuation and termination of firmware download:

• Each time 32 bits of data are written, IAA[20:0] is automatically incremented. Accordingly, when

writing to consecutive addresses, only the data is transferred.

• When nMICS changes from low level to high level, firmware download ends and the

microprocessor interface returns to accessing registers.

• When accessing non-consecutive on-chip memory addresses or when resuming firmware

downloading after an access interruption, be sure to set IAA[20:0] as described in <1> above.

<4> When this LSI has not been selected:

<5> Register setting:

After completing a firmware download, perform the following processing.

• Set the instruction code firmware execution mode (IACNFG = 0).

• Report the existence of boot firmware to this LSI (DL = 1).

• Change the firmware program mode PRGMOD[1:0] from “IA carrier” to another mode.

13

YSS944/943/940

[Note]

Interruption of burst transfer:

• Burst transfer can be interrupted by setting nMICS to high level.

• The write operation becomes invalid when the rising edge of MISCK occurs for the 32nd bit of data (D31

in the figure).

• The MISO pin is set to high impedance (High-Z).

(b) Runtime transfer mode

When the main decoder, noise generator, or impulse generator is used (PRGMOD[1:0] = 00, 01, or 10), the

coefficient data firmware can be downloaded in this mode. By using this mode, coefficients such as the

amount of 6-/7-/8-channel output delay can be changed without disruption of sound. The features of the

runtime transfer mode are as follows.

• Transfer is executed while decoding continues. Muting is not automatically effected during the transfer

period.

• One word is transferred at a time while the device is handshaking with the microprocessor.

• Up to 32 words of transfer data are buffered and written all at once to the on-chip memory.

• Downloading coefficient firmware is supported.

[Access steps and statuses]

<1> Start firmware download:

Set the runtime transfer mode and transfer start address by using registers.

• Initialize the handshake-related registers (RDLFLG = RDLEND = RDLCNT[4:0] = 0).

• Set the runtime transfer mode (RDLMODE = 1).

• Set the on-chip memory access start address IAA[20:0].

<2> Execute firmware download:

One word (32 bits) is downloaded at a time.

• Change the microprocessor interface pin function from register access to on-chip memory access (IA

= 1). IAA[20:16] in this byte is valid only when it is set for the first time (for the second and

subsequent time, any value may be written).

• Fix nMICS to L.

• Transfer data with the LSB first and in 32-bit units.

• Raise nMICS from L to H.

• Read RDLCNT[4:0].

• Specify starting data transfer (RDLFLG = 1).

Set RDLEND to 1 if the transferred data is the last word in successive address transfer; otherwise,

clear RDLEND to 0. At this time, write back the value that is read, to RDLCNT[4:0].

<3> Continuation of firmware download (if RDLEND = 0 in <2>):

• Confirm the termination of data transfer (RDLFLG = 0).

• Return to step <2> above.

<4> Termination of firmware download (if RDLEND = 1 in <2>):

• Confirm the termination of data transfer/successive address transfer (RDLFLG = RDLEND = 0).

• Cancel the runtime transfer mode (RDLMODE = 0).

[Note]

• Runtime transfer can be stopped by making nMICS high and clearing RDLMODE to 0.

• Start from <1> if non-successive addresses are transferred or when execution is started again after stopping

downloading.

• When the transfer data is captured in the internal buffer, the value of RDLFLG automatically changes from

1 to 0.

If RDLEND = 0 at this time, the transfer data is written only to the internal buffer and not to the transfer

destination address.

If RDLEND = 1, the transfer data, along with the data in the internal buffer, is sequentially written from

the transfer start address. If data of two or more words, such as filter coefficients, are changed at the

same time, transfer them as successive address data.

• Transfer successive address data in the order of the address data that has been incremented starting from

the data of the transfer start address.

• Up to 32 words can be transferred as successive address data.

If more than 32 words are transferred to successive addresses, start the next transfer from <1> after the

first 32 words have been transferred.

• The time until RDLFLG is automatically cleared to 0 after it has been set to 1 varies from 0 to 4 ms.

• Unlike the burst transfer mode, it is not necessary to change IACNFG and PRGMOD[1:0].

14

YSS944/943/940

(3) Microprocessor interface connection example

When microprocessor interface pins are shared by several LSIs, the target LSI can be selected by either of the

following two methods.

• Design nMICS pins dedicated to specific LSIs.

• When nMICS pins are shared by several LSIs, use the ChipAdr register to select the target LSI.

These two examples are described below.

(a) Microprocessor interface connection example 1 (single LSI)

nMICS

Default value after hardware reset is CAE = 0,

Chip 0

so there is no need to write to ChipAdr.

IOPORT3 to IOPORT0 = X

<1>

<2>

<3>

<4>

<5>

nMICS

MISI

WriteChipAdr

CAE = 0

CA [3:0] =0100

WriteChipAdr

CAE = 1

CA [3:0] =XXXX

Read ChipAdr

CAE = 0

CA [3:0] =0100

On-chip memory access

CAE

(Chip0)

0

Internal signal

nMICS (Chip0)

<1> A write operation to ChipAdr as the register access immediately after the falling edge of nMICS is

valid.

In the above figure, an example of writing when CAE = 0 and CA[3:0] = 4 is illustrated.

<2> A write operation to ChipAdr as the register access immediately after the falling edge of nMICS is

invalid.

<3> ChipAdr can be read at any time.

In this case, the write operation (<2>) is disabled, so the write results from <1> are read.

<4> Registers cannot be accessed while accessing on-chip memory.

15

YSS944/943/940

(b) Microprocessor interface connection example 2 (multiple LSIs)

nMICS

When multiple LSIs are connected such as on

the left, or when the device has a similar

interface, access is performed using the register

byte ChipAdr (CAE, CA[3:0]).

Chip 2

Chip 3

IOPORT3 to IOPORT0 = 2

IOPORT3 to IOPORT0 = 3

<1>

<2>

<3>

<4>

<5>

n MICS

MI SI

Write ChipAdr

CAE = 1

CA[3:0] = 0011

Write ChipAdr

CAE = 1

CA[3:0] = 0010

Read ChipAdr

CAE = 1

CA[3:0] = 0011

On-chip memory access

CAE

(Chip 2, 3)

0

1

0

Internal signal

nMICS (Chip 2)

Internal signal

nMICS (Chip 3)

<1> A write operation to ChipAdr as the register access immediately after the falling edge of nMICS is

valid to for all LSIs (chips 2 and 3 in this example) that share the nMICS pin. In this case, CAE = 1

and CA[3:0] = 3, so only the access only for chip 3 is valid.

<2> A write operation to ChipAdr not immediately after the falling edge of nMICS is also invalid for chip

3.

(Chip 2 is not affected by the register access itself.)

<3> The ChipAdr register can be read at any time. In this case, the write results from <1> are read from

chip 3.

(Chip 2 is not affected by the register access itself.)

<4> During on-chip memory access, register access for chip 3 is invalid.

(Chip 2 is not affected by on-chip memory access.)

<5> CAE of all LSIs becomes zero at the rising edge of nMICS.

[Note]

The timing by which the chip selection is confirmed in <1> is determined by the value of IOPORT3 to

IOPORT0 either at:

• the register access immediately after falling edge of nMICS, or

• a write operation to ChipAdr.

Once the chip selection is confirmed, the current value is retained until the next rising edge of nMICS.

Accordingly, even if the selected chip’s own IOPORT3 to IOPORT0 values change, the chip does not

become deselected immediately.

When nMICS is shared by multiple chips:

• CAE = 0 at the register access immediately after the falling edge of nMICS or CAE = 1 is not written.

• CAE = 1 at the register access immediately after the falling edge of nMICS, but the values of IOPORT3

to IOPORT0 are the same for multiple LSIs.

In the above cases, the multiple LSIs that share nMICS become the selected devices. In such cases,

multiple LSIs can be written to at once, but note with caution that a conflict can occur with the MISO output

when they are read.

16

YSS944/943/940

Audio Interface

Input and output of digital audio data is performed via two interfaces:

• SDI (serial data input) interface

• SDO (serial data output) interface

(1) SDI interface format

The following serial data input format is supported via register settings.

Regardless of the register setting, the input signals for SDI3 to SDI0 are always handled as fixed-point 24-bit

data.

１ frame （IEC60958 Frame）

L ch

R ch

SDIWP = 0

SDIWP = 1

SDIBP = 0

SDIBP = 1

SDIWCK

SDIBCK

32 clock cycles

24 clock cycles

SDIFMT[1:0]=00

SDIBIT[1:0]=XX

M

L

M

L

24 bits

SDIFMT[1:0]=1X

SDIBIT[1:0]=XX

M

L

M

L

SDIFMT[1:0]=01

SDIBIT[1:0]=00

L

M

8 7

6 5

4 3

L

M

8 7

6 5

4 3

L

SDI3

to

SDIFMT[1:0]=01

SDIBIT[1:0]=01

L

M

L

M

SDI0

SDIFMT[1:0]=01

SDIBIT[1:0]=10

L

M

L

M

SDIFMT[1:0]=01

SDIBIT[1:0]=11

M

M : MSB DATA L : LSB DATA

17

YSS944/943/940

(2) SDO interface format

The following serial data output format is supported via register settings.

Regardless of the register setting, the output signals for SDO3 to SDO0 are always handled as fixed-point

24-bit data.

１ frame （IEC60958 frame）

L ch

R ch

SDIWP = 0

SDOWP = 1

SDOBP = 0

SDOBP = 1

SDOWCK

SDOBCK

32 clock cycles

24 clock cycles

SDOFMT[1:0]=00

SDOBIT[1:0]=XX

M

L

M

L

24 bits

SDOFMT[1:0]=1X

SDOBIT[1:0]=XX

M

L

M

L

SDOFMT[1:0]=01

SDOBIT[1:0]=00

L

M

8 7

6 5

4 3

L

M

8 7

6 5

4 3

L

SDO3

to

SDOFMT[1:0]=01

SDOBIT[1:0]=01

L

M

L

M

SDO0

SDOFMT[1:0]=01

SDOBIT[1:0]=10

L

M

L

M

SDOFMT[1:0]=01

SDOBIT[1:0]=11

M

M : MSB DATA L : LSB DATA

18

YSS944/943/940

Interrupt Requests

This LSI’s status changes by any of the following five factors are externally reported as interrupt requests via

the nINT pin.

<1> When mute status is set by the auto mute function

<2> When mute status is canceled by the auto mute function

<3> When decode information is changed

<4> When the main decoder is changed (MAINMOD[7:0] are changed)

<5> When the post decoder is changed (POSTMOD[7:0] are changed)

IM register can enable or disable generation of the interrupt of each interrupt factor, and IR register can check

generation of and clear an interrupt factor. However, generation of an interrupt factor is not affected by the

IM register setting. Changes in the status of this LSI are always detected and reported to IR register.

General Purpose I/O Ports

The general-purpose I/O ports IOPORT7 to IOPORT0 have the following functions. The functions are

switched by IOSEL[7:0].

<1> Input port:

Pin statuses are read via IPORT[7:0].

<2> Output port:

Setting values in OPORT[7:0] are output from pins.

<3> CA comparison port:

IOPORT3 to IOPORT0 function as a CA comparison port that is used when nMICS is shared by

several LSIs.

A functional outline of IOPORT7 to IOPORT0 is shown below.

19

YSS944/943/940

Register List

The YSS422/421 is controlled by accessing the following registers via the microcomputer interface (nMICS,

MISCK, MISI, and MISO).

Default

Address Byte Name R/W

D7

D6

0

D5

0

D4

0

D3

D2

D1

D0

Value

0x00

ChipAdr R/W 0x00

CAE

CA[3:0]

0x01

0x02

0x03

IOsel

IPort

R/W 0x00

IOSEL[7:0]

R

IPORT[7:0]

OPORT[7:0]

Undefined

OPort

R/W 0x00

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

Mute

R/W 0x00 nMUTE_3R nMUTE_3L

nMUTE_2R

nMUTE_2L

nMUTE_1R nMUTE_1L nMUTE_0R nMUTE_0L

SDIOClk R/W 0x00

MCKOUT

SDISEL[1:0]

0

MSEL[1:0]

WBCKOUT

SDIBIT[1:0]

SDOBIT[1:0]

WBSEL[2:0]

SDIWP

SDI

R/W 0x00

SDIFMT[1:0]

SDOFMT[1:0]

SDIBP

SDO

BYPASS

0

SDOWP

SDOBP

SDOsel0 R/W 0x10

SDOsel1 R/W 0x32

SDOsel2 R/W 0x54

SDOsel3 R/W 0x76

0

SDOSEL_0R[2:0]

0

SDOSEL_0L[2:0]

SDOSEL_1L[2:0]

SDOSEL_2L[2:0]

SDOSEL_3L[2:0]

SDOSEL_1R[2:0]

SDOSEL_2R[2:0]

SDOSEL_3R[2:0]

EM0

EM1

EM2

Zero

IA0

R/W 0x00

EM_OEH[1:0]

EM_WEH[1:0]

EM_CYC[3:0]

EM_INSIZE[4:0]

R/W 0x00 EM_INCLR

0

R/W 0x00

EM_OUTSIZE[4:0]

EM_OUTCLR

IA

ZERO[7:0]

0

IAA[20:16]

IA1

IAA[15:8]

IAA[7:0]

IA2

IACnfg

IACNFG

IMMUTE

0

IMUMUTE

IMBSCHG

IMMAINCHG IMPOSTCHG

IRMAINCHG IRPOSTCHG

0

0x14

IM

R/W 0x00

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

IR

State

IRMUTE

nMUTE

IRUMUTE

0

IRBSCHG

0

R

0x00

0

IEC61937

PC[15:8]

DTSCD[1:0]

ZEROFLG

Pc0

Pc1

PC[7:0]

FsCnt

MainMod

PostMod

Stream

FSCNT[7:0]

MAINMOD[7:0]

POSTMOD[7:0]

STREAM[7:0]

PrgMod R/W 0x00

PRGMOD[1:0]

0

DTSCDIGN

DSNIGN

DSNSEL[2:0]

DELAY[11:8]

Dly0

Dly1

R/W 0x00

0

DELAY[7:0]

0x20

0x21

Download R/W 0x00 RDLMODE

0

CHISEL[2:0]

CHCNFG[1:0]

OUTMOD[3:0]

DL

OutMode R/W 0x00

VOLON

PNWN

DUALMOD[1:0]

0x22 NoiseMode R/W 0x00

0x23 NoiseLevel R/W 0x00

0

NOISEFS[1:0]

NOISELEV[7:0]

0x24

0x25

SDly

CDly

R/W 0x00

0

SDELAY[4:0]

0

CDELAY[2:0]

0x26

0x27

0x28

0x29

BSDly

Switch

R/W 0x00

0

BSDELAY[5:0]

RSOUTOFF LSOUTOFF ROUTOFF

LFEOUTOFF LBOUTOFF

COUTOFF

LOUTOFF

RBOUTOFF

LVolume R/W 0x00

RVolume R/W 0x00

LVOL[7:0]

RVOL[7:0]

LSVOL[7:0]

RSVOL[7:0]

CVOL[7:0]

0x2A LSVolume R/W 0x00

0x2B RSVolume R/W 0x00

0x2C

CVolume R/W 0x00

0x2D LSVolume R/W 0x00

0x2E LFEVolume R/W 0x00

LBVOL[7:0]

LFEVOL[7:0]

20

YSS944/943/940

0x2F RBVolume R/W 0x00

RBVOL[7:0]

MVOL[7:0]

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

R/W 0x00

MasterVolume

LScaleH R/W 0x00

LScaleL R/W 0x00

RScaleH R/W 0x00

RScaleL R/W 0x00

LSScaleH R/W 0x00

LSScaleL R/W 0x00

RSScaleH R/W 0x00

RSScaleL R/W 0x00

CScaleH R/W 0x00

CScaleL R/W 0x00

LSCALE[15:8]

LSCALE[7:0]

RSCALE[15:8]

RSCALE[7:0]

LSSCALE[15:8]

LSSCALE[7:0]

RSSCALE[15:8]

RSSCALE[7:0]

CSCALE[15:8]

CSCALE[7:0]

0x3B LBScaleH R/W 0x00

0x3C LBScaleL R/W 0x00

LBSCALE[15:8]

LBSCALE[7:0]

LFESCALE[15:8]

LFESCALE[7:0]

RBSCALE[15:8]

RBSCALE[7:0]

0x3D LFEScaleH R/W 0x00

0x3E LFEScaleL R/W 0x00

0x3F RBScaleH R/W 0x00

0x40

0x41

0x42

0x43

0x44

0x45

RBScaleL R/W 0x00

SimMode R/W 0x00

ALLDELAY DELAYOFF

BASS[3:0]

0

TC

R/W 0x00

TREBLE[3:0]

PCMFS[3:0]

BMMode R/W 0x00

HDynrng R/W 0x00

LDynrng R/W 0x00

0

BMMODE

HDYNRNG[7:0]

LDYNRNG[7:0]

0x46 PCMMode0 R/W 0x00

0x47 PCMMode1 R/W 0x00

PCMDLY

0

PCMIGN

PCMEMPON

PCMDS

PCMDCCUTON

PCM20MOD[2:0]

0

0x48 AC3Mode0 R/W 0x00 AC3P11OFF AC3DIALOFF AC3DITHOFF AC3CRCOFF

AC3STAUTO

AC3COMP[1:0]

AC3KARAOKE

0x49 AC3Mode1 R/W 0x00

0x4A DTSMode0 R/W 0x00

0x4B DTSMode1 R/W 0x00

0x4C AACMode0 R/W 0x00

0x4D AACMode1 R/W 0x00

0

AC320MOD[2:0]

0

AC3S2MOD[2:0]

DTSEXT[1:0]

DTSDITHOFF

0

DTSDIAL

DTSS2MOD[2:0]

0

DTSCOMP

0

DTS20MOD[2:0]

AACMIX AACMIXSET AACMIXLEV AACCRCOFF

0

AAC20MOD[2:0]

AACS2MOD[2:0]

0x4E

0x4F

0x50

Reserved R/W 0x00

0

0x51 PL2XMode0 R/W 0x00

0x52 PL2XMode1 R/W 0x00

PL2XDECMOD[1:0]

PL2XINVMAT PL2XSPLIT PL2XRSINV PL2XAIBON

PL2XSRFIL[1:0]

PL2XDIMCFG[3:0]

PL2XCWCFG[2:0]

0

0x53 Neo6Mode0 R/W 0x00 N6DECMOD

0x54 Neo6Mode1 R/W 0x00 N6CGAINON

0

N6CGAIN[6:0]

0

0x55

0x56

0x57

Reserved R/W 0x00

RunTime R/W 0x00

Reserved R/W 0x00

0

RDLFLG

0

RDLEND

0

RDLCNT[4:0]

0

0x58 Bitstream0 R/W 0x00

0x59 Bitstream1 R/W 0x00

0x5A Bitstream2 R/W 0x00

0x5B Bitstream3 R/W 0x00

0x5C Bitstream4 R/W 0x00

0x5D Bitstream5 R/W 0x00

0x5E Bitstream6 R/W 0x00

0x5F Bitstream7 R/W 0x00

0x60 Bitstream8 R/W 0x00

0x61 Bitstream9 R/W 0x00

0x62 Bitstream10 R/W 0x00

0x63 Bitstream11 R/W 0x00

0x64 Bitstream12 R/W 0x00

0x65 Bitstream13 R/W 0x00

Main decoder’s decode information output

21

YSS944/943/940

Main decoder’s decode information output

0x66 Bitstream14 R/W 0x00

0x67 Bitstream15 R/W 0x00

0x68 Bitstream16 R/W 0x00

0x69 Bitstream17 R/W 0x00

0x6A Bitstream18 R/W 0x00

0x6B Bitstream19 R/W 0x00

0x6C Bitstream20 R/W 0x00

Main decoder’s decode information output

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

Test

Access prohibited.

0x7A

0x7B

0x7C

0x7D

PLL0

PLL1

R/W 0x1B

R/W 0x00

R/W 0x80

0

PLL_F[6:0]

PLL_OD[1:0]

nRESET

PD[1:0]

PLL_RDIV1

PLL_R[4:0]

IC[3:0]

nReset

Power

0

UP

DOWN

0x01

R

0x7E ADAMID

0

ADAM_ID[2:0]

0x00

0x7F

DevID

R

0x03

DEV_ID = 0x03

[Note]

Register addresses 0x6D to 0x79 comprise a test area. Writing of values to this area is prohibited and read

values are undefined.

Access conditions for other addresses are shown below.

(Bold frame) indicates area that is accessible regardless of PD[1:0] value.

(Narrow frame) indicates area that is accessible only when PD[1:0] = 00. When PD[1:0] is not “00”

values in this area are undefined when read or written.

(Shaded) indicates areas reserved for future expansion. Write zeros to these areas. Their output is

undefined.

0

22

YSS944/943/940

Electrical Characteristics

(1) Absolute Maximum Ratings

Item

Symbol

Min.

-0.5

Max.

4.6

Unit

V

VDD1

AVDDR

AHVDD

AHVDDG

VDD2

DVDD

VI

Power supply voltage 1 (3.3 V)

Power supply voltage 2 (1.2 V)

-0.5

1.68

V

Input voltage1 Note 1)

Input voltage2 Note 2)

Storage temperature

-0.5

-50

5.5

4.6

125

V

V12

V

TSTG

°C

Condition: All GND pins (VSS, AVSSR, AHVSS, AHVSSG, and DVSS) are 0 V.

Note 1) Applies to input pins other than the X1 pin.

Note 2) Applies to the X1 pin.

(2) Recommended Operating Conditions

Parameter

Symbol

Min.

3.0

Typ.

3.3

Max.

Unit

V

VDD1

AVDDR

AHVDD

AHVDDG

VDD2

Power supply voltage 1(3.3 V)

3.6

Power supply voltage 2(1.2 V)

Operating temperature

1.14

-40

1.2

25

1.26

85

V

DVDD

Top

°C

Condition: All GND pins (VSS, AVSSR, AHVSS, AHVSSG, and DVSS) are 0 V.

(3) Current Consumption

Parameter

Condition

Min.

Typ.

211

13

Max.

Unit

Power consumption

395

21

mW

mA

µA

Notes 1 and 4)

3.3 V current consumption(normal operation mode)

1.2 V current consumption(normal operation mode)

3.3 V current consumption (power-down mode)

1.2 V current consumption (power-down mode)

Notes 1, 2, and 4)

Notes 1, 3, and 4)

Notes 1, 2, 5 and 6)

Notes 1, 3, 5, and 6)

140

35

253

90

15

85

mA

Note 1) Typical values are typical under the recommended operating conditions. Maximum values are the

maximum conditions under the recommended operating conditions.

Note 2) Total current of VDD1, AVDDR, AHVDD, and AHVDDG

Note 3) Total current of VDD2 and DVDD

Note 4) Typical value is at Dloby Digital. Maximum values are at PCM 2-chanel 192kHz+Dolby Pro Logic

IIx+Bass Management.

Note 5) Value in power-down mode 3. XI input is at high level.

Note 6) The current consumption increases during power-down at higher temperatures.

23

YSS944/943/940

(4) DC Characteristics

Parameter

Symbol

V_IH1

V_IL1

V_IH2

V_IL2

V_OH

V_OL

I_OH

Condition

Min.

Typ.

Max.

VDD1

0.2VDD1

5.25

Unit

High level input voltage (1)

Low level input voltage (1)

High level input voltage (2)

Low level input voltage (2)

High level output voltage

Low level output voltage

High level output current

Low level output current

Input leakage current

XI pin

0.8VDD1

V

Input pin other than XI Note 1)

IOH = -1.0 mA, Note 2)

2.2

2.4

V

0.8

V

IOL = 1.0 mA,

Note 2)

0.4

-1.0

1.0

1

V

mA

µA

kΩ

pF

I_OL

Pin without pull-up resistor

-1

I_LI

Pull-up resistance

37

72

7

R_U

Input pin’s capacitance

C_I

Note 1) All input pins other than XI are tolerant of 5 V.

Note 2) Applies to all output pins other than XO. No rating for the XO output voltage level.

24

YSS944/943/940

(5) AC Characteristics

(a) Power up, Hardware Reset, and clock

No.

Parameter

nIC time 1

Symbol

Condition

Min.

Typ.

Max.

60

Unit

1

2

3

4

T_IC1

T_IC2

Figure 1) below

Figure 2) below

5

1

ms

µs

MHz

%

nIC time 2

XI clock frequency

XI clock duty

f_XIN

X_DUTY

12.288

40

Internal operating

clock cycle

5

6

T_CLK

1000/178.176

ns

Note 1)

0

1

s

Note 2)

Note 3)

Power ON time

T_V1V2

Note 1) When using recommended XI input and recommended PLL setting. The internal operating clock

frequency is 178.176 MHz.

Note 2) When Shortcut key barrier diode is not connected

The 3.3 V power supply (VDD1, AVDDR, AHVDD, and AHVDDG) should be started before the

1.2 V power supply (VDD2 and DVDD).

Note 3) When Shortcut key barrier diode is connected

Insert a Shortcut key barrier diode with forward voltage of 0.4 V or less between the 3.3 V power

supply (VDD1, AVDDR, AHVDD, and AHVDDG) and 1.2 V power supply (VDD2 and DVDD)

(cathode is VDD1 and anode is VDD2).

The 3.3 V power supply and 1.2 V power supply can be started in either order.

Note 4) The time interval of power ON or OFF between 3.3V power supply and 1.2V power supply must

be within one second. Only one power keep on supplying, LSI would be damaged.

1)At power-on

6

1

VDD1, AVDDR,

AHVDD, AHVDDG

VDD2,

DVDD

XI

nIC

• If a crystal oscillator is connected, this includes the time between power supply stabilization and

oscillator stabilization.

• Turn on the power when nIC is at low level.

2)In normal operation mode

2

nIC

• The XI input and power supply must be stabilized.

• If XI oscillation has stopped during initialization in power-down mode, time is required to stabilize

the oscillation.

25

YSS944/943/940

(b)Microprocessor interface

No.

Parameter

MISCK cycle

Symbol Condition

Min.

160

Typ.

Max.

Unit

1

2

3

4

5

6

7

8

9

tcc

tcr

tcf

tch

tcl

ns

MISCK rise time

20

MISCK fall time

MISCK high level time

MISCK low level time

nMICS and MISI setup time

nMICS and MISI hold time

MISO output delay time

MISO output High-Z time

80

10

tset

Note 1)

thold

tdelay CL = 50pF

tz CL = 50pF

50

20

Note 1) Satisfy the setup time/hold time (vs. MISCK) on starting/ending transfer, with nMICS = L.

nMICS

1

6

3

2

7

5

4

MISCK

MISI

6

7

8

9

High-Z

MISO

26

YSS944/943/940

(c)Audio interface

1) SDIMCK

No.

Parameter

Symbol Condition

Min.

Typ.

50

Max.

25

Unit

1

2

3

4

SDIMCK input frequency

SDIMCK duty

f_IMCK

d_IMCK

t_IMR

MHz

%

SDIMCK rise time

SDIMCK fall time

10

ns

t_IMF

ns

1

2

SDIMCK

3

4

2) SDOMCK

No.

Parameter

Symbol Condition

f_OMCK

Min.

Typ.

50

Max.

25

Unit

1

2

3

4

SDOMCK output frequency

SDOMCK duty

MHz

%

d_OMCK

t_OMR

Note 1)

SDOMCK rise time

SDOMCK fall time

CL = 50pF

10

ns

t_OMF

ns

Note 1) When MSEL[1:0] = 00 has been set and “through” has been selected for SDIMCK, the SDOMCK

duty factor is affected by the SDIMCK duty factor.

1

2

SDOMCK

3

4

27

YSS944/943/940

3) SDIBCK, SDIWCK, SDI3 to SDI0 (slave operation)

No.

Parameter

Symbol Condition

f_IBCK

Min.

Typ.

50

Max.

12.5

Unit

1

2

3

4

5

6

SDIBCK input frequency

SDIBCK duty

MHz

%

d_IBCK

t_IBR

Note 1)

SDIBCK rise time

10

ns

SDIBCK fall time

t_IBF

ns

SDIWCK and SDI3-0 setup time

SDIWCK and SDI3-0 hold time

t_IWS

t_IWH

10

ns

Note 1) The polarity of SDIBCK can be changed by SDIBP. In the figure below, SDIBP = 0.

1

3

4

2

SDIBCK

SDIWCK

SDI3-0

5

6

4) SDOBCK, SDOWCK, SDO3 to SDO0 (slave operation)

No.

Parameter

Symbol Condition

f_OBCK

Min.

Typ.

50

Max.

12.5

Unit

1

2

3

4

5

6

7

SDOBCK input frequency

SDOBCK duty

MHz

%

d_OBCK

t_OBR

Note 1)

SDOBCK rise time

10

ns

SDOBCK fall time

t_OBF

ns

SDOWCK setup time

SDOWCK hold time

SDO3-0 output delay time

t_OWS

t_OWH

t_ODLY

10

ns

CL = 50pF

30

ns

Note 1) The polarity of SDOBCK can be changed by SDOBP. In the figure below, SDOBP = 0.

1

3

4

2

SDOBCK

SDOWCK

SDO3-0

5

6

7

28

YSS944/943/940

5) SDOBCK, SDOWCK, SDO3 to SDO0 (master operation)

No.

Parameter

Symbol

Condition

Min.

Typ.

50

Max.

12.5

Unit

SDOBCK output frequency

SDOBCK output duty factor

1

2

3

4

f_OBCK

d_OBCK

t_OBR

MHz

%

Note 2)

Notes 1 and 3)

CL = 50 pF

10

ns

SDOBCK rise time

SDOBCK fall time

t_OBF

ns

SDOWCK, SDO3 to SDO0

Output delay time

5

6

t_ODLY

CL = 50 pF

-15

0

15

25

ns

CL = 50 pF

Note 4)

SDIBCK → SDOBCK

Output delay time

t_OBDLY

Note 1) The output polarity of SDIBCK and SDOBCK can be changed by DSIBP and DSOBP. In the

figure below, SDOBP = SDOBP = 0.

Note 2) Although output divided from SDIMCK can be selected for SDOBCK via WBSEL[2:0], operation

is not guaranteed if SDIMCK’s frequency exceeds the range noted above.

Note 3) When “SDIBCK through” has been selected (WBSEL[2:0] = 00), the SDDBCK output duty factor

is affected by the SDIBCK duty factor.

Note 4) When “SDIBCK through” has been selected (WBSEL[2:0] = 00).

6

SDIBCK

1

3

4

2

SDOBCK

SDOWCK

SDO3-0

5

29

YSS944/943/940

(d)External memory interface

When EM_CYC = c, EM_WEH = w, and EM_OEH = o, the timing is as described below.

1) Read

No.

Parameter

Symbol Condition

t_RCYCCL = 20 pF

Min.

Typ.

t_{ASR+ REP+ AHR}

Max.

Unit

1

2

3

4

5

6

7

8

Read cycle time

t

ns

CL = 20 pF

Address access time

nMEMOE access time

Data setup time

t_AA

t_EAC

t_DSR

t_DHR

T_CLK×(2c+3)-25

T_CLK×(2c+2)-25

25

0

Data hold time

Address setup time

Address hold time

nMEMOE pulse width

t_ASRCL = 20 pF

t_AHRCL = 20 pF

t_REPCL = 20 pF

T_CLK×1

T_CLK×(2^o+1)

T_CLK×(2c+2)

1

MEMA18-0

nMEMCE

nMEMOE

nMEMWE

MEMD7-0

6

8

7

3

2

4

5

Read

Data

30

YSS944/943/940

2) Write

No.

1

Parameter

Write cycle time

Data setup time

Symbol Condition

t_WCYCCL = 20 pF

Min.

Typ.

Max.

Unit

ns

T_CLK×(2c+5+2w)

T_CLK×(w+1)

T_CLK×(w+2)

T_CLK×(w+1)

T_CLK×(w+2)

T_CLK×(2c+2)

2

t_DSW

t_DHW

t_ASW

t_AHW

t_WEP

CL = 20 pF

0

ns

3

Data hold time

ns

4

Address setup time

Address hold time

nMEMWE pulse width

ns

5

ns

6

ns

1

MEMA18-0

nMEMCE

nMEMOE

nMEMWE

MEMD7-0

4

2

6

5

3

Write Data

31

YSS944/943/940

Example of System Configuration

The YSS944/943/940 is connected to CODEC (ADC/DAC) or DIR/DIT via the audio interface.

The YSS944/943/940 is connected to a microprocessor for control via the microcomputer interface.

External memory (SRAM) is an option when using the input/output delay function. The YSS944/943/940 can

be used with only the internal RAM (without connecting external memory).

Microprocessor

nIC

Reset

SDIMCK

SDIBCK

SDIWCK

SDOMCK

SDOBCK

SDOWCK

Digital output

Digital input

DIR

DIT

ADAMB

SDI0

SDI1

SDO0

Analog output

Analog input

SDO1

SDO2

SDO3

(YSS944/943/941)

DAC

ADC

12.288MHz

(SRAM)

optional

32

YSS944/943/940

Package Dimensions

The shape of the molded corner may slightly differ from the

shape in this diagram.

The figure in the parentheses ( ) should be used as a reference.

Plastic body dimensions do not include resin burr.

UNIT: mm

The storage and soldering of LSIs for surface mounting need special consideration.

For detailed information, please contact your local Yamaha agent

33

YSS944/943/940


型号：	YSS940
厂家：	YAMAHA CORPORATION
描述：	ADAMB Advanced Digital Audio Multi channel decode processor ADAMB先进的数字音频多声道解码处理器
文件：	总34页 (文件大小：899K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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