YTD428_07 [YAMAHA]
IDSU ISDN DSU for Terminal Equipment; IDSU ISDN DSU的终端设备
| 型号： | YTD428_07 |
| 厂家： | 
YAMAHA CORPORATION |
| 描述： | IDSU ISDN DSU for Terminal Equipment |
| 文件： | 总28页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
YTD428
APPLICATION MANUAL
IDSU
ISDN DSU for Terminal Equipment
YTD428 APPLICATION MANUAL
CATALOG No.: LSI-6TD428A32
2005.1
CONTENTS
- 1 -
Contents
1. INTRODUCTION.....................................................................................2
1.1 Features ................................................................................................................................ 3
2. BLOCK DIAGRAM ..................................................................................4
2.1 Internal Block Diagram.......................................................................................................... 4
2.2 DSU Configuration Example ................................................................................................. 5
3. PIN DESCRIPTIONS ..............................................................................7
3.1 Pin Assignments.................................................................................................................... 7
3.2 Pin Functions ........................................................................................................................ 8
4. DETAILS OF FUNCTIONS....................................................................13
4.1 U Reference Point Section .................................................................................................. 13
4.2 Circuit Termination / Line Termination Section .................................................................... 13
4.3 Interface Switch Section...................................................................................................... 14
4.4 T Reference Interface Section ............................................................................................ 15
5. ELECTRICAL CHARACTERISTICS .....................................................16
5.1 Absolute Maximum Ratings................................................................................................. 16
5.2 Recommended Operating Conditions ................................................................................. 16
5.3 DC Characteristics .............................................................................................................. 17
5.4 AC Characteristics............................................................................................................... 18
6. PIN DESCRIPTIONS ............................................................................22
REFERENCE CIRCUIT ............................................................................23
- 2 -
INTRODUCTION
1. INTRODUCTION
YTD428 is a LSI which provides the ISDN subscriber interface (two-wire time compression
multiplexing operation) and the NT side of the ISDN Basic Rate user-network interface function
(digital four-wire time-division full-duplex operation). It is capable of providing the electric
characteristics conforming to TTC Standard JT-I430 and JT-G961.
YTD428 incorporates the circuit termination and line termination functions on a single chip
allowing the user to easily configure a DSU (Digital Service Unit) that consumes small amount of
power at a minimal cost.
In addition, a TTL interface is provided at the T reference point (layer 1 level). This feature is
especially effective when combined with YAMAHA's ISDN LSI for S/T reference point interface,
YTD423 or YTD418. It allows considerable cost reduction on parts around the pulse transformer
when constructing a device with a built-in DSU.
The driver/receiver section of the T reference point interface can be separated from the DSU section
and be used independently. The user can enable or disable this feature as necessary.
INTRODUCTION
- 3 -
1.1 Features
ꢀꢀCircuit Termination Section
ꢀ
ꢀConforms to TTC Standard JT-I430 and JT-G961
ꢀ
ꢀDigital four-wire time-division full-duplex operation
ꢀ
ꢀTwo-wire time compression multiplexing operation
ꢀ
ꢀTransmission rate at U reference point: 320 kbit/s, at T reference point: 192 kbit/s
ꢀ
ꢀFrame assembling and disassembling function
ꢀ
ꢀState transition control
ꢀ
ꢀLoopback function
ꢀ
ꢀT reference point timing control
(switch between short passive bus / extended passive bus, point-to-point)
ꢀ
ꢀU reference point driver control
ꢀꢀLine Termination Section
ꢀ
ꢀConforms to TTC Standard JT-G961
ꢀ
f
ꢀ equalizer
ꢀ
ꢀBridged tap equalizer
ꢀꢀT Reference Point Interface Section
ꢀ
ꢀThe T reference point driver / receiver section can be separated from DSU section, and use
independently (TE mode). The user can enable or disable this feature as necessary.
ꢀꢀOthers
ꢀ
ꢀ+5 V single power supply
ꢀ
ꢀLow power consumption
ꢀ
ꢀ100 pin SQFP
- 4 -
BLOCK DIAGRAM
2. BLOCK DIAGRAM
2.1 Internal Block Diagram
U ref. pt. I/F section
YTD428
Variable
Amplifier
ADC
Peak hold
T ref. pt. I/F section
CT/LT section
T ref. pt.
driver
CT block
LT block
Interface
switch section
U ref. pt.
driver control
T ref. pt.
receiver
TTL I/F
CT : Circuit Termination
LT : Line Termination
S/T ref. pt. LSI
YTD418 or
YTD423
BLOCK DIAGRAM
- 5 -
2.2 DSU Configuration Example
YTD428 incorporates the circuit termination, line termination, T reference point interface and U
reference point interface functions on a single chip allowing the user to easily configure a DSU that
consumes small amount of power at a minimal cost. The user can select from the two types of
configurations. One is the general configuration in which a transformer is used at the T reference
point interface. The other is a configuration in which a TTL interface is used to directly connect to
the T reference point LSI.
ꢀꢀConfiguration example of a general DSU
Various functions are incorporated on a single chip allowing the user to create a low power-consuming
product at a low cost.
Layer 3 info.
Bch data
T ref. pt.
DSU
RA / RB
YM7405 or
YTD410
for S/T ref. pt.
included driver/receiver
for S/T ref. pt.
YTD428
L1
L2
TA / TB
U ref. pt. driver
Call control
circuit
- 6 -
BLOCK DIAGRAM
ꢀꢀConfiguration example of a device with a built-in DSU that uses an I.430 TTL
interface at the T ref. pt.
When using YTD428 with YAMAHA'S S/T reference point interface LSI to create a device with a built-in
DSU, they can be connected directly through the I.430 TTL interface. This results in a reduction of pulse
transformer parts.
DSU section
YTD428
RA / RB
CT
and
LT
U ref.
pt. I/F
T ref.
pt. I/F
I/F
switch
L1
L2
TA / TB
U ref. pt.
driver
Call control
circuit
I.430 TTL I/F
(No transformer is requied)
YTD418 or
YTD423
Layer 3 information
(Bch data)
ꢀꢀExample of using T reference point driver / receiver section independently
By setting the Interface switch, the drive / receiver of the T reference point interface section can be separated
from the circuit termination (CT) and line termination (LT) section and be used independently.
The user can enable or disable this feature as necessary.
DSU section
YTD428
RA / RB
CT
and
LT
U ref.
pt. I/F
T ref.
pt. I/F
I/F
switch
L1
L2
TA / TB
U ref. pt.
driver
Call control
circuit
TTL I/F
(No transformer is required)
YTD418 or
YTD423
Layer 3 information
(Bch data)
PIN DESCRIPTIONS
- 7 -
3. PIN DESCRIPTIONS
3.1 Pin Assignments
TEST4
TEST5
TEST6
TEST7
LOOP2A
LPSW
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AVSS
2
RX
LO2
AVDD
LO1
CX1
AVDD
LI2
CX2
LICT
LI1
2
2
TEST8
DVSS
CLK1536
DVDD
CLK4K
CLK256K
CLK200
CLK400
DVSS
AVSS
AVSS
SXA
2
1
YTD428-S
100pin SQFP
SGBP
SGB
RXS
EXID
TEST9
AVDD
1
TEST10
TEST11
TEST12
TEST13
TEST14
TEST15
DVDD
SGA
RUC
RXU2
SGR
AVSS
1
RXU1
ATEO
TEST16
- 8 -
PIN DESCRIPTIONS
3.2 Pin Functions
ꢀꢀCommon Section
Pin No.
3, 13, 96
14, 25
Pin Name
AVSS
AVSS
I/O
Function
Remarks
1
GND Analog ground 1 (U ref. pt.)
GND Analog ground 2 (T ref. pt.)
2
26, 43, 58,
65, 83, 95
DVSS
AVDD
GND Digital ground
8, 99
1
PWR +5 V ± 5 % analog power supply 1 (U ref. pt.)
PWR +5 V ± 5 % analog power supply 2 (T ref. pt.)
19, 22
AVDD
2
31, 50, 60
74, 88
DVDD
PWR +5 V ± 5 % digital power supply
59
CLK1536
IN
IN
System clock (15.36 MHz ± 50 ppm or less)
Power supply monitor of the equipment on the T ref. pt. side
"H": Power supply OFF
41
POWMON
"L": Power supply ON
Haerdware reset
Apply the reset pulse for 1 ms or more after the clock oscillation to operate
hardware reset. If the pulse is less than 1 ms, the operation is
unpredictable.
Hardware reset is required when all following conditions are met.
1. operated by local power
42
RESET
IN
2. LPSEL = "H"
3. U ref. pt. polarity is positive.
Note
Connect input pins that are not normally used to the power supply pin or ground pin.
In the same fashion, do not leave pins with pull-up resistor open. Connect them to the power supply pin or ground pin.
PIN DESCRIPTIONS
- 9 -
ꢀꢀMode Setting Section
Pin No.
Pin Name
I/O
Function
Remarks
HTD, LTD pulse polarity setting
"H": positive polarity
"L": negative polarity
with pull-up
resistor
33
TDP
IN
HRD, LRD pulse polarity setting
"H": positive polarity
"L": negative polarity
with pull-up
resistor
34
35
RDP
IN
IN
T ref. pt. transmit signal setting
"H": HRD, LRD pins normal output
"L": HRD, LRD pins open drain
with pull-up
resistor
ODSEL
T ref. pt. receive data sampling timing setting
"H": fixed timing (short passive bus)
When T ref. pt. data sampling mode is set to "automatic" (TSMPAUT = "L"),
set this pin to "H".
with pull-up
resistor
36
TSMPSEL
IN
"L": adaptive timing (point-to-point connection, extended passive bus)
T ref. pt. data sampling mode setting
"H": manual setting (TSMPSEL pin state is valid)
"L": automatic setting (set TSMPSEL pin to "H")
with pull-up
resistor
37
38
39
44
TSMPAUT
MULTI
IN
IN
IN
IN
T ref. pt. multiframe support setting
"H": support multiframe
"L": do not support multiframe
with pull-up
resistor
T ref. pt. mode setting
"H": NT mode
"L": TE mode (T ref. pt. I/F block operates independently of DSU block)
with pull-up
resistor
NTSEL
Power feeding mode setting
"H": phantom power feeding mode
"L": local power fedding mode
with pull-up
resistor
LOCAL
LPSW signal setting
"H": call only extended loopback 2A
"L": normal call, call by extended loopback 2A
(loop control signal at local power feeding mode)
with pull-up
resistor
45
LPSEL
IN
Loopback setting
"H": transmit ID1 = "1" (correspond to extended loopback 2)
"L": transmit ID1 = "0" (loopback 2A operates at AP = "1")
with pull-up
resistor
66
82
EXID
IN
IN
Clock output setting
"H": do not output clock
"L": output clock
with pull-up
resistor
CLKSEL
Note 1 When not using TTL interface, set HTD, LTD pins as bellow.
When TDP = “H”, set HTD, LTD = “L”
When TDP = “L”, set HTD, LTD = “H”
Note 2 When using the YTD428 on a terminal with built-in DSU, it is recommended that fixed timing be selected for the sample
timing of T reference point receive data (TSMPSEL=“H” and TSMPAUT=“H”). This is because the bus distribution form
becomes a short passive bus in this case.
Note 3 When using NTSEL, external terminating resistor setting is required.
When NTSEL = “H”, terminating resistor is required.
When NTSEL = “L”, remove terminating resistor as necessary.
Note 4 Set LOCAL = “L” when LPSEL = “L” or CLKSEL = “L”.
- 10 -
PIN DESCRIPTIONS
ꢀꢀT Reference Point Section
Pin No.
15
Pin Name
LI1
I/O
Function
Remarks
IN
S/T line input
16
LICT
OUT S/T line reference source output
Connecting external capacitor and resistor
17
CX2
-
0.1 µF capacitor and 1 MΩ resistor are to be connected across the CX2 pin
and the AVSS2 pin.
18
20
LI2
IN
-
S/T line input
Connecting external capacitor
22 µF capacitor is to be connected across the CX1 pin and the AVSS2 pin.
CX1
21
23
LO1
LO2
OUT S/T line output
OUT S/T line output
Connecting external resistor
33 kΩ resistor is to be connected across the RX pin and the AVSS2 pin .
24
RX
-
Note 1 When not using T ref. pt. analog interface, set these pins as bellow.
The LI1, LI2 and LICT pins are to be connected each other (short).
0.1 µF capacitor is to be connected across the LICT pin and the AVSS2 pin.
Note 2 About how to connect external capacitor and resistor, refer to “REFERENCE CIRCUIT” .
Pin No.
Pin Name
I/O
Function
NTSEL = "H": DSU transmit data (+)
Remarks
27
HRD
OUT
NTSEL = "L": TE receive data (+)
NTSEL = "H": DSU transmit data (--)
NTSEL = "L": TE receive data (--)
28
29
30
LRD
HTD
LTD
OUT
IN
NTSEL = "H": DSU receive data (+)
NTSEL = "L": TE transmit data (+)
NTSEL = "H": DSU receive data (--)
NTSEL = "L": TE transmit data (--)
IN
Note
When not using TTL interface, set HTD, LTD pins as bellow.
When TDP = “H”, set HTD, LTD = “L”
When TDP = “L”, set HTD, LTD = “H”
PIN DESCRIPTIONS
- 11 -
ꢀꢀU Reference Point Section
Pin No.
Pin Name
RXU1
SGR
I/O
Function
Remarks
2
4
5
6
IN
Receive signal input 1
OUT Analog signal reference output
RXU2
RUC
IN
-
Receive signal input 2
0.1 µF capacitor is to be connected across the RUC pin and the AVSS1 pin.
0.0047 µF (10%) capacitor is to be connected across the SGA pin and the
SGR pin.
7
9
SGA
RXS
SGB
-
-
-
0.0022 µF (10%) capacitor is to be connected across the RXS pin and the
SGR pin.
0.015 µF (10%) capacitor is to be connected across the SGB pin and the
SGR pin.
10
0.15 µF (10%) capacitor is to be connected across the SGBP pin and the
SGR pin.
11
12
97
SGBP
SXA
VRB
-
-
This pin must be left unconnected.
ADC reference power supply (low voltage)
0.1 µF capacitor is to be connected across the VRB pin and the AVSS1 pin.
OUT
ADC reference power supply (high voltage)
0.1 µF capacitor is to be connected across the VRT pin and the AVSS1 pin.
98
VRT
OUT
Pin No.
84
Pin Name
UDM0
UDM1
UDP0
I/O
Function
Remarks
OUT Negative pulse driving signal
OUT Negative pulse driving signal
OUT Positive pulse driving signal
OUT Positive pulse driving signal
85
86
87
UDP1
Pin No.
Pin Name
I/O
Function
Remarks
U ref. pt. polarity
When LPSEL = "H", set this pin to "H".
When LPSEL = "L", set this pin as bellow.
"L": positive polarity
40
REV
IN
"H": reverse polatity
"L": normal operation
"H": indicating loopbak 2
55
56
LOOP2A
LPSW
OUT
Call control signal
OUT "L": normal operation
"H": call initiate request
- 12 -
PIN DESCRIPTIONS
ꢀꢀClock Output Pins
Pin No.
Pin Name
I/O
Function
192 kHz clock (usually fixed to "L")
Remarks
Note 1, 2
32
CLK192K
OUT
Output clock when CLKSEL = "L" and LOCAL = "L".
4 kHz clock (usually fixed to "L")
Output clock when CLKSEL = "L" and LOCAL = "L".
61
62
63
64
CLK4K
CLK256K
CLK200
CLK400
OUT
OUT
OUT
OUT
Note 1, 2
Note 1
256 kHz clock (usually fixed to "L")
Output clock when CLKSEL = "L" and LOCAL = "L".
200 Hz clock (usually fixed to "L")
Output clock when CLKSEL = "L".
Note 1, 2
Note 1, 2
400 Hz clock (usually fixed to "L")
Output clock when CLKSEL = "L".
Note 1 Outputs “L” when the YTD428 is set to not output the clock. In addition, if the YTD428 is not synchronized to the network,
the frequency of the output clock is not guaranteed.
Note 2 Clock is output when REV = “H.”
ꢀꢀTest Pins
These are for LSI examinations, and not used in normal operation.
Be sure that each pin is set as bellow.
Pin No.
Pin Name
I/O
Function
Remarks
46, 48, 49,
51 ~ 54,
57, 67,
TEST0,
2 ~ 9,
21, 22
Test pin
Usually fixed to "H".
with pull-up
resistor
IN
80, 81
TEST
23, 25 ~ 27
Test pin
Usually fixed to "L".
89, 91 ~ 93
94
IN
IN
Test pin
Usually fixed to "H".
TEST28
TEST1,
16 ~ 19
Test pin
Usually pull up to "H".
with pull-up
resistor
47, 75 ~ 78
68, 69, 90
70 ~ 73
79
I/O
I/O
I/O
OUT
IN
TEST10,
11, 24
Test pin
Usually pull up to "H".
TEST
12 ~ 15
Test pin
Usually fixed to "L".
Test pin
TEST20
ATEI
This pin must be left unconnected.
Test pin
Usually fixed to "L".
100
Test pin
Usually pulled up to "H".
1
ATEO
I/O
DETAILS OF FUNCTIONS
- 13 -
4. DETAILS OF FUNCTIONS
4.1 U Reference Point Section
ꢀꢀVariable Amplifier
This block amplifies the receive signal amplitude to the maximum dynamic range.
ꢀꢀADC
This block makes an A/D conversion of the received signal and transfers it to the line termination block.
ꢀꢀPeak Hold
This block is performed during the initial training so that the gain of the Variable amplifier block is set to
make best communication condition.
4.2 Circuit Termination / Line Termination Section
ꢀꢀCircuit Termination Block
The following functions provide the necessary functions for TTC Standard JT-G961 (TCM operation) and the
NT function described in TTC Standard JT-I430.
ꢀ
Rate adaptation and frame assembly / disassembly at the U and T reference points
ꢀ
State transition control
ꢀ
U reference point drive control
ꢀ
T reference point receive timing control
ꢀ
Loopback control
YTD428 supports loopback 2 and loopback C for testing and maintenance.
These loopback tests are under local switch control.
ꢀꢀLine Termination Block
The line termination provides the f equalization which compensates the DLL (Digital Local Line) loss and the
amplitude distortion, and the BT equalization which compensates the waveform distortion caused by the
bridged tap.
- 14 -
DETAILS OF FUNCTIONS
4.3 Interface Switch Section
Normally, this section connects T I/F section with CT/LT section to provide DSU function (NTSEL = “H”).
By setting this section, the driver/receiver function of the T I/F section can be separated from the CT/LT
section and be used independently (NTSEL = “L”).
For example, it is useful under such a situation that there are some terminals which have DSU function on
the same S/T line.
DSU section
YTD428
RA / RB
CT
and
LT
U ref.
pt. I/F
T ref.
pt. I/F
I/F
switch
L1
L2
TA / TB
U ref. pt.
driver
Call control
circuit
TTL I/F
(No transformer is required)
YTD418 or
YTD423
Layer 3 information
(Bch data)
Figure 4.1 Image Of Using T Ref. Pt. I/F Drive/Receiver Independently
In case of using NTSEL = "L" (TE mode), the signals of TA/TB and RA/RB should be reversed by switches
or other devices. Because S/T bus signals that are connected to TA, TB, RA and RB pin are different between
using YTD428 as DSU (NTSEL = "H") and S/T terminal (NTSEL = "L").
Generally speaking, the terminal resistors are only mounted on the nearest terminal from DSU and other
terminals that are connected with the same bus don't require the terminal resistors. Therefore, it is useful that
switches which can control ON/OFF of the terminal resistors are provided on the equipment.
DETAILS OF FUNCTIONS
- 15 -
4.4 T Reference Interface Section
ꢀꢀReference Power Supply Block
This block provides the electric power to supply for the receiver block and the driver block.
ꢀꢀReceiver Block
The receiver block receives signal from the S/T bus through the external pulse transformer and converts it to
the logic level signal.
The voltage threshold level for he receiver is properly adapted automatically according to the receiving signal
level.
192kHz
+ 0
I.430 receive signal
(AMI)
(RA/RB)
- 0
HRD pin
(TTL level)
(NRZ)
LRD pin
(TTL level)
(NRZ)
Figure 4.2 Receive Signal Logic (RDP = “H”, NTSEL = “L”)
ꢀꢀ Driver Block
The driver block drives the 2:1 turn ratio transformer according to the logic level transmitting signal.
HTD pin
(TTL level)
(NRZ)
LTD pin
(TTL level)
(NRZ)
192kHz
+ 0
I.430 transmit signal
(AMI)
(TA/TB)
- 0
Figure 4.3 Transmit Signal Logic (TDP = “H”, NTSEL = “L”)
- 16 -
ELECTRICAL CHARACTERISTICS
5. ELECTRICAL CHARACTERISTICS
5.1 Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Symbol
Min.
Max
Units
VDD
V
SS - 0.3
SS - 0.3
- 50
V
SS + 7.0
V
VI
V
V
DD + 0.3
V
Storage Temperature
T
stg
+ 125
° C
5.2 Recommended Operating Conditions
Parameter
Symbol
Range
Supply Voltage
V
DD
5.0 V ± 5 %
-20 ~ +70 ° C
Operating Temperature
T
op
ELECTRICAL CHARACTERISTICS
- 17 -
5.3 DC Characteristics
(DVDD = AVDD = 5 .0V, DVSS = AVSS = 0.0 V, Operating Temperature: Top = 25 ºC)
Parameter
Symbol
Condition
Note 1
Min.
Typ.
Max.
Units
Analog Output Allowable
Load Impedance
Z
O
30
kΩ
Analog Receive Buffer
Input Impedance
Z
i1
Note 2
Note 3
10
MΩ
Analog Signal Reference
Voltage
VSG
2.45
2.50
2.55
V
Self-Bias VRT
ADC
V
RT
RB
Note 4
Note 5
0.7AVDD - 0.1
0.3AVDD - 0.1
0.7AVDD
0.3AVDD
0.7AVDD + 0.1
0.3AVDD + 0.1
V
V
Self-Bias VRB
V
Note 1 With respect to SGR, SXA pins.
Note 2 With respect to RXU1 and RXU2 pins.
Note 3 Set SGR pin to open.
Note 4 With respect to VRT pin.
Note 5 With respect to VRB pin.
(DVDD = AVDD = 5.0 ± 5% V, Top = -20 ~ 70 ºC)
Parameter
Symbol Condition
Min.
2.2
Typ.
Max.
Units
V
V
V
V
V
V
IH
IH
IL
IL
IH
IL
(Note 1)
(Note 2)
(Note 1)
(Note 2)
(Note 3)
(Note 3)
(Note 4)
(Note 5)
(Note 4)
(Note 5)
(Note 6)
V
V
V
V
V
V
V
V
V
V
V
High Level Input Voltage (TTL)
3.0
0.8
0.8
Low level Input Voltage (TTL)
High Level Input Voltage (CMOS)
Low Level Input Voltage (COMS)
3.5
1.0
DVDD - 1.0
DVDD - 1.0
High Level Output Voltage (TTL)
Low Level Output Voltage (TTL)
VOH
DVSS + 0.4
DVSS + 0.4
DVSS + 0.4
10
V
OL
OL
Low Level Output Voltage (Open-D)
Leak Current
V
IL
-10
-10
µA
µA
mA
Idle Condition Leak Current
Power Supply Current
ILZ
10
I
DD
(Note 7)
36
Note 1 With respect to the digital pins other than RESET, POWDET, CLK1536 and TEST23 ~ 28 pins
Note 2 With respect to RESET, POWDET pins
Note 3 With respect to CLK1536, TEST23 ~ 28 pins
Note 4 With respect to the pin other than HRD, LRD pins
Test condition: Output Current "H" level (IOH) = -0.2 mA, Output Current "L" level (IOL) = 1.2 mA
Note 5 With respect to HRD, LRD pins (when ODSEL = "H"), Test condition: IOH = -0.2 mA, IOL = 1.2 mA
Note 6 With respect to HRD, LRD pins (when ODSEL = "L"),
Note 7 When using T ref. pt. analog interface
Test condition: IOL = 1.2 mA
- 18 -
ELECTRICAL CHARACTERISTICS
5.4 AC Characteristics
ꢀꢀT Reference Point Receive Characteristic (NT mode)
(VDD = 5.0 ± 5% V , Top = -20 ~ 70 °C, Load Capacity: CL = 50 pF)
Parameter
Transmit Pulse Width
Receive Pulse Width
Rise Time
Symbol Condition
Min.
Typ.
5.208
5.208
Max.
Units
µs
t
TPW
RPW
PR
PF
5.00
5.40
t
µs
t
260
30
ns
Fall Time
t
ns
t
t
TRD
TRD
Note 1
Note 2
10.0
10.0
14.0
42.0
µs
Phase Diffierence between
Tx and Rx signals
µs
Phase Difference between
Rx signals
Note 2,
Note 3
t
PH
2.0
µs
Note 1 With respect to using the Fixed timing
Note 2 With respect to using the Adaptive timing
Note 3 This value shows the difference between two terminals which are connected with bus system.
t
TPW
2.0 V
0.8 V
HRD
LRD
F
t
t
TPW
2.0 V
0.8 V
L
Transmit data slot
Receive data slot
FD
t
RPW
t
TRD
2.4 V
0.4 V
HTD
LTD
F
t
RPW
2.4 V
0.4 V
L
t
PR
t
PF
HTD/LTD
(closest terminal)
t
PH
Note 1
HTD/LTD
(farthest terminal)
Note 2
Note 1 Indicates the terminal that is connected closest from the DSU. The signal from this terminal
reaches the DSU the fastest.
Note 2 Indicates the terminal that is connected farthest from the DSU. The signal from this terminal
reaches the DSU the slowest.
Figure 5.1 Timing At T Ref. Pt. Interface
ELECTRICAL CHARACTERISTICS
- 19 -
ꢀꢀT Reference Point Receive Characteristic (TE mode)
(VDD = 5.0 ± 5% V, Top = -20 ~ 70 °C, CL = 50 pF)
Parameter
Symbol Condition
Min.
Typ.
Max.
700
200
700
700
30
Units
ns
t
RDR
RDL
RDH
RDF
RR
RF
t
ns
Delay Time
t
ns
t
ns
Rise Time
Fall Time
t
Note 1
Note 2
ns
t
30
ns
Note 1 With respect to HRD, LRD pins (ODSEL = “H”)
Note 2 With respect to HRD, LRD pins
Note 3 Figure 5.2 shows the timing when RDP = “H”. When RDP = “L”, the output signal polarity from HRD and LRD pins
are inverted.
Receive signal (I)
0 V
(LI1 - LI2)
t
RDR
t
RDL
RF
t
RR
t
2.0V
HRD (O)
LRD (O)
0.8 V
t
RDH
RR
t
t
RDF
RF
t
2.0 V
0.8 V
Figure 5.2 Receive Timing
- 20 -
ELECTRICAL CHARACTERISTICS
ꢀ T Reference Point Transmit Characteristic (TE mode)
(VDD = 5.0 5% V, Top = -20 ~ 70 °C, CL = 50 pF)
Parameter
Symbol
Condition
Min.
4.95
0
Typ.
Max.
5.45
260
260
30
Units
µs
ns
HTD, LTD Pulse Period
HTD, LTD Pulse Gap
HTD, LTD Rise Time
HTD, LTD Fall Time
tSW
tG
AP
tSR
ns
tSF
ns
t
SRL
Note 1
Note 1
Note 1
Note 1
Note 1
490
1010
165
685
1010
ns
t
SRH
ns
Transmit Signal
Delay Time
t
SFH
SFL
DZ
ns
t
t
ns
Zero Cross Delay Time
S
ns
Note 1 Measuring with RL voltage drop as shown in Figure 5.4
Note 2 Figure 5.3 shows the timing when TDP = “H”. When TDP = “L”, the output signal polarity from HRD and LRD pins are
inverted.
t
SW
2.4 V
0.4 V
HTD (I)
LTD (I)
t
SR
t
SF
t
SW
t
GAP
2.4 V
0.4 V
t
t
SRH
SRL
t
SFL
SFH
t
SR
t
SF
SDZ
t
SFL
t
t
SRH
t
t
SFH
1.35 V
0.15 V
-0.15 V
-1.35 V
t
SRL
Transmit signal (O)
(LOI - LO2)
Figure 5.3 Transmit Timing
ELECTRICAL CHARACTERISTICS
- 21 -
100 Ω
HTD
LTD
LO1
LO2
R
O
YTD428
R
L
200 Ω
Transmit signal
Figure 5.4 Transmit Block Test Circuit
ꢀꢀDriver, Receiver I/O Impedance
Parameters
Symbol
Condition
LI1 - LI2
Min.
50
Typ.
Max.
Units
kΩ
Receiver Input Impedance
Driver Ouput Impedance
Driver Ouput Impedance
Z
LI
ZLO1
LO1 - LO2 (Note1)
LO1 - LO2 (Note2)
50
kΩ
Ω
Z
LO0
15
Note 1 When no pulse is output.
Note 2 When pulse is output.
- 22 -
PIN DESCRIPTIONS
6. PIN DESCRIPTIONS
REFERENCE CIRCUIT
- 23 -
REFERENCE CIRCUIT
The reference circuit using YTD428 is shown as bellow.
1S953 12
YTD428
R(1%)
LO1
1µ
1µ
R(1%)
A1
A1
2SJ278
LO2
LI1
UDM1
UDP1
2SJ278
TDK
NL322522T-3R3J
8.2k
8.2k
LI2
8(1%)
8(1%)
UDP0
UDM0
2SK2315
2SK2315
A2
RA
LICT
15(1W)
15(1W)
A1
A1
L2
L1
0.1µ
6
5
8
7
1
2
3
4
0.01µ(10%)
RX
CX1
CX2
33k
22µ
0.1µ
1M
100
KP15N14
560(1%)
560(1%)
RXU2
RXU1
RB
TA
1.8k(1%)
1.8k(1%)
FG
1µ/160V
VRYA15
A2
KP4N12
TDK
TRTEPC9.8-0319C
100
6
KP15N14
FG
SGA
RXS
SGB
SGBP
SGR
0.0047µ(10%)
0.0022µ(10%)
0.015µ(10%)
0.15µ(10%)
10k
TB
NTSEL
Varistor
Line activation
circuit
D
0.33µ(10%)
0.1µ
RUC
VRB
VRT
FG
HRD
LRD
HTD
LTD
HRD
LRD
HTD
LTD
0.1µ
0.1µ
I.430 TTL Interface
YTD418 or YTD423
A1
Line activation
circuit
CLK1536
RESET
LPSW
LOOP2A
CLK200
CLK400
CLK4K
CLK192K
CLK256K
SXA
CLK1536
RESET
Line activation
circuit
REV
TDP
RDP
TEST20
ODSEL
TSMPSEL
MULTI
EXID
CLKSEL
ATEO
TEST0,2-9,21,22
TEST1,16-19
TEST10,11,24
TEST28
10k
10k
10k
10k
10k
10k
10k
10k
10k
AVDD
2
1u
AVSS2
A2
11
5
3
AVDD
1
1u
AVSS1
POWMON
LOCAL
A1
LPSEL
TSMPAUT
ATEI
TEST12 - 15
TEST23, 25-27
DVDD
DVSS
1u
D
D
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