SFSL4.5MDB [YAMAR]
for DC-LIN Asynchronous Communication Over Noisy Lines; 对于DC -LIN异步通信在嘈杂的线路
| 型号： | SFSL4.5MDB |
| 厂家： | 
YAMAR ELECTRONICS LTD. |
| 描述： | for DC-LIN Asynchronous Communication Over Noisy Lines |
| 文件： | 总12页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Proprietary and Confidential Information of YAMAR Electronics Ltd.
SIG40 for DC-LIN
Asynchronous Communication
Over Noisy Lines
YAMAR
Preliminary Data Sheet
Electronics Ltd
This information is preliminary and may be changed without notice
1
GENERAL
The SIG40 is an innovative VLSI solution for digital communication over a single wire or a battery-
powered line for asynchronous LIN and UART protocols, using original multiplex digital signaling
technology. It provides a new economical physical communication layer for asynchronous protocols.
Since the SIG40 consists of CMOS technology, it can be economically integrated with other CMOS
applications such as micro controllers.
When implemented in a LIN network, the SIG40 replaces the LIN transceiver and the LIN Data wire. Its
57.6Kbps data rate triples the LIN transfer rate. The SIG40 saves node costs and increases the
network capacity. A sleep mode enables power saving. Wakeup messages on the DC line awaken
remote devices as required by the LIN protocol.
The SIG40 capability of communicating over battery-powered line as a new physical layer of the LIN
protocol is useful for a wide range of vehicular applications, such as doors, seats, mirrors, climate
control, lights etc. The SIG40 contains a host and LIN interface, modem, line driver and ceramic filter
interface.
The device features a unique Signaling technology to overcome the hostile communication conditions
of a vehicle battery line. It consists of a Signaling Modem, Signaling Coder/Decoder and a
Communication Controller overcoming the hostile environment over vehicle battery lines. Sleep mode
reduces the power consumption when there is no bus activity.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
HDO
INH
HDI
nSleep
HDC
nReset
Wake
InterfHop
VccPLL
MF0nF1
RxOn
TxOn
DTxO
Gnd
RxP
RxN
Vcc
OscIn
OscOut
GndPLL
Figure 1.1 - SIG40 Pin Diagram
@ 2006 Yamar Electronics Ltd.
www.yamar.com
1
DS-SIG40 R1.8
Tel: +972-3-5445294 Fax: +972-3-5445279
Proprietary and Confidential Information of YAMAR Electronics Ltd.
2
OVERVIEW
Signaling System
2.1
The SIG40 device is based on a patented Signaling technology. The device transmits and receives a
special signaling carrier, which can be differentiated from noise. The receiver receives the signaling
patterns, extracting them into the original bits. The rest of the spectrum is reserved for additional
communication channels over the same DC noisy lines.
2.2
Channels and Network
The SIG40 operates over one of two preset selectable channels (frequencies) using a single line such
as the vehicle's battery power line. Up to 16 devices can be connected to each of the channels over the
same line. Each of them can broadcast asynchronous data messages to other devices on the bus
according to the LIN protocol. The device is controlled by its host microprocessor through its UART.
Channel frequencies: 3.58MHz to 6.5MHz
19.2Kbps to 57.6Kbps.
See 3.3.9.
Data transfer rate:
Cable length:
2.3
The SIG40 Device
The SIG40 device is responsible to transfer messages to all devices over the line. The device handles
the communication physical layer and Interference detection. The device communicates with its host via
an asynchronous serial port for data transfer and device control. Figure 2.1 outlines the building blocks
of the SIG40 device.
H o s t In te rfa c e
S IG 4 0
H o s t I/F
P ro to c o l
T im in g
H a n d le r
&
S y n c h
S ig n a lin g
G e n e ra to r a n d
D e te c to r
P L L
P r o to c o l
C o n tr o lle r
S le e p
C o n tro l
M o d e m
In te rfe re n c e
D e te c to r
3 2 K
O s c illa to r
T o / F ro m L in e in te rfa c e
Figure 2.1 - SIG40 logical blocks
2.4
Protocol
The LIN protocol is based on a master device communicating with up to 15 slaves using half-duplex
UART data. The device is transparent to the LIN host while providing additional services for the link and
application layers with a built-in Interference detector and frequency management.
2.5
Power Management
Sleep Mode, controlled by the host, saves power by disabling most of the circuits.
During Sleep Mode, the device is switched On for a short period to detect wakeup messages from other
devices on the bus. If no activity is detected, the device is switched back to Sleep.
@ 2007 Yamar Electronics Ltd.
2
DS-SIG40 R1.8
Proprietary and Confidential Information of YAMAR Electronics Ltd.
3
SIG40 SIGNALS
The SIG40 Signals are divided into three main functions:
•
•
•
Host input / output
Line interface
Sleep mechanism
Figure 3.1 describes the interconnections between SIG40 its host, the ceramic filters and the DC line.
Ceramic
Filter
DC-Line
HDI
HDO
HDC
UART
TxOn
DTxO
HOST
LIN Controller
SIG40
Line
Interface
Wake
MF0nF1
nSleep
INH
RxOn
DRxP
InterfHop
Ceramic
Filter II
Crystal
Figure 3.1 - Interfacing the SIG40
Device signals are defined in table 3.1.
Table 3.1 - Device signals
Host I/O
signals
HDO
Line Interface
signals
Data Output
1
2
3
4
5
6
7
8
MF0nF1
OscOut
OscIn
RxN
F0/F1 selected Output
Crystal Output
10
12
13
15
16
18
19
20
INH
Inhibit operation Output
Data Input
HDI
Crystal Input
nSleep
HDC
Sleep Input
Rx Analog - Input
Rx Analog + Input
Transmit data Output
Transmit On Output
Receive On Output
Data/Command Input
Reset Input
RxP
nReset
Wake
InterfHop
DTxO
TxOn
RxOn
Wakeup Input
Allow Interference hopping Input
Power signals
Vcc
Power
14
17
11
9
Gnd
Power
GndPLL
VccPLL
Ground for PLL
Vcc for PLL
3.1
Host interface
Three lines are dedicated for Host data input / output and for command.
3.1.1
HDI
Data input signal to the SIG40. Transfer data from host to SIG40. When not in use should be pulled Up.
3.1.2
HDO
Data output signal from SIG40. Transfers received data to host.
3.1.3
HDC
Data/Command mode. When Low, enables read and write to internal registers. When not in use should
be pulled Up.
@ 2007 Yamar Electronics Ltd.
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Proprietary and Confidential Information of YAMAR Electronics Ltd.
3.2
Sleep Mechanism
Three signals are dedicated for Sleep wakeup mechanism
3.2.1 nSleep
Sleep control input from the host. This pin is high for normal operation, and low for Sleep Mode. When
not in use, this pin should be pulled Up.
3.2.2
Wake
Local wakeup input. Negative or positive edge wakes up the device. When not in use, this pin should be
pulled Up or Down.
3.2.3
INH
Inhibit output for enabling the host (or an external voltage regulator powering the host. This output is
LOW when in Sleep Mode, and HIGH in normal operation and after a wakeup event.
3.3
Line interface
Whenever a dual channel F0/F1 is required, the line interface is described in figure 3.2. It requires
addition analog switch such as FSA157 and two transistors for Tx and Rx drivers.
Ceramic
Filter F0
TxOn
MF0nF1
DC Line
Tx.
Driver
Tx.
Modulator
DTxO
RxOn
RxP
Data Out
RxN
Rx.
Demodulator
Rx.
Buffer
Ceramic
Figure 3.2 – DC - line interface block diagram
The line interface signals are:
3.3.1
DTxO
Modulated transmit signal output
3.3.2
TxOn
High when the device is transmitting
3.3.3
MF0nF1
Output signal indicates the selected channel. F0=”High”, F1= “Low”.
3.3.4
RxP
Comparator’s positive pin input signal. It swings around RxN.
3.3.5
RxN
Comparator’s negative pin input signal. Its value should be about Vcc/2.
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Proprietary and Confidential Information of YAMAR Electronics Ltd.
3.3.6
RxOn
High when the device is in receive mode.
3.3.7
Power Signals
There are two sets of power signals, Vcc, Gnd and VccPLL, GndPLL. See 3.6
Analog Interface
C104
0.1u
TxOn
VCC
VCC
R59
100K 100K
Ceramic Filter
VCC
R22
1M
R23 VCC
3.3K
Q1
R58
R8
1M
R7
1M
Protection Network
VCC
C7
1n
SIG40
RxOn
U1
JP1
PZT2222
C3
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HDO
INH
HDI
nSleep
HDC
nReset
Wake
InterfHop
VccPLL
MF0nF1
1
3
FSA3157
4
6
TxOn
DTxO
Gnd
RxP
RxN
Vcc
OscIn
OscOut
GndPLL
R24
39K
R34
2K
330
R3
75
R4
2.2
0.1
R7
R5
100
R101
VCC
R9
1M
RxOn
BAS31
C5
C4 2.2nF/200V
D1
9
10
100K
R1
R9 6.8
R11
6.8
C6
R10
10M
R14
C9 1K
Q2
VCC
R2
330K
R15
4.3K
0.1u R12
1K
C10
1n
47p
C37
1u
1M
VCC
VCC
R26 1n
1M
X1
R17
C108
C8
0.1u
C2
C1
12p
R13
2.2
Host-I/F
3.9K
R18
18
VCC
470u/4V
12p
C32
0.1u
32.768KHz
R19
470
C12
1n
DC-Powerline
Figure 3.3 - Single channel line interface example
Notes: A SPST analog switch can replace FSA157.
3.3.8 Ceramic Filter Considerations
The SIG40 is designed to operate with one ceramic filter for transmission and reception. However, if
switching between two channels is desired, two ceramic filters are required. The minimum allowable
bandwidth of the ceramic filters is +/-70 kHz @ 3dB. Narrower bandwidth limits the maximal bit rate.
The SIG40 selectable frequencies are designed according to the market available ceramic filters.
Nominal 3 db BW 20db Insertion
Stop band
attenuation
dB
In/Out
imped.
Ohm
Murata
part #
Oscilent
part #
freq.
MHz
BW
KHz
loss
dB
KHz
min.
max.
max.
min.
*3.58
+/-40 530
+/-70 750
+/-80 750
+/-80 750
+/-80 800
6.0
25
530
1000
600
470
470
SFSH3.58MCB
SFSL4.5MDB
SFSL5.5MDB
SFSL6.0MDB
SFSL6.5MDB
4.5
5.5
6.0
6.5
6.0
6.0
6.0
6.0
30
30
30
30
773-0045
773-0055
773-0060
773-0065
* The 3.58MHz frequency can be operated at 19.2Kbps only.
3.3.9 Communication performance
The maximal cable length between extreme devices depends mainly on the AC impedance of loads
connected to that line and number of nodes. The DC cable length has less effect on communication.
The SIG40 needs at least 20mVpp for proper reception. Good communication should be achieved if
the transmitted signal can be seen on an oscilloscope at the receiving side within the line noise.
@ 2007 Yamar Electronics Ltd.
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Proprietary and Confidential Information of YAMAR Electronics Ltd.
3.4
Frequency Control
The device is designed for operation in two selectable carrier frequencies (channels).
Presence of an interference signal can be read from the device internal register.
3.4.1
Operating Frequency
Bit 0 in control register 0 determines the operating channel F1 or F0.
3.4.2
InterfHop
When high, the device switches its channel automatically whenever an interference signal is detected in
the operating frequency. If the device did not receive any data in the new channel it will return to the
previous channel after 2Sec. if, again, no data has been received for 2Sec. and the interference has
stopped, it will switch frequency once more and will stay at the new channel.
3.4.3
MF0nF1
Output signal indicates the selected channel. F0=”High”, F1= “Low”.
3.5
Crystal Oscillator
The SIG40 is designed to operate with a low cost 32.768KHz crystal connected between OscIn and
OscOut pins. This type of crystal has the advantage of very low power consumption and low cost.
However there are also drawbacks. It is very sensitive to noise and has a temperature dependency that
should be carefully considered when selecting the crystal.
The following guidelines should be used when designing the PCB:
1. Design the trace length as short as possible.
2. Avoid thin line on resonator traces (< 0.010"), keep them as wide as possible.
3. To avoid noise, protect these signals with Ground shields.
The values of C1, C2 in Figure 3.3 oscillator circuitry should be determined according to the crystal
manufacturer recommendations.
3.5.1
Recommended 32.768KHz Crystal Specifications
Type
Value
Nominal Frequency:
Frequency tolerance @25ºC
Load capacitance
Serial resistance
Drive level
32.768KHz
+/-20 ppm
12.5 pF
50K Ohm (max.)
1uW (max.)
50,000 (max.)
Quality factor
Turnover temperature
Parabolic constant
Aging
Operating temperature
Storage temperature
+25ºC +/- 5ºC
-0.04 ppm/ºC² (max.)
+/-3 ppm in first year (max.)
-40ºC to + 85ºC
-55ºC to + 125ºC
The overall frequency tolerance should not exceed 200ppm.
3.6
PLL Power Pins
VccPLL should be connected to Vcc. GndPLL should be connected to ground. The PLL supply has to
be sufficiently powered, to avoid any fluctuations of power supply. A capacitor of at least 47uF should
be connected as close as possible to these pins. It is recommended to keep the lines between 3.3V
power supply and the Vcc pins as short as possible with wide PCB traces.
@ 2007 Yamar Electronics Ltd.
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Proprietary and Confidential Information of YAMAR Electronics Ltd.
4
OPERATION
Message Construction
4.1
The host constructs a message from bytes of data sent to its UART. The device receives this data on
its HDI data-In line. The 1st low input bit (start bit) starts the signaling transmission, and the 10th high bit
(stop bit) stops the transmission. If all bits, including the 10th bit, are low, the transmission continues
until a bit becomes high, but no more than 31-bit duration. It is considered as the Synch_Break Field of
the LIN protocol. The stop bit stops the transmission unless a new byte is received from host. The total
byte length does not change. The data latency between transmitter and receiver is about four bits.
4.1.1
LIN Protocol Messages
In order to comply with the LIN protocol, transmission of two kinds of bytes are allowed:
1. Bytes beginning with a start bit, followed by 8 bits and ending with a stop bit.
2. Bytes beginning with a start bit followed by a number of zeros ranging from 9 to 30 bits and
ending with a stop bit.
4.1.2
Commanding the SIG40
Writing and reading to/from the internal Control registers (See 4.2) using write and read commands set
the device behavior.
The registers are set by power-up Reset to operate at 19.2KBps, F0 = 5.5Mhz and F1 = 6.5Mhz.
Writing into the registers allows changing the selectable frequencies, the bit rate, and the operating
frequency. It also allows activating the automatic sleep feature and the automatic response to received
bytes feature.
4.1.3
Transmit
Upon detection of a start bit in HDI, the SIG40 starts to transmit modulated signal to the DC line
according to the set-up channel frequency and bit rate.
Note: After transmission, it takes duration of 2 bits before the device starts to listen to the DC-line.
4.1.4
Receive
When not transmitting, the SIG40 listens to the DC line in order to:
•
•
•
Detect and decode a legal signaling pattern according to the setup channel and bit rate.
In Sleep mode, the device detects wakeup messages.
Detects Interference signals.
Note: After transmission, it takes duration of 2 bits before the device starts to listen to the DC-line.
4.2
Control Registers
4.2.1
Device operating parameters and statuses
The internal control registers shown in table 4.1 contain the device parameters and statuses:
Register 0
7
Interference
6
5
4
Sleep (“0”)
3
2
1
0
~F0/F1
Register 1
7
“1”
6
“1”
5
4
3
2
Select frequency (table 4.2)
1
0
Bit rate
Table 4.1 - Device Control Registers
dir bits
Address Register Name
Description
R/W 1 1 = F1, 0 = F0.
R/W 1 Transmits back the last received byte
Default
0[0]
0[1]
F1/~F0
Remote loopback
For future use
F0
0
00
0[3:2]
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0[4]
nAuto sleep
R/W 1 0 = Automatically enters into Sleep Mode
when no reception from the DC line for 8 Sec.
1
0[6:5]
0[7]
1[5:0]
1[7:6]
For future use
Interference
F0, F1, bit rate select R/W 6 See Tables 4.2 and 4.3
00
-
“FF”H
11
R
1 Interference Detected indication
For future use
Should be “11”
4.3
SIG40 Configuration
The SIG40 operates at default with the following parameters:
Bit rate: 19.2 kbps
F0=5.5MHz, F1=6.5MHz
The following configuration bits set the operating frequencies according to table 4.2.
Table 4.2 – F0, F1 select
Control_register1
(3:0)
F0
F1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
3.58Mhz
3.58Mhz
3.58Mhz
3.58Mhz
4.5Mhz
4.5Mhz
4.5Mhz
4.5Mhz
Reserved
5.5Mhz
5.5Mhz
6Mhz
4.5Mhz
5.5Mhz
6Mhz
6.5Mhz
5.5Mhz
6Mhz
6.5Mhz
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6.5Mhz
6Mhz
6.5Mhz
6.5Mhz
5.5Mhz
Table 4.3 – bit rates select
Control_register_1 01 = 57.6Kbps
(5:4)
00 = 38.4Kbps
11 = 19.2Kbps
10 = Reserved
4.3.1
Command Mode
When in command mode, the host can configure the device according to the desired operating
parameters. The device enters command mode when pin HDC is lowered to zero. When in command
mode, data on the HDI pin is not transmitted to the bus, but is used to configure the SIG40. The
command can be written in any of the allowed Bit Rates.
In order to write to a control register, the host sends two bytes. The first byte begins with the address of
the register followed by 5(hex), and the second byte is the configuration data, as shown in figure 4.2.
The bytes should be sent more than 200nSec after lowering HDC.
Higher nibble [7:4]
Register Address
Configuration Data
Lower nibble [3:0]
5(hex)
Configuration Data
First Byte
Second Byte
Table 4.4 - Write Command
Figure 4.3 shows the pins involved in the writing process:
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T3
T1
HDC
HDI
2
3
1
0
2
3
d
a
t
a
0
start
bit
start
bit
stop
bit
start
bit
stop
bit
Data
Address
Configuration Data
T2
T3>1/half bit rate
Figure 4.3 - Writing to a Control Register
In order to read from a control register, the host sends one byte. The byte should be sent more than
200nSec after lowering HDC. The byte begins with the address of the register followed by ”D”H. The
SIG40 will then output the content of the register to pin HDO.
Read Command
Register Address[3:0]
D(hex)
Read Command
Figure 4.4 shows the pins involved in the reading process:
HDC:
T1
0
1
2
3
HDI Read
Command:
start bit
stop bit
Address
Figure 4.4 - Reading from a Control register
Note: Writing to Register 1
Writing a change frequencies command to register 1 is not always interpreted correctly by the device.
The device will switch to the correct frequencies pair however, it will not function properly, resulting a
communication lost.
Workaround: When changing frequencies by writing to register 1, use the following procedure:
Lower the H_DC.
Send a command to register 1 containing the require frequencies pair and a false bit rate.
Raise the H_DC
Lower the H_DC
Send a command to register 1 containing the require frequencies pair and the required bit rate.
Raise the H_DC.
For example, when wanting to work with frequencies 3.58MHz and 4.5MHz at 19.2Kbps the correct way
to program the device is described in Figure 4.4.1
HDC
0x15C0
0x15F0
HDI
Sending a command
for 3.58MHz/4.5MHz at
19.2Kbps
Sending a command
for 3.58MHz/4.5MHz at
38.4Kbps
Figure 4.4.1 – Writing to Register
Note: Changing only the bit rate can be done with a single write, as described above.
4.4
Loopback
The device operates like a transceiver, therefor while transmitting or writing a command the HDI signal
is looped back to the HDO pin.
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4.5
Reset and Power-up
The device has internal Power-up reset. It takes 6mS until a stable operation is achieved from power-
up, or from raising the nReset signal to high.
4.6
Sleep Mode
The device has three operation modes: Normal mode (normal transmitting and receiving), Sleep mode
(power saving mode), and Standby mode (after waking up, while pin nSleep is low). Transitions
between the modes are done via dedicated pins, or remotely, due to bus activity.
4.6.1
Entering Sleep mode
Host can move the device into Sleep mode from Normal mode either by a lowering to "0" (falling edge)
pin nSleep or enabling the AutoSleep option (Setting Register 0 bit 4 to “0”). The device enters to Sleep
mode and lowers output pin INH.
When AutoSleep option is enabled the device will enter Sleep mode if there was no reception from the
bus for a period of 8 Sec. EVEN if the device is currently transmitting. The device must receive data
from the bus in order to reset its internal autosleep timer. There are three ways to wakeup the device
from Sleep mode.
4.6.2
Wakeup from pin nSleep
In this case, the host raises pin nSleep. The device then enters Normal mode and raises pin INH. The
device automatically transmits a wakeup message to wakeup all other devices on the bus. While
transmitting this wakeup message to the bus, the device lowers pin HDO. After the transmission is
complete the device raises pin HDO (can be used to signal/interrupt the host). After the transmission is
completed and pin nSleep is high, the device enters Normal mode. See Figure 4.5 for signals
description.
T5
nSleep
INH
Wakeup Message
DC-BUS
Normal
Standby
HDO
T7
Figure 4.5 - Wakeup from nSleep
Wakeup from pin Wake
4.6.3
In this case, a transition on pin Wake (caused by an external switch of the application) is used to wake
the device. The device then enters Standby mode, raises pin INH, and transmits a wakeup message to
the bus. While transmitting the wakeup message to the bus, the device lowers pin HDO. After the
transmission is complete the device raises pin HDO (can be used to signal/interrupt the host). After the
transmission is completed and pin nSleep is high, the device enters Normal mode. The host has to raise
the nSleep pin (otherwise the device will remain in Standby mode).
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Wake
INH
T6
nSleep
Wakeup Message
DC-BUS
HDO
Standby
Normal
T8
Figure 4.6 - Wakeup from Wake
Wakeup from bus message
4.6.4
During Sleep mode, the device wakes up periodically to check for activity on the bus every 32 mSec. If
a wakeup message is detected, the device enters Standby mode and raises pin INH. The device then
signals the host by lowering pin HDO for a minimal duration of 8 bits, and a maximal duration of about
150mSec. The host has to raise nSleep pin (otherwise the device will remain in Standby mode). After
completing the reception, the device enters Normal mode. See Figure 4.7 for signals description.
Wakeup Message
DC-BUS
msg. detected
INH
nSleep
HDO
Normal
Standby
Figure 4.7 - Wakeup from bus message
4.7
Timing Characteristic
Symbol Figure
Characteristics
Min
200nS
Max
T1
T2
T3
4.3,4.4 Drop of HDC to drop of HDI
4.3
4.3
Raise of HDC to drop of HDI
Command stop bit to raise of HDC
200nS
Half bit
rate
T4
T5
T6
T7
T8
Drop of nSleep to drop of INH
Raise of nSleep to raise of INH
Transact on Wake to raise of INH
Raise of nSleep to drop of HDO
Transact on Wake to drop of HDO
Power Up or Reset to Normal mode
30uS
30uS
30uS
92uS 124uS
92uS 124uS
6mS
62uS
62uS
62uS
4.5
4.6
4.5
4.6
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5
ELECTRICAL PARAMETERS
Absolute Maximal Rating
5.1
Ambient Temperature under bias
Storage Temperature
Input Voltage
-40°C to 125°C
-55°C to 150°C
-0.6V to Vcc+0.3V
-0.3V to 4V
Vcc Supply voltage
5.2
Electrical Operating Conditions
Symbol
Vcc
Icc
Characteristics
Supply Voltage
Supply Current
Min
3.0
Typ
Max Units
V
Conditions
Conditions
3.3
35
3.6
mA
uA
Ipd
Power in Sleep mode
80
5.3
DC Electrical Characteristics
Symbol
VIH
Characteristics
Vcc
3.0
3.0
3.0
3.0
3.3
Typ
2.1
Units
V
Minimum high level input voltage
Maximum low level input voltage
Minimum high level output voltage
Minimum low level output voltage
Maximum input current
VIL
0.9
2.4
V
VOH
VOL
IIN
V
0.4
+/- 10
V
uA
5.4
Operating Temperature
Commercial:
Industrial:
0°C to 70°C
-40°C to 85°C
5.5
Package
20 lead SOP
@ 2007 Yamar Electronics Ltd.
12
DS-SIG40 R1.8
相关型号：
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