54RHSCFDXXX [ZARLINK]
Logic Circuit,;
| 型号： | 54RHSCFDXXX |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Logic Circuit, |
| 文件： | 总11页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
APRIL 1995
DS3595-3.4
54HSC/T630
RADIATION HARD 16-BIT PARALLEL ERROR
DETECTION & CORRECTION
The 54HSC/T630 is a 16-bit parallel Error Detection and
Correction circuit. It uses a modified Hamming code to
generate a 6-bit check word from each 16-bit data word. The
check word is stored with the data word during a memory write
cycle. During a memory read cycle a 22-bit word is taken from
memory and checked for errors.
Single bit errors in data words are flagged and corrected.
Single bit errors in check words are flagged but not corrected.
The position of the incorrect bit is pinpointed, in both cases, by
the 6-bit error syndrome code which is output during the error
correction cycle.
Two bit errors are flagged but not corrected. Any
combination of two bit errors occurring within the 22-bit word
read from memory, (ie two errors in the 16-bit data word, two
bits in the 16-bit check word or one error in each) will be
correctly identified.
The gross errors of all bits, low or high, will be detected.
The control signals S1 and S0 select the function to be
performed by the EDAC They control the generation of check
words and the latching and correction of data (see table 1)
When errors are detected, flags are placed on outputs SEF
and DEF (see table 2).
Figure 1: Block Diagram
FEATURES
■ Radiation Hard:
Dose Rate Upset Exceeding 3x1010 Rad(Si)/sec
Total Dose for Functionality Upto 1x106 Rad(Si)
■ High SEU Immunity, Latch Up Free
■ CMOS-SOS Technology
■ All Inputs and Outputs Fully TTL Compatible (54HST630)
or CMOS Compatible (54HSC630)
■ Low Power
■ Detects and Corrects Single-Bit Errors
■ Detects and Flags Dual-Bit Errors
■ High Speed:
Write Cycle - Generates Checkword In 40ns Typical
Read Cycle - Flags Errors In 20ns Typical
54HSC/T630
Control
S1 S0
Error Flags
SEF
Cycle
EDAC Function
Data UO
Checkword
DEF
WRITE
READ
READ
READ
Low Low Generates Checkword
Low High Read Data BCheckword
High High Latch & Flag Error
Input Data
Input Data
Output Checkword
Input Checkword
Low
Low
Low
Low
Latch Data Latch Checkword
Enabled
Enabled
Enabled
Enabled
High Low Correct Data Word &
Generate Syndrome Bits
Output
Corrected
Data
Output Syndrome Bits
Table 1: Control Functions
Total Number of Errors
Error Flags
Data Correction
16-bit Data
6-bit Checkword
SEF
DEF
0
1
0
1
2
0
0
0
1
1
0
2
Low
Low
Low
Low
High
High
High
Not Applicable
Correctlon
Correction
Interrupt
High
High
High
High
High
Interrupt
Interrupt
Table 2: Error Functions
ERROR DETECTION & CORRECTION
Any two-bit error will change the sense of an even number
of check bits. The two-bit error is not correctable since the
parity tree can only identify singlebit errors. Both error flags are
set high when any two-bit error is detected.
During a memory write cycle, six check bits (CBO-CB5)
are generated by eight-input parity generators using the data
bits defined in Table 3. During a memory read cycle, the 6-bit
checkword is retrieved along with the actual data.
Three or more simultaneous bit errors cause the EDAC to
transmit that no error, a correctable error, or an uncorrectable
error has occurred and hence produce erroneous results in all
three cases.
Error correction is accomplished by identifying the bad bit
and inverting it. Identification of the erroneous bit is achieved
by comparing the 16-bit word and 6-bit checkword from
memory with the new checkword with one (checkword error)
or three (data word error) inverted bits.
As the corrected word is made available on the data word l/
O port, the checkword l/O port presents a 6-bit syndrome error
code. This syndrome code can be used to identify the
corrupted bit in memory (see Table 4. overleaf).
Error detection is accomplished as the 6-bit checkword and
the 16-bit data word from memory are applied to internal parity
generators/checkers. If the parity of all six groupings of data
and check bits are correct, it is assumed that no error has
occurred and both error flags will be low. It should be noted
that the sense of two of the check bits, bits CBO and CB1, is
inverted to ensure that the gross-error condition of all lows and
all highs is detected.
If the parity of one or more of the check groups is incorrect,
an error has occurred and the proper error flag or flags will be
set high. Any single error in the 16bit data word will change the
sense of exactly three bits of the 6-bit checkword. Any single
error in the 6bit checkword changes the sense of only that one
bit. In either case, the single error flag will be set high while the
dual error flag will remain low.
2
54HSC/T630
16-bit Data Word
Checkword
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
X
X
X
X
X
X
X
X
X
X
X
CB0
CB1
CB2
CB3
CB4
CB5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The six check bits are partly bits derived from the matrix of data bits as indicated by 'X' for each bit.
Table 3: Check Word Generation
Syndrome
Error
Error Location
No
Code
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 CB0 CB1 CB2 CB3 CB4 CB5 Error
CB0
CB1
CB2
CB3
CB4
CB5
L
L
L
H
L
H
L
L
L
L
H
L
H
L
H
L
H
H
L
L
L
L
H
L
L
H
H
L
H
L
H
H
L
L
H
H
H
L
H
L
H
H
L
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
L
H
L
H
H
L
H
H
H
H
L
L
H
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
L
L
H
L
H
L
H
L
H
H
H
H
H
H
H
L
L
L
H
Table 4: Error Syndrome Codes
APPLICATIONS
In most applications, status registers will be used to keep
tabs on error flags and error syndrome bits. If repeated
patterns of error flags and syndrome bits occur, the CPU will
be able to recognize these symptoms as a “hard” error. The
syndrome bits can be used to pinpoint the faulty memory chip,
See Figure 3.
Although many semiconductor memories have separate
input and output pins, it is possible to design the error
detection and correction function using a single EDAC. EDAC
data and check bit pins function as inputs or outputs
dependent upon the state of control signals S0 and S1. It
becomes necessary to use wired AND logic, with fairly
complex timing system, to control the EDAC and data bus.
This scheme becomes difficult to implement both in terms of
board layout and timing. System performance is also
adversely affected, See Figure 2.
Optimised systems can be implemented using two EDAC’s
in parallel, One of the units is used strictly as an encoder
during the memory write cycle. Both controls S0 and Sl are
grounded, The encoder chip will generate the 6-bit check word
for memory storage along with the 16-bit data.
The second of the two EDAC’s will be used as a decoder
during the memory read cycle. This decoder chip requires
timing pulses for correct operation. Control S1 is set low and
S0 high as the memory read cycle begins. After the memory
output data is valid, the control S1 input is moved from the low
to a high. This low-to-high transition latches the 22-bit word
from memory into internal registers of this second EDAC and
enables the two error flags. If no error occurs, the CPU can
accept the 16-bit word directly from memory. If a single error
has occurred, the CPU must move the control SO input from
the high to a low to output corrected data and the error
syndrome bits. Any dual error should be an interrupt condition.
Figure 2: Error Detection and Correction Using a
Single EDAC Unit
3
54HSC/T630
S1
S0
Function
L
H
H
L
Start READ
H
H
Latch data & flag errors
Correct data & Output syndrome bits
Figure 3: Error Detection and Correction Using Two EDAC Units
DEFINITION OF SUBGROUPS
Subgroup
Definition
1
2
Static characteristics specified in Table 6 at +25°C
Static characteristics specified in Table 6 at +125°C
Static characteristics specified in Table 6 at -55°C
Switching characteristics specified in Table 7 at +25°C
Switching characteristics specified in Table 7 at +125°C
Switching characteristics specified in Table 7 at -55°C
3
9
10
11
DC CHARACTERISTICS AND RATINGS
Note: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these conditions, or at
any other condition above those indicated in the operations
section of this specification, is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Parameter
Min
Max
Units
V
Supply Voltage
-0.5
7
Input Voltage
VSS-0.3 VDD+0.3
V
Current Through Any Pin
Operating Temperature
Storage Temperature
-20
-55
-65
+20
125
150
mA
°C
°C
Table 5: Absolute Maximum Ratings
4
54HSC/T630
Total dose radiation not
exceeding 3x105 Rad(SI)
Symbol
Parameter
Supply Voltage
Conditions
Min
Typ
Max
Units
VDD
VIH1
VIL1
-
4.5
2.0
-
5.0
5.5
-
V
V
V
V
V
V
V
TTL Input High Voltage
TTL Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
TTL Output High Voltage
TTL Output Low Voltage
-
-
-
-
-
-
-
-
0.8
-
VIH2
VIL2
-
3.5
-
-
1.5
-
VOH1
VOL1
IOH = -4mA
2.4
-
IOL = 12mA (CB or DB),
IOL = 4mA (SEF or DEF)
0.4
VOH2
VOL2
CMOS Output High Voltage
CMOS Output Low Voltage
IOH = -4mA
VDD-0.5
-
-
-
-
V
V
IOL = 12mA (CB or DB),
IOL = 4mA (SEF or DEF)
0.5
I1L
I1H
I2L
Input Low Current
Input High Current
IO Low Current
VDD = 5.5, VIN = VSS
VDD = 5.5, VIN = VDD
VDD = 5.5, VIN = VSS
VDD = 5.5, VIN = VDD
-
-
-
-
-
-
-
-
-
-
-10
50
-50
50
1
µA
µA
µA
µA
mA
I2H
IDD
IO High Current
Power Supply Current
VDD = Max, S0 & S1 at
5.5V, All CB & DB pins
grounded, DEF & SEF
open
VDD = 5V±10%, over full operating temperature range.
Mil-Std-883, method 5005, subgroups 1, 2, 3
Parameters at higher radiation levels available on request.
Table 6: Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
From
To
(Input) (Output)
Max. Units
Min.
Conditions (HST)
Conditions (HSC)
Parameter
DB
DB
CB
CB
-
-
58
58
29
29
40
45
45
65
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S0 = 0V, S1 = 0V
S0 = 0V, S1 = 0V
S0 = 3V
S0 = 0V, S1 = 0V
S0 = 0V, S1 = 0V
S0 = VDD-1V
tPLH Propogation delay time, low-to-high-level output (Note 4)
tPLH Propogation delay time, low-to-high-level output (Note 4)
tPLH Propogation delay time, low-to-high-level output (Note 5)
tPLH Propogation delay time, low-to-high-level output (Note 5)
tPZH Output enable time to high level (Note 6)
tPZL Output enable time to low level (Note 6)
tPHZ Output disable time to high level (Note 7)
tPLZ Output disable time to low level (Note 7)
tS Set-up time to S1 ›
S1 Ý
S1 Ý
S0 ß
DEF
SEF
-
-
S0 = 3V
S0 = VDD-1V
CB, DB
CB, DB
CB, DB
CB, DB
-
-
S1 = 3V (fig. 5)
S1 = 3V (fig. 4)
S1 = 3V (fig. 5)
S1 = 3V (fig. 4)
-
S1 = V -1V (fig. 5)
DD
S0 ß
-
S1 = V -1V (fig. 4)
DD
S0 Ý
S0 Ý
CB, DB
CB, DB
-
S1 = V -1V (fig. 5)
DD
-
S1 = V -1V (fig. 4)
DD
30
15
-
-
-
-
-
tH Hold time after S1 ›
1. VDD = 5V ±10% and CL = 50pF, over full operating temperature and total dose = 300K Rad(Si)
2. Input Pulse VSS to 3.0 Volts.(TTL), VDD -1V (CMOS).
3. Times Measurement Reference Level 1.5 Volts.
4. These parameters describe the time intervals taken to generate the check word during the memory write cycle.
5. These parameters describe the time intervals taken to flag errors during memory read cycle.
6. These parameters describe the time intervals taken to correct and output the data word and to generate and output the syndrome error code during
the memory read cycle.
7. These parameters describe the time intervals taken to disable the CB & DB buses in preparation for a new data word during the memory read cycle.
8. Mil-Std-883, method 5005, subgroups 9, 10, 11
9. Parameters at higher radiation levels available on request.
Table 7: AC Electrical Characteristics
5
54HSC/T630
Figure 4: Output Load Circuit
Figure 5: Output Load Circuit
(Note 6)
(Note 6)
ts
(Note 7)
(Note 7)
(Note 5)
(Note 5)
Figure 6: Read, Flag and Correct, Made Switching Waveforms
6
54HSC/T630
PIN ASSIGNMENTS
Figure 8: 28-Lead Flatpack (Solder Seal) - Package Style F
Figure 7: 28-Lead Ceramic DIL (Solder Seal)
- Package Style C
PACKAGE OUTLINES
Millimetres
Inches
Ref
Min.
Nom.
Max.
5.715
1.53
0.59
0.36
36.02
-
Min.
Nom.
Max.
0.225
0.060
0.023
0.014
1.418
-
A
A1
b
-
-
-
-
0.38
-
0.015
-
D
0.35
-
0.014
-
c
0.20
-
0.008
-
D
-
-
-
-
e
-
2.54 Typ.
-
0.100 Typ.
14
15
1
e1
H
-
15.24 Typ.
-
-
0.600 Typ.
-
4.71
-
-
-
-
5.38
15.90
1.27
1.53
0.185
-
-
-
-
0.212
0.626
0.050
0.060
Me
Z
-
-
-
-
-
-
28
W
XG404
W
ME
Seating Plane
A1
A
C
H
e1
e
b
Z
15°
Figure 9: 28-Lead Ceramic DIL (Solder Seal) - Package Style C
7
54HSC/T630
Millimetres
Inches
Ref
Min.
-
Nom.
Max.
2.97
0.48
0.152
18.49
12.90
9.85
1.40
9.27
-
Min.
-
Nom.
Max.
0.117
0.019
0.006
0.728
0.508
0.388
0.055
0.365
-
A
b
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.38
0.076
18.08
12.50
9.45
1.14
8.00
0.66
-
0.015
0.003
0.712
0.492
0.372
0.045
0.315
0.026
-
c
D
E
E2
e
L
Q
S
1.14
0.045
XG543
E
b
D
S
e
L
A
c
E2
Q
Pin 1
Figure 10: 28-Lead Ceramic Flatpack (Solder Seal) - Package Style F
8
54HSC/T630
RADIATION TOLERANCE
Total Dose (Function to specification)*
Transient Upset (Stored data loss)
Transient Upset (Survivability)
Neutron Hardness (Function to specification)
Single Event Upset**
3x105 Rad(Si)
5x1010 Rad(Si)/sec
>1x1012 Rad(Si)/sec
>1x1015 n/cm2
Total Dose Radiation Testing
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
<1x10-10 Errors/bit day
Not possible
Latch Up
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
GEC Plessey Semiconductors can provide radiation
testing compliant with Mil-Std-883 method 1019 Ionizing
Radiation (total dose) test.
Figure 11: Radiation Hardness Parameters
ORDERING INFORMATION
Unique Circuit Designator
54xHSC/T630xxxxx
Radiation Tolerance
‘Blank’ No tolerance implied
QA/QCI Process
(See Section 9 Part 4)
R
Q
100 kRads (Si) Guaranteed
300 kRads (Si) Guaranteed
H * 1000 kRads (Si) Guaranteed
*HSC Only
Test Process
(See Section 9 Part 3)
Package Type
Assembly Process
(See Section 9 Part 2)
C
F
Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Reliability Level
L
Rel 0
C
D
E
B
S
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
9
54HSC/T630
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire, SN2 2QW, United Kingdom.
Tel: (01793) 518000
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK Tel: (01793) 518527/518566
Fax: (01793) 518582
Fax: (01793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road, Scotts Valley,
California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1995 Publication No. DS3595-3.4 April 1995
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to
be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only
and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose
failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
相关型号：
©2020 ICPDF网 联系我们和版权申明