AGRL8583DAJ-D_技术文档

L8583D Line Card Access Switch

The L8583D has eight states: the idle talk state (line

break switches closed, all other switches open), the

power ringing state (ringing access switches closed,

all other switches open), loop access state (loop

access switches closed, all switches open), SLIC test

state (test in switches closed, all other switches

open), simultaneous loop and SLIC access state

(loop and test in switches closed, all others open),

ringing generator test state (ring test switches closed,

all others open), simultaneous test-out and ring-test

state (ring and test out switches closed), and an all-

off state. The L8583D is appropriate for central office,

access, digital loop carrier, and other Telcordia Tech-

nologies™ TR-57 applications.

Features

I Small size/surface-mount packaging

I Monolithic IC reliability

I Low impulse noise

I Make-before-break, break-before-make operation

I Clean, bounce-free switching

I Low, matched on-resistance

I Built-in current limiting, thermal shutdown, and

SLIC protection

I 5 V only operation, very low power consumption

I Battery monitor, all-off state upon loss of battery

I No EMI

The L8583D offers break-before-make or make-

before-break switching, with simple logic-level input

control. Because of the solid-state construction, volt-

age transients generated when switching into an

inductive ringing lead during ring cadence or ring trip

are minimized, possibly eliminating the need for

external zero cross switching circuitry. State control is

via logic level inputs, so no additional driver circuitry

is required.

I Latched logic level inputs, no driver circuitry

I Only one external protector required

Applications

The line break switch is a linear switch that has

exceptionally low on-resistance and an excellent

on-resistance matching characteristic. The ringing

access switch has a breakdown voltage rating

>480 V which is sufficiently high, with proper protec-

tion, to prevent breakdown in the presence of a tran-

sient fault condition (i.e., passing the transient on to

the ringing generator).

I Central office

I DLC

I PBX

I DAML

I HFC/FITL

The L8583D provides an integrated diode bridge

along with current limiting and thermal shutdown for

protection of the device itself and the subsequent

subscriber line integrated circuit (SLIC). For LCAS

protection, power cross is reduced by the current-

limiting and thermal shutdown circuits and lightning

reduced by the current-limit circuit. Residue faults are

shunted from the SLIC by the diode bridge.

Description

The Legerity L8583D line card access switch is a

monolithic solid-state device providing

the equivalent switching functionality of three 2-form

C switches. The L8583D is designed to provide

power ringing access, line test access (test out), and

SLIC test access (test in) to tip and ring in central

office, digital loop carrier, private branch exchange,

digitally added main line, and hybrid fiber coax/fiber-

in-the-loop analog line card applications. An addi-

tional pair of solid-state contacts are also available to

provide access for testing of the ringing generator.

Document ID# 080990 Date:

Oct 31, 2002

1

Rev:

A

Version:

Distribution:

Public

Data Sheet

L8583D Line Card Access Switch

October 2002

Description (continued)

Pin Information

To protect the L8583D from an overvoltage fault condi-

tion, use of a secondary protector is required. The

secondary protector must limit the voltage seen at the

tip/ring terminals to prevent the breakdown voltage of

the switches from being exceeded. To minimize stress

on the solid-state contacts, use of a foldback-type or

crowbar-type secondary protector is recommended.

Please contact your Legerity account representative for

a choice of recommended secondary protection

device. With proper choice of secondary protection, a

line card using the L8583D will meet all relevant ITU-T,

LSSGR, FCC, or UL^®protection requirements.

FGND

TTESTin

TBAT

1

2

3

4

5

6

7

8

9

20 V^BAT

SW1

SW2

19 RTESTin

18 RBAT

SW3

SW5

SW4

SW6

TLINE

17 RLINE

TRINGING

TTESTout

NC

16 R^RINGING

15 RTESTout

14 LATCH

13 INTESTin

12 INRING

11 INTESTout

SW7

SW9

SW8

SW10

The L8583D operates off of a 5 V supply only. This

gives the device extremely low idle and active power

dissipation and allows use with virtually any range of

battery voltage. This makes the L8583D especially

appropriate for remote power applications such as

DAML or FOC/FITL or other Telcordia Technologies

GR 909 applications where power dissipation is partic-

ularly critical.

VDD

CONTROL

LOGIC

TSD

DGND 10

1670

A battery voltage is also used by the L8583D, only as a

reference for the integrated protection circuit. The

L8583D will enter an all-off state upon loss of battery.

Figure 1. 20-Pin Plastic SOG

During power ringing, to turn on and maintain the on

state, the ring access switch and ring test switch will

draw a nominal 2 mA from the ring generator.

F^GND

1

28 V^BAT

NC

2

3

4

27

26

NC

The L8583D device is packaged in a 20-pin plastic

SOG (L8583DEY) and a 28-pin plastic SOG

(L8583DAE). See Figure 1 for an illustration of the

20-pin package and Figure 2 for an illustration of the

28-pin package.

25 NC

NC

SW1

SW2

TTESTin

5

6

7

24

23

RTESTin

RBAT

TBAT

TLINE

SW3

SW5

SW4

22

21

RLINE

8

TRINGING

NC

SW6

SW7

9

10

11

20

19

18

NC

R^RINGING

SW8

SW10

RTESTout

TTESTout

SW9

NC

LATCH

V^DD12

17

16

INTESTin

CONTROL

LOGIC

IN^RING

TSD

13

14

INTESTout

12-2365 (F).d

15

DGND

Figure 2. 28-Pin Plastic SOG

2

Data Sheet

L8583D Line Card Access Switch

October 2002

Pin Information (continued)

Table 1. Pin Descriptions

20-Pin SOG 28-Pin SOG Symbol*

Description

1

2

3

4

5

6

7

1

5

6

7

8

F^GND

Fault ground.

T^TESTinTest (in) access on TIP.

T^BAT

T^LINE

T^RINGINGConnect to return ground for ringing generator.

T^TESToutTest (out) access on TIP.

Connect to TIP on SLIC side.

Connect to TIP on line side.

10

2, 3, 4, 9, 11, 21,

NC

No connection.

25, 26, 27

8

9

12

13

V^DD

T^SD

5 V supply.

Temperature shutdown pin. Can be used as a logic level input or an output. See

Table 16 and the Switching Behavior section of this data sheet for input pin

description. As an output flag, this pin will read 5 V when the device is in its

operational mode and 0 V in the thermal shutdown mode. To disable the thermal

shutdown mechanism, tie this pin to 5 V (not recommended).

10

11

12

13

14

15

16

17

18

19

20

14

15

16

17

18

19

20

22

23

24

28

D^GNDDigital ground.

u

IN^TESToutLogic level switch input control.

u

IN^RINGLogic level switch input control.

d

IN^TESTinLogic level switch input control.

LATCH^dData input control, active-high, transparent low.

R^TESToutTest (out) access on RING.

R^RINGINGConnect to ringing generator.

R^LINE

R^BAT

Connect to RING on line side.

Connect to RING on SLIC side.

R^TESTinTest (in) access on RING.

V^BATBattery voltage. Used as a reference for protection circuit.

* u = 75K typical pull-up resistor.

d = 75K typical pull-down resistor.

3

Data Sheet

L8583D Line Card Access Switch

Absolute Maximum Ratings

October 2002

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Table 2. Absolute Maximum Ratings

Parameter

Min

–40

5

Max

110

150

95

Unit

°C

%

Operating Temperature Range

Storage Temperature Range

Relative Humidity Range

Pin Soldering Temperature (t = 10 s max)

5 V Power Supply

Battery Supply

—

260

7

–85

7

°C

V

Logic Input Voltage

V

Input-to-output Isolation

Pole-to-pole Isolation

—

330

V

Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions

must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test

operations. Legerity employs both a human-body model (HBM) and a charged-device model (CDM) qualification

requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresh-

olds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114

(HBM) and JESD22-C101 (CDM) standards.

Table 3. HBM ESD Threshold Voltage

Device

L8583D

Rating

1000 V

4

Data Sheet

L8583D Line Card Access Switch

October 2002

Electrical Characteristics

TA = –40 °C to +85 °C, unless otherwise specified.

Minimum and maximum values are testing requirements. Typical values are characteristics of the device and are

the result of engineering evaluations. Typical values are for information purposes only and are not part of the test-

ing requirements.

Table 4. Power Supply Specifications

Supply

V^DD

Min

4.5

Typ

5

Max

5.5

Unit

V

Supply

VBAT*

Min

–19

Typ

—

Max

–72

Unit

V

* VBAT is used only as a reference for internal protection circuitry. If VBAT rises above –10 V, the device will enter an all-off state and remain in

this state until the battery voltage drops below –15 V.

Table 5. Test In Switches, 1 and 2

Parameter

Test Condition

Measure Min Typ Max Unit

Off-state Leakage Current:

+25 °C

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 V to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 V to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

Iswitch

—

1

µA

+85 °C

–40 °C

On-resistance:

+25 °C

Iswitch (on) = ±5 mA, ±10 mA

∆ V^ON

∆ VON

—

49

—

37

—

77

—

Ω

+85 °C

–40 °C

Isolation:

+25 °C

Vswitch (both poles) = ±320 V,

logic inputs = Gnd

Iswitch

—

1

µA

+85 °C

–40 °C

Vswitch (both poles) = ±330 V,

logic inputs = Gnd

Vswitch (both poles) = ±310 V,

logic inputs = Gnd

dV/dt Sensitivity*

—

200

—

V/µs

* Applied voltage is 100 Vp-p square wave at 100 Hz.

5

Data Sheet

L8583D Line Card Access Switch

October 2002

Electrical Characteristics (continued)

Table 6. Break Switches, 3 and 4

Parameter

Off-state Leakage Current:

+25 °C

Test Condition

Measure

Min Typ Max Unit

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 V to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 V to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

Iswitch

—

1

µA

+85 °C

–40 °C

On-resistance:

+25 °C

T^LINE= ±10 mA, ±40 mA, TBAT = –2 V

∆ V^ON

∆ VON

—

21.5

—

16

—

31

—

Ω

+85 °C

–40 °C

On-resistance Match

Per on-resistance test

condition of SW3, SW4

Magnitude

R^ONSW3 – RON SW4

—

0.2 1.0

Ω

On-state Voltage*

Iswitch = I^LIMITat 50 Hz/60 Hz

VON

—

220

—

V

dc Current Limit:

+85 °C

Vswitch (on) = ±10 V

Iswitch

80

—

mA

250 mA

–40 °C

Dynamic Current Limit

(t = <0.5 µs)

Break switches in on state; ringing access

switches off; apply ±1000 V at 10/1000 µs

pulse; appropriate secondary protection in

place

Iswitch

—

2.5

—

A

Isolation:

+25 °C

Vswitch (both poles) = ±320 V,

logic inputs = Gnd

Iswitch

—

1

µA

+85 °C

–40 °C

Vswitch (both poles) = ±330 V,

logic inputs = Gnd

Vswitch (both poles) = ±310 V,

logic inputs = Gnd

dV/dt Sensitivity^†

—

200

—

V/µs

* This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.

† Applied voltage is 100 Vp-p square wave at 100 Hz.

6

Data Sheet

L8583D Line Card Access Switch

October 2002

Electrical Characteristics (continued)

Table 7. Ring Test Return Switch, 5

Parameter

Test Condition

Measure Min Typ Max Unit

Off-state Leakage Current:

+25 °C

+85 °C

–40 °C

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 V to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 V to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

Iswitch

—

1

µA

On-resistance

Iswitch (on) = ±0 mA, ±10 mA

∆ V^ON

—

55

110

Ω

Isolation:

+25 °C

Vswitch (both poles) = ±320 V,

logic inputs = Gnd

Iswitch

—

1

µA

+85 °C

–40 °C

Vswitch (both poles) = ±330 V,

logic inputs = Gnd

Vswitch (both poles) = ±310 V,

logic inputs = Gnd

dV/dt Sensitivity*

—

200

—

V/µs

* Applied voltage is 100 Vp-p square wave at 100 Hz.

Table 8. Ringing Test Switch, 6

Parameter

Test Condition

Measure

Min Typ Max Unit

Off-state Leakage Current:

+25 °C

+85 °C

–40 °C

Vswitch (differential) = –60 V to +190 V

Vswitch (differential) = +60 V to –190 V

Vswitch (differential) = –60 V to +200 V

Vswitch (differential) = +60 V to –200 V

Vswitch (differential) = –60 V to +180 V

Vswitch (differential) = +60 V to –180 V

Iswitch

—

1

µA

On-resistance

On Voltage

Steady-state Current*

Release Current

Iswitch (on) = ±70 mA, ±80 mA

∆ V^ON

—

20

1.5

100 mA

—

Ω

V

Iswitch (on) = ±1 mA

—

500

µA

Isolation:

+25 °C

Vswitch (both poles) = ±320 V,

logic inputs = Gnd

Iswitch

—

1

µA

+85 °C

–40 °C

Vswitch (both poles) = ±330 V,

logic inputs = Gnd

Vswitch (both poles) = ±310 V,

logic inputs = Gnd

dV/dt Sensitivity^†

—

200

—

V/µs

* Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded.

† Applied voltage is 100 Vp-p square wave at 100 Hz.

7

Data Sheet

L8583D Line Card Access Switch

October 2002

Electrical Characteristics (continued)

Table 9. Ring Return Switch, 7

Parameter

Test Condition

Measure Min Typ Max Unit

Off-state Leakage Current:

+25 °C

+85 °C

–40 °C

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 V to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 V to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

Iswitch

—

1

µA

dc Current Limit

Dynamic Current Limit

(t = <0.5 µs)

Vswitch (on) = ±10 V

Iswitch

—

200

2.5

—

mA

A

Break and loop switches in off state; ring return switch Iswitch

on; apply ±1000 V at 10/1000 µs pulse; appropriate sec-

ondary protection in place

On-resistance

On-state Voltage*

Iswitch (on) = ±0 mA, ±10 mA

Iswitch = I^LIMITat 50 Hz/60 Hz

∆ V^ON

VON

—

110

130

Ω

V

Isolation:

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, logic inputs = Gnd

Vswitch (both poles) = ±330 V, logic inputs = Gnd

Vswitch (both poles) = ±310 V, logic inputs = Gnd

Iswitch

—

1

µA

dV/dt Sensitivity^†

—

200

—

V/µs

* This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.

† Applied voltage is 100 Vp-p square wave at 100 Hz.

Table 10. Ringing Access Switch, 8

Parameter

Off-state Leakage Current:

+25 °C

Test Condition

Measure Min Typ Max Unit

Vswitch (differential) = –255 V to +210 V

Vswitch (differential) = +255 V to –210 V

Vswitch (differential) = –270 V to +210 V

Vswitch (differential) = +270 V to –210 V

Vswitch (differential) = –245 V to +210 V

Vswitch (differential) = +245 V to –210 V

Iswitch

—

1

µA

+85 °C

–40 °C

On Voltage

Ring Generator Current Dur-

ing Ring

Iswitch (on) = ±1 mA

—

2

3

—

V

mA

V^CC= 5 V

I^RING-

IN^RING= 1

SOURCE

IN^TESTin= 0

IN^TESTout= 0

Steady-state Current*

Surge Current*

Release Current

On-resistance

—

500

—

150 mA

2

A

µA

Ω

—

12

Iswitch (on) = ±70 mA, ±80 mA

∆ V^ON

Isolation:

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, logic inputs = Gnd

Vswitch (both poles) = ±330 V, logic inputs = Gnd

Vswitch (both poles) = ±310 V, logic inputs = Gnd

Iswitch

—

1

µA

dV/dt Sensitivity^†

—

200

—

V/µs

* Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded.

† Applied voltage is 100 Vp-p square wave at 100 Hz.

8

Data Sheet

L8583D Line Card Access Switch

October 2002

Electrical Characteristics (continued)

Table 11. Loop Access Switches, 9 and 10

Parameter

Test Condition

Measure Min Typ Max Unit

Off-state Leakage Current:

+25 °C

+85 °C

–40 °C

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 V to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 V to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

Iswitch

—

1

µA

On-resistance:

+25 °C

Iswitch (on) = ±5 mA, ±10 mA

∆ Von

—

49

—

37

—

77

—

Ω

+85 °C

–40 °C

On-state Voltage*

Iswitch = I^LIMITat 50 Hz/60 Hz

VON

—

130

V

dc Current Limit:

+85 °C

Vswitch (on) = ±10 V

Iswitch

80

—

mA

–40 °C

250 mA

Dynamic Current Limit

(t = <0.5 µs)

Break switches in on state; ringing access switches off; Iswitch

apply ±1000 V at 10/1000 µs pulse; appropriate second-

ary protection in place

—

2.5

—

A

Isolation:

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, logic inputs = Gnd

Vswitch (both poles) = ±330 V, logic inputs = Gnd

Vswitch (both poles) = ±310 V, logic inputs = Gnd

Iswitch

—

1

µA

dV/dt Sensitivity^†

—

200

—

V/µs

* This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.

† Applied voltage is 100 Vp-p square wave at 100 Hz.

9

Data Sheet

L8583D Line Card Access Switch

October 2002

Electrical Characteristics (continued)

Table 12. Additional Electrical Characteristics

Parameter

Test Condition

Measure Min Typ Max Unit

Digital Input Characteristics:

Input Low Voltage

Input High Voltage

—

llogicin

—

3.5

—

1.5

—

500 µA

V

Input Leakage Current (high)

V^DD= 5.5 V, VBAT = –75 V,

Vlogicin = 5 V

Input Leakage Current (low)

V^DD= 5.5 V, VBAT = –75 V,

llogicin

—

500 µA

Vlogicin = 0 V

Power Requirements:

Power Dissipation

V^DD= 5 V, VBAT = –48 V,

idle/talk state

I^DD, IBAT

IDD, IBAT

—

4.5

3.8

4.4

7

6

mW

all-off state,

ringing state or access state

11 mW

V^DDCurrent

V^BATCurrent

VDD = 5 V,

idle/talk state

all-off state,

ringing state

I^DD

IDD

—

0.860 1.3 mA

0.760 1.1 mA

0.850 2.1 mA

VBAT = –48 V,

idle/talk state

I^BAT

IBAT

—

4

10

µA

all-off state,

ringing state or access state

Digital Input Characteristics:

Input Low Voltage

Input High Voltage

—

llogicin

—

3.5

—

0.5

1.5

—

V

µA

Input Leakage Current (high)

VDD = 5.5 V, VBAT = –58 V,

INTESTOUT, INRING

Vlogicin = 5 V

Input Leakage Current (low)

INTESTOUT, INRING

Input Leakage Current (high)

INTESTIN, LATCH

Input Leakage Current (low)

INTESTIN, LATCH

VDD = 5.5 V, VBAT = –58 V,

llogicin

—

100

0.5

—

µA

Vlogicin = 0 V

V^DD= 5.5 V, VBAT = –58 V,

Vlogicin = 5 V

V^DD= 5.5 V, VBAT = –58 V,

Vlogicin = 0 V

Temperature Shutdown Requirements*:

Shutdown Activation Temperature

—

110

10

125

—

150

25

°C

Shutdown Circuit Hysteresis

* Temperature shutdown flag (TSD) will be high during normal operation and low during temperature shutdown state.

Zero Cross Current Turn Off

The ring access switch (SW8) is designed to turn off on the next zero current crossing after application of the

appropriate logic input control. This switch requires a current zero cross to turn off. Switch 8, once on, will remain in

the on state (regardless of logic input) until a current zero cross. Therefore, to ensure proper operation of switch 8,

this switch should be connected, via proper impedance, to the ringing generator or some other ac source. Do not

attempt to switch pure dc with switch 8. The ringing test access switch, SW6, also has similar characteristics to

switch 8 and should also only be used to switch signals with zero current crossings. For a detailed explanation of

the operation of switches 6 and 8, please refer to the An Introduction to L758X Series of Line Card Access

Switches Application Note.

10

Data Sheet

L8583D Line Card Access Switch

October 2002

Switching Behavior

When switching from the power ringing state to the idle/talk state, via simple logic level input control, the L8583D is

able to provide control with respect to the timing when the ringing access contacts are released relative to the state

of the line break contacts.

Make-before-break operation occurs when the line break switch contacts are closed (or made) before the ringing

access switch contact is opened (or broken). Break-before-make operation occurs when the ringing access contact

is opened before the line break switch contacts are closed.

Using the logic level input pins RING, TESTin, and TESTout, either make-before-break or break-before-make oper-

ation of the L8583D is easily achieved. The logic sequences for either mode of operation are given in Table 13 and

Table 14. See the Truth Table (Table 16) for an explanation of logic states.

When using an L8583D in the make-before-break mode, during the ring-to-idle transition, for a period of up to one-

half cycle at the ringing frequency, the ring break switch and the pnpn-type ring access switch can both be in the on

state. This is the maximum time after the logic signal at IN^RINGhas transitioned that the ring access switch is wait-

ing for the next zero current cross, so it can close. During this interval, current that is limited to the dc break switch

current-limit value will be sourced from the ring node of the SLIC.

Table 13. Make-Before-Break Operation—Part I

RIN TESTin TESTout T^SD

G

State

Timing

Break

Ring

All Other

Access

Switches Return

Access

3 and 4 Switch 7 Switch 8 Switches

5 V

0 V

Float Power

Ringing

Float Make- SW8 waiting for next zero cur-

before- rent crossing to turn off maxi-

break mum time—one-half of ringing.

In this transition state, current

that is limited to the dc break

—

Open

Closed

Open

Closed

Open

switch current-limit value will be

sourced from the ring node of the

SLIC.

0 V

Float Idle/Talk Zero cross current has occurred.

Closed

Open

11

Data Sheet

L8583D Line Card Access Switch

October 2002

Switching Behavior (continued)

Table 14. Break-Before-Make Operation—Part II

INPUT TESTin TESTout T^SD

State

Timing

Break

Ring

All Other

Switches Return Access Switches

3 and 4 Switch 7 Switch 8

5 V

0 V

5 V

Float Power

Ringing

Float All Off Hold this state for ≤25 ms. SW8

—

Open

Closed

Open

Closed

Open

waiting for zero current to turn

off.

5 V

0 V

5 V

Float All Off Zero current has occurred and

Open

SW8 has opened.

0 V

Float Idle/Talk Release break switches.

Closed

Notes:

Break-before-make operation can be achieved using TSD as an input. In lines two and three of Table 14, instead of using the logic input pins to

force the all-off state, force TSD to ground. This will override the logic inputs and also force the all-off state. Hold this state for 25 ms. During this

25 ms all-off state, toggle the inputs from 100 (ringing state) to 000 (idle/talk state). After 25 ms, release TSD to return switch control to the input

pins which will set the idle talk state.

When using the L8583D in this mode, forcing TSD to ground will override the INPUT pins and force an all-off state. Setting TSD to 5 V will allow

switch control via the logic INPUT pins. However, setting TSD to 5 V will also disable the thermal shutdown mechanism. This is not recom-

mended. Therefore, to allow switch control via the logic INPUT pins, allow TSD to float.

Thus, when using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all-off state) and float (allows switch

control via logic input pins and thermal shutdown mechanism is active). This may require use of an open-collector buffer.

Also note that TSD operation in L8583D is different than TSD operation of the L7581, where application of 5 V does not disable the thermal shut-

down mechanism.

Power Supplies

Both the 5 V and battery supply are brought onto the L8583D. The L8583D requires only the 5 V supply for switch

operation; that is, state control is powered exclusively off of the 5 V supply. Because of this, the L8583D offers

extremely low power dissipation, both in the idle and active states. The battery voltage is not used for switch state

control and is only used by the battery monitor circuit.

Loss of Battery Voltage

As an additional protection feature, the L8583D monitors the battery voltage. Upon loss of battery voltage, the

L8583D will automatically enter an all-off state and remain in that state until the battery voltage is restored. The

L8583D is designed such that the device will enter the all-off state if the battery rises above –10 V and will remain

off until the battery drops below –15 V. Monitoring the battery for the automatic shutdown feature will draw a small

current from the battery, typically

4 µA. This will add slightly to the overall power dissipation of the device.

Impulse Noise

Using the L8583D will minimize and possibly eliminate the contribution to the overall system impulse noise that is

associated with ringing access switches. Because of this characteristic of the L8583D, it may not be necessary to

incorporate a zero cross switching scheme. This ultimately depends upon the characteristics of the individual sys-

tem and is best evaluated at the board level.

12

Data Sheet

L8583D Line Card Access Switch

October 2002

Temperature Shutdown Mechanism

Protection

When the device temperature reaches a minimum of

110 °C, the thermal shutdown mechanism will activate

and force the device into an all-off state, regardless of

the logic input pins. Pin T^SD, when used as an output,

will read 0 V when the device is in the thermal shut-

down mode and +V^DDduring normal operation.

Integrated SLIC Protection

Diode Bridge

In the L8583D, protection to the SLIC device or other

subsequent circuitry is provided by a combination of

current-limited break switches, a diode bridge clamping

circuit, and a thermal shutdown mechanism.

During a lightning event, due to the relatively short

duration, the thermal shutdown will not typically acti-

vate.

During a positive lightning event, fault current is

reduced by the dynamic current-limit circuit and

directed to ground via the diode bridge. Voltage is

clamped to a diode drop above ground. Negative light-

ning is again reduced by the dynamic current limit and

directed to battery via the diode bridge.

During an extended power cross, the device tempera-

ture will rise and cause the device to enter the thermal

shutdown mode. This forces an all-off mode, and the

current seen at T^BAT/RBAT drops to zero. Once in the

thermal shutdown mode, the device will cool and exit

the thermal shutdown mode, thus re-entering the state

it was in prior to thermal shutdown. Current, limited to

the dc current-limit value, will again begin to flow and

device heating will begin again. This cycle of entering

and exiting thermal shutdown will last as long as the

power-cross fault is present. The frequency of entering

and exiting thermal shutdown will depend on the mag-

nitude of the power cross. If the magnitude of the

power cross is great enough, the external secondary

protector may trigger shunting all current to ground.

For power cross and power induction faults, the posi-

tive cycle of the fault is clamped a diode drop above

ground and fault currents steered to ground and the

negative cycle of the power cross is steered to battery.

Fault currents are limited by the current-limit circuit.

Current Limiting

During a lightning event, the current that is passed

through the break switches and presented to the inte-

grated protection circuit and subsequent circuitry is lim-

ited by the dynamic current-limit response of the break

switches (assuming idle/talk state). When the voltage

seen at the T^LINE/RLINE nodes is properly clamped by

an external secondary protector, upon application of a

1000 V, 10 x 1000 pulse (LSSGR lightning), the current

seen at the T^BAT/RBAT nodes will typically be a pulse of

magnitude 2.5 A and duration less than 0.5 µs.

In the L8583D, the thermal shutdown mechanism can

be disabled by forcing the T^SDpin to +VDD. This func-

tionality is different from the L7581, whose thermal

shutdown mechanism cannot be disabled.

Electrical specifications relating to the integrated over-

voltage clamping circuit are outlined in Table 15.

During a power-cross event, the current that is passed

through the break switches and presented to the inte-

grated protection circuit and subsequent circuitry is lim-

ited by the dc current-limit response of the break

switches (assuming idle/talk state). The dc current limit

is specified over temperature between 80 mA and

250 mA. Note that the current-limit circuitry has a nega-

tive temperature coefficient. Thus, if the device is sub-

jected to an extended power cross, the value of current

seen at T^BAT/RBAT will decrease as the device heats

due to the fault current. If sufficient heating occurs, the

temperature shutdown mechanism will activate and the

device will enter an all-off mode.

13

Data Sheet

L8583D Line Card Access Switch

October 2002

I |Vringingpeakmax| + |VBATmax| < |Vbreakovermin|.

where:

Protection (continued)

Integrated SLIC Protection (continued)

External Secondary Protector

I VBATmax—Maximum magnitude of battery voltage.

I Vbreakovermax—Maximum magnitude breakover

voltage of external secondary protector.

With the above integrated protection features, only one

overvoltage secondary protection device on the loop

side of the L8583D is required. The purpose of this

device is to limit fault voltages seen by the L8583D so

as not to exceed the breakdown voltage or input-output

isolation rating of the device. To minimize stress on the

L8583D, use of a foldback-type or crowbar-type device

is recommended. A detailed explanation and design

equations on the choice of the external secondary pro-

tection device are given in the An Introduction to L758X

Series of Line Card Access Switches Application Note.

Basic design equations governing the choice of exter-

nal secondary protector are given below:

I Vbreakovermin—Minimum magnitude breakover

voltage of external secondary protector.

I Vbreakdownmin(break)—Minimum magnitude

breakdown voltage of L8583D break switch.

I Vbreakdownmin(ring)—Minimum magnitude break-

down voltage of L8583D ring access switch.

I Vringingpeakmax—Maximum magnitude peak volt-

age of ringing signal.

Series current-limiting fused resistors or PTCs should

be chosen so as not to exceed the current rating of the

external secondary protector. Refer to the manufac-

turer’s data sheet for requirements.

I |VBATmax| + |Vbreakovermax| <

|Vbreakdownmin(break)|.

I |Vringingpeakmax| + |VBATmax| +

|Vbreakovermax| < |Vbreakdownmin(ring)|.

Table 15. Electrical Specifications, Protection Circuitry

Parameters Related to Diodes (in Diode Bridge)

Parameter

Test Condition

Measure

Min

Typ

Max

Unit

Voltage Drop at Continuous Current (50

Hz/60 Hz)

Apply ±dc current limit of

Forward

Voltage

—

3.5

V

break switches

Voltage Drop at Surge Current

Apply ±dynamic current

limit of break switches

Forward

Voltage

—

5

—

V

14

Data Sheet

L8583D Line Card Access Switch

October 2002

Typical Performance Characteristics

+I

RON

dc CURRENT-LIMIT

BREAK SWITCHES

–VOS

VBAT – 3

VBAT

–V

+V

+VOS

<1 µA

3 V

–I

dc CURRENT LIMIT

12-2312 (F)

(OF BREAK SWITCHES)

Figure 5. Switches 6, 8

12-2309 (F).b

Figure 3. Protection Circuit Version

CURRENT

+I

LIMITING

ILIMIT

2/3 RON

RON

1.5 V

–1.5 V

–V

+V

RON

2/3 RON

ILIMIT

CURRENT

LIMITING

–I

12-2311 (F)

Figure 4. Switches 1—5, 7, 9, 10

15

Data Sheet

L8583D Line Card Access Switch

Application

October 2002

VBAT

(REFERENCE)

RINGING

TEST RETURN

SW5

SW9

SW7

SW1

TEST IN

TEST OUT

RINGING

RETURN

R1

TIP

SW3 BREAK

BATTERY

FEED

CROWBAR

BATTERY

MONITOR

PROTECTION

BREAK SW4

RING

R2

RING

SW10

SW8

SW2

RINGING

ACCESS

TEST IN

TEST OUT

SW6

RINGING TEST

RING

GENERATOR

BATTERY

12-2366 (F).g

Figure 6. Typical LCAS Application, Idle, or Talk State Shown

16

Data Sheet

L8583D Line Card Access Switch

October 2002

Application (continued)

Table 16. Truth Table for L8583D

IN^RING

INTESTin

INTESTout

TSD

TESTin

Break

Ring Test

Switches

Ring

TESTout

Switches

Switches Switches

0 V

5 V

0 V

5 V

0 V

5 V

0 V

5 V

0 V

5 V

0 V

5 V

0 V

5 V

5 V/Float¹

0 V²

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

Off³

On⁴

Off⁵

Off⁶

Off⁷

On⁸

Off^9,10

On¹¹

Off⁹

Don’t Care Don’t Care Don’t Care

Off

1. If TSD = 5 V, the thermal shutdown mechanism is disabled. If TSD is floating, the thermal shutdown mechanism is active.

2. Forcing TSD to ground overrides the logic input pins and forces an all-off state.

3. Idle/talk state.

4. TESTout state.

5. TESTin state.

6. Power ringing state.

7. Ringing generator test state.

8. Simultaneous TESTout and TESTin state.

9. All-off state.

10. Device will power up in this state.

11. Simultaneous TESTout—ring test state.

A parallel in/parallel out data latch is integrated into the L8583D. Operation of the data latch is controlled by the

logic-level input pin LATCH. The data input to the latch is the INPUT pin of the L8583D and the output of the data

latch is an internal node used for state control.

When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from

INPUT, through the data latch to state control. Any changes in INPUT will be reflected in the state of the switches.

When the LATCH control pin is at logic 1, the data latch is active; the L8583D will no longer react to changes at the

INPUT control pin. The state of the switches is now latched; that is, the state of the switches will remain as they

were when the LATCH input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT

as long as LATCH is held high.

Note that the T^SDinput is not tied to the data latch. TSD is not affected by the LATCH input. TSD input will override

state control via INPUT and LATCH.

The input logic pins INRING and INTESTOUT have internal pull-up resistors. Input logic pins INTESTIN and LATCH

have internal pull-down resistors. Thus, the device will power up into the disconnect state.

17

Data Sheet

L8583D Line Card Access Switch

Outline Diagrams

October 2002

20-Pin SOG

Dimensions are in millimeters.

Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Legerity Sales Representative.

L

N

B

1

PIN #1 IDENTIFIER ZONE

W

H

SEATING PLANE

0.10

0.61

0.51 MAX

1.27 TYP

0.28 MAX

5-4414 (F)

Package Description

Number of

Pins

Maximum

Width Without

Leads

Maximum

Width

Maximum

Length

(L)

Height

Above

Board

(H)

(N)

Including

Leads

(B)

(W)

SOG (Small Outline Gull-Wing)

20

13.00

7.62

10.64

2.67

18

Data Sheet

L8583D Line Card Access Switch

October 2002

Outline Diagrams (continued)

28-Pin SOG

Dimensions are in millimeters.

Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Legerity Sales Representative.

L

N

B

1

PIN #1 IDENTIFIER ZONE

W

H

SEATING PLANE

0.10

0.61

0.51 MAX

1.27 TYP

0.28 MAX

5-4414 (F)

Package Description

Number of

Pins

Maximum

Width Without

Leads

Maximum

Width

Maximum

Length

(L)

Height

Above

Board

(H)

(N)

Including

Leads

(B)

(W)

SOG (Small Outline Gull-Wing)

28

18.11

7.62

10.64

2.67

19

L8583D Line Card Access Switch

Ordering Information

Device Part Number

LULC8583DEY-D

Description

Line Card Access Switch

Package

20-Pin SOG,

Dry-bagged

Comcode

109058099

LULC8583DEY-DT

Line Card Access Switch

20-Pin SOG,

Dry-bagged,

Tape and reel*

109058115

AGRL8583DAJ-D

AGRL8583DAJ-DT

Line Card Access Switch

28-Pin SOG,

700024229

700024230

Dry-bagged

28-Pin SOG,

Dry-bagged,

Tape and reel*

* Devices on tape and reel must be ordered in 1000-piece increments.

Telcordia Technologies is a trademark of Telcordia Technologies, Inc.

UL is a registered trademark of Underwriters Laboratories, Inc.

Legerity, Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.


型号：	AGRL8583DAJ-D
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	Telecom Circuit, 1-Func, PDSO28, PLASTIC, SOG-28 电信光电二极管电信集成电路
文件：	总21页 (文件大小：454K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AGRL8583DAJ-D [ZARLINK]

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