KESRX05KG1T [ZARLINK]
260 to 470MHz ASK Receiver with Power Down; 260至470MHz ASK接收器，带有掉电
| 型号： | KESRX05KG1T |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 260 to 470MHz ASK Receiver with Power Down |
| 文件： | 总28页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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KESRX05
260 to 470MHz ASK Receiver with Power Down
Preliminary Information
DS5023 Issue 1.9 August 1999
Features
Ordering Information
G In-band Interference Rejection 20dB max.
G 2103dBm Sensitivity (IF BW = 470kHz)
G AGC around LNA and Mixer
KESRX05B/KG/QP1S (anti-static tubes)
KESRX05B/KG/QP1T (tape and reel)
G Low Supply voltage (3 to 6V)
The KESRX05 is a single chip ASK (Amplitude Shift Key)
Receiver IC. It is designed to operate in a variety of low
power radio applications including keyless entry, general
domestic and industrial remote control, RF tagging and
local paging systems.
G 2-Stage Power Down for Low Current Applications
G Interface for Ceramic IF Filters up to 15MHz
G All Pins Meet 2kV Human Body Model ESD
Protection Requirement
G Compliant to ETS 300-220 and FCC Part 15
The receiver offers an exceptionally high level of integration
and performance to meet the local oscillator radiation
requirements of regulatory authorities world wide.
Functionally the device works in the same way as the
KESRX01 with the added features of low supply voltage,
in-band interference rejection (anti-jamming detector), a
2-stage power down to enable receiver systems to be
implemented with less than 1mA supply, and a wide IF
bandwidth and drive stage to interface to an external
ceramic IF bandpass filter at intermediate
Applications
G Remote Keyless Entry
G Security, tagging
G Remote Controlled equipment
Absolute Maximum Ratings
20·5V to 17V
255°C to 150°C
255°C to 150°C
120dBm from 50Ω
Supply voltage, V
Storage temperature,T
Junction temperature, T
RF input power
CC
frequencies from 0·2MHz to 15MHz.
stg
j
The KESRX05 is an ideal receiver for difficult reception
areas where high level interferers would jam the wanted
signal. The anti-jamming circuit allows operation to be
possible with interfering signals which are more than 20dB
stronger than the wanted signal, without the cost penalties
of increased IF selectivity and frequency accuracy.
AGC
RF INPUT
DATA
FILTER
CERAMIC
IF FILTER
RSSI DETECTOR
SLICER
MIXER
ANTI
JAM
LNA
SLICED
DATA
SAW
FILTER
NOISE
REDUCTION
FILTER
LOOP
FILTER
REF
VCO
XTAL
PHASE
DETECTOR
464
PHASE LOCKED LOOP
Figure 1 Typical system application
KESRX05
IFFLT1
IFDC1
IFIN
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IFFLT2
RSSI
DETB
PD
2
3
IFDC2
4
V
5
XTAL1
XTAL2
DF0
CC
IFOUT
RF
6
V
7
CC
KESRX05
MIXIP
RFOP
8
DF1
9
DF2
V RF
EE
10
11
12
13
14
VCO1
VCO2
RFIN
AGC
V
EE
PEAK
LF
DATAOP
DSN
Figure 2 Pin connections (top view)
DESCRIPTION
The single conversion superheterodyne receiver
approach is now generally considered the way forward
for ISM band type applications because of lower cost,
superior selectivity, lower radiation, and flexibility over
other techniques. For power-conscious, hand-held
applications KESRX05 provides improved performance
and flexibility on a lower 3·0V supply and a power down
feature allows faster switch-on times for use in a pulsed
power saving mode.
the performance for a wide range of applications and
locations world wide.
The KESRX05, with its anti-jamming detector circuit, is
an ideal ASK/ OOK receiver for difficult reception areas
caused by interference such as amateur radio repeater
stations and wireless stereo headphones. Operation is
possible with interfering signals which are more than
20dB stronger than the wanted signal (IF bandwidth =
470kHz.), without the cost penalities of increased IF se-
lectivity and frequency accuracy.
Although this is a relatively simple receiver, the flexibility
of using an external IF filter allows the designer to
choose both the selectivity and the IF in order to optimise
Figure 1 is the system block diagram, with an external
ceramic IF filter, SAW fillter and noise reduction filter.
Name
Function
Noise reducing IF filter
Schematic
Pin
1
IFFLT1
A simple LC noise reduction filter (L5 and C7) is
connected between pins 1 (IFFLT1 ) and 28 (IFFLT2)
to reduce the noise contribution from the earlier
stages of the logathrimic amplifier. The LC filter helps
to reduce the bandwidth of the log amplifier from
approximately 45MHz to typically 1MHz, preventing
wideband noise from being detected as a signal. To
reduce the Q of the simple LC circuit, an external
damping resistor in parallel with L5, C7. However,
the preferred method to a damping resistor is to lower
the Q of L5 or increase the tolerances of L5 and C7.
V
CC
10k
10k
IFFLT1
IFFLT2
For further information refer to the
IFAmp/RSSIDetector sectionoftheFunctionalDescription.
Table 1 Pin descriptions
Cont…
2
KESRX05
Name
Function
Schematic
Pin
2
IFDC1
Log Amplifier DC Blocking Capacitor
Capacitors C3 and C4 provide DC blocking within
the high gain stage of the log amplifier. The log
amplifier has a small gain of greater than 80dB
between pins 3 (IFIN) and 27 (RSSI output)
Capacitors C3 and C4 eliminate DC offsets, allowing
the amplification of AC signals only.
181k
3·1k
181k
IFDC1
IFDC
950
IFIN
For further information, refer to the IFAmp/RSSI De-
tector section of the Functional Description.
3
IFIN
Log Amp Input (IFamplifier input)
INTERNAL
181k
C3
IFDC1
The bandwidth of KESRX05 is set by the external
ceramic filter CF1. Impedance matching from the
output of the ceramic filter to the input of the log
amplifier is achieved by an external shunt resistor
R9 in parallel with an internal resistor.
R9
3·1k
IFIN
FROM
CF1
For further information please refer to the IF Interface
section of the Functional Description.
Matching circuit for CF1
See pin 2
4
5
6
IFDC2
Log amplifier DC stability capacitor
Positive supply
V
CC
IFOUT
IF output
The IF output drive is a voltage drive with a low output
impedance of 300Ω via an internal series resistor.
The IFOUT pin is designed for direct connection to
an external 10·7MHz FM ceramic filter with a typical
input impedance of 300Ω.
300
IFOUT
50µA
For further information refer to the IF Interface section
of the Functional Description.
7
8
V
RF
Positive supply for RF circuits
CC
MIXIP
Mixer input
To a first order approximation the input impedance
of the mixer at UHF frequencies is set by the internal
bias resistor and capacitor network. Effects of internal
and external stray parasitics ignored.
MIXIP
2k
2p
V
RF
EE
For further information refer to the AC Electrical
Characteristics.
Table 1 Pin descriptions (continued)
Cont…
3
KESRX05
Name
RFOUT
Function
Schematic
Pin
9
Output from internal RF amplifier
RFOP
300
The RF amplifier has a high output impedance. The
internal 300Ω resistor is used to improve the ESD
protection of RFOUT.
For further information refer to the AC Electrical
Characteristics.
240µA
(AGC OFF)
10
11
V
RF
Negative supply for RF circuits
EE
RFIN
nternal input RF amplifier
240µA
To a first order approximation the input impedance
of the RF amplifier at UHF frequencies is set by the
internal bias resistor and capacitor network. Effects
of internal and external stray parasitics ignored.
RFIN
1k
5p
830
10p
V
RF
EE
For further information please refer to the AC
Electrical Characteristics.
12
AGC
RF AGC time constant
The attack and decay time constant of the AGC is
set by the internal series resistor, current sink and
the external capacitor C8. Increasing the decay time
constant of the AGC circuit will impair the time to
good data of the receiver from power up PD0 to PD2.
360
AGC
6µA
For further information please refer to the IF Amp/
RSSI Detector section of the Functional Description.
13
PEAK
Data signal peak detector output
The peak detector output is designed to be a low
impedance output. The peak detector monitors the
peak of the signal at pin 20 (DF2).
300
190k
PEAK
For further information please refer to the Baseband
section of the Functional Description.
V
EE
14 DATAOP Sliced data output
The data output is the inverted sense of the input
HIGH
LOW
120µA
220µA
DATAOP
signal at pin 20 (DF2) and is designed as a high im-
pedance output via two internal sink and source cur-
rent generators
Table 1 Pin descriptions (continued)
Cont…
4
KESRX05
Name
Function
Data slice reference level
Schematic
Pin
15
DSN
DF2
The DSN pin is defined internally by the Slice volt-
age V . The DSN slice voltage can be offset from
REF
3k
3k
the internal reference V
by connecting a resistor
DSN
100k
REF
from the DSN pin to V and/or the peak detector
EE
output.
VREF
HYSTERESIS
25mV
(V
)
BE
For further information please refer to the Baseband
section of the Functional Description.
V
EE
16
LF
PLL loop filter connection
UP
The phase detector output current is derived by two
internal current sources. The nominal linear average
output current is 115µA (5µA/radian).
115µA
LF
DOWN
215µA
For further information please refer to the Phase Lock
Loop VCO section of the Functional Description
17
18
V
Negative supply
EE
VCO2
Voltage controlled oscillator
V
CC
1·4k
50
1·4k
The voltage controlled oscillator circuit is designed
from two cross coupled transistors. The centre fre-
quency of the VCO is set by the external tank circuit.
50
VCO1
VCO2
For further information please refer to the Voltage
Controlled Oscillator (VCO) Circuit Design / Layout
section of the Functional Description
300µA
See pin 18
19
20
VCO1
DF2
Voltage controlled oscillator
Data Filter Output
DF2
The data filter is configured as a unity gain amplifier
with a low impedance output. Tracking of the received
baseband signal is achieved by an internal current
source.
3k
3k
DSN
100k
VREF
(V
HYSTERESIS
25mV
)
For further information please refer to the Baseband
section of the Functional description.
BE
V
EE
21
DF1
Data filter input
Input to data filter. Bandwidth of second order Sallen
and Key data filter is set by external components
R10, R1 1, C5 and C6.
DF1
For further information please refer to the Baseband
section of the Functional Description.
Table 1 Pin descriptions (continued)
Cont…
5
KESRX05
Name
Function
Schematic
Pin
22
DF0
Anti-jam detector circuit output
DF0
7µA
23
XTAL2
Crystal oscillator input
V
CC
6k
This pin is directly connected to the base of the
Colpitts oscillator input transistor. The value of the
feedback capacitors C13, C14 connected between
XTAL1 and XTAL2 are set by the parallel load
capacitance of the external crystal. Connecting a
200kΩ resistor from XTAL 1 to ground (in parallel
with C14 ) will maintain oscillation of the crystal in
PD0 mode but increase the receiver current
consumption by approx 20µA.
12k
XTAL2
XTAL1
18·7k
200k
42µA
See pin 23
24
25
XTAL1
PD
Crystal oscillator input
Power down input
V
CC
This tristate input pin is designed to power-up the
device in two modes PD0 to PD2 and PD1 to PD2.
300k
PD
For further information please refer to the Functional
Description.
124k
V
EE
26
27
28
DETB
Anti-jam detector input
V
CC
DETB input is configured as a high impedance input
where the signal is DC restored on the peak of the
signal, with the aid of capacitor C10.
3µA
DETB
For further information please refer to the Anti
Jamming Circuit
RSSI
RSSI output
The RSSI output is configured as a low impedance
output. Tracking of the receive baseband signal is
achieved by an internal current source. See pins 3
and 11.
For further information please refer to IF Amp/RSSI
Detector
RSSI
7µA
V
EE
See pin 1
IFFLT2
Noise reducing IF filter
Table 1 Pin descriptions (continued)
6
KESRX05
Electrical Characteristics – Test Conditions
These characteristics are guaranteed by either production test or design over the following range of operating conditions
unless otherwise stated: TAMB = 240°C to 1105°C, VCC = 3·0V to 6·0V
Value
Characteristic
Symbol
Units
Conditions
Min. Typ. Max.
Supply voltage
VCC
3·0
6·0
V
Ambient temperature
Test frequency
TAMB
240
1105
°C
MHz
470
Local oscillator frequency configured for
high side injection, except where
otherwise specified (Note 9)
240°C to 185°C
Local oscillator frequency
VCO
480·7
550
470
MHz
MHz
240°C to 1105°C
DC Electrical Characteristics
These characteristics are guaranteed by either production test or design over the following range of operating conditions
unless otherwise stated: TAMB = 240°C to 1105°C, VCC = 3·0V to 6·0V, application circuit Figure 25
Value
Characteristic
Symbol
Units
Conditions
Typ. Max.
Min.
Supply Current
Receive mode (PD2)
Power down 1 (PD1)
ICC
ICC1
3·9
0·35 0·55
5·5
mA
mA
All. PD = high, RF input ,250dBm (Figure 24)
All. PD = VCC/2 or high impedance source
VCC = 3·0V to 6·0V (Note 4 and Figure 20)
All. PD = VEE (Figure 22)
Power down 2 (PD0)
ICC2
29
57
µA
AC Electrical Characteristics (1)
These characteristics are guaranteed by either production test or design over the following range of operating conditions
unless otherwise stated: TAMB = 240°C to 1105°C, VCC = 3·0V to 6·0V, application circuit Figure 25
Value
Characteristic
Symbol
Units
Conditions
Typ. Max.
Min.
Input frequency range
Intermediate frequency
Test fixture functionality
fS
IF
VIN(MIN)
260
0·2
470
15
MHz All (Notes 9 and 10)
MHz All (Notes 8 and 11)
8·0
23 µVrms 20kb/s data rate at 470MHz (Note 1)
(289) (280) (dBm)
Sensitivity (application),
receiver BW = 470kHz
Sensitivity (application),
receiver BW = 50kHz
Overload performance
PLL control line (pin 16) to
achieve 90% of final value
PD1 and PD2
VIN(MIN)
1·5
1·12 0·89 µVrms 2kb/s data rate, VCC = 5V,
(2103) (2106) (2108) (dBm) f0 = 433·92MHz (Figure 19, Notes 3 and 11)
VIN(MIN) 0·79
0·56 0·45 µVrms 2kb/s data rate, VCC = 5V,
(2109) (2112) (211 4 ) (dBm) f0 = 433·92MHz (Figure 20, Notes 10 and 11)
VIN(MAX) 0·5
2·23
3·5
Vrms 20kb/s data rate at 470MHz (Note 2)
tS2
2·0
6·0
1·5
ms
All, local oscillator low side injection
423·33MHz, VCC = 5V (Figures 7 and 18,
Notes 5 and 11)
PLL control line (pin 16) to
achieve 90% of final value
PD1 and PD2
tS3
0·20
0·35
ms
All, local oscillator low side injection
423·33MHz, VCC = 5V (Figures 7 and 18,
Notes 5 and 11)
Data output voltage high
Data output voltage low
Conducted emissions
VOH VCC20·7
VOL
Antenna
(LO)
Jam
V
V
IOH = 120µA (Figure 20)
0·7
IOL = 220µA (Figure 20)
5·6
(292)
mVrms All, LO low side injection 423·33MHz, with
(dBm) SAW filter (Figure 26, Notes 6 and 11)
100 mVrms All, LO low side injection 423·33MHz, SAW
(260) (dBm) filter removed (Figure 25, Notes 6 and 11)
Anti-jam rejection
112 120
dB
VCC = 5V (Figure 8, Notes 7 and 11)
7
KESRX05
AC Electrical Characteristics (2)
These characteristics are typical values measured for a limited sample size. They are not guaranteed by production test.
They are only given as a guide to assist in the design-in phase of KESRX05 (refer to Note 11)
All characteristics measured at TAMB = 25°C and VCC = 5V unless otherwise stated.
Value
Characteristic
Symbol
Units
Conditions
Min.
Typ. Max.
Internal RF Amplifier
Parallel input impedance
RFIN
RFOUT
NF
2·8//1·8
1·78//1·7
10//1·1
18//1·1
4·5
kΩ//pF fS = 434MHz
kΩ//pF fS = 315MHz
kΩ//pF fS = 434MHz
kΩ//pF fS = 315MHz
Parallel output impedance
Noise figure
dB
fS = 434MHz, matched 50Ω environment
input and output
Noise matching impedance
1dB compression point
RFIN
RFIN
1·0//4·6
220
kΩ//nH fS = 434MHz
dBm Input referred, fS = 434MHz, matched 50Ω
environment input and output
Amplifier gain
RFAMP
MIXIP
13
dB
fS = 434MHz, output matched to mixer
input impedance
Mixer
Parallel input impedance
1·6//1·8
1·6//1·8
300
kΩ//pF fS = 434MHz
kΩ//pF fS = 315MHz
Ω
dB
Output impedance
IF1
NF
fS = 10·7MHz
Noise figure (double
sideband measurement
Mixer conversion gain
10
fS = 434MHz, matched 50Ω
environment input and output
fS = 434MHz,fS = 434MHz, measured at
input to ceramic filter. Include 6dB matching
loss
AMIX
9
dB
IF Strip (RSSI)
IF input impedance
IF gain of log amp
IFIN
ALOG
3·1
80
kΩ
dB
fS = 10·7MHz
All (Figures 14 and 15)
NOTES
1. The Sensitivity of the test fixture is degraded by loading the input to RF amplifier with 50Ω, lack of image rejection and increasing the data filter
bandwidth from 5 to 50kHz Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0·01
where the input signal is a return to zero pulse at 470MHz,with an average duty cycle of 50%, 20kb/s data rate with the receiver bandwidth set to
470kHz.
2. Peak RF input level, pin RFIN, to overload the demodulator with the AGC operating. Equivalent to 17dBm for 50Ω input impedance, Where the
input signal is a return to zero pulse at 470MHz with an average duty cycle of 50% and 20kB/s data rate with the receiver bandwidth set to 470kHz.
3. Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0·01 where the input signal is a
return to zero pulse with an average duty cycle of 50%, 2kb/s data rate. Equivalent to 2103dBm for 50Ω input impedance. Does not include
insertion loss of SAW filter at RF input but does include IF filter of 470kHz 3dB bandwidth and a data filter bandwidth of 5kHz. The results shown
in Figure 20 and in the AC Electrical Characteristics (1) on page 7 are with the simple LC circuit L5//C7 tuned correctly to 10·7MHz.
4. The performance of the power down option PD1 to PD2 cannot be guaranteed below 3V for temperatures less than 0°C. However, the time to
good data of PD0 to PD2 can be improved by connecting a 200kΩ in parallel wth C14 (see Table 1, pin 23).
5. Time taken for PLL lock voltage to achieve 90% transition point of the control signal and the VCO frequency to achieve within 470kHz of the final
frequency. The time taken to acquire PLL acquisition is governed by the PLL loop filter (C12, C1 and R2) and the crystal oscillator components
(XTAL1, C13 and C14). The dominant term for PLL aquistion is the start-up time of the crystal oscillator circuit, provided the PLL loop filter settling
time is much less than the crystal oscillator start-up time. Figure 7 illustrates a suitable test setup for measuring the acquisition time of the PLL and
the results are shown in Figure 18. The electrical characterisation parameters are based on the following sets of conditions:
Crystal oscillator circuit
Ident Value
C13 = C14 15pF
PLL loop filter
Ident
C12
C1
Value
1·5nF
180pF
10kΩ
XTAL1
ESR
L
6·6128MHz
15·3Ω
R1
85·36mH
1·83pF
6·8pF
C0
C1
The performance of the crystal oscillator can be improve by increasing the value of ESR (100Ω max.) or bt maintaining the crystaloscillator in PD0
mode by connecting a 200kΩ resistor in parallel with C14 (see Table 1, pin 23). The typical time to valid data of the receiver at a data rate of 2kb/s
is shown in Figure 17, which is accurate to 6250µs since the duration of the SPACE at 2kb/s = 250µs.
6. Local oscillator power fed back into 50Ω source at antenna input (RF input). Measured with RF input matching network shown in Figures 25 and 26.
8
KESRX05
NOTES (continued)
7. In-band interference rejection for an unmodulated interfering signal at 100kHz low side from the wanted modulated signal at 433.92MHz to
achieve a Bit Error Rate = 0·01. Figure 6 illustrates a suitable test set-up for measuring the interference rejection and selectivity of the receiver.
Wanted signal = 290dBm at 433·92MHz (2kb/. 50% duty cycle), interfering signal = 278dBm at 433·82MHz. (unmodulated). Interference rejection
typically equals +12dBm i.e. in-band interfering signal is 12dBm above the wanted signal level at -90dBm.
8. Actual intermediate frequency determined by choice of crystal and external ceramic filter.
9. For temperatures between 85°C and 105°C the maximum frequency of operation of the VCO local oscillator must be limited to 470MHz. The
recommended components to limit the maximum free running frequency of the VCO to less than 470MHz, for an operating supply range of
5V65%, are:
Ident
D1
C11
C18
L2
Value
BB833
6·8pF
10pF
Tolerance
69%
60·1pF
60·1pF
62%
39nH
The component values recommended in Tables 5 and 6 are to allow the KESRX05 to operate below VCC = 3V by maintaining the PLL lock voltage
at approximately 1·5V (VCC/2) so that the VCO maximum free running frequency can exceed 470MHz. Thus, the recommended VCO component
values for D!, C11, C18 and L2 given in Tables 5 and 6 cannot be used at temperatures above 85°C.
10.Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error rate of 0·01 where the input signal is a
return to zero pulse with an average duty cycle of 50%, 2kb/s data rate. Equivalent to 2109dBm for a 50Ω input impedance. Does not include the
insertion loss of a front end SAW filter at the R F input but does include the IF filter of 50kHz 3dB bandwidth and a data filter bandwidth of 5kHz.
The results shown in Figure 20 and in the AC Electrical Characteristics (1) on page 7 are with the simple LC circuit L5//C7 tuned correctly to
10·7MHz.
11.This parameter is not 100% tested by production.
FUNCTIONAL DESCRIPTION
Power Down
The PD pin, a tristate input, provides a 2-stage power down
for the receiver. The receiver is fully operational when the
pin is held high and is fully powered down when the pin is
taken to ground as shown in Table 2.
an antenna or to an input SAW filter with a maximum
insertion loss of 3dB. The RF amplifier gain is about 1 3dB
at 460MHz when matched into the mixer, while the RF
amplifer noise figure is about 4·5dB when fed from a 50Ω
source. The internal RF amplifier feeds a double balanced
mixer through an external impedance matching circuit,
RFOP to MIXIP.
Pin 25
Status
PD0
PD1
PD2
Low (0V) Receiver powered down
VCC/2
Crystal oscillator running
High (VCC) Receive mode
The AGC circuit monitors the mixer signal output level.
Control is fed back, applying AGC to the RF amplifier to
prevent overloading in the mixer and the generation of
unwanted distortion products. This also has the effect of
reducing the RSSI characteristic slope and extending its
range of operation by more than 20dB at high signal levels
(Figure 13).
Table 2
PD0 = Low
None of the receiver circuits are functional. Current ICC2,
is reduced to its lowest level of ,50µA (VCC applied). A
longer settling time (tS2) is required to restore full
performance after switching to receive mode PD0 to PD2
(Figures 7, 17 and 18). The settling time (time to valid data)
of the receiver can be improved by maintaining the
oscillation of the crystal in PD0 mode by placing a 200KΩ
resistor in parallel with C14. The addition of this resistor
will increase the current consumption of the receiver by
approximately 20µA (see Table 1, pin 23).
The AGC circuit also applies mixer booster current to
improve the linearity of the mixer at high signal levels. This
can be confirmed by monitoring the current consumption
of the receiver with applied RF signal level (Figure 16).
The AGC circuit comes into operation at mixer output
signals greater than approximately 225dBm and reduces
the RF amplifer gain by 6dB at an input signal level of
approximaely 230dBm. Since the AGC operates on the
mixer output signal level then the exact point where the
AGC comes into opera tion depends on the RF amplifer to
mixer matching circuits and RF amplifer gain.
PD1 = VCC/2 or High-Z source (CMOS tristate)
A non-receiving state with some critical circuits running
including the crystal oscillator. Current consumption ICC1,
is reduced to about 330µA. When switching to the receive
state, PD1 to PD2 (Figures 7, 17 and 18), data can start to
be recovered within 1ms (tS2) for signals close to maximum
sensitivity.
IF Interface
Unlike KESRX01 there is no internal integrated IF filter.
This is to provide a more flexible design and allows the
system designer to use a low IF or high IF up to 15MHz.
Typically, a 10·7MHz ceramic IF filter connected between
IFOUT and IFIN would be used together with an input RF
SAW filter to give very good image channel rejection. The
PD2 = High
The receiver is fully functional and ready to receive data.
RF Down-Converter
An internal RF amplifier is designed to interface directly to
9
KESRX05
choice of bandwidth for the 10·7MHz ceramic filter depends
on frequency tolerancing of the transmitter, receiver, data
rate and component cost.
4. Note that the LO level is ,,265 dBm, range = 300 to
500MHz.
5. Vary the value of the PSU input to confirm that there is
a corresponding change in LO frequency. Set the PSU
at VCC/2. If the VCO does not oscillate at VCC/2, char-
acterise the LO at an alternative voltage.
The IF filter drive, IFOUT, is a voltage drive with a 300Ω
series resistance (see Table 1, pin 6). This allows
impedance matching to the ceramic IF filter to be set by
an external series resistor. A 10·7MHz ceramic filter with,
typically, a 300Ω input impedance does not require an
external matching resistor at IFOUT.
6. Using a plot of the varactor characteristic determine
the varactor capacitance at VCC/2. e.g. for a 2V VCC
design the Siemens BB833 capacitance at 1V = 10pF
(approx.).
The input to the log amp, IFIN, is high impedance with an
internal 3kΩ shunt resistor. Impedance matching to the
output of the ceramic filter is achieved by an external shunt
resistor R9 between IFIN and IFDC1 (see Table 1, pin 3).
7. Using the following equation deduce the value of the
total stray parasitic capacitance CP.
1
CP =
Phase Lock Loop VCO
~2p3fLO23L2!2C
V
@
#
The local oscillator (LO) is a VCO locked to a crystal
reference by a phase lock loop (PLL). The VCO gain is
nominally 26MHz/V depending on the external varactor
used. The LO frequency is divided by 64 and fed into the
phase-frequency detector, where the reference frequency
is provided from the crystal oscillator. The AC phase
detector output current into the PLL loop filter is nominally
615µA. The maximum loop filter bandwidth is 50kHz.
where CV = varactor capacitance at VCC/2
8. Using the following equation select the nearest value
for L2 to centre the VCO at VCC/2.
1
L2 =
2
~2p3fLO !3~CP1CV!
9. By varying the PSU voltage confirm that the LO is
centred correctly at VCC/2, and that the oscillator
operates over the range 0V to VCC.
10. Disconnect the PSU and reconnect R1. Measure the
value at LF output using a 310 probe and an
oscilloscope. This should be a direct voltage with no
ripple at VCC/2 (60.3V). If not repeat steps 1 to 8. To
compensate for non standard inductor values vary the
value of C18 and C11 to vary the capacitance of the
varactor to centre the VCC at VCC/2.
VCO Circuit Design and Layout
The Local Oscillator (LO) frequency is controlled by a
parallel resonant tuned circuit. The frequency of the local
oscillator is controlled by a Phase Locked Loop (PLL),
referenced to the crystal frequency.
Designing for VCO Track Parasitics
To remove the effect of track parasitics the following pro-
cedure should be adopted.
1. Open circuit the control feed back from the PLL con-
trol loop by removing R1.
NOTE: It is important to minimise stray capacitance in
the VCO circuit to ensure that the VCO starts oscillat-
ing. The use of a varactor with a low capacitance at
zero bias is advisable. Similarly, reducing the values of
C11 and C18 whilst increasing L2 will help to reduce
the capacitance of the varactor at 0V, improving the re-
liability of the oscillator. A compact design methodology
is recommended for the VCO circuit components L2,
C11, C18 and D1.
2. Connect an external Power Supply Unit (PSU = VCC/ 2)
in place of R1, LF output (Figure 3).
3. Using a spectrum analyser, monitor the LO level at
the RFIN port. Alternatively use a small pick-up coil to
loosely couple to the signal generated across L2.
10
KESRX05
KESRX05
C11
C18
R4
19
VCO1
VCO2
VCO
D1
L2
18
CONNECTOR
CHARACTERISATION
+
-
464
R
TEST
PSU
(=R1)
R1
XTAL1
16
LF
PHASE
DETECTOR
C12
C1
23/24
XTAL1/2
R2
Figure 3 Characterising the VCO/PLL operation
IF Amp/RSSI Detector
This is a log amplifierwith a small signal gain .80dB and
an RSSI output used as the detector. The 3dB bandwidth
of the IF log amplifier is typically 45MHz to allow for high
IFs to be used. However, normally, this wide IF bandwidth
would limit the overall sensitivity of the receiver due to the
amplified wideband noise generated in the first IF stage.
Since the RSSI detector is not frequency selective, any
wide band noise introduced after the intermediate filter CF1
will be detected as signal. A simple LC noise reduction
filter is therefore positioned part way down the log amplifier
to reduce the noise power from the earlier stages. Typically
this filter only needs to be a fixed component parallel LC
filter (L5 and C7) between pins IFFLT1 and IFFLT2 with a
1 MHz bandwidth (i.e. Q ~10). There are two internal 20kΩ
damping resistors across these pins which will determine
the Q and the choice of L and C values (AC equivalent
circuit = 20kΩ), i.e:
path to remove any DC voltage offsets at the output of the
high gain log amplifier, RSSI pin 27. Further improvement
in sensitivity can be gained by increasing the Q of the
parallel LCfilter, provided that tolerancing of the LC filter is
taken into account.
For a low IF receiver, ,1 MHz, a low pass filter can be
used for both the IF and noise reduction filter. Such a
receiver, however, will have virtually no image rejection
capability, and will thus have a 3dB penality in noise factor,
impairing the ultimate sensitivity of the receiver by a
minimum of 3dB.
The RSSI output transfer characteristic, at the RSSI pin,
has a slope of about 16mV/d B. A typical transfer
characteristic from RFIN input to RSSI output is plotted in
Figures 14 and 15, measured with a constant wave (n0
modulation RF input signal. This shows the effect of the
AGC in extending the range of the detector to .110dBm
RF input signal and includes the effect of the AGC circuit
adapting to this signal level.
23104
2pfIF Q
1
L =
C =
(2pfIF)2 L
An external damping resistor can be used to lower the Q
of the tuned LC circuit. This will alter the gain of the log
amplifier, i.e., slope and gradient of Figure 15. The objective
of the damping resistor is to prevent mis-tuning of the LC
circuit due to component tolerancing and thus degrading
the sensitivity of the receiver. The sensitivity results shown
in Figures 19 and 20 and in theAC Electrical Characterisics
(1) apply with no external damping resistor and the LC
circuit correctly tuned to 10·7MHz. The preferred alternative
to a damping resistor is to lower the Q of the the inductor
L5 or to increase the tolerance of C6.
Because the RF amplifier AGC has a fast attack time and
slow decay time characteristic, the gain of the stage
remains constant during the data burst. This means that
the change in output for a given extinction ratio also remains
constant at approximately 16mV/dB up to peak input signal
levels .110dBm. This requires the decay time constant
to exceed the transmitted bit period and no long period of
zero signal power has been transmitted.
Increasing the decay time constant of the AGC circuit by
increasing the value of C8 will impair the settling time (time
to good data) of the receiver. When duty cycling the
A ceramic resonator or filter is not a recommended here
as the external LC filter provides a low impedance DC
11
KESRX05
operation to the receiver between PDO and PD2 to lower
power consumption of the receiver. When Duty cycling
the receiver between PD1 and PD2 the settling time of the
receiver is independent of C8. In the application circuit
Figures 25 and 26 the value of C8 is configured for
minimum settling time. The times to valid data with C8 =
10nF are shown in Figure 18 for PD0 to PD2 and PD1 to
PD2.
the data rate or increasing the mark/space ratio will require
a corresponding increrase in the value of C10.
Figure 6 illustrates a suitable test setupforcharacterising
the interference rejection and selectivity of the receiver.
Figure 8 illustrates the in-band interference rejection with
the anti-jam circuit connected as shown in Figure 10 and
bypassed (Figure 11) at VCC = 3V and TAMB = 25°C. Note
the improvement in interference rejection between the two
modes of operation over the wanted signal range of 294
to 0dBm. Note also the 40dB improvement in signal
handling capability with the anti- jam circuit connected and
the 20dB improvement with the SAW filter removed
Anti-jamming Circuit
The output of the RSSI isAC coupled by C10 into theAnti-
jamming circuit where the signal is DC restored on the
peak signal level (Figure 10). The coupling capacitor
charges to the appropriate DC level, which is related to
the final slice level for the data comparator. The anti-
jamming circuit amplifies the peak of the signal to recover
the data signal component even in the presence of
jamming signals. The interferer causes modulation of the
wanted signal at the beat frequency of the two signals and
reduces the amplitude of the wanted data component
making it more difficult to recover. The action of the anti-
jamming circuit centres the bandwidth of the receiver
around the wanted signal proportional to the data filter
bandwidth to suppress the interfering beat frequency
recovering the wanted signal. Bypassing the anti-jamming
circuit (Figure 11) will result in data corruption for interfering
RF signal levels 6dB below the wanted signal (Figures 8
and 9).
Figure 9 illustrates the difference in receiver selectivity with
the ant-jam circuit connected and bypassed. Note the
improvement in receiver selectivity between the two modes
of operation over the frequency range 433·92MHz 65kHz
and the ability of the anti-jam circuit to improce the
selectivity of the SAW filter over the frequency range
433MHz to 434·5MHz. Also note the 20dB improvement
in the in-band signal handling capability demonstrated in
Figure 8 with the SAW filter not used. This can be used to
improve the out-of-band blocking capability of the
application without SAW filter (Figure 25); this design option
can reduce the overall cost of the receiver by, typically, 1
to 2 US Dollars.The selectivity curve with the anti-jam circuit
by-passed is governed by the response of the front end IF
ceramic filter, secondary IF filter and data filter.
The DC restoration circuit has a fast attack time and slow
decay time, both controlled by the value of coupling
capacitor chosen between RSSI and DETB pins. Reducing
Figures 8 and 8 were recorded with the component
specifications given in Table 3.
Component specification (Figure 10)
Component specification (Figure 11)
R6
C2
R6
C2
130kΩ
270pF
12kΩ
N/A
L5//C7
Data filter BW
IF BW
L5//C7
Data filter BW
IF BW
1MHz at 10·7MHz
5kHz
470kHz
1MHz at 10·7MHz
5kHz
470kHz
SAW BW/No SAW BW
OOK modulation
SAW BW/No SAW BW
OOK modulation
750kHz/1MHz
2kb/s (50% duty cycle)
750kHz/1MHz
2kb/s (50% duty cycle)
Table 3 Component specification for Figures 10 and 11. The values given are changes from those given in Table 5
necessary to obtain the results shown in Figures 8 and 9.
12
KESRX05
Improving Anti-Jamming Performance
G
Interference rejection (dB) = Interferer (dBm)2Wanted
(dBm). The interference rejection of the receiver for
different modulation schemes can be improved by:
for sensitivity, squelch and optimum interference rejection
the slice level can be offset from the internal reference by
a high value resistor from the DSN pin to Vee and/or the
peak detector output (Figures 25 and 26).
G
G
Changing the value of C2. Increasing the value of C2
may result in pulse stretching of the recovered signal.
The data comparator (slicer) output, DATAOP, is CMOS
compatible but is only capable of driving small capacitive
loads, ,20pF, depending on data rate. With the anti-jam
circuit connected, data output has the inverted sense of
the input signal at DF2.
Adjusting the comparator reference level (DSN) by
offsetting the internal reference (Figure 6) by a high
value resistor from the DSN pin to VEE and or the peak
detector output. (Figures 25 and 26).
To invert the sense of the data output with the anti-jam
circuit connected, the buffer transistor circuit shown in
Figure 4 can be used.
G
G
Reducing the bandwidth of the data fillter, intermediate
frequency filter CF1 and/or the noise reduction filter
(L5 C7). Thebandwidth of the receiver must
accommodate tolerancing of the data, transmitter and
receiver.
V
CC
R
BIAS
C
IN
Increasing the value of AGC capacitor C8 to maintain
the level of theAGC controi during the off period of the
wanted modulation signal. This will improve the
interference rejection of the receiver but increase the
time to good data from power-up PD0 to PD2. The
application circuit Figure 26 has been optimised for
time to good data.
FROM
DATAOP
BUFFERED
DATAOP
R
IN
R
OUT
V
EE
Figure 4
G
Changing the value of C10 to allow the anti-jam circuit
to detect/recover alternative data modulation schemes
such as PWM.
Data state
Buffered state
High
Low
Data
Data
Low
High
VEE
VCC
Baseband
Table 4
The RSSI output will contain wide band demodulated noise
and signals which are within the RF and IF filter pass bands.
An additional low pass data filter is therefore used to
improve overall sensitivity.
NOTE
Buffered DATAOP will squelch low if the input data signal
remains continuously in a high or low state. The time taken
for the buffered data output to squelch low is governed by
the time constant CINRIN.
KESRX05 has an integrated second-order Sallen and Key
data filter whose characteristic is set by R10, R11, C5 and
C6. Figure 10 showsthe connections and calculation for
the 23dB cut-off frequency and filter type. The cut-off
frequency is determined from the data rate and the level
of pulse distortion which can be tolerated. The data filter
cut off frequency is usually set at 3 to 5 times the minimum
pulse width period, i.e:
The output drive current is nominally 650µA so that a
system using high data rates or higher capacitive loads,
e.g. Iong track lengths, may need to incorporate a buffer
transistor to provide the necessary edge speeds to the
following logic circuits.The comparator has 20mV
hysteresis built-in to reduce edge chatter.
1
fC = 53
The sense of the squelch on the data output is low when
no signal is present. This may be confusing, as a low output
during the data burst also corresponds to the on period,
i.e. the MARK, of the RF OOK signal. However, it is the
very first pulse of the data signal which causes the DC
restoration capacitor of the anti-jamming circuit to charge
to the correct level appropriate to the final slice level. As a
consequence of this the very first pulse of the data
transmission may be lost as the receiver adapts to the
incoming signal level.
Data pulse width
The output from this filter, DF2, is directly coupled into the
inverting input of the data comparator with a fixed slice
level applied to the non-inverting input, DSN. A peak
detector recovers the signal amplitude on the capacitor.
Normally, the comparator reference level used is the
internal reference, a capacitor at Pin DSN serving to
remove noise pick-up. In order to fine tune the slice level
13
KESRX05
IFDC1
IFFLT2
RFOP
MIXIP
IFOUT IFIN
IFFLT1
IFDC2
RSSI DETB
DF0DF1
DF2
V
RF
CC
9
8
6
2
1
28
4
2
27
26
22
21
20
7
13
PEAK
PEAK
DET
ANTI-JAM
DATA
FILTER
14
15
DATAOP
DSN
12
11
AGC
RFIN
AGC
LOG AMP
DATA
SLICER
PHASE/
FREQUENCY
DETECTOR
464
100k
+
-
LNA
REFERENCE
VCO
V
REF
CRYSTAL
OSCILLATOR
25
5
17
18
19
16
23
24
10
PD
V
CC
V
EE
V
EE
RF
VCO1
LF
XTAL2
XTAL1
VCO2
Figure 5 Block schematic of KESRX05
VARIABLE
DELAY LINE
PULSE
GENERATOR
4kb/s
50% DUTY CYCLE
RX CLK
OOK
INPUT
BUFFER
AMPLIFIER
KESRX05 PCB
BIT ERROR
RATE
ANALYSER
SIGNAL
GENERATOR
1
WANTED
SIGNAL
433·92MHz
RF
NC RFIN GND
GND
V
CC
DATA PD NC
NC
TRIGGER
SIGNAL
GENERATOR
2
INTERFERING
SIGNAL
433·82MHz
RFIN
DATA O/P
HYBRID
COMBINER
OSCILLO-
SCOPE
DC PSU
3V TO 6V
NOTES
1. Variable delay line used to equalise the propagation delay of the receiver.
2. Buffer amplifier used to drive the low input impedance of the Bit Error Rate analyser.
3. High impedance (310) oscilloscope probe recommended.
Figure 6 Characterising selectivity and interference rejection
SPECTRUM
KESRX05 PCB
ANALYSER
PLL
RF
OSCILLO-
SCOPE 1
6470kHz
NC RFIN GND
GND
V
CC
DATA PD NC
NC
t
POWER DOWN
TRIGGER
POWER DOWN SWITCH
(SEE TABLE 2, PAGE 9)
DC PSU
3V TO 6V
NC
NOTES
1. High impedance (310) oscilloscope probe recommended.
2. Loosely coupled antenna or high impedance FET probe recommended for the spectrum analyser measurement.
3. Time taken for PLL to achieve 90% of final voltage within 6470kHz of final frequency (423·33MHz).
4. Spectrum analyser set to PLL lock frequency (423·33MHz), zero span 470kHz IF bandwidth, tSWEEP 20ms.
Figure 7 Characterising the PLL acquisition time from power-up
14
KESRX05
20
10
0
NO SAW
SAW
ANTI-JAM CIRCUIT CONNECTED
ANTI-JAM 40dB IMPROVEMENT
NO SAW 40dB
IMPROVEMENT
2
10
20
30
NO SAW
SAW
ANTI-JAM CIRCUIT BYPASSED
2
2
2
40
2
100
290
280
270
2
60
WANTED SIGNAL LEVEL (dBm)
Unmodulated interfering signal is 100kHz low side from wanted signal. Both signals are within the passband of the receiver (ceramic filter)
250
240
230
220
210
0
NOTE
i.e.
Wanted signal = 433·92 MHz at 2kb/s, 290 to 0dBm (50% duty cycle)
Interfering signal = 433·82MHz continuous carrier, 290 to 0dBm
Figure 8 In-band interference rejection of the receiver
100
SAW
NO SAW
80
ANTI-JAM
CONNECTED
ANTI-JAM
CONNECTED
ANTI-JAM
BYPASSED
60
40
20
ANTI-JAM
BYPASSED
0
220
431
431·5
432
432·5
433
433·5
434
434·5
435
435·5
436
FREQUENCY (MHz)
NOTE
The action of the anti-jam circuit to centre the bandwidth of the receiver around the wanted modulated signal at 433·92 MHz, 20kb/s, 50% duty
cycle, 290dBm Also notice the ability of the receiver to achieve the same selectivity performance over the frequency range 433 to 434.5 MHz
with and wthout a SAW filter.
Figure 9 KESRX05 selectivity response
15
KESRX05
C5
L5
C7
R10
R11
C10
C6
C2
DF2
20
IFIN IFLT1
3
IFLT2
RSSI
DETB
27 26
DF0
22
DF1
21
1
28
13
100k
PEAK
RSSI
O/P
ANTI-JAM
CIRCUIT
AMP
A
AMP
14
15
B
AMP
C
DATAOP
DSN
SALLEN-KEY
DATA FILTER
SLICER
REF
KESRX05
100k
INTERNAL
REFERENCE
VOLTAGE
Figure 10 Anti-jam circuit and data filter. Component idents refer to Figure 25, Figure 26 and Table 5.
Sallen and Key Filter Components
Cut-off frequency = fC, therefore vC = 2pfCY
Example
To implement a filter response with a 10kHz 3dB cut-
off frequency and with R10 = R11 = 100kΩ,
2Q
1
C5 =
C6 =
RvC
2QRvC
where, for a Bessel response, Q = 0·557 and Y = 1·732
and, for a Butterworth response, Q = 0·71 and Y = 1·0.
Bessel filter:
Butterworth filter:
C5 = 106pF, C6 = 80pF
C5 = 150pF, C6 = 150pF
C5
L5
C10
R10
R11
C7
C6
DF0
22
DF2
20
IFIN IFLT1
3
IFLT2
RSSI
DETB
27 26
DF1
21
1
28
PEAK
13
100k
C6
RSSI
O/P
ANTI-JAM
CIRCUIT
AMP
A
AMP
DATAOP
DSN
14
15
R6
B
AMP
C
SALLEN-KEY
DATA FILTER
SLICER
REF
KESRX05
100k
INTERNAL
REFERENCE
VOLTAGE
Figure 11 Bypassing the anti-jam circuit (use component revisions recommended in Table 3)
16
KESRX05
100n
250
SIGNAL
GENERATOR
2
10·7
MHz
REMOVE
IF FILTER
BEFORE
CONNECTING
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
RSSI
OSCILLOSCOPE 1
IFIN
IFOUT
SPECTRUM
ANALYSER
FET PROBE
9
10
11
12
13
14
AGC
V
KESRX05
PCB
RF
NC RFIN GND
GND
V
DATA PD NC
NC
CC
SIGNAL
GENERATOR
1
433·92MHz
A
DC PSU
3V TO 6V
NOTES
1. The 250Ω resistor added to the output of signal generator 2 modifies its characteristic impedance to mimic the output of the ceramic filter.
2. The 100nF capacitor brevents de-biasing of IFIN/
Figure 12 Characterising the receiver performance (Figures 13 to 16)
The characteristics shown in Figures 13 to 24 are typical results measured from a a limited sample of produc-
tion devices (see notes on page 19)
30
25
20
15
AT V = 3V
CC
6V
and
10
5
0
25
210
215
2100
290
2
80
2
70
RFIN UNMODULATED CARRIER AT 433·92MHz (dBm)
Figure 13 RFIN to IFOUT conversion gain (see RF Down-Converter, page 9)
2
60
2
50
2
40
2
30
2
20
2
10
0
10
17
KESRX05
1·8
1·4
1·2
1
V
= 3V
= 6V
CC
V
CC
0·8
0·6
0·4
0·2
0
2100
280
260
240
220
28
24
4
8
RFIN UNMODULATED AT 433·92MHz (dBm)
Figure 14 RFIN to RSSI output transfer characteristic (see IF Amp/RSSI Detector, page 11)
1·60
1·40
1·20
1·0
V
= 3V
= 6V
CC
V
CC
0·80
0·60
0·40
0·40
2100
280
260
240
220
28
24
0
4
8
IFIN UNMODULATED CARRIER AT 10·7MHz (dBm)
Figure 15 IFIN to RSSI output transfer characteristic (see IF Amp/RSSI Detector, page 11)
18
KESRX05
7·0
6·5
6·0
5·5
V
= 3V
= 6V
CC
V
CC
5·0
4·5
4·0
3·5
2
0
100
280
260
240
220
20
RFIN UNMODULATED CARRIER AT 433·92MHz (dBm)
Figure 16 Receiver current consumption v. received signal strength RFIN (see RF Down-converter, page 9)
NOTES
1. Conversion gain of the receiver is limited by the insertion loss of the front end SAW filter.
2. Dynamic range of the RSSI output transfer characteristic (Figure 14) is governed by the noise figure of the receiver,
which is limited by the insertion loss of the front end SAW filter and the bandwidth of the 10·7MHz ceramic filter.
3. Reduction in conversion gain and increase in receiver current consumption coincides with lift-off of the AGC control
line (pin 12). Action of the AGC applies additional mixer booster current to improve the linearity of the mixer at high
signal levels.
6
PD0 TTVD MAX
PD0 TTVD TYP
PD0 TTVD MIN
5
4
3
2
1
0
PD1 TTVD MAX
PD1 TTVD TYP
PD1 TTVD MIN
0
240
25
85
105
110
TEMPERATURE (°C)
NOTE
Time to valid data of PD0 to PD2 can be improved by maintaining the crystal oscillator in PD0 mode (see Power Down, page 9 and Table 1,
pin 23.)
Figure 17 PD0 to PD2 and PD1 to PD2 time to valid data (see Power Down, page 9)
19
KESRX05
6
5
PD0 LF LOCK MAX
PD0 LF LOCK TYP
PD0 LF LOCK MIN
4
3
2
1
0
PD2 LF LOCK MAX
PD2 LF LOCK TYP
PD2 LF LOCK MIN
0
240
25
85
105
110
TEMPERATURE (°C)
NOTE
Time to PLL acquisition of PD0 to PD2 can be improved by maintaining the crystal oscillator in PD0 mode (see Power Down, page 9 and Table
1, pin 23).
Figure 18 PD0 to PD2 and PD1 to PD2 time to PLL acquisition (tS1 and tS2, AC Electrical Characteristics (1), page 7)
2103
2103·5
2104
2104·5
2105
MAX SENSITIVITY
TYP SENSITIVITY
MIN SENSITIVITY
2105·5
2106
2106·5
2107
240
25
85
110
OPERATING TEMPERATURE (°C)
Figure 19 Receiver sensitivity v. temperature at VCC = 5V (VIN, AC Electrical Characteristics (1), page 7)
20
KESRX05
6
5
DATAOP V MAX
OH
DATAOP V TYP
OH
DATAOP V MIN
OH
4
3
2
1
0
DATAOP V MAX
OL
DATAOP V TYP
OL
DATAOP V MIN
OL
0
240
25
85
105
110
TEMPERATURE (°C)
Figure 20 DATAOP I/O voltage drive at 620µA (VOH/VOH, AC Electrical Characteristics (1), page 7)
80
60
40
DATAOP I MAX
OH
DATAOP I TYP
OH
DATAOP I MIN
OH
20
0
20
40
60
80
2
2
2
2
DATAOP I MAX
OL
DATAOP I TYP
OL
DATAOP I MIN
OL
0
240
25
85
105
110
TEMPERATURE (°C)
Figure 21 DATAOP I/O current drive at 620µA (see Baseband, page 13)
21
KESRX05
30
29·5
I
I
I
2MAX
TYP
MIN
CC2
CC2
CC2
29
28·5
28
27·5
27
26·5
26
0
240
25
85
105
110
TEMPERATURE (°C)
Figure 22 Receiver current consumption in PD0 mode, DC Electrical Characteristics, page 7
360
I
I
I
MAX
TYP
MIN
CC1
CC1
CC1
355
350
345
340
335
330
225
0
240
25
85
105
110
TEMPERATURE (°C)
Figure 23 Receiver current consumption in PD1 mode, DC Electrical Characteristics, page 7
22
KESRX05
4·2
4·1
4
3·9
3·8
I
I
I
MAX
TYP
MIN
CC
CC
CC
3·7
3·6
3·5
3·4
0
240
25
85
105
110
TEMPERATURE (°C)
Figure 24 Receiver current consumption in PD2 mode, DC Electrical Characteristics, page 7
23
KESRX05
C7
L6
V
CC
KESRX05
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C25
C26
CF1
IFFLT1
IFFLT2
RSSI
DETB
PD
C3
R9
2
IFDC1
IFIN
C10
3
4
PD
IFDC2
C14
V
C4
C23
C15
CC
5
V
XTAL1
XTAL2
DF0
CC
XTAL1
C2
C13
6
3
1
O/P
I/P
IFOUT
GND
2
R10
R11
V
CC
7
V
CC
RF
C28
C29
C6
8
L1
MIXIP
RFOP
DF1
C5
C9
9
DF2
C11
R4
R1
10
11
12
13
14
L2
V
RF
VCO1
VCO2
EE
C21
C8
L3
C12
C1
D1
RFIN
RF IN
C19
C18
AGC
V
EE
R2
PEAK
DATAOP
LF
R7
DSN
DATA
C22
R6
Figure 25 Application circuit diagram for KESRX05 with NO SAW filter
C7
L6
V
CC
KESRX05
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C25
C26
CF1
IFFLT1
IFDC1
IFIN
IFFLT2
RSSI
DETB
PD
C3
R9
2
C10
3
4
PD
IFDC2
C14
V
C4
C23
C15
CC
5
V
XTAL1
XTAL2
DF0
CC
XTAL1
C2
C13
6
3
1
O/P
I/P
IFOUT
GND
2
R10
R11
V
CC
7
V
CC
RF
C28
8
C29
C6
8
L1
MIXIP
RFOP
DF1
C5
C9
9
7
DF2
BS3550
GND
GND
C11
R4
R1
10
11
12
13
14
L2
1
6
5
V
RF
VCO1
VCO2
I/P GND O/P GND
EE
C12
C1
D1
L4
L3
2
I/P
GND
O/P
GND
RFIN
RF IN
C19
C18
AGC
V
EE
R2
3
4
C8
PEAK
DATAOP
LF
R7
DSN
DATA
C22
R6
Figure 26 Application circuit diagram for KESRX05 with SAW filter
24
KESRX05
Ident
Value
Part No./tolerance
Supplier
Size
0603
C1
C2
C3
C4
C5
C6
C7 (1)
C8
C9
C10
C11 (1)
C12
C13
C14
C15
C18 (1)
C19 (2)
C21 (3)
C22
C23
C25
GRM39C0G151J
GRM39C0G271J
GRM39X7R103K
GRM39X7R103K
GRM39SL271J
GRM39SL271J
GRM39COG470G
GRM39Y5V103K
GRM39COG560J
GRM40Y5V105Z
GRM39COG120J
GRM39X7R152K
GRM39COG180J
G RM39COG180J
GRM39COG101J
GRM39COG120J
GRM39COG2R0C
GRM39COG221J
GRM40Y5V105Z
GRM39COG101J
GRM39COG101J
GRM40Y5V105Z
GRM40Y5V105Z
GRM39COG101J
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4 to 10pF
3dB BW = 230kHz
3dB BW = 230kHz
LL2012-F39NJ
LL2012-F27NJ
LL2012-F68NJ
LL1608-FHR10J
LL2012-F33NJ
FLU25204R7J
6100 PPM
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Rohm
Rohm
Rohm
Rohm
Rohm
Rohm
Rohm
Rohm
Siemens
Murata
TOKO
TOKO
TOKO
TOKO
TOKO
TOKO
TOKO
150ph
270pF
10nF
0603
0603
0603
0603
0603
0603
0603
0603
0805
0603
0603
0603
0603
0603
0603
0603
0603
0805
0603
0603
0805
0805
0603
0603
0603
0603
0805
0603
0603
0603
0603
SOD323
Radial
5mm2
2012
2012
1608
1608
2021
2520
10nF
270pF
270pF
47pF
10nF
56pF
1µF
12pF
1·5nF
18pF
18pF
100pF
12pF
2pF
220pF
1µF
100pF
100pF
1µF
C26
C28
C29
R1
R2
R4
R6
R7
1µF
100pF
4.7kΩ
10kΩ
4.7kΩ
100kΩ
100kΩ
360Ω
R9 (1)
R10
R11
100kΩ
100kΩ
BB833
SFE10.7MA26
B3550
39nH
D1
CF1 (1)
SAWF
L1 (2)
L2 (2)
L3 (2, 3)
L3 (1,3)
L4 (2,4)
L5 (1)
XTAL1 (2)
KESRX05
27nH
68nH
100nH
33nH
4.7µH
Kinseki / Quartz Tek HC49/4H
Mitel Semiconductor QP28
6·61281MHz
Table 5 Components for Figures 25 and 26
NOTES
1. Adjust for alternative IF/ceramic filter.
2. Adjust for alternative centre frequency.
3. Without SAW filter (Figure 25).
4. With SAW filter (Figure 26).
25
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