MAS2901CL [ZARLINK]

RADIATION HARD 4-BIT MICROPROCESSOR SLICE; 辐射HARD 4位微处理器SLICE


型号：	MAS2901CL
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	RADIATION HARD 4-BIT MICROPROCESSOR SLICE 辐射HARD 4位微处理器SLICE 微处理器
文件：	总13页 (文件大小：261K)
中文：	中文翻译
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This product is obsolete.

This information is available for your

convenience only.

For more information on

Zarlink’s obsolete products and

replacement product lists, please visit

http://products.zarlink.com/obsolete_products/

FEBRUARY 1995

MA2901

DS3576-3.3

MA2901

RADIATION HARD 4-BIT MICROPROCESSOR SLICE

The MA2901 is an industry standard 4-bit microprocessor

OPERATION

slice It provides a set of ALU functions selected by microcode

data applied to the inputs. The device is cascadable to handle

any word length. It can be used as a building block in the

construction of microcomputers and controllers tailored to

meet specialised applications.

A detailed block diagram of the microprogrammable

microprocessor structure is shown in figure 1. The circuit is a

four-bit slice, cascadable to any number of bits. Therefore, all

data paths within the circuit are four bits wide. The two key

elements in the figure 1 are the 16-word by 4-bit 2-port RAM

and the high speed ALU.

Dual Address Architecture

Data from any of the 16 words of the Random Access

Memory (RAM) can be read from the A-port of the RAM as

controlled by the 4-bit A-address field input. Likewise, data

from any of the 16 words of the RAM as defined by the B-

address field input can be simultaneously read from the B-port

of the RAM. The same code can be applied to the A-select field

and B-select field in which case the identical file data will

appear at both the RAM A-port and B-port outputs

simultaneously.

Machine cycles are saved by simultaneous, independent

access to two working registers.

ALU has Eight Functions

Operations performed are addition, two subtractions and five

logic functions on two source operands.

Four State Flags

Zero, negative, carry and overflow.

When enabled by the RAM write enable (RAM EN), new

data is always written into the file (word) defined by the B-

address field of the RAM. The RAM data input field is driven by

a 3-input multiplexer. This configuration is used to shift the

ALU output data (F) if desired. This three-input multiplexer

scheme allows the data to be shifted up one bit position,

shifted down one bit position, or not shifted in either direction.

The RAM A-port data outputs and RAM B-port data outputs

drive separate 4-bit latches. These latches hold the RAM data

while the clock input is LOW. This eliminates any possible race

conditions that could occur while new data is being written into

the RAM.

Left / Right Shift is Independent of ALU

Only one cycle taken for add and shift operations.

Expandable

Any number of MA2901 units can be connected together to

achieve longer word lengths.

Micro Programmable

Three groups, each of three bits, for ALU function, source

operand and destination control.

The high-speed Arithmetic Logic Unit (ALU) can perform

three binary arithmetic and five logic operations on the two 4-

bit input words R and S. The R input field is driven from a 2-

input multiplexer, while S input field is driven from a 3-input

multiplexer. Both multiplexers also have an inhibit capability;

that is, no data is passed. This is equivalent to a “zero” source

operand.

The ALU R-input multiplexer has the RAM A-port and the

direct data inputs (D) connected as inputs. Likewise, the ALU

S-input multiplexer has the RAM A-port, the RAM B-port and

the Q register connected as inputs.

FEATURES

■ Fully Compatible with Industry Standard 2901

■ CMOS SOS Technology

■ High SEU Immunity and Latch-up Free

■ High Speed

■ Low Power

MA2901

C_n+4

OVR

F=0

F₃

C_n

Figure 1: Block Diagram

MA2901

This multiplexer scheme gives the capability of selecting

various pairs of the A, B, D, Q and “0” inputs as source

operands to the ALU. These five inputs, when taken two at a

time, result in ten possible combinations of source operand

pairs. These combinations include AB, AD, AQ, A0, BD, BQ,

B0, DQ, D0 and Q0. It is apparent the AD, AQ and A0 are

somewhat redundant with BD, BQ and B0 in that if the A

address and B address are the same, the identical function

results. Thus, there are only seven completely non-redundant

sourced operand pairs for the ALU. The MA2901

microprocessor implements eight of these pairs. The

microinstruction inputs used to select the ALU source

operands are the l₀, I₁, and I₂inputs. The definition of l₀, I₁, and

I₂for the eight source operand combinations are as shown in

figure 2. Also shown is the octal code for each selection.

The two source operands not fully described as yet are the

D input and Q input. The D input is the four-bit wide direct data

field input. This port is used to insert all data into the working

registers inside the device. Likewise this input can be used in

the ALU to modify any of the internal data files. The Q register

is a separate 4-bit file intended primarily for multiplication and

division routines but it can also be used as an accumulator or

holding register for some applications.

The ALU itself is a high speed arithmetic/logic operator

capable of performing three binary arithmetic and five logic

functions. The I₃, I₄, and I₅microinstruction inputs are used to

select the ALU function. The definition of these inputs is shown

in Figure 3. The octal code is also shown for reference. The

normal technique for cascading ALU of several devices is in a

look-ahead carry mode. Carry generate, GN, and carry

propagate, PN, are outputs of the device for use with a carry-

look-ahead-generator. A carry-out Cn + 4, is also generated

and is available as an output for use as the carry flag in a

status register. Both carry-in (Cn) and carry-out (Cn+4) are

active HIGH.

The ALU has three other status-oriented outputs. These

are F₃, F=0, and overflow (OVR). The F₃output is the most

significant (sign) bit of the ALU and can be used to determine

positive or negative results without enabling the three-state

data outputs. F₃is non-inverted with respect to the sign bit

output Y3. The F = 0 output is used for zero detect. It is an

open-collector output and can be wire OR’ed between

microprocessor slices. F = 0 is HIGH when all F outputs are

LOW. The overflow output (OVR) is used to flag arithmetic

operations that exceed the available two’s complement

number range. The overflow output (OVR) is HIGH when

overflow exists. That is when Cn + 3 and Cn + 4 are not the

same polarity.

The ALU data output is routed to several destinations. It

can be a data output of the device and it can also be stored in

the RAM or the Q register. Eight possible combinations of ALU

destination functions are available as defined by the I₆, I₇, and

I₈microinstruction inputs. These combinations are shown in

figure 4.

The four-bit data output field (Y) features three-state

outputs and can be directly bus organised. An output control

(OEN) is used to enable the three-state outputs. When OEN is

HIGH, the Y outputs are in the high impedance state.

A two-input multiplexer is also used at the data output

such that either the A-port of the RAM or the ALU outputs (F)

are selected at the device Y outputs. This selection is

controlled by the I₆, I₇, and I₈microinstruction inputs.

As was discussed previously, the RAM inputs are driven

from a three-input multiplexer. This allows the ALU outputs to

be entered non-shifted, shifted up one position (x 2) or shifted

down one position (÷ 2). The shifter has two ports; labeled

RAM₀and RAM₃. Both of these ports consist of a buffer-driver

with a three-state output and an input to the multiplexer.

Microcode

ALU Source

Operands

Microcode

ALU

Symbol

Function

Octal

Code

Octal

Code

R + S

R plus S

S - R

S minus R

R minus S

R OR S

R - S

R ÚS

RN Ù S

R Ù S

R Ñ S

RN Ñ SN

RN AND S

R AND S

R EX-OR S

R EX-NOR S

+ = plus; - = minus; = OR; L = AND; Ñ = EX-OR

Figure 2: ALU Source Operand Control

Figure 2: ALU Function Control

MA2901

In the shift up mode, the RAM₃buffer is enabled and the

SOURCE OPERANDS & ALU FUNCTION

RAM₀multiplexer input is enabled. Likewise, in the shift down

mode, the RAM₀buffer and RAM₃input are enabled. In the no-

shift mode, both buffers are in the high-impedance state and

the multiplexer inputs are not selected. The shifter is controlled

from the I₆, I₇and I₈microinstruction inputs as defined in Figure

Similarly, the Q register is driven from a 3-input

multiplexer. In the non-shift mode, the multiplexer enters the

ALU data into the Q register. In either the shift-up or shift-down

mode, the multiplexer selects the Q register data appropriately

shifted up or down. The Q shifter also has two ports; one is

labeled Q₀and the other is Q₃. The operation of these two

ports is similar to the RAM shifter and is also controlled from I₆,

I₇and I₈as shown in Figure 4.

The clock input shown in Figure 1 controls the RAM, the Q

resister and the A and B data latches. When enabled, data is

clocked into the Q register on the LOW-to-HlGH transition of

the clock. When the clock input is HIGH, the A and B latches

are open and will pass whatever data is present at the RAM

outputs. When the clock input is LOW, the latches are closed

and will retain the last data entered. If the RAM-EN is enabled

new data will be written into the RAM file (word) defined by the

B address field when the clock input is LOW.

Any one of eight source operand pairs can be selected by

instruction inputs lo, l₁and I₂for use by the ALU; instruction

inputs I₃, I₄, and I₅then control function selection for the ALU -

five logic and three arithmetic functions. In the arithmetic

mode, the carry input (Cn) also affects the ALU functions; the

carry input has no effect on the ‘F’ result in the logic mode.

These control parameters (I₆- l₀and Cn) are summarised in

Figure 5 to completely define the ALU/source operand

functions.

The ALU functions can also be examined on a task basis:

that is, add, subtract, AND, OR, and so on. Again, in the

arithmetic mode, the carry input still affects the result, whereas

in the logic mode it will not. Figures 6 and 7, respectively,

define the various logic and arithmetic functions of the ALU;

both carry states (Cn = 0 / Cn = 1) are defined in the function

matrices.

Microcode

RAM Function

Q-Reg Function

RAM Shifter

RAM RAM

Q Shifter

Octal

Code

Output

Shift

None

Load

None

F® B

Shift

None

Load

F® Q

None

Down F/2® B Q/2® Q

Down F/2® B

None

2Q® Q

None

2F® B

X = Don't Care. Electrically, the shift pin is a TTL input internally connected to a TRI-STATE output which is in the high-impedance state.

B = Register addressed by 8 inputs. Up is towards MSB, Down is towards LSB.

Figure 4: ALU Destination Control

Octal

0,Q

0,B

0,A

D,0

2,1,0

ALU Source

/ALU

Octal

A,Q

A+Q

A,B

A+B

D,A

D + A

D,Q

D + Q

Function

C =L

R plus S

5,4,3

A+Q+1

Q-A-1

A+B+1

B-A-1

Q +1

Q -1

B + 1

B - 1

A + 1

A - 1

D + A + 1 D + Q + 1

D + 1

-D - 1

C =H

Cn=L

A - D1

Q - D - 1

S minus R

C =H

Q-A

A-Q-1

B-A

A-B-1

-Q-1

A - D

D - A -1

Q - D

D - Q - 1

- D

D - 1

C =L

- B - 1

- A - 1

R minus S

A-Q

A-B

- Q

- B

- A

D - A

D - Q

C =H

R or S

R and S

D Q

A L Q

ANL Q

A Ñ Q

A L B

ANL B

A Ñ B

D L A

DNL A

D Ñ A

D L Q

DNL Q

D Ñ Q

RN and S

R EX-OR S

R EX NOR S ANÑ QN ANÑ BN

DNÑ AN

DNÑ QN

+ = plus; - = minus; = OR; L = AND; Ñ = EX-OR

Figure 5: Source Operand and ALU Function Matrix

MA2901

Octal

Group

AND

Function

5,4,3 2,1,0

A L Q

A L B

D L A

D L Q

A Ñ Q

A Ñ B

D Ñ A

EX-OR

EX-NOR

INVERT

DÑ Q

ANÑ QN

ANÑ BN

DNÑ AN

DNÑ QN

PASS

‘ZERO’

AND

ANL Q

ANL B

DNL A

DNL Q

+ = plus; - = minus; = OR; L = AND; Ñ = EX-OR

Figure 6: ALU Logic Mode Functions (C_nIrrelevant)

Octal

Cn=0(Low)

Function

Cn = 1 (High)

Function

Group

5,4,3 2,1,0

A + Q

A + B

D + A

D + Q

Q - 1

A + Q +1

A + B +1

D + A +1

D + Q + 1

Q +1

B + 1

A + 1

D + 1

- Q

- B

- A

- D

Q - A

B - A

A - D

Q - D

A - Q

A - B

D - A

D - Q

ADD

plus one

ADD

PASS

Decrement

1s comp

Increment

PASS

B - 1

A - 1

D - 1

- Q - 1

- B - 1

- A - 1

- D - 1

Q - A -1

B - A-1

A - D-1

Q - D-1

A - Q-1

A - B-1

D - A-1

D - Q-1

2s comp

(negate)

SUBTRACT

(1s comp)

SUBTRACT

(2s comp)

Figure 7: ALU Arithmetic Mode Functions

MA2901

PIN DESCRIPTION

Name

I/O

Description

0-3

The four address inputs to the register stack used to select one register whose

contents are displayed through the A port

The four address inputs to the register stack used to select one register whose

contents are displayed through the B port and into which new data can be written

when the clock goes LOW

0-3

The nine instruction control lines. Used to determine what data sources will be

0-8

applied to the ALU(I

), what function the ALU will perform (I

), and what

0,1,2

3,4,5

data is to be deposited in the Q-register or the register stack (I

)

6,7,8

I/O

The shift line at the MSB of the Q-register (Q ) and the register stack (RAM ).

3 3

RAM

Electrically these lines are three-state outputs connected to TTL inputs internal to

the device. When the destination code on I indicates an up shift (Octal 6 or 7)

6,7,8

the three state outputs are enabled and the MSB of the Q-register is available on

the Q pin and the MSB of the ALU output is available on the RAM pin.

Otherwise, the three state outputs are electrically OFF (high impedance) and the

pins are electrically LS-TTL inputs. When the destination code calls for a down

shift, the pins are used as the data inputs to the MSB of the Q-register (Octal 4)

and RAM (Octal 4 or 5)

RAM

I/O

Shift lines like Q and RAM but at the LSB of the Q-register and RAM. These

pins are tied to the Q and RAM pins of the adjacent device to transfer data

3 3

between devices for up and down shifts of the Q-register and ALU data.

0-3

Direct data inputs. A four-bit data field which may be selected as one of the ALU

data sources for entering data into the device D is the LSB

0-3

The four data outputs. These are three-state output lines. When they are enabled,

they display either the four outputs of the ALU or the data on the A-port of the

6,7,8.

OEN

Output enable. When OEN is HIGH, the Y outputs are OFF; when OEN is LOW, the

Y outputs are active (HIGH or LOW)

GN,PN

OVR

The carry generate and propagate outputs of the internal ALU. These signals are

used with the MA2901 for carry lookahead.

Overflow. This pin is logically the Exclusive OR of the carry-in and carry-out of the

MSB of the ALU. At the most significant end of the word, this pin indicates that the

result of an arithmetic two’s complement operation has overflowed into the sign-bit

This is an open collector output which goes HIGH(OFF) if the data on the four ALU

F = 0

outputs F are all LOW. In positive logic, it indicates that the result of the ALU

0-3

operation is zero

C + 4

The most significant ALU output bit.

The carry-in to the internal ALU.

The carry-out of the ALU internal ALU.

The clock input. The Q-register and register stack outputs change on the clock

LOW - to HIGH transition. The clock LOW time is internally the write enable to the

16 x 4 RAM which compromises the “master” latches of the register stack. While

the clock is LOW, the “slave” latches on the RAM outputs are closed, storing the

data previously on the RAM outputs. This allows synchronous master-slave

operation of the register stack.

Figure 8: Pin Description

MA2901

DC CHARACTERISTICS AND RATINGS

Note: Stresses above those listed may cause permanent

damage to the device. This is a stress rating only and

functional operation of the device at these conditions, or at

any other condition above those indicated in the operations

section of this specification, is not implied. Exposure to

absolute maximum rating conditions for extended periods

may affect device reliability.

Parameter

Min

-0.5

-0.3

-20

-55

-65

Max

Units

Supply Voltage

Input Voltage

V_DD+0.3

+20

Current Through Any Pin

Operating Temperature

Storage Temperature

°C

125

150

°C

Figure 9: Absolute Maximum Ratings

Subgroup

Definition

Static characteristics specified in Figure 11 at +25°C

Static characteristics specified in Figure 11 at +125°C

Static characteristics specified in Figure 11 at -55°C

Functional characteristics at +25°C

Functional characteristics at +125°C

Functional characteristics at -55°C

Switching characteristics specified in Figures 12, 13 and 14 at +25°C

Switching characteristics specified in Figures 12, 13 and 14 at +125°C

Switching characteristics specified in Figures 12, 13 and 14 at -55°C

Figure 10: Definition of Subgroups

Total dose radiation not

exceeding 3x10⁵Rad(Si)

Symbol

Parameter

Supply Voltage

Conditions

Min

Typ

Max

Units

V_DD

V_IH

V_IL

4.5

2.4

5.0

5.5

Input High Voltage

Input Low Voltage

0.8

V_OH

V_OL

I_IN

Output High Voltage

Output Low Voltage

Input Leakage Current (Note 1)

I_OH= -6mA

I_OL= 10mA

2.4

0.4

±10

V_DD= 5.5V,

µA

V_IN= V_SSor V_DD

I_OZ

I_DD

Output Leakage Current (Note 1)

Power Supply Current

V_DD= 5.5V,

V_IN= V_SSor V_DD

±50

µA

Static, V_DD= 5.5V

0.1

V_DD= 5V±10%, over full operating temperature range.

Mil-Std-883, method 5005, subgroups 1, 2, 3

Notes: 1. Guaranteed but not measured at -55°C

Figure 11: Operating Electrical Characteristics

MA2901

AC ELECTRICAL CHARACTERISTICS

Read-Modify-Write Cycle (from selection of A,B registers to end of a cycle

Maximum Clock Frequency to shift Q(50% duty cycle, I = 432 or 632)

Minimum Clock LOW time

Minimum Clock HIGH time

Minimum Clock Period

40ns

25MHz

20ns

40ns

Note: 1. These timings are applied during functional tests and are not routinely measured.

Figure 12: Cycle Time and Clock Characteristics

To Output

+ 4

RAM

G,P

F = 0

OVR

From Input

RAM

A,B Address

0,1,2

3,4,5

6,7,8

A Bypass ALU(I=2xx)

Clock

Note: All timings in ns

Figure 13: Combinational Propagation Delays

Input

CP:

Set-up Time

Before H ® L

Hold Time

After H ® L

Set-up Time

Before L ® H

Hold Time

After L ® H

A,B Source Address

B Destination Address

No change

0,1,2

3,4,5

6,7,8

No change

RAM

0,3, 0,3

MIL-STD-883, method 5005, subgroups 9, 10, 11

Note: 1. V = 5V±10%, over full operational temperature range

2. CL = 50 pF

Figure 14: Set-up and Hold Times Relative to Clock (CP) Input

MA2901

OUTLINES AND PIN ASSIGNMENTS

Millimetres

Ref

Inches

Min.

Nom.

Max.

5.715

1.53

0.59

0.36

51.31

Min.

Nom.

Max.

0.225

0.060

0.023

0.014

2.020

39 Y3

38 Y2

37 Y1

36 Y0

0.38

0.015

0.35

0.014

0.20

0.008

2.54 Typ.

0.100 Typ.

15.24 Typ.

0.600 Typ.

34 OVR

33 Cn+4

4.71

5.38

15.90

1.27

1.53

0.185

0.212

0.626

0.050

0.060

RAM3

RAM0

VDD

Top

View

31 F3

30 VSS

29 Cn

28 I4

XG405

F = 0 11

I0 12

I1 13

I2 14

27 I5

CP 15

Q3 16

B0 17

B1 18

B2 19

B3 20

26 I3

25 D0

24 D1

23 D2

22 D3

21 Q0

M_E

Seating Plane

A₁

e₁

15°

Figure 15: 40-Lead Ceramic DIL (Solder Seal) - Package Style C

MA2901

Millimetres

Min.

Inches

42 I6

Ref

Max.

2.49

0.53

0.25

27.69

16.76

17.27

Min.

0.070

0.017

0.006

1.050

0.620

Max.

0.098

0.023

0.010

1.080

0.660

0.630

41 A0

40 A1

39 A2

38 A3

37 OE

36 Y3

35 Y2

34 Y1

33 Y0

1.75

0.43

0.15

26.67

15.75

RAM3

RAM0

VCC

F=0

13.21

0.76

1.14

7.87

32.51

0.76

0.520

0.030

0.045

0.310

1.250

0.030

I2 10

CP 11

NC 12

Q3 13

B0 14

B1 15

B2 16

B3 17

Q0 18

D3 19

D2 20

D1 21

1.40

9.40

34.54

1.52

1.14

0.055

0.370

1.360

0.060

0.045

31 OVR

30 Cn+4

28 F3

27 GND

26 Cn

25 I4

0.13

0.005

XG136

24 I5

23 I3

22 D0

Figure 16: 42-Lead Flatpack (Solder Seal)

MA2901

RADIATION TOLERANCE

Total Dose (Function to specification)*

Transient Upset (Stored data loss)

Transient Upset (Survivability)

Neutron Hardness (Function to specification)

Single Event Upset**

3x10⁵Rad(Si)

5x10¹⁰Rad(Si)/sec

>1x10¹²Rad(Si)/sec

>1x10¹⁵n/cm²

Total Dose Radiation Testing

For product procured to guaranteed total dose radiation

levels, each wafer lot will be approved when all sample

devices from each lot pass the total dose radiation test.

The sample devices will be subjected to the total dose

radiation level (Cobalt-60 Source), defined by the ordering

code, and must continue to meet the electrical parameters

specified in the data sheet. Electrical tests, pre and post

irradiation, will be read and recorded.

1x10^-10Errors/bit day

Not possible

Latch Up

* Other total dose radiation levels available on request

** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit

GEC Plessey Semiconductors can provide radiation

testing compliant with Mil-Std-883 method 1019 Ionizing

Radiation (total dose) test.

Figure 17: Radiation Hardness Parameters

ORDERING INFORMATION

Unique Circuit Designator

MAx2901xxxxx

Radiation Tolerance

Radiation Hard Processing

100 kRads (Si) Guaranteed

300 kRads (Si) Guaranteed

QA/QCI Process

(See Section 9 Part 4)

Test Process

(See Section 9 Part 3)

Package Type

Ceramic DIL (Solder Seal)

Flatpack (Solder Seal)

Assembly Process

(See Section 9 Part 2)

Reliability Level

Rel 0

Rel 1

Rel 2

Rel 3/4/5/STACK

Class B

Class S

For details of reliability, QA/QC, test and assembly

options, see ‘Manufacturing Capability and Quality

Assurance Standards’ Section 9.

MA2901

HEADQUARTERS OPERATIONS

CUSTOMER SERVICE CENTRES

• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07

• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55

• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993

GEC PLESSEY SEMICONDUCTORS

Cheney Manor, Swindon,

Wiltshire, SN2 2QW, United Kingdom.

Tel: (01793) 518000

• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510

• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023

• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872

• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36

• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260

• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK

Tel: (01793) 518527/518566 Fax: (01793) 518582

Fax: (01793) 518411

GEC PLESSEY SEMICONDUCTORS

P.O. Box 660017,

1500 Green Hills Road, Scotts Valley,

California 95067-0017,

United States of America.

Tel: (408) 438 2900

Fax: (408) 438 5576

These are supported by Agents and Distributors in major countries world-wide.

TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED

This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to

be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or

service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide

only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of

any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose

failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.

MAS2901CL [ZARLINK]

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