NJ88C29KG/NPAS [ZARLINK]
PLL Frequency Synthesizer, CMOS, PDSO20, MINIATURE, PLASTIC, SSOP-20;
| 型号： | NJ88C29KG/NPAS |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | PLL Frequency Synthesizer, CMOS, PDSO20, MINIATURE, PLASTIC, SSOP-20 光电二极管 |
| 文件： | 总10页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
DECEMBER 1993
ADVANCE INFORMATION
DS3889-1.6
NJ88C29
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
WITH NON-RESETTABLE COUNTERS
T
he NJ88C29 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-holdcomparators,10-bitprogrammable‘M’counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although 28 bits of data are initially
required to program all counters, subsequent updating can be
abbreviatedto17bits,whenonlythe‘A’and‘M’countersrequire
changing.
PDA
PDB
NC
20
11
1
CH
RB
NC
LD
MC
F
CAP
ENABLE
CLOCK
DATA
NC
IN
V
NJ88C29
SS
V
DD
NC
OSC IN
The NJ88C29 is intended to be used in conjunction with a
two-modulus prescaler such as the SP8715 series to produce
a universal binary coded synthesiser for up to 1100MHz
operation. Operation from a 3.8V supply is also supported.
OSC OUT
NC
10
NP20
FEATURES
Fig.1 Pin connections - top view (not to scale)
■
■
■
■
■
■
Low Power Consumption
High Performance Sample and Hold Phase Detector
Serial Input with Fast Update Feature
3.8V Operation
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD-VSS
Input voltage
-0·75V to 7V
7V
SS-0·3V to VDD+0·3V
-55°C to +125°C
Open drain output, pin 4
All other pins
V
Storage temperature
Fast Lock Up Time
ORDERING INFORMATION
SSOP Package
NJ88C29 KG/NPAS Shrunk Miniature Plastic DIL Package
RB
(19)
CAP
(16)
CH
(20)
f
(9)
REFERENCE COUNTER
(11BITS)
r
SAMPLE/HOLD
PHASE
DETECTOR
÷2
(1)
OSC IN
PDA
(10)
OSC OUT
LATCH 6 LATCH 7 LATCH 8
‘R’ REGISTER
(13)
(15)
FREQUENCY/
PHASE
DETECTOR
(2)
(4)
DATA
ENABLE
f
PDB
V
(14)
‘M’ REGISTER
‘A’ REGISTER
CLOCK
LOCK DETECT (LD)
V
SS
LATCH 1 LATCH 2 LATCH 3
LATCH 4 LATCH 5
(5)
‘M’ COUNTER
(10 BITS)
‘A’ COUNTER
(7 BITS)
F
IN
(7)
(6)
V
DD
MODULUS
CONTROL
OUTPUT (MC)
(17)
CONTROL LOGIC
V
SS
Fig.2 block diagram
NJ88C29
ELECTRICAL CHARACTERISTICS AT VDD = 3.8V
Thesecharacteristicsareguaranteedoverthefollowingconditions,unlessotherwisestated:
V
DD–VSS=3.8V ±0·4V. Temperature range = –15°C to +70°C
DCCharacteristics
Value
Characteristic
Units
Conditions
Min. Typ. Max.
0 to 3.8V
square
wave
Supply current
3.0
0.6
5·0
0.94
mA
mA
f
f
, fFIN = 10MHz
, fFIN = 4·096MHz
osc
osc
ModulusControlOutput(MC)
High level
Low level
LockDetectOutput(LD)
Low level
2.5
2.5
V
V
I
I
SOURCE = ImA
SINK = ImA
0·4
0·4
7·0
V
V
I
SINK = 4mA
Open drain pull-up voltage
PDB Output
High level
Low level
V
V
I
I
SOURCE = 3mA
SINK = 3mA
0·4
3-state leakage current
±100
nA
ACCharacteristics
Characteristic
Value
Typ.
Units
Conditions
Min.
Max.
mV RMS
MHz
200
20
OSC IN input level and FIN input level
12.8MHz AC-coupled sinewave
See note 4
Max. operating frequency, FIN and OSC IN inputs
Input squarewave VDD to VSS
25°C. See note 5.
See note 2
,
50
30
ns
Propagation delay, FIN to modulus control MC
ProgrammingInputs
0.5
0.5
0.2
0.2
0.2
0.2
µs
µs
µs
µs
µs
µs
µs
V
Clock high time, tCH
Clock low time, tCL
Enable set-up time, tES
Enable hold time, tEH
Data set-up time, tDS
Data hold time, tDH
Clock rise and fall times
High level threshold
Low level threshold
Hysteresis
All timing periods
are referenced to
the negative
transition of the
clock waveform
See note 4
tCH
0.2
DD-0.24
V
See note 1
See note 1
See note 1
See note 3
V
V
0.4
1.23
1.8
PhaseDetector
1.12
DD–0.9
500
V
V
ns
µA
Positive going threshold, VT +
Negative going threshold, VT –
Digital phase detector propagation delay
RB current, IRB
CAP/RB current gain, α
Programming capacitor, CAP
Output resistance, PDA, PDB
V
300
7.8
5
6.3
Set by external conditions.
Over RB current range.
7.0
100
80
pF
Ω
Cint plus packaging strays.
NOTES
1. Data, Clock and Enable inputs are high impedance Schmitt buffers without pull-up resistors; they are therefore not TTL compatible.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically; 1µs for the sample and hold amplifier.
4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the signal/osc.
frequency inputs.
5. The minimum Fin period is governed by a time constant determined by the capacitance value on the CAP pin and the internal CAP discharge
resistance. Depending on the value of CAP, PLL performance may be degraded at frequencies below 20MHz - see AN112 for further
2
NJ88C29
PIN DESCRIPTIONS
Pin no.
Name
Description
Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Voltage
NP
1
PDA
increases as f (the output from the ‘M’ counter) phase lead increases; voltage decreases as f (the
v
r
output from the ‘R’ counter) phase lead increases. Output is linear over only a narrow phase window,
determined by gain (programmed by RB). This pin is at (VDD–VSS)/2 when the system is in lock, for an
external loop filter amplifier biased to (VDD–VSS)/2. Ideally, VBIAS should be chosen such that the PDA
window is centred between the thresholds, typically at 0·55(VDD–VSS
)
2
PDB
Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
f >f or f leading: positive pulses with respect to the bias point VBIAS
v
r
v
f <f or f leading: negative pulses with respect to the bias point VBIAS
v
r
r
f = f and phase error within PDA window: high impedance.
v
r
(Minimum, M = 3 for correct function of PDB).
Not connected..
3
4
NC
LD
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
5
FIN
The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or,
when a full logic swing is available, may be DC-coupled.
6
7
VSS
VDD
NC
Negative supply (ground).
Positive supply.
8
Not connected.
9,10
OSC IN/
OSC OUT
These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. The addition of a 2·2kΩ resistor between pin 10 and
the crystal will improve stability. An external reference signal may, alternatively, be applied to OSC IN.
This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled.
The program range of the reference counter is 3 to 2047 in steps of 1, with the total division ratio being
twice the programmed value i.e., 6 to 4094 in steps of 2.
11
12
13
NC
NC
Not connected.
Not connected.
DATA
Information on this input is transferred to the internal data latches during the appropriate data read time
slot. DATA is high for a ‘1’ and low for a ‘0’. There are three data words which control the NJ88C29;
MSB is first in the order: ‘A’ (7 bits), ‘M’ (10 bits), ‘R’ (11 bits).
14
15
CLOCK
Data is clocked on the negative transition of the CLOCK waveform. If less than 28 negative clock
transitions have been received when the ENABLE line goes low (i.e., only ‘M’ and ‘A’ will have been
clockedin), thenthe‘R’counterlatchwillremainunchangedandonly‘M’and‘A’willbetransferredfrom
the input shift register to the counter latches. If 28 negative transitions have been counted, then the ‘R’
counter will be loaded with the new data.
ENABLE
When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is
high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is
transferred from the input shift register to the counter latches on the negative transition of the ENABLE
input and both inputs to the phase detector are synchronised to each other.
16
17
CAP
MC
This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and
allows further programming of the device. (This capacitor is connected from CAP to VSS).
Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the
beginning of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes
high and remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters
are reset. This gives a total division ratio of MP+A, where P and P+1 represent the dual-modulus
prescaler values. The program range of the ‘A’ counter is 0–127 and therefore can control prescalers
with a division ratio up to and including ÷ 128/129. The programming range of the ‘M’ counter is 3-1023
but M>8 for correct PDA operation and, for correct operation with a prescaler, M>A. Where every
possible channel is required, the minimum total division ratio N should be: N>P 2–P, where N = MP+A.
18
NC
Not connected
3
NJ88C29
PIN DESCRIPTIONS (continued)
Pin no.
Name
NP
Description
RB
An external sample and hold phase comparator gain programming resistor should be connected
between this pin and VSS. IRB 300µA at VDD = 3.8V.
19
CH
An external hold capacitor should be connected between this pin and VSS
.
20
PROGRAMMING
ReferenceDividerChain
Note that M>A and
The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of th ‘R’ counter,
which can be programmed in the range 3 to 2047, and a fixed
divide by two stage.
fVCO
N =
fcomp
For example, if the desired VCO frequency = 275MHz, the
comparisonfrequencyis12·5kHzandatwo-modulusprescaler
of ÷ 64/65 is being used, then
fosc
R =
2xfcomp
275x106
12·5x103
N =
= 22x103
where fosc = oscillator frequency,
fcomp = comparison frequency,
R = ‘R’ counter ratio
For example, where the crystal frequency = 10MHz and a
channelspacingcomparisonfrequencyof12·5kHzisrequired,
Now, N = MP+A, which can be rearranged as N/P = M+A/P.
In our example we have P = 64, therefore
22x103
A
64
= M+
107
2x12·5x103
64
R =
= 400
such that M = 343 and A/64 = 0.75.
Thus,the‘R’registerwouldbeprogrammedto400expressed
in binary. The total division ratio would then be 2X400 = 800
since the total division ratio of the ‘R’ counter plus the÷ 2 stage
is from 6 to 4094 in steps of 2.
Now, M is programmed to the integer part = 343 and A is
programmed to the fractional partx64 i.e., A = 0·75x64 = 48.
NB The minimum ratio N that can be used is P2–P (4032 in our
example) for all contiguous channels to be available.
VCODividerChain
To check: N = 343x64+48 = 22000, which is the required
division ratio and is greater than 4032 ( = P 2–P ).
Thesynthesisedfrequencyofthevoltagecontrolledoscillator
(VCO) will depend on the division ratios of the ‘M’ and ‘A’
counters, the ratio of the external two-modulus prescaler
(P/P+1)and the comparison frequency .
When re-programming, the counters are changed only at
the zero state. There is no reset to zero, which means that the
synthesiserlooplockuptimewillbevariablewithrespecttothe
programming sequence timing. When only small changes in
frequency are required, the NJ88C29 non-resettable
synthesiser should achieve the shortest loop lock up times.
The division ratio N = MP+A,
where M is the ratio of the M counter in the range 3 to 1023
and A is the ratio of the ‘A’ counter in the range 1 to 127.
t
t
CL
CH
CLOCK
ENABLE
DATA
t
t
ES
t
t
t
ES
EH
EH
t
DS
DH
Fig. 3 Timing diagram showing timing periods required for correct operation
1
2
(15)26
(16)27
(17)28
3
4
5
CLOCK
ENABLE
DATA
A
A
A
A
A
(M )R
(M )R
(M )R
0 0
6
5
4
3
2
2
2
1
1
Fig. 4 Timing diagram showing programming details
4
NJ88C29
PHASECOMPARATORS
Noise output from a synthesiser loop is related to loop gain:
KPD KVCO
is sufficient if the required sideband performance is not
high.The output from the sample and hold phase detector
should be combined with that of the coarse phase/frequency
detector and filtered to generate a single control voltage to
drive the VCO. The PDB gain is:
N
where KPD is the phase detector constant (volts/rad), KVCO is
the VCO constant (rad/sec-volt) and N is the overall loop
division ratio. When N is large and the loop gain is low, noise
may be reduced by employing a phase comparator with a high
gain. The sample and hold phase comparator in the NJ88C29
has a high gain and uses a double sampling technique to
reduce spurious outputs to a low level.
VDD
4π
KPDB
=
The stated minimum of 3 for the ‘M’ counter is true for the
PDBoutputonly. Toavoidraceconditionsintheinternalphase
comparatorcounterforcontrollingthePDAtiming,theminimum
division ratio for the ‘M’ counter should be 8 or more. Fig. 6
shows a typical NJ88C29 application.
Astandarddigitalphase/frequencydetectordrivingathree-
state output, PDB, provides a ‘coarse’ error signalto enable
fast switching between channels.
The PDB output is active until the phase error is within the
sample and hold phase detector window, when PDB becomes
high impedance. Phase-lock is indicated at this point by a low
level on LD. The sample and hold phase detector provides a
‘fine’ error signal to give further phase adjustment and to hold
theloopinlock. Aninternallygeneratedramp, controlledbythe
digital output from both the reference and main divider chains,
is sampled at the reference frequency to give the ‘fine’ error
signal, PDA. When in phase lock, this output would be typically
at the bias voltage set by the external loop filter amplifier; any
offset from this would be proportional to phase error.
The relationship between this offset and the phase error is
the phase comparator gain, KPDA, which is programmable with
an external resistor, RB, and a capacitor, CAP. An internal
100pF capacitor is used in the sample and hold comparator.
Typically, the gain is given by:
CRYSTALOSCILLATOR
When using the internal oscillator, the stability may be
enhanced at high frequencies by the inclusion of a resistor
between pin 10 (OSC OUT) and the other components, as
shown in Fig. 5. A value of between 220Ω and 2·2kΩ is
advised, depending on the crystal series resistance.
NJ88C29
9
10
2·2k
αIRB
SERIES
68p
100
KPDA
=
2π CCAP
f
comp
5 – 65p
where CCAP = internal 100pF+CEXT. Application Note AN112
deals with this further.
A hold capacitor (CH) of non-critical value, which might be
typically 470pF, is connected from pin 18 to VSS. A smaller
value
Fig. 5 Suggested crystal oscillator circuit
C2
R1a
R2
1
K
K
PDA
9
–
÷R
÷2
OSC IN
R1b
V
+
2
5
-
PDB
+
BIAS
F
in
÷M
÷A
R3
C3
÷P/P+1
NJ88C29
17 MC
K
VCO
s
f
out
Fig.6 NJ88C29 application circuit
5
NJ88C29
PROGRAMMING/POWER UP
LOOP EQUATIONS
1
3
All data and signal input pins should have no input applied
to them prior to the application of VDD, as otherwise latch-up
may occur. When programming the device, DATA, ENABLE
andCLOCKpinsmustnotexceedVDD aslockuptimesmaybe
compromised. A suggested interface to prevent this situation
is shown in Fig. 7.
KVCO KPD
N R C2 C3 R3
w0 =
ζ =[(KVCO KPD R2 ) / {(NC3 R3 ω02 )–1}]/2R
C3R3 = [ ωo (2ζ+R)]–1
Nω0(1+2ζR)
V
(> V )
DD
R2 =
CC
V
DD
KVCO
KPD ( R+2ζ)
2k
KVCO
K
PD (2ζ+R)
C2 =
2
N R ω0
PROGRAMMING
DEVICE
NJ88C29
ω0 = loop natural frequency
ζ = damping factor
R = ratio of real pole to ω0
N = MP+A
1N5711
where
KPD = KPDA /R1a
KPD = KPDB /R1b
R1a >> R1b
Fig. 7 Suggested programming circuit
or
provided
VDD–[(VT+)+(VT–)]Nfcomp
2π KPDA
PDA window =
Further details are to be found in Application Note AN112.
6
NJ88C29
7
NJ88C29
11
10
20
1
5.21/5.38
(0.205/0.212)
7.764/7.899
(0.301/0.311)
PIN 1 IDENT
0.254/0.381
(0.010/0.015)
1.676/1.778
(0.066/0.070)
1.727/1.981
(0.065/0.078)
0.6502
(0.0256)
REF
0.559/0.940
(0.022/0.037)
0.127/0.229
(0.005/0.009)
7.061/7.341
(0.278/0.289)
20 - LEAD SHRUNK MINIATURE PLASTIC DIL - NP20
CUSTOMER SERVICE CENTRES
HEADQUARTERS OPERATIONS
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• NORTH AMERICA Integrated Circuits and Microwave Products Scotts Valley, USA
Tel (408) 438 2900 Fax: (408) 438 7023.
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000
Fax: (0793) 518411
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These are supported by Agents and Distributors in major countries world-wide.
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
© GEC Plessey Semiconductors 1993 Publication No. DS3889 Issue No. 1.6 December 1993
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
8
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performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee
that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any
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