PCA844 [ZARLINK]
Read Channel, 1 Channel, PQFP64, PLASTIC, QFP-64;
| 型号： | PCA844 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Read Channel, 1 Channel, PQFP64, PLASTIC, QFP-64 驱动 接口集成电路 |
| 文件： | 总11页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
July 1993
PRELIMINARY INFORMATION
DS3827 -1.0
PCA844
SINGLE ZONE MODD READ CHANNEL CHIP
FOR DATA RATES BETWEEN 5 AND 15 MBITS/SEC
GENERAL DESCRIPTION
The Filter provides the normal low-pass and differentiated
outputs used by the on-chip pulse position detector. This detector
generates RAWDATA pulses for clock and data recovery in the
phase-lock loop.
The PCA844 is a low power monolithic mixed signal fully-
integrated Read Channel IC for use in optical disk drive (MODD)
applications. It is designed for use in drives with a single zone
facility. The data rate handling capability of the chip can be
externally selected for the data to be accessed at a rate of
between 5 and 15 Mbits/sec. The chip requires only a single 5
volt ±10% power supply.
A full functional block diagram of the PCA844 will be found
in Figure 1.
It contains all the necessary Read Channel functions;
including AGC Loop, Programmable Active Bessel Filter, Pulse
Detector, Sector Mark Detector and Phase Locked Loop; to
interface with the head pre-amplifiers and data controller and
ENDEC functions. The architecture of the chip is designed such
as to provide the maximum amount of flexibility for different drive
electronics designs and partitioning, whilst minimizing the number
of external components required.
FEATURES
■ Single rail 5V ±10% operation
■ 5 to 15 Mbits/sec selectable data rates
■ Low power plus power down modes
■ Compatible with 2,7 RLL coding
■ Dual AGC functions for ROM and MO data
■ On-chip Filtering
■ Programmable cut-off and boost
■ Sector Mark signal regeneration
■ MODD Pulse Detector
■ PLL with on-chip timing components
■ Data Synchroniser
■ Preamble Detection to (8 or 16 x 3T pattern)
■ 64 pin Plastic Quad Flat Pack package
Data is input to the PCA844 from the laser head photodiodes
via current-to-voltage conversion pre-amplifiers. This data would
usually be in the form of differential signals, however, the chip
is also capable of handling single ended input signals by tying
one set of data input to a reference voltage. The use of
differential input signal design techniques significantly reduces
noise within the circuitry.
Dual AGC inputs are provided for the ROM data (read only
area of the disk) and for the MO data (read and write area)
signals. On the PCA844 the ROM input signal range has been
set at 70mV to 600mV and the MO range at 35mV to 300mV
(peak to peak differential). On-chip circuitry regenerates the
digital sector mark signal from a low-level analog input.
The outputs of the AGCs are multiplexed into a full 7th order
Bessel Filter. This filtering is incorporated on-chip along with the
necessary programmable cut-off and boost functions for the
range of data rates supported by the chip. The boost can be
used to equalise the higher frequency components in the MODD
signal.
1
PCA844
BLOCK DIAGRAM
Figure 1. PCA844 Functional Block Diagram
2
PCA844
DEVICE MAXIMUM RATING
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VCC
7
VCC +0.3
+70
V
V
All Inputs
-0.3
0
Operating Temperature Range
Storage Temperature
°C
°C
-55
+150
POWER
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Operating Voltage Range
Supply Current Mode:
all VCC's
4.5
5.0
5.5
V
SYNCEN
PULEN
Sleep
Pulse Detect. Enabled
Full Power Up
0
0
1
0
1
1
15
70
120
mA
Note: Supply currents are calculated with all inputs high, and no load on the outputs.
DIGITAL INPUTS AND OUTPUTS
Digital circuit characteristics over the operating temperature and voltage range.
Parameter
TTL Inputs
Test Conditions
Min.
Typ.
Max.
Units
Low Level Input Voltage
High Level Input Voltage
Low Level Input Current
High Level Input Current
0
2.0
0.8
VCC
200
10
V
V
µA
µA
VIL = 0.4
VIH = VCC
TTL Outputs
Low Level Output Voltage
High Level Output Voltage
Output Source Current
Output Sink Current
IOL = 4mA
IOH = -400µA
VOH = 2.4
0.5
V
V
mA
mA
2.4
1
4
VOL = 0.5V
3
PCA844
AGC LOOP AND FILTER
external resistors and capacitors on pins RAGCMO/CD and
CAGCMO/CD.
There are two independent AGC amplifiers which accept
input signals from the read only (CD) and the read/write (MO)
parts of the disk. The amplifier outputs are multiplexed into a
filter which has a single 7th order low pass Bessel output
(NORM), and a differential differentiated out (DIFFP, DIFFN).
For the comparator which is not selected by IPSEL at any
time, the pins CAGC and RAGC will be high impedance to hold
the current gain setting for that channel. In addition, bothAGC
control voltages may be held simultaneously by taking the TTL
input AGCHOLD high.
These outputs are AC coupled to the pulse detector. The
filter is on chip and has programmable bandwidth and boost.
The TTL input SQUELCH when high, reduces the gain of
AGC amplifier to minimum. The input VIMP, when high,
introduces a low impedance between the AGC inputs.
The TTL input IPSEL multiplexes the AGC inputs and
selects the appropriate AGC control voltage. When IPSEL=1,
MO is active; when IPSEL=0, CD is active.
The internally generated reference VACREF is a low
impedance voltage source of VCC/2, used to bias the inputs to the
pulse detector. The pin must be externally decoupled and set up
so that a minimum of current is sourced from the pin. The pin
cannot sink current.
The single-ended output of the filter NORM is passed to the
AGC control comparators and compared with external AGCSET
voltage which defines the level of the peaks at PULDETIN. The
output of the comparators, CAGCMO & CAGCCD are gain
control voltages for the AGC amplifier. The rate of attack and
decay of these voltages can be set set independently by the
Digital circuit characteristics over the operating temperature and voltage range.
Parameter
Test Conditions
Min.
Typ.
Max.
Units
CD Signal Input Range
MO Signal Input Range
p-p differential
p-p differential
70
35
600
300
mV
mV
AGC Gain Range
8.5
V/V
MHz
%
Filter Cut Off - fc
3dB - no boost
fc=22.5 MHz
4.0
-10
22.5
+10
Filter fc Accuracy
Max. Programmable Boost
at Unboosted fc
3T to 8T pattern
15
7
dB
dB
6
8
Boost Level Accuracy
Max. Boost
-1
+1
dB
Filter Output Voltage
- DIFF
p-p differential
p-p single
1.5
1.5
V
V
- NORM
AGC Gain Control
Active Region
2.3
3.3
V
The level of high frequency boost when applied (BOOST=HI) may be calculated from the following formula.
Fbst = 20*log
(6.18*BOOSTSET - 1.38*VCCFILT)
(VCCFILT - 1.4*BOOSTSET)
dB
[
]
where :
BOOSTSET = Boost level control voltage (pin 50)
VCCFILT = Filter VCC supply (pin 56) (5V nom.)
Note : BOOSTSET must be related to VCCFILT and that the above formula holds for BOOSTSET from 0.3VCCFILT
to 0.5 VCCFILT. With BOOSTSET below 0.3 VCCFILT the boost level is zero, and with BOOSTSET above 0.5
VCCFILT the boost level is maximum.
4
PCA844
PULSE POSITION DETECTOR
the peaks of the input signal to eliminate false differentiator zero
crossings. The threshold and zero crossing comparators drive
the qualification logic which provides a positive fixed-duration
digital output at RAWDAT for each peak detected.
This system detects the position of the positive peaks in the
analog signal from the filter, and generates the digital pulses
used for clock and data recovery in the Phase-Locked Loop.
The differentiated outputs of the filter DIFFN and DIFFP are
externally AC-coupled into the zero crossing detector at pins
ZCP and ZCN. The normal filter output NORM is AC-coupled
into the threshold comparator (and AGC control comparators) at
PULDETIN, and compared with the DC level on the THRESH
pin. The threshold comparator provides gate pulses to qualify
The qualifier output also fires an on-chip tracking monostable
which provides 1/4 cell wide pulses. These pulses are used in
the phase detector and data synchroniser sections of the PLL.
In test mode, the gate and zero-crossing comparator outputs
can be monitored.
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Threshold Comparator
Input Voltage
Pk-Pk
1.5
V
Threshold Comparator
Input Voltage
5
mV
%
Threshold Comparator
Threshold
relative to VACREF
50
Zero Crossing Comparator
Input Offset Voltage
5
mv
MHz
ns
Zero Crossing Comparator
Bandwidth
30
50
20
RAWDAT Pulse Width
PHASE LOCK LOOP
switched; the clamp is then released on the 3rd rising edge of
the new data stream (from REFCLK or the 1/4 cell mono). This
ensures that the restarted VCO is in near phase lock with the
initial data.
The 'data' input to the PLL block is either 1/4 Cell tracking
monostable pulses (when RDGATE=1); or the reference clock,
REFCLK (when RDGATE=0). The reference clock is a square
wave with a frequency equal to twice the data rate (2/7 coding).
The 1/4 cell monostable pulse width tracks variations in the
VCO period.
The data synchroniser operates on the (phase locked)
inputs to the phase detector and produces the recovered data
and clock outputs at SYNCDT an SYNCLK respectively. The
SYNCLK pulses are one VCO period wide and change state on
the falling edges of SYNCLK. In a test mode the phase detector
/synnchroniser inputs PDDAT and PDCLK can be observed.
The PLL synchronises the VCO to the data pulses. A digital
phase detector compares the data signal with the VCO to
produce UP and DOWN pulses at CP1 to increase or decrease
the VCO frequency. A loop filter amplifier provides a control
voltage for the VCO and tracking monostable at CP3. External
loop filter components connected between pins CP1, CP2, and
CP3 are used to set the natural frequency and damping factor
of the PLL.
Preamble Detection
If RDGATE=1, the TTL output, PREDET, goes high as soon
as the required preamble sequence has been detected in the
synchronised data. PREDET then remains high irrespective of
subsequent data pattern until RDGATE is taken low. When
RDGATE=0, PREDET=0.
The frequency of the VCO is defined by the sum of two
current components: a fixed current, set by the external resistor
between the pin CEN and VCCPLL; and a variable current, set
by the resistor between the pins VCOI and CP3 (the control
voltage). R(VCOI) determines the gain of the VCO.
The preamble sequence to be detected is set by the TTL
input PRESEL: when PRESEL=0 the sequence is eight
consecutive 3T patterns; when PRESEL=1 the sequence is
sixteen consecutive 3T patterns;
For each RDGATE transition, the VCO is halted using an
internally generated clamp signal: the PLL data multiplexor is
5
PCA844
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VCO Frequency Range
10
30
MHz
VCO Centre Frequency Drift
VCO Jitter
0 to +70°C
±
5
1
%
ns
VCO Duty Cycle
internal
49
50
0.1
±
51
%
V/rad
ns
Phase Detector Gain
Window Centering
CP1 Output Current
CP2 Input Current
CP3 Centre Voltage
0.5
1.0
10
mA
µA
2.8
V
SECTOR MARK DETECTOR
This block consists of a differentiator, Comparators, RS
Latch, and a TTL Output Buffer. The input signal is a low
amplitude sector mark data pattern with relatively slow edges.
The output (at SMDATA) is an amplified TTL compatible
version of the input signal with relatively fast edges. The sector
mark pattern detecting logic is off-chip.
The differentiator output is given by:
Vout = 6000 x Cext x d/dt(Vin)
The differentiator produces positive and negative pulses
corresponding to the rising and falling edges of the input signal.
The differentiator outputs are AC coupled into the positive inputs
of two comparators at SIN and RIN,which are dc biased at
VACREF via internal resistors. The negative inputs of the
comparators are both connected to SMTHRESH which is an
external DC threshold, and should typically be set to a few
hundred millivolts above VACREF.
The sector mark detector has independent differential
input pins at SMINP and SMINN. These are connected to the
differentiator, which has outputs at SMDIFFP and SMDIFFN.
The gain and high-frequency pole of the differentiator are set
by the external series capacitor and resistor connected between
the pins SMEX1 and SMEX2.
The outputs of the comparators drive the set and reset inputs
of the internal SR latch to produce the SMDATA output.
Parameter
Test Conditions
ptp differential
ptp differential
Min.
Typ.
Max.
500
4
Units
mV
V
SM Input Voltage
50
Differential Output Swing
TEST MODES
The TTL input, NTEST, is used to provide test modes for
ATE purposes, and for evaluating mixed mode functions with
embedded logic eg. PLL and pulse detector.
When NTEST=1 (or floating) the device operates normally.
When NTEST=0, the function of certain TTL inputs are redefined
depending upon the state of SQUELCH and VIMP, as follows:
Mode
Mode Select
PLL Inputs
TTL Outputs
NTEST SQUELCH VIMP
PLLDATA
PLLCLK
SYNCDT SYNCLK RAWDAT SMDATA
Normal
1
0
0
X
0
1
X
X
0
mono
(PULDET)
vco
SYNCDT SYNCLK RAWDAT SMDATA
Qualifier Test
Digital Data
mono
(PULDET)
vco
vco
gate
zc
RAWDAT SMDATA
mono
(IPSEL)
SYNCDT SYNCLK
pddat
pddat
pdclk
pdclk
ATE
0
1
1
IPSEL
AGCHOLD SYNCDT SYNCLK
6
PCA844
'gate' is the output of the comparator which compares
PULDETIN and THRESH in the pulse detector. 'zc' is the
output of the differentiator zero-crossing comparator. In the
'qualifier test' mode, these logic signals can be observed at the
TTL outputs shown above.
normally fired by the pulses detected in the qualifier logic
(PULDET). In the 'digital data' mode, the mono is fired directly
by positive edges at the IPSEL TTL input. This allows easy
bench evaluation of PLL using a digital signal generator,
without the need for the full analog AGC loop and filter to
operate.
'pddat' and 'pdclk' are the internal inputs to the phase
detector and data syncroniser. When the PLL is locked, these
signals will be phase-aligned.
In the ATE mode, the IPSEL and AGCHOLD pins are
substituted directly for the normal output signals from the vco
and mono circuits (ie the mono is bypassed completely).
'mono' refers to the 1/4 cell tracking monostable. This is
The PREDET TTL output always retains its normal function.
PIN LIST AND DESCRIPTIONS
Pin
Name
Type Function
Not Connected
1
2
3
4
5
6
7
8
9
N/C
SMDIFFN O/P Sector Mark Differentiator -ve output signal
SMDIFFP O/P Sector Mark Differentiator +ve output signal
SMTHRESH I/P
Threshold Voltage for sector mark comparators
Input for 'reset' for sector mark comparator
Input for 'set' for sector mark comparator
RIN
SIN
VIMP
IPSEL
I/P
I/P
I/P
I/P
TTL Compatible. High activates impedance switch at AGC inputs. Low for normal operation
TTL Compatible. Selects one of the two input channels. High selects MO, Low selects CD
TTL Compatible. High forces AGC into minimum Gain Mode. Low for normal operation
TTL Compatible. High holds the AGC control voltage level
TTL Compatible. Test Mode Control. See spec. for details
TTL Compatible. Reference Clock Frequency
TTL Compatible. Pre-Amble Detect Mode Select. High selects 16 x 3T, low 8 x 3T Detect
Not Connected
SQUELCH I/P
10 AGCHOLD I/P
11 NTEST I/P
12 REFCLK I/P
13 PRESEL I/P
14
15
16
N/C
N/C
VCCPLL
Not Connected
Phase Locked Loop VCC conection
17 GNDPLL
Phase Locked Loop Ground conection
18
19
20
21
22
23
24
N/C
VCOI
CEN
CP3
CP2
Not Connected
Control Iput for to VCO
VCO Centre Frequency Current Input
I/P
I/P
O/P Loop Filter Amplifier Output (VCO) control voltage)
I/P Loop Filter Amplifier Input
O/P Charge Pump Output
Digital VCC connection
CP1
VCCDIG
25 RDGATE I/P
TTL Compatible. High activates Read Mode - VCO Locks to Data. Low - VCO locks to REFCLK
26 PRESEL O/P TTL Compatible. High when selected Pre-Amble pattern has been detected
27 RAWDAT O/P TTL Compatible. Unsynchronised detected raw data
28 SYNCDT O/P TTL Compatible. Read Data, synchronised to SYNCLK
29 SYNCLK O/P TTL Compatible. Recovered VCO clock
30 SMDATA O/P TTL Compatible. Sector Mark Data Output
31
N/C
Not Connected
32 GNDDIG
Digital Ground connection
33 SYNCEN I/P
TTL Compatible. PLL Power Up Enable
TTL Compatible. Pulse Detector Power Up Enable. See spec. for Power Up Control Truth Table
AGC Control Comparator Threshold Voltage
34
PULEN
I/P
35 AGCSET I/P
36 RAGCCD O/P Control Voltage Discharge Resistor (CD loop)
37 CAGCCD O/P AGC Control Voltage (CD loop)
38 RAGCMO O/P Control Voltage Discharge Resistor (MO loop)
39 CAGCMO O/P AGC Control Voltage (MO loop)
40
41
ZCN
ZCP
I/P
I/P
Zero Crossing Comparator -ve input
Zero Crossing Comparator +ve input
Pulse Detector Threshold Voltage
Pulse Detector Input
42 THRESH I/P
43 PULDETIN I/P
44
VACRF
O/P Circuit Reference Voltage (VCCANA/2)
Analog VCC connection
45 VCCANA
7
PCA844
46
NORM
O/P Filter NORMAL (single ended) output
Analog Ground connection
47 GNDANA
48
49
DIFFP
DIFFN
O/P Filter Differentiated Output, +ve
O/P Filter Differentiated Output, -ve
50 BOOSTSET I/P
Filter Boost Level Control
51 IPROGOP O/P Current defined by Rfcset is available at this pin. This can be used as a reference current for
a DAC, or connected directly to pin 52 for fixed value fc
52 IPROGIP I/P
Filter fc Programming Current Input. Can be obtained directly from pin 51, or from a
frequency control DAC
53
54
55
FCSET
MON
MOP
fc Programming Resistor (Rfcset) connection
MO Channel -ve Input Signal
MO Channel +ve Input Signal
I/P
I/P
56 VCCFILT
Filter VCC connection
57
58
59
60
CDP
CDN
SMINP
SMINN
I/P
I/P
I/P
I/P
CD Channel +ve Input Signal
CD Channel -ve Input Signal
Sector Mark Differentiator +ve Input Signal
Sector Mark Differentiator -ve Input Signal
TTL Compatible. High Enables Filter Boost function. Low - no boost irrespective of
BOOSTSET voltage
61 BOOSTEN I/P
62
63
SMEX2
SMEX1
SM Differentiator external component connection
SM Differentiator external component connection
Filter Ground connection
64 GNDFILT
PIN OUT DIAGRAM
N/C 1
SMDIFFN 2
48 DIFFP
47 GNDANA
46 NORM
SMDIFFP 3
SMTHRESH 4
RIN 5
45 VCCANA
44 VACRF
43 PULDETIN
42 THRESH
41 ZCP
SIN 6
VIMP 7
PCA844
IPSEL 8
64 PIN QFP
SQUELCH 9
AGCHOLD 10
NTEST 11
REFCLK 12
PRESEL 13
N/C 14
40 ZCN
39 CAGCMO
38 RAGCMO
37 CAGCCD
36 RAGCCD
35 AGCSET
34 PULEN
33 SYNCEN
N/C 15
VCCPLL 16
14 x14mm Square Package
8
PCA844
PRIMARY SEMI-CUSTOM DESIGN CENTRES
UNITED KINGDOM: Swindon, Tel: (01793) 518000 Fax: (01793) 518411. Oldham, Tel: (0161) 682 6844, Fax: (0161) 688
7898. Lincoln, Tel: (01522) 500500 Fax: (01522) 500550. UNITED STATES OF AMERICA: Scotts Valley, CA, Tel: (408)
438 2900 Fax: (408) 438 5576. Boston, MA, Tel: (617)251-0100. Fax: (617) 251-0104. Irvine, CA, Tel: (714) 455-2950.
Fax: (714) 455-9671. AUSTRALIA: Rydalmere, NSW, Tel: (612) 638 1888. Fax: (612) 638 1798. FRANCE: Les Ulis
Cedex, Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07. ITALY: Milan, Tel: (02) 66040867 Fax: (02) 66040993. GERMANY:
Munich, Tel: (089) 3609 06 0 Fax: (089) 3609 06 55. JAPAN: Tokyo, Tel: (3) 5276-5501. Fax: (3) 5276-5510.
CUSTOMER SERVICE CENTRES
HEADQUARTERS OPERATIONS
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire, United Kingdom SN2 2QW.
Tel: (01793) 518000
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
Fax: (01793) 518411
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm, Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
•
TAIWAN, ROC Taipei, Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY
Swindon Tel: (01793) 518510 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1993 Publication No.DS3827 Issue No. 1.0 July 1993
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
Fax: (408) 438 5576
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be
regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service.
The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and
does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment
using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may
result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or
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use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such
information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or
parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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