PDSP16116/MC/GC1R [ZARLINK]

Multiplier, CMOS, PQFP144, QFP-144;


型号：	PDSP16116/MC/GC1R
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	Multiplier, CMOS, PQFP144, QFP-144 时钟外围集成电路
文件：	总15页 (文件大小：125K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PDSP16116

16 X 16 Bit Complex Multiplier

DS3707

ISSUE 6.0

November 1998

The PDSP16116 contains four 16316 array multipliers, two

32-bit adder/subtractors and all the control logic required to sup-

port Block Floating PointArithmetic as used in FFT applications.

The PDSP16116A variant will multiply two complex (16116)

bit words every 50ns and can be configured to output the com-

plete complex (32132) bit result within a single cycle. The data

format is fractional two’s complement.

In combination with a PDSP16318A, the PDSP16116Aforms

a two-chip 20MHz complex multiplier accumulator with 20-bit

accumulator registers and output shifters. The PDSP16116Ain

combination with two PDSP16318As and two PDSP1601As

forms a complete 20MHz Radix 2 DIT FFT butterfly solution

which fully supports block floating point arithmetic. The

PDSP16116 has an extremely high throughput that is suited to

recursive algorithms as all calculations are performed with a

single pipeline delay (two cycle fall-through).

Ordering Information

PDSP16116/MC/GC1R

PDSP16116A B0 AC

PDSP16116A A0 AC

10MHz MIL-883 screened

20MHz Industrial

20MHz Military

PDSP16116A/IG/GC1R 20MHz Industrial

PDSP16116A/MC/GC1R 20MHz MIL-883 screened

PDSP16116B B0 AC 25MHz Industrial

PDSP16116D IG/GC1R 31.5MHz Industrial

XR15:0

REG

XI15:0

REG

YR15:0

REG

YI15:0

REG

FEATURES

• Complex Number (16116)3(16116) Multiplication

• Full 32-bit Result

• 20MHz Clock Rate

• Block Floating Point FFT Butterfly Support

• (21)3(21) Trap

• Two’s Complement Fractional Arithmetic

• TTL Compatible I/O

• Complex Conjugation

• 2 Cycle Fall Through

• 144-pin PGA or QFP packages

MULT

REG

MULT

REG

MULT

REG

MULT

REG

APPLICATIONS

ADD/SUB

• Fast Fourier Transforms

• Digital Filtering

• Radar and Sonar Processing

• Instrumentation

• Image Processing

SHIFT

REG

PR15:0

PI15:0

Figure 1 - Simplified block diagram

ASSOCIATED PRODUCTS

PDSP16318/A Complex Accumulator

PDSP16112/A (16116)3(12112) Complex Multiplier

PDSP16330/A Pythagoras Processor

PDSP1601/A ALU and Barrel Shifter

PDSP16350

PDSP16256

Precision Digital Modulator

Programmable FIR Filter

PDSP16510A Single Chip FFT Processor

PDSP16116

SYSTEM FEATURES

Complex Conjugation

The PDSP16116 has a number of features tailored for sys-

tem applications.

Many algorithms using complex arithmetic require conjuga-

tion of complex data stream. This operation has traditionally re-

quired an additional ALU to multiply the imaginary component

by -1. The PDSP16116 eliminates this requirement by offering

on-chip complex conjugation of either of the two incoming com-

plex data words with no loss in throughput.

(21)3(21) Trap

In multiply operations using two’s complement fractional no-

tation, the (21)3(21) operation forms an invalid result because

11 is not representable in the fractional number range. The

PDSP16116 eliminates this problem by trapping the (21)3(21)

operation and forcing the multiplier result to become the most

positive representable number.

Easy Interfacing

As with all PDSP family members the PDSP16116 has reg-

istered l/O for data and control. Data inputs have independent

clock enables and data outputs have independent three state

output enables.

Normal

mode

Signal

Type

Description

configuration

XR15:0

Input

16-bit input for real X data

Xl15:0

Input

16-bit input for imaginary X data

16-bit input for real Y data

YR15:0

Yl15:0

Input

16-bit input for imaginary Y data

16-bit output for real P data

PR15:0

Pl15:0

Output

Input

16-bit output for imaginary P data

Clock; new data is loaded on rising edge of CLK

Clock, enable X-port input register

Clock, enable Y-port input register

Conjugate X data

CLK

CEX

Input

CEY

Input

CONX

Input

CONY

Input

Conjugate Y data

ROUND

MBFP

Input

Rounds the real and imaginary results

Mode select (BFP/Normal)

Input

Tie low

SOBFP

EOPSS

AR15:1 3

Al15:1 3

WTA1:0

WTB1:0

WTOUT1:0

SFTA1:0

SFTR2:0

GWR4:0

OSEL1:0

OER, OEI

V_DD

Input

Start of BFP operations (see Note 1)

End of pass (See Note 1)

Input

3 MSBs from real part of A-word (See Note 1)

3 MSBs from imaginary part of A-word (See Note 1)

Word tag from A-word

Input

Word tag from B-word/shift control (See Note 2)

Word tag output (See Note 1)

Output

Input

Shift control for A-word / overflow flag (See Note 2)

Shift control for accumulator result (See Note 1)

Global weighting register contents (See Note 1)

Selects the desired output configuration

Output enables

Input

Power

15V Supply (See Note 3)

GND

0V Supply (See Note 3)

NOTES

1. Used only in BFP mode

2. Performs different functions in BFP/Normal modes

3. All supply pins must be connected

Table 1 - Signal descriptions

PDSP16116

XR15:0

REG

CEX

XI15:0

REG

YR15:0

REG

CEY

YI15:0

REG

16316

MULT

16316

MULT

16316

MULT

16316

MULT

‘1’

MUX

REG

MUX

REG

MUX

REG

MUX

REG

OVR

ADD/SUB

CLK

WTA

CONX

CONY

DECODE

AR15:13

WTB

SHIFT

REG

SHIFT

REG

AI15:13

SOBPF

EOPSS

SFTR

INTERNAL

SIGNALS

CONTROL

LOGIC

ROUND

SFTA

GWR4:0

WTOUT

MUX

OSEL

OER

OEI

PR15:0

PI15:0

Figure 2 - PDSP16116 Block diagram

PDSP16116

AC144 (POWER)

Figure 3a - Pin connections for 144 I/O power pin grid array package (bottom view)

PIN 1

PIN 144

PIN 1 IDENT

(SEE NOTE 2)

GC144

Fig. 3b - Pin connections for 144 I/O ceramic quad flatpack (top view)

Figure 3 - Pin connection diagrams (not to scale). See Table 1 for signal descriptions and Table 2 for pinouts.

PDSP16116

Signal

XI1

XI2

XI3

XI4

XI5

XI6

XI7

XI8

XI9

XI10

XI11

XI12

XI13

XI14

XI15

GND

V_DD

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

N14

M13

A14

B12

C11

A13

B11

A12

C10

B10

A11

B13

C12

A10

PI14

PI15

V_DD

GND

PR13

PR12

PR11

PR10

PR9

PR8

PR7

PR6

PR5

GND

V_DD

PR4

PR3

PR2

PR1

PR0

PI0

PI1

PI2

PI3

PI4

V_DD

PI5

GND

PI6

PI7

YR12

YR11

YR10

YR9

YR8

YR7

YR6

YR5

YR4

YR3

YR2

YR1

YR0

P15

M14

L13

N15

L14

M15

K13

K14

L15

J14

J13

K15

J15

H14

H15

H13

G13

G15

F15

G14

F14

F13

E15

E14

D15

C15

D14

E13

C14

B15

D13

C13

B14

A15

WTOUT1

WTOUT0

SFTR0

SFTR1

SFTR2

OEI

CONX

CONY

ROUND

AI13

AI14

AI15

AR13

AR14

AR15

YI15

YI14

YI13

YI12

YI11

YI10

YI9

YI8

YI7

YI6

YI5

YI4

YI3

YI2

YI1

CEY

EOPSS

V_DD

CEX

XR15

R10

SOBFP

WTB1

XR14

XR13

XR12

XR11

XR10

XR9

XR8

XR7

XR6

XR5

WTB0

WTA1

WTA0

MBFP

CLK

P10

N10

R11

P11

R12

R13

P12

N11

P13

R14

N12

N13

P14

R15

OSEL1

OSEL0

OER

SFTA0

100

101

102

103

104

105

106

107

108

XR4

XR3

XR2

XR1

SFTA1

GWR0

GWR1

GWR2

GWR3

GWR4

PR15

PI8

PI9

PI10

PI11

PI12

PI13

GND

V_DD

XR0

YI0

XI0

GND

V_DD

YR15

YR14

YR13

PR14

NOTE. All GND and V_DDpins must be used

Table 2 - Pin connections for AC144 (Power) and GC144 packages

PDSP16116

NORMAL MODE OPERATION

When the MBFP mode select input is held low the ‘Normal’

mode of operation is selected. This mode supports all complex

multiply operations that do not require block floating point

arithmetic.

Complex two’s complement fractional data is loaded into the

X and Y input registers via the X and Y Ports on the rising edge

of CLK. The X and Y port registers are individually enabled by

CEX CEY

signals respectively. If the registers are re-

quired to be permanently enabled, then these signals may be

tied to ground.

The Real and Imaginary components of the fractional data

are each assumed to have the following format:

the

and

Bit Number

Weighting

15 14 13 12 11 10

2^–12^–22^–32^–42^–52^–62^–72^–82^–92^–102^–112^–122^–132^–142^–15

Where S = sign bit, which has an effective weighting of 22⁰

The value of the 16-bit two’s complement word is (213S)1(bit1432²¹)1(bit1332²²)1(bit1232²³) …

Multiplier Stage

Oneachclockcyclethecontentsoftheinputregistersarepassed

to the four multipliers to start a new complex multiply operation.

Each complex multiply operation requires four partial products

(XR3YR), (XR3YI), (XI3YR), (XI3YI), all of which are calculated

in parallel by the four 16316 multipliers. Only one clock cycle is

required to complete the multiply stage before the multiplier results

are loaded into the multiplier output registers for passing on to the

adder/ subtractors in the next cycle. Each multiplier produces a 31-

bit result with the duplicate sign bit eliminated. The format of the

output data from the multipliers is:

Bit Number

Weighting

30 29 28 27 26 25 24

2^–12^–22^–32^–42^–52^–6

2^–232^–242^–252^–262^–272^–282^–292^–30

The effective weighting of the sign bit is 22⁰

Adder/Subtractor Stage

The 31-bit real and imaginary results from the multipliers

are passed to two 32-bit adder/subtractors. The adder calcu-

lates the imaginary result [(XR 3 YI) 1 (XI 3 YR)] and the

subtractor calculates the real result (XR 3 YR) = (XI 3 YI).

Each adder/subtractor produces a 32-bit result with the

following format:

Bit Number

Weighting

31 30 29 28 27 26

2⁰2^–12^–22^–32^–4

^–222^–232^–242^–252^–262^–272^–282^–292^–30

The effective weighting of the sign bit is 22¹

Rounding

significant 16 bits are unaffected). Inserting a ‘1’ ensures that

the rounding error is never greater than 1 LSB and that no DC

bias is introduced as a result of the rounding processes. The

format of the rounded result is:

The ROUND control when asserted rounds the most

significant 16 bits of the full 32-bit result from the shifter. If the

ROUND signal is active (high), then bit 16 is set to ‘1’, rounding

the most significant 16 bits of the shifted result. (The least

Bit Number

Weighting

31 30 29 28 27

2⁰2^–12^–22^–3

18 17 16 15 14 13

^–122^–132^–142^–152^–162^–17

2^–282^–292^–30

ROUNDED VALUE

LSBs

The effective weighting of the sign bit is 22¹

Result Correction

Complex Conjugation

Due to the nature of the fraction two’s complement repre-

sentation it is possible to represent 21 exactly but not 11. With

conventional multipliers this causes a problem when 21 is mul-

tiplied by 21 as the multiplier produces an incorrect result. The

PDSP16116 includes a trap to ensure that the most positive

number (value = 1·2²³⁰, hex = 7FFFFFFFF) is substituted for

the incorrect result. The multiplier result is therefore always a

correct fractional value. Fig.2 shows the value ‘1’ being multi-

plexed into the data path controlled by four comparators.

Either the X or Y input data may be complex conjugated by

asserting the CONX or CONY signals respectively. Asserting

either of these signals has the effect of inverting (multiplying

by 21 ) the imaginary component of the respective input. Table 3

shows the effect of CONX and CONY on the X and Y inputs.

Operation

CONX

CONY

Function

Low

High

Low

High

Low

High

X 3 Y

(XR 1 XI)3(YR 1 YI)

Conj. X 3 Y (XR 2 XI)3(YR 1 YI)

X 3 Conj. Y (XR 1 XI)3(YR 2 YI)

Invalid

Table 3 - Conjugate functions

PDSP16116

Shifter

Each of the two adder/subtractors are followed by shifters

controlled via the WTB control input. These shifters can each

apply two different shifts; however, the same shift is applied to

both real and imaginary components. The four shift options are:

1. WTB1:0 = 11 Shift complex product one place to the left, giving a shifter output format:

Bit Number

31 30 29 28 27 26 25

2^–12^–22^–32^–42^–52^–6

Weighting

2^–242^–252^–262^–272^–282^{–29 –30}2^–31

The effective weighting of the sign bit is 22⁰

2. WTB1:0 = 00 No shift applied, giving a shifter output format:

Bit Number

Weighting

31 30 29 28 27 26

2⁰2^–12^–22^–32^–4

^–222^–232^–242^–252^–262^–272^–282^–292^–30

The effective weighting of the sign bit is 22¹

3. WTB1:0 = 01 Shift complex product one place to the right, giving a shifter output format:

Bit Number

Weighting

31 30 29 28 27 26 25 24

2¹2⁰2^–12^–22^–32^–42^–5

2^–232^–242^–252^–262^–272^–282^–29

The effective weighting of the sign bit is 22²

4. WTB1:0 = 10 Shift complex product two places to the right, giving a shifter output format:

Bit Number

Weighting

31 30 29 28 27 26 25 24

2²2¹2⁰2^–12^–22^–32^–4

2^–222^–232^–242^–252^–262^–272^–28

The effective weighting of the sign bit is 22³

Overflow

PIN DESCRIPTIONS

If the left shift option is selected and the adder/subtractor

contains a 32-bit word, then an invalid result will be passed to

the output. An invalid output arising from this combination of

events will be flagged by the SFTA0 flag output. The SFTA0 flag

will go high if either the real or imaginary result is invalid.

XR, XI, YR, YI

Data inputs, 16 bits. Data is loaded into the input registers

from these ports on the rising edge of CLK. The data format is

fractional two’s complement, where the MSB (sign bit) is bit 15.

In normal mode the weighting of the MSB is 22⁰i.e. 21.

Output Select

The output from the shifters is passed to the output select

mux, which is controlled via the OSEL inputs. These inputs are

not registered and hence allow the output combination to be

changed within each cycle. The full complex 64-bit result from

the multiplier may therefore be output within a single cycle. The

OSEL control selects four different output combinations as

summarised in Table 4.

PR, PI

Data outputs, 16 bits. Data is clocked into the output regis-

ters and passed to the PR and PI outputs on the rising edge of

CLK. The data format is fractional two’s complement. The field

of the internal result selected for output via PR and PI is control-

led by signals OSEL1:0 (see Table 4).

CLK

OSEL0

Common clock to all internal registers

OSEL1

MSR

LSR

MSR

MSI

LSI

LSR

LSI

CEX, CEY

Clock enables for X and Y input ports. When low these inputs

enable the CLK signal to the X or Y input registers, allowing

new data to be clocked into the Multiplier.

Table 4 Output selection

CONX, CONY

Conjugate controls. If either of these inputs is high on the

rising edge of CLK, then the data on the associated input has its

imaginary component inverted (multiplied by 21), see Table 3.

CONX and CONY affect data input on the same clock rising

edge.

MSR and LSR are the most and least siginificant 16-bit words

of the real shifter output, MSl and LSl are the most and least

significant 16-bit words of the imaginary shifter output.

The output select options allow two different modes for ex-

tracting the full 32-bit result from the PDSP16116. The first mode

treats the two 16-bit outputs as real and imaginary ports, allow-

ing the real and imaginary results to be output in two halves on

the real and imaginary output ports. The second mode treats

the two 16-bit outputs as one 32-bit output and allows the real

and imaginary results to be output as 32-bit words.

ROUND

The ROUND control pin is used to round the most significant 16

bits of the output register. The ROUND input is not latched and is

intended to be tied high or low depending upon the application.

PDSP16116

MBFP

WTOUT1:0 (BFP Mode Only)

Mode select. When high, block floating point (BFP) mode is

selected. This allows the device to maintain the dynamic range

of the data using a series of word tags. This is especially useful

in FFTapplications. When low, the chip operates in normal mode

for more general applications. This pin is intended to be tied

high or low, depending on application.

Word tag output. This tag records the weighting of the output

words from the current cycle relative to the current global

weighting register (see Table 6). It should be stored along with

theA′ and B′ words as it will form the input word tags, WTAand

WTB, for each complex word during the next pass. In normal

mode, WTOUT1:0 are not used and should be left unconnected.

Weighting of the output relative to

the current global weighting register

SOBFP (BFP Mode Only)

WTOUT1:0

Start of BFP. This input should be held low for the first cycle

of the first pass of the BFP calculations (see Fig.7). It serves to

reset the internal registers associated with BFP control. When

operating in normal mode this input should be tied low.

One less

The same

One more

Two more

EOPSS (BFP Mode Only)

End of pass. This input should be held low for the last cycle

of each pass and for the lay time between passes. It instructs

the control logic to update the value of the global weighting reg-

ister and prepare the BFP circuitry for the next pass. When op-

erating in normal mode this input should be tied low.

Table 6 - Word tag weightings

WTA1:0 (BFP Mode Only)

Word tag from the A-word. This word records the weighting

of the A-word relative to the global weighting register on the

previous pass.Although theA-word itself is not processed in the

PDSPl 6116, this information is required by the control logic for

the radix 2 butterfly FFT application. These inputs should be

tied low in normal mode.

AR15:13 (BFP Mode Only)

Three MSBs of the real part of the A-word. These are used

in the FFT butterfly application (see Fig. 4) to determine the

magnitude of the real part of the A-word and, hence, to deter-

mine if there will be any change of word growth in the

PDSP16318 Complex Accumulator. When operating in normal

mode, these inputs are not used and may be tied low.

WTB1:0 (BFP and Normal Modes)

In BFP mode, this is the word tag from the B-word. This is

operated in the same manner as WTA but for the B-word. The

value of the word tags are used to ensure that the binary weight-

ing of the A-word and the product of the complex multiplier are

the same at the inputs to the complex accumulator. Depending

on which word is the larger, the weighting adjustment is per-

formed using either the internal shifter or an external shifter con-

trolled by SFTA. The word tags are also used to maintain the

weighting of the final result to within plus two and minus one

binary points relative to the new GWR. (On the first pass all

word tags will be ignored). In normal mode. these inputs per-

form a different function. They directly control the internal shifter

at the output port as shown in Table 7.

AI15:13 (BFP Mode Only)

Three MSBs of the imaginary part of theA-word. Used in the

same fashion as AR15:13.

SFTR2:0 (BFP Mode Only) Accumulator result shift control.

These pins should be linked directly to the S2:0 pins on the

PDSP16318 Complex Accumulator. They control the

accumulator’s barrel shifter (see Table 5). The purpose of this

shift is to minimise sign extension in the multiplier or accumulator

ALUs. In normal mode, SFTR2:0 are not used and should be

left unconnected.

WTB1:0

Function

Reserved

Shift right by one

No shift

Shift left by one

Shift left by two

Reserved

SFTR2:0

Shift complex product 1 place to the left

No shift applied

Shift complex product 1 place to the right

Shift complex product 2 places to the right

000

001

010

011

100

101

110

111

Table 7 - Normal mode shift control

SFTA1:0 (BFP and Normal Modes)

In BFP mode, these signals act as the A-word shift control.

They allow shifting from one to four places to the right, (see

Table 8). Depending on the relative weightings of the A-words

and the complex product, theA-word may have to be shifted to

the right to ensure compatible weightings at the inputs to the

PDSP16318 complex accumulator. The two words must have

the same weighting if they are to be added.

In normal mode, SFTA0 performs a different function. If

WTB1:0 is set to implement a left shift, then overflow will occur

if the data is fully 32 bits wide. This pin is used to flag such an

overflow. SFTA1 is not used in normal mode.

Table 5 - Accumulator shifts (BFP mode)

GWR4:0 (BFP Mode Only)

Contents of the global weighting register. The GWR stores

the weighting of the largest word present with respect to the

weighting of the original input words. Hence, if the contents of

the GWR are 00010, it indicates that the largest word currently

being processed has its binary point two bits to the right of the

original data at the start of the BFP calculations.

Function

SFTA1:0

Shift A-word 1 place to the right

Shift A-word 2 places to the right

Shift A-word 3 places to the right

Shift A-word 4 places to the right

The contents of this register are updated at the end of each

pass, according to the largest value of WTOUT occuring during

that pass. For example, if WTOUT = 11, then GWR will be

increased by 2 (see Table 6). The GWR is presented in two’s

complement format. In normal mode, GWR4:0 are not used and

should be left unconnected.

Table 8 - External A-word shift control

PDSP16116

OSEL1 :0

The outputs from the device are selected by the OSEL0

The operation of the PDSP16116-based BFP buttertly proces-

sor (see Fig.4) is described below.

and OSEL1 instruction bits. These controls allow selection

of the output combination during the current cycle (they are

not registered). There are four possible output configurations

that allow either complex outputs of the most or least signifi-

cant bytes, or real or imaginary outputs of the full 32-bit word

(see Table 4). OSEL0 and OSEL1 should both be tied low

when in BFP mode.

The Block Floating Point System

A block floating point system is essentially an ordinary inte-

ger arithmetic system with some additional logic, the purpose of

which is to lend the system some of the enormous dynamic

range afforded by a true floating point system without suffering

the corresponding loss in perlormance.

The initial data used by the FFT should all have the same

binary arithmetic weighting. In other words, the binary point

should occupy the same position in every data word as is nor-

mal in integer arithmetic. However, during the course of the FFT,

a variety of weightings are used in the data words to increase

the dynamic range available. This situation is similar to that within

a true floating point system, though the range of numbers rep-

resentable is more limited. In the BFP system used in the

PDSP16116, there are, within any one pass of the FFT, four

possible positions of the binary point wihin the integer words. To

record the position of its binary point, each word has a 2-bit

word tag associated with it. By way of example, in a particular

pass the following four positions of binary point may be avail-

able, each denoted by a certain value of word:

BFP MODE FFT APPLICATION

The PDSP16116 may be used as the main arithmetic unit of

the butterfly processor, which will allow the following FFTbench-

marks:

1024-point complex radix 2 transform in 517µs

512-point complex radix 2 transform in 235µs

256-point complex radix 2 transform in 106µs

In addition, with pin MBFP tied high, the BFP circuitry within

the PDSP16116 can be used to adaptively rescale data through-

out the course of the FFT so as to give high-resolution results.

The BFP system on the PDSP16116 can be used with any vari-

ation of the radix 2 decimation-in-time (DIT) FFT, for example,

the constant geometry algorithm, the in-place algorithm etc. An

N-point Radix 2 DIT FFT is split into log(N) passes. Each pass

consists of N/2 ‘butterflies’, each performing the operation:

XX·XXXXXXXXXXXX word tag = 00

XXX·XXXXXXXXXXX word tag = 01

XXXX·XXXXXXXXXX word tag = 10

XXXXX·XXXXXXXXX word tag = 11

A′ = A1BW

B′ = A2BW

At the end of each constituent pass of the FFT, the positions

of the binary point supported may change to reflect the trend of

data increase or decreases in magnitude. Hence, in the pass

following that of the above example, the four positions of binary

point supported may be changed to:

Where W is the complex coefficient and A and B are the

complex data. Fig.4 illustrates how a single PDSP16116 may

be combined with two PDSP1601s and two PDSP16318s to

form a complete BFPbutterfly processor. The PDSP16318s are

used to perform the complex addition and subtraction of the

butterfly operation, while the PDSP1601s are used to match

the data path of the A-word to the pipelining and shifting opera-

tions within the PDSP16116.

XX·XXXXXXXXXXXX word tag = 00

XXX·XXXXXXXXXXX word tag = 01

XXXX·XXXXXXXXXX word tag = 10

XXXXX·XXXXXXXXX word tag = 11

For more information on the theory and construction of this

butterfly processor, refer to application note AN59.

This variation in the range of binary points supported from

pass to pass (i.e. the movement of the binary point relative to its

position in the original data) is recorded in the GWR. Thus, the

position of the binary point can be determined relative to its ini-

tial position by modifying the value of GWR by WTOUT for a

given word as shown in Table 6.As an example, if GWR=01001

and WTOUT=10 then the binary point has moved 10 places to

the right of its original position.

BFP MODE OPERATION

The BFP mode on the PDSP16116 is intended for use in the

FFT application described above, that is, it is intended to pre-

vent data degradation during the course of an FFT calculation.

SOBFP EOPSS

BR BI WR WI

WTA

WTB

AR15:13

AI15:13

XR XI YR YI

PDSP16116/A

PDSP1601/A

OER

OEI

SFTA

DAR

DAI

SFTR

PDSP16318/A

A′R

A′I

WTOUT GWR

B′R

B′I

Figure 4 FFT butterfly processor

PDSP16116

The butterfly operation

The butterfly operation is the arithmetic operation which is

repeated many times to produce an FFT. The PDSP16116- based

butterfly processor performs this operation in a low power high

accuracy chip set.

A new butterfly operation is commenced each cycle, requir-

ing a new set ot data for B, W, WTA and WTB. Five cycles later,

the corresponding results A′ and B′ are produced along with

their associated WTOUT. In between, the signals SFTA and

SFTR are produced and acted upon by the shifters in the

PDSP1601/A and PDSP16318/A. The timing of the data and

control signals is shown in Fig.6.

A′

The results (A′ and B′) of each butterfly calculation in a pass

must be stored to be used later as the input data (A and B) in

the next pass. Each result must be stored together with its as-

sociated word tag, WTOUT. Although WTOUT is common to

both A′ and B′, it must be stored separately with each word as

the words are used on different cycles during the next pass. At

the inputs, the word tag associated with the Aword is known as

WTA and the word tag associated with the B word is known as

WTB. Hence, the WTOUTs from one pass will become the WTAs

and WTBs for the following pass. It should be noted that the first

pass is unique in that word tags need not be input into the but-

terfly as all data initially has the same weighting. Hence, during

the first pass alone, the inputs WTA and WTB are ignored.

A′ = A1BW

B′ = A2BW

B′

Figure 5 - Butterfly operation

CLK

BR, BI, WR, WI

WTA, WTB

AR, AI

SFTA

SFTR

PR, PI

DAR, DAI

WTOUT

A′R, A′I, B′R, B′I

Figure 6 - Butterfly data and control signals

Control of the FFT

be kept low as long as necessary; the next pass cannot com-

mence until it is brought high again. On the initial cycle of each

new pass, the signal EOPSS should be pulled high and it should

remain high until the final cycle of that pass, when it is pulled

low again.

To enable the block floating point hardware to keep track of

the data, the following signals are provided:

SOBFP

EOPSS

- start of the FFT

- end of current pass

FFT Output Normalisation

These inform the PDSPl 6116/Awhen an FFTis starting and

when each pass is complete. Fig.7 shows how these signals

should be used and a commentary is provided below.

When an FFT system outputs a series of FFT results for

display, storage or transmission, it is essential that all results

are compatible, i.e. with the binary point in the same position.

However, in order to preserve the dynamic range of the data in

the FFT calculation, the PDSP1601/A employs a range of dif-

ferent weightings. Therefore, data must be re-formatted at the

end of the FFT to the pre-determined common weighting. This

can be done by comparing the exponent of given data word

with the pre-determined universal exponent and then shifting

the data word by the difference. The PDSP1601/A, with its

multifunction 16-bit barrel shifter, is ideally suited to this task.

According to theory, the largest possible data result from an

FFT is N times the largest input data. This means that the bi-

nary point can move a maximum of log₂(N) places to the right.

Hence, if the universal exponent is chosen to be log₂(N) this

should give a sufficient range to represent all data points faithfully.

EOPSS

To begin the FFT, the signal

(where it will remain for the duration of the pass).

should be set high

SOBFP

should

be pulled low during the initial cycle when the first data words

A and B are presented to the inputs of the butterfly processor.

SOBFP

The following cycle

must be pulled high where it should

remain for the duration of the FFT. New data is presented to the

processor each successive cycle until the end of the first pass

EOPSS

of the FFT. On the last cycle of the pass, the

should be

pulled low and held low for a minimum of five cycles, the time

required to clear the pipeline of the butterfly processor so that

all the results from one pass are obtained before beginning the

following pass.

Should a longer pause be required between passes – to ar-

EOPSS

range the data for the next pass, for example – then

may

PDSP16116

CLK

SOBFP

EOPSS

A, B, W,

WTA, WTB

n21

n24

n23

n21

A′, B′, BTOUT

GWR

START OF

FIRST PASS

END OF FIRST PASS/

START OF NEXT PASS

(MINIMUM NUMBER OF

LAY CYCLES SHOWN).

PERIOD BETWEEN

OTHER INTERMEDIATE

PASSES IS SIMILAR.

NOTES

1. 1 = FIRST CYCLE OF DATA IN PASS

2. n = LAST CYCLE OF DATA IN PASS

Figure 7 - Use of the BFP control signals

In practice, data output may never approach the theoretical

maximum. Hence, it may be worthwhile to try various universal

exponents and choose the one best suited to the particular ap-

plication.

NB It is easier to simply add the word tag to the exponent for the

purpose of determing the shift required, instead of modifying it

according to Table.6. To compensate for this, the universal ex-

ponent may be increased by one.

Data is output from the butterfly processor with a two-part

exponent: the 5-bit GWR applicable to all data words from a

given FFT and a 2-bit WTOUT associated with each individual

dataword. To find the complete exponent for a given word, the

GWR for that FFT must be modified by its WTOUT as shown in

Table 6. The result is the number of places the binary point has

shifted to the right during the course of the FFT.

WTOUT

GWR

16-BIT DATA

SIGN

BIT

UNIVERSAL

EXPONENT

4-BIT ADDER

This value must be compared with the universal exponent to

determine the shift required. This is done by subtracting it from

the universal exponent. The number of places to be shifted is

equal to the difference between the two exponents. The shift

can be implemented in a PDSP1601/A (the shift value is fed

into the SV port).

4-BIT SUBTRACTOR

1111

4-BIT MUX

As FFT data consists of real and imaginary parts, either two

PDSP1601/As must be used (controlled by the same logic) or a

single PDSP1601/A could be used handling real and imaginary

data on alternate cycles (using the same instructions for both

cycles).

An example of an output normalisation circuit is shown

in Fig.8. Only 4-bit data paths are used in calculating the

shift. This means that we must be able to trap very small

values negative of GWR and force a 15-bit right shift in

such cases.

SV PORT

B PORT

PDSP1601

C PORT

ASRSV

NORMALISED OUTPUT DATA

Figure 8 - Output normalisation circuit

PDSP16116

t_CLK

CLK

t_CLKH

t_CLKL

t_CP

VALID DATA

OUTPUT P PORTS

t_CSFTA

OUTPUT SFTA1:0

t_DS

t_DH

INPUT DATA X AND Y

t_CES

t_CEH

INPUT CONTROLS CEX AND CEY

t_CONS

t_CONH

INPUT CONTROLS CONX AND CONY

INPUT CONTROL WTB1:0

t_WS

t_WH

Figure 9 - Normal mode timing

OER AND OEI

t_OPLZ

t_OPZL

t_OPZH

t_OPHZ

HIGH Z

OUTPUT P PORTS

Figure 10 - Output tristate timing

Test

Waveform measurement level

Delay from

output high

to output

0·5V

= 0V

high Z (t

)

OPHZ

Delay from

output low

to output

= V

1·5k

0·5V

DUT

30p

high Z (t

)

OPLZ

Delay from

1·5V

output high Z

to output low

Three state delay measurement load

OPZL

)

Delay from

output high Z

to output high

OPZH

0·5V

1·5V

)

V_His the voltage reached when the output is driven high

V is the voltage reached when the output is driven low

Figure 11 - Three state delay measurement

PDSP16116

ELECTRICAL CHARACTERISTICS

The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated:

V_DD= 15V±10%, GND = 0V, T_AMB(Industrial) = 240°C to 185°C, T_AMB(Military) = 255°C to 1125°C

Static Characteristics

Value

Units

Characteristic

Symbol

Conditions

Min. Typ. Max.

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input leakage current

Input capacitance

Output leakage current

Output short circuit current

V_OH

V_OL

V_IH

V_IL

I_IN

C_IN

I_OZ

I_OS

2·4

3·0

2·2

0·4

µA

I_OH= 8mA

I_OL= 28mA

CLK input only

All other inputs

GND < V_IN< V_DD

0·8

110

210

GND < V_OUT< V_DD

V_DD= 15·5V

250

150

300

Switching Characteristics

PDSP16116

PDSP16116A PDSP16116D

Characteristic

Symbol

Units Conditions Fig.

Min. Max. Min.

Min.

Max.

t_CP

t_CW

t_CG

t_CSFTA

t_CSFTR

t_CES

t_CEH

t_DS

t_DH

t_WS

t_WH

t_CONS

t_CONH

t_AS

t_AH

t_OP

t_OPHZ

t_OPLZ

t_OPZH

t_OPZL

f_CLK

t_CLK

t_CLKH

t_CLKL

I_DDC

I_DDT

MHz

30pF

P ports setup time

WTOUT1:0 setup time

GWR4:0 setup time

SFTA1:0 setup time

SFTR2:0 setup time

CEX

CEY

setup time

hold time

X or Y ports setup time

X or Y ports hold time

WTA, WTB, SOBFP or EOPSS setup time

WTA, WTB, SOBFP or EOPSS hold time

CONX or CONY setup time

CONX or CONY hold time

AR15:13 or AI15:13 setup time

AR15:13 or AI15:13 hold time

OSEL to valid P ports

OER or OEI high to PR or PI high to high Z

OER or OEI low to PR or PI low to high Z

OER or OEI low to PR or PI high Z to high

OER or OEI high to PR or PI high Z to low

CLK frequency

31·5

30pF

10, 11

100

31·7

CLK period

CLK high time

CLK low time

100

130

See Note 1

_DDcurrent (CMOS input levels)

_DDcurrent (TTL input levels)

NOTES

1. V_DD= 15·5V, outputs unloaded, clock frequency = Max.

2. The PDSP16116B is specified as the PDSP16116A except that the maximum clock frequency is guaranteed at 25MHz, with a minimum

clock period of 40ns.

PDSP16116

NOTES

ABSOLUTE MAXIMUM RATINGS (NOTE 1)

Supply voltage, V_DD

1. Exceeding these ratings may cause permanent damage.

Functional operation under these conditions is not implied.

2. Maximum dissipation should not be exceeded for more

than1 second, only one output to be tested at any one time.

3. Exposure to absolute maximum ratings for extended

periods may affect device reliablity.

20·5V to 17·0V

20·5V to V_DD10·5V

18mA

Input voltage, V_IN

Output voltage, V_OUT

Clamp diode current per pin, I_K(see note 2)

Static discharge voltage (HBM)

Storage temperature, T_S

500V

265°C to1150°C

Ambient temperature with power applied, T_AMB

Military grade

Industrial grade

Junction temperature

255°C to1125°C

240°C to185°C

120°C

Package power dissipation

Thermal resistances

1000mW

Junction-to-case, θ_JC

Junction-to-ambient, θ_JA

12°C/W

29°C/W

PACKAGE DETAILS

Dimensions are shown thus: mm (in).

PIN 1

0° - 7°

0.11/0.23

PIN 144

2.10/2.80

PIN 1 IDENT

(SEE NOTE 2)

4.07

MAX.

28.00

BSC

22.75

BSC

31.20

BSC

0.73/1.03

0.65

BSC

0·25

MIN.

0.22/0.38

NOTES

1. Controllingdimensionsaremillimetres.

2. Pin 1 identificationcanbeeitheradotoracut-out.

3. Thispackageoutlinediagramisforguidanceonly. Please

contactyourMitelSemiconductorCustomerServiceCentrefor

further information.

144-LEAD QUAD FLATPACK – GC144

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TECHNICAL DOCUMENTATION - NOT FOR RESALE

PDSP16116/MC/GC1R [ZARLINK]

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