SC220C0P [ZARLINK]
XpressFlow 2020 Ethernet Routing Switch Chipset; XpressFlow 2020年以太网路由交换机芯片组
| 型号： | SC220C0P |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | XpressFlow 2020 Ethernet Routing Switch Chipset |
| 文件： | 总34页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
P R E L I M I N A R Y
I N F O R M A T I O N
Distinctive Characteristics
SC220 – XpressFlow Engine
t Highly integrated central switch controller
XpressFlow 2020 Ethernet Routing Switch Chipset
t State of the art 0.35 micron 3.3 Volt CMOS
process
t 256-PIN PQFP package
t Operating frequency
C A M
(Optional)
à
à
à
-40
-50
-66
40 MHz maximum
50 MHz maximum
66 MHz maximum
ADDRESS
MAPPING
TABLE
SC220
16
t 16-bit external CAM interface
Supports ½k to 16k MAC addresses
t 32-bit Control Buffer Memory interface
à
XpressFlow
CONTROL
BUFFER
ENGINE
à
à
Supports 128k to 1M bytes
32
MEMORY
Utilize high performance 32-bit Syn-
chronous Burst SRAM
t Hardware assisted Buffer and Queue Man-
32
32
agement to minimize CPU overhead
XpressFlow BUS
XpressFlow BUS
t 32-bit Management Bus I/O interface
à
Allows host to access CAM and Control
Buffer Memory
à
à
Supports Big and Little Endian CPUs
Direct interface with various different
standard microprocessors including
386, 486 families and Motorola MPC se-
ries embedded processors
SC220 - XpressFlow Engine
t 32-bit XpressFlow Bus Interface
Switching bandwidth
à
General Description
- 1.28 Gbps @ 40 MHz system clock
- 1.60 Gbps @ 50 MHz system clock
- 2.10 Gbps @ 66.67 MHz system clock
The XpressFlow Engine contains the switching data base in-
terface and buffer management logic in order to do the switching
decision making for unicast, multicast, and broadcast frames.
Hardware assisted queue manager is incorporated to facilitate
buffer management. It also provides a generic Management Bus
interface to allow external processor to do initialization, learning,
VLAN, and RMON support, etc. In addition, a XpressFlow Bus
interface block is responsible for communicating with the Network
Access Controllers through the XpressFlow message passing
protocol.
à
Supports up to 8 Multi-port Network Ac-
cess Controllers
à
à
XpressFlow Bus access arbitration
XpressFlow Bus data transfer load
regulation
t Full IP Switching
à
Addresses resolved by SC220
t MAC Address Mapping Table
Related Components:
à
Supports either CAM based or SRAM
based Switching data base
t EA218E – 8-port 10Mbps Ethernet Access Controller
t EA218 – 6-port 10 + 2-port 10/100 Ethernet Access Controller
t EA234 – 4-port 10/100 Fast Ethernet
© 1998 Vertex Networks, Inc.
1
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
Characteristics Continue
SC220
XpressFlow
Engine
t Built-in address to port resolution
HISC Core
à
à
à
Embedded 32-bit HISC™ (High density
Instruction Set Core) Processor
CAM
Optimized architecture for switch appli-
cations
32
32
ADDRESS
MAPPING
TABLE
16
32
CAM
Interface
Loadable firmware for easy upgrade
16
Mngmt
Bus
Interface
t Supports unicast, multicast, and broadcast
16
32
HISC
I/O
Registers
frames
SRAM
t Address Filtering
Control
Buffer
Memory
Interface
CONTROL
BUFFER
MEMORY
32
32
32
32
à
Destination & Source MAC address
matching & filtering
32
32
32
t
VLAN classification & verification
Automatic
Buffer
Manager
à
Up to 62 groups
XpressFlow Bus
Interafce
à
à
à
Level 1 and 2 mapping
32
VLAN ID tagging & stripping
Auto padding if necessary after stripping
XpressFlow BUS
t Supports Store-&-Forward Frame Forward-
ing Mode
Block Diagram –
t Collects statistics for RMON
SC220 XpressFlow Engine
Typical Application:
à A 16-port Ethernet Switch with 4-Fast Ethernet
RS232 Local
Control Console
Address
Mapping
Table
SC220
XpressFlow
Engine
Switch
Manager
CPU
Buffer
RAM
Flash
ROM
DRAM
Management Bus
XpressFlow Bus
Buffer
RAM
Buffer
RAM
Buffer
RAM
EA208E
8-Port
EA208E
8-Port
EA234
4-Port
Ethernet
Access
Ethernet
Access
Ethernet
Access
Controller
Controller
Controller
8 Ethernet ports
8 Ethernet ports
Four 100M
Fast Ethernet ports
System Block Diagram --
16-Port Ethernet Switch with 4 Fast Ethernet Up-Links
© 1998 Vertex Networks, Inc.
2
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1. PIN ASSIGNMENT
1.1 Logic Symbol
SC220
T_MODE
C_D[15:0]
Test Pin
L_D[31:0]
L_A[18:2]
4
C_CE#
C_WE#
C_CM#
C_EC#
C_MF#
C_FF#
L_BWE[3:0]#
4
L_WE[3:0]#
4
L_OE[3:0]#
L_ADSC#
L_CLK
P_D[31:0]
P_A[11:1]
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_OVLD#
P_CS#
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_INT
S_HPREQ#
8
S_REQ[8:1]#
S_GNT[8:1]#
P_RSTIN#
P_RSTOUT
P_CLK
8
S_CLK
Note:
The SC220 is pin compatible to the SC201 with only one exception:
The RSTOUT pin of SC201 is defined as a synchronous RESET output pin which follows the RSTIN input and re-synchronous with
P_CLK for meeting the 80386 timing requirement.
The RSTOUT pin for SC220 has a totally different function. It is no longer related with the RSTIN input. The RSTOUT is a watch-
dog output from SC220 to keep track of the active state of the host processor. Host processor needs to access the Keep
Alive register periodically to prevent the setting of the RSTOUT output. The RSTOUT output can be use as Reset input to
the host processor.
© 1998 Vertex Networks, Inc.
3
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1.2 Pin Assignment (Preliminary)
Note:
#
Input
Active low signal
Input signal
I-ST
Output
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Out-OD
I/O-TS
I/O-OD
5VT
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Input with 5V Tolerance
Pin No(s).
XpressFlow Bus Interface
Symbol
Type
Name & Functions
122,121,119,118, 116 S_D[31:27] /
P_C[0:4]
CMOS I/O-TS XpressFlow Bus – Data Bit [31:28] or
Processor Interface Configuration Bit
[0:4]
114,113,111,109,108, S_D[26:0]
106,105,104,103,101,
CMOS I/O-TS XpressFlow Bus – Data Bit [27:0]
100,98,97,96,95,93,92,
90,89,88,87,85,84,82,
80,79,77
71
69
72
70
123
S_MSGEN#
S_EOF#
CMOS I/O-TS XpressFlow Bus – Message Envelope
CMOS I/O-TS XpressFlow Bus – End of Frame
CMOS I/O-TS XpressFlow Bus – Initiator Ready
CMOS I/O-OD XpressFlow Bus – Target Abort
CMOS I/O-OD XpressFlow Bus – High Priority Request
S_IRDY
S_TABT#
S_HPREQ#
140,138,135,133,131, S_REQ[8:1]# CMOS Input ** XpressFlow Bus – Bus Request [8:1]
129,126,124
141,139,137,134,132, S_GNT[8:1]# CMOS Output XpressFlow Bus – Bus Grant [8:1]
130,128,125
73
75
S_OVLD#
S_CLK
CMOS Output XpressFlow Bus – Bus Overload
CMOS Input XpressFlow Bus – Clock
© 1998 Vertex Networks, Inc.
4
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
Pin No(s).
Symbol
Type
Name & Functions
XpressFlow Bus Interface
185,184,183,182,180,
179,177,176,175,174,
172,171,169,168,167,
P_D[31:0]
TTL I/O-TS Management Bus – Data Bit [31:0]
(5VT)
166,164,163,160,159,
157,156,154,153,151,
150,149,148,146,145,
143,142
211,210,208,207,205,
204,203,202,201,199,
198
P_A[11:1]
TTL Input
(5VT)
Management Bus – Address Bit [11:1]
196
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
TTL Input
(5VT)
Management Bus – Address Strobe
191
183
184
185
189
TTL Input
(5VT)
Management Bus – Read/Write Control
CMOS Out- Management Bus – Data Ready
OD
CMOS Out- Management Bus – 16 bit Data Bus
OD
TTL Input
(5VT)
Management Bus – Chip Select
P_RSTIN#
TTL In-ST
(5VT)
System RESET Input
190
192
187
P_RSTOUT
P_INT
CMOS Output CPU RESET Output
CMOS Output Management Bus – Interrupt Request
P_CLK
TTL Input
(5VT)
CPU Clock
Control Buffer Memory Interface
60,59,58,57,56,54,53,51, L_D[31:0]
50,49,48,47,46,45,43,42,
40,39,38,37,36,34,33,30,
TTL I/O-TS Local Memory Bus – Data Bit [31:0]
CMOS Output Local Memory Bus – Address Bit [17:2]
29,27,26,25,24,23,22,21,
8,6,5,3,2,1,256,255,254, L_A[18:2]
253,251,250,248,247,
246,245,244
9
L_A[19] /
L_OE[3]#
CMOS Output Local Memory Bus – Address Bit [19:18]
or Memory Read Chip Select [3]
63, 11, 19
242, 62, 10, 18
12,13,14,15
16
L_OE[2:0]#
CMOS Output Local Memory Bus- Read Chip Select
[2:0]
L_WE[3:0]#, CMOS Output Local Memory Bus – Write Chip Select
[3:0]
L_BWE[3:0]# CMOS Output Local Memory Bus – Byte Write Enable
[3:0]
L_ADSC#
CMOS Output Local Memory Bus – Controller Address
Status
66
L_CLK
CMOS Output Local Memory Bus – Synchronous Clock
© 1998 Vertex Networks, Inc.
5
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
Pin No(s).
Symbol
Type
Name & Functions
CAM Interface
214,215,217,218,219, C_D[15:0]
220,221,222,223,225,
TTL I/O-TS CAM Interface – Data Bus bit [15:0]
(5VT)
226,228,229,220.221,
239
241
233
234
236
C_WE#
C_CE#
C_EC#
C_CM#
C_FF#
CMOS Output CAM Interface – Write Enable
CMOS Output CAM Interface – Chip Enable
CMOS Output CAM Interface – Enable Comparison
CMOS Output CAM Interface – Data/Command Select
TTL Input
(5VT)
CAM Interface – Full Flag
237
C_MF#
TTL Input
(5VT)
CAM Interface – Match Flag
Test & Reserved Pins
65
TEST
n/c
CMOS I/O-TS Test Pin – Set Test Mode upon Reset,
and provides test status output during
test mode
62,63,64,67,242
---
Reserved Pins (5 pins)
Power Pins
32,78,115,161,206,243 VDD (Core)
Input
Input
+3.3 Volt DC Supply for Core Logic (6
pins)
7,20,31,44,55,68,76,86, VDD
94,102,110,120,144,
+3.3 Volt DC Supply for I/O Pads (23
pins)
152,162,170,178,186,
197,216,227,238,252
35,81,112,158,209,240 VSS (Core)
Input
Input
Ground for Core Logic (6 pins)
Ground for I/O Pads (26 pins)
4,17,28,41,52,61,66,74, VSS
83,91,99,197,117,127,
136,147,155,165,173,
181,188,200,213,224,
235,249
© 1998 Vertex Networks, Inc.
6
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1.1
1.2
1.3 Connection Diagram – 256-PQFP Package (Top View)
256
193
1
L_A[13]
192
P_INT
L_A[14]
L_A[15]
VSS
L_A[16]
L_A[17]
VDD
P_RWC
P_RSTOUT
P_RSTIN#
VSS
P_CLK
VDD
CAM Interface
Pin 1 I.D.
L_A[18]
L_A[19] / L_OE[3]#
L_WE[1]#
L_OE[1]#
L_BWE[3]#
L_BWE[2]#
L_BWE[1]#
L_BWE[0]#
L_ADSC#
VSS
P_D[31]
P_D[30]
P_D[29]
P_D[28]
VSS
P_D[27]
P_D[26]
VDD
P_D[24]
P_D[25]
P_D[23]
P_D[22]
VSS
L_WE[0]#
L_OE[0]#
VDD
L_D[0]
L_D[1]
L_D[2]
P_D[21]
P_D[20]
VDD
L_D[3]
L_D[4]
L_D[5]
L_D[6]
P_D[19]
P_D[18]
P_D[17]
P_D[16]
VSS
VSS
L_D[7]
L_D[8]
VDD
P_D[15]
P_D[14]
VDD
VDD (Core)
VDD (Core)
P_D[13]
P_D[12]
VSS (Core)
P_D[11]
P_D[10]
VSS
P_D[9]
P_D[8]
VDD
L_D[9]
L_D[10]
VSS (Core)
L_D[11]
L_D[12]
L_D[13]
L_D[14]
L_D[15]
VSS
L_D[16]
L_D[17]
VDD
P_D[7]
P_D[6]
P_D[5]
L_D[18]
L_D[19]
L_D[20]
L_D[21]
L_D[22]
L_D[23]
L_D[24]
VSS
L_D[25]
L_D[26]
VDD
L_D[27]
L_D[28]
L_D[29]
L_D[30]
L_D[31]
VSS
P_D[4]
VSS
P_D[3]
P_D[2]
VDD
P_D[1]
P_D[0]
S_GNT[8]#
S_REQ[8]#
S_GNT[7]#
S_REQ[7]#
S_GNT[6]#
VSS
S_REQ[6]#
S_GNT[5]#
S_REQ[5]#
S_GNT[4]#
S_REQ[4]#
S_GNT[3]#
S_REQ[3]#
L_WE[2]#
L_OE[2]#
Test
XpressFlow Bus Interface
64
129
128
65
© 1998 Vertex Networks, Inc.
7
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1.4 Connection Diagram – 256-BGA Package (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P_
20
P_
L_A
[13]
L_A
[12]
L_A
[10]
L_A[5] / L_A[2] /
P_C[3] P_C[0]
C_ C_ EC# C_D
MF#
C_D
[3]
C_D
[6]
C_D
[10]
C_D
[13]
P_A
[11]
P_A
[8]
P_A
[6]
P_A
A
B
C
D
E
F
[2]
[3] BS16# RDY#
L_A
[14]
L_A
[11]
L_A
[8]
L_A L_A[3] / C_ CE#
[6] P_C[1]
C_
CM#
C_D
[1]
C_D
[4]
C_D
[7]
C_D
[11]
C_D
[14]
P_A
[10]
P_A
[7]
P_A
[4]
P_
ADS#
P_A
[2]
P_
INT
L_A
[18]
L_A
[16]
L_A
[15]
L_A
[9]
L_A L_A[4] / L_WE C_
[7] P_C[2] [3] WE#
C_
FF#
C_D
[0]
C_D
[5]
C_D
[9]
C_D
[12]
C_D
[15]
P_A
[9]
P_A
[5]
P_A P_ CS# P_ P_RST
[1]
RWC OUT
L_OE L_OE L_A
[1]# [3]#
VDD
C_D
[8]
VDD
(Core)
P_RST
IN#
P_
CLK
VSS VDD VSS VDD VSS VSS
VDD VSS VDD
VSS VDD
VSS
[17] (Core)
L_BWE L_BWE L_WE
[2]# [3]# [1]#
P_D
[31]
P_D
[30]
VSS
VDD
VSS
L_ L_BWE L_BWE
ADSC# [0]#
P_D
[29]
P_D
[28]
P_D
[27]
VDD
[1]#
L_D L_OE
[0]
VDD P_D
(Core) [26]
P_D
[25]
P_D
[24]
G
H
J
[0]#
L_D
[3]
L_D
[2]
L_D L_WE
[1]
P_D
[23]
P_D
[22]
P_D
[21]
VSS
[0]#
L_D
[7]
L_D
[6]
L_D
[4]
L_D
[5]
P_D
[20]
P_D
[19]
P_D
[18]
VDD
L_D
[9]
L_D
[8]
P_D
[17]
P_D
[16]
P_D
[15]
VDD
VSS
K
L
L_D
[10]
L_D
[11]
L_D
[12]
P_D
[12]
P_D
[13]
P_D
[14]
VSS
VDD
L_D
[13]
L_D
[14]
L_D
[15] (Core)
P_D
[9]
P_D
[10]
P_D
[11]
VSS
M
N
P
R
T
L_D
[16]
L_D
[17]
L_D
[18]
P_D
[3]
P_D
[6]
P_D
[7]
P_D
[8]
VSS
L_D
[19]
L_D
[20]
L_D
[21]
VDD P_D
P_D
[4]
P_D
[5]
VDD
(Core)
[2]
L_D
[22]
L_D
[23]
L_D
[24]
L_D
[26]
P_D
[0]
P_D
[1]
VDD
L_D
[25]
L_D
[27]
L_D
[28]
S_REQ S_REQ S_GNT
VSS
VSS
[7]#
[8]#
[8]#
L_D
[29]
L_D
[30]
L_D
[31]
S_D
[4]
VDD
(Core)
S_D
[25]
S_D S_REQ S_GNT S_GNT S_GNT S_GNT
VDD VSS
VSS VDD
VSS VDD VSS
U
V
W
Y
[29]
[1]#
[4]#
[5]#
[6]#
[7]#
L_WE
[2]#
L_
S_
S_D
[0]
S_D
[3]
S_D
[7]
S_D
[10]
S_D
[13]
S_D
[20]
S_D
[23]
S_D
[26]
S_D
[30]
S_REQ S_REQ
VDD
VDD
VDD
CLK TABT#
[4]#
[5]#
L_OE S_MSG S_
[2]#
S_
S_D
[1]
S_D
[5]
S_D
[8]
S_D
[11]
S_D
[14]
S_D
[17]
S_D
[19]
S_D
[22]
S_D
[27]
S_HP S_GNT S_REQ S_GNT
REQ# [1]# [6]# [3]#
VSS
EN# EOF# OVLD#
T_
MODE
S_ S_
IRDY CLK
S_D
[2]
S_D
[6]
S_D
[9]
S_D
[12]
S_D
[15]
S_D
[16]
S_D
[18]
S_D
[21]
S_D
[24]
S_D
[28]
S_D S_REQ S_GNT S_REQ
[31] [2]# [2]# [3]#
© 1998 Vertex Networks, Inc.
8
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1.5 Pin Reference Table: (256 Pin PQFP& 256-BGA)
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
P_RDY#
1
L_A[13]
65
66
TEST
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
S_REQ[3]#
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
2
L_A[14]
L_A[15]
VSS
VSS
S_GNT[3]#
S_REQ[4]#
S_GNT[4]#
S_REQ[5]#
S_GNT[5]#
S_REQ[6]#
VSS
P_BS16#
P_CS#
P_ADS#
VDD
3
67
L_CLK
4
68
VDD
5
L_A[16]
L_A[17]
VDD
69
S_EOF#
S_TABT#
S_MSGEN#
S_IRDY
S_OVLD#
VSS
6
70
P_A[1]
7
71
P_A[2]
8
L_A[18]
L_A[19] / L_OE[3]#
L_WE[1]#
L_OE[1]#
L_BWE[3]#
L_BWE[2]#
L_BWE[1]#
L_BWE[0]#
L_ADSC#
VSS
72
VSS
9
73
S_GNT[6]#
S_REQ[7]#
S_GNT[7]#
S_REQ[8]#
S_GNT[8]#
P_D[0]
P_A[3]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
74
P_A[4]
75
S_CLK
VDD
P_A[5]
76
P_A[6]
77
S_D[0]
P_A[7]
78
VDD (Core)
S_D[1]
VDD (Core)
P_A[8]
79
P_D[1]
80
S_D[2]
VDD
P_A[9]
81
VSS (Core)
S_D[3]
P_D[2]
VSS (Core)
P_A[10]
P_A[11]
L_WE[0]#
L_OE[0]#
VDD
82
P_D[3]
83
VSS
VSS
84
S_D[4]
P_D[4]
L_D[0]
85
S_D[5]
P_D[5]
VSS
L_D[1]
86
VDD
P_D[6]
C_D[15]
C_D[14]
VDD
L_D[2]
87
S_D[6]
P_D[7]
L_D[3]
88
S_D[7]
VDD
L_D[4]
89
S_D[8]
P_D[8]
C_D[13]
C_D[12]
C_D[11]
C_D[10]
C_D[9]
L_D[5]
90
S_D[9]
P_D[9]
L_D[6]
91
VSS
VSS
VSS
92
S_D[10]
S_D[11]
VDD
P _D[10]
P_D[11]
VSS (Core)
P_D[12]
P_D[13]
VDD (Core)
VDD
L_D[7]
93
L_D[8]
94
C_D[8]
VDD
95
S_D[12]
S_D[13]
S_D[14]
S_D[15]
VSS
C_D[7]
VDD (Core)
L_D[9]
96
VSS
97
C_D[6]
L_D[10]
VSS (Core)
L_D[11]
L_D[12]
L_D[13]
L_D[14]
L_D[15]
VSS
98
C_D[5]
99
P_D[14]
P_D[15]
VSS
VDD
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
S_D[16]
S_D[17]
VDD
C_D[4]
C_D[3]
P_D[16]
P_D[17]
P_D[18]
P_D[19]
VDD
C_D[2]
S_D[18]
S_D[19]
S_D[20]
S_D[21]
VSS
C_D[1]
C_D[0]
C_EC#
C_CM#
VSS
L_D[16]
L_D[17]
VDD
P_D[20]
P_D[21]
VSS
S_D[22]
S_D[23]
VDD
C_FF#
L_D[18]
L_D[19]
L_D[20]
L_D[21]
L_D[22]
L_D[23]
L_D[24]
VSS
C_MF#
VDD
P_D[22]
P_D[23]
P_D[24]
P_D[25]
VDD
S_D[24]
VSS (Core)
S_D[25]
S_D[26]
VDD (Core)
S_D[27]
VSS
C_WE#
VSS (Core)
C_CE#
L_WE[3]
VDD (Core)
L_A[2] / P_C[0]
L_A[3] / P_C[1]
L_A[4] / P_C[2]
L_A[5] / P_C[3]
L_A[6]
P_D[26]
P_D[27]
VSS
L_D[25]
L_D[26]
VDD
S_D[28]
S_D[29]
VDD
P_D[28]
P_D[29]
P_D[30]
P_D[31]
VDD
L_D[27]
L_D[28]
L_D[29]
L_D[30]
L_D[31]
VSS
S_D[30]
S_D[31]
S_HPREQ#
S_REQ[1]#
S_GNT[1]#
S_REQ[2]#
VSS
VSS
L_A[7]
P_CLK
L_A[8]
VSS
VDD
P_RSTIN#
P_RSTOUT
P_RWC
P_INT
L_A[9]
L_WE[2]#
L_OE[2]#
L_A[10]
L_A[11]
L_A[12]
S_GNT[2]#
© 1998 Vertex Networks, Inc.
9
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
Note:
•
‚
ƒ
For 256-BGA package: F4, K4, P4, U5, U9, U12, V11, V15, V17, R17, J17, F17, D17, D14, D12, D8 and D6 are VDD.
For 256-BGA package: D4, M4, U10, P17, G17 and D15 are VDD(Core).
For 256-BGA package: E4, G4, L4, N4, T4, U6, U8, U11, U13, W14, T17, M17, K17, H17, E17, D16, D13, D10, D9, D7, and
D5 are VSS.
© 1998 Vertex Networks, Inc.
10
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2
FUNCTIONAL DESCRIPTION
2.1 CAM Interface
Command
From HISC
Block
t Direct interface with MUSIC MU9C1480 1k x
64 bit Content Addressable Memory (CAM)
Response
To HISC
Data Block
à Expandable to support 8k MAC Addresses
CAM
Interface
Logic
CAM
t Two access masters: HISC in XpressFlow
Command
From CPU
Block
Engine, and Switch Manager CPU
t Master interface with CAM Interface logic via
Response
To CPU
two dedicated CAM Command Blocks
Data Block
à One for HISC
à One for Switch Manager CPU
Block Diagram – CAM Interface
t Both HISC and Switch Manager CPU can ac-
cess the CAM by setting up their corresponding CAM Command Blocks, and read the return informa-
tion from their own Response Data Block
2.1.1 Pin Description
Symbol
Type Name & Functions
C_D[15:0]
TTL CAM Data Bus bit [15:0] – a 16-bit data bus for Data/Command in-
I/O-TS
put/output.
C_CE#
CAM Chip Enable – Enables the CAM by registers the control signals
on its falling edge and release them on its rising edge. Also used for
locking and unlocking the cascaded daisy chain.
CMOS
Output
C_WE#
C_CM#
C_EC#
CAM Write Enable – allows to write data or command to CAM
CMOS
Output
CAM Data/Command Select – defines data or command operations
CMOS
Output
CAM Enable Comparison – latches and enables the MF and FF outputs
during a comparison cycle.
CMOS
Output
C_MF#
C_FF#
TTL CAM Match Flag – indicates a valid match during a comparison cycle.
Input
TTL CAM Full Flag – indicates there is no empty location in the CAM.
Input
© 1998 Vertex Networks, Inc.
11
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.1.2 Bus Cycle Waveforms
S_CLK
C_CE#
C_CM#
C_EC#
C_WE#
C_MF#
C_D[15:0]
Write
MAC Address MAC Address
Byte 0, & 1 Byte 2, & 3
Write
Write
MAC Address
Byte 4, & 5
Read
MAC Control
Buffer Pointer
Typical MAC Address Compare Operation
Note: Refer to MUSIC MU9C1480 CAM data sheet for detailed timing parameters.
© 1998 Vertex Networks, Inc.
1999
12
Rev. 4.5 – February
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.2 Local Memory (Control Buffer Memory) Interface
t Uses industry standard Synchronous Burst SRAM (Pipe-lined Mode)
à Supports 64k x 32, 128k x 32, or 256k x 32 chips up to maximum 2M bytes
t Provides 4 individual Byte Write Enable controls
t Supports back to back Read or Write operations
2.2.1 Pin Description
Symbol
Type Name & Functions
L_D[31:0]
TTL Local Memory Data Bus Bit [31:0] – a 32-bit synchronous data bus.
I/O-TS
L_A[18:2]
CMOS Local Memory Address Bus Bit [18:2] – Bit [17:2] of a synchronous ad-
Output
dress bus. The memory address is sampled when L_CS# is enabled
and L_ADSC# is asserted.
L_A[19] /
CMOS Local Memory Address Bus Bit [19] or Local Memory Write Chip Select
L_WE[3]#
Output
[3] – Depends on memory configuration, this pin can be used as the
Local Memory Address Bit [19] or as the Local Memory Write Chip
Select [3].
L_WE[2:0]#
L_OE[3:0]#
CMOS Local Memory Write Chip Select [2:0] – allows up to write one of the 4
Output
banks of memory.
CMOS Local Memory Read Chip Select [3:0] – allows up to read one of the 4
Output
banks of memory.
L_BWE[3:0]# CMOS Local Memory Byte Write Enable [3:0] – use to write individual bytes.
Output
L_ADSC#
L_CLK
CMOS Local Memory Controller Address Status – to load a new address.
Output
CMOS Local Memory Clock – a synchronous clock to memory devices.
Output
© 1998 Vertex Networks, Inc.
13
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
Supported Memory Configurations
Read/Write Chip Select and High Address Bits
Chip #3 Chip #2 Chip #1 Chip #0
# of Total Buffer L_A[19] /
RAM
L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
Chip Size RAM
Chips
Memory L_WE[3]#
Size
64k x 32
128k x 32
256k x32
1
2
4
1
2
4
1
2
256k bytes
512k bytes
----
----
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
1M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
256k bytes
1M bytes
----
----
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
2M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
1M bytes L_A[19]
2M bytes L_A[19]
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
2.2.2 Bus Cycle Waveforms
L_CLK
L_ADSC#
L_CS#
L_A[19:2]
A1
A2
A3
A3+1
A3+2
A3+3
A4
A4+1
A4+2
A4+3
A5
A6
L_WE[3:0]#
L_BWE[3:0]#
L_OE[3:0]#
L_D[31:0] (Wr)
L_D[31:0] (Rd)
D1
D3 D3+1
D3+2
D3+3
D6
D2
D4
D4+1
D4+2
D4+3
D5
Typical Local Memory Access Operations
Note: Refer to manufacturer’s data sheet for detailed timing parameters.
© 1998 Vertex Networks, Inc.
1999
14
Rev. 4.5 – February
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.3 Management Bus Interface
t Supports various industry standard micro-
t Provides separate Address and Data bus
t Supports Big & Little Endian byte ordering
t Supports 16- or 32-bit Data Bus
processors including:
à Intel 186/486 family or equivalent
à Motorola MPC series embedded processors
t Easily adapts to other industry standard CPUs
t Provides a single interrupt signal to Switch
Manager CPU
2.3.1 Pin Description
Symbol
P_C[4:0]
Type
Name & Functions
CMOS Input Processor Configuration bit [4:0]: – During the Reset Cycle, the P_C[4:0] pins provides the proc-
essor configuration. By using external weak pull-up or -down resistors, they define the External
Management Bus Interface Configuration. These inputs are sampled at the trailing edge of the
Reset cycle.
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Data Bus width – 16-bit or 32-bit
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
C[0]
C[1]
C[2]
C[3]
C[4]
CPU Clock
Byte Order
RWC
Bus Width
RDY Timing
Lo
Hi
1X Clock
2x Clock
Little Endian
Big Endian
P_R/W#
P_W/R#
16-bit
32-bit
Normal
Early
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
Address Bus Bit [11:1] – I/O port address
P_A[11:1]
P_D[15:0]
P_ADS#
P_RWC
TTL In
(5VT)
TTL I/O-TS Data Bus Bit [15:0] – a 16-bit synchronous data bus.
(5VT)
TTL In
(5VT)
Address Strobe – indicates valid address is on the bus
TTL
put (5VT)
In- Read/Write Control – indicates the current bus cycle is a read or write cycle. C[1] defines the
polarity of this signal during the Reset cycle.
C[1]=Low
C[1]=High
P_R/W# is used for PowerPC or other similar processors.
P_W/R# is used for 386, 486 or other similar processors
P_RDY#
TTL Out- Data Ready – timing indicates for bus data valid
OD
P_BS16#
P_CS#
TTL Out-OD Bus Size 16 – response to bus master that the SC-201 only supports 16-bit data bus width.
TTL In
(5VT)
Chip Select – indicates the XpressFlow Engine is the target for the current bus operation.
TTL Out- Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable via
P_INT
•
put
chip configuration register.
P_RSTIN#
TTL In-ST Power Up Reset Input – Asynchronous Reset Input from either Power-Up Reset circuit or from
(5VT)
Switch Manager CPU (except 386)
P_RSTOUT
P_CLK
CMOS
Output
Synchronous Reset Output – Synchronous Reset Output for i386 family as the Switch Manager
CPU
TTL In
(5VT)
CPU Clock – 1X Clock for the others
Note:
•
Output signal with programmable polarity.
15
© 1998 Vertex Networks, Inc.
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.3.2 Motorola MPC801 Processor Interface
P_CLK
{CLKOUT}
P_ADS#
{TS#}
P_A[11:1]
{A[20:30]}
P_CS#
P_RWC
{RD/WR#}
P_RDY#
{TA#}
P_D[31:0]
{D[0:31]}
(in)
P_D[31:0]
{D[0:31]}
(out)
Note: Mnemonics within {} are the equivalent signals defined by MPC801
Typical Motorola MPC801 CPU I/O Access Operations
2.3.3 Intel 486 Processor Interface
P_CLK
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[31:0] (in)
P_D[31:0] (out)
Typical 486 CPU I/O Access Operations
© 1998 Vertex Networks, Inc.
16
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.3.4 Intel 386 Processor Interface
P_CLK
PH2 (internal)
PH2
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D15:0] (out)
Typical 386 CPU I/O Access Operations
P_CLK
PH2 (internal)
P_RSTIN#
PH2
PH1
PH2
PH2 or PH1
P_RSTOUT#
Internal PH2 Clock Synchronization
Note: See Intel 386 Processor Data Book for more details
© 1998 Vertex Networks, Inc.
1999
17
Rev. 4.5 – February
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.3.5 Register Map
Note: All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
This is a Global Register. CPU is allowed to write the Global Register of all devices by a
single operation.
These registers are reserved for system diagnostic usage only.
I/O Offset
Register Description
Little
Big
Reg. W/R Note:
Endian Endian Size
Device Configuration Registers (DCR)
GCR
Global Control Register
Device Status Register
Signature & Revision Register
ID Register
hF00 hF02 16-bit W/--
hF00 hF02 16-bit --/R
hF10 hF12 16-bit --/R
hF20 hF22 16-bit W/R
hF30 hF32 16-bit W/R
hF40 hF42 16-bit --/R
hF50 hF52 16-bit W/R
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
Local Control Register
Interface Status Register
Bus Credit Register
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
hF80 hF82 16-bit --/R
hF90 hF92 16-bit --/R
hFA0 hFA2 16-bit W/R
hFB0 hFB2 16-bit W/--
ISRM
IMSK
IAR
Interrupt Status Register – Masked
Interrupt Mask Register
Interrupt Acknowledgment Register
Buffer Memory Interface
MWAR Memory Write Address Register – Single Cycle hE08 hE08 32-bit W/R
MRAR Memory Read Address Register – Single Cycle hE18 hE18 32-bit W/R
MBAR Memory Address Register – Burst Mode
MWBS Memory Write Burst Size (in D-words)
MRBS Memory Read Burst Size (in D-words)
MWDR Memory Write Data Register
hE28 hE28 32-bit W/R
hE40 hE42 16-bit W/R
hE50 hE52 16-bit W/R
hE68 hE68 32-bit W/--
hE6C hE6C 32-bit W/--
hE68 hE68 32-bit --/R
hE6C hE6C 32-bit --/R
MWDX Memory Write Data Register – Byte Swapping
MRDR Memory Read Data Register
MRDX Memory Read Data Register – Byte Swapping
Buffers & Stacks Management
Frame Control Buffers
FCBBA Frame Control Buffer – Base Address
hD00 hD02 16-bit W/R
hD20 hD22 16-bit --/R
hD20 hD22 16-bit W/--
hD30 hD32 16-bit --/R
hD80 hD82 16-bit W/R
hD90 hD92 16-bit W/R
FCBA
FCBR
Frame Control Buffer – Buffer Allocation
Frame Control Buffer – Buffer Release
FCBAG Frame Control Buffer – Buffer Aging Status
FCBSA Frame Ctrl Buffer Stack – Base Address
FCBSL Frame Ctrl Buffer Stack – Size Limit
FCBST Frame Ctrl Buffer Stack – Buffer Low Threshold hDA0 hDA2 16-bit W/R
FCBSS Frame Ctrl Buffer Stack – Allocation Status hDB0 hDB2 16-bit --/R
© 1998 Vertex Networks, Inc.
1999
18
Rev. 4.5 – February
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
I/O Offset
Little Big
Register Description
Reg. W/R Note:
Endian Endian Size
Buffers & Stacks Management (Continue)
Switch Control Buffers
SCBBA Switch Control Buffer – Base Address
SCBA Switch Control Buffer – Buffer Allocation
hC00 hC02 16-bit W/R
hC20 hC22 16-bit --/R
hC30 hC32 16-bit --/R
hC80 hC82 16-bit W/R
hC90 hC92 16-bit W/R
SCBAG Switch Control Buffer – Buffer Aging Status
SCBSA Switch Ctrl Buffer Stack – Base Address
SCBSL Switch Ctrl Buffer Stack – Size Limit
SCBST Switch Ctrl Buffer Stack – Buffer Low Threshold hCA0 hCA2 16-bit W/R
SCBSS Switch Ctrl Buffer Stack – Allocation Status
hCB0 hCB2 16-bit --/R
MAC Control Tables
MCTA
MAC Control Table – Table Allocation
hB20 hB22 16-bit --/R
MCTR MAC Control Table – Table Release
MCTSA MAC Ctrl Table Stack – Base Address
MCTSS MAC Ctrl Table Stack – Allocation Status
hB20 hB22 16-bit
W/-
hB80 hB82 16-bit W/R
hBB0 hBB2 16-bit --/R
Queue Management
QSBA
MFTA
CINQ
Queue Structure – Base Address
Multicast Frame Table – Base Address
CPU Input Queue
hA00 hA02 16-bit W/R
hA10 hA12 16-bit W/R
hA88 hA88 32-bit W/--
hA88 hA88 32-bit --/R
hA98 hA98 32-bit --/R
hAA8 hAA8 32-bit --/R
hAB8 hAB8 32-bit --/R
COTQ CPU Output Queue
CSQ0
CSQ1
CSQ2
CPU Status Queue – 1st D-word
CPU Status Queue – 2nd D-word
CPU Status Queue – 3rd D-word
CAM Interface
CCWR CAM Command/Data Write Register
h908 h908 32-bit W/--
h928 h928 32-bit --/R
h938 h938 32-bit --/R
CSRL
CSRH
CAM Status/Data Read Register Low
CAM Status/Data Read Register High
HISC Control
HPCR
HMCL
HPRC
HISC Processor Control Register
h980 h982 16-bit W/R
h998 h998 32-bit W/R
h9B0 h9B2 16-bit W/R
HISC Micro-Code Loading Port
HISC Priority Control Register
© 1998 Vertex Networks, Inc.
19
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.4 XpressFlow Bus Interface
à Data Messages for forwarding an Ethernet
frame from receiving port to transmission
port
t Vertex Networks’ optimized XpressFlow Bus
architecture
t Provides 1G bps switching bandwidth
t Full multi bus master structure
t Built-in intelligent bus load regulator for data
traffic balancing
t Allows XpressFlow Engine to communicate
t Provides centralized bus arbitration with two
with Access Controllers via a message pass-
ing protocol
level request priorities
à High priority for Data Messages
à Command Messages for passing control
à Low priority for Command Messages
information between devices
2.4.1 Pin Description
Symbol
Type Name & Functions
CMOS Data Bus Bit [31:0] – a 32-bit synchronous data bus.
S_D[31:0]
I/O-TS
Note: During the system RESET period, Data Bit [31:28] are used as
Processor Interface Configuration bit [0:3]
S_MSGEN# CMOS Message Envelope – encompasses the entire period of a message
I/O-TS
transfer. Targets use the leading edge of this signal to detect the be-
ginning of a message transfer, and to decode the message header for
the intended target(s).
S_EOF#
S_IRDY
CMOS
I/O-TS
End of Frame – only used by frame data transfer messages to identify
the end of frame condition. This signal is synchronous with the Rx
Frame Status word appended to the end of the message.
CMOS Initiator Ready – a normal true signal. When negated, it indicates the
I/O-TS
initiator had asserted wait state(s) in between command words. Target
should use this signal as enable signal for latching the data from the
bus.
S_TABT#
CMOS Target Abort – when asserted, the target had aborted the reception of
I/O-OD
current message on the bus.
CMOS High Priority Request – indicates one or more Bus Requester is re-
I/O-OD
S_HPREQ#
questing for high priority message transfer.
S_REQ[8:1]# CMOS Bus Request [8:1] – Bus Request signals from Access Controllers to
Input
S_GNT[8:1]# CMOS Bus Grant [8:1] – Bus Grant signals from Bus Arbitrator to Bus Re-
Output
Bus Access Arbitrator in XpressFlow Engine
questers
CMOS Bus Overload – when asserted all data forwarding bus bandwidth has
S_OVLD#
Output
been allocated. Cannot support additional load for data forwarding traf-
fic
S_CLK
CMOS XpressFlow Bus Clock – 33MHz system clock
Input
© 1998 Vertex Networks, Inc.
20
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.4.2 Bus Cycle Waveforms
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
D0
D1
D2
D3
D4
D5
EoF
S_EOF#
S_IRDY
XpressFlow Bus Data Transfer Cycle
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
C0
C1 EOF
C0
C1
S_EOF#
S_TABT#
Command Cycle
Data Xfer w/o Data
Aborted Command
Other XpressFlow Bus Cycles
S_CLK
S_REQ[k]#
S_REQ[j]#
S_HPREQ#
High Priority Request pre-empts the low priority request
© 1998 Vertex Networks, Inc.
21
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
S_CLK
S_MSGEN#
S_REQ[j]#
S_GNT[j]#
S_HPREQ#
S_REQ[I]#
S_GNT[I]#
XpressFlow Bus arbitration
S_CLK
S_REQ[k]#
S_OVLD#
Bus Overload pre-empts the data transfer request
2.5 Test Pins
Symbol
TEST
Type Name & Functions
CMOS Test Mode Selection & Test Output – Set Test Mode upon Reset,
I/O
and provides test status output during test mode
© 1998 Vertex Networks, Inc.
22
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
3
DC SPECIFICATION
3.1 ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Operating Temperature
-65 C to +150 C
0 C to +70 C
Supply Voltage VDD with Respect to VSS
Voltage on 5V Tolerant Input Pins
Voltage on Other Pins
+3.0 V to +3.6 V
-0.5 V to (VDD + 2.5 V)
-0.5 V to (VDD + 0.3 V)
Stresses above those listed may cause permanent device failure. Functionality at or above these
limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device
reliability.
3.2 DC CHARACTERISTICS
VDD = 3.0 V to 3.6 V;
TAMBIENT = 0 C to +70 C
Preliminary
Typ
Symbol
fosc
Parameter Description
Frequency of Operation ( -40)
Min
Max
Unit
20
20
20
40.0000
50.0000
66.6666
500
MHz
MHz
MHz
mA
Frequency of Operation ( -50)
Frequency of Operation (-66)
IDD
Supply Power – @ 33.3333 MHz (VDD =3.3
V)
300
Supply Power – @ 40 MHz (VDD =3.3 V)
Supply Power – @ 50 MHz (VDD =3.3 V)
300
300
500
500
mA
mA
V
VOH-CMOS Output High Voltage (CMOS) IOH = -1.0 mA
VOL-CMOS Output Low Voltage (CMOS) IOL = 1.0 mA
VDD - 0.5
2.4
0.45
V
VOH-TTL
VOL-TTL
Output High Voltage (TTL) IOH = -1.0 mA
Output Low Voltage (TTL) IOL = 1.0 mA
V
0.45
VDD + 0.3
VDD x 30%
VDD + 0.3
+0.8
V
VIH-CMOS Input High Voltage (CMOS)
VDD x 70%
-0.5
V
VIL-CMOS
VIH-TTL
VIL-TTL
VIH-5VT
VIL-5VT
ILI
Input Low Voltage (CMOS)
Input High Voltage (TTL)
V
2.0
V
Input Low Voltage (TTL)
-0.3
V
Input High Voltage (TTL 5V tolerant)
Input Low Voltage (TTL 5V tolerant)
2.0
VDD + 2.5
+0.8
V
-0.3
V
Input Leakage Current (0.1 V V
V
)
DD
10
A
IN
(all pins except those with internal pull-
up/pull-down resistors)
ILO
IIH
Output Leakage Current (0.1 V V
VDD)
15
60
A
A
OUT
Input Leakage Current VIH = VDD - 0.1 V
(pins with internal pull-down resistors)
Input Leakage Current VIL = 0.1 V
(pins with internal pull-up resistors)
Input Capacitance
IIL
-60
A
CIN
COUT
CI/O
8
8
pF
pF
pF
Output Capacitance
I/O Capacitance
10
© 1998 Vertex Networks, Inc.
23
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
4
AC SPECIFICATION
4.1 XpressFlow Bus Interface:
S_CLK
S_CLK
S12
S1-min
S1-max
S1-min
S_D[31:0]
S_D[31:0]
S13
S2-min
S2-max
S2-min
S_MSGEN#
S_EOF#
S_MSGEN#
S14
S3-min
S3-max
S3-min
S_EOF#
S15
S4-min
S4-max
S4-min
S_IRDY
S_IRDY
XpressFlow Bus Interface –
Output float delay timing
S6-max
S6-min
S_TABT#
S7-max
S7-min
S_CLK
S_HPREQ#
S17
S19
S21
S23
S27
S29
S31
S8-max
S8-min
S18
S20
S22
S24
S28
S30
S32
S_D[31:0]
S_MSGEN#
S_EOF#
S_GNT[7:0]#
S9-max
S9-min
S_OVLD#
XpressFlow Bus Interface –
Output valid delay timing
S_IRDY
S_TABT#
S_HPREQ#
S_REQ[7:0]#
XpressFlow Bus Interface –
Input setup and hold timing
© 1998 Vertex Networks, Inc.
24
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
-40
-50
-66
Symbol
Parameter
Min (ns) Max Min (ns) Max Min (ns) Max
Note:
CL = 50pf
(ns)
(ns)
(ns)
S1
S2
S_D[31:0] output valid delay
S_MSGEN# output valid delay
S_EOF# output valid delay
S_IRDY output valid delay
S_TABT# output valid delay
S_HPREQ# output valid delay
6
6
6
6
6
6
6
6
14
14
14
14
14
14
14
14
18
18
18
18
5
5
5
5
5
5
5
5
11
11
11
11
11
11
11
11
15
15
15
15
4
4
4
4
4
4
4
4
8.5
8.5
8.5
8.5
8.5
8.5
8.5
8.5
12
CL = 50pf
CL = 50pf
CL = 50pf
CL = 50pf
CL = 50pf
CL = 20pf
CL = 50pf
S3
S4
S6
S7
S8
S_GNT[7:0]# output valid delay
S_OVLD# output valid delay
S_D[31:0] output float delay
S_MSGEN# output float delay
S_EOF# output float delay
S_IRDY output float delay
S_D[31:0] input set-up time
S_D[31:0] input hold time
S_MSGEN# input set-up time
S_MSGEN# input hold time
S_EOF# input set-up time
S_EOF# input hold time
S9
S12
S13
S14
S15
S17
S18
S19
S20
S21
S22
S23
S24
S27
S28
S29
S30
S31
S32
12
12
12
2
1.5
4.5
1.5
4.5
1.5
4.5
1.5
4.5
4.5
4.5
3.5
4.5
5
1
5.5
2
3.5
1
5.5
2
3.5
1
5.5
2
3.5
1
S_IRDY input set-up time
S_IRDY input hold time
5.5
5.5
5.5
4.5
5.5
6
3.5
3.5
3.5
2.5
3.5
4
S_TABT# input set-up time
S_TABT# input hold time
S_HPREQ# input set-up time
S_HPREQ# input hold time
S_REQ[7:0]# input set-up time
S_REQ[7:0]# input hold time
5.5
4.5
3.5
AC Characteristics -- XpressFlow Bus Interface
© 1998 Vertex Networks, Inc.
25
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
P_CLK
4.2 CPU Bus Interface:
P1
P3
P2
P4
P6
P8
P_CLK
P_RST#
P15
P16-min
P_D[31:0]
P_ADS#
P_W/R#
P_CS#
P5
P7
CPU Bus Interface –
Output float delay timing
P_CLK
P16-max
P16-min
P9
P10
P12
P_D[31:0]
P_RDY#
P_INT
P_A[11:1]
P_D[31:0]
P17-max
P17-min
P11
P18-max
P18-min
CPU Bus Interface –
Input setup and hold timing
CPU Bus Interface –
Output valid delay timing
-40
-50
-66
Symbol
Parameter
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Note:
P1
P2
P_RST# input setup time
P_RST# input hold time
P_ADS# input set-up time
P_ADS# input hold time
P_W/R# input set-up time
P_W/R# input hold time
P_CS# input set-up time
P_CS# input hold time
13
3.5
13
10
2.5
10
8
2
8
2
8
2
8
2
8
2
8
2
P3
P4
3.5
13
2.5
10
P5
P6
3.5
13
2.5
10
P7
P8
3.5
13
2.5
10
P9
P_A[11:1] input set-up time
P_A[11:1] input hold time
P_D[31:0]# input set-up time
P_D[31:0]# input hold time
P_D[31:0]# output float delay
P_D[31:0]# # output valid delay
P_RDY# output valid delay
P_INT# output valid delay
P10
P11
P12
P15
P16
P17
P18
3.5
13
2.5
10
3.5
2.5
17
17
13
13
10
10
8
CL = 60pf
10
13
CL = 60pf
CL = 20pf
6.5
5
8.5
AC Characteristics -- CPU Bus Interface
© 1998 Vertex Networks, Inc.
26
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
4.3 Local Memory Interface:
Local Memory Interface:
L_CLK
L_CLK
L_D[31:0]
L_A[19:2]
L3-max
L3-min
L1
L2
L_D[31:0]
L4-max
L4-min
Local Memory Interface –
Input setup and hold timing
L5-max
L5-min
L_CS[3:0]#
L_ADSC#
L_BWE[3:0]#
L_WE#]
L_CLK
L6-max
L6-min
L10
L3-min
L_D[31:0]
L7-max
L7-min
Local Memory Interface –
Output float delay timing
L8-max
L8-min
L9-max
L9-min
L_OE#
Local Memory Interface –
Output valid delay timing
-40
-50
-66
Symbol
Parameter
Min Max Min Max Min Max
(ns) (ns) (ns) (ns) (ns) (ns)
Note:
L1
L2
L3
L4
L6
L7
L8
L9
L10
L_D[31:0]# input set-up time
L_D[31:0]# input hold time
L_D[31:0]# output valid delay
L_A[19:2] output valid delay
L_ADSC# output valid delay
L_BWE[3:0]# output valid delay
L_WE# output valid delay
L_OE# output valid delay
6.5
3
5.5
2.5
4
4
2
3
3
3
3
3
3
5
17
17
17
17
17
17
22
13
13
13
13
13
13
18
10 CL = 30pf
10 CL = 30pf
10 CL = 30pf
10 CL = 30pf
10 CL = 10pf
10 CL = 10pf
14
5
4
5
4
5
4
5
4
5
4
L_D[31:0]# output float delay
AC Characteristics – Local Memory Interface
© 1998 Vertex Networks, Inc.
27
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
4.4 CAM Memory Interface:
S_CLK
C1
S_CLK
C_D[15:0]
C_CE#
C2
C_D[15:0]
C7-max
C7-min
C3
C5
C4
C6
C_MF#
C_FF#
C8-max
C8-min
C9-max
C9-min
CAM Memory Interface –
Input setup and hold timing
C_WE#
C_CM#
C10-max
C10--min
S_CLK
C11-max
C11-min
C12
C7-min
C_EC#
C_D[15:0]
CAM Memory Interface –
Output valid delay timing
CAM Memory Interface –
Output float delay timing
-40
-50
-66
Symbol
Parameter
Min Max Min Max Min Max
(ns) (ns) (ns) (ns) (ns) (ns)
Note:
C1
C2
C_D[15:0]# input set-up time
C_D[15:0]# input hold time
C_MF# input set-up time
C_MF# input hold time
C_FF# input set-up time
C_FF# input hold time
4.5
1.5
4.5
1.5
4.5
1.5
5
4
1.5
4
5
2
5
2
5
2
6
6
6
6
6
C3
C4
1.5
4
C5
C6
1.5
4
C7
C_D[15:0]# output valid delay
C_CE# output valid delay
C_WE# output valid delay
C_CM# output valid delay
C_CE# output valid delay
C_D[16:0]# output float delay
18
18
18
18
18
13
15
15
15
15
15
10
20
20
20
20
20
15
C8
5
4
C9
5
4
C10
C11
C12
5
4
5
4
AC Characteristics – CAM Memory Interface
© 1998 Vertex Networks, Inc.
28
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
5
PACKAGING INFORMATION
5.1 256-PIN PQFP
30.6 ± 0.20
25.2 REF
256
193
192
1
Pin 1 I.D.
25.2
28.0 30.6
A
B
REF ± 0.20 ± 0.20
64
129
65
128
0.14/0.22
0.40
TYP
D
28.0 ± 0.20
3.40
± 0.20
4.10
MAX.
C
0.25
MIN.
1.30 REF.
0.50/0.75
© 1998 Vertex Networks, Inc.
29
Rev. 4.5 – February
1999
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
5.2 256- Pin BGA
B
Pin 1 I.D.
20 18 16 14 12 10
19 17 15 13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
A
M
N
P
R
T
U
V
W
Y
1.27
27.00
24.13
C
2.50
max
0.50 / 0.70
Ordering Information
Part Number
Description
XpressFlow Switch Engine
Identification
C 0 B
Vertex Networks Use
TAV
Revision
rrr
SC220
Environmental –
Speed grade -
C = Commercial
I = Industrial
Revision -
For latest revision, leave blank
001 = Rev.1
0 = 40 MHz
5 = 50 MHz
6 = 66 MHz
Package -
B = BGA
P= PQFP
This document contains preliminary information on our product. Vertex reserves the right to make any changes without notice.
16842 Von Karman Ave, Suite 250
Rev. 4.5- February, 1999
Irvine, CA 92606-4950
Tel. 1-714-252-8880, FAX: 1-714-252-8868
Web Site: www.vertex-networks.com
Ó 1998 V
N
ERTEX ETWORKS
DIMENSION
MIN
MAX
A
A1
A2
D
2.20
0.50
1.17 REF
26.80
2.46
0.70
27.20
D1
E
E1
b
e
24.00 REF
27.20
0.90
26.80
24.00 REF
E1
E
0.60
1.27
256
Conforms to JEDEC MS - 034
e
D1
D
A2
A
A1
1. CONTROLLING DIMENSIONS ARE IN MM
2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER
3. PRIMARY DATUM -C- AND SEATING PLANE
ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
4. N IS THE NUMBER OF SOLDER BALLS
5. NOT TO SCALE.
6. SUBSTRATE THICKNESS IS 0.56 MM
Package Code
c
Zarlink Semiconductor 2003 All rights reserved.
Previous package codes:
ISSUE
ACN
DATE
APPRD.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
©2020 ICPDF网 联系我们和版权申明