SP5611KG/MPAD [ZARLINK]
PLL/Frequency Synthesis Circuit, PDSO16;
| 型号： | SP5611KG/MPAD |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | PLL/Frequency Synthesis Circuit, PDSO16 光电二极管 |
| 文件： | 总11页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP5611
1·3GHz Bidirectional I2C Bus Controlled Synthesiser
Advance Information
DS3758
ISSUE 5.0
June 1998
The SP5611 is a single chip frequency synthesiser de-
signed for TV tuning systems. Control data is entered in the
standardI2CBUSformat. Thedevicecontains4addressable
bidirectional open collector ports, one of which is a 3-bit
ADC. The information on these ports can be read via the I2C
BUS. the device has 4 programmable addresses, pro-
grammed by applying a specific input voltage to the P3
address select input. This enables two or more synthesisers
to be used in a system.
Ordering Information
SP5611 KG/MPAS (Tubes)
SP5611S KG/MPAD(Tape and reel)
FEATURES
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CHARGE PUMP
DRIVE OUTPUT
I Complete 1·3GHz Single Chip System
I High Sensitivity RF Inputs
I Programmable via I2C BUS
I Low Power Consumption (5V, 20mA)
CRYSTAL Q1
CRYSTAL Q2
SDA
V
EE
RF INPUT
RF INPUT
SP5611
SCL
V
CC
NC
P3 ADD SELECT PORT
I/O PORT P4
†
*
†
I/O PORT P7
I/O PORT P6
I/O PORT P5
I
Low Radiation
†
I Phase Lock Detector
MP16
I Varactor Drive Amp Disable
† = Logic level I/O port
* = 3-bit ADC input
I 4 Bi-directional Controllable Outputs
I 5-Level ADC
I Variable I2C BUS Address for Multi-tuner Applications
I ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1)
I Switchable 4512/1024 Reference Divider
I Pin and Function Compatible with SP5511S (2)
Fig. 1 Pin connections – top view
APPLICATIONS
I Satellite TV
I Cable Tuning Systems
I VCRs
(1) Normal ESD handling precautions should be observed.
(2) The SP5511S does not have a switchable reference
division ratio.
THERMAL DATA
uJC = 41°C/W
uJA = 111°C/W
SP5611 Advance Information
ELECTRICAL CHARACTERISTICS
TAMB = 240°C to 185°C, VCC = 14·5V to 15·5V, reference frequency = 4MHz.
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated.
Value
Characteristic
Pin
Units
Conditions
Min.
Typ.
Max.
Supply current
12
20
27
mA
VCC = 4·5V to 5·5V (note 1)
Prescaler input voltage
13,14
12·5
300 mVrms 50MHz to 1·3GHz sinewave,
see Fig. 5
Prescaler input impedance
Prescaler input capacitance
13,14
13, 14
50
2
Ω
pF
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
4,5
4,5
4,5
4,5
4,5
3
0
5·5
1·5
10
210
10
V
V
µA
µA
µA
Input voltage = VCC
Input voltage = 0V
When VCC = 0V
SDA
Output voltage
4
0·4
V
Sink current = 3mA
Charge pump current low
Charge pump current high
1
1
1
650
6170
µA
µA
nA
µA
Byte 4, bit 2 = 0, pin 1 = 2V
Byte 4, bit 2 = 1, pin 1 = 2V
Byte 4, bit 4 = 1, pin 1 = 2V
V pin 16 = 0·7V
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance
External reference input frequency
External reference input amplitude
6 5
200
8
16
500
10
6400
Ω
mV p-p
Ω
Parallel resonant crystal (note 2)
2
2
2
2
80
1000
750
2
70
MHz AC coupled sinewave
200 mVrms AC coupled sinewave
Output Ports
P4-P7 sink current
P4-P7 leakage current
9-6
9-6
10
mA
µA
V
OUT = 0·7V
10
VOUT = 13·2V
Input Ports
P3 input current high
P3 input current low
P4, P5, P7 input voltage low
P4, P5, P7 input voltage high
P6 input current high
P6 input current low
10
10
9,8,6
9,8,6
7
1
20·5
0·8
mA
mA
V
V
µA
µA
V pin 10 = VCC
V pin 10 = 0V
2·7
110
210
See Table 3 for ADC levels
7
NOTES
1. Maximum power consumption is 150mW with VCC = 5·5V and all ports off.
2. Resistance specified is maximum under all conditions.
2
Advance Information SP5611
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE and pin 3 at 0V
Value
Parameter
Pin
Units
Conditions
Min.
Max.
Supply voltage
RF input voltage
Port voltage
12
13,14
6-9
6-9
6-9
10
20·3
7
V
V p-p
V
2·5
20·3
20·3
14
Port in off state
6
V
Port in on state
Total port output current
Address select voltage
RF input DC offset
50
mA
V
20·3
20·3
20·3
20·3
20·3
20·3
20·3
255
V
V
V
V
V
V
CC10·3
CC10·3
CC10·3
CC10·3
CC10·3
CC10·3
6
13-14
1
V
Charge pump DC offset
Drive output DC offset
Crystal oscillator DC offset
SDA, SCL input voltage
V
16
V
2
V
4,5
V
V
Storage temperature
Junction temperature
1150
1150
°C
°C
PREAMP
13
OSC
2
F
F
Q1
Q2
PD
COMP
15-BIT
PHASE
DIVIDER
4512/1024
PRESCALER
PROGRAMMABLE
RF IN
COMP
CRYSTAL
14
48
3
1
DIVIDER
F
LOCK
DET
CHARGE PUMP
15-BIT LATCH
DIVIDE RATIO
POWER
ON DET
DN
UP
16
CHARGE
PUMP
DRIVE/
VARICAP OUT
POR
F
L
5
4
SCL
SDA
2
I
C BUS
CONTROL DATA
LATCHES
TRANSCEIVER
CP
TO
OS
AND
CONTROL LOGIC
4
LEVEL
3 TTL
COMP
4-BIT LATCH
PORT INFO
ADDRESS
SELECT
3-BIT
ADC
4
PORT OUTPUT
DRIVERS
V
V
CC
15
EE
10
9
8
7
6
P3 ADD SELECT
P4
P5
P6
P7
Fig. 2 Block diagram
3
SP5611 Advance Information
FUNCTIONAL DESCRIPTION
The SP5611 is programmed from an I2C Bus. Data and
Clock are fed in on the SDA and SCL lines respectively, as
defined by the I2C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
LSB of the address byte (R/W) sets the device into write
mode if it is low and read mode if it is high. The Tables in Fig.
3 illustrate the format of the data. The device can be pro-
grammed to respond to several addresses, which enables
the use of more than one synthesiser in an I2C Bus sys-
tem. Table 4 shows how the address is selected by applying
a voltage to P3.
from 512 to 1024, and is controlled by bit 7 of byte 4 (TS0);
a logic 1 to 512, a logic 0 for 1024. The SP5611 differs from
the SP5511 in this respect, only 512 being available on the
SP5511. Note that the comparison frequency is 7·8125kHz
when a 4MHz reference is used, and divide by 512 is
selected.
Bit 2 of byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for 170µA and
a logic 0 for 50µA, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. When the device is frequency
locked, the charge pump current is internally set to 50µA
regardless of CP.
When the device receives a correct address byte, it pulls
the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are
programmed. When the device is programmed into the read
mode, the controller accepting the data must pull the SDA
line low during all status byte acknowledge periods to read
another status byte. If the controller fails to pull the SDA line
lowduringthisperiod, thedevicegeneratesaninternalSTOP
condition, which inhibits further reading.
Bit 4 of byte 4 (T0) disables the charge pump when it is set
to a logic 1.
Bit 8 of byte 4 (OS) switches the charge pump drive
amplifier’s output off when it is set to a logic 1.
Bit 3 of byte 4 (T1) enables various test modes when set
high. These modes are selected by bits 5, 6 and 7 of byte 4
(TS2, and TS1, TS0) as detailed in Table 5. When T1 is set
low, TS2 and TS1 are assigned a ‘don’t care’ condition, and
TS0 selects the reference divider ratio as previously de-
scribed.
WRITE Mode (Frequency Synthesis)
When the device is in write mode bytes 2 and 3 select the
synthesised frequency, while bytes 4 and 5 control the output
port states, charge pump, reference divider ratio and various
test modes.
Byte 5 programs the output ports P4 to P7; a logic 0 for a
high impedance output and a logic 1 for low impedance (on).
READ Mode
Once the correct address is received and acknowledged,
the first bit of the next byte determines whether that byte is
interpreted as byte 2 or 4; a logic 0 for frequency information
and a logic 1 for control and output port information. When
byte 2 is received the device always expects byte 3 next.
Similarly, when byte 4 is received the device expects byte 5
next. Additional data bytes can be entered without the need
to re-address the device until an I2C stop condition is
recognised. This allows a smooth frequency sweep for fine
tuning or AFC purposes.
When the device is in read mode the status byte read from
the device on the SDA line takes the form shown in Table 2.
Bit 1 (POR) is the power-on reset indicator and is set to
a logic 1 if the VCC supply to the device has dropped below 3V
(at 25˚C), for example, when the device is initially turned on.
The POR is reset to 0 when the read sequence is terminated
by a stop command. When POR is set high (at low VCC), the
programmed information is lost and the output ports are all
set to high impedance.
Bit 2 (FL) indicates whether the device is phase locked, a
logic 1 is present if the device is locked, and a logic 0 if the
device is unlocked.
If the transmission of data is stopped mid-byte (for exam-
ple, by another device on the bus) then the previously pro-
grammed byte is maintained.
Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports
P7, P5andP4respectively. Alogic0indicatesalowleveland
a logic 1 a high level. If the ports are to be used as inputs they
should be programmed to a high impedance state (logic 1).
These inputs will then respond to data complying with TTL
type voltage levels.
Frequency data from bytes 2 and 3 are stored in a 15-bit
register and used to control the division ratio of the 15-bit
programmable divider. This is preceded by a divide-by-8
prescaler and amplifier to give excellent sensitivity at the local
oscillator input, see Fig. 5. The input impedance is shown in
Fig. 7.
Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
the 5-level ADC. The ADC can be used to feed AFC informa-
tion to the microprocessor from the IF section of the receiver,
as illustrated in the typical application circuit.
The programmed frequency can be calculated by multiply-
ing the programmed division ratio by 8 times the comparison
frequency FCOMP. When frequency data is entered, the phase
comparator, via a charge pump and varicap drive amplifier,
adjusts the local oscillator control voltage until the output of
the programmable divider is frequency and phased locked to
the comparison frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2, or provided by an on-
chip crystal controlled oscillator. The comparison frequency
APPLICATION
A typical application is shown in Fig. 4. All input/output
interfacecircuitsareshowninFig.6.TheSP5611isfunctionand
pin equivalent to the SP5511 device apart from the switchable
reference divider, and has much lower power dissipation,
improved RF sensitivity and better ESD performance.
F
COMP is derived from the reference frequency via the refer-
ence divider. The reference divider division ratio is switchable
4
Advance Information SP5611
MSB
LSB
Address
1
0
27
1
0
0
0
MA1 MA0
0
A
A
A
A
A
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
214 213 212 211 210
26 25 24 23 22
29
21
28
20
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits
1
CP T1 T0 TS2 TS1 TS0 OS
P7 P6 P5 P4
X
X
X
X
Table 1 Write data format (MSB transmitted first)
Address
1
1
0
0
0
MA1 MA0
1
A
A
Byte 1
Byte 2
Status byte
POR FL
I2
I1
I0
A2 A1 A0
Table 2 Read data format
A2 A1 A0
Voltage input to P6
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0·6VCC to 13·2V
0·45VCC to 0·6VCC
0·3VCC to 0·45VCC
0·15VCC to 0·3VCC
0V to 0·15VCC
MA1 MA0 Address select input voltage
0
0
1
1
0
1
0
1
0V to 0·1VCC
Open circuit
0·4VCC to 0·6VCC
0·9VCC to VCC
Table 3 ADC levels
Table 4 Address selection
T1 TS2 TS1 TS0
Operation mode description
Normal operation, test modes disabled, reference divider ratio = 1024
Normal operation, test modes disabled, reference divider ratio = 512
Charge pump source (down). Status bit FL set to 0
Charge pump sink (up). Status bit FL set to 1
0
0
1
1
1
1
1
X
X
0
0
1
1
1
X
X
0
1
0
0
1
0
1
X
X
0
1
X
Ports P4, P5, P6, P7set to state X
Port P7 = FPD/2; P4, P5, P6 set to state X
Port P7 = FPD; P6 = FCOMP; P4, P5 set to state X
Table 5 Operation modes
NOTES
X = don’t care
For further details of test modes, see Table 6
A
:
:
:
:
:
:
:
:
:
:
:
:
:
Acknowledge bit
MA1, MA0
CP
T1
T0
TS2, TS1, TS0
OS
P7, P6, P5, P4,
POR
Variable address bits (see Table 4)
Charge Pump current select
Test mode selection
Charge pump disable
Operation mode control bits (see Table 5)
Varactor drive Output disable Switch
Control output port states
Power On Reset indicator
Phase lock detect flag
Digital information from ports P7, P5 and P4 respectively
5-level ADC data from P6 (see Table 3)
Don’t care
FL
I2, I1, I0
A2, A1, A0
X
Fig. 3 Data formats
5
SP5611 Advance Information
112V
112V
IF SECTION
AFC OUT
IF SIGNAL
P7
P5
P4
BAND
INPUTS
9
8
7
6
5
4
3
2
1
P6
P3
10
11
12
13
14
15
16
15V
TUNER
15V
SCL
1n
CONTROL
MICRO
SP5611
0·1µ
2
I
C BUS SDA
OSCILLATOR
OUTPUT
4MHz
CRYSTAL
1n
130V
18p
39n
22k
22k
180n
V
T
47k
10k
VARICAP
INPUT
10n
BCW31
Fig. 4 Typical application
300
37·5
25
OPERATING
WINDOW
12·5
50
500
1000
FREQUENCY (MHz)
1300
1500
Fig. 5 Typical input sensitivity
6
Advance Information SP5611
V
CC
V
REF
CHARGE
PUMP
3k
3k
RF INPUTS
150
DRIVE
OUTPUT
OS
(O/P DISABLE)
Loop amplifier
RF input
V
CC
V
CC
67k
3k
SCL/SDA
CRYSTAL Q1
CRYSTAL Q2
ACK
*
*
ON SDA ONLY
SCL and SDA inputs
Reference oscillator
V
CC
V
CC
30k
3k
3k
PORT
P3
10k
P3 address select
Ports P7-P4
Fig. 6 SP5611 input/output interface circuits
7
SP5611 Advance Information
j1
j0.5
j2
j0.2
j5
0.5
5
0.2
1
2
0
1·25GHz
2j5
2j0.2
2j2
S11:ZO = 50Ω
NORMALISED TO 50Ω
2j0.5
FREQUENCY MARKER STEP = 250MHz
2j1
Fig. 7 Typical input impedance,
APPLICATION NOTES
An application note, AN168, is available for designing with
synthesisers such as the SP5611. It covers aspects such as
loop filter design, decoupling and I2C bus radiation problems.
The application note is published in the Zarlink Semiconduc-
torMediaICHandbook.Agenerictest/demonstrationboardhas
been produced, which can be used for the SP5611. A circuit
diagram and layout for the board are shown in Figs. 8 and 9.
The board can be used for the following purposes:
(A) Measuring RF sensitivity perfomance
(B) Indicating port function
(C) Synthesising a voltage controlled oscillator
(D)Testing external reference sources
The programming codes relevant to these tests are given in
Table 6.
EXTERNAL
REFERENCE
15V
130V
112V
P2
SK2
15V
C7
C8
100n
C9
100n
100n
C3 47n
R7 22k
R11 3k
S1
C6 10n
(NOT FITTED,
SEE NOTE)
C2
220n
R8 22k
S2
P3
R9 10k
R10 47k
VAR
GND
X1
4MHz
C1
18p
R12 1k
C14 10n
C5 1n
TR1
1
2
3
4
5
6
7
8
16
15
14
13
2N3904
SK1
TP1
RFINPUT
C4 1n
112V
DATA/SDA
R14 22k
15V
SP5611
C12 100p
12
11
10
9
R13 12k
C10 1n
TR2
2N3906
CLOCK/SCL
C13 100p
ENABLE/ADDRESS SEL
P1
P4
NOTE
To use an external reference,
capacitor C6 must be fitted
and capacitor C1 removed
from the board.
112V
D1
D2
D3
D4
D5
D6
6
7
8
9
10
11
PIN NO.
C11
1n
Fig. 8 Test board circuit
8
Advance Information SP5611
TP1 = PIN 3 DC BIAS
Top view (ground plane)
Underside (surface mounted components side)
NOTES
1. CIRCUIT SCHEMATIC IS SHOWN IN FIG. 8
2. ALL SUFACE MOUNT COMPONENTS ARE
MOUNTED ON UNDERSIDE OF BOARD
Fig. 9 Test board layout
9
SP5611 Advance Information
TEST MODES
As explained in the functional description, The SP5611 can
be programmed into a numb er of test modes. These are
invoked by programming Hex codes into byte 4, those most
commonly used being shown in Table 6.
NOTE:
WhenlookingatFPD orFCOMP signalsfromportsP7andP6.byte
should be sent twice, first to set the desired reference division
ratio then to switch on the chosen test mode.
Other codes will also apply due to don’t care conditions,
which are assumed to be 1 in the Table.
The pulses can then be measured by simply connecting an
oscilloscopeorcountertotherelevantoutputpinonthetestboard.
Hex code (byte 4)
Operation mode description
CP high mode
CP low mode
8C
8E
A2
A6
AA
AE
9E
8F
9F
Normal operation, reference divider ratio = 1024
Normal operation, reference divider ratio = 512
Charge pump source (down), FL set to 0
Charge pump sink (up), FL set to 1
CC
CE
E2
E6
EA
EE
DE
CF
DF
Port P7 = FPD/2
Port P7 = FPD, P6 = FCOMP
Charge pump disable, reference divider ratio = 512
Varactor line disable, reference divider ratio = 512
Charge pump and varactor linedisable, reference divider ratio = 512
Table 5 Operation modes
10
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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