SP5659/KG/MP2T [ZARLINK]
PLL Frequency Synthesizer, BIPolar, PDSO16, 0.150 INCH, PLASTIC, SOIC-16;
| 型号： | SP5659/KG/MP2T |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | PLL Frequency Synthesizer, BIPolar, PDSO16, 0.150 INCH, PLASTIC, SOIC-16 光电二极管 |
| 文件： | 总12页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP5659
2·7GHz I2C Bus Low Phase Noise Synthesiser
Data Sheet
January 2005
The SP5659 is a single chip frequency synthesiser
designed for tuning systems up to 2·7GHz.
Ordering Information
The RF preamplifier drives a divide-by two prescaler
which can be disabled for applications up to 2GHz, allowing
direct interfacing with the programmable divider, resulting in
astepsizeequaltothecomparisonfrequency.Forapplications
up to 2·7GHz the divide-by two is enabled to give a step size
of twice the comparison frequency.
SP5659/KG/MP1S 16 Pin SOIC Tubes
SP5659/KG/MP1T
16 Pin SOIC Tape & Reel
SP5659/KG/MP2S 16 Pin SOIC* Tubes
SP5659/KG/MP2T
16 Pin SOIC* Tape & Reel
*Pb Free Matte Tin
The comparison frequency is obtained either from an on-
chip crystal controlled oscillator or from an external source.
The oscillator frequency FREF or the comparison frequency
FCOMP may be switched to the REF/COMP output; this
feature is ideally suited to providing the reference frequency
for a second synthesiser such as in a double conversion
tuner (see Fig. 5).
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CHARGE PUMP
CRYSTAL
REF/COMP
ADDRESS
SDA
DRIVE
V
EE
RF INPUT
RF INPUT
The synthesiser is controlled via an I2C bus and responds
to one of four programmable addresses which are selected
by applying a specific voltage to the Address input. This
feature enables two or more synthesisers to be used in a
system.
SP5659
V
CC
SCL
ADC
PORT P3
PORT P2
PORT P0
PORT P1
The SP5659 contains four switching ports, P0-P3 and a
5-level ADC, the output of which can be read via the I2C bus.
The SP5659 also contains a varactor line disable and
charge pump disable facility.
MP16
Figure 1 – Pin connections – top view
Features
•
•
•
•
•
•
•
•
Complete 2·7GHz Single Chip System
Optimised for Low Phase Noise
Selectable 42 prescaler
•
•
•
Variable I2C BUS Address for Multi-tuner Applications
ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1)
Pin Compatible with SP5658
Selectable Reference Division Ratio
Selectable Reference/Comparison Frequency Output
Selectable Charge Pump Current
Varactor Drive Amplifier Disable
5-Level ADC
(1) Normal ESD handling precautions should be observed.
Applications
•
•
Satellite TV
High IF Cable Tuning Systems
Thermal Data
uJC = 41°C/W
uJA = 111°C/W
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
SP5659
ELECTRICAL CHARACTERISTICS
TAMB = -20°C to +80°C, VCC = +4·5V to +5·5V, reference frequency = 4MHz.
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient
temperature and supply voltage ranges unless otherwise stated.
Value
Characteristic
Supply current, ICC
Pin
12
Units
Conditions
Min.
Max.
V
V
CC = 5V, PE = 1 (note 1)
CC = 5V, PE = 0
68
58
85
73
mA
mA
300MHz to 2·7GHz, PE = 1
(prescaler enabled) see Fig. 4b
100MHz, PE = 1 (prescaler
enabled) see Fig. 4b
RF input voltage
13,14
50
300 mVrms
mVrms
100MHz to 2·0GHz, PE = 0
(prescaler disabled) see Fig. 4b
mVrms
See Fig. 10
See Fig. 10
RF input impedance
RF input capacitance
13,14
13,14
50
2
Ω
pF
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
Input hysteresis
5, 6
5, 6
5, 6
5, 6
5, 6
5, 6
3
0
5·5
1·5
10
-10
10
V
V
µA
µA
µA
V
Input voltage = VCC
Input voltage = VEE
VCC = VEE
0·8
Sink current = 3mA
SDA
V
Output voltage
5
0·4
Charge Pump
Output current
1
1
16
16
Output leakage current
Drive output current
Drive saturation voltage
+- 3
+-10
350
200
nA
mA
mV
1
Drive output disabled
AC coupled sinewave
AC coupled sinewave
External reference input frequency
External reference input amplitude
Crystal frequency
Crystal oscillator drive level
Recommended crystal series resistance
Crystal oscillator negative resistance
2
2
2
2
2
200
4
35
10
400
20
MHz
500 mVp-p
16
MHz
mVp-p
Ω
Parallel resonant crystal (note 2)
Includes temperature and
process tolerances
200
Ω
2
3
AC coupled, RE = 1, see note 3
REF/COMP output voltage, enabled
350
mVp-p
Comparison frequency
2
MHz
See note 4
Equivalent phase noise at phase detector
-142
dBC/Hz
Prescaler disabled, see Table 1
Prescaler enabled, see Table 1
See Table 1
RF division ratio
240
480
131071
262142
Reference division ratio
VPORT = 0·7V
P0, P1, P2, P3 sink current
7,8,9,10
10
mA
VPORT = 13·2V
P0, P1, P2, P3 leakage current
10
µA
See Fig. 3 Table 5
VCC >VINPUT >VEE
ADC input voltage
ADC input current
11
11
610
µA
Input voltage = VCC
Input voltage = VEE
Address input current high
Address input current low
4
4
1
-0·5
mA
mA
NOTES
1. Maximum power consumption is 468mW with VCC = 5·5V and all ports off.
2. Resistance specified is maximum under all conditions including start up.
3. If the REF/COMP output is not used, it should be left open circuit or connected to VCC and disabled by setting RE to logic 0.
4. 6kHz loop bandwidth, phase comparator frequency 250kHZ. Figure measured at 1kHz offset DSB (within loop bandwidth).
2
SP5659
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE at 0V
Value
Parameter
Pin
Units
Conditions
Min.
Max.
Supply voltage
RF input voltage
RF input DC offset
Port voltage
12
13,14
13, 14
7-10
7-10
7-10
11
-0·3
7
V
V p-p
V
2·5
V
CC+0·3
14
-0·3
-0·3
V
Port in off state
6
V
Port in on state
Total port current
50
mA
V
ADC input DC offset
REF/COMP output DC offset
Charge pump DC offset
Drive DC offset
-0·3
-0·3
-0·3
-0·3
-0·3
-0·3
-0·3
-55
V
V
V
V
V
V
CC+0·3
CC+0·3
CC+0·3
CC+0·3
CC+0·3
CC+0·3
6
3
V
1
V
16
V
Crystal oscillator DC offset
Address DC offset
2
V
4
V
SDA, SCL input voltage
Storage temperature
Junction temperature
5, 6
V
+150
+150
°C
°C
3
2
REF/COMP
CRYSTAL
PROGRAMMABLE DIVIDER
F
COMP
PREAMP
OSC
13
F
PD
REFERENCE
13-BIT
COUNT
PHASE
COMP
42/1
416/17
DIVIDER
RF IN
14
F
REF
(SEE TABLE 1)
LOCK
DET
1
CHARGE
PUMP
4-BIT
COUNT
16
DRIVE
CHARGE
PUMP
PE
C1, C0
MODE
CONTROL
DISABLE
1-BIT
COUNT
2-BIT
2-BIT
LATCH
17-BIT LATCH
DIVIDE RATIO
LATCH
5-BIT LATCH AND
MODE CONTROL LOGIC
(SEE TABLE 6)
F /2
PD
4
ADDRESS
SDA
5
6
F
L
2
I
C
12
15
P0 TEST
CONTROL
V
V
CC
TRANSCEIVER
SCL
4-BIT LATCH
AND
PORT INTERFACE
3
11
EE
ADC
3-BIT ADC
POWER ON
DETECT
7
8
9
10
P0
P3
P2
P1
Figure 2 - Block diagram
3
SP5659
FUNCTIONAL DESCRIPTION
The SP5659 contains all the elements necessary – with
theexceptionofafrequencyreference,loopfilterandexternal
high voltage transistor – to control a varactor tuned local
oscillator, so forming a complete PLL frequency synthesised
source.Thedeviceallowsforoperationwithahighcomparison
frequencyandisfabricatedinhighspeedlogicwhichenables
the generation of a loop with good phase noise performance.
The block diagram is shown in Fig. 2.
respectively. After two complete data bytes have been re-
ceived, additional data bytes can be entered, where byte
interpretation follows the same procedure without read-
dressing the device. This procedure continues until a STOP
condition is received. The STOP condition can be generated
after any data byte; if, however, it occurs during a byte
transmission then the previous data is retained.
To facilitate smooth fine tuning, the frequency data bytes are
only accepted by the device after all 17 bits of the data have
been received or after the generation of a STOP condition.
Repeatedly sending bytes 2 and 3 only will not change the
frequency. A frequency change when one of the following
data sequences is sent to an addressed device:
TheRFinputsignalisfedtoaninternalpreamplifier, which
provides gain and reverse isolation from the divider signals.
The output of the preamplifier interfaces with a 17-bit fully
programmable divider via a 42 prescaler. For applications
up to 2·0GHz RF input, the prescaler can be disabled, so
eliminating the degradation in phase noise due to prescaler
action. The divider is of MN1A architecture, where N = 16 or
17, the M counter is 13 bits and the A counter is 4 bits.
The output of the programmable divider, FPD, is fed to the
phase comparator where it is compared in phase and
Bytes 2, 3, 4, 5
Bytes 4, 5, 2, 3
or when a STOP condition follows valid data bytes thus:
Bytes 2, 3, 4, STOP
Bytes 4, 5, 2, STOP
Bytes 2, 3, STOP
Bytes 2, STOP
frequency domains with the comparison frequency FCOMP
.
This frequency is derived either from the on-chip crystal
controlled oscillator or from an external reference source. In
either case, the reference frequency FREF is divided down to
the comparison frequency by the reference divider, which is
programmable to one of 15 ratios as detailed in Table 1.
Theoutputofthephasedetectorfeedsachargepumpand
loop amplifier section which, when used with an external high
voltagetransistorandloopfilter, integratesthecurrentpulses
into the varactor line voltage. By invoking the device test
modes as described in Fig. 3, Table 6, the varactor drive
output can be disabled, so switching the external transistor
off. This allows an external voltage to be applied to the
varactor line for tuner alignment purposes. Similarly, the
charge can also be disabled to a high impedance state.
The programmable divider output FPD/2 can be switched
to port P0 by programming the device into test mode as set
out in Table 6.
Bytes 4, STOP
It should be noted that the SP5569 must be addressed
initially with both frequency AND control byte data, since the
control byte contains reference divider information which
must be provided before a chosen frequency can be synthe-
sised. This implies that after initial turn on, bytes 2, 3 and 4
must be sent followed by a STOP condition as a minimum
requirement. Alternatively, bytes 2, 3, 4 and 5 must be sent
if port information is also required.
READ Mode
When the device is in read mode the status byte read from
the device on the SDA line takes the form shown in Fig. 3,
Table 3.
Bit 1 (POR) is the power-on reset indicator and is set to
a logic ‘1’ if the VCC supply to the device has dropped below
3V (at 25˚C), for example, when the device is initially turned
on. The POR is reset to 0 when the read sequence is
PROGRAMMING
The SP5659 is controlled by an I2C Bus. Data and Clock
are fed in on the SDA and SCL lines respectively, as defined
bythe I2CBusformat. Thesynthesisercaneitheracceptnew
data (write mode) or send data (read mode). The LSB of the
address byte (R/W) sets the device into write mode if it is low
and read mode if it is high. Tables 1 and 2 in Fig. 3 illustrate
the format of the data. The device can be programmed to
respondtoseveraladdresses, whichenablestheuseofmore
than one synthesiser in an I2C Bus system. Table 4 in Fig. 3
shows how the address is selected by applying a voltage to
the address input.
R3 R2 R1 R0
Ratio Comparison frequency
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
2MHz
1MHz
8
500kHz
250kHz
125kHz
62·5kHz
31·25kHz
15·625kHz
16
When the device receives a valid address byte, it pulls the
SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are
programmed. When the device is programmed into the read
mode, the controller accepting the data must pull the SDA
line low during all status byte acknowledge periods to read
another status byte. If the controller fails to pull the SDA line
low during this period, the device generates an internal
STOP condition, which inhibits further reading.
32
64
128
256
Invalid
5
800kHz
400kHz
200kHz
100kHz
50kHz
10
WRITE Mode (Frequency Synthesis)
WithreferencetoTable2, bytes2and3containfrequency
information bits 214 to 20 inclusive. Auxiliary frequency bits
216 and 215 are in byte 4. For most frequencies, only bytes 2
and 3 will be required. The remainder of byte 4 and byte 5
control the prescaler enable, reference divider ratio (see
Fig. 3), output ports and test modes (see Table 6).
20
40
80
160
320
25kHz
After reception and acknowledgment of a valid address
(byte 1), the first bit of the following byte determines whether
the byte is interpreted as byte 2 (logic ‘0’) or byte 4 (logic ‘1’);
the next data byte is then interpreted as byte 3 or byte 5,
12·5kHz
Table 1 - Reference division ratios (4MHz external reference)
4
SP5659
terminated by a STOP command. When POR is set high (at
low VCC), the programmed information is lost and the output
ports are all set to high impedance.
Bit 2 (FL) indicates whether the device is phase locked, a
logic ‘1’ is present if the device is locked, and a logic ‘0’ if the
device is unlocked.
Test mode
The test modes are invoked by setting bit RE to logic ‘0’ and
bitRTStologic‘1’withintheprogrammingdataandareselected
by bits TS2, TS1 and TS0 as shown in Fig. 3, Table 6. When
TS2, TS1 and TS0 are received, the device retains previously
P2, P1 and P0 data.
Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
the ADC. The ADC can be used to feed AFC information to
the microprocessor via the I2C bus.
Reference comparison frequency output
The reference frequency FREF can be switched to the REF/
COMP output (pin 3) by setting byte 5 bit RE to logic ‘1’ and bit
RTS to logic ‘0’. The comparison frequency FCOMP can be
switched to the REF/COMP output by setting bit RE to logic ‘1’
and bit RTS to logic ‘1’. For RE set to logic ‘0’, the output is
disabled and set to a high state. RE and RTS default to logic ‘1’
during power-up, thus enabling FCOMP at the REF/COMP out-
put.
Additional Programmable Features
Prescaler enable
The 42 prescaler is enabled by setting bit PE in byte 4 to
a logic ‘1’. A logic ‘0’ disables the prescaler, directly passing
theRFinputtothe17-bitcounter. BitPEisastaticselectonly.
Charge pump current
ThechargepumpcurrentcanbeprogrammedbybitsC1and
C0 in data byte 5, as defined in Fig. 3, Table 7.
MSB
LSB
Address
1
1
0
0
0
MA1
210
22
MA0
29
21
0
A
A
A
A
A
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Programmable divider 0
Programmable divider 27
214 213 212 211
26 25 24 23
216 215 PE R3
28
20
R0
Control data
Control data
1
R2
R1
C1 C0 RE RTS P3 P2/TS2 P1/TS1 P0/TS0
Table 1 Write data format (MSB transmitted first)
Address
1
1
0
0
0
MA1 MA0
1
A
Byte 1
Byte 2
Status byte
POR FL
X
X
X
A2 A1 A0
A
Table 3 Read data format
A2 A1
A0 Voltage on ADC input
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0·6VCC to VCC
0·45VCC to 0·6VCC
0·3VCC to 0·45VCC
0·15VCC to 0·3VCC
0V to 0·15VCC
MA1 MA0 Address input voltage level
0
0
1
1
0
1
0
1
0V to 0·1VCC
Open circuit
0·4VCC to 0·6VCC
0·9VCC to VCC
Table 4 ADC levels
Table 5 Address selection
A
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Acknowledge bit
Variable address bits (see Table 5)
Programmable division ratio control bits
Prescaler enable
Reference division ratio select (see Table 1)
Charge pump current select (see Table 7)
Reference oscillator output enable
REF/COMP select when RE = 1, Test mode enable when RE = 0 (see Table 6)
Test mode control bits (valid when RE = 0 and RTS = 1,see Table 6)
Port P0 output state (always valid except when RE = 0 and RTS = 1 (see Table 6)
Ports P2, P1 and P0 output states
MA1, MA0
216-20
PE
R3, R2, R1, R0
C1, C0
RE
RTS
TS2, TS1, TS0
P0
P3, P2, P1
POR
FL
A2, A1, A0
X
Power on reset indicator
Phase lock flag
ADC data (see Table 4)
Don’t care
Figure 3 - Data formats
cont…
5
SP5659
TS2 TS1 TS0 REF/COMP O/P mode
RE RTS
Test mode description
Normal operation
X
X
X
X
X
1
X
0
0
1
1
X
X
X
X
0
1
0
1
X
X
X
Disabled to high state
Disabled to high state
Disabled to high state
Disabled to high state
Disabled to high state
Disabled to high state
FREF switched
0
0
1
1
1
1
1
0
1
0
0
0
0
0
1
1
Charge pump sink, status byte FL = 1
Charge pump source, status byte FL = 0
Charge pump disabled, status byte FL = 0
Port P0 = FPD/2
Varactor drive output disabled
Normal operation
X
X
FCOMP switched
Normal operation
Table 6 - REF/COMP output mode and test modes
C1
C0
Current (µA)
byte 5, bit 1
byte 5, bit 2
Min.
Typ.
Max.
0
0
1
1
0
1
0
1
+-90
+-120
+-260
+-555
+-1200
+-150
+-325
+-694
+-1500
+-195
+-416
+-900
Table 7 - Charge pump current
Figure 3 - Data formats (continued)
300
100
300
100
OPERATING
WINDOW
OPERATING
WINDOW
40
10
40
10
100
1000
2000
FREQUENCY (MHz)
3000
3500
100 300
1000
2000
FREQUENCY (MHz)
2700 3000
3500
Figure 4a - Prescaler disabled, PE = 0
Figure 4b - Prescaler enabled, PE = 1
Figure 4 - Typical input sensitivity
6
SP5659
DOUBLE CONVERSION TUNER SYSTEMS
The high 2·7GHz maximum operating frequency and
excellent noise characteristics of the SP5659 allow the
construction of double conversion high IF tuners.
AtypicalasshowninFig.5usestheSP5659asthefirstlocal
oscillator control for full band up conversion to an IF of greater
than 1GHz. The wide range of reference division ratios allows
the SP5659 to be used for both the up converter local oscillator
with a high phase comparison frequency (hence low phase
noise) and the down converter which uses the device in a lower
comparison frequency mode, which gives a fine step size.
1·6GHz
50-900MHz
38·9MHz
1650-2700MHz
REFERENCE CLOCK
SP8659
FIRST LO
SECOND LO
SP8659
Figure 5 - Example of double conversion from VHF/UHF frequencies to TV IF
1
130V
4MHz 18p
2
3
SP5659
112V
22k
68p
16k
47k
15n
Optional application using on-chip
crystal controlled oscillator
2·2n
13·3k
BCW31
TUNER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
10n
REF
1n
REF/COMP
1n
OSCILLATOR OUTPUT
ADDRESS
SDA
CONTROL
MICRO
15V
SP5659
10n
SCL
ADC
P0
P3
P2
P1
Figure 6 - Typical application
APPLICATION NOTES
An application note, AN168, is available for designing with
synthesisers such as the SP5659. It covers aspects such as
loop filter design and decoupling.
The board can be used for the following purposes:
(A) Measuring RF sensitivity performance
(B) Indicating port function
TheapplicationnoteispublishedintheZarlinkSemiconduc-
tor Media IC Handbook. A generic test/demonstration board
hasbeenproduced,whichcanbeusedfortheSP5659.Acircuit
diagram and layout for the board are shown in Figs. 7 and 8.
(C) Synthesising a voltage controlled oscillator
(D) Testing external reference sources
The programming codes relevant to these tests are given in
Fig. 3.
7
SP5659
EXTERNAL
REFERENCE
15V
130V
112V
P2
SK2
C7
C8
100n
C9
100n
100n
C3 68p
C6 10n
(NOT FITTED,
SEE NOTE 3)
C2
15n
R8 22k
P3
R8 16k
R9 47k
R6 13·3k
VAR
GND
X1
4MHz
C1
C12 2·2n
TR1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
18p
2N3904
P1
C5 1n
SK1
DISABLE/REF
RFINPUT
C4 1n
ENABLE
DATA/SDA
15V
C10 1n
CLOCK/SCL
C13
100p
C14
100p
NOTES
1. The circuit diagram shown is designed
for use with a number of synthesisers.
2. The LED connected to pin 11 is
redundant when an SP5659 is used in
this board.
P4
3. To use an external reference,
capacitor C6 must be fitted and
capacitor C1 removed from the board.
112V
D1
D2
D3
D4
D5
C11
1n
Figure 7 - Test board circuit diagram
RJM51 BOTTOM SILK SCREEN COMPONENT LOCATION
Figure 8 - Test board layout
8
SP5659
LOOP BANDWIDTH
Assuming the phase comparator noise floor is flat
regardless of sampling frequency, this means that the best
performancewillbeachievedwhentheoveralllocaloscillator
to phase comparator division ratio is a minimum.
Thearetwowaysofachievingahigherphasecomparator
sampling frequency:
Most applications for which the SP5659 is intended
require a loop filter bandwidth of between 2kHz and 10kHz.
Typically, the VCO phase noise will be specified at both
1kHz and 10kHz offset. It is common practice to arrange the
loop filter bandwidth such that the 1kHz figure lies within the
loop bandwidth. The phase noise therefore depends on the
synthesiser comparator noise floor rather than the VCO
The 10kHz offset figure should depend on the VCO
provided that the loop has been designed correctly and is not
underdamped.
1. Reducethedivisionratiobetweenthereferencesource
and the phase comparator
2. Use a higher reference source frequency
The second approach may be preferred for best
performance since it is possible that the noise floor of the
reference oscillator may degrade the phase comparator
performance if the reference division ratio is very small.
REFERENCE SOURCE
The SP5659 offers optimal local oscillator phase noise
performance when operated with a large step size. This is
because the local oscillator phase noise within the loop
bandwidth is:
DRIVING TWO SP5659s FROM A COMMON
REFERENCE
The REF/COMP output on pin 3 allows two synthesisers to
be driven from a common reference. To do this, the first device
should be programmed by setting RE = 1 and RTS = 0. The
driven device should be programmed for normal operation with
RE = 0 and RTS = 0. The two devices should be connected as
shown in Fig. 9.
FLO
Phase comparator noise floor 120log10
FCOMP
where FLO is the local oscillator frequency and FCOMP is the
phase comparator frequency.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
4MHz 18p
1n
SP5659
SP5659
Figure 9 - Two SP5659 devices using a common reference
j1
j0.5
j2
j0.2
j5
0.5
5
0.2
1
2
0
2j5
2j0.2
2j2
S11:ZO = 50Ω
NORMALISED TO 50Ω
2j0.5
FREQUENCY MARKERS AT 100MHz,
500MHz, 1GHz AND 2·7GHz
2j1
Figure 10 - Typical RF input impedance
9
SP5659
V
CC
V
REF
1
CHARGE
PUMP
500
500
13
RF INPUT
RF INPUT
14
200
100
16
DRIVE
OUTPUT
OS
(O/P DISABLE)
Loop amplifier
RF inputs
V
CC
V
CC
30k
3k
4
3k
ADDRESS
SCL/SDA/ADC
10k
ACK
*
*
ON SDA ONLY
Address input
SDA, SCL and ADC
V
CC
V
CC
PORT
3
REF/COMP
ENABLE/
DISABLE
2
CRYSTAL
Output ports
REF/COMP output
Reference oscillator
Figure 11 - Input/output interface circuits
10
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