概述
数据手册VP101-5BAHP 概述
30/50MHz 8-BIT CMOS VIDEO DAC 30 / 50MHz的8位CMOS视频DAC
VP101-5BAHP 数据手册
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FEBRUARY 1994
DS3002-2.0
VP101
30/50MHz 8-BIT CMOS VIDEO DAC
The VP101 is a CMOS 8-bit video DAC designed for
use in high performance, high resolution colour graphics
applications.
The device uses video control inputs (BLANK, SYNC
and REF WHITE) to provide the VP101 with the video
pedestal levels required to generate RS-343A compatible
video signals into a doubly-terminated 75Ω load, or
alternatively to produce RS-170 video signals across a
singly-terminated 75Ω load.
Data and control inputs are fully pipelined to maintain
synchronisation between the DAC outputs.
The full scale output current is defined by a 1.2V
reference and a single resistor. The reference voltage is
included on-chip in the VP101, but may be supplied
externally if required (see Fig. 2).
Differential and integral linearity errors of the D-A
converters are guaranteed to be a maximum of ±1LSB over
the full operating temperature range.
G5
G6
G7
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
G4
R7
R6
1
2
3
4
R5
R4
B7
BLANK
SYNC
AGND
IOB
5
6
7
8
B6
B5
B4
IOR
IOG
ISYNC
9
VAA
10
11
12
13
14
VAA
AGND
B0
AGND
FS ADJUST
VREF
COMP
REF WHITE
G3
B1
B2
B3
15
16
17
18
CLOCK
R0
R1
R2
R3
G2
G1
19
20
FEATURES
G0
DP40
■ 30/50MHz Pipeline Operation
■ Triple 8-Bit D-A Converters
■ ±1 LSB Differential Linearity Error
■ ±1 LSB Integral Linearity Error
■ Guaranteed Monotonic
■ RS-343A/RS-170 Compatible Levels
■ Drives Doubly Terminated 75Ω Load
■ Single 5V Power Supply
VREF
6
5
4
3
2
1
B3
B2
B1
B0
18
FS ADJUST 19
20
AGND
AGND 21
VAA
22
AGND
AGND
VAA
23
ISYNC
24
44 VAA
■ Typical Power Dissipation 500mW
■ Direct Replacement for Bt101
■ On-Chip Reference Available
43
42
41
40
VAA
B4
IOG 25
IOR
26
B5
IOB 27
B6
AGND 28
HP44
APPLICATIONS
■ High Resolution Colour Graphics
■ CAE/CAD/CAM Applications
■ Image Processing
■ Video Reconstruction
■ Instrumentation
ORDERING INFORMATION
VP101-3 BA DP (Commercial - Plastic DIL Package)
VP101-3 BA HP (Commercial - J-lead Package)
VP101-5 BA DP (Commercial - Plastic DIL Package)
VP101-5 BA HP (Commercial - J-lead Package)
VP101-3 BA GP (Commercial - Plastic Leaded Chip
Carrier, Gullwing formed leads)
VREF
12
44 B3
FS ADJUST 13
43
B2
14
AGND
42 B1
41 B0
AGND 15
VAA
VAA
16
17
18
40
AGND
39 AGND
ISYNC
38
37
36
35
34
VAA
IOG 19
VAA
B4
IOR
20
ABSOLUTE MAXIMIM RATINGS (Referenced to AGND)
IOB 21
B5
AGND 22
B6
DC supply voltage (V ) -0.3 to +7V
AA
Digital input voltage-0.3 to V +0.3V
AA
GP44
Analog output short circuit duration Indefinite
Ambient operating temperature 0°C to +70°C
Storage temperature range-55°C to +125°C
Fig.1 Pin connections (not to scale) - top view
VP101
Fig.2 functional block diagram of VP101
RECOMENDED OPERATING CONDITIONS
Symb
ol
Value
Typ.
Parameter
Units
Conditions
Min.
Max.
Supply voltage
V
4.75
0
5.00
5.25
+70
V
°C
Ω
V
AA
Ambient operating temperature
Output load
T
amb
R
37.5
1.20
542
L
Reference voltage
(internal or external)
FS ADJUST resistor
V
1.14
1.26
for RS-343A compatible output levels
REF
R
Ω
SET
THERMAL CHARACTERISTICS
DP HP GP
Thermal resistance, chip-to-case θ
=
12 17 17 °C/W
jc
Thermal resistance, chip-to-ambient θ = 45 50 50 °C/W
jc
2
VP101
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
As specified in recommended operating conditions.
DC CHARACTERISTICS
Value
Typ.
Parameter
Symbol
Units
Conditions
Min.
Max.
Resolution (each DAC)
8
Bits
Accuracy (each DAC)
Integral linearity error
Differential linearity error
Grey scale error
INL
DNL
±0.3
±0.3
±1%
±1
±1
±5%
LSB
LSB
% grey scale
Monotonicity
guaranteed
Digital inputs
Input high voltage
Input low voltage
Input high current
Input low current
V
V
3.0
AGND-0.3
V
+0.3
1.2
+1
-1
V
V
µA
µA
IH
AA
binary
coding
IL
I
IH
I
IL
Analog outputs
Grey scale current range
15
20
mA
255
LSB
Output currents
White level relative to blank level
17.69
16.74
0.95
0
19.06
276
17.62
255
1.44
21
5
0
7.62
111
5
20.40
18.50
1.90
50
mA
LSB
mA
LSB
mA
LSB
mA
LSB
mA
LSB
µA
White level relative to black level
Black level relative to blank level
Blank level on IOR, IOB
Blank level on IOG
RS-343A
tolerances
assumed
6.29
0
8.96
50
Sync level on IOG
LSB
µA
%
V
µA
LSB size
DAC to DAC matching
Output compliance
LSB
69.1
2
V
-0.5
+1.4
10
OC
External V
input current
I
REF
REF
Internal voltage reference
Internal V temperature coefficient
V
1.14
1.20
40
1.26
V
REF
ppm/°C
REF
AC CHARACTERISTICS
Parameter
VP101-5
Typ.
VP101-3
Typ. Max.
Symbol
Units
Conditions
Min.
Max.
Min.
Max clock rate
f
50
30
MHz
max
Data and control setup time
Data and control hold time
t
t
6
2
8
2
ns
ns
SU
H
Clock cycle time
Clock pulse width high time
Clock pulse width low time
t
20
8
8
33.3
10
10
ns
ns
ns
CYC
t
CLKH
t
CLKL
Analog output delay
Analog output rise/fall time
Analog output settling time
Glitch energy
t
10
10
ns
ns
ns
pV-sec
ns
DLY
t
8
9
VRF
t
12
100
0
15
100
0
S
Analog output skew
3
1
3
1
Pipeline delay
1
1
1
1
Clock
mA
V
supply current
I
120
175
100
140
at f
, V = 5V
AA
AA
max AA
3
VP101
CIRCUIT DESCRIPTION
As shown in the Fig. 2, the VP101 contains three 8-bit
D-A converters, input latches, and a loop amplifier.
On the rising edge of each clock cycle, (see Fig. 4), 24
Full Scale output current is set by an external resistor
) between the FS ADJUST pin and AGND. R has a
(R
SET
SET
typical value of 542Ω for generation of RS-343A video into a
37.5Ω load. The VP101 may be used in applications where
an external 1.2V (typical) reference is provided, in which
case the external reference should be temperature
compensated and provide a low impedance output.
The D-A converters on the VP101 use a segmented
architecture in which bit currents are routed to either the
output or AGND by a sophisticated decoding scheme.This
architecture eliminates the need for precision component
ratios and greatly reduces the switching transients
associated with turning current sources on or off.
Monotonicity and low glitch energy are guaranteed by using
identical current sources and current steering their outputs.
An on-chip operational amplifier stabilises the full scale
output current against temperature and power supply
variations.
bits of colour information (R -R , G -G , and B -B ) are
0
7
0
7
0
7
latched into the device and presented to the three 8-bit D-A
converters. The REF WHITE input, also latched on the rising
edge of each clock cycle, and will force the inputs of each D-
A converter to $FF.
SYNC and BLANK are latched on the rising edge of the
clock to maintain synchronisation with the colour data.These
inputs add appropriately weighted currents to the analog
outputs, producing the specific output levels required for
video applications as shown in Fig. 3. Table 1 details how the
SYNC, BLANK, and REFWHITE inputs modify the output
levels.
The I
current output is typically connected directly
SYNC
to the IOG output and is used to encode sync information
onto the IOG output. If I is not connected to the IOG
SYNC
output, sync information will not be encoded on the green
channel, and the IOR, IOG and IOB outputs will have the
same full scale output current.
The analog outputs of the VP101 are capable of directly
driving a 37.5Ω load, such as a doubly terminated 75Ω co-
axial cable or interpolation filters.
Fig.3 Composite video output waveform
IOG
(mA)
IOR/IOB
(mA)
REF
WHITE
DAC
I/P Data
Description
White Level
SYNC
BLANK
26.68
26.68
19.06
19.06
Data + 1.44
Data + 1.44
1.44
1
0
0
0
0
0
X
X
1
1
1
0
1
0
1
0
1
1
1
1
1
1
0
0
$XX
$FF
Data
Data
$00
White Level
Data
Data + 9.06
Data + 1.44
9.06
Data-Sync
Blank Level
Blank-Sync
Blank Level
Sync Level
1.44
1.44
$00
7.62
0
$XX
$XX
0
0
NOTE: Typical with full scale IOG = 26.68mA, R
= 542Ω, V
= 1.2V, I
connected to IOG
SET
REF
SYNC
Table 1:Video output truth table
4
VP101
Pin name
BLANK
Description
Composite blank control input. A logic ‘0’ forces the IOR, IOG and IOB outputs to the blanking level, as
illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK is a logic zero, the R -R , G -
0
7
0
G , B -B , and REF WHITE inputs are ignored.
7
0
7
SYNC
Composite sync control input. A logic ‘0’ on this input switches off a 40 IRE current source on the I
SYNC
output. SYNC does not override any other control or data input as shown in Table 1; therefore it should be
asserted only during the blanking interval. It is latched to the rising edge of CLOCK.
REF
WHITE
Reference white level control input. A logic ‘1’ on this input forces the IOR, IOG and IOB outputs to the white
level, regardless of the R -R , G -G and B -B inputs. It is latched on the rising edge of CLOCK. See table 1.
0 7 0 7 0 7
R -R
Red, Green, and Blue data inputs. R , G , and B are the least significant data bits. They are latched on the
0 0 0
rising edge of CLOCK. Coding is binary. Unused inputs should be connected to either the regular PCB power
or ground plane.
0
7
G -G
0
7
7
B -B
0
CLOCK
Clock input. The rising edge of CLOCK latches the R -R , G -G and B -B SYNC, BLANK, and REFWHITE
0 7 0 7 0 7
inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be
driven by a dedicated CMOS buffer.
IOR,IOG,
IOB
Red, Green, and Blue current outputs. these high impedance current sources are capable of directly driving a
doubly terminated 75Ω co-axial cable. All outputs, whether used or not, should have the same output load
(Note: A DC path to ground must be maintained).
I
Sync current output. Typically this current output is directly wired to the IOG output, and enables sync
information to be encoded onto the green channel. A logic ‘0’ on the SYNC input results in no current being
output to this pin, while logic ‘1’ results in the following current being output:
SYNC
V
R
(V)
(Ω)
REF
I
(mA) = 3468 X −−−−−−− ≡ 111 LSBs
SYNC
SET
If sync information is not required on the green channel, this output may be connected to V and the SYNC
AA
input tied high, causing the I
current source to be turned off, reducing the power consumption.
SYNC
FS
ADJUST
Full scale adjust control. A resistor (R
the full video signal (Fig. 3). The current flowing in the R
) connected between this pin and AGND controls the magnitude of
SET
resistor is equal to 32 LSBs. note that the IRE
SET
relationships in Fig. 3 are maintained, regardless of the full scale output current.
The relationship between R and full scale current on IOG (assuming I is connected to IOG) is:
SET
SYNC
V
R
(V)
(Ω)
REF
IOG (mA) = 12082 X −−−−−−− ≡ 387 LSBs
SET
The full scale output current on IOR, IOB (mA) for a given R
is defined as:
SET
V
(V)
REF
IOR, IOB (mA) = 8624 X −−−−−−− ≡ 276 LSBs
(Ω)
R
SET
COMP
Compensation pin. This pin provides compensation for the internal loop amplifier. A 0.01µF ceramic capacitor must
be connected between this pin and the nearest V pin.
AA
Connecting the capacitor to V rather than to the AGND provides the highest possible power supply noise
AA
rejection.
V
Voltage reference output. The output from an internal reference circuit, providing 1.2V (typical) reference.A
REF
0.1µF ceramic capacitor must be used to decouple this output to V
.
AA
AGND
Analog ground. All AGND pins must be connected.
V
Analog power. All V pins must be connected.
AA
AA
5
VP101
Non-Video Applications
APPLICATION NOTES
The VP101 may be used in non-video applications by
disabling the video specific control inputs. REF WHITE
should be a logic ‘0’ while BLANC and SYNC should be a
RS-343A and RS-170 Video Generation
For generation of RS-343A compatible video levels it is
recommended that a doubly terminated 75Ω load be used
logic ‘1’. I
should be connected to V or AGND. All
SYNC
AA
with an R
resistor value of approximately 542Ω
SET
three outputs will have the same full scale output current.
The relationship between R and full scale output
Similarly for generation of RS-170-compatible video, it is
recommended that a singly terminated 75Ω load be used
SET
current (I
) in this configuration is as follows:
OUT
with an R
value of about 774Ω. If the VP101 is not driving
SET
a large capacitive load, there will be negligible difference in
video quality between doubly terminated 75Ω and singly
terminated 75Ω loads.t
V (V)
REF
(mA) = 7968 X −−−−−−− ≡ 255 LSBs
I
out
R
(Ω)
SET
If driving a large capacitive load (load RC >1/20IIf ) it is
recommended that an output buffer with unloaded gain >2 be
used to drive a doubly terminated 75Ω load.
V
(V)
c
REF
Note that 1 LSB ≡
32 X R
(Ω)
SET
With the data inputs at $00, there is a DC offset current (I
defined as follows:
)
min
COMP Resistor
To optimise the settling time of the VP101, a resistor
may be added in series between the COMP capacitor and
COMP pin. The series resistor damps inductive ringing on
COMP, thus improving settling time.
V
R
(V)
(Ω)
I
(mA) = 656 X −−−−−−− ≡ 21 LSBs
REF
min
SET
Therefore the total full scale output current will be I
. The REF WHITE input may optionally be used as a
+
OUT
I
min
‘force to full scale’ control.
TIMING WAVEFORMS
Fig.4 Input/output timing
NOTES
1. Output delay, t , measured from the 50% point of the rising edge of CLOCK to the 50% point of full scale transition.
DLY
2. Settling time, t , measured from the 50% point of full scale transition to the output remaining within ± 1 LSB.
s
3. Output rise/fall time, t , measured between the 10% and 90% points of full scale transition.
VRF
6
VP101
Supply Decoupling
PCB LAYOUT CONSIDERATIONS
Noise on the analog power plane will be further reduced
by the use of multiple decoupling capacitors (See Fig. 5).
Optimum performance is obtained with 0.1µF chip
To obtain the optimum performance from the VP101
great care must be taken in the PCB layout to ensure low
noise power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
ceramic capacitors placed as close as possible to the V
AA
pins, with the shortest leads possible to reduce lead
inductance.
Power and Ground Planes
The VP101 and its associated circuitry should have its
own power/ground planes connected at a single point
through a ferrite bead. It is important that the regular PCB
and ground planes do not overlay any portions of the analog
power or ground planes to minimise plane-to-plane noise
coupling.
It should be noted that while the loop amplifier circuitry
of the VP101 will reject power supply noise, this rejection
decreases with frequency. Any high frequency noise on the
regular supply (such as produced by a switch mode power
supplies) must be adequately suppressed, else the designer
should consider using a three terminal regulator to supply
the analog power plane.
Digital Signal Interconnect
The digital signal lines to the VP101 should be isolated
as much as possible from the analog circuitry. Due to the
high clock rates used, the clock lines to the VP101 should be
as short as possible to minimise noise pickup.
Any pull-up resistors used on the inputs should be
connected to the regular PCB power plane, not to the analog
power plane.
Analog Signal Interconnect
For optimum performance the analog output connectors
and source termination resistors should be as close as
possible to the VP101 to minimise noise pickup and
reflections due to impedance mismatch. The video out
signals should overlay the ground plane and not the analog
power plane, to maximise the high frequency power supply
rejection.
Fig.5 VP101 typical connections
7
VP101
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02)66040993
Wiltshire SN2 2QW, United Kingdom.
Tel: (01793) 518000
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
Fax: (01793) 518411
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023.
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• UK, EIRE, DENMARK, FINLAND & NORWAY
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Swindon Tel: (01793) 518510 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1994 Publication No. DS3002 Issue No. 2.0 Feb 1994
Fax: (408) 438 5576
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be
regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The
Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not
constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such
information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
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use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
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of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
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Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
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