VP5513 [ZARLINK]

NTSC/PAL Digital Video Encoder; NTSC / PAL数字视频编码器


型号：	VP5513
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	NTSC/PAL Digital Video Encoder NTSC / PAL数字视频编码器编码器
文件：	总19页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

This product is obsolete.

This information is available for your

convenience only.

For more information on

Zarlink’s obsolete products and

replacement product lists, please visit

http://products.zarlink.com/obsolete_products/

VP5313/VP5513

NTSC/PAL Digital Video Encoder

Supersedes DS4509 1.9 September 1997 edition

DS4509 - 2.2 October 1998

The VP5313/VP5513 converts digital Y Cr Cb data into

analog PAL or NTSC composite video, and also provides

simultaneous RGB outputs. These additional converters can

optionally provide separate luma and chroma outputs plus a

further composite video channel. All outputs are capable of

driving doubly terminated 75Ω loads with standard video

levels.

All D/A converters are to 9 bit accuracy, and are provided with

27MHz oversampled data. The latter simplifies the

requirement for external analog anti-aliasing filters, and

reduces the sinx/x distortion inherent in D/A converters.

Separate digital scaling is applied to the chroma data path in

ordertomakethemostefficientuseofthe9bitdynamicrange.

The device accepts data inputs complying with CCIR

recommendation 656. In this format 4:2:2 video is multiplexed

onto an 8 bit bus using a 27MHz clock. Active video markers

are embedded into the data stream and extracted by the

VP5313/VP5513. Optionally the user can supply separate

horizontal and vertical syncs, and colour can be genlocked to

an external subcarrier if necessary.

In an alternative operating mode the VP5313/VP5513 can

be configured as the source of sync for the rest of the system.

In this master mode the horizontal and vertical sync pins

become outputs, and any control codes in the CCIR656 bit

stream are ignored.

The VP5313/VP5513 supports the insertion of teletext

data through a serial interface. An internal filter shapes the

data edges.

GP44

Fig.1 Pin connections (top view)

FUNCTION

VDD

FUNCTION

SCL

PD5

PD6

PD7

SDA

DACCOMP

RED/C

GREEN/Y

AVDD

AGND

AVDD

BLUE/CVBS2

CVBS1

VREF

CLAMP

COMPSYNC

PALID

SCSYNC

REFSQ

GND

FEATURES

■

Converts Y, Cr, Cb data to analog RGB and composite

or S-video and composite video

VDD

FC2

FC1

FC0

■

Supports CCIR recommendations 601 and 656

All digital video encoding

Selectable master/slave mode for sync signals

Switchable chrominance bandwidth

CCIR 624 PAL SMPTE or 170M NTSC compatible

outputs

RREF

AGND

AVDD

PD0

PD1

PD2

PD3

PD4

HSYNC

VSYNC

TTXREQ

TTXDATA

VDD

■

GENLOCK mode

I²C bus serial microprocessor interface

Only VP5313 supports Macrovision anti-taping

Rev. 7.01

■

Line 21 Closed Caption encoding

Teletext insertion, fully line programmable

GND

PXCK

RESET

APPLICATIONS

■

Digital Cable TV

Digital Satellite TV

Multi-media

Video games

Digital VCRs

Karaoke

ORDERING INFORMATION

VP5313A/CG/GP1N

VP5513A/CG/GP1N

VP5313/VP5513

RECOMMENDED OPERATING CONDITIONS

Parameter

Typ.

Units

Symbol

Min.

Max.

Power supply voltage

VDD, AVDD

IDD

4.75

5.25

230

190

+50ppm MHz

500

5.00

Power supply current (including analog outputs)¹

Power supply current (including analog outputs)²

Input clock frequency

IDD

PXCK

f^SCL

-50ppm

27.00

SCL clock frequency

Analog video output load

DAC gain resistor

Ambient operating temperature

kHz

Ω

37.5

730

°C

All four DACs driving 37R5 loads

All four DACs driving 75R loads

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions

DC CHARACTERISTICS

Parameter

Conditions

Typ.

Units

Symbol Min.

Max.

Digital Inputs TTL compatible (except SDA, SCL)

Input high voltage

VIN

VIL

2.0

0.8

Input low voltage

Digital Inputs SDA, SCL

Input high voltage

VIH

VIL

IIH

IIL

0.7VDD

0.3VDD

Input low voltage

µA

Input high current

VIN = VDD

-10

Input low current

VIN = VSS

Digital Outputs CMOS compatible

Output high voltage

VOH

VOL

3.7

IOH = -1mA

IOL = +4mA

0.4

0.6

Output low voltage

Digital Output SDA

VOL

Output low voltage

IOL = +6mA

DC CHARACTERISTICS DACs

Parameter

Typ.

Units

Symbol Min.

Max.

Accuracy (each DAC)

INL

±1.5

±1

±5

LSB

Integral linearity error

DNL

Diffential linearity error

DAC matching error

Monotonicity

LSB size

Internal reference voltage

Internal reference voltage output impedance

Reference Current (V^REF/RREF) RREF = 730Ω

Maximum output

guaranteed

66.83

1.00

µA

VREF

IREF

0.95

1.05

Ω

pV-s

1.3899

34.15

Peak Glitch Energy (see fig.3)

ABSOLUTE MAXIMUM RATINGS

Note: Stresses exceeding these listed under Absolute

Maximum Ratings may induce failure. Exposure to Absolute

Maximum Ratings for extended periods may reduce

reliability. Functionality at or above these conditions is not

implied.

Supply voltage

VDD, AVDD

-0·3 to 7·0V

-0·3 to VDD+0·3V

0 to 70°C

Voltage on any non power pin

Ambient operating temperature

Storage temperature

-55°C to 150°C

VP5313/VP5513

ESD COMPLIANCE

Pins

Test Levels

Notes

Test

All pins

2kV on 100pF through 1k5Ω

200V on 200pF through 0Ω & 500nH

Meets Mil-Std-883 Class 2

Human body model

Machine model

DC CHARACTERISTICS DACs

Parameter

Typ.

Units

Symbol Min.

Max.

RGB outputs:

Peak level

19.98

1.337

Black level

CVBS1, 2 Y and C outputs - NTSC (pedestal enabled)

Maximum output, relative to sync bottom

White level relative to black level

Black level relative to blank level

Blank level relative to sync level

Colour burst peak - peak

33.75

17.63

1.40

7.61

0.40

DC offset (bottom of sync)

CVBS1, 2, Y and C outputs - PAL

White level relative to black level

Black level relative to sync level

Colour burst peak - peak

18.70

8.01

0.00

DC offset (bottom of sync)

All figures are for: RREF = 730Ω; if RL = 75Ω then RREF = 1460Ω

VIDEO CHARACTERISTICS (NTSC, PAL COMPOSITE VIDEO)

Parameter

Typ.

Units

Symbol Min.

Max.

Luminance bandwidth

5.5

1.3

650

3.57954545

4.43361875

3.58205625

MHz

kHz

MHz

Chrominance bandwidth (Extended B/w mode)

Chrominance bandwidth (Reduced B/w mode)

Burst frequency (NTSC)

Burst frequency (PAL-B, D,G,H,I)

Burst frequency (PAL-N Argentina)

Burst cycles (NTSC and PAL-N)

Fsc cycles

Burst cycles ( PAL-B, D, G, H,I)

Fsc cycles

Burst envelope rise / fall time (NTSC )

Burst envelope rise / fall time (PAL-B, D, G, H, I, N)

Analog video sync rise / fall time (NTSC)

Analog video sync rise / fall time (PAL-B, D, G, H,I)

Analog video blank rise / fall time (NTSC )

Analog video blank rise / fall time (PAL-B, D, G, H,I)

Differential gain

300

145

245

145

245

% pk-pk

° pk-pk

Differential phase

Signal to noise ratio (unmodulated ramp)

Chroma AM signal to noise ratio (100% red field)

Chroma PM signal to noise ratio (100% red field)

Hue accuracy

Colour saturation accuracy

Residual sub carrier

-61

-56

-58

2.5

-60

Luminance / chrominance delay

VP5313/VP5513

PIN DESCRIPTIONS

Pin Name

Pin No.

Description

PD0-7

2-4,

38-42

8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit. These pins are

internally pulled low.

PXCK

27MHz Pixel Clock input. The VP5313/VP5513 internally divides PXCK by two to provide the

pixel clock.

12-14

Slave address select.

Standard I²C bus serial clock input.

Standard I²C bus serial data input/output.

SCL

SDA

FC0-2

Field Counter output in master sync mode.

REFSQ

SCSYNC

PALID

COMPSYNC

CLAMP

Reference square wave input used only during Genlock mode.

Subcarrier sync input, (synchronises phase quadrant in 4xfsc genlock mode), see fig 6.

PAL IDENT input, controls swinging colour burst phase in PAL genlock mode.

Composite sync pulse output. This is an active low output signal.

The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of

the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PAL-

B,D,G,I,N(Argentina)).

TTXREQ

TTXDATA

HSYNC

VSYNC

RESET

Teletext Data Request output, requests next line of teletext data.

Teletext Data input.

Horizontal Sync, output in master mode, input in slave mode

Vertical Sync, output in master mode, input in slave mode

Master reset. This is an asynchronous, active low, input signal and must be asserted for a

minimum 200ns in order to reset the VP5313/VP5513.

VREF

RREF

Voltage reference output. This output is nominally 1·0V and should be decoupled with a

100nF capacitor to GND.

DAC full scale current control. A resistor connected between this pin and GND sets the

magnitude of the video output current. An internal loop amplifier controls a reference current

flowing through this resistor so that the voltage across it is equal to the Vref voltage. This

reference current has a weighting equal to 20.8 LSB’s.

DACCOMP

CVBS1

DAC compensation. A 100nF ceramic capacitor must be connected to AVDD.

Composite video output. These are high impedance current source outputs. A DC path to

GND must exist from each of these pins.

BLUE/CVBS2

GREEN/Y

RED/C

VDD

Blue or composite DAC output. Output type as CVBS1.

Green or luminance DAC output. Output type as CVBS1.

Red or chrominance DAC output. Output type as CVBS1.

1, 11, 20 Positive supply input. All VDD pins must be connected.

37,28,30 Analog positive supply input. All AVDD pins must be connected.

10,21,43 Negative supply input. All GND pins must be connected.

36,29,35 Analog negative supply input. All AGND pins must be connected.

AVDD

GND

AGND

VP5313/VP5513

SDA

SCL

SET-UP

REGISTERS

ANTI-TAPING

CONTROL

CLOSED

CAPTION

I²C INTERFACE

RESETB

TTXDATA

TTXREQ

G/Y

9 BIT

DAC

TELETEXT

SHAPING

FILTER

TELETEXT

CONTROL

YCrCb to

RGB

YCrCb

B/CVBS2

9 BIT

DAC

MUX

YCrCb

YUV

R/C

INPUT

DEMUX

INTERPOLATING

FILTERS

9 BIT

DAC

PD7-0

SYNC

INSERT

CVBS1

9 BIT

DAC

PXCK

VIDEO TIMING GENERATOR

REFSQ

HSYNC

VSYNC

FC0-2

MODULATOR

DAC

REF

RREF

VREF

COMPSYNC

CLAMP

DIGITAL

COLOUR SUBCARRIER

GENERATOR

SCSYNC

PHASE COMP

PALID

DACCOMP

Figure 2 Functional block diagram

Peak Glitch Area = H x W/2

T(ps)

The glitch energy is calculated by measuring the area under the voltage

time curve for any LSB step, typically specified in picoVolt-seconds (pV-s)

Figure 3 Glitch Energy (see Peak Glitch Energy in table on page 2)

VP5313/VP5513

REGISTERS MAP

See Register Details for further explanations.

ADDRESS REGISTER

DEFAULT

hex

NAME

hex

R/W

BAR

RA4

ID14

ID0C

ID04

REV4

DACCFG

RA3

ID13

ID0B

ID03

REV3

VFS1

RA7

ID17

ID0F

ID07

REV7

RA6

ID16

ID0E

ID06

REV6

RA5

ID15

ID0D

ID05

REV5

RA2

ID12

ID0A

ID02

REV2

VFS0

RA1

ID11

ID09

ID01

REV1

SYNCM1

RA0

ID10

ID08

ID00

REV0

SYNCM0

13-1F

20-33

34-3F

48-4F

PART ID2

PART ID1

PART ID0

REV ID

MODE

R/W

GCR

VOCR

RSTCTL

SC_ADJ

FREQ2

FREQ1

FREQ0

SCHPHM

SCHPHL

HSOFFL

HSOFFM

FSC4SEL GENDITH GENLKEN NOLOCK PALIDEN YCDELAY CLMPDIS CVBSCLMP

DITHEN CHRMCLIP CHRBW SYNCDIS BURDIS

LUMDIS

CHRDIS

PEDEN

TSURST

SC0

FR10

FR08

SC7

FR17

FR0F

FR07

SC6

FR16

FR0E

FR06

SC5

FR15

FR0D

FR05

SC4

FR14

FR0C

FR04

SC3

FR13

FR0B

FR03

SC2

FR12

FR0A

FR02

SC1

FR11

FR09

FR01

FR00

SCH8

SCH7

HSOFF7

SCH6

SCH5

SCH4

SCH3

HSOFF3

SL_HS1

HCNT3

SCH2

HSOFF2

SL_HS0

HCNT2

SCH1

HSOFF1

HSOFF9

HCNT9

HCNT1

TTXPAT

SCH0

HSOFF6 HSOFF5 HSOFF4

HSOFF0

HSOFF8

HCNT8

HCNT0

RAMPEN

SLAVE1 NCORSTD VBITDIS VSMODE F_SWAP

SLAVE2

TSTPAT

Not used

Reserved

Not used

TTXLO2

TTXLO1

TTXLO0

TTXLE2

TTXLE1

TTXLE0

TTXDD

TTXCTL

Not used

CCREG1

CCREG2

CCREG3

CCREG4

CC_CTL

Not used

IICEXCTL

IICEXW/R

Not used

Reserved

HCNT4

HCNT7

HCNT6

HCNT5

L14

L22

L13

L21

L10

L18

L17

L16

L319

L321

L329

TTXDD1

L15

L318

L320

L328

TTXDD0

TTXEN

R/W

L12

L20

L325

L333

L11

L19

L324

L332

L327

L335

TTXDD7

L326

L334

TTXDD6

L323

L331

TTXDD3

L322

L330

TTXDD2

TTXDD5 TTXDD4

F1W1D6 F1W1D5 F1W1D4

F1W2D6 F1W2D5 F1W2D4

F2W1D6 F2W1D5 F2W1D4

F2W2D6 F2W2D5 F2W2D4

F1W1D3

F1W2D3

F2W1D3

F2W2D3

F2ST

F1W1D2

F1W2D2

F2W1D2

F2W2D2

F1ST

F1W1D1

F1W2D1

F2W1D1

F2W2D1

F2EN

F1W1D3

F1W2D3

F2W1D3

F2W2D3

F1EN

R/W

55-5F

62-FD

FE-FF

CTL7

CTL6

CTL5

CTL4

CTL3

CTL2

CTL1

CTL0

R/W

W/RD7

W/RD6

W/RD5

W/RD4

W/RD3

W/RD2

W/RD1

W/RD0

Table.1 Register map

VP5313/VP5513

YCDELAY

Add delay to luma channel

Luma to Chroma delay, 0ns

Luma to Chroma delay, 37ns

BAR

RA7-0

Base register

CLAMPDIS

CLAMP O/P select

CLAMP O/P enabled

CLAMP O/P disabled

PART ID 2-0

ID17-00

Part number

Chip part ID number

REV ID

Revision number

REV7-0

Chip revision ID number

CVBSCLAMP Composite clamp enable

MODE

DACCFG

Mode Control

CVBS Clamp disabled

Clamps CVBS output, to prevent out of

range DAC codes.

R,G,B & CVBS analog outputs

Y,C, CVBS1 & CVBS2 analog outputs

VFS1

VFS0

Video Standard

PAL-B,D,G,H,I,N(Arg.)

NTSC

Reserved

VOCR

Video Output Control

Luma dither enable

Normal operation

DITHEREN

Luma dither enabled

SYNCM1 SYNCM0 Sync mode

CHRMCLIP

Chroma clipping select

No chroma clipping

Slave, Rec. 656

Slave H & V I/P

Master H & V O/P

Reserved

Enable clipping of chroma data when

luma is clipped

GCR

FSC4SEL

Global Control

Input subcarrier frequency select

CHRBW

Chroma bandwidth select

±650kHz

REFSQ I/P = Fsubcarrier

SCSYNC I/P ignored

±1·3MHz

REFSQ I/P = 4 x Fsubcarrier

When SCSYNC I/P is asserted the

REFSQ I/P divide by 4 is reset

SYNCDIS

Sync disable (in CVBS signal)

Normal operation

Sync disabled

GENDITH

Genlock dither addition control

No dither added

(COMPSYNC O/P is not affected)

Dither added

BURDIS

Chroma burst disable

Normal operation

GENLKEN

Genlock enable control

Chroma burst disabled

Internal subcarrier generation

When high, enable Genlock to REFSQ

LUMDIS

Luma input disable - force black level

Normal operation

NOLOCK

Genlock status bit (read only)

Genlocked

Luma disabled

Cannot lock to REFSQ.

This bit is cleared by reading and set

again if lock cannot be attained.

CHRDIS

Chroma input disable - force monochrome

Normal operation

Chroma disabled

PALIDEN

PAL Ident select

PEDEN

Pedestal (set-up) select

Valid for NTSC

Normal operation, internal PAL switch

is used.

Pedestal disabled

Enables PALID input, a phase control

an for PALID signal, (0 = +135°, 1 = -135°)

7·5 IRE pedestal on lines

23-262 and 286-525

VP5313/VP5513

RSTCTL

Reset Data Control

Soft reset control

Normal operation

Chip soft reset

TSTPAT

Test Pattern Register

TSURST

TTX_PAT

Teletext test pattern enable

Normal operation

Teletext test pattern enabled

SC_ADJ

SC7-0

Sub Carrier Adjust

Sub carrier frequency seed value.

RAMPEN

Modulated test ramp enable

Normal operation

Modulated test ramp enabled

FREQ2-0

Sub carrier frequency

FR17-00

24 bit Sub carrier frequency programmed via

I²C bus. FREQ3 is the MSB.

TTXLO2-0

Teletext Odd Line Enable

L6-22

1 = Teletext Enabled on that line number

SCHPHM-L

Sub carrier phase offset

SCH8-0

9 bit Sub carrier phase relative to the 50%

point of the leading edge of the horizontal

part of composite sync. SCHPHM bit 0 is the

MSB.

TTXLE2-0

L318-335

Teletext Even Line Enable

1 = Teletext Enabled on that line number

TTXDD7-0

Teletext Request Pulse Position

HSOFFL-M

HSOFF9-0

Horizontal Sync Output Offset

TTXCTL

TTXEN

Teletext Control

Teletext enable

This is a 10 bit number which allows the user

to offset the start of digital data input with

reference to the pulse HS.

Teletext disabled

Teletext enabled

SLAVE1-2

H & V Slave Mode Control

CCREG1

F1W1D6-0

Closed Caption register 1

Field one (line 21), first data byte

NCORSTD

NCO line reset disable

NCO is always reset at end of 4(8)

field sequence in NTSC(PAL) regardless

of the value of this control bit

CCREG2

F1W2D6-0

Closed Caption register 2

Field one (line 21), second data byte

NCO is reset every line in NTSC mode

NCO line reset is disabled

CCREG3

Closed Caption register 3

F2W2D6-0

Field two (line 284), first data byte

VBITDIS

Ignore REC656 V-bit select

CCREG4

F2W2D6-0

Closed Caption register 4

Field two (line 284), second data byte

REC656 V-bit will be decoded and the

line blanked accordingly

REC656 V-bit will be ignored

CCCTL

Closed Caption control register

F1ST

Field one (line 21) status bit

VSMODE

Select type of Vsync input

Standard Vsync I/P

New data has been loaded to CCREG1-2

Data has been encoded

Field even/odd Vsync I/P

F2ST

Field one (line 284) status bit

New data has been loaded to CCREG3-4

Data has been encoded

F_SWAP

Invert field detect decision

Standard relationship applies

Inverted relationship applies

F1EN

Closed Caption field one (line 21)

SL_HS(1:0)

Internal Hsync delay control

No internal delay

Disabled

Enabled

1 x 27MHz cycle delay

2 x 27MHz cycle delay

3 x 27MHz cycle delay

F2EN

Closed Caption field one (line 284)

Disabled

Enabled

TSLAVE2

HCNT(9:0)-InternalHcounterisresettothis

value on falling edge of Hsync input.

VP5313/VP5513

IICEXCTL

CTL7-0

I²C Extension Control

Each bit controls port direction

0 = output 1 = input

The V bit within REC656 defines the video blanking when

in TRS slave mode. By setting VBITDIS in the SLAVE1

mode the V bit is ignored; hence, if any lines are required to be

blank, they must have no video signal input on them.

IICEXR/W

RD7-0

I²C Extension Control

I²C bus read and write data from

I²C extension port

Interpolator

The luminance and chrominance data is separately

passed through interpolating filters to produce output

sampling rates double that of the incoming pixel rate. This

reduces the sinx/x distortion that is inherent in the digital to

analog converters (DACs), and also simplifies the analog

reconstruction filter requirements.

I²C BUS CONTROL INTERFACE

I²C bus address

R/ W

Digital to Analog Converters

The VP5313/VP5513 contains four 9 bit digital to analog

converters which produce the analog video signals. The

DACs use a current steering architecture in which bit currents

are routed to one of two outputs; thus the DAC has true and

complimentary outputs, however, only the true outputs are

available on the pins. The use of identical current sources and

current steering their outputs means that monoticity is

guaranteed. An on-chip voltage reference of 1·00V (typ.)

provides the necessary biasing; if required, this can be

overridden by an external reference.

The full-scale output currents of the DACs is set by an

external730Ω resistorbetweentheRREFandAGNDpins. An

on-chip loop amplifier stabilises the full-scale output current

against temperature and power supply variations.

By digitally summing the luma and chroma outputs a

composite output is generated. The analog outputs of the

VP5313/VP5513 are capable of directly driving doubly

terminated 75Ω co-axial cable. If it is required only to drive a

single 75Ω load then the DACGAIN resistor is simply doubled.

Theserialmicroprocessorinterfaceisviathebi-directional

port consisting of a data (SDA) and a clock (SCL) line. It is

compatible to the Philips I²C bus standard (Jan. 1992

publication number 9398 393 40011). The interface is a slave

transmitter - receiver with a sub-address capability. All

communication is controlled by the microprocessor. The SCL

line is input only. The most significant bit (MSB) is sent first.

Data must be stable during SCL high periods.

A bus free state is indicated by both SDA and SCL lines

being high. START of transmission is indicated by SDA being

pulledlowwhileSCLishigh. Theendoftransmission, referred

to as a STOP, is indicated by SDA going from low to high while

SCL is high. The STOP state can be omitted if a repeated

START is sent after the acknowledge bit. The reading device

acknowledges each byte by pulling the SDA line low on the

ninth clock pulse, after which the SDA line is released to allow

the transmitting device access to the bus.

The device address can be partially programmed by the

setting of the pin SA. This allows the device to respond to one

of two addresses, providing for system flexibility. The I²C bus

address is seven bits long with the last bit indicating read/write

for subsequent bytes.

Thefirstdatabytesentafterthedeviceaddress,isthesub-

address - BAR (base address register). The next byte will be

written to the register addressed by BAR and subsequent

bytes to the succeeding registers. The BAR maintains its data

after a STOP signal.

Luminance, Chrominance and Composite Video Outputs

The Luminance video output drives a 37.5Ω load at 1·0V,

sync tip to peak white. It contains only the luminance content

of the image plus the composite sync pulses. In the NTSC

mode, a set-up level offset is added during the active video

portion of the raster.

The Chrominance video output drives a 37.5Ω load at

levels proportional in amplitude to the luma output (40 IRE pk-

pk burst). Burst is injected with the appropriate timing relative

to the luma signal.

NTSC/PAL Video Standards

Both NTSC (4-field, 525 lines) and PAL (8-field, 625 lines)

video standards are supported by the VP5313/VP5513. All

raster synchronisation, colour sub-carrier and burst charac-

teristics are adapted to the standard selected. The VP5313/

VP5513 generates outputs which follow the requirements of

SMPTE 170M and CCIR 624 for PAL signals.

Output sinx/x compensation filters are required on all

videooutputs,asshowninthetypicalapplicationdiagram,see

fig. 11 & 12.

RGB Video Outputs

The RGB video outputs drive a 37.5Ω load at 0.7V blank

to peak.

The device supports the following standards:

PAL B, D, G, H, I, N (Argentina) (default state) and

NTSC.

Output sinx/x compensation filters are required on all

videooutputs,asshowninthetypicalapplicationdiagram,see

fig. 11 & 12.

Video Blanking

Video Timing - Slave sync mode

The VP5313/VP5513 automatically performs standard

composite video blanking. Lines 1-9, 264-272 inclusive, as

well as the last half of line 263 are blanked in NTSC mode. In

PAL mode, lines 1-5, 311-318, 624-625 inclusive, as well as

the last half of line 623 are blanked.

The VP5313/VP5513 has an internal timing generator

which produces video timing signals appropriate to the mode

of operation. TRS slave mode means that the video encoder

synchronises itself to the TRS (Timing Reference Signal)

codesthatareembeddedintotheRec.656datapattern.Inthe

VP5313/VP5513

default(powerup)theTRSslavemodeisselected. Allinternal

timing signals are derived from the input clock, (PXCK) this

must be derived from a crystal controlled oscillator. Input pixel

data is latched on the rising edge of the PXCK clock.

Thevideotiminggeneratorproducestheinternalblankingand

burst gate pulses, together with the composite sync output

signal.

H&V slave mode is enabled by setting the SYNCM1-0 bits

in the MODE register to 01. In this mode the position of the

video syncs is derived from the HS and VS inputs. These HS

and VS pins are automatically configured as inputs.

Two data bytes per field are loaded via I²C bus registers

CCREG1-4. Each field can be independently enabled by

programmingtheenablebitsinthecontrolregister(CC_CTL).

The data is cleared to zero in the Closed Caption shift

registers after it has been encoded by the VP5313/VP5513.

Two status bit are provided (in CC_CTL), which are set high

when data is written to the registers and set low when the data

has been encoded on the Luma signal. The data is cleared to

zero in the Closed Caption shift registers after it has been

encoded by the VP5313/VP5513. The next data bytes must

be written to the registers when the status bit goes high,

otherwise the Closed Caption data output will contain Null

characters. If a transmission slot is missed (ie. no data

received) the encoder will send Null characters. Null

characters are invisible to a closed caption reciever. The MSB

(bit 7) is the parity bit and is automatically added by the

encoder.

Video Timing - Master sync mode

When SYNCM1-0 of the MODE register are 10, the

VP5313/VP5513 operates in a MASTER sync mode, all

REC656 timing reference codes are ignored with VS, HS and

FC0-2 outputs providing synchronisation signals to an

external (MPEG) device. The PXCK signal is, however, still

used to generate all internal clocks. In master mode the

direction setting of bits 4 - 0 of the IICEXCTL register are

ignored.

VS is the start of the field sync datum in the middle of the

equalisation pulses. HS is the line sync which is used by the

preceding MPEG2 decoder to define when to output digital

video data to the VP5313/VP5513. The position of the falling

edge of HS relative to the first data Cb0, can be programmed

in HSOFFM-L registers, see figure 5.

Teletext

The Teletext function within the VP5313/VP5513 co-

ordinates the insertion of teletext serial data into the

luminancedatastreamandsubsequentlythecompositevideo

data stream.

The serial data is filtered prior to insertion to minimise the

highfrequencycomponentsandtoreducethejitterinherentin

the digital data stream.

Genlock using REFSQ input

Thelinesinwhichteletextdataareinsertedareindividually

programmable for both even and odd fields. The insertion of

teletext data will only be enabled if the format of the composite

video is configured to be PAL-B,G,H,I,N and the teletext

enable bit TTXEN is asserted.

The VP5313/VP5513 can be Genlocked to another video

source by setting GENLKEN high (in GCR register) and

feeding a phase coherent sub carrier frequency signal into

REFSQ. Under normal circumstances, REFSQ will be the

samefrequencyasthesubcarrier;howeverifFSC4SELisset

high (in GCR register), a 4 x sub carrier frequency signal may

be input to REFSQ. In this case, the Genlock circuit can be

reset to the required phase of REFSQ, by supplying a pulse

to SCSYNC. The frequency of SCSYNC can be at the sub

carrier frequency, once per line or once per field could be

adequate, depending on the application. When GENLKEN is

set high, the direction setting of bit 5 of the IICEXCTL register

is ignored.

For test purposes, the teletext function incorporates

control logic to generate a serial clock cracker pattern in place

of the normal teletext data. This test pattern is enabled when

the TTX_PAT bit is asserted. There is no row coding used so

it will not display on a TV.

The VP5313/VP5513 teletext interface comprises of a

teletext request output, TTX_REQ, and a serial data input,

TTX_DATA.

PALID input

WhenusingPALandGenlockmode;theVP5313/VP5513

requires a PAL phase identification signal, to define the

correct phase on every line. This is supplied to PALID input,

High = -135° and low = +135°. The signal is asynchronous,

and should by changed before the sub carrier burst signal.

PALID input is enabled by setting PALIDEN high (in GCR

bit 7 of the IICEXCTL register is ignored.

To ensure that the composite video timing requirements

are satisfied, the serial data must be received at a specific

point in time during lines containing teletext data. The teletext

request output, TTX_REQ, will be asserted to indicate when

datamustbeappliedtoTTX_DATA, whichmustbegenerated

synchronoustotherisingedgesofPXCK. TheTTX_REQmay

be advanced in multiples of PXCK, to compensate for the

latency within the source device, by writing to the TTXDD

Line 21 coding

Two bytes of data are coded on the line 21 of each field,

see figure 8. In the NTSC Closed Caption service, the default

state is to code on line 21 of field one only. An additional

service can also be provided using line 21 (284) of the second

field. The data is coded as NRZ with odd parity, after a clock

run-in and framing code. The clock run-in frequency =

0.5034965MHz which is related to the nominal line period, D

= H / 32.

The serial teletext data which is applied to the TTX_DATA

input must obey the sequence defined below.

The teletext bit rate is defined to be 6.9375 MHz, which

equates to 444 times the PAL line frequency (15.625 kHz). It

is clear that for a 27 MHz system clock, a constant bit period

cannot be achieved.

D = 63.55555556 / 32µs

VP5313/VP5513

have a duration of 3 CLK27M cycles. The sequence will be

repeated for all subsequent 37 bit groups.

The horizontal line duration for PAL equates to 1728

CLK27M cycles and within each line there are 444 data bit

periods. The duration of 37 data bits (the smallest number

possible for an integer number of CLK27M cycles) therefore

equates to 144 CLK27M cycles.

Master Reset

TheVP5313/VP5513mustbeinitialisedwithRESET. This

is an asynchronous, active low signal and must be active for

a minimum of 200ns in order to reset the VP5313/VP5513.

The device resets to line 64, start of horizontal sync (i.e. line

blanking active). There is no on-chip power on reset circuitry.

To ensure that the average bit rate is 6.9375 MHz, 33 in

every37databitswillhaveadurationof4CLK27Mcyclesand

4inevery37databitswillhaveadurationof3CLK27Mcycles.

Of the first 37 data bits in each line, bits 10, 19, 28 and 37 will

CVBS/Y

textbit #:

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

TTX_DATA

TTX_REQ

TTXDD

Figure 4 Teletext timing diagram

Number of Horizontal Subcarrier

NCO Adjustment

SC_ADJ

hex

fSC/fH

Standard

Field

freq. HZ

59.94

FREQ2-0

registers hex

87 C1 F1

Lines/

field

525

pixels/line freq. kHz.

freq. kHz.

f^SC

at 27MHz

f^H

15.734266

NTSC

1716

(455/2)

3.57954545

15.625000

PAL-B, G, H, I (d)

PAL-N (Argentina)

1728

(1135/4+1/625)

(917/4+1/625)

A8 26 2B

625

4.43361875

3.58205625

87 DA 51

625

Table.2 Line, field and subcarrier standards and register settings

(d) = default

xx = don’t care.

The calculation of the FREQ register value is according to the following formula:-

FREQ = 2²⁶x fSC/PXCK hex, where PXCK = 27.00MHz

NTSC value is rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN. The SC_ADJ

value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier frequency. Note the

SC_ADJ value of 9C required for PAL-B, D, G, H, I.

PXCK Input (27MHz)

SU; PD

HD; PD

Nck=2

Nck=0

Cb0 Y0 Cr0

Y1 Cb1 Y2 Cr1

Pixel Data Input (PD[7,0])

Figure 5 REC 656 interface with HS output timing

VP5313/VP5513

2:1 mux

REFSQ

Divide by 4

Synchronous

Counter

Input to

Genlocking

Block

RESET

FSC4_SEL

SC_SYNC

REFSQ

(register bit)

SC_SYNC

1/ f

PWH; SC_SYNC

SU; SC_SYNC

HD; SC_SYNC

SC_SYNC

Figure 6 REFSQ and SC_SYNC input timing

Pixel Data Input (PD[7,0\)

Sample Number

1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450

Y719 $FF $00 $00 $XY

ANCILLARY DATA...

EAV SEQUENCE

SU; PD

HD; PD

PWL; PXCK

PWH; PXCK

PXCK Input (27MHz)

DUR; PAL_ID

SU; PAL_ID

HD; PAL_ID

PAL_ID Stable

Input (PAL_ID)

Figure 7 PAL_ID input timing

VP5313/VP5513

TIMING INFORMATION

Symbol

Conditions

Parameters

Master clock frequency (PXCK input)

PXCK pulse width, HIGH

PXCK pulse width, LOW

PXCK rise time

Typ.

Min.

Max.

Units

MHz

f^PXCK

tPWH; PXCK

tPWL; PXCK

tRP

27.0

14.5

TBD

10% to 90% points

90% to 10% points

tFP

PXCK fall time

PD7-0 set up time

tSU;PD

PD7-0 hold time

tHD;PD

tSU;SC_SYNC

tHD;SC_SYNC

tSU;PAL_ID

tHD;PAL_ID

tDUR;PAL_ID

SCSYNC set up time

SCSYNC hold time

PALID set up time

PALID hold time

PALID duration

PXCK

periods

tDOS

Output delay

PXCK to COMPSYNC

PXCK to CLAMP

Note: Timing reference points are at the 50% level. Digital CLOAD <40pF.

C D

START BITS

CLOCK RUN-IN

HSYNC COLOUR BURST

DATA BYTE 1

DATA BYTE 2

BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

S1 S2 S3

-40

0 0 0 0 1 1

IRE

FRAME CODE

P = Parity Bit

Figure 8 Closed Capation format

VP5313/VP5513

Encoder minimum

Encoder nominal

Encoder maximum

Interval

Description

H-sync to clock run-in

Clock run-in^{2, 3}

Clock run-in to third start bit ³

Data bit ^{1, 3}

Data characters ⁴

Horizontal line ¹

Rise / fall time of data bit transitions ⁵

10.250µs

10.500µs

6.5D (12.910µs)

2.0D (3.972µs)

1.0D (1.986µs)

16.0D (31.778µs)

32.0D (63.556)

0.240µs

10.750µs

0.288µs

Data bit high (logic level one) ⁶

Clock run-in maximum

Data bit low (logic level zero) ⁶

Clock run-in minimum

48 IRE

0 IRE

50 IRE

52 IRE

0 IRE

2 IRE

48 IRE

Data bit differential (high - low)

50 IRE

52 IRE

Clock run-in differential (max. - min)

Table. 5 Closed Caption data timing. (source EIA R - 4.3 Sept 16 1992)

Notes

1. The Horizontal line frequency f is nominally 15734.26Hz ±0.05Hz. Interval D shall be adjusted to D = 1/(f x 32) for the

instantaneous f at line 21.

2. The clock run-in signal consists of 7.0 cycles of a 0.5034965MHz (1/D) sine wave when measured from the leading to trailing

0 IRE points. The sine wave is to be symmetrical about the 25 IRE level.

3. The negative going midpoints (half amplitude) of the clock run-in shall be coherent with the midpoints (half amplitude) of the

Start and Data bit transitions.

4. Two characters, each consisting of 7 data bits and 1 odd parity bit.

5. 2 T Bar, measured between the 10% and 90% amplitude points.

6. The clock run-in maximum level shall not differ from the data bit high level by more than ±1 IRE. The clock run-in minimum

level shall not differ from the data bit low level by more than ±1 IRE.

VP5313/VP5513

Frequency Response Luma in RGB Path

5e+6 7.5e+6

2.5e+6

10e+6

12e+6

-20

-40

-60

2.5e+6

5e+6

7.5e+6

Frequency in Hz

10e+6

12e+6

Figure 9 Luma filter for RGB datapath

Frequency Response of Cr and Cb in RGB Path

2.5e+6

5e+6

7.5e+6

10e+6

12e+6

-20

-40

-60

-80

2.5e+6

5e+6

7.5e+6

Frequency in Hz

10e+6

12e+6

Figure 10 Chroma filter for RGB datapath

VP5313/VP5513

FERRITE

BEAD

VDD

GND

+5V

AT EVERY

VDD PIN

10nF

100µF

2k2Ω

VDD, AVDD

OUTPUT

FILTER

SCL

SDA

I²C

GREEN/LUMA

BLUE/CVBS

SCL

G/Y

SDA

BUS

OUTPUT

FILTER

B/CVBS2

DIGITAL

VIDEO

PD0-7

TELETEXT

OUTPUT

FILTER

TTXDATA

R/C

RED/CHROMA

CVBS

INTERFACE

TTXREQ

PXCK

SYSTEM

CLOCK

OUTPUT

FILTER

CVBS1

RESET

100nF

730Ω

DAC

COMP

+5V

SYNC

INTERFACE

RREF

VREF

100nF

GND, AGND

GND

Figure 11 Typical application diagram. (Output filter - see Fig.12)

to drive 37.5ohms

15pF

1.0µH

EXT

75Ω

470pF

220pF

75Ω

GND

Figure 12 Output reconstruction filter

VP5313/VP5513

Note:

The VP5313 is only available to customers with a valid and existing authorisation to purchase issued by MACROVISION

CORPORATION.

This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of

the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial, home and limited exhibition uses

only. Reverse engineering or disassembly is prohibited.

For more information about all Zarlink products

visit our Web Site at

www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.

However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such

information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or

use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual

property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in

certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part

of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other

information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the

capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute

any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and

suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does

not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in

significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink’s I²C components conveys a licence under the Philips I²C Patent rights to use these components in and I²C System, provided that the system

conforms to the I²C Standard Specification as defined by Philips.

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TECHNICAL DOCUMENTATION - NOT FOR RESALE

VP5513 [ZARLINK]

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