ZL10312 [ZARLINK]
Satellite Demodulator; 卫星解调器
| 型号： | ZL10312 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Satellite Demodulator |
| 文件： | 总15页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL10312
Satellite Demodulator
Data Sheet
November 2004
Features
•
Conforms to EBU specification for DVB-S and
DirecTV specification for DSS
Ordering Information
ZL10312QCG
ZL10312QCF
ZL10312QCG1
ZL10312UBH
64 Pin LQFP
64 Pin LQFP
Trays, Bake & Drypack
Tape & Reel
•
On-chip digital filtering supports 1 - 45 MSps
symbol rates
64 Pin LQFP* Trays, Bake & Drypack
Die supplied in wafer form**
•
•
On-chip 60 or 90 MHz dual-ADC
*Pb Free Matte Tin
**Please contact Sales for further details
High speed scanning mode for blind symbol
rate/code rate acquisition
0°C to +70°C
•
•
Automatic spectral inversion resolution
Description
High level software interface for minimum
development time
The ZL10312 is
a
QPSK/BPSK 1 - 45 MSps
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification. It receives analogue
I and Q signals from the tuner, digitises and digitally
demodulates this signal, and implements the complete
DVB/DSS FEC (Forward Error Correction), and de-
scrambling function. The output is in the form of
MPEG2 or DSS transport stream data packets. The
ZL10312 also provides automatic gain control to the RF
front-end device.
•
•
Up to ±22 MHz LNB frequency tracking
DiSEqC™ v2.2: receive/transmit for full control of
LNB, dish and other components
•
•
Compact 64 pin LQFP package (7 x 7 mm)
Sleep pin gives ~1,000 fold reduction in power to
help products meet ENERGY STAR®
requirements
Applications
The ZL10312 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required to
control the ZL10312 because of the built in automatic
search and decode control functions.
•
•
•
DVB 1 - 45 MSps compliant satellite receiver
DSS 20 MSps compliant satellite receivers
SMATV trans-modulators. (Single Master
Antenna TV)
•
Satellite PC applications
MPEG/
DSS
I I/P
DVB
DSS
FEC
Packets
Timing recovery
Matched filter
Decimation
Filtering
Dual ADC
De-rotator
Phase recovery
Q I/P
Bus I/O
Analog
AGC
Acquisition
Control
2-Wire Bus
Interface
Clock Generation
Control
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL10312
Data Sheet
Figure 2 - ZL10312 Pin Allocation
Pin Table
No.
Name
No.
Name
No.
Name
No.
Name
1
2
Reset
DiSEqC[2]
DiSEqC[1]
DiSEqC[0]
Vdd
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CVdd
Gnd
XTI
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Gnd
CVdd
Addr[1]
Addr[2]
Addr[3]
Addr[4]
Vdd
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MDO[1]
CVdd
3
Gnd
4
XTO
Gnd
CVdd
Gnd
Iin
MDO[2]
MDO[3]
Gnd
5
6
Gnd
7
CVdd
Vdd
8
Gnd
Gnd
MDO[4]
MDO[5]
Gnd
9
Sleep
Iin
AGC
10
11
12
13
14
15
16
CLK1
Gnd
Vdd
Gnd
Qin
Test
DATA1
CVdd
IRQ
CVdd
CVdd
Gnd
MDO[6]
MDO[7]
MOCLK
BKERR
Status
Gnd
DATA2
CLK2
Qin
MOSTRT
MOVAL
MDO[0]
Gnd
CVdd
OscMode
Note: All supply pins must be connected as they are not all commoned internally.
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Zarlink Semiconductor Inc.
ZL10312
Data Sheet
Table of Contents
1.0 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Analogue-to-Digital Converter and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 QPSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Forward Error Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 ZL10312 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7 Alphabetical Listing of Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Zarlink Semiconductor Inc.
ZL10312
Data Sheet
Overview
The ZL10312 is a QPSK/BPSK 1 - 45 MSps demodulator and channel decoder for digital satellite television
transmissions compliant to both DVB-S and DSS standards and other systems.
A Command Driven Control (CDC) system is provided making the ZL10312 very simple to program. After the tuner
has been programmed to the required frequency to acquire a DVB transmission, the ZL10312 requires a minimum
of five registers to be written.
The ZL10312 provides a monitor of Bit Error Rate after the QPSK module and also after the Viterbi module. For
receiver installation, a high speed scan or 'blind search' mode is available. This allows all signals from a given
satellite to be evaluated for frequency, symbol rate and convolutional coding scheme. The phase of the IQ signals
can be automatically determined.
Full DiSEqC v2.x is provided for both writing and reading DiSEqC messages. Storage in registers for up to eight
data bytes sent and eight data bytes received is provided.
Additional Features
De-Interleaver
•
2-wire bus microprocessor interface with
separate interface to tuner
•
Compliant with DVB and DSS standards
Reed Solomon
•
•
All digital clock and carrier recovery
On-chip PLL clock generation using low cost 10
to 16 MHz crystal
•
•
(204, 188) for DVB and (146,130) for DSS
Reed Solomon bit-error-rate monitor to indicate
Viterbi performance
•
Low power operation, with stand-by and sleep
modes
•
•
•
•
3.3 V operation with 1.8 V for core logic
7 x 7mm 64 pin LQFP package
De-Scrambler
•
EBU specification de-scrambler for DVB mode
Low external component count
Outputs
Commercial temperature range 0 to 70°C
•
•
MPEG transport parallel & serial output
Demodulator
Integrated MPEG2 TEI bit processing for DVB
only
•
•
BPSK or QPSK programmable
Optional fast acquisition mode for low symbol
rates
Application Support
•
•
•
•
Design Manual
Viterbi
Channel decoder system evaluation board
Windows based evaluation software
ANSI-C generic software
•
Programmable decoder rates 1/2, 2/3, 3/4, 5/6,
6/7, 7/8
•
•
•
•
Automatic spectral inversion resolution
Constraint length k=7
Trace back depth 128
Extensive SNR and BER monitors
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Zarlink Semiconductor Inc.
ZL10312
Data Sheet
Figure 3 - Typical Application Schematic
5
Zarlink Semiconductor Inc.
ZL10312
Data Sheet
1.0 Functional Overview
1.1 Introduction
ZL10312 is a single-chip variable rate digital QPSK/BPSK satellite demodulator and channel decoder. The
ZL10312 accepts base-band in-phase and quadrature analogue signals and delivers an MPEG or DSS packet data
stream. Digital filtering in ZL10312 removes the need for programmable external anti-alias filtering for all symbol
rates from 1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to the
analogue front-end is for automatic gain control. The digital phase recovery loop enables very fine bandwidth
control that is needed to overcome performance degradation due to phase and thermal noise.
All acquisition algorithms are built into the ZL10312 controller. The ZL10312 can be operated in a Command Driven
Control (CDC) mode by specifying the symbol rate and Viterbi code rate. There is also a provision for a search for
unknown symbol rates and Viterbi code rates.
1.2 Analogue-to-Digital Converter and PLL
The A/D converters sample single-ended or differential analogue inputs and consist of a dual ADC and circuitry to
provide improved SiNaD (Signal-Noise and Distortion) and channel matching.
The fixed rate sampling clock is provided on-chip using a programmable PLL needing only a low cost 10 to 16 MHz
crystal. Different crystal frequencies can be combined with different PLL ratios, depending on the maximum symbol
rate, allowing a very flexible approach to clock generation. An external clock signal in the range 4 to 16 MHz can
also be used as the master clock.
1.3 QPSK Demodulator
The demodulator in the ZL10312 consists of signal amplitude offset compensation, frequency offset compensation,
decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous
operation from 2Mbits/s to 90Mbits/s allowing one receiver to cover the needs of the consumer market as well as
the single carrier per channel (SCPC) market with the same components without compromising performance, that
is, the channel reception is within 0.5dB of theoretical. For a given symbol rate, control algorithms on the chip
detect the number of decimation stages needed and switch them in automatically.
The frequency offset compensation circuitry is capable of tracking out up to ±22.5 MHz frequency offset. This
allows the system to cope with relatively large frequency uncertainties introduced by the Low Noise Block (LNB).
Full control of the LNB is provided by the DiSEqC outputs from the ZL10312. Horizontal/vertical polarisation and an
instruction modulated 22kHz signal are available under register control. All DiSEqC v2.x functions are implemented
on the ZL10312. An internal state machine that handles all the demodulator functions controls the signal acquisition
and tracking. Various pre-set modes are available as well as blind acquisition where the receiver has no prior
knowledge of the received signal. Fast acquisition algorithms have been provided for low symbol rate applications.
Full interactive control of the acquisition function is possible for debug purposes. In the event of a signal fade or a
cycle slip, the QPSK demodulator allows sufficient time for the FEC to re-acquire lock, for example, via a phase
rotation in the Viterbi decoder. This is to minimise the loss of signal due to the signal fade. Only if the FEC fails to
re-acquire lock for a long period (which is programmable) would QPSK try to re-acquire the signal.
The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with DSS and DVB
standards. Although not a part of the DVB standard, ZL10312 allows a roll-off of 0.20 to be used with other DVB
parameters. An AGC signal is provided to control the signal levels in the tuner section of the receiver and ensure
the signal level fed to the ZL10312 is set at an optimal value under all reception conditions.
The ZL10312 provides comprehensive information on the input signal and the state of the various parts of the
device. This information includes signal to noise ratio (SNR), signal level, AGC lock, timing and carrier lock signals.
A maskable interrupt output is available to inform the host controller when events occur.
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Zarlink Semiconductor Inc.
ZL10312
Data Sheet
1.4 Forward Error Correction
The ZL10312 contains FEC blocks to enable error correction for DVB-S and DSS transmissions. The Viterbi
decoder block can decode the convolutional code with rates 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8. The block features
automatic synchronisation, automatic spectral inversion resolution and automatic code rate detection. The trace
back depth of 128 provides better performance at high code rates and the built-in synchronisation algorithm allows
the Viterbi decoder to lock onto signals with very poor signal-to-noise ratios. A Viterbi bit error rate monitor provides
an indication of the error rate at the QPSK output.
The 24-bit error count register in the Viterbi decoder allows the bit error rate at the output of the QPSK demodulator
to be monitored. The 24-bit bit error count register in the Reed-Solomon decoder allows the Viterbi output bit error
rate to be monitored. The 16-bit uncorrectable packet counter yields information about the output packet error rate.
These three monitors and the QPSK SNR register allow the performance of the device and its individual
components, such as the QPSK demodulator and the Viterbi decoder, to be monitored extensively by the external
microprocessor. The frame/byte align block features a sophisticated synchronisation algorithm to ensure reliable
recovery of DVB and DSS framed data streams under worst case signal conditions. The de-interleaver uses
on-chip RAM and is compatible with the DVB and DSS algorithms. The Reed-Solomon decoder is a truncated
version of the (255, 239) code. The code block size is 204 for DVB and 146 for DSS. The decoder provides a count
of the number of uncorrectable blocks as well as the number of bit errors corrected. The latter gives an indication of
the bit error rate at the output of the Viterbi decoder. In DVB mode, spectrum de-scrambling is performed
compatible with the DVB specification. The final output is a parallel or serial transport data stream; packet sync;
data clock; and a block error signal. The data clock may be inverted under software control.
2.0 Electrical Characteristics
2.1 Recommended Operating Condition
Parameter
Core power supply voltage
Symbol
Min.
Typ.
Max.
Units
CVdd
Vdd
1.71
3.13
3.99
9.99
1.8
3.3
1.89
3.47
16.01
16.01
400
V
Periphery power supply voltage
Input clock frequency (note 1)
V
Fxt1
Fxt2
Fclk1
MHz
MHz
kHz
°C
Crystal oscillator frequency
CLK1 clock frequency 2 (with 10 MHz or above)
Ambient operating temperature
0
70
1. When not using a crystal, XTI may be driven from an external source over the frequency range shown.
2. The maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100 kHz with a
4.0 MHz clock.
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Zarlink Semiconductor Inc.
ZL10312
Data Sheet
2.2 Absolute Maximum Ratings
Maximum Operating Conditions
Parameter
Symbol
Min.
-0.3
Max.
Unit
Power supply
Vdd
CVdd
Vi
+4.5
2.3
V
V
Power supply
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Voltage on input pins (5 V rated)
Voltage on input pins (3.3 V rated)
Voltage on input pins (1.8 V rated, i.e. XTI)
Voltage on output pins (5 V rated)
Voltage on output pins (3.3 V rated)
Voltage on output pins (1.8 V rated, i.e., XTO)
Storage temperature
6.5
V
Vi
Vdd + 0.5
CVdd + 0.5
5.5
V
Vi
V
Vo
V
Vo
Vdd + 0.5
CVdd + 0.5
150
V
Vo
V
Tstg
Top
Tj
-55
°C
°C
°C
kV
Operating ambient temperature
Junction temperature
0
70
125
ESD protection (human body model)
4
Note 1: Stresses exceeding these listed under 'Absolute Ratings' may induce failure. Exposure to absolute maximum ratings for
extended periods may reduce reliability. Functionality at or above these conditions is not implied.
2.3 Primary 2-Wire Bus Timing
Figure 4 - Primary 2-Wire Bus Timing
Where: S = Start
Sr = Restart, i.e. Start without stopping first.
P = Stop.
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Zarlink Semiconductor Inc.
ZL10312
Data Sheet
Value
Parameter: Primary 2-wire bus only
CLK1 clock frequency (for XTI ≥10 MHz)
Symbol
Unit
Min.
Max.
400
fCLK
to
0
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus free time between a STOP and START condition.
Hold time (repeated) START condition.
LOW period of CLK1 clock.
1300
tHD;STA 600
tLOW
tHIGH
1300
600
600
0
HIGH period of CLK1 clock.
Set-up time for a repeated START condition.
Data hold time (when input).
tSU;STA
tHD;DAT
Data set-up time
tSU;DAT 100
Rise time of both CLK1 and DATA1 signals.
Fall time of both CLK1 and DATA1 signals, (100pF to ground)
Set-up time for a STOP condition.
tR
tF
20+0.1Cb1
20+0.1Cb1
Note2
300
tSU;STO 600
Table 1 - Primary 2-wire Bus Timing
1. Cb = the total capacitance on either clock or data line in pF.
2. The rise time depends on the external bus pull up resistor and bus capacitance.
2.4 Crystal Specification
Parallel resonant fundamental frequency (preferred) 9.99 to 16.00 MHz.
Tolerance over operating temperature range ±25 ppm.
Tolerance overall ±50 ppm.
Nominal load capacitance 30 pF.
Equivalent series resistance <75 Ω
Figure 5 - Crystal Oscillator Circuit
Note: The crystal frequency should be chosen to ensure that the system clock would marginally exceed the
maximum symbol rate required, e.g. 10.111 MHz with a multiplier of x9 will give a 91 MHz system clock to
guarantee 45 MSps operation.
9
Zarlink Semiconductor Inc.
ZL10312
Data Sheet
2.5 Electrical Characteristics
DC Electrical Characteristics
Parameter
Conditions/Pin
Symbol
CVdd
Vdd
Min.
Typ.
Max.
Unit
V
Core voltage
1.71
3.13
1.8
3.3
1.89
3.47
V
Peripheral voltage
Core current
CIdd
mA
mA
mW
45 MSps CR 7/8 91 MHz system clock
160
10
216
Idd
Peripheral current
11.25
450
Ptot1
Total power
(91 MHz system
clock)
320
Ptot2
mW
Total power
(stand-by)
See Note 1
2.2
3.3
Ptot3
Vol
mW
V
Total power (sleep)
Output low level
Pin 9 = logic ‘1’. See Note 1
0.35
0.525
0.4
2, 6 or 12 mA per output (see section
2.6, ZL10312 Pinout Description)
Voh
V
Output high level
Output leakage
2, 6 or 12 mA per output
2.4
µA
Tri-state when off or open-drain when
high
±1
pF
pF
All outputs except XTO, CLK1 &
Output capacitance open-drain types. Excludes packaging
contribution (~0.35 pF)
2.7
3.3
Open-drain outputs.
Excludes packaging
contribution (~0.35 pF)
Vil
V
V
Input low level
Input high level
0.8
±1
Vih
2.0
µA
pF
Input leakage
Vin = 0 or Vdd
Input capacitance
Excludes packaging contribution
(~0.35 pF)
1.5
Note 1: To minimize the power comsumption the MPEG outputs should be tristated and the ADC turned off.
AC Electrical Characteristics
Parameter
Conditions/Pin
Min.
Typ.
Max.
Unit
ADC Full-scale input single range
(single-ended or differential)
Differential source is recommended
Vpp
0.5
1.0
ADC analog input resistance
ADC input common mode voltage level
ADC input impedance
Per input pin
kΩ
10
V
0.7
1.7
Typically 12 K in parallel with 2 pF
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Zarlink Semiconductor Inc.
ZL10312
Data Sheet
2.6 ZL10312 Pinout Description
Pin Description Table
Pin
Name
Description
I/O
Note
V
mA
1
2
Reset
Active low reset input
I
CMOS1
5
5
DiSEqC[2] DiSEqC input for level 2 control. Also usable as I/O
GPP2 (general purpose port pin) for other purposes.
Open
drain1
6
3
4
9
DiSEqC[1] Horizontal/vertical LNB control (acts as input only in I/O
production test modes)
CMOS
CMOS
CMOS
3.3
3.3
3.3
2
2
DiSEqC[0] 22 kHz output to LNB (acts as input only in I/O
production test modes)
Sleep
Stops oscillator and sets minimum power levels to
entire device (except ADCs - register controlled
power-down)
I
10
11
CLK1
Primary 2-wire serial bus clock
Primary 2-wire serial bus data
I
CMOS1
5
5
DATA1
I/O
Open
drain1
6
6
14
15
16
DATA2
CLK2
Secondary 2-wire bus data to tuner front end. Also I/O
usable as GPP1 (general purpose port pin) for other
purposes.
Open
drain1
5
Secondary 2-wire bus clock to tuner front end. Also I/O
usable as GPP0 (general purpose port pin) for other
purposes.
Open
drain1
5
6
OscMode Controls oscillator mode to suit crystal or external
signal
I
CMOS
3.3
19
20
XTI
Crystal input or external reference clock input
I
CMOS
CMOS
1.8
1.8
XTO
Crystal output, includes internal feedback resistor to
XTI
I/O
24
25
29
30
Iin
Iin
I channel input
I
I
I
I
I
analog
analog
analog
analog
CMOS
I channel negative input
Q channel negative input
Q channel input
Qin
Qin
35,36,37
38
ADDR[1:4] Primary 2-wire bus address defining pins
3.3
5
41
AGC
AGC sigma-delta output (acts as input only in
production test modes)
I/O
Open
drain1
6
42
43
Test
IRQ
For normal operation, this pin must be held at 0V.
I
CMOS
3.3
5
Active low interrupt output. Reading all active
interrupt registers resets this pin (acts as input only in
production test modes)
I/O
Open
drain1
6
2
46
MOSTRT MPEG output start signal. High during the first byte of
a packet.
O
CMOS
Tri-state
3.3
11
Zarlink Semiconductor Inc.
ZL10312
Data Sheet
Pin Description Table (continued)
Pin
Name
Description
I/O
Note
V
mA
47
MOVAL
MPEG data output valid. High during the MOCLK
cycles when valid data bytes are being output.
O
CMOS
Tri-state
3.3
2
48,49,52,
53,56,
MDO[0:7] MPEG transport packet data output bus. Can be
tri-stated under control of a register bit.
O
CMOS
Tri-state
3.3
2
57,60,61
62
63
MOCLK
BKERR
MPEG clock output at the data byte rate.
O
O
CMOS
Tri-state
3.3 12
Active low uncorrectable block indicator or no-signal
indicator. Mode selected by ERR_IND bit (#7) of the
QPSK_DIAG_CTL register (add. 0x67). Can also be
inverted.
CMOS
Tri-state
3.3
2
64
STATUS
Status output. Register defined function including I/O
audio frequency proportional to BER (acts as input
only in production test modes)
CMOS
3.3
2
5, 39, 55
27
Vdd
Vdd
Peripheral supply pins. All pins must be connected.
Peripheral supply pin used for the ADC.
3.3
3.3
1.8
7, 12, 44,
50, 59
CVdd
Core supply pins. All pins must be connected.
17, 22,
32, 34
CVdd
Gnd
PLL/ADC supply pins. All pins must be connected.
Ground supply pins. All pins must be connected.
1.8
0
6, 8, 13,
40, 45 51,
54, 58
18, 21, 23
26, 28,
Gnd
PLL/ADC ground supply pins. All pins must be
connected.
0
31, 33
Note 1: 5 V tolerant pins with thresholds related to 3.3 V.
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Zarlink Semiconductor Inc.
ZL10312
Data Sheet
2.7 Alphabetical Listing of Pin-Out
Name
Addr[1]
No.
Name
No.
Name
No.
Name
MOCLK
No.
35
36
37
38
41
63
10
15
7
CVdd
59
11
14
4
Gnd
40
45
51
54
58
24
25
43
48
49
52
53
56
57
60
61
62
46
47
16
29
30
1
Addr[2]
Addr[3]
Addr[4]
AGC
DATA1
DATA2
DiSEqC[0]
DiSEqC[1]
DiSEqC[2]
Gnd
Gnd
MOSTRT
MOVAL
OscMode
Qin
Gnd
Gnd
3
Gnd
BKERR
CLK1
CLK2
CVdd
CVdd
CVdd
CVdd
CVdd
CVdd
CVdd
CVdd
2
Iin
Qin
6
Iin
Reset
Sleep
Status
Test
Gnd
8
IRQ
9
Gnd
13
18
21
23
26
28
31
33
MDO[0]
MDO[1]
MDO[2]
MDO[3]
MDO[4]
MDO[5]
MDO[6]
MDO[7]
64
42
5
12
17
22
32
34
44
50
Gnd
Gnd
Vdd
Gnd
Vdd
27
39
55
19
20
Gnd
Vdd
Gnd
Vdd
Gnd
XTI
Gnd
XTO
3.0 Trademarks
DiSEqC™ is a trademark of EUTELSAT.
ENERGY STAR® is a registered trademark of the United States Environmental Protection Agency (EPA).
13
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