ZL30121GGG2 [ZARLINK]
SONET/SDH Low Jitter System Synchronizer; SONET / SDH的低抖动同步器系统
| 型号： | ZL30121GGG2 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | SONET/SDH Low Jitter System Synchronizer |
| 文件： | 总30页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL30121
SONET/SDH
Low Jitter System Synchronizer
Data Sheet
May 2006
A full Design Manual is available to qualified customers.
To
register,
please
send
an
email
to
Ordering Information
TimingandSync@Zarlink.com.
ZL30121GGG
100 Pin CABGA
Trays
Trays
ZL30121GGG2 100 Pin CABGA*
Features
*Pb Free Tin/Silver/Copper
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•
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Supports the requirements of Telcordia GR-253 and
GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and
the requirements of ITU-T G.781 SETS, G.813
SEC, G.823, G.824 and G.825 clocks
Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
-40oC to +85oC
•
Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
•
•
•
•
•
•
Supports master/slave configuration for
AdvancedTCATM
Programmable output synthesizers generate clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
Configurable input to output delay and output to
output phase alignment
Optional external feedback path provides dynamic
•
•
Provides two DPLLs which are independently
input to output delay compensation
configurable through a serial software interface
Provides 3 sync inputs for output frame pulse
alignment
DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover),
selectable loop bandwidth and pull-in range
Generates several styles of output frame pulses
with selectable pulse width, polarity and frequency
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Supports IEEE 1149.1 JTAG Boundary Scan
•
DPLL2 provides a comprehensive set of features
necessary for generating derived output clocks and
other general purpose clocks
•
dpll2_ref
dpll1_holdover diff0_en diff1_en
trst_b tck tdi tms tdo
dpll1_hs_en
dpll1_lock
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
osco
osci
Master
Clock
IEEE 1449.1
JTAG
P0
DPLL2
Synthesizer
ref
ref
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
P1
Synthesizer
ref7:0
diff0_p/n
diff1_p/n
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
SONET/SDH
APLL
DPLL1
sync0
sync1
sync2
sync2:0
sync
fb_clk
Feedback
fb_clk
fb_fp
ref_&_sync_status
Reference
Monitors
Synthesizer
ext_fb_fp
ext_fb_clk
Controller &
int_b
SPI Interface
State Machine
sdh_filter filter_ref0 filter_ref1
sck
si
so cs_b
rst_b slave_en dpll1_mod_sel1:0
Figure 1 - Block Diagram
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30121
Data Sheet
Applications
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•
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•
•
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AdvancedTCATM Systems
Multi-Service Edge Switches or Routers
Multi-Service Provisioning Platforms (MSPPs)
Add-Drop Multiplexers (ADMs)
Wireless/Wireline Gateways
Wireless Base Stations
DSLAM / Next Gen DLC
Core Routers
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Table of Contents
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 DPLL Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7 Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.8 External Feedback Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Automatic Mode State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 - Typical Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9 - External Feedback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
List of Tables
Table 1 - DPLL1 and DPLL2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5 - Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Pin Description
I/O
Pin #
Name
Description
Type
Input Reference
C1
B2
A3
C3
B3
B4
C4
A4
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
Id
Input References (LVCMOS, Schmitt Trigger). These are input references
available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight
input references can be automatically or manually selected using software
registers. These pins are internally pulled down to Vss.
B1
A1
A2
sync0
sync1
sync2
Id
Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).
These are the frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled down to Vss.
C5
B5
ext_fb_clk
ext_fb_fp
Id
External DPLL Feedback Clock (LVCMOS, Schmitt Trigger). External
feedback clock input. This allows DPLL1 to adjust for PCB trace propagation
delays. This pin is internally pulled down to Vss. Leave open when not is use.
Id
External DPLL Feedback Frame Pulse (LVCMOS, Schmitt Trigger). External
feedback frame pulse input. This allows DPLL1 to adjust for PCB trace
propagation delays. This pin is internally pulled down to Vss. Leave open when
not is use.
Output Clocks and Frame Pulses
D10
G10
E10
sdh_clk0
sdh_clk1
sdh_fp0
O
O
O
SONET/SDH Output Clock 0 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 77.76 MHz.
SONET/SDH Output Clock 1 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 19.44 MHz.
SONET/SDH Output Frame Pulse 0 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 8 kHz.
F10
sdh_fp1
O
SONET/SDH Output Frame Pulse 1 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 2 kHz.
K9
K7
p0_clk0
p0_clk1
O
O
Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 8.192 MHz.
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
I/O
Pin #
Name
Description
Type
K8
p0_fp0
O
O
O
O
Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
J7
p0_fp1
p1_clk0
p1_clk1
Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz
J10
K10
Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).
Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p1_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 3.088 MHz (2x DS1).
H10
E1
fb_clk
O
O
O
O
Feedback Clock (LVCMOS). This output is a buffered copy of the feedback
clock for DPLL1. The frequency of this output always equals the frequency of the
selected reference.
dpll2_ref
DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the
output of the reference selector for DPLL2. Switching between input reference
clocks at this output is not hitless.
A9
diff0_p
diff0_n
Differential Output Clock 0 (LVPECL). This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 155.52 MHz
B10
A10
B9
diff1_p
diff1_n
Differential Output Clock 1 (LVPECL). This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 622.08 MHz clock
Control
H5
rst_b
I
Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
J5
dpll1_hs_en
Iu
DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at
this input enables hitless reference switching. A logic low disables hitless
reference switching and re-aligns DPLL1’s output phase to the phase of the
selected reference input. This feature can also be controlled through software
registers. This pin is internally pulled up to Vdd.
C2 dpll1_mod_sel0
D2 dpll1_mod_sel1
Iu
DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels
on these pins determine the default mode of operation for DPLL1 (Automatic,
Normal, Holdover or Freerun). After reset, the mode of operation can be
controlled directly with these pins, or by accessing the dpll1_modesel register
(0x1F) through the serial interface. This pin is internally pulled up to Vdd.
D1
slave_en
Iu
Master/Slave control (LVCMOS, Schmitt Trigger). This pin selects the mode of
operation for the device. If set high, slave mode is selected. If set low, master
mode is selected. This feature can also be controlled through software registers.
This pin is internally pulled up to Vdd.
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
I/O
Pin #
Name
Description
Type
K1
diff0_en
Iu
Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 0 driver is enabled. When set low, the differential
driver is tristated reducing power consumption. This pin is internally pulled up to
Vdd.
D3
diff1_en
Iu
Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 1 driver is enabled. When set low, the differential
driver is tristated reducing power consumption.This pin is internally pulled up to
Vdd.
Status
H1
dpll1_lock
O
O
Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output
goes high when DPLL1’s output is frequency and phase locked to the input
reference.
J1
dpll1_holdover
Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the
holdover mode.
Serial Interface
E2
F1
G1
E3
sck
I
I
Clock for Serial Interface (LVCMOS). Serial interface clock.
Serial Interface Input (LVCMOS). Serial interface data input pin.
Serial Interface Output (LVCMOS). Serial interface data output pin.
si
so
O
Iu
cs_b
Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This
pin is internally pulled up to Vdd.
G2
int_b
O
Interrupt Pin (LVCMOS). Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled up to VDD.
APLL Loop Filter
A6
B6
C6
sdh_filter
filter_ref0
filter_ref1
A
A
A
External Analog PLL Loop Filter terminal.
Analog PLL External Loop Filter Reference.
Analog PLL External Loop Filter Reference.
JTAG and Test
J4
K2
H4
tdo
O
Iu
Iu
Test Serial Data Out (Output). JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
tdi
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it
should be left unconnected.
trst_b
Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
K3
tck
I
Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
I/O
Pin #
Name
Description
Type
J3
tms
Iu
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to VDD. If this pin is not used
then it should be left unconnected.
Master Clock
K4
osci
I
Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz
reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of
the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
K5
osco
O
Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
Miscellaneous
J2
H7
J6
IC
Internal Connection. Connect to ground.
G3
K6
IC
Internal Connection. Leave unconnected.
No Connection. Leave unconnected.
F2
F3
NC
Power and Ground
D9
E4
G8
G9
J8
VDD
P
P
P
P
P
P
P
P
Positive Supply Voltage. +3.3VDC nominal.
J9
H6
H8
E8
F4
VCORE
AVDD
P
P
Positive Supply Voltage. +1.8VDC nominal.
A5
A8
P
P
P
Positive Analog Supply Voltage. +3.3VDC nominal.
C10
B7
B8
H2
AVCORE
P
P
P
Positive Analog Supply Voltage. +1.8VDC nominal.
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
I/O
Pin #
Name
Description
Type
D4
D5
D6
D7
E5
E6
E7
F5
F6
F7
G4
G5
G6
G7
E9
F8
F9
H9
VSS
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
Ground. 0 Volts.
A7
C7
C8
C9
D8
H3
AVSS
G
G
G
G
G
G
Analog Ground. 0 Volts.
I -
Id -
Input
Input, Internally pulled down
Iu -
Input, Internally pulled up
O - Output
A -
P -
Analog
Power
G - Ground
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
1.0 Functional Description
The ZL30121 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality
required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to
one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
1.1 DPLL Features
The ZL30121 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or
frame pulse synchronization. Table 1 shows a feature summary for both DPLLs.
Feature
DPLL1
DPLL2
Modes of Operation
Loop Bandwidth
Free-run, Normal (locked), Holdover
Free-run, Normal (locked), Holdover
User selectable: 0.1 Hz, 1.7 Hz, 3.5 Hz, Fixed: 14 Hz
fast lock (7 Hz), 14 Hz, 28 Hz1, or
wideband2 (890 Hz / 56 Hz / 14 Hz)
Phase Slope Limiting
Pull-in Range
User selectable: 885 ns/s, 7.5 µs/s,
61 µs/s, or unlimited
User selectable: 61 µs/s, or unlimited
User selectable: 12 ppm, 52 ppm,
83 ppm, 130 ppm
Fixed: 130 ppm
Holdover Parameters
Selectable Update Times: 26 ms, 1 s,
10 s, 60 s, and Selectable Holdover
Post Filter BW: 18 mHz, 2.5 Hz, 10 Hz.
Fixed Update Time: 26 ms
No Holdover Post Filtering
Holdover Frequency
Accuracy
Better than 1 ppb (Stratum 3E) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Better than 50 ppb (Stratum 3) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Reference Inputs
Sync Inputs
Ref0 to Ref7
Ref0 to Ref7
Sync0, Sync1, Sync2
2 kHz, N * 8 kHz up to 77.76 MHz
Sync inputs are not supported.
2 kHz, N * 8 kHz up to 77.76 MHz
Sync inputs are not supported.
Input Ref Frequencies
Supported Sync Input
Frequencies
166.67 Hz, 400 Hz, 1 kHz, 2 kHz,
8 kHz, 64 kHz.
Input Reference
Automatic (based on programmable
priority and revertiveness), or manual
Automatic (based on programmable
priority and revertiveness), or manual
Selection/Switching
Hitless Ref Switching
Output Clocks
Can be enabled or disabled
Can be enabled or disabled
diff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1, p0_clk0, p0_clk1, p1_clk0, p1_clk1.
p0_clk0, p0_clk1, p1_clk0, p1_clk1,
fb_clk.
Output Frame Pulses
sdh_fp0, sdh_fp1, p0_fp0, p0_fp1
p0_fp0, p0_fp1 not synchronized to sync
reference.
synchronized to active sync reference.
Supported Output Clock As listed in Table 4
Frequencies
As listed in Table 4 for p0_clk0, p0_clk1,
p1_clk0, p1_clk1
Table 1 - DPLL1 and DPLL2 Features
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Feature
DPLL1
As listed in Table 4
DPLL2
Supported Output
Frame Pulse
As listed in Table 4 for p0_fp0, p0_fp not
synchronized to sync reference.
Frequencies
External Status Pin
Indicators
Lock, Holdover
None
Table 1 - DPLL1 and DPLL2 Features
1. Limited to 14 Hz for 2 kHz references)
2. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies greater than
8 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to 8 kHz, the loop bandwidth = 56 Hz. The loop bandwidth is
equal to 14 Hz for reference frequencies of 2 kHz.
1.2 DPLL Mode Control
Both DPLL1 and DPLL2 independently support three modes of operation - free-run, normal, and holdover. The
mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.
All references are monitored for
frequency accuracy and phase
regularity, and at least one
reference is qualified.
Reset
Free-Run
Lock
Another reference is
qualified and available
for selection
Acquisition
Phase lock on
the selected
reference is
achieved
No references are
qualified and available
for selection
Holdover
Selected reference
fails
Normal
(Locked)
Figure 2 - Automatic Mode State Machine
Free-run
The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a
reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the
external master oscillator.
Lock Acquisition
The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the
input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given
a stable reference input, the ZL30121 will enter in the Normal (locked) mode.
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Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by
the DPLL so that its initial frequency offset is better than 1 ppb which meets the requirement of Stratum 3E. The
frequency drift after this transition period is dependant on the frequency drift of the external master oscillator.
1.3 Ref and Sync Inputs
There are eight reference clock inputs (ref0 to ref7) available to both DPLL1 and DPLL2. The selected reference
input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which can
be controlled using a built-in state machine or set in a manual mode.
DPLL2
ref7:0
DPLL1
sync2:0
Figure 3 - Reference and Sync Inputs
Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz.
Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is
within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz
are also available.
2 kHz
8 kHz
16.384 MHz
19.44 MHz
38.88 MHz
77.76 MHz
64 kHz
1.544 MHz
2.048 MHz
6.48 MHz
8.192 MHz
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies
13
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
In addition to the reference inputs, DPLL1 has three optional frame pulse synchronization inputs (sync0 to sync2)
used to align the output frame pulses. The syncn input is selected with its corresponding refn input, where n = 0, 1,
or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of the
frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.
refn
n = 0, 1, 2
x = 0, 1
Without a frame pulse
signal at the sync
input, the output
syncn - no frame pulse signal present
frame pulses will align
to any arbitrary cycle
of its associated
diffx/sdh_clkx/p0_clkx/p1_clkx
sdh_fpx/p0_fpx
output clock.
When a frame pulse
signal is present at
the sync input, the
DPLL will align the
output frame pulses
to the output clock
edge that is aligned
to the input frame
pulse.
refn
n = 0, 1, 2
x = 0, 1
syncn
diffx/sdh_clkx/p0_clkx/p1_clkx
sdh_fpx/p0_fpx
Figure 4 - Output Frame Pulse Alignment
Each of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising
edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width
requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies
shown in Table 3.
166.67 Hz
(48x 125 µs frames)
400 Hz
1 kHz
2 kHz
8 kHz
64 kHz
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies
14
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
1.4 Ref and Sync Monitoring
All input references (ref0 to ref7) are monitored for frequency accuracy and phase regularity. New references are
qualified before they can be selected as a synchronization source and qualified references are continuously
monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on
four levels of monitoring.
Single Cycle Monitor (SCM)
The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock
edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure
(scm_fail) is declared.
Coarse Frequency Monitor (CFM)
The CFM block monitors the reference frequency over a measurement period of 30 µs so that it can quickly detect
large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3%
or approximately 30000 ppm.
Precise Frequency Monitor (PFM)
The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an
accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities
are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the
rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the
edge of the acceptance range.
When determining the frequency accuracy of the reference input, the PFM uses the external oscillator’s output
frequency (focsi) as its point of reference.
Guard Soak Timer (GST)
The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the
SCM blocks and applying a selectable rate of decay when no failures are detected.
As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper
threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator
decrements until it reaches its lower threshold during the qualification window.
CFM or SCM failures
ref
upper threshold
lower threshold
td
tq
td - disqualification time
tq - qualification time = n * td
gst_fail
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures
15
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference
clock cycles within the frame pulse period.
1.5 Output Clocks and Frame Pulses
The ZL30121 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (diff0_p/n,
diff1_p/n), two SONET/SDH LVCMOS (sdh_clk0, sdh_clk1) output clocks, and four programmable LVCMOS
(p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH
frame pulse outputs (sdh_fp0, sdh_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also
available.
The feedback clock (fb_clk) of DPLL1 is available as an output clock. Its output frequency is always equal to
DPLL1’s selected input frequency.
The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and
the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1
or DPLL2. This allows the ZL30121 to have two independent timing paths.
p0_clk0
p0_fp0
p0_clk1
p0_fp1
P0
Synthesizer
DPLL2
DPLL1
P1
p1_clk0
p1_clk1
Synthesizer
diff0
diff1
SONET/SDH
APLL
sdh_clk0
sdh_fp0
sdh_clk1
sdh_fp1
Feedback
fb_clk
Synthesizer
Figure 6 - Output Clock Configuration
16
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
The supported frequencies for the output clocks and frame pulses are shown in Table 4.
diff0_p/n,
diff1_p/n
(LVPECL)
sdh_clk0,
sdh_clk1
(LVCMOS)
p0_clk0, p1_clk0
(LVCMOS)
p0_clk1, p1_clk1
(LVCMOS)
sdh_fp0, shd_fp1,
p0_fp0, p0_fp1
(LVCMOS)
6.48 MHz
6.48 MHz
2 kHz
px_clk0
px_clk1 =
166.67 Hz
(48x 125 µs frames)
2M
19.44 MHz
9.72 MHz
N * 8 kHz
400 Hz
(Up to 77.76 MHz)1
(up to 77.76 MHz)2
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
622.08 MHz
12.96 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
1 kHz
2 kHz
4 kHz
8 kHz
32 kHz
64 kHz
Table 4 - Output Clock and Frame Pulse Frequencies
1. M= -128 to 127 defined as an 8-bit two’s complement value. +ve values divide, -ve values multiply
2. N = 0 to 9270, N = 0 selects 2 kH
17
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
1.6 Configurable Input-to-Output and Output-to-Output Delays
The ZL30121 allows programmable static delay compensation for controlling input-to-output and output-to-output
delays of its clocks and frame pulses.
All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag
the selected input reference clock using the DPLL1 Fine Delay. The delay is programmed in steps of 119.2 ps with
a range of -128 to +127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative
values delay the output clock, positive values advance the output clock. Synthesizers that are locked to DPLL2 are
unaffected by this delay adjustment.
In addition to the fine delay introduced in the DPLL1 path, the SONET/SDH, P0, and P1 synthesizers have the
ability to add their own fine delay adjustments using the P0 Fine Delay, P1 Fine Delay, and SDH Fine Delay.
These delays are also programmable in steps of 119.2 ps with a range of -128 to +127 steps.
In addition to these delays, the single-ended output clocks of the SONET/SDH, P0, and P1 synthesizers can be
independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential outputs
can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame pulses
(SONET/SDH, P0) can be independently offset with respect to each other using the FP Delay.
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
Coarse Delay
Coarse Delay
P0
P0 Fine Delay
P1 Fine Delay
Synthesizer
DPLL2
FP Delay
FP Delay
Coarse Delay
Coarse Delay
P1
Synthesizer
diff0
diff1
Diff Delay
Diff Delay
SONET/SDH
APLL
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
Coarse Delay
Coarse Delay
SDH Fine Delay
DPLL1
FP Delay
FP Delay
Feedback
Synthesizer
DPLL1 Fine Delay
fb_clk
Figure 7 - Phase Delay Adjustments
18
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
1.7 Master/Slave Configuration
In systems that provide redundant timing sources, it is desirable to minimize the output skew between the master
and the slave’s output clocks. This can be achieved by synchronizing the slave to one of the master’s output clocks
instead of synchronizing the slave to an external reference. If frame pulse alignment between the timing sources is
required, then the crossover link should consist of a clk/fp pair.
One method of connecting two ZL30121 devices in a master/slave configuration is shown in Figure 8 where there is
a dedicated crossover link between timing cards. Any of the master’s unused outputs and the slave’s unused inputs
can be used as a crossover link.
External
External
References
References
ref0 ref1
ref0 ref1
Crossover Link
sdh_clk0
sdh_fp0
ref2
sync2
ZL30121
(Master)
ZL30121
(Slave)
sdh_clk0
sdh_fp0
ref2
sync2
sdh_fp0
sdh_fp0
sdh_clk0
sdh_clk0
clk bus 1
fp bus 1
clk bus 2
fp bus 2
ref0 sync0
ref1 sync1
ref0 sync0
ref1 sync1
Line Card DPLL
(ZL30119,
Line Card DPLL
(ZL30119,
ZL30117,
ZL30106)
ZL30117,
ZL30106)
Figure 8 - Typical Master/Slave Configuration
19
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
1.8 External Feedback Inputs
In addition to the static delay compensation described in the “External Feedback Inputs” section on page 20, the
ZL30121 also provides the option of dynamic delay compensation to minimize path delay variation associated with
external clock drivers and long PCB traces. This is accomplished by re-directing the internal DPLL1 feedback path
to external pins and closing the loop externally as shown in Figure 9.
ZL30121
DPLL1
clk_out
fp_out
clk
fp
SONET/P0/P1
Synthesizers
clk_in
fp_in
Path Delay
ref
sync
fb_clk
fb_fp
Feedback
Synthesizer
fb_clk
fb_fp
ext_fb_fp
ext_fb_clk
realignment of input and output clocks
clk_in
fp_in
clk_out
fp_out
Figure 9 - External Feedback Configuration
20
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
2.0 Software Configuration
The ZL30121 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The
device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s
processor, or it can operate in a manual mode where the system processor controls most of the operation of the
device.
The following table provides a summary of the registers available for status updates and configuration of the device.
.
Reset
Value
(Hex)
Addr
(Hex)
Register
Name
Description
Type
Miscellaneous Registers
00
01
id_reg
A5
00
Chip and version identification and reset ready
indication register
R
use_hw_ctrl
Allows some functions of the device to be
controlled by hardware pins
R/W
Interrupts
02
03
ref_fail_isr
dpll1_isr
FF
70
Reference failure interrupt service register
DPLL1 interrupt service register
R
Sticky
R
04
05
06
07
08
09
dpll2_isr
00
FF
FF
FF
FF
00
DPLL2 interrupt service register
Ref0 and ref1 failure indications
Ref2 and ref3 failure indications.
Ref4 and ref5 failure indications
Ref6 and ref7 failure indications
Sticky
R
ref_mon_fail_0
ref_mon_fail_1
ref_mon_fail_2
ref_mon_fail_3
ref_fail_isr_mask
Sticky
R
Sticky
R
Sticky
R
Sticky
R
Reference failure interrupt service register
mask
R/W
0A
0B
0C
dpll1_isr_mask
00
00
FF
DPLL1 interrupt service register mask
DPLL2 interrupt service register mask
R/W
R/W
R/W
dpll2_isr_mask
ref_mon_fail_mask_0
Control register to mask each failure indicator
for ref0 and ref1
0D
0E
ref_mon_fail_mask_1
ref_mon_fail_mask_2
FF
FF
Control register to mask each failure indicator
for ref2 and ref3
R/W
R/W
Control register to mask each failure indicator
for ref4 and ref5
Table 5 - Register Map
21
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Reset
Value
(Hex)
Addr
(Hex)
Register
Name
Description
Type
0F
ref_mon_fail_mask_3
FF
Control register to mask each failure indicator
for ref6 and ref7
R/W
Reference Monitor Setup
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
detected_ref_0
detected_ref_1
detected_ref_2
detected_ref_3
detected_sync_0
detected_sync_1
oor_ctrl_0
FF
FF
FF
FF
EE
0E
33
33
33
33
FF
FF
1A
Ref0 and ref1 auto-detected frequency value
status register
R
R
R
R
R
Ref2 and ref3 auto-detected frequency value
status register
Ref4 and ref5 auto-detected frequency value
status register
Ref6 and ref7 auto-detected frequency value
status register
Sync0 and sync1 auto-detected frequency
value and sync failure status register
Sync2 auto-detected frequency value and sync
valid status register
R
Control register for the ref0 and ref1 out of
range limit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
oor_ctrl_1
Control register for the ref2 and ref3 out of
range limit
oor_ctrl_2
Control register for the ref4 and ref5 out of
range limit
oor_ctrl_3
Control register for the ref6 and ref7 out of
range limit
gst_mask_0
Control register to mask the inputs to the guard
soak timer for ref0 to ref3
gst_mask_1
Control register to mask the inputs to the guard
soak timer for ref4 to ref7
gst_qualif_time
Control register for the guard_soak_timer
qualification time and disqualification time for
the references
DPLL1 Control
1D
1E
dpll1_ctrl_0
dpll1_ctrl_1
See
Register
Description
Control register for the DPLL1 filter control;
phase slope limit, bandwidth and hitless
switching
R/W
R/W
See
Register
Description
Holdover update time, filter_out_en,
freq_offset_en, revert enable
Table 5 - Register Map (continued)
22
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Reset
Value
(Hex)
Addr
(Hex)
Register
Name
Description
Type
1F
dpll1_modesel
See
Register
Description
Control register for the DPLL1 mode of
operation
R/W
20
21
dpll1_refsel
00
DPLL1 reference selection or reference
selection status
R/W
R/W
dpll1_ref_fail_mask
3C
Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
22
23
24
25
26
27
dpll1_wait_to_restore
dpll1_ref_rev_ctrl
00
00
10
32
54
76
Control register to indicate the time to restore a
previous failed reference
R/W
R/W
R/W
R/W
R/W
R/W
Control register for the ref0 to ref7 enable
revertive signals
dpll1_ref_pri_ctrl_0
dpll1_ref_pri_ctrl_1
dpll1_ref_pri_ctrl_2
dpll1_ref_pri_ctrl_3
Control register for the ref0 and ref1 priority
values
Control register for the ref2 and ref3 priority
values
Control register for the ref4 and re5 priority
values
Control register for the ref6 and ref7 priority
values
28
29
dpll1_lock_holdover_status
dpll1_pullinrange
04
03
DPLL1 lock and holdover status register
Control register for the pull-in range
R
R/W
DPLL2 Control
2A
dpll2_ctrl_0
00
Control register to program the DPLL2: hitless
switching, the phase slope limit and DPLL
enable
R/W
2B
2C
dpll2_ctrl_1
04
02
Control register to program the DPLL2:
filter_out_en, freq_offset_en, revert enable
R/W
R/W
dpll2_modesel
Control register to select the mode of operation
of the DPLL2
2D
2E
dpll2_refsel
00
DPLL2 reference selection or reference
selection status
R/W
R/W
dpll2_ref_fail_mask
3C
Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
2F
30
dpll2_wait_to_restore
dpll2_ref_rev_ctrl
00
00
Control register to indicate the time to restore a
previous failed reference for the DPLL2 path
R/W
R/W
Control register for the ref0 to ref7 enable
revertive signals
Table 5 - Register Map (continued)
23
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Reset
Value
(Hex)
Addr
(Hex)
Register
Name
Description
Type
31
32
33
34
35
dpll2_ref_pri_ctrl_0
dpll2_ref_pri_ctrl_1
dpll2_ref_pri_ctrl_2
dpll2_ref_pri_ctrl_3
dpll2_lock_holdover_status
10
32
54
76
04
Control register for the ref0 and ref1 priority
values
R/W
R/W
R/W
R/W
R
Control register for the ref2 and ref3 priority
values
Control register for the ref4 and re5 priority
values
Control register for the ref6 and ref7 priority
values
DPLL2 lock and holdover status register
P0 Configuration Registers
36
p0_enable
8F
Control register to enable p0_clk0, p0_clk1,
p0_fp0, p0_fp1, the P0 synthesizer and select
the source
R/W
37
38
39
3A
3B
3C
3D
3E
p0_run
0F
00
01
00
3E
00
00
05
Control register to generate p0_clk0, p0_clk1,
p0_fp0 and p0_fp1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
p0_freq_0
Control register for the [7:0] bits of the N of
N*8k clk0
p0_freq_1
Control register for the [13:8] bits of the N of
N*8k clk0
p0_clk0_offset90
p0_clk1_div
p0_clk1_offset90
p0_offset_fine
p0_fp0_freq
Control register for the p0_clk0 phase position
coarse tuning
Control register for the p0_clk1 frequency
selection
Control register for the p0_clk1 phase position
coarse tuning
Control register for the output/output phase
alignment fine tuning for p0 path
Control register to select the p0_fp0 frame
pulse frequency
3F
40
p0_fp0_type
83
00
Control register to select fp0 type
R/W
R/W
p0_fp0_fine_offset_0
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
41
42
43
p0_fp0_fine_offset_1
p0_fp0_coarse_offset
p0_fp1_freq
00
00
05
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
R/W
R/W
Programmable frame pulse phase offset in
multiples of 8 kHz cycles
Control register to select p0_fp1 frame pulse
frequency
Table 5 - Register Map (continued)
24
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Reset
Value
(Hex)
Addr
(Hex)
Register
Name
Description
Type
44
45
p0_fp1_type
11
00
Control register to select fp1 type
R/W
R/W
p0_fp1_fine_offset_0
p0_fp1_fine_offset_1
p0_fp1_coarse_offset
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
46
47
00
00
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
R/W
Programmable frame pulse phase offset in
multiples of 8 kHz cycles
P1 Configuration Registers
48
49
4A
4B
4C
4D
4E
4F
p1_enable
83
03
C1
00
00
3F
00
00
Control register to enable p1_clk0, p1_clk1, the
P1 synthesizer and select the source
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
p1_run
Control register to generate enable/disable
p1_clk0 and p1_clk1
p1_freq_0
Control register for the [7:0] bits of the N of
N*8k clk0
p1_freq_1
Control register for the [13:8] bits of the N of
N*8k clk0
p1_clk0_offset90
p1_clk1_div
p1_clk1_offset90
p1_offset_fine
Control register for the p1_clk0 phase position
coarse tuning
Control register for the p1_clk1 frequency
selection
Control register for the p1_clk1 phase position
coarse tuning
Control register for the output/output phase
alignrment fine tuning
SDH Configuration Registers
50
51
52
53
54
55
sdh_enable
8F
0F
42
00
00
00
Control register to enable sdh_clk0, sdh_clk1,
sdh_fp0, sdh_fp1 and the SDH PLL
R/W
R/W
R/W
R/W
R/W
R/W
sdh_run
Control register to generate sdh_clk0,
sdh_clk1, sdh_fp0 and sdh_fp1
sdh_clk_div
Control register for the sdh_clk0 and sdh_clk1
frequency selection
sdh_clk0_offset90
sdh_clk1_offset90
sdh_offset_fine
Control register for the sdh_clk0 phase position
coarse tuning
Control register for the sdh_clk1 phase position
coarse tuning
Control register for the output/output phase
alignrment fine tuning for sdh path
Table 5 - Register Map (continued)
25
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Reset
Value
(Hex)
Addr
(Hex)
Register
Name
Description
Type
56
57
sdh_fp0_freq
05
Control register to select the sdh_fp0 frame
pulse frequency
R/W
R/W
sdh_fp0_type
23
Control register to select fp0 type
58
59
5A
5B
sdh_fp0_fine_offset_0
sdh_fp0_fine_offset_1
sdh_fp0_coarse_offset
sdh_fp1_freq
00
00
00
03
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
R/W
R/W
R/W
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
Programmable frame pulse phase offset in
multiples of 8 kHz cycles
Control register to select sdh_fp1 frame pulse
frequency
5C
5D
sdh_fp1_type
03
00
Control register to select fp1 type
R/W
R/W
sdh_fp1_fine_offset_0
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
5E
5F
sdh_fp1_fine_offset_1
sdh_fp1_coarse_offset
00
00
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
R/W
Programmable frame pulse phase offset in
multiples of 8 kHz cycles
Differential Output Configuration
60
61
diff_ctrl
diff_sel
A3
53
Control register to enable diff0, diff1
R/W
R/W
Control register to select the diff0 and diff1
frequencies
External Feedback Configuration
62
63
64
fb_control
fb_offset_fine
reserved
80
Control register to enable fb_clk and the FB
R/W
R/W
PLL, int/ext feedback select
F5
Control register for the output/output phase
alignment fine tuning
N * 8 kHz Reference Control
65
66
67
ref_freq_mode_0
ref_freq_mode_1
custA_mult_0
00
00
00
Control register to set whether to use auto
R/W
R/W
R/W
detect, CustomA or CustomB for ref0 to ref3
Control register to set whether to use auto
detect, CustomA or CustomB for ref4 to ref7
Control register for the [7:0] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
Table 5 - Register Map (continued)
26
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Reset
Value
(Hex)
Addr
(Hex)
Register
Name
Description
Type
68
custA_mult_1
00
Control register for the [13:8] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
69
6A
6B
custA_scm_low
custA_scm_high
custA_cfm_low_0
00
00
00
Control register for the custom configuration A:
single cycle SCM low limiter
R/W
R/W
R/W
Control register for the custom configuration
A: single cycle SCM high limiter
Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM low
limit
6C
6D
6E
custA_cfm_low_1
custA_cfm_hi_0
custA_cfm_hi_1
00
00
00
Control register for the custom configuration
A: The [15:0] bits of the single cycle CFM low
limit
R/W
R/W
R/W
Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM high
limit
Control register for the custom configuration
A: The [15:0] bits of the single cycle CFM high
limiter
6F
70
custA_cfm_cycle
custA_div
00
00
Control register for the custom configuration
A: CFM reference monitoring cycles - 1
R/W
R/W
Control register for the custom configuration
A: enable the use of ref_div4 for the CFM and
PFM inputs
71
72
custB_mult_0
custB_mult_1
00
00
Control register for the [7:0] bits of the custom
configuration B. This is the 8 k integer for the
N*8kHz reference monitoring.
R/W
R/W
Control register for the [13:8] bits of the custom
configuration B. This is the 8 k integer for the
N*8kHz reference monitoring.
73
74
75
custB_scm_low
custB_scm_high
custB_cfm_low_0
00
00
00
Control register for the custom configuration B:
single cycle SCM low limiter
R/W
R/W
R/W
Control register for the custom configuration
B: single cycle SCM high limiter
Control register for the custom configuration
B: The [7:0] bits of the single cycle CFM low
limiter.
76
custB_cfm_low_1
00
Control register for the custom configuration
B: The [15:0] bits of the single cycle CFM low
limiter.
R/W
Table 5 - Register Map (continued)
27
Zarlink Semiconductor Inc.
ZL30121
Data Sheet
Reset
Value
(Hex)
Addr
(Hex)
Register
Name
Description
Type
77
custB_cfm_hi_0
00
Control register for the custom configuration
B: The [7:0] bits of the single cycle CFM high
limiter.
R/W
78
custB_cfm_hi_1
00
Control register for the custom configuration
B: The [15:0] bits of the single cycle CFM high
limiter.
R/W
79
7A
custB_cfm_cycle
custB_div
00
00
Control register for the custom configuration
B: CFM reference monitoring cycles - 1
R/W
R/W
Control register for the custom configuration
B: enable the use of ref_div4 for the CFM and
PFM inputs
7B -
7F
Reserved
Table 5 - Register Map (continued)
3.0 References
AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer
Manufacturers Group.
28
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
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