ZL30145GGG [ZARLINK]
Telecom IC,;
| 型号： | ZL30145GGG |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Telecom IC, |
| 文件： | 总4页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL30145
SyncE (10 GbE) SONET/SDH Rate
Conversion and Jitter Attenuator PLL
Short Form Data Sheet
July 2009
Features
Ordering Information
•
Can be used in systems to support the
ZL30145GGG
ZL30145GGG2
64 Pin CABGA
64 Pin CABGA*
Trays
Trays
requirements of ITU-T G.8262 for synchronous
Ethernet Equipment slave Clocks (EEC option 1
and 2)
*Pb Free Tin/Silver/Copper
-40oC to +85oC
•
Meets jitter generation requirements of Telcordia
GR-253-CORE for OC-192, OC-48, OC-12 and
OC-3 rates
•
•
Configurable through a serial interface (SPI or I2C)
DPLL can be configured to provide synchronous or
asynchronous clock outputs
•
•
Meets jitter generation requirements of ITU-T G.813
for STM-64, STM-16, STM-4 and STM-1 rates
•
Supports IEEE 1149.1 JTAG Boundary Scan
Synchronizes to standard telecom or Ethernet clock
and provides jitter filtered output clock for
SONET/SDH and Synchronous Ethernet line cards
Applications
•
•
Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
•
ITU-T G.8262 Line Cards which support 1 GbE
and 10 GbE interfaces
•
•
SONET line cards up to OC-192
SDH line cards up to STM-64
Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Ethernet PHYs
•
Selectable loop bandwidth of 14 Hz, 28 Hz, or
890 Hz
osci
osco
SONET/SDH/
diff
Ethernet
DPLL
/N
ref
ref
apll_clk
APLL
I2C/SPI
JTAG
hold
lock
Figure 1 - Simplified Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30145
Short Form Data Sheet
1.0 High Level Overview
The ZL30145 is a highly integrated device that provides timing for line cards. The DPLL automatically locks to one
input reference and provides two synchronized output clocks for synchronizing SONET/SDH and Synchronous
Ethernet line cards.
The ZL30145 has a on-chip digital phase-locked loop (DPLL) designed to provide rate conversion and jitter
attenuation for Synchronous Ethernet, (SyncE), Synchronous Digital Hierarchy (SDH) and Synchronous Optical
Network (SONET) networking equipment. The ZL30145 generates very low jitter clocks that meet the jitter
requirements of ITU-T G.8262, Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-
16, STM-4 and STM-1 rates.
2
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