ZL30414 [ZARLINK]
SONET/SDH Clock Multiplier PLL; SONET / SDH时钟倍频PLL
| 型号： | ZL30414 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | SONET/SDH Clock Multiplier PLL |
| 文件： | 总24页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL30414
SONET/SDH Clock Multiplier PLL
Data Sheet
February 2005
Features
•
Meets jitter requirements of Telcordia GR-253-
Ordering Information
CORE for OC-192, OC-48, OC-12, and OC-3
rates
ZL30414QGC 64 Pin TQFP Trays
ZL30414QGC1 64 Pin TQFP* Trays
*Pb Free Matte Tin
•
•
Meets jitter requirements of ITU-T G.813 for STM-
64, STM-16, STM-4 and STM-1 rates
-40°C to +85°C
Provides four LVPECL differential output clocks at
622.08 MHz
Description
•
•
Provides a CML differential clock at 155.52 MHz
The ZL30414 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30414 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC-
3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and
STM-1 rates.
Provides a single-ended CMOS clock at 19.44
MHz
•
•
•
•
Lock Indicator
Provides enable/disable control of output clocks
Accepts a CMOS reference at 19.44 MHz
3.3 V supply
Applications
•
•
The ZL30414 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 622.08 MHz, a CML differential
clock at 155.52 MHz and a single-ended CMOS
clock at 19.44 MHz. The output clocks can be
individually enabled or disabled. The ZL30414
provides a LOCK indication.
SONET/SDH line cards
Network Element timing cards
C622oEN-A
C622oEN-B
C622oEN-C
C622oEN-D
LPF
C622oP/N-A
Frequency
& Phase
Detector
C19i
C622oP/N-B
Frequency
Loop
Filter
VCO
Dividers
and
C622oP/N-C
C622oP/N-D
C155oP/N
C19o
Clock
Drivers
19.44MHz
Reference
and
State
Machine
Bias Circuit
C155oEN
C19oEN
VDD GND VCC
LOCK
BIAS
05
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30414
Data Sheet
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
GND
VCC1
GND
VCC
VDD
GND
VCC
GND
VDD
GND
NC
GND
GND
LOCK
GND
C19o
VDD
GND
2
4
65 - EP_GND
VCC
C155oN
C155oP
GND
6
8
VCC2
LPF
GND
GND
ZL30414
10
12
14
16
BIAS
C155oEN
C622oEN-A
C622oEN-B
C622oEN-C
C622oEN-D
18
20
22
24
26
28
30
32
Figure 2 - TQFP 64 pin (Top View)
Pin Description
Pin Description Table
Pin #
Name
Description
1
GND
VCC1
VCC
Ground. 0 volt
2
3
Positive Analog Power Supply. +3.3 V ±10%.
Positive Analog Power Supply. +3.3 V ±10%.
4
5
C155oN
C155oP
C155 Clock Output (CML). These outputs provide a differential 155.52 MHz
clock.
6
7
GND
Ground. 0 volt
VCC2
Positive Analog Power Supply. +3.3 V ±10%
Low Pass Filter (Analog). Connect to this pin external RC network (RF and
8
LPF
CF) for the low pass filter.
9
GND
GND
Ground. 0 volt
Ground. 0 volt
10
2
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
Pin Description Table (continued)
Pin #
Name
Description
Bias. See Figure 13 for the recommended bias circuit.
11
BIAS
12
C155o Clock Enable (CMOS Input). If tied high this control pin enables the
C155oP/N differential driver. Pulling this input low disables the output clock and
deactivates differential drivers.
C155oEN
C622oEN-A
C622oEN-B
C622oEN-C
C622oEN-D
C622 Clock Output Enable A (CMOS Input). If tied high this control pin
enables the C622oP/N-A output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
13
14
15
16
C622 Clock Output Enable B (CMOS Input). If tied high this control pin
enables the C622oP/N-B output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
C622 Clock Output Enable C (CMOS Input). If tied high this control pin
enables the C622oP/N-C output clock.Pulling this input low disables the output
clock without deactivating differential drivers.
C622 Clock Output Enable D (CMOS Input). If tied high this control pin
enables the C622oP/N-D output clock.Pulling this input low disables the output
clock without deactivating differential drivers.
17
18
GND
VDD
Ground. 0 volt
Positive Digital Power Supply. +3.3 V ±10%
19
20
21
22
NC
NC
NC
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
VDD
IC
Positive Digital Power Supply. +3.3 V ±10%
23
24
25
26
Internal Connection. Connect this pin to Ground (GND).
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
NC
NC
C19o Output Enable (CMOS Input). If tied high this control pin enables the
C19o output clock. Pulling this pin low forces output driver into a high
impedance state.
C19oEN
27
28
GND
C19i
VDD
Ground. 0 volt
C19 Reference Input (CMOS Input). This pin is a single-ended input reference
source used for synchronization. This pin accepts 19.44 MHz.
29
30
Positive Digital Power Supply. +3.3 V ±10%
GND
VDD
GND
Ground. 0 volt
31
32
Positive Digital Power Supply. +3.3 V ±10%
Ground. 0 volt
3
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
Pin Description Table (continued)
Pin #
Name
GND
VDD
Description
33
Ground. 0 volt
Positive Digital Power Supply. +3.3 V ±10%
34
35
C19 Clock Output (CMOS Output). This pin provides a single-ended CMOS
C19o
clock at 19.44 MHz.
36
37
GND
Ground. 0 volt
LOCK
Lock Indicator (CMOS Output). This output goes high when PLL is frequency
locked to the input reference C19i.
38
39
GND
Ground. 0 volt
GND
NC
Ground. 0 volt
40
41
No internal bonding Connection. Leave unconnected.
Ground. 0 volt
GND
42
43
44
45
46
47
48
49
VDD
GND
VCC
GND
VDD
VCC
GND
VCC
Positive Digital Power Supply. +3.3 V ±10%
Ground. 0 volt
Positive Analog Power Supply. +3.3 V ±10%
Ground. 0 volt
Positive Digital Power Supply. +3.3 V ±10%
Positive Analog Power Supply. +3.3 V ±10%
Ground. 0 volt
Positive Analog Power Supply. +3.3 V ±10%.
50
51
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL
clock at 622.08 MHz. Unused LVPECL port should be left unterminated to
decrease supply current.
C622oN-D
C622oP-D
52
53
GND
VCC
Ground. 0 volt
Positive Analog Power Supply. +3.3 V ±10%.
54
55
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL
clock at 622.08 MHz. Unused LVPECL port should be left unterminated to
decrease supply current.
C622oP-C
C622oN-C
56
57
GND
VCC
Ground. 0 volt
Positive Analog Power Supply. +3.3 V ±10%.
58
59
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL
clock at 622.08 MHz. Unused LVPECL port should be left unterminated to
decrease supply current.
C622oN-B
C622oP-B
4
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
Pin Description Table (continued)
Pin #
60
Name
GND
VCC
Description
Ground. 0 volt
Positive Analog Power Supply. +3.3 V ±10%.
61
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL
clock at 622.08 MHz. Unused LVPECL port should be left unterminated to
decrease supply current.
62
63
C622oP-A
C622oN-A
64
65
GND
NC
Ground. 0 volt
No internal bonding Connection. Leave unconnected.
1.0 Functional Description
The ZL30414 is an analog phased-locked loop which provides rate conversion and jitter attenuation for
SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block
diagram of the ZL30414 is shown in Figure 1 and a brief description is presented in the following sections.
1.1 Frequency/Phase Detector
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback
signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase
difference between the two. This error signal is passed to the Loop Filter circuit.
1.2 Lock Indicator
The ZL30414 has a built-in LOCK detector that measures frequency difference between input reference clock C19i
and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency
then the LOCK pin is set high. The LOCK pin is pulled low if the frequency difference exceeds ±1000 ppm.
1.3 Loop Filter
The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an
input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external
capacitor and resistor connected to the LPF pin and ground as shown in Figure 3.
ZL30414
Frequency
and Phase
Detector
LPF
Loop
Filter
RF=8.2 kΩ, CF=470 nF
RF
CF
VCO
Figure 3 - Loop Filter Elements
5
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
1.4 VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the
voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers
and Clock Drivers" block that divides VCO frequency and buffer generated clocks.
1.5 Output Interface Circuit
The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at
622.08 MHz, one CML differential clock at 155.52 MHz and a single-ended 19.44 MHz output clock. This block
provides also a 19.44 MHz feedback clock that closes PLL loop. Each output clock can be enabled or disabled
individually with the associated Output Enable pin.
Output Clocks
C622oP/N-A
Output Enable Pins
C622oEN-A
C622oEN-B
C622oEN-C
C622oEN-D
C155oEN
C622oP/N-B
C622oP/N-C
C622oP/N-D
C155oP/N
C19o
C19oEN
Table 1 - Output Enable Control
To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be
disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations.
6
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
2.0 ZL30414 Performance
The following are some of the ZL30414 performance indicators that complement results listed in the Characteristics
section of this data sheet.
2.1 Input Jitter Tolerance
Jitter tolerance is a measure of the PLL’s ability to operate properly (i.e., remain in lock and/or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its input reference. The
input jitter tolerance of the ZL30414 is shown in Figure 4. On this graph, the single line at the top represents
measured input jitter tolerance and the three overlapping lines below represent minimum input jitter tolerance for
OC-192, OC-48, and OC-12 network interfaces. The jitter tolerance is expressed in picoseconds (pk-pk) to
accommodate requirements for interfaces operating at different rates.
Figure 4 - Input Jitter Tolerance
7
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
2.2 Jitter Transfer Characteristic
Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a
PLL. This ratio is expressed in dB and it characterizes the PLLs ability to attenuate (filter) jitter. The jitter transfer
characteristic for the ZL30414 configured with recommended loop filter components (RF=8.2 kΩ, CF=470 nF) is
shown in Figure 5. The plotted curves represent jitter transfer characteristics over the recommended voltage (3.0 V
to 3.6 V) and temperature (-40C to 85C) ranges.
Figure 5 - Jitter Transfer Characteristic
8
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
3.0 Applications
3.1 Ultra-Low Jitter SONET/SDH Equipment Clocks
The ZL30414 functionality and performance complements the entire family of the Zarlink’s advanced network
synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical
interfaces operating up to OC-192/STM-64 rate (10 Gbit/s). The ZL30414 in combination with the MT90401 or the
ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks
suitable for network synchronization (see Figure 6) .
C622oA
C622oB
C622oC
C622oD
C155o
LVPECL
LVPECL
LVPECL
LVPECL
CML
622.08 MHz
622.08 MHz
622.08 MHz
622.08 MHz
155.52 MHz
19.44 MHz
C19i
ZL30414
C19o
CMOS
LPF
CF
RF
C19o
C155o
C34o/C44o
C16o
C8o
C6o
C4o
C2o
CMOS
LVDS
19.44 MHz
PRI
SEC
155.52 MHz
34.368 MHz or 44.736 MHz
16.384 MHz
8.192 MHz
6.312 MHz
4.096 MHz
2.048 MHz
1.544 MHz
8 kHz
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Synchronization
Reference
Clocks
RefSel
RefAlign
ZL30407
or
PRIOR
SECOR
MT90401
C1.5o
F16o
F8o
LOCK
8 kHz
8 kHz
HOLDOVER
F0o
CMOS
20 MHz
OCXO
Data Port
uP
Controller Port
Note: Only main functional connections are shown
Figure 6 - SONET/SDH Equipment Clock
9
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
The ZL30414 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure
7).
C622oA
C622oB
C622oC
C622oD
C155o
LVPECL
LVPECL
LVPECL
LVPECL
CML
622.08 MHz
622.08 MHz
622.08 MHz
622.08 MHz
155.52 MHz
19.44 MHz
C19i
ZL30414
C19o
CMOS
LPF
R1 = 680
Ω
R1
C1
C1 = 820 nF
C2 = 22 nF
C2
C19o
C16o
C8o
C6o
C4o
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
19.44 MHz
16.384 MHz
8.192 MHz
6.312 MHz
4.096 MHz
2.048 MHz
1.544 MHz
8 kHz
PRI
SEC
Synchronization
Reference
Clocks
RSEL
C2o
MT9046
LOCK
HOLDOVER
C1.5o
F16o
F8o
8 kHz
8 kHz
C20i
F0o
CMOS
20 MHz
TCXO
uC
Hardware Control
Note: Only main functional connections are shown
Figure 7 - SONET/SDH Line Card
10
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
3.2 Recommended Interface circuit
3.2.1 LVPECL to LVPECL Interface
The C622oP/N-A, C622oP/N-B, C622oP/N-B, and C622oP/N-D outputs provide differential LVPECL clocks at
622.08 MHz. The LVPECL output drivers require a 50 Ω termination connected to the Vcc-2V source for each
output terminal at the terminating end as shown below. The terminating resistors should be placed as close as
possible to the LVPECL receiver.
+3.3 V
0.1 uF
VCC=+3.3 V
R1
ZL30414
VCC
LVPECL
Receiver
R1
Z=50 Ω
Z=50 Ω
LVPECL
Driver
C622oP-A
C622oN-A
622.08 MHz
R2
R2
GND
Typical resistor values: R1 = 130 Ω, R2 =82 Ω
Figure 8 - LVPECL to LVPECL Interface
3.2.2 CML to CML Interface
The C155o output provides a differential CML/LVDS compatible clock at 155.52 MHz. The output drivers require a
50 Ω load at the terminating end if the receiver is CML type.
+3.3 V
Low impedance
DC bias source
0.1 uF
VCC
ZL30414
CML
Receiver
50 Ω
50 Ω
0.1 uF
0.1 uF
Z=50 Ω
Z=50 Ω
CML
C155oP
C155oN
Driver
155.52 MHz
GND
Figure 9 - CML to CML Interface
11
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
3.2.3 CML to LVDS Interface
To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode
voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the VCM (common mode voltage)
as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for
LVDS applications.
+3.3 V
0.1 uF
VCC=+3.3 V
R1
ZL30414
VCC
LVDS
10 nF
10 nF
R1
R2
Receiver
Z=50 Ω
Z=50 Ω
CML
C155oP
C155oN
Driver
100
Ω
155.52 MHz
R2
GND
Typical resistor values: R1 = 16 kΩ, R2 = 10 k
Ω
Figure 10 - LVDS Termination
3.2.4 CML to LVPECL Interface
The CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as
close as possible to the LVPECL receiver.
+3.3 V
0.1 uF
VCC=+3.3 V
R1
ZL30414
VCC
LVPECL
Receiver
R1
R2
10 nF
10 nF
Z=50 Ω
Z=50 Ω
CML
Driver
C155oP
C155oN
155.52 MHz
R2
GND
Typical resistor values: R1 = 82 Ω, R2 =130
Ω
Figure 11 - CML to LVPECL Interface
12
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
3.3 Tristating LVPECL Outputs
The ZL30414 has four differential 622.08 MHz LVPECL outputs, which can be used to drive four different OC-3/OC-
12/OC-48/OC-192 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are
required, a user can disable unused LVPECL outputs on the ZL30414 by pulling the corresponding enable pins low.
When disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V.
For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling can be used as
shown in Figure 12. Typically this might be required in hot swappable applications.
Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC
coupling capacitors. During disable mode (C622oEN pin pulled low) those capacitors present infinite impedance to
the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6
are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the
LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4,
R5 and R6 should not be populated.
C622oEN
3.3 V 3.3 V
ZL30414
R5
R3
C1
127
127
0.1 u
Z=50
Z=50
C2
0.1 u
R6
R1
R2
R4
82.5
200
200
82.5
Figure 12 - Tristatable LVPECL Outputs
13
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
3.4 Power Supply and BIAS Circuit Filtering Recommendations
Figure 13 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter
performance. The level of required filtering is subject to further optimization and simplification. Please check
Zarlink’s web site for updates.
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
+3.3 V Power Rail
0.1 uF
GND
VCC1
VCC
Ferrite Bead
64
62
60
58
56
54
52
50
4.7
Ω
48
46
44
42
40
38
GND
VCC
VDD
2
4
+
+
33 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
10 uF 0.1 uF
0.1 uF
GND
GND
GND
VCC
VDD
6
8
GND
VCC2
0.1 uF
+
+
ZL30414
33 uF
33 uF
GND
GND
10
11
12
220
Ω
GND
GND
BIAS
0.1 uF
36
34
GND
14
16
VDD
GND
0.1 uF
30
18
20
22
24
26
28
32
0.1 uF
0.1 uF
0.1 uF
Notes:
1. All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same ground plane.
2. Select Ferrite Bead with IDC > 400 mA and RDC in a range from 0.10 to 0.15
Ω
Ω
Figure 13 - Power Supply and BIAS Circuit Filtering
14
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
4.0 Characteristics
Absolute Maximum Ratings†
Characteristics
Sym.
DDR, VCCR
VPIN
Min.‡
Max.‡
Units
1
2
Supply voltage
V
TBD
-0.5
TBD
V
V
Voltage on any pin
VCC + 0.5
V
DD + 0.5
30
3
4
5
6
Current on any pin
ESD Rating
IPIN
VESD
TST
-0.5
-55
mA
V
1250
125
Storage temperature
Package power dissipation
°C
W
PPD
1.8
† Voltages are with respect to ground unless otherwise stated.
‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions†
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes
1
2
Operating Temperature
Positive Supply
TOP
-40
3.0
25
+85
3.6
°C
VDD, VCC
3.3
V
† Voltages are with respect to ground unless otherwise stated.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics†
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes
1
Supply Current
IDD+ICC
146
mA
LVPECL, CML
drivers
disabled and
unterminated
2
3
Incremental Supply Current to
single LVPECL driver (driver
enabled and terminated, see
Figure 8)
ILVPECL
37
26
mA
mA
Note 1
Note 2
Incremental Supply Current to
CML driver (driver enabled and
terminated, see Figure 9)
ICML
Note 3
4
5
6
CMOS: High-level input
voltage
VIH
VIL
IIL
0.7VDD
0
VDD
0.3VDD
5
V
V
CMOS: Low-level input
voltage
CMOS: Input leakage current
1
uA
VI = VDD
or 0 V
15
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
DC Electrical Characteristics† (continued)
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes
7
CMOS: Input bias current for
pulled-down inputs:
IB-PU
300
uA
VI = VDD
C622oEN-A, C622oEN-C,
C622oEN-D, OC-CLKoEN
8
9
CMOS: Input bias current for
pulled-up inputs: , C622oEN-B,
C19oEN
IB-PD
90
uA
VI = 0V
CMOS: High-level output
voltage
VOH
VOL
VOH
VOL
2.4
2.4
V
V
IOH = 8 mA
IOL = 4 mA
10 CMOS: Low-level output
voltage
0.4
0.4
11 LOCK pin: High-level output
voltage
IOH = 0.5 mA
IOL = 0.5 mA
12 LOCK pin: Low-level output
voltage
13 CMOS: C19o output rise time
14 CMOS: C19o output fall time
TR
TF
1.8
1.1
3.3
1.4
ns
ns
V
18 pF load
18 pF load
Note 2
15 LVPECL: Differential output
voltage (622.08 MHz)
IVOD_LVPECL
I
1.17
16 LVPECL: Offset voltage
(622.08 MHz)
VOS_LVPECL
Vcc-
1.31
Vcc-
1.20
Vcc-
1.09
V
Note 2
17 LVPECL: Output rise/fall times
(622.08 MHz)
TRF
170
ps
V
Note 2
Note 3
Note 3
18 CML: Differential output
voltage (155.52 MHz)
IVOD_CMLI
VOS_CML
0.73
19 CML: Offset voltage
(155.52 MHz)
Vcc-
0.58
Vcc-
0.54
Vcc-
0.50
V
20 CML: Output rise/fall times
(155.52 MHz)
TRF
220
ps
Note 3
†
-
-
-
-
: Voltages are with respect to ground unless otherwise stated.
‡
:Typical figures are for design aid only: not guaranteed and not subject to production testing.
Supply voltage and operating temperature are as per Recommended Operating Conditions
Note 1: The ILVPECL current is determined by the termination network connected to LVPECL outputs. More than 25% of this current
flows outside the chip and it does not contribute to the internal power dissipation.
-
-
Note 2: LVPECL outputs terminated with ZT = 50 Ω resistors biased to VCC-2V (see Figure 8)
Note 3: CML outputs terminated with ZT = 50 Ω resistors connected to low impedance DC bias voltage source (see Figure 9)
16
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
AC Electrical Characteristics† - Output Timing Parameters Measurement Voltage Levels
Characteristics
Sym
CMOS
LVPECL
CML
Units
1
Threshold Voltage
VT-CMOS
VT-LVPECL
VT-CML
0.5VDD
0.5VOD_LVPECL
0.5VOD_CML
V
2
3
Rise and Fall Threshold Voltage High
Rise and Fall Threshold Voltage Low
VHM
0.7VDD
0.3VDD
0.8VOD_LVPECL
0.2VOD_LVPECL
0.8VOD_CML
0.2VOD_CML
V
V
VLM
† Voltages are with respect to ground unless otherwise stated.
Timing Reference Points
VHM
VLM
VT
All Signals
tIF, tOF
tIR, tOR
Figure 14 - Output Timing Parameter Measurement Voltage Levels
17
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
AC Electrical Characteristics† - C19i Input to C19o, C155o and C622o Output Timing
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes
1
2
3
4
5
C19i to C19o delay
tC19D
tc155D
tC622D
dC155L
dC622L
6.2
3
7.2
4
8.2
5
ns
ns
ns
%
C19i to C155o delay
C19i to C622oA delay
C155o duty cycle
0
0.8
50
50
1.6
52
52
48
48
C622o duty cycle
%
†
Supply voltage and operating temperature are as per Recommended Operating Conditions
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
C19i
(19.44 MHz)
VT-CMOS
tC19D
C19o
VT-CMOS
(19.44 MHz)
tC155D
C155o
(155.52 MHz)
VT-CML
tC622D
C622oA
(622.08 MHz)
VT-LVPECL
Figure 15 - C19i Input to C19o, C155o and C622o Output Timing
18
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
AC Electrical Characteristics†- C622 Clocks Output Timing
Characteristics
Sym.
Min.
Typ.‡
Max. Units
Notes
1
2
3
C622oA to C622oB
tC622D-AB
tC622D-AC
tC622D-AD
-50
-50
-50
0
0
0
+50
+50
+50
ps
ps
ps
C622oA to C622oC
C622oA to C622oD
†
Supply voltage and operating temperature are as per Recommended Operating Conditions
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
C622oA
VT-LVPECL
tC622D-AB
VT-LVPECL
C622oB
C622oC
tC622D-AC
VT-LVPECL
tC622D-AD
C622oD
VT-LVPECL
Note: All output clocks have nominal 50% duty cycle.
Figure 16 - C622oB, C622oC, C622oD Outputs Timing
19
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
Performance Characteristics - Functional (VCC = 3.3 V ±10%; TA = -40 to 85°C )
Characteristics
Pull-in range
Min.
Typ.
Max.
Units
Notes
1
2
±1000
ppm
At nominal input
reference frequency
C19i = 19.44 MHz
Lock Time
300
ms
Performance Characteristics : Output Jitter Generation - GR-253-CORE conformance (VCC = 3.3V ±10%;
TA = -40 to 85°C )
ZL30414 Jitter Generation
GR-253-CORE Jitter Generation Requirements
Performance
Jitter
Measurement
Filter
Equivalent
limit in time
domain
Interface
Limit in
UI
Typ.†
Max.‡
Units
psP-P
(Category II)
1
2
3
OC-192
50 kHz - 80 MHz 0.1 UIPP
0.01 UIRMS
12 kHz - 20 MHz 0.1 UIPP
0.01 UIRMS
0.1 UIPP
0.01 UIRMS
10.0
1.0
-
7.31
0.94
7.32
0.83
4.37
0.60
STS-192
0.52
-
psRMS
psP-P
OC-48
40.2
4.02
161
16.1
STS-48
0.58
-
psRMS
psP-P
OC-12
12 kHz - 5 MHz
STS-12
0.34
psRMS
† Typical figures are for design aid only: not guaranteed and not subject to production testing.
‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF
20
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
Performance Characteristics : Output Jitter Generation - G.813 conformance (Option 1 and 2) (VCC = 3.3V
±10%; TA = -40 to 85°C )
ZL30414 Jitter Generation
G.813 Jitter Generation Requirements
Performance
Jitter
Measurement
Filter
Equivalent
limit in time
domain
Limit in
UI
Interface
Typ.†
Max.‡
Units
Option 1
1
2
3
STM-64
4 MHz to 80 MHz
0.1 UIpp
0.5 UIpp
0.1 UIpp
0.5 UIpp
0.1 UIpp
0.5 UIpp
10.0
50.2
40.2
201
161
804
-
0.49
-
6.95
0.89
11.5
1.04
6.40
0.68
8.67
1.06
3.33
0.42
19.1
2.88
psP-P
psRMS
psP-P
20 kHz to 80 MHz
1 MHz to 20 MHz
5 kHz to 20 MHz
250 kHz to 5 MHz
1 kHz to 5 MHz
0.82
-
psRMS
psP-P
STM-16
STM-4
0.50
-
psRMS
psP-P
0.68
-
psRMS
psP-P
0.26
-
psRMS
psP-P
1.51
psRMS
Option 2
5
STM-64
4 MHz to 80 MHz
0.1 UIpp
0.3 UIpp
0.1 UIpp
0.1 UIpp
10.0
30.1
40.2
161
-
0.49
-
6.95
0.89
11.5
1.04
7.32
0.83
4.37
0.60
psP-P
psRMS
psP-P
psRMS
psP-P
psRMS
psP-P
psRMS
20 kHz to 80 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.82
-
6
7
STM-16
STM-4
0.58
-
0.34
† Typical figures are for design aid only: not guaranteed and not subject to production testing.
‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF
21
Zarlink Semiconductor Inc.
ZL30414
Data Sheet
Performance Characteristics : Output Jitter Generation - ETSI EN 300 462-7-1conformance (VCC = 3.3V
±10%; TA = -40 to 85°C )
ZL30414 Jitter Generation
EN 300 462-7-1 Jitter Generation Requirements
Performance
Jitter
Measurement
Filter
Equivalent
limit in time
domain
Limit in
UI
Interface
Typ.†
Max.‡
Units
psP-P
1
2
STM-16
1 MHz to 20 MHz
0.1 UIpp
0.5UIpp
40.2
201
161
804
-
0.50
-
6.40
0.68
8.67
1.06
3.33
0.42
19.1
2.88
psRMS
psP-P
5 kHz to 20 MHz
0.68
-
psRMS
psP-P
STM-4
250 kHz to 5 MHz 0.1 UIpp
0.26
-
psRMS
psP-P
1 kHz to 5 MHz
0.5 UIpp
1.51
psRMS
† Typical figures are for design aid only: not guaranteed and not subject to production testing.
‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF
22
Zarlink Semiconductor Inc.
Package Code
c
Zarlink Semiconductor 2005 All rights reserved.
Previous package codes
ISSUE
ACN
DATE
APPRD.
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