ZL38070GBG [ZARLINK]
256 Channel Voice Echo Canceller; 256信道语音回声消除器
| 型号： | ZL38070GBG |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 256 Channel Voice Echo Canceller |
| 文件： | 总51页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL38070
256 Channel Voice Echo Canceller
Data Sheet
January 2006
Features
Ordering Information
•
ZL38070 has eight Echo Voice Processors in a
single BGA package. This single device provides
256 channels of 64 msec echo cancellation or
128 channels at 128 msec echo cancellation
ZL38070GBG
535 Ball BGA Trays, Bake & Drypack
ZL38070GBG2 535 Ball BGA** Trays, Bake & Drypack
**Pb Free Tin/Silver/Copper
•
•
•
•
•
Each Echo Voice Processor has the capability of
-40°C to +85°C
cancelling echo over 32 channels
Each Echo Voice Processor (EVP) shares the
address bus and data bus with each other
•
Each EVP can be programmed independently in
any mode e.g., Back-to-Back or Extended Delay
to provide capability of cancelling different echo
tails
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
•
•
Each EVP has +9 to -12 dB level adjusters at all
Passed all AT&T voice quality tests for carrier
grade echo canceller
signal ports (Rin, Sin, Sout and Rout)
Parallel controller interface compatible with
Motorola microcontrollers
Sub 50 ms initial convergence times under many
typical network conditions
•
•
Unparalleled in-system tunability
Applications
The ZL38070 provides more than 58% board
space savings when compared with eight
individually packaged Echo Voice Processor
devices
Each EVP has a Patented Advanced Non-Linear
Processor with high quality subjective
performance
Each EVP has protection against narrow band
signal divergence and instability in high echo
environments
•
•
•
•
•
•
Voice over IP network gateways
Voice over ATM, Frame Relay
T1/E1/J1 multichannel echo cancellation
Wireless base stations
•
•
Echo Canceller pools
DCME, satellite and multiplexer system
ZL38070GB
Rin1...Rin8
Sin1....Sin8
Rout1..Rout8
EVP3
EVP1
EVP4
EVP2
D0....D7
Sout1..Sout8
CS1..CS8
A0..A12
EVP5
IRQ1..IRQ8
EVP6
EVP7
EVP8
RESET1..RESET8
DTA1..DTA8
Figure 1 - ZL38070 Device Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL38070
Data Sheet
Description
The ZL38070 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation
conforming to ITU-T G.168 requirements. The ZL38070 architecture contains 128 groups of two echo cancellers
(ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of
128 milliseconds echo cancellation. This provides 256 channels of 64 milliseconds to 128 channels of
128 milliseconds echo cancellation or any combination of the two configurations. The ZL38070 supports ITU-T
G.165 and G.164 tone disable requirements.
V
V
DD1 (3.3V)
V
DD2 (1.8V)
SS
ODE
Echo Canceller Pool
Rin
Sin
Rout
Sout
Group 0
Group 1
ECA/ECB
Group 2
ECA/ECB
Group 3
ECA/ECB
Parallel
to
Serial
to
ECA/ECB
Serial
Parallel
Group 4
ECA/ECB
Group 5
ECA/ECB
Group 6
ECA/ECB
Group 7
ECA/ECB
MCLK
Fsel
Group 8
ECA/ECB
Group 9
ECA/ECB
Group 10 Group 11
ECA/ECB ECA/ECB
PLL
IC0
Note:
Group 12 Group 13 Group 14 Group 15
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Refer to Figure 4
for EVP block
diagram
C4i
F0i
RESET
Timing
Unit
Microprocessor Interface
Test Port
DS CS R/W A12-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 2 - Single Echo Voice Processor (EVP) Overview
2
Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Table of Contents
1.0 Single Echo Voice Processor (EVP) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Adaptive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Double-Talk Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3 Path Change Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4 Non-Linear Processor (NLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 Disable Tone Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Instability Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.7 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.8 Offset Null Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.9 Adjustable Level Pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.0 EVP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Normal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Back-to-Back Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Extended Delay Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.0 Echo Canceller Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Mute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Disable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Enable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.0 Echo Voice Processor (EVP) Throughput Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.0 Serial PCM I/O channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.0 Memory Mapped Control and Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Normal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 Extended Delay Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 Back-to-Back Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6 Call Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.0 EVP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
List of Figures
Figure 1 - ZL38070 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Single Echo Voice Processor (EVP) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 - 535 Ball BGA Ball Grid Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4 - Functional Block Diagram of an Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - Sample G.168 Test 2A Convergence Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6 - Disable Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 - Normal Device Configuration (64 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9 - Extended Delay Configuration (128 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10 - ST-BUS and GCI Interface Channel Assignment for 2 Mb/s Data Streams . . . . . . . . . . . . . . . . . . . . 21
Figure 11 - Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12 - Power Up Sequence Flow Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13 - The MU Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14 - ST-BUS Timing at 2.048 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 15 - GCI Interface Timing at 2.048 Mb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 16 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17 - Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 18 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
List of Tables
Table 1 - Quiet PCM Code Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2 - Memory Page Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3 - Group and Channel Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4 - Memory Mapping of Per Channel Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Features of Echo Voice Processor (EVP)
•
Independent multiple channels of echo cancellation; from 32 channels of 64 ms to 16 channels of 128 ms
with the ability to mix channels at 128 ms or 64 ms in any combination
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully compliant to ITU-T G.165, G.168 (2000) and (2002) specifications
Passed all AT&T voice quality tests for carrier grade echo canceller systems
Unparalleled in-system tunability
Sub 50 ms initial convergence times (G.168 Test 2A, Hybrid 5, 40 ms delay, ERL=24 dB, Lrin=0 dBm0)
Fast reconvergence on echo path changes
Patented Advanced Non-Linear Processor with high quality subjective performance
Superior noise matching algorithm
PCM coding, µ/A-Law ITU-T G.711 or sign magnitude
Per channel Fax/Modem G.164 2100 Hz or G.165 2100 Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Protection against narrow band signal divergence and instability in high echo environments
+9 dB to -12 dB level adjusters (3 dB steps) at all signal ports
Offset nulling of all PCM channels
Independent Power Down mode for each group of 2 channels for power management
Compatible to ST-BUS and GCI interface at 2 Mbps serial PCM
3.3 V pads and 1.8 V Logic core operation with 5 V tolerant inputs
IEEE-1149.1 (JTAG) Test Access Port
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1
A
B
A
B
C
D
C
D
E
F
E
F
G
G
H
J
H
J
ZL38070GB
BGA BALL GRID ARRAY
K
L
K
L
M
N
P
R
M
N
P
R
T
T
U
V
U
V
W
Y
W
Y
AA
AB
AA
AB
AC
AC
AD
AE
AF
AG
AH
AD
AE
AF
AG
AH
AJ
AJ
AK
AK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Figure 3 - 535 Ball BGA Ball Grid Array
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Pin Description
Signal
Name
Signal
Type
Signal
Description
BGA Ball #
AC5,AC26,AC27,AD26,AD5,AE5,AF12,AF13,AF1 Positive Power
VDD1 = 3.3V
Power
Supply. Nominally
3.3 volt (I/O
4,AF17,AF18,AF19,AF24,AF6,AF7,AF8,AG24,AH
24,E13,E14,E17,E18,E19,E23,E24,E25,E6,E7,E8,
F5,G26,G27,G5,H26,H5,M26,M5,N26,N5,P26,P27
, P4,P5,U26,U27,U4,U5,V26,V5,W26,W5
(VDD_IO
)
voltage).
AA26,AA28,AA3,AA5,AB26,AB28,AB3,AB5,AF11, Positive Power
VDD2 = 1.8V
(VDD_Core
Power
Supply. Nominally
1.8 volt (Core
voltage).
AF20,AG10,AG21,AG22,AH10,AH11,AH22,AJ15,
AJ16,AJ9,AK9,C10,C11,C22,C23,C9,D10,D23,D9,
E11,E20,E21,E22,J26,J27,J4,J5,K26,K27,K3,K5,
L26,L27,L3,L5,Y26, Y27,Y3,Y5
)
A29,A30,AF5,AG15,AG16,AG26,AG27,AG4,
AH15,AH16,AH21,AH28,AH3,AJ2,AJ21,AJ29,
AK1,AK30,B1,B15,B16,B2,B29,C15,C16,C28,C3,
D15,D16,D27,D4,E26,E5,N13,N14,N15,N16,N17,
N18,P13,P14,P15,P16,P17,P18,R13,R14,R15,
R16,R17,R18,R2,R27,R28,R29,R3,R4,T13,T14,
T15,T16,T17,T18,T2,T27,T28,T29,T3,T4,U13,U14,
U15, U16,U17,U18,V13,V14,V15,V16, V17,V18
Ground
VSS
Power
TEST PINS
TE1, TE2,
TE3, TE4,
TE5, TE6,
TE7, TE8
M4,AK26,M3,AJ4,AK4,AK25,K30,N28
Internal
Connection.
Connected to VSS
for normal
Test Mode
Pins
operation.
D8,P28,C12,AK10,AH12,AD29,H28,J29,AC28,
D12,P29,E9,AJ11,AK11,AD30,G28,H29,AB27,A3,
P2,A2,Y1,AA1,AJ17,C20,B21,AK17,B3,P1,D3,
AA2,AB1,AK18,B22,D21,AJ18,C2,R1,E3,AB2,
AB4,AH18,D19,A22,AK19,D2,T1,E4,AC1,AC2,
AG18,A21,B20,AJ19,C1,U1,F4,AC4,AD1,AK20,
C19,A20,AH19,F3,U2,E2,AC3,AD2,AK21,B19,
A19,AG19,E10,P30,B12,AJ12,AG13,AC29,J30,
G29,AC30,A11,N30,D11,AH13,AK12,AB29,H30,
G30,AB30,A10,N27,B11,AJ13,AG14,AA27,F29,
F30,AA29,A9,A14,B10,AG11,AG12,Y28,E29,E28,
AA30,A8,A13,B9,AJ10,AF10,Y29,D29,E30,Y30,
C8,B14,B8,AG9,AH9,W28,D26,D28,W29,C4,
E12,C5,AA4,Y4,R30,A23,B23,T30,B4,P3,A4,Y2,W
1,AG17,D20,C21,AH17
No connection.
These pins must be
left open for normal
operation.
OUTPUT
Test
pins
TEST PINS
INPUT TEST
PINS
SC_EN, SC_FCLK, A27,D5,A25,A26,A24,B24,A28
SC_IN, SC_M_MCLK,
Internal
Connection.
Connected to VSS
for normal
SC_RESET,
SC_SET, SC_T_MCLK,
operation.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Pin Description (continued)
Signal
Name
Signal
Signal
BGA Ball #
C14, D14
Type
Description
THalt
Halt
Internal
and TStep
Step
Connection.
Connected to VSS
for normal
operation.
Signal
Type
Signal Name
BGA Ball #
Signal Description
User Signal Pins
D0, D1, D2, D3, D4, D5,
D6, D7
User
AK7,AJ8,AK8,
AJ27,AK29,AJ28,
AH27, AJ30
Data Bus D0 to D7 (Bidirectional). These pins form
the 8-bit bidirectional data bus of the microprocessor
port. They are connected to all the EVP’s.
Signals
A0,A1,A2,A3,A4,A5,
A6,A7, A8, A9,
A10,A11,A12
User
AG28,AH29,
AH30,AG29,AF28,
AG30,AE28,AF29,
AE29,AF30,AD27,
AE30,AD28
Address A0 to A12 (Input). These inputs provide the
A12 - A0 address lines to the internal registers. They
are connected to all the EVP’s.
Signals
CS1,CS2,CS3,
CS4, CS5, CS6,
CS7, CS8
User
R5,L28,T5,AF15, Chip Select (Input). These active low inputs are used
Signals
enable the microprocessor interface of each EVP.
AF16,E16,T26,
R26
EVP Reset (Schmitt Trigger Input). An active low
resets the device and puts the Voice Processor into a
low-power stand-by mode. When the RESET pin is
returned to logic high and a clock is applied to the
MCLK pin, the EVP will automatically execute
initialization routines, which preset all the Control
and Status Registers to their default power-up
values. Each reset pin controls a single processor. A
user can connect all of them together if required.
RESET1 RESET2,
RESET3, RESET4,
RESET5, RESET6,
RESET7, RESET8
User
M2,AH23,M1,AH5,
AJ5,AJ23,N29,M30
Signals
Rin1,Rin2,Rin3,
Rin4,Rin5,Rin6,
Rin7,Rin8
User
C6,V27,B5,AG5, Receive PCM Signal Inputs (Input). Port 1 TDM data
Signals
input streams. Each Rin pin receives serial TDM data
streams at 2.048 Mb/s with 32 channels per stream.
AH6,U28,B27,B28
Sin1,Sin2,Sin3,Sin4,
Sin5,Sin6,Sin7,Sin8
User
C7,U30,B6,AG7, Send PCM Signal Inputs (Input). Port 2 TDM data
Signals
input streams. Each Sin pin receives serial TDM data
streams at 2.048 Mb/s with 32 channels per stream.
AG6,U29,B30,C27
Rout1,Rout2,Rout3,
Rout4,Rout5,Rout6,
Rout7,Rout8,
User
A5,V30,A6,AH7, Receive PCM Signal Outputs (Output). Port 2 TDM
Signals
data output streams. Each Rout pin outputs serial
TDM data streams at 2.048 Mb/s with 32 channels per
stream.
AG8,V28,C26,C30
Sout1,Sout2,Sout3,
Sout4,Sout5,Sout6,
Sout7,Sout8
User
B7,W27,A7,AH8, Send PCM Signal Outputs (Output). Port 1 TDM
Signals
data output streams. Each Sout pin outputs serial TDM
data streams at 2.048 Mb/s with 32 channels per
stream.
AF9,W30,C29,D30
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Signal
Type
Signal Name
DS
BGA Ball #
Signal Description
User
K29
Data Strobe (Input). This active low input works in
conjunction with CS to enable the read and write
operations. This signal is connected to all processors.
Signal
User
M29
Read/Write (Input). This input controls the direction of
the data bus lines (D7-D0) during a microprocessor
access. This signal is connected to all processors.
R/W
Signal
DTA1, DTA2, DTA3,
DTA4, DTA5, DTA6,
DTA7, DTA8
User
N2,AK28,N1,AK6, Data Transfer Acknowledgment (Open Drain
Signals
Output). These active low outputs indicate that a data
bus transfer is completed. A pull-up resistor (1 K
typical) is required at these outputs.
AJ7,AK27,M28,
M27
User
V29
Output Drive Enable (Input). This input pin is
logically AND’d with the ODE bit-6 of the Main Control
Register. When both ODE bit and ODE input pin are
high, the Rout and Sout ST-BUS outputs are enabled.
When the ODE bit is low or the ODE input pin is low,
the Rout and Sout ST-BUS outputs are high
Signal
ODE
impedance. This signal is connected to all processors.
User
B26
Frame Pulse (Input). This input accepts and
automatically identifies frame synchronization signals
formatted according to ST-BUS or GCI interface
specifications.This signal is connected to all
processors.
Signal
F0i
C4i
User
B25
A15
Serial Clock (Input). 4.096 MHz serial clock for
shifting data in/out on the serial streams (Rin, Sin,
Rout, Sout).This signal is connected to all processors.
Signal
User
Frequency select (Input). This input selects the Mas-
ter Clock frequency operation. When Fsel pin is low,
nominal 20 MHz Master Clock input must be applied.
When Fsel pin is high, nominal 10 MHz Master Clock
input must be applied.This signal is connected to all
processors.
Signal
Fsel
User
A16
Master Clock (Input). Nominal 10 MHz or 20 MHz
Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock
source.This signal is connected to all processors.
MCLK
Signal
User
N4,AJ26,N3,AK5, Interrupt Request (Open Drain Output). These
IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6,
IRQ7, IRQ8
Signals
outputs go low when an interrupt occurs in any
channel. Each IRQ returns high when all the interrupts
have been read from the Interrupt FIFO Register of
respective EVP. A pull-up resistor (1 K typical) is
required at these outputs.
AJ6,AG23,L30,L29
-
W3,E15,V4,AK16, No connection. The ball pins must be left open for
Extra Device Pins
normal operation.
AK15,AK14,D13,
C13,V3,A12,B13,
AK13,AH14,U3,V2,
AJ14
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Signal
Type
Signal Name
TMS
BGA Ball #
JTAG Signal Pins
Signal Description
K2
Test Mode Select (3.3 V Input). JTAG signal that
controls the state transitions of the TAP controller. This
pin is pulled high by an internal pull-up when not
driven. This signal is connected to all processors. See
DC Electrical Characteristics, Note 1 on page 45.
JTAG
Signal
JTAG
D6
D7
Test Clock (3.3 V Input). Provides the clock to the
JTAG test logic.This signal is connected to all
processors.
TCK
Signal
Test Reset (3.3 V Input). Asynchronously initializes
the JTAG TAP controller by putting it in the Test-Logic-
Reset state. This pin should be pulsed low on power-
up or held low, to ensure that all the EVP’s are in the
normal functional mode. This pin is pulled by an
internal pull-down when not driven. This signal is
connected to all EVP’s. See DC Electrical
JTAG
TRST
Signal
Characteristics, Note 1 on page 45.
TDI1,TDI2,TDI3,TDI4,
TDI5,TDI6,TDI7,TDI8
JTAG
K1,AK23,L2,AK2, Test Serial Data In (3.3 V Input). JTAG serial test
AJ3,AH20,F27,H27
Signals
instructions and data are shifted in on these pins.
These pins are pulled high by an internal pull-up when
not driven.
TDO1,TDO2,TDO3,
TDO4,TDO5,TDO6
TDO7,TDO8
JTAG
L1,AJ22,L4,AH4, Test Serial Data Out (Output). JTAG serial data is
AK3,AK24,J28,K28
Signals
outputted on these pins on the falling edge of TCK.
These pins are held in high impedance state when
JTAG scan is not enabled.
PLL Signal Pins
PLLVDD2 = 1.8V
PLL
H3,V1,H4,AE3, PLL Power Supply. Must be connected to PLLVDD2 =
Power
1.8 V.
AG2,AE26,D22,
C24, AE27
J3,W2,H2,AF4, PLL Ground. Must be connected to VSS.
PLLVSS1
PLLVSS2
PLL
AF3,AF27,D24,
C25,AF26,H1,W4,
J2,AH1,AG3,AF22,
D25,E27,AF21
Power
T1M1, T1M2, T1M3,
T1M4, T1M5, T1M6,
T1M7, T1M8
PLL Test D1,AH26,E1,AE1, Internal Connection. Connected to VSS for normal
AD4,AK22,D18,
C18
Signals
operation.
T2M1, T2M2, T2M3,
T2M4, T2M5, T2M6,
T2M7, T2M8
PLL Test F2,AG25,G3,AF1, Internal Connection. Connected to VSS for normal
AD3,AF25,B18,A18
Signals
operation.
SG1, SG2, SG3, SG4, PLL Test G4,AJ25,F1,AE2, Internal Connection. Connected to VSS for normal
AG1,
SG5, SG6, SG7, SG8
Signals
operation.
AH25,B17,C17
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Signal
Type
Signal Name
BGA Ball #
Signal Description
DT1, DT2, DT3, DT4,
DT5, DT6, DT7, DT8
PLL Test G2,AF23,G1,AF2, No connection. These pins must be left open for
AE4,AJ24,D17,
A17
Signals
normal operation.
AT1, AT2, AT3, AT4,
AT5, AT6, AT7, AT8
PLL Test
Signals
K4,AJ20,J1,
AH2,AJ1,AG20,
F28,F26
No connection. These pins must be left open for
normal operation.
1.0 Single Echo Voice Processor (EVP) Description
The following description applies to a single EVP (Echo Voice Processor). Note that the ZL38070 contains eight
EVP’s. Each single Echo Voice Processor (EVP) contains 32 echo cancellers divided into 16 groups. Each group
has two echo cancellers, Echo Canceller A (ECA) and Echo Canceller B (ECB). Each group can be configured in
Normal, Extended Delay or Back-to-Back configurations. In Normal configuration, a group of echo cancellers
provides two channels of 64 ms echo cancellation, which run independently on different channels. In Extended
Delay configuration, a group of echo cancellers achieves 128 ms of echo cancellation by cascading the two echo
cancellers (A & B). In Back-to-Back configuration, the two echo cancellers from the same group are positioned to
cancel echo coming from both directions in a single channel, providing full-duplex 64 ms echo cancellation.
Each Echo Voice Processor contains the following main elements (see Figure 4).
•
•
•
•
•
•
•
•
•
•
•
•
Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter adaptation during periods of double-talk
Path Change detector for fast reconvergence on major echo path changes
Instability Detector to combat instability in very low ERL environments
Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
Offset Null filters for removing the DC component in PCM channels
+9 to -12 dB level adjusters at all signal ports
PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the EVP has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in section 3.0, “Echo Canceller Functional States“ on page 19.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
+9 to -12 dB
Level Adjust
Non-Linear
Processor
+9 to -12 dB
Level Adjust
Offset
Null
Linear/
/A-Law
µ
/A-Law/
Sin
Σ
Sout
µ
Linear
(channel N)
(channel N)
-
Microprocessor
Disable Tone
MuteS
Interface
Detector
Double - Talk
Detector
Path Change
Detector
ST-BUS
PORT2
ST-BUS
PORT1
Instability
Detector
Disable Tone
Detector
Narrow-Band
Detector
MuteR
Offset
Null
Linear/
/A-Law
+9 to -12 dB
Level Adjust
+9 to -12 dB
Level Adjust
µ
/A-Law/
Rout
Rin
µ
Linear
(channel N)
(channel N)
Echo Canceller (N), where 0 < N < 31
Programmable Bypass
Figure 4 - Functional Block Diagram of an Echo Canceller
1.1 Adaptive Filter
The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then
subtracted from Sin. For each group of echo cancellers, the Adaptive Filter is a 1024 tap FIR adaptive filter which is
divided into two sections. Each section contains 512 taps providing 64 ms of echo estimation. In Normal
configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay
configuration, both sections are cascaded to provide 128 ms of echo estimation in channel A. In Back-to-Back
configuration, the first section is used in the receive direction and the second section is used in the transmit
direction for the same channel.
The ZL38070 offers industry leading convergence speeds, both in initial convergence and reconvergence. A
sample test result from G.168-2002 Test 2A can be seen in Figure 5. This test result demonstrates one of the many
conditions where the Zarlink device offer sub 50 ms initial convergence times (G.168 Test 2A, Hybrid 5, 40 ms
delay, ERL=24 dB, Lrin=0 dBm0). Full G.168 test results across all hybrids and test conditions are available
upon request.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Figure 5 - Sample G.168 Test 2A Convergence Result
1.2 Double-Talk Detector
Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.
When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter
coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller
continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the
relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition:
Lsin > Lrin + 20log10(DTDT)
where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0.
A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo
return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence
speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is
reduced by a factor of 2Slow relative to normal convergence for non-zero values of Slow. If Slow equals zero,
adaptation is halted completely.
In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the
DTDT is set internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The EVP allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
DTDT(hex) = hex(DTDT(dec) * 32768)
where 0 < DTDT(dec) < 1
Example:For DTDT = 0.5625 (-5 dB), the hexadecimal value becomes hex(0.5625 * 32768) = 4800hex
1.3 Path Change Detector
Integrated into the EVP is a Path Change Detector. This permits fast reconvergence when a major change occurs
in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is
achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,
the existing echo channel estimate will also be cleared (i.e., the adaptive filter will be filled with zeroes) upon
detection of a major path change.
1.4 Non-Linear Processor (NLP)
After echo cancellation, there is always a small amount of residual echo which may still be audible. The EVP uses
Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal
as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be
calculated by the following equation:
TSUP = Lrin + 20log10(NLPTHR)
where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed
in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the
following equation:
NLPTHR(hex) = hex(NLPTHR(dec) * 32768)
where 0 < NLPTHR(dec) < 1
When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal.
To prevent a perceived decrease in background noise due to the activation of the NLP, a spectrally-shaped comfort
noise, equivalent in power level to the background noise, is injected. This keeps the perceived noise level constant.
Consequently, the user does not hear the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted
that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
The Advanced NLP uses an exponential noise ramping scheme to quickly and more accurately estimate the
background noise level. The NLINC register is used to set the ramping speed. A lower value will give faster
ramping. The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this
value will scale the injected noise level down, conversely, raising the value will scale the comfort noise up.
IMPORTANT NOTE: The Noise Scaling register has been pre-programmed with G.168 compliant values. Changing
this value may result in undesirable comfort noise performance and G.168 test failures.
The Advanced NLP also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for
background noise. These features can be disabled by setting the NLRun1 bit in Control Register 3 to “0”.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
1.5 Disable Tone Detector
The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21 Hz) sine
wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every
450 ms (±25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the
Tone Detector will trigger.
The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between
0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone
Detector will trigger.
Each EVP has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid
disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic
high and an interrupt is generated (i.e., IRQ pin low). Refer to Figure 6 and to the Interrupts section.
Tone Detector
Tone Detector
Rin
Sin
ECA
Status reg
TD bit
Echo Canceller A
Tone Detector
Tone Detector
Rin
Sin
ECB
Status reg
TD bit
Echo Canceller B
Figure 6 - Disable Tone Detection
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to
maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the
signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the
frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is
generated (i.e., IRQ pin low).
The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per
channel basis. When the PHDis bit is set to “1”, G.164 tone disable requirements are selected.
In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the
Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors
internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by
setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the
interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a
given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
1.6 Instability Detector
In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause
stability problems in the Adaptive Filter. This instability can result in variable pitched ringing or oscillation. Should
this ringing occur, the Instability Detector will activate and suppress the oscillations.
The Instability Detector is activated by setting the RingClr bit in Control Register 3 to “1”.
1.7 Narrow Band Signal Detector (NBSD)
Single or dual frequency tones (i.e., DTMF tones) present in the receive input (Rin) of the echo canceller for a
prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is
designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When
narrow band signals are detected, adaptation is halted but the echo canceller continues to cancel echo.
The NBSD will be active regardless of the EVP functional state. However the NBSD can be disabled by setting the
NBDis bit to “1” in Control Register 2.
1.8 Offset Null Filter
Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC
component, each EVP incorporates Offset Null filters in both Rin and Sin inputs.
The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.
1.9 Adjustable Level Pads
Each canceller provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be
adjusted both inside and outside the echo path. Each signal level may be independently scaled with anywhere from
+9 dB to -12 dB level, in 3 dB steps. Level values are set using the Gains register.
CAUTION: Gain adjustment can help interface the ZL38070 to a particular system in order to provide optimum echo
cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels
and slow convergence. Exercise great care when adjusting these values. Also, due to internal signal routings in
Back to Back mode, it is not recommended that gain adjustments be used on Rin or Sout in this mode.
The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of
attenuation at Rin, and override the values in the Gains register.
1.10
ITU-T G.168 Compliance
The ZL38070 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes
(i.e., Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.
The ZL38070 core has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The
ZL38070 core was classified as “carrier grade” echo canceller.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
2.0 EVP Configuration
The EVP architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers
which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB). They can be set in
three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 7, 8 and 9.
2.1 Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 7, providing 64 milliseconds of echo cancellation in two channels simultaneously.
channel A
Sout
Sin
+
-
echo
path A
Adaptive
Filter (64 ms)
channel A
Rout
Rin
PORT2
PORT1
ECA
channel B
+
-
echo
Adaptive
path B
Filter (64 ms)
channel B
ECB
Figure 7 - Normal Device Configuration (64 ms)
2.2 Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 8. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo
cancellation is required.
Sout
+
Sin
-
Adaptive
echo
path
echo
path
Filter (64 ms)
Adaptive
Filter (64 ms)
-
+
Rout
Rin
PORT1
PORT2
ECA
ECB
Figure 8 - Back-to-Back Device Configuration (64 ms)
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo
Canceller A and Echo Canceller B for a given group of echo canceller. Table 3 shows the 16 groups of 2 cancellers
that can be configured into Back-to-Back.
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a
transmission device or between two codecs for echo control on analog trunks.
2.3 Extended Delay Configuration
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 9. This configuration uses only one timeslot on PORT1 and PORT2 and
the second timeslot normally associated with ECB contains quiet code.
channel A
Sin
+
Sout
-
echo
Adaptive Filter
(128 ms)
path A
channel A
ECA
Rout
Rin
PORT1
PORT2
Figure 9 - Extended Delay Configuration (128 ms)
Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.
For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control
Register 1, Bit 0 must always be set to zero.
Table 3 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity.
3.0 Echo Canceller Functional States
Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.
3.1 Mute
In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which
is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with
quiet code.
SIGN/
MAGNITUDE
µ-Law
CCITT (G.711)
LINEAR
16 bits
2’s complement
µ-Law
A-Law
D5hex
A-Law
+Zero
0000hex
80hex
FFhex
(quiet code)
Table 1 - Quiet PCM Code Assignment
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be
“0”. Refer to Figure 4 and to Control Register 2 for bit description.
3.2 Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125 µs) in order to properly clear the filter.
3.3 Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
3.4 Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller
to model the echo return path characteristics in order to cancel echo. This is the normal operating state.
The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:
MuteS, MuteR, Bypass and AdaptDis. Refer to 8.0, “EVP Register Description“ on page 28 for details.
4.0 Echo Voice Processor (EVP) Throughput Delay
The throughput delay of the EVP varies according to the device configuration. For all device configurations, Rin to
Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and
Sin to Sout paths have a delay of two frames.
5.0 Serial PCM I/O channels
There are four TDM I/O streams, each with channels numbered from 0 to 31. One input stream is for Receive (Rin)
channels, and the other input stream is for Send (Sin) channels. Likewise, two output streams is for Rout PCM
channels, and Sout PCM channels. See Figure 10 for channel allocation.
5.1 Serial Data Interface Timing
The ZL38070 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.
The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The EVP automatically detects the presence
of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of
the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way
into the bit cell (See Figure 14). In GCI format, every second rising edge of the C4i clock marks the bit boundary,
and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 15).
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
125 µsec
F0i
ST-BUS
F0i
GCI interface
Rin/Sin
Channel 0
Channel 1
Channel 30
Channel 31
Rout/Sout
Note: Refer to Figure 14 and Figure 15 for timing details.
Figure 10 - ST-BUS and GCI Interface Channel Assignment for 2 Mb/s Data Streams
6.0 Memory Mapped Control and Status registers
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 0A0hex to 0BFhex and interfaces to
PCM channel #5 on all serial PCM I/O streams.
As illustrated in Table 4, the “per channel” registers provide independent control and status bits for each echo
canceller. Figure 11 shows the memory map of the control/status register blocks for all echo cancellers of the EVP.
Each internal echo canceller has four pages of registers. Page access control is done through address lines A11
and A12. The majority of registers are located on page 0 (A11=0, A12=0). Figure 11 shows which page each of the
relevant registers are mapped to respectively. Table 2 shows how the memory pages are related to address lines
A11 and A12.
Page
A12
A11
0
1
2
3
0
0
1
1
0
1
0
1
Table 2 - Memory Page Selection
When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control
Register 2 of the selected group of echo cancellers require special care. Refer to the EVP Register description
section.
Table 3 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
6.1 Normal Configuration
For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
Group
Channels
Group
Channels
0
1
2
3
4
5
6
7
0, 1
2, 3
8
16, 17
18, 19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31
9
4, 5
10
11
12
13
14
15
6, 7
8, 9
10, 11
12, 13
14, 15
Table 3 - Group and Channel Allocation
6.2 Extended Delay Configuration
For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B
(Channel 5) will carry quiet code.
6.3 Back-to-Back Configuration
For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B
(Channel 11) will carry quiet code.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
0000h --> 001Fh
0020h --> 003Fh
Channel 0, ECA Ctrl/Stat Registers
Channel 1, ECB Ctrl/Stat Registers
Group 0
Echo
Cancellers
Registers
0040h --> 005Fh
0060h --> 007Fh
Channel 2, ECA Ctrl/Stat Registers
Channel 3, ECB Ctrl/Stat Registers
Group 1
Echo
Cancellers
Registers
Groups 2 --> 14
Echo Cancellers
Registers
03C0h --> 03DFh
03E0h --> 03FFh
Channel 30, ECA Ctrl/Stat Registers
Group 15
Echo
Cancellers
Registers
Channel 31, ECB Ctrl/Stat Registers
0400h --> 040Fh
0410h
Main Control Registers <15:0>
Interrupt FIFO Register
Test Register
0411h
0412h ---> FFFFh
Reserved Test Register
Figure 11 - Memory Mapping
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Base Address +
Echo Canceller A
Register Name
Base Address +
Echo Canceller B
MS
LS
MS
LS
Page
Page
Register Name
Byte
Byte
Byte Byte
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
2
2
2
2
3
3
3
-
-
00h
01h
02h
04h
06h
07h
08h
09h
0Ch
0Eh
10h
12h
13h
14h
16h
18h
1Ah
1Ch
1Eh
1Fh
04h
06h
10h
18h
1Ah
1Ch
02h
04h
0Ch
Control Reg 1
Control Reg 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
2
2
2
2
3
3
3
-
-
20h
21h
22h
24h
26h
27h
28h
29h
2Ch
2Eh
30h
32h
33h
34h
36h
38h
3Ah
3Ch
3Eh
3Fh
24h
26h
10h
38h
3Ah
3Ch
22h
24h
2Ch
Control Reg 1
Control Reg 2
-
Status Reg
-
Status Reg
-
-
Flat Delay Reg
-
-
Flat Delay Reg
Decay Step Size Reg
Decay Step Number
Control Reg 3
Decay Step Size Reg
Decay Step Number
Control Reg 3
-
-
-
-
-
-
Control Reg 4
Control Reg 4
0Dh
0Fh
11h
-
Rin Peak Detect Reg
Sin Peak Detect Reg
Error Peak Detect Reg
Path Change Timer
Path Change Sensitivity
DTDT/ERL
2Dh
2Fh
31h
-
Rin Peak Detect Reg
Sin Peak Detect Reg
Error Peak Detect Reg
Path Change Timer
Path Change Sensitivity
DTDT/ERL
-
-
15h
17h
19h
1Bh
1Dh
-
35h
37h
39h
3Bh
3Dh
-
ERLLOW
ERLLOW
NLP Threshold
NLP Threshold
Step Size, MU
Step Size, MU
Gain Pad Control
NLP Threshold 2
RIN Low Power Threshold
Estimated Cancellation
Residual Error Signal
NLINC
Maximum Comfort Noise
NLP Ramp-out Speed
NLP Ramp-in Speed
Noise Level Estimate
NLP Gain Factor
Gain Pad Control
NLP Threshold 2
RIN Low Power Threshold
Estimated Cancellation
Residual Error Signal
NLINC
Maximum Comfort Noise
NLP Ramp-out Speed
NLP Ramp-in Speed
Noise Level Estimate
NLP Gain Factor
-
-
05h
07h
11h
19h
1Bh
1Dh
03h
05h
0Dh
25h
27h
11h
39h
3Bh
3Dh
23h
25h
2Dh
Noise Level Scaling
Factor
Noise Level Scaling
Factor
Table 4 - Memory Mapping of Per Channel Control and Status Registers
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
6.4 Power Up Sequence
On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put each EVP in power
down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16
Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.
When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µs for the PLL to
lock. C4i and F0i can be active during this period. At this point, the echo canceller must have the internal registers
reset to an initial state. This is accomplished by one of two methods. The user can either issue a second hardware
reset or perform a software reset. A second hardware reset is performed by driving the RESET pin low for at least
500 ns and no more than 1500 ns before being released. A software reset is accomplished by programming a “1” to
each of the PWUP bits in the Main Control Registers, waiting 250 µs (2 frames) and then programming a “0” to
each of the PWUP bits.
The user must then wait 500 µs for the PLL to relock. Once the PLL has locked, the user can power up the 16
groups of echo cancellers individually by writing a “1” into the PWUP bit in Main Control Register of each echo
canceller group.
For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute
their initialization routine. The initialization routine sets their registers, Base Address+00hex to Base Address+3Fhex
,
to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization
routine to execute properly.
Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00hex
to Base Address+3Fhex, for the specific application.
System Powerup
Reset Held Low
Delay 100 µs
Reset High
MCLK Active
Delay 500µs
Hardware
Software
Reg. Reset
Reset Low
PWUP to “1”
Delay 1000 ns
Reset High
Delay 250 µs
PWUP to “0”
Delay 500 µs
ECAN Ready
Figure 12 - Power Up Sequence Flow Diagram
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
6.5 Power Management
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
on page 42 for description.
The typical power consumption can be calculated with the following equation:
PC = 9 * Nb_of_groups + 3.6, in mW
where 0 ≤ Nb_of_groups ≤ 16.
6.6 Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting
the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.
Since the Narrow Band Detector is “ON” regardless of the functional state of the Echo Canceller it is recommended
that the Echo Cancellers are reset before any call progress tones are applied.
6.7 Interrupts
The EVP provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable is
detected and released.
Although each EVP may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate application-specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt
when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Table 4 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the EVP. To provide more flexibility, the MTDBI
(bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or unmasked
from generating an interrupt on a per channel basis. Refer to the Registers Description section on page 42.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
7.0 JTAG Support
The EVP JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-
for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
7.1 Test Access Port (TAP)
The TAP provides access to many test functions of the EVP. It consists of four input pins and one output pin. The
following pins are found on the TAP.
•
•
•
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
VDD1 when it is not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VDD1 when it is not driven from an external source.
•
•
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS
.
7.2 Instruction Register
In accordance with the IEEE 1149.1 standard, the EVP uses public instructions. The JTAG Interface contains a 3-bit
instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
7.3 Test Data Registers
As specified in IEEE 1149.1, each of the Echo Voice Processor’s JTAG Interface contains three test data registers:
•
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of each EVP core logic.
•
•
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
8.0 EVP Register Description
Page 0
Power-up
R/W Address:
ECA: Control Register 1
00hex
A12=0 00hex + Base Address
A11=0
Bit 7
Bit 6
Bit 5
BBM
Bit 4
PAD
Bit 3
Bit 2
Bit 1
0
Bit 0
Reset
INJDis
Bypass
AdpDis
ExtDis
Functional Description of Register Bits
Reset
When high, the power-up initialization is executed. This presets all register bits including this bit
and clears the Adaptive Filter coefficients.
INJDis
BBM
When high, the noise injection process is disabled. When low noise injection is enabled.
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers (Control Register 1) of the same group to
the same logic value to avoid conflict.
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive
Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on
both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
When high, Echo Cancellers A and B of the same group are internally cascaded into one
128 ms echo canceller. When low, Echo Cancellers A and B of the same group operate
independently.
AdpDis
0
ExtDl
Page 0
Power-up
02hex
R/W Address:
ECB: Control Register 1
A12=0 20hex + Base Address
A11=0
Bit 7
Bit 6
Bit 5
BBM
Bit 4
PAD
Bit 3
Bit 2
Bit 1
1
Bit 0
0
Reset
INJDis
Bypass
AdpDis
Functional Description of Register Bits
Reset
When high, the power-up initialization is executed which presets all register bits including this
bit and clears the Adaptive Filter coefficients.
INJDis
BBM
When high, the noise injection process is disabled. When low, noise injection is enabled.
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers (Control Register 1) of the same group to
the same logic value to avoid conflict.
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive
Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on
both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.
AdpDis
1
0
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
R/W Address:
Page 0
ECA: Control Register 2
ECB: Control Register 2
01hex + Base Address
Power-up
00hex
A12=0
A11=0
R/W Address:
21hex + Base Address
Bit 7
TDis
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
HPFDis
Bit 1
Bit 0
PHDis
NLPDis
AutoTD
NBDis
MuteS
MuteR
Functional Description of Register Bits
TDis
When high, tone detection is disabled. When low, tone detection is enabled. When both Echo
Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are
put into Power Down mode.
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of
the presence/absence of periodic phase reversals. When low, the tone detectors will trigger
only upon the presence of a 2100 Hz tone with periodic phase reversals.
PHDis
NLPDis
AutoTD
When high, the non-linear processor is disabled. When low, the non-linear processors function
normally. Useful for G.165 conformance testing.
When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the
presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state of the
2100 Hz tone detectors.
NBDis
When high, the narrow-band detector is disabled. When low, the narrow-band detector is
enabled.
HPFDis
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low,
the offset nulling filters are active and will remove DC offsets on PCM input signals.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
MuteS
MuteR
Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one
immediately after another. The two writes must be separated by at least 350 ns and no more than 20 us.
Read Address:
Page 0
ECA: Status Register
ECB: Status Register
02hex + Base Address
Power-up
N/A
A12=0
A11=0
Read Address:
22hex + Base Address
Bit 7
Bit 6
TD
Bit 5
DTDet
Bit 4
Bit 3
Bit 2
ACTIVE
Bit 1
TDG
Bit 0
NB
Reserved
Reserved
Reserved
Functional Description of Register Bits
Reserved Reserved bit.
TD
DTDet
Logic high indicates the presence of a 2100 Hz tone.
Logic high indicates the presence of a double-talk condition.
Reserved
Reserved bit.
Reserved Reserved bit.
ACTIVE
TDG
Logic high indicates that the level on Rin has exceeded the LP threshold.
Tone detection status bit gated with the AutoTD bit. (Control Register 2)
Logic high indicates that AutoTD has been enabled and the tone detector has detected the
presence of a 2100 Hz tone.
Logic high indicates the presence of a narrow-band signal on Rin.
NB
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
R/W Address:
Page 0
ECA: Flat Delay Register (FD)
ECB: Flat Delay Register (FD)
04hex + Base Address
Power-up
00hex
A12=0
A11=0
R/W Address:
24hex + Base Address
Bit 7
FD7
Bit 6
FD6
Bit 5
FD5
Bit 4
FD4
Bit 3
FD3
Bit 2
FD2
Bit 1
FD1
Bit 0
FD0
R/W Address:
Page 0
ECA: Decay Step Number Register (NS)
ECB: Decay Step Number Register (NS)
07hex + Base Address
Power-up
00hex
A12=0
A11=0
R/W Address:
27hex + Base Address
Bit 7
SS7
Bit 6
SS6
Bit 5
SS5
Bit 4
SS4
Bit 3
SS3
Bit 2
SS2
Bit 1
SS1
Bit 0
SS0
R/W Address:
Page 0
ECA: Decay Step Size Control Register (SSC)
ECB: Decay Step Size Control Register (SSC)
06hex + Base Address
Power-up
04hex
A12=0
A11=0
R/W Address:
26hex + Base Address
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
SSC2
Bit 1
SSC1
Bit 0
SSC0
Amplitude of MU
FIR Filter Length (512 or 1024 taps)
1.0
Step Size (SS)
Flat Delay (FD7-0
)
2-16
Time
Number of Steps (NS7-0
)
Figure 13 - The MU Profile
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Functional Description of Register Bits
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS
adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the
performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the
echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo
impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby
improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one
tap is equivalent to 125 µs (64 ms/512 taps).
FD7-0 Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2-16). The
delay is defined as FD7-0 x 8 taps. For example; If FD7-0 = 5, then MU=2-16 for the first 40 taps of the
echo canceller FIR filter. The valid range of FD7-0 is: 0 ≤ FD7-0 ≤ 64 in normal mode and 0 ≤ FD7-0
≤
128 in extended-delay mode. The default value of FD7-0 is zero.
SSC2-0 Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay
of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter,
where SS = 4 x2SSC . For example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of
2-0
the FIR filter. The default value of SSC2-0 is 04hex
.
NS7-0 Decay Step Number: This register defines the number of steps to be used for the decay of MU where each
step has a period of SS taps (see SSC2-0). The start of the exponential decay is defined as: Filter
Length (512 or 1024) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2SSC
.
2-0
For example; If NS7-0=4 and SSC2-0=4, then the exponential decay start value is 512 - [NS7-0 x SS] =
512 - [4 x (4x24)] = 256 taps for a filter length of 512 taps.
R/W Address:
Page 0
ECA: Control Register 3
ECB: Control Register 3
08hex + Base Address
Power-up
DBhex
A12=0
A11=0
R/W Address:
28hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PathClr
Bit 1
Bit 0
Reserve
Reserve
NLRun1
RingClr
Reserve
PathDet
Reserve
Functional Description of Register Bits
Reserved Reserved bit.
Reserved Reserved bit.
NLRun1
When high, the comfort noise level estimator actively rejects uncancelled echo as being
background noise. When low, the noise level estimator makes no such distinction.
RingClr
When high, the instability detector is activated. When low, the instability detector is disabled.
Reserve
PathClr
Reserved bit. Must always be set to one for normal operation.
When high, the current echo channel estimate will be cleared and the echo canceller will enter
fast convergence mode upon detection of a path change. When low, the echo canceller will
keep the current path estimate but revert to fast convergence mode upon detection of a path
change. Note: this bit is ignored if PathDet is low.
PathDet
When high, the path change detector is activated. When low, the path change detector is
disabled.
Reserved Reserved bit.
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Zarlink Semiconductor Inc.
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Data Sheet
R/W Address:
Page 0
ECA: Control Register 4
ECB: Control Register 4
09hex + Base Address
Power-up
54hex
A12=0
A11=0
R/W Address:
29hex + Base Address
Bit 7
0
Bit 6
SD2
Bit 5
SD1
Bit 4
SD0
Bit 3
0
Bit 2
Slow2
Bit 1
Bit 0
Slow1
Slow0
Functional Description of Register Bits
0
Must be set to zero.
SupDec
These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast
convergence state following a path change, Reset or Bypass operation. A value of zero will
keep the echo canceller in fast convergence indefinitely.
0
Must be set to zero.
Slow
Slow convergence mode speed adjustment.(Bits Slow2, Slow1,Slow0)
For Slow = 1, 2, ..., 7, slow convergence speed is reduced by a factor of 2Slow as compared to
normal adaptation.
For Slow = 0, no adaptation occurs during slow convergence.
Read Address:
Page 0
ECA: Rin Peak Detect Register 2 (RP)
ECB: Rin Peak Detect Register 2 (RP)
0Dhex + Base Address
Power-up
N/A
A12=0
A11=0
Read Address:
2Dhex + Base Address
Bit 7
RP15
Bit 6
RP14
Bit 5
RP13
Bit 4
RP12
Bit 3
RP11
Bit 2
RP10
Bit 1
RP9
Bit 0
RP8
Read Address:
Page 0
ECA: Rin Peak Detect Register 1 (RP)
ECB: Rin Peak Detect Register 1 (RP)
0Chex + Base Address
Power-up
N/A
A12=0
A11=0
Read Address:
2Chex + Base Address
Bit 7
RP7
Bit 6
RP6
Bit 5
Bit 4
Bit 3
Bit 2
RP2
Bit 1
Bit 0
RP5
RP4
RP3
RP1
RP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The
information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo
canceller. The high byte is in Register 2 and the low byte is in Register 1.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Read Address:
Page 0
ECA: Sin Peak Detect Register 2 (SP)
ECB: Sin Peak Detect Register 2 (SP)
0Fhex + Base Address
Power-up
N/A
A12=0
A11=0
Read Address:
2Fhex + Base Address
Bit 7
SP15
Bit 6
SP14
Bit 5
SP13
Bit 4
SP12
Bit 3
SP11
Bit 2
SP10
Bit 1
SP9
Bit 0
SP8
R/W Address:
Page 0
ECA: Sin Peak Detect Register 1 (SP)
ECB: Sin Peak Detect Register 1 (SP)
0Ehex + Base Address
Power-up
N/A
A12=0
A11=0
R/W Address:
2Ehex + Base Address
Bit 7
SP7
Bit 6
SP6
Bit 5
Bit 4
Bit 3
Bit 2
SP2
Bit 1
Bit 0
SP5
SP4
SP3
SP1
SP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information
is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The
high byte is in Register 2 and the low byte is in Register 1.
Read Address:
Page 0
ECA: Error Peak Detect Register 2 (EP)
ECB: Error Peak Detect Register 2 (EP))
11hex + Base Address
Power-up
N/A
A12=0
A11=0
Read Address:
21hex + Base Address
Bit 7
EP15
Bit 6
EP14
Bit 5
EP13
Bit 4
EP12
Bit 3
EP11
Bit 2
EP10
Bit 1
EP9
Bit 0
EP8
Read Address:
Page 0
ECA:Error Peak Detect Register 1 (EP)
ECB: Error Peak Detect Register 1 (EP)
10hex + Base Address
Power-up
N/A
A12=0
A11=0
Read Address:
30hex + Base Address
Bit 7
EP7
Bit 6
EP6
Bit 5
Bit 4
Bit 3
Bit 2
EP2
Bit 1
Bit 0
EP5
EP4
EP3
EP1
EP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16
bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller.
R/W Address:
Page 0
ECA: Path Change Timer (PATHTMR)
ECB: Path Change Timer (PATHTMR)
12hex + Base Address
Power-up
10hex
A12=0
A11=0
R/W Address:
32hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PTMR2
Bit 1
Bit 0
PTMR7
PTMR6
PTMR5
PTMR4
PTMR3
PTMR1
PTMR0
Functional Description of Register Bits
Negative ERLE time required to declare a path change. Raising this value decreases the path change
sensitivity.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
R/W Address:
Page 0
ECA: Path Change Sensitivity (PTHSENS)
ECB: Path Change Sensitivity (PTHSENS)
13hex + Base Address
Power-up
41hex
A12=0
A11=0
R/W Address:
33hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PSENS2
Bit 1
Bit 0
PSENS7
PSENS6
PSENS5
PSENS4
PSENS3
PSENS1
PSENS0
Functional Description of Register Bits
This register sets the negative ERLE sensitivity value. Raising this value decreases path change sensitivity.
ECA: Double-Talk Detection Threshold Register 2
(DTDT or ERL)
R/W Address:
Page 0
15hex + Base Address
Power-up
48hex
A12=0
A11=0
ECB: Double-Talk Detection Threshold Register 2
R/W Address:
(DTDT or ERL)
35hex + Base Address
Bit 7
DTDT15
Bit 6
DTDT14
Bit 5
DTDT13
Bit 4
DTDT12
Bit 3
DTDT11
Bit 2
DTDT10
Bit 1
DTDT9
Bit 0
DTDT8
ECA: Double-Talk Detection Threshold Register 1
(DTDT or ERL)
R/W Address:
Page 0
14hex + Base Address
Power-up
00hex
A12=0
A11=0
ECB: Double-Talk Detection Threshold Register 1
R/W Address:
(DTDT or ERL)
34hex + Base Address
Bit 7
DTDT7
Bit 6
DTDT6
Bit 5
Bit 4
Bit 3
Bit 2
DTDT2
Bit 1
DTDT1
Bit 0
DTDT0
DTDT5
DTDT4
DTDT3
Functional Description of Register Bits
This register should reflect the minimum return echo level (SIN) relative to ROUT expected in the system.
The default value of 4800hex= 0.5625 represents a path loss of -5 dB. This value sets the high-level double-
talk detection threshold (DTDT). The information is in 16 bit 2’s complement linear coded format presented
in two 8 bit registers for each echo canceller. The maximum value is 7FFFhex = 0.9999 or 0 dB.
R/W Address:
Page 0
ECA: SUP Lower Limit 2 (ERLLOW)
ECB: SUP Lower Limit 2 (ERLLOW)
17hex + Base Address
Power-up
04hex
A12=0
A11=0
R/W Address:
37hex + Base Address
Bit 7
ERLW15
Bit 6
ERLW14
Bit 5
ERLW13
Bit 4
ERLW12
Bit 3
ERLW11
Bit 2
ERLW10
Bit 1
ERLW9
Bit 0
ERLW8
R/W Address:
Page 0
ECA: SUP Lower Limit 1 (ERLLOW)
ECB: SUP Lower Limit 1 (ERLLOW)
16hex + Base Address
Power-up
00hex
A12=0
A11=0
R/W Address:
36hex + Base Address
Bit 7
ERLW7
Bit 6
ERLW6
Bit 5
Bit 4
Bit 3
Bit 2
ERLW2
Bit 1
ERLW1
Bit 0
ERLW0
ERLW5
ERLW4
ERLW3
Functional Description of Register Bits
This register sets the lower limit on SUP, which marks the region below which fast convergence always
occurs (provided a signal is present). If ERLLOW is set to the DTDT starting value (4800hex), the echo
canceller will remain in fast convergence mode and will not switch to slow convergence. The information is
in 16 bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
ECA: Non-Linear Processor Threshold Register 2
(NLPTHR)
R/W Address:
Page 0
19hex + Base Address
Power-up
0Chex
A12=0
A11=0
ECB: Non-Linear Processor Threshold Register 2
R/W Address:
(NLPTHR)
39hex + Base Address
Bit 7
NLP15
Bit 6
NLP14
Bit 5
NLP13
Bit 4
NLP12
Bit 3
NLP11
Bit 2
NLP10
Bit 1
NLP9
Bit 0
NLP8
ECA: Non-Linear Processor Threshold Register 1
(NLPTHR)
R/W Address:
Page 0
18hex + Base Address
Power-up
E0hex
A12=0
A11=0
R/W Address:
ECB: Non-Linear Processor Threshold Register 1
(NLPTHR)
38hex + Base Address
Bit 7
NLP7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NLP2
Bit 1
NLP1
Bit 0
NLP0
NLP6
NLP5
NLP4
NLP3
Functional Description of Register Bits
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16
bit 2’s complement linear value defaults to 0CE0hex = 0.1 or -20.0 dB. The maximum value is 7FFFhex
0.9999 or 0 dB.
=
R/W Address:
Page 0
ECA: Adaptation Step Size Register 2 (MU)
ECB: Adaptation Step Size Register 2 (MU)
1Bhex + Base Address
Power-up
40hex
A12=0
A11=0
R/W Address:
3Bhex + Base Address
Bit 7
MU15
Bit 6
MU14
Bit 5
MU13
Bit 4
MU12
Bit 3
MU11
Bit 2
MU10
Bit 1
MU9
Bit 0
MU8
R/W Address:
Page 0
ECA: Adaptation Step Size Register 1 (MU)
ECB: Adaptation Step Size Register 1 (MU)
1Ahex + Base Address
Power-up
00hex
A12=0
A11=0
R/W Address:
3Ahex + Base Address
Bit 7
MU7
Bit 6
MU6
Bit 5
Bit 4
Bit 3
Bit 2
MU2
Bit 1
MU1
Bit 0
MU0
MU5
MU4
MU3
Functional Description of Register Bits
This register allows the user to program the level of MU, which is the LMS filter step size. Increasing this
value can speed up convergence times, but can also potentially decrease VEC stability. MU is a 16 bit 2’s
complement value which defaults to 4000hex = 1.0 The maximum value is 7FFFhex or 1.9999 decimal. The
high byte is in Register 2 and the low byte is in Register 1.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
R/W Address:
Page 0
ECA: Gains Register 2
ECB: Gains Register 2
1Dhex + Base Address
Power-up
40hex
A12=0
A11=0
R/W Address:
3Dhex + Base Address
Bit 7
0
Bit 6
Rin2
Bit 5
Rin1
Bit 4
Rin0
Bit 3
0
Bit 2
Rout2
Bit 1
Rout1
Bit 0
Rout0
R/W Address:
Page 0
ECA: Gains Register 1
ECB: Gains Register 1
1Chex + Base Address
Power-up
00hex
A12=0
A11=0
R/W Address:
3Chex + Base Address
Bit 7
0
Bit 6
Sin2
Bit 5
Bit 4
Bit 3
0
Bit 2
Sout2
Bit 1
Bit 0
Sin1
Sin0
Sout1
Sout0
Functional Description of Register Bits
This register is used to select gain values on RIN, ROUT, SIN and SOUT.
Gains is split into four groups of four bits. Each group maps to a different signal port (as indicated above),
and has three gain bits. The following table indicates how these gain bits are used:
Bit2 Bit1 Bit0 Gain Level
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
+9 dB
+6 dB)
+3 dB
0 dB (default)
-3 dB
0
0
0
0
-6 dB
-9 dB
-12 dB
Note that the -12 dB PAD bit in Control Register 1 provides 12 dB of attenuation in the Rin to Rout path, and
will override the settings in Gains.
R/W Address:
Page 0
ECA: NLP Threshold 2 (NLPTHR2)
ECB: NLP Threshold 2 (NLPTHR2)
1Ehex + Base Address
Power-up
08hex
A12=0
A11=0
R/W Address:
3Ehex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NLPTH2
Bit 1
Bit 0
NLPTH7
NLPTH6
NLPTH5
NLPTH4
NLPTH3
NLPTH1
NLPTH0
Functional Description of Register Bits
This register is used to force the NLP off when very small signals exist on RIN. NLP is forced off if RIN is
below NLPTHR2 << 4. Raising this value can help prevent NLP masking at very low signal levels.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
R/W Address:
Page 0
ECA: Low Power Threshold (LPTHRES)
ECB: Low Power Threshold (LPTHRES)
1Fhex + Base Address
Power-up
08hex
A12=0
A11=0
R/W Address:
3Fhex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LPTH2
Bit 1
Bit 0
LPTH7
LPTH6
LPTH5
LPTH4
LPTH3
LPTH1
LPTH0
Functional Description of Register Bits
This register is used to control the RIN low power threshold. The threshold is set by LPTHRES << 4 and is
compared to RIN. Raising LPTHRES makes the VEC less responsive to very small signals.
R/W Address:
Page 1
ECA: Estimated Echo Cancellation Level 2 (SUP)
ECB: Estimated Echo Cancellation Level 2 (SUP)
05hex + Base Address
Power-up
N/A
A12=0
A11=1
R/W Address:
25hex + Base Address
Bit 7
SUP15
Bit 6
SUP14
Bit 5
SUP13
Bit 4
SUP12
Bit 3
SUP11
Bit 2
SUP10
Bit 1
SUP9
Bit 0
SUP8
Read Address:
Page 1
ECA: Estimated Echo Cancellation Level 1 (SUP)
ECB: Estimated Echo Cancellation Level 1 (SUP)
04hex + Base Address
Power-up
N/A
A12=0
A11=1
Read Address:
24hex + Base Address
Bit 7
SUP7
Bit 6
SUP6
Bit 5
Bit 4
Bit 3
Bit 2
SUP2
Bit 1
SUP1
Bit 0
SUP0
SUP5
SUP4
SUP3
Functional Description of Register Bits
This register is the estimate of the level of error as compared to RUN. SUP is used to detect low-level
double-talk and to select convergence speed (fast or slow). This register is a 16 bit 2’s complement linear
value and defaults to 4800hex = 0 dB. As cancellation progresses, this value decreases with its lower limit
set by ERLLOW. It is reset after a path change or reset/bypass operation.
Read Address:
Page 1
ECA: Residual Error Signal 2 (ERR)
ECB: Residual Error Signal 2 (ERR)
07hex + Base Address
Power-up
N/A
A12=0
A11=1
Read Address:
27hex + Base Address
Bit 7
ERR15
Bit 6
ERR14
Bit 5
ERR13
Bit 4
ERR12
Bit 3
ERR11
Bit 2
ERR10
Bit 1
ERR9
Bit 0
ERR8
Read Address:
Page 1
ECA: Residual Error Signal 1 (ERR)
ECB: Residual Error Signal 1 (ERR)
06hex + Base Address
Power-up
N/A
A12=0
A11=1
Read Address:
26hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ERR2
Bit 1
Bit 0
ERR0
ERR7
ERR6
ERR5
ERR4
ERR3
ERR1
Functional Description of Register Bits
This register represents the error signal after the filter and prior to NLP. This register is a 16 bit 2’s
complement linear value.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
R/W Address:
Page 2
ECA: Noise Level Control 2 (NLINC)
ECB: Noise Level Control 2 (NLINC)
11hex + Base Address
Power-up
00hex
A12=1
A11=0
R/W Address:
31hex + Base Address
Bit 7
NLINC15
Bit 6
NLINC14
Bit 5
NLINC13
Bit 4
NLINC12
Bit 3
NLINC11
Bit 2
NLINC10
Bit 1
NLINC9
Bit 0
NLINC8
R/W Address:
Page 2
ECA: Noise Level Control 1 (NLINC)
ECB: Noise Level Control 1 (NLINC)
10hex + Base Address
Power-up
04hex
A12=1
A11=0
R/W Address:
30hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NLINC2
Bit 1
Bit 0
NLINC7
NLINC6
NLINC5
NLINC4
NLINC3
NLINC1
NLINC0
Functional Description of Register Bits
Noise level estimator ramping rate. A lower value will give faster ramping. The default value of 4hex will
provide G.168 compliance.
R/W Address:
Page 2
ECA: Maximum Comfort Noise Level 2 (NLIMIT)
ECB: Maximum Comfort Noise Level 2 (NLIMIT)
19hex + Base Address
Power-up
40hex
A12=1
A11=0
R/W Address:
39hex + Base Address
Bit 7
Bit 6
Bit 5
NLIMIT13
Bit 4
NLIMIT12
Bit 3
NLIMIT11
Bit 2
NLIMIT10
Bit 1
NLIMIT9
Bit 0
NLIMIT8
NLIMIT15 NLIMIT14
R/W Address:
Page 2
ECA: Maximum Comfort Noise Level 1 (NLIMIT)
ECB: Maximum Comfort Noise Level 1 (NLIMIT)
18hex + Base Address
Power-up
00hex
A12=1
A11=0
R/W Address:
38hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NLIMIT2
Bit 1
Bit 0
NLIMIT7
NLIMIT6
NLIMIT5
NLIMIT4
NLIMIT3
NLIMIT1
NLIMIT0
Functional Description of Register Bits
This register controls the maximum comfort noise injection value that the VEC is able to use. This register is
a 16-bit linear value.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
R/W Address:
Page 2
ECA: NLP Ramp-out Rate 2 (RAMPOUT)
ECB: NLP Ramp-out Rate 2 (RAMPOUT)
1Bhex + Base Address
Power-up
3Ehex
A12=1
A11=0
R/W Address:
3Bhex + Base Address
Bit 7
RMPO15
Bit 6
RMPO14
Bit 5
RMPO13
Bit 4
RMPO12
Bit 3
RMPO11
Bit 2
RMPO10
Bit 1
RMPO9
Bit 0
RMPO8
R/W Address:
Page 2
ECA: NLP Ramp-out Rate 1 (RAMPOUT)
ECB: NLP Ramp-out Rate 1 (RAMPOUT)
1Ahex + Base Address
Power-up
00hex
A12=1
A11=0
R/W Address:
3Ahex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RMPO2
Bit 1
Bit 0
RMPO7
RMPO6
RMPO5
RMPO4
RMPO3
RMPO1
RMPO0
Functional Description of Register Bits
This register controls how quickly the NLP turns on. RAMPOUT is normalized to 4000hex = 1 and only
values lower than this are valid. Lowering this value will cause the NLP to turn on more quickly.
R/W Address:
Page 2
ECA: NLP Ramp-in Rate 2 (RAMPIN)
ECB: NLP Ramp-in Rate 2 (RAMPIN)
1Dhex + Base Address
Power-up
41hex
A12=1
A11=0
R/W Address:
3Dhex + Base Address
Bit 7
RMPI15
Bit 6
RMPI14
Bit 5
RMPI13
Bit 4
RMPI12
Bit 3
RMPI11
Bit 2
RMPI10
Bit 1
RMPI9
Bit 0
RMPI8
R/W Address:
Page 2
ECA: NLP Ramp-in Rate 2 (RAMPIN)
ECB: NLP Ramp-in Rate 2 (RAMPIN)
1Chex + Base Address
Power-up
00hex
A12=1
A11=0
R/W Address:
3Chex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RMPI2
Bit 1
Bit 0
RMPI7
RMPI6
RMPI5
RMPI4
RMPI3
RMPI1
RMPI0
Functional Description of Register Bits
This register controls how quickly the NLP turns off. RAMPIN is normalized to 4000hex = 1 and only values
higher than this are valid. Raising this value will cause the NLP to turn off more quickly.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Read Address:
Page 3
ECA: Background Noise Level Estimate 2 (NOISLEV)
ECB: Background Noise Level Estimate 2 (NOISLEV)
03hex + Base Address
Power-up
N/A
A12=1
A11=1
Read Address:
23hex + Base Address
Bit 7
NSL15
Bit 6
NSL14
Bit 5
NSL13
Bit 4
NSL12
Bit 3
NSL11
Bit 2
NSL10
Bit 1
NSL9
Bit 0
NSL8
Read Address:
Page 3
ECA: Background Noise Level Estimate 1 (NOISLEV)
ECB: Background Noise Level Estimate 1 (NOISLEV)
02hex + Base Address
Power-up
N/A
A12=1
A11=1
Read Address:
22hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NSL2
Bit 1
Bit 0
NSL0
NSL7
NSL6
NSL5
NSL4
NSL3
NSL1
Functional Description of Register Bits
This register reflects the VEC’s current estimation of background noise as a 16 bit linear value.
Read Address:
Page 3
ECA: NLP Signal Scaling Factor 2 (NLPGAIN)
ECB: NLP Signal Scaling Factor 2 (NLPGAIN)
05hex + Base Address
Power-up
N/A
A12=1
A11=1
Read Address:
25hex + Base Address
Bit 7
Bit 6
Bit 5
NLPSS13
Bit 4
NLPSS12
Bit 3
NLPSS11
Bit 2
NLPSS10
Bit 1
NLPSS9
Bit 0
NLPSS8
NLPSS15 NLPSS14
Read Address:
Page 3
ECA: NLP Signal Scaling Factor 1 (NLPGAIN)
ECB: NLP Signal Scaling Factor 1 (NLPGAIN)
04hex + Base Address
Power-up
N/A
A12=1
A11=1
Read Address:
24hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NLPSS2
Bit 1
Bit 0
NLPSS7
NLPSS6
NLPSS5
NLPSS4
NLPSS3
NLPSS1
NLPSS0
Functional Description of Register Bits
This register reflects the NLP attenuation, and is affected by the RAMPIN and RAMPOUT values. NLPGAIN
is a 16-bit linear value which is normalized to 4000hex = 1 (no attenuation). Lower values reflect more
attenuation.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
R/W Address:
Page 3
ECA: Noise Level Scaling Factor 2 (NLSCALE)
ECB: Noise Level Scaling Factor 2 (NLSCALE)
0Dhex + Base Address
Power-up
01hex
A12=1
A11=1
R/W Address:
2Dhex + Base Address
Bit 7
NLS15
Bit 6
NLS14
Bit 5
NLS13
Bit 4
NLS12
Bit 3
NLS11
Bit 2
NLS10
Bit 1
NLS9
Bit 0
NLS8
R/W Address:
Page 3
ECA: Noise Level Scaling Factor 1 (NLSCALE)
ECB: Noise Level Scaling Factor 1 (NLSCALE)
0Chex + Base Address
Power-up
AAhex
A12=1
A11=1
R/W Address:
2Chex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NLS2
Bit 1
Bit 0
NLS7
NLS6
NLS5
NLS4
NLS3
NLS1
NLS0
Functional Description of Register Bits
This register is used to scale the comfort noise up or down. Larger values will increase the relative level of
comfort noise. The default value of 01AAhex will provide G.168 compliance with the Advanced NLP. The high
byte is in Register 2 and the low byte is in Register 1.
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Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Page 0
Power-up
00hex
R/W Address:
400hex
Main Control Register 0 (EC Group 0)
A12=0
A11=0
Bit 7
WR_all
Bit 6
ODE
Bit 5
Bit 4
Bit 3
Bit 2
Format
Bit 1
Law
Bit 0
PWUP
MIRQ
MTDBI
MTDAI
Functional Description of Register Bits
Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into
0000hex to 0003Fhex which is Group 0 address mapping. Useful to initialize the 16 Groups of
Echo Cancellers as per Group 0. When low, address mapping is per Figure 11. Note: Only the
Main Control Register 0 has the WR_all bit.
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When both ODE
bit and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is
low or the ODE input pin is low, the Rout and Sout outputs are high impedance. Note: Only the
Main Control Register 0 has the ODE bit.
WR_all
ODE
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The
Tone Detectors operate as specified in their Echo Canceller B, Control Register 2.
When low, the Tone Detectors Interrupts are active.
MIRQ
Note: Only the Main Control Register 0 has the MIRQ bit.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control
Register 2. When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control
Register 2. When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T
(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-
magnitude PCM code.
A/µ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law
companded PCM code. When low, both Echo Cancellers A and B for a given group, accept µ-
Law companded PCM code.
MTDBI
MTDAI
Format
Law
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group,
are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from
Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from
zero to one, the echo canceller A and B execute their initialization routine which presets their
registers, Base Address+00hex to Base Address+3Fhex, to default power up value and clears
the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to
execute properly. Once the initialization routine is executed, the user can set the per channel
Control Registers for their specific application.
PWUP
42
Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Main Control Register 1 (EC Group 1)
Main Control Register 2 (EC Group 1)
Main Control Register 3 (EC Group 1)
Main Control Register 4 (EC Group 1)
Main Control Register 5 (EC Group 1)
Main Control Register 6 (EC Group 1)
Main Control Register 7 (EC Group 1)
Main Control Register 8 (EC Group 1)
Main Control Register 9 (EC Group 1)
Main Control Register 10 (EC Group 1)
Main Control Register 11 (EC Group 1)
Main Control Register 12 (EC Group 1)
Main Control Register 13 (EC Group 1)
Main Control Register 14 (EC Group 1)
Main Control Register 15 (EC Group 1)
R/W Address: 401hex
R/W Address: 402hex
R/W Address: 403hex
R/W Address: 404hex
R/W Address: 405hex
R/W Address: 406hex
R/W Address: 407hex
R/W Address: 408hex
R/W Address: 409hex
R/W Address: 40Ahex
R/W Address: 40Bhex
R/W Address: 40Chex
R/W Address: 40Dhex
R/W Address: 40Ehex
R/W Address: 40Fhex
Page0
Power-up
00hex
A12=0
A11=0
Bit 7
Unused
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Format
Bit 1
Law
Bit 0
PWUP
Unused
Unused
MTDBI
MTDAI
Functional Description of Register Bits
Unused
MTDBI
Unused bits
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control
Register 2. When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control
Register 2. When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T
(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-
magnitude PCM code.
A/µ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law
companded PCM code. When low, both Echo Cancellers A and B for a given group, accept µ-
Law companded PCM code.
MTDAI
Format
Law
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group,
are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from
Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from
zero to one, the echo cancellers A and B execute their initialization routine which presets their
registers, Base Address+00hex to Base Address+3Fhex, to default Reset Value and clears the
Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute
properly. Once the initialization routine is executed, the user can set the per channel Control
Registers for their specific application.
PWUP
43
Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Page 0
Power-up
00hex
R/W Address:
410hex
Interrupt FIFO Register
A12=0
A11=0
Bit 7
IRQ
Bit 6
0
Bit 5
0
Bit 4
I4
Bit 3
I3
Bit 2
I2
Bit 1
I1
Bit 0
I0
Functional Description of Register Bits
IRQ
Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into
0000hex to 0003Fhex which is Group 0 address mapping. Useful to initialize the 16 Groups of
Echo Cancellers as per Group 0. When low, address mapping is per Figure 11. Note: Only the
Main Control Register 0 has the WR_all bit.
Unused bits. Always zero.
I<4:0> binary code indicates the channel number at which a Tone Detector state change has
occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
0
I<4:0>
Page 0
Power-up
00hex
R/W Address:
Test Register
A12=0
411hex
A11=0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Functional Description of Register Bits
Reserved Reserved bits. Must always be set to zero for normal operation.
Tirq
Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high,
any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and
its corresponding channel number will be available from the Interrupt FIFO Register. When low,
normal operation is selected.
44
Zarlink Semiconductor Inc.
ZL38070
Data Sheet
Absolute Maximum Ratings*
Parameter
I/O Supply Voltage (VDD1
Symbol
Min.
Max.
Units
1
2
3
4
5
6
7
)
VDD_IO
VDD_CORE
-0.5
-0.5
VSS - 0.5
VSS - 0.3
5.0
2.5
VDD1+0.5
7.0
V
V
V
V
mA
W
°C
Core Supply Voltage (VDD2
)
Input Voltage
VI3
VI5
Io
PD
TS
Input Voltage on any 5 V Tolerant I/O pins
Continuous Current at digital outputs
Package power dissipation
20
3.0
150
Storage temperature
-55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated
Characteristics
Operating Temperature
I/O Supply Voltage (VDD_IO
Core Supply Voltage (VDD_CORE
Input High Voltage on 3.3 V tolerant I/O
Input High Voltage on 5 V tolerant I/O pins
Input Low Voltage
Sym.
Min.
Typ.‡
Max.
Units
1
2
3
4
5
6
TOP
VDD1
VDD2
VIH3
VIH5
VIL
-40
3.0
1.6
+85
3.6
2.0
VDD1
5.5
0.3VDD1
°C
V
V
V
V
)
3.3
1.8
)
0.7VDD1
0.7VDD1
V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Sym.
Min.
Typ.‡
Max. Units
Test Conditions
Static Supply Current
IDD_IO (VDD1 = 3.3 V)
Single EV Processor
IDD_CORE (VDD2 = 1.8 V)
Single EV Processor
Power Consumption
ICC
IDD_IO
250
µA RESET = 0
1
10
65
mA 32 channels of single
EVP are active
IDD_CORE
PC
mA 32 channels of single
EVP are active
I
2
1.2
W
All EVP’s i.e., 256 chan-
N
P
U
T
S
nels are active
3
4
5
Input High Voltage
Input Low Voltage
VIH
VIL
0.7VDD1
V
V
0.3VDD1
Input Leakage
IIH/IIL
ILU
10
µA VIN=VSS to VDD1or 5.5 V
µA VIN=VSS
Input Leakage on Pullup
Input Leakage on Pulldown
-100
100
ILD
µA VIN=VDD1
See Note 1
6
7
8
9
10
Input Pin Capacitance
Output High Voltage
Output Low Voltage
High Impedance Leakage
Output Pin Capacitance
CI
10
pF
V
V
O
U
T
VOH
VOL
IOZ
0.8VDD1
IOH = 12 mA
IOL = 12 mA
0.4
10
10
P
U
T
µA VIN=VSS to 5.5 V
pF
S
CO
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD1 =3.3 V and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: Typical leakage for TMS and TRSTB pins is ~ 1mA max due to lower effective resistance due to parallelled EVPs.
45
Zarlink Semiconductor Inc.
ZL38070
Data Sheet
AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels
- Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
CMOS Threshold
CMOS Rise/Fall Threshold Voltage High
CMOS Rise/Fall Threshold Voltage Low
Sym.
Level
Units
Conditions
1
2
3
VTT
VHM
VLM
0.5VDD1
0.7VDD1
0.3VDD1
V
V
V
† Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics† - Frame Pulse and C4i
Characteristic
Sym.
Min.
Typ.‡ Max.
Units
Notes
tFPW
1
2
3
Frame pulse width (ST-BUS, GCI)
20
2*
ns
tCP-20
tFPS
tFPH
Frame Pulse Setup time before
C4i falling (ST-BUS or GCI)
10
10
122
122
150
ns
ns
150
Frame Pulse Hold Time from C4i
falling (ST-BUS or GCI)
tCP
tCH
tCL
4
5
6
7
190
85
244
300
150
150
10
ns
ns
ns
ns
C4i Period
C4i Pulse Width High
C4i Pulse Width Low
C4i Rise/Fall Time
85
tr, tf
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes
Characteristic
Sym. Min. Typ.‡ Max.
Units
Test Conditions
tSIS
tSIH
1
2
3
Rin/Sin Set-up Time
Rin/Sin Hold Time
Rout/Sout Delay
- Active to Active
10
10
ns
ns
ns
tSOD
60
30
4
Output Data Enable (ODE)
tODE
ns
Delay
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated.
Characteristic
Sym.
Min.
Typ.‡ Max.
Units
Notes
1
Master Clock Frequency,
- Fsel = 0
fMCF0
fMCF1
19.0
9.5
20.0
10.0
21.0
10.5
MHz
MHz
- Fsel = 1
tMCL
tMCH
2
3
Master Clock Low
Master Clock High
20
20
ns
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.
46
Zarlink Semiconductor Inc.
ZL38070
Data Sheet
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
tCSS
0
ns
1
2
3
4
5
6
7
8
9
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data delay on read
tRWS
tADS
tCSH
tRWH
tADH
tDDR
tDHR
tDSW
tDHW
tAKD
tAKH
tIRD
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
79
15
3
0
0
Data hold on read
Data setup on write
10 Data hold on write
11 Acknowledgment delay
12 Acknowledgment hold time
13 IRQ delay
80
8
0
20
65
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.
tFPW
F0i
VTT
tCP
tCH
tFPS
tr
tFPH
tCL
VHM
VTT
VLM
C4i
tSOD
tf
Bit 0, Channel 31
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
Rout/Sout
Rin/Sin
VTT
tSIS
tSIH
Bit 0, Channel 31
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
VTT
Figure 14 - ST-BUS Timing at 2.048 Mb/s
47
Zarlink Semiconductor Inc.
ZL38070
Data Sheet
tFPW
F0i
C4i
VTT
tCP
tCH
tFPS
tFPH
tCL
tr
VHM
VTT
VLM
tSOD
tf
Bit 7, Channel 31
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
Bit 2, Channel 0
Sout/Rout
Sin/Rin
VTT
tSIS
tSIH
Bit 7, Channel 31
Bit 0, Channel 0
Bit 1, Channel 0
VTT
Figure 15 - GCI Interface Timing at 2.048 Mb/s
VTT
ODE
tODE
tODE
VTT
Valid Data
Sout/Rout
HiZ
HiZ
Figure 16 - Output Driver Enable (ODE)
tMCH
VTT
MCLK
tMCL
Figure 17 - Master Clock
48
Zarlink Semiconductor Inc.
ZL38070
Data Sheet
VTT
VTT
DS
CS
tCSS
tCSH
tRWH
tRWS
VTT
VTT
VTT
VTT
R/W
tADS
tADH
VALID ADDRESS
tDDR
A0-A12
tDHR
VALID READ DATA
tDHW
D0-D7
READ
tDSW
VALID WRITE DATA
tAKD
D0-D7
WRITE
tAKH
VTT
DTA
IRQ
tIRD
VTT
Figure 18 - Motorola Non-Multiplexed Bus Timing
49
Zarlink Semiconductor Inc.
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of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
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