ZL50019QCC [ZARLINK]
Enhanced 2 K Digital Switch with Stratum 4E DPLL; 增强型2 k数字交换机与地层4E DPLL
| 型号： | ZL50019QCC |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| 文件： | 总115页 (文件大小：858K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL50019
Enhanced 2 K Digital Switch with
Stratum 4E DPLL
Data Sheet
October 2004
Features
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2048 channel x 2048 channel non-blocking digital
Ordering Information
Time Division Multiplex (TDM) switch at 8.192
and 16.384 Mbps or using a combination of ports
running at 2.048, 4.096, 8.192 and 16.384 Mbps
ZL50019GAC 256-ball PBGA
ZL50019QCC 256-lead LQFP
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32 serial TDM input, 32 serial TDM output
streams
Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 4E
specifications
-40°C to +85°C
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Output streams can be configured as bi-
directional for connection to backplanes
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Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
Per-stream input and output data rate conversion
selection at 2.048, 4.096, 8.192 or 16.384 Mbps.
Input and output data rates can differ
DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
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Per-stream high impedance control outputs
(STOHZ) for 16 output streams
Per-stream input bit delay with flexible sampling
point selection
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Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
VDD_COREA
VDD_IOA
RESET
VDD_CORE
VDD_IO
VSS
ODE
P/S Converter
STio[31:0]
S/P Converter
Input Timing
Data Memory
STi[31:0]
FPi
CKi
Output HiZ
Control
STOHZ[15:0]
MODE_4M0
MODE_4M1
Connection Memory
REF0
REF1
REF2
REF3
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
Output Timing
Test Port
DPLL
OSC
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
Internal Registers &
Microprocessor Interface
OSC_EN
Figure 1 - ZL50019 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50019
Data Sheet
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Per-stream output bit and fractional bit advancement
Per-channel ITU-T G.711 PCM A-Law/µ-Law Translation
Four frame pulse and six reference clock outputs
Three programmable delayed frame pulse outputs
Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
Input frame pulses: 61 ns, 122 ns, 244 ns
Per-channel constant or variable throughput delay for frame integrity and low latency applications
Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151
Per-channel high impedance output control
Per-channel message mode
Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
Connection memory block programming
Supports ST-BUS and GCI-Bus standards for input and output timing
IEEE-1149.1 (JTAG) test port
3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage
Applications
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PBX and IP-PBX
Small and medium digital switching platforms
Remote access servers and concentrators
Wireless base stations and controllers
Multi service access platforms
Digital Loop Carriers
Computer Telephony Integration
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
Description
The ZL50019 is a maximum 2,048 x 2,048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has
thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and
Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be
independently programmed to operate at any of the following data rates: 2.048, 4.096, 8.192 or 16.384 Mbps. The
ZL50019 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external
tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in
bi-directional mode, in which case STi0 - 31 will be ignored.
The device contains two types of internal memory - data memory and connection memory. There are four modes of
operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the
contents of the connection memory define, for each output stream and channel, the source stream and channel
(the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for
the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be
broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with
a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the
input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output
channel can be put into a high impedance state.
When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external
20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input
reference signals (which can be 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitter
attenuation. The jitter attenuation function exceeds the Stratum 4E specification.
The configurable non-multiplexed microprocessor port allows users to program various device operating modes
and switching configurations. Users can employ the microprocessor port to perform register read/write, connection
memory read/write and data memory read operations. The port is configurable to interface with either Motorola or
Intel-type microprocessors.
The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
Table of Contents
1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 External High Impedance Control, STOHZ0 - 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.0 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.0 Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.5 External High Impedance Control Advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.0 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.0 Device Performance in Master Mode and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.1 Master Mode Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12.2 Divided Slave Mode Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12.3 Multiplied Slave Mode Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.0 Overall Operation of the DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1 DPLL Functional Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1.1 Normal Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1.3 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1.4 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1.5 DPLL Internal Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14.0 DPLL Frequency Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14.1 Input Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14.2 Input Frequencies Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14.3 Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14.4 Pull-In/Hold-In Range (also called Locking Range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15.0 Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15.1 Input Clock Cycle to Cycle Timing Variation Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15.2 Input Jitter Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15.3 Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
16.0 DPLL Specific Functions and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
16.1 Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
16.2 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
16.3 Phase Alignment Speed (Phase Slope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16.4 Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16.5 Single Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16.6 Multiple Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
Table of Contents
17.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
18.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
18.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
18.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
18.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
19.0 Pseudo Random Bit Generation and Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
20.0 PCM A-law/m-law Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
21.0 Quadrant Frame Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
22.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
22.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
22.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
22.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
22.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
23.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
24.0 Detailed Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
25.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
25.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
25.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
25.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
26.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
26.1 OSCi Master Clock Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
26.1.1 External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
26.1.2 External Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
27.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
28.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
List of Figures
Figure 1 - ZL50019 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50019 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . 10
Figure 3 - ZL50019 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7 - Output Timing for CKo0 and FPo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8 - Output Timing for CKo1 and FPo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9 - Output Timing for CKo2 and FPo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10 - Output Timing for CKo3 and FPo3 with CK0FPo3SEL1-0=”11” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11 - Output Timing for CKo4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 12 - Output Timing for CKo5 and FPo5 (FPo_OFF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13 - Input Bit Delay Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18 - Channel Switching External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 22 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 23 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 24 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 25 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 26 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 27 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 28 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 29 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 30 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 31 - ST-BUS Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps. . . . . . . . . . . . . . . . . . . . 95
Figure 32 - ST-BUS Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 33 - GCI-Bus Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps . . . . . . . . . . . . . . . . . . . 96
Figure 34 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 35 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 36 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 37 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 38 - Output Drive Enable (ODE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 39 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 40 - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 41 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 42 - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 43 - FPo3 and CKo3 (32.768 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 44 - FPo4 and CKo4 Timing Diagram (1.544/2.048 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 45 - CKo5 Timing Diagram (19.44 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 46 - REF0 - 3 Reference Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 47 - Output Timing (ST-BUS Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
List of Tables
Table 1 - CKi and FPi Configurations for Master and Divided Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 2 - CKi and FPi Configurations for Multiplied Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3 - Output Timing Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6 - Connection Memory High After Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7 - ZL50019 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9 - Generated Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 10 - Values for Single Period Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11 - Multi-Period Hysteresis Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 13 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 14 - Quadrant Frame Bit Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 15 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 16 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17 - Internal Mode Selection Register (IMS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 18 - Software Reset Register (SRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19 - Output Clock and Frame Pulse Control Register (OCFCR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 20 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 21 - FPo_OFF[n] Register (FPo_OFF[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 22 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 23 - BER Error Flag Register 0 (BERFR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 24 - BER Error Flag Register 1 (BERFR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 25 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 26 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 27 - DPLL Control Register (DPLLCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 28 - Reference Frequency Register (RFR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 29 - Centre Frequency Register - Lower 16 Bits (CFRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 30 - Centre Frequency Register - Upper 10 Bits (CFRU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 31 - Frequency Offset Register (FOR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 32 - Lock Detector Threshold Register (LDTR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 33 - Lock Detector Interval Register (LDIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 34 - Slew Rate Limit Register (SRLR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 35 - Reference Change Control Register (RCCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 36 - Reference Change Status Register (RCSR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 37 - Interrupt Register (IR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 38 - Interrupt Mask Register (IMR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 39 - Interrupt Clear Register (ICR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 40 - Reference Failure Status Register (RSR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 41 - Reference Mask Register (RMR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 42 - Reference Frequency Status Register (RFSR) Bits - Read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 43 - Output Jitter Control Register (OJCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 44 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 45 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 46 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 47 - BER Receiver Start Register [n] (BRSR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 48 - BER Receiver Length Register [n] (BRLR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
List of Tables
Table 49 - BER Receiver Control Register [n] (BRCR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 50 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 51 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 52 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 54 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
1.0 Changes Summary
Page
Item
Change
10
Figure 2, “ZL50019 256-Ball 17 mm x
17 mm PBGA (as viewed through top of
package)
•
•
•
•
•
•
•
Re-labeled IC_OPEN to MODE_4M0 Location:
Ball M14
Re-labeled IC_OPEN to MODE_4M1 Location:
Ball R13
11
Figure 3, “ZL50019 256-Lead 28 mm x
28 mm LQFP (top view)
Re-labeled IC_OPEN to MODE_4M0 Location:
Pin 46
Re-labeled IC_OPEN to MODE_4M1 Location:
Pin 48
12
19
35
37
37
37
3.0, “Pin Description“
4.0, “Device Overview“
Added MODE_4M0 & MODE_4M1
descriptions
Added reference to ZLAN-120 "Mid-Density
Digital Switches Timing Modes”
12.0, “Device Performance in Master Mode
and Slave Modes“
Added Table 7 "Operating Modes" along with
description of table
13.0, “Overall Operation of the DPLL“
13.1, “DPLL Functional Modes“
13.1.2, “Holdover Mode“
•
•
•
Removed reference to programmable locking
range of DPLL
Removed reference to software controlled
mode
Removed reference to Stratum 4E holdover
requirements of 0.05 ppm
38
46
48
14.2, “Input Frequencies Selection“
23.0, “Register Address Mapping“
24.0, “Detailed Register Description“
•
•
•
Changed reference from Table 31 to Table 36
Changed from R/W to R Only
Updated Bits 12-11 description. Removed
Table
•
Changed Bits 6-5 Description - Added MODE
4M0/1 reference
84
85
26.1, “OSCi Master Clock Requirement“
26.1.2, “External Clock Oscillator“
•
•
•
Added Reference to ZLAN-68
Removed reference to Fox Oscillator
Updated text & removed reference to Raltron
Oscillators
9
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
2.0 Pinout Diagrams
2.1 BGA Pinout
1
2
3
4
5
6
7
8
9
10
STio22
FPi
11
STio23
CKi
12
13
14
15
16
A
B
A
B
VSS
STi29
STi10
STi9
STi28
STi5
STi27
STi4
STi25
CKo2
STi6
STi2
VSS
STi26
STi0
STi1
CKo4
STi24
CKo0
CKo1
REF3
NC
NC
STio21
STio20
NC
NC
VSS
VDD_
COREA
IC_
IC_
STi31
STi30
STi17
STi16
STi19
REF2
OSCi
VSS
ODE
STio19
OPEN
OPEN
REF_
FAIL2
IC_
IC_
C
D
E
F
C
D
E
F
VSS
STi7
VSS
OSCo IC_GND
STio15
STio14
FPo2
STio18
OPEN
OPEN
REF_
FAIL0
FPo_
OFF1
OSC_
STio13
EN
STi11
STi14
STi15
VDD_IO
STi8
STi3
REF1
VSS
NC
VDD_IO
STio12
FPo3
FPo1
STio16
VDD_
CORE
REF_
FAIL3
REF_
FAIL1
VDD_
CORE
VDD_IO
STi13
REF0
VSS
VSS
VSS
VSS
VSS
VSS
D10
D11
D14
D12
NC
VSS
VDD_IO
A12
A9
VDD_IO
STio17
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
IC_
FPo_
OFF2
STi12
VDD_IO
TDo
VSS
VSS
VSS
VSS
VSS
VSS
D6
STOHZ15
STOHZ14
STOHZ12
STOHZ13
STOHZ11
STOHZ10
STOHZ9
OPEN
IC_
G
H
G
H
STi18 RESET IC_GND
VDD_IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_IO
A13
A10
FPo0
A11
OPEN
VDD_
COREA
FPo_
OFF0
STi21
VSS
VSS
CKo5
VSS
VSS
A7
J
J
STi20 VDD_IOA VDD_IOA
VSS
VSS
TCK
D0
CKo3
VDD_IO
A3
A4
A5
A8
A2
A6
VDD_
COREA
IC_
K
K
STi22
STi23
STio25
STio24
STio26
STio27
VSS
VSS
TMS
TRST
TDi
VDD_IO
A0
A1
OPEN
VDD_
COREA
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
L
M
N
L
M
N
VDD_IO
VDD_IO
STio10
STio11
STio9
STio8
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
MOT
MODE_
4M0
NC
NC
VSS
VSS
_INTEL
R/W
DTA_
RDY
VDD_IO
STio0 STOHZ3
D1
D5
D3
D4
NC
7
D7
D13
IRQ
D15
NC
STio4
VDD_IO STOHZ5 STOHZ8
_WR
P
R
P
R
NC
VSS
STio1
STio3 STOHZ1
D8
STio5 STOHZ4 STOHZ6
VSS
STio6
NC
STOHZ7
STio7
NC
NC
NC
VSS
16
MODE_
NC
STOHZ0 STio2 STOHZ2
D2
NC
6
D9
CS
NC
11
DS_RD
NC
4M1
NC
T
T
STio28
2
STio29
3
STio31
4
STio30
5
NC
8
1
9
10
12
13
14
15
Note: A1 corner identified by metallized marking.
Note: Pinout is shown as viewed through top of package.
Figure 2 - ZL50019 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)
10
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
2.2 QFP Pinout
192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130
194
STi28
STi29
STio_19
STio_18
STio_17
STio_16
STOHZ_15
VSS
128
126
124
122
120
118
116
114
112
110
108
106
104
102
100
98
VDD_IO
STi30
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
STi31
STi_8
VSS
STOHZ_14
VDD_IO
STOHZ_13
STOHZ_12
STio_15
STio_14
STio_13
STio_12
VSS
STi_9
STi_10
STi_11
STi_12
STi_13
STi_14
STi_15
VDD_IO
IC_GND
VDD_IO
FPo3
VSS
IC_OPEN
RESET
TDo
VSS
FPo2
VDD_CORE
VDD_CORE
VSS
FPo_OFF2
OSC_EN
FPo1
NC
VSS
IC_OPEN
FPo_OFF1
VSS
VDD_COREA
VSS
NC
FPo0
VDD_IOA
CKO5
VDD_IO
FPo_OFF0
A13
VSS
VSS
VDD_COREA
NC
A12
VSS
96
A11
VDD_IOA
CKo3
VDD_CORE
A10
94
VSS
A9
A8
A7
A6
A5
A4
A3
NC
92
VSS
VDD_COREA
VSS
90
VDD_CORE
88
TMS
VSS
NC
A2
86
VSS
A1
NC
TCK
84
VDD_CORE
TRST
TDi
A0
82
VSS
VDD_IO
IC_OPEN
80
VSS
STi_16
STi_17
STi_18
STi_19
STi_20
STi_21
VDD_IO
STi_22
VSS
VDD_IO
STOHZ_11
STOHZ_10
STOHZ_9
STOHZ_8
STio_11
78
76
74
STio_10
STio_9
72
VSS
STio_8
70
STi_23
STio_24
STio_25
STio_26
STio_27
VDD_IO
NC
68
NC
NC
66
NC
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
Figure 3 - ZL50019 256-Lead 28 mm x 28 mm LQFP (top view)
11
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
3.0 Pin Description
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
E6, E11, F6,
F7, F10,
F11, L6, L7,
L10, L11,
M6, M7,
19, 33,
45, 83,
95, 109,
146, 173,
213, 233
VDD_CORE
Power Supply for the core logic: +1.8 V
M10, M11
H4, K5, B9,
L2
217, 231,
157, 224
VDD_COREA
VDD_IO
Power Supply for analog circuitry: +1.8 V
Power Supply for I/O: +3.3 V
D3, D14, E4,
E13, F5,
F12, G6,
G11, K6,
K11, L5,
L12, N3,
N14
5, 15, 29,
49, 57,
69, 79,
101, 113,
121, 133,
143, 160,
169, 177,
186, 195,
207, 241,
249
J2, J3
220, 226
VDD_IOA
VSS
Power Supply for the CKo5 and CKo3 outputs: +3.3 V
A1, A16, C3,
C9, C14,
8, 17, 21,
31, 35,
Ground
D10, E5,
47, 50,
60, 71,
81, 85,
E12, F8, F9,
G7, G8, G9,
G10, H2,
H3, H6, H7,
H8, H9,
H10, J4, J5,
J7, J8, J9,
J10, K2, K4,
K7, K8, K9,
K10, L8, L9,
M5, M12,
97, 103,
111, 114,
123, 142,
145, 147,
156, 158,
162, 171,
175, 178,
188, 199,
209, 214,
216, 218,
222, 223,
228, 230,
232, 235,
242, 251
P3, P14, T1,
T16
12
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
K3
234
TMS
Test Mode Select (5 V-Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
L4
L3
238
239
TCK
Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Provides the clock to the JTAG test logic.
TRST
Test Reset (5 V-Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional
mode. When JTAG is not being used, this pin should be pulled low
during normal operation.
M3
G5
240
212
TDi
TDo
Test Serial Data In (5 V-Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
Test Serial Data Out (5 V-Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when JTAG is not
enabled.
B12, B13,
C10, C11,
F13, G4,
K12
80, 105,
150, 151,
152, 153,
210
IC_OPEN
Internal Test Mode (5 V-Tolerant Input with Internal Pull-down)
These pins may be left unconnected.
C13, G3
144, 208
IC_GND
NC
Internal Test Mode Enable (5 V-Tolerant Input)
These pins MUST be low.
A8, A9, A14,
A15, E10,
M2, N2, P2,
P16, R2,
61, 62,
63, 64,
65, 66,
No Connect
These pins MUST be left unconnected.
67, 68,
R16, T6, T7,
T8, T9, T10,
T11, T12,
T13, T14,
T15
134, 135,
136, 137,
138, 139,
140, 215,
219, 225,
229, 236,
237
13
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
M14, R13
46, 48
MODE_4M0,
MODE_4M1
4M Input Clock Mode 0 to 1 (5 V-Tolerant Input with internal
pull-down)
These two pins should be tied together and are typically used to
select CKi = 4.096 MHz operation. See Table 7, “ZL50019
Operating Modes” on page 36 for a detailed explanation.
See Table 16, “Control Register (CR) Bits” on page 48 for CKi and
FPi selection using the CKIN1 - 0 bits.
D12
107
OSC_EN
Oscillator Enable (5 V-Tolerant Input with Internal Pull-down) If
tied high, this pin indicates that there is a 20 MHz external
oscillator interfacing with the device. If tied low, there is no
oscillator and CKi will be used for master clock generation.
If the device is in master mode, an external oscillator is required
and this pin MUST be tied high.
C12
B14
149
148
OSCo
OSCi
Oscillator Clock Output (3.3 V Output)
If OSC_EN = ‘1’, this pin should be connected to a 20 MHz crystal
(see Figure 21 on page 84) or left unconnected if a clock oscillator
is connected to OSCi pin under normal operation (see Figure 22
on page 85). If OSC_EN = 0, this pin MUST be left unconnected.
Oscillator Clock Input (3.3 V Input)
If OSC_EN = ‘1’, this pin should be connected to a 20 MHz crystal
(see Figure 21 on page 84) or to a clock oscillator under normal
operation (see Figure 22 on page 85). If OSC_EN = 0, this pin
MUST be driven high or low by connecting either to VDD_IO or to
ground.
E9, D8, B8,
D7
161, 164,
166, 168
REF0 - 3
DPLL Reference Inputs 0 to 3 (5 V-Tolerant Schmitt-Triggered
Inputs)
If the device is in Master mode, these input pins accept 8 kHz,
1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz timing references independently. One of these inputs is
defined as the preferred or forced input reference for the DPLL.
The Reference Change Control Register (RCCR) selects the
control of the preferred reference.These pins are ignored if the
device is in slave mode unless SLV_DPLLEN (bit 13) in the
Control Register (CR) is set. When these input pins are not in use,
they MUST be driven high or low by connecting either to VDD_IO or
to ground.
D9, E8, C8,
E7
159, 163,
165, 167
REF_FAIL0 - 3 Failure Indication for DPLL References 0 to 3 (5 V-Tolerant
Three-state Outputs)
These output pins are used to indicate input reference failure when
the device is in master mode.
If REF0 fails, REF_FAIL0 will be driven high.
If REF1 fails, REF_FAIL1 will be driven high.
If REF2 fails, REF_FAIL2 will be driven high.
If REF3 fails, REF_FAIL3 will be driven high.
If the device is in slave mode, these pins are driven low, unless
SLV_DPLLEN (bit 13) in the Control Register (CR) is set.
14
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
G15, G14,
E15, F14
102, 106,
110, 112
FPo0 - 3
ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output
clock of CKo0.
FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output
clock of CKo1.
FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output
clock of CKo2.
FPo3: Programmable 8 kHz frame pulse corresponding to
4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock
of CKo3.
In Divided Slave modes, the frame pulse width of FPo0 - 3 cannot
be narrower than the input frame pulse (FPi) width.
H14, D11
F15
100, 104
108
FPo_OFF0 - 1 Generated Offset Frame Pulse Outputs 0 to 1 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.
FPo_OFF2
or
Generated Offset Frame Pulse Output 2 or 19.44 MHz Frame
Pulse Output (5 V-Tolerant Three-state Output)
As FPo_OFF2, this is an individually programmable 8 kHz frame
pulse, offset from the output frame boundary by a programmable
number of channels.
FPo5
By programming the FP19EN (bit 10) of FPOFF2 register to high,
this signal becomes FPo5, a non-offset frame pulse corresponding
to the 19.44 MHz clock presented on CKo5. FPo5 is only available
in Master mode or when the SLV_DPLLEN bit in the Control
Register is set high while the device is in one of the slave modes.
B7, C7, B5,
J6, D6, H5
170, 172,
174, 227,
176, 221
CKo0 - 5
ST-BUS/GCI-Bus Clock Outputs 0 to 5 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
programmable output clock.
CKo4: 1.544 MHz or 2.048 MHz programmable output clock.
CKo5: 19.44 MHz output clock.
See Section 7.0 on page 23 for details. In Divided Slave mode, the
frequency of CKo0 - 3 cannot be higher than input clock (CKi).
CKo4 and CKo5 are only available in Master mode or when the
SLV_DPLLEN bit in the Control Register is set high while the
device is in one of the slave modes.
15
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
Frame Pulse
B10
155
FPi
ST-BUS/GCI-Bus
Input
(5 V-Tolerant
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz. The frame pulse associated with the highest
input or output data rate must be applied to this pin when the
device is operating in Divided Slave mode or Master mode. The
exception is if the device is operating in Master mode with
loopback (i.e., CKi_LP is set in the Control Register). In that case,
this input must be tied high or low externally. When the device is
operating in Multiplied Slave mode, the frame pulse associated
with the highest input data rate must be applied to this pin. For all
modes (except Master mode with loopback), if the data rate is
16.384 Mbps, a 61 ns wide frame pulse must be used. By default,
the device accepts a negative frame pulse in ST-BUS format, but it
can accept a positive frame pulse instead if the FPINP bit is set
high in the Control Register (CR). It can accept a GCI-formatted
frame pulse by programming the FPINPOS bit in the Control
Register (CR) to high.
B11
154
CKi
ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt Triggered
The Input)
This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock.
The clock frequency associated with twice the highest input or
output data rate must be applied to this pin when the device is
operating in either Divided Slave mode or Master mode. The
exception is if the device is operating in Master mode with
loopback (i.e., CKi_LP is set in the Control Register). In that case,
this input must be tied high or low externally. The clock frequency
associated with twice the highest input data rate must be applied
to this pin when the device is operating in Multiplied Slave mode.
In all modes of operation (except Master mode with loopback),
when data is running at 16.384 Mbps, a 16.384 MHz clock must be
used. By default, the clock falling edge defines the input frame
boundary, but the device allows the clock rising edge to define the
frame boundary by programming the CKINP bit in the Control
Register (CR).
16
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
B6, C6, D5,
D4, B4, B3,
C5, C4, E3,
C2, B2, D2,
F3, F4, E2,
F2, E1, D1,
G1, F1, J1,
H1, K1, L1,
A7, A5, A6,
A4, A3, A2,
C1, B1
179, 180,
181, 182,
183, 184,
185, 187,
198, 200,
201, 202,
203, 204,
205, 206,
243, 244,
245, 246,
247, 248,
250, 252,
189, 190,
191, 192,
193, 194,
196, 197
STi0 - 31
Serial Input Streams 0 to 31 (5 V-Tolerant Inputs with Enabled
Internal Pull-downs)
The data rate of each input stream can be selected independently
using the Stream Input Control Registers (SICR[n]). In the
2.048 Mbps mode, these pins accept serial TDM data streams at
2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode,
these pins accept serial TDM data streams at 4.096 Mbps with 64
channels per frame. In the 8.192 Mbps mode, these pins accept
serial TDM data streams at 8.192 Mbps with 128 channels per
frame. In the 16.384 Mbps mode, these pins accept TDM data
streams at 16.384 Mbps with 256 channels per frame.
N4, P4, R4,
P5, N13,
P11, R14,
R15, M15,
L15, L13,
L14, E14,
D13, D15,
C15, D16,
E16, C16,
B16, A13,
A12, A10,
A11, N1,
6, 7, 9,
10, 51,
52, 53,
54, 70,
72, 73,
74, 115,
116, 117,
118, 125,
126, 127,
128, 129,
130, 131,
132, 253,
254, 255,
256, 1, 2,
3, 4
STio0 - 31
Serial Output Streams 0 to 31 (5 V-Tolerant Slew-Rate-Limited
Three-state I/Os with Enabled Internal Pull-downs)
The data rate of each output stream can be selected
independently using the Stream Output Control Registers
(SOCR[n]). In the 2.048 Mbps mode, these pins output serial TDM
data streams at 2.048 Mbps with 32 channels per frame. In the
4.096 Mbps mode, these pins output serial TDM data streams at
4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode,
these pins output serial TDM data streams at 8.192 Mbps with 128
channels per frame. In the 16.384 Mbps mode, these pins output
serial TDM data streams at 16.384 Mbps with 256 channels per
frame. These output streams can be used as bi-directionals by
programming BDH (bit 7) and BDL (bit 6) of Internal Mode
Selection (IMS) register.
M1, P1, R1,
T2, T3, T5,
T4
R3, P6, R5,
N5, P12,
N15, P13,
P15, N16,
M16, L16,
K16, H16,
J16, G16,
F16
11, 12,
13, 14,
55, 56,
58, 59,
75, 76,
77, 78,
119, 120,
122, 124
STOHZ0 - 15
Serial Output Streams High Impedance Control 0 to 15
(5 V-Tolerant Slew-Rate-Limited Three-state Outputs)
These pins are used to enable (or disable) external three-state
buffers. When an output channel is in the high impedance state,
the STOHZ drives high for the duration of the corresponding output
channel. When the STio channel is active, the STOHZ drives low
for the duration of the corresponding output channel. STOHZ
outputs are available for STio0 - 157 only.
17
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
B15
141
ODE
Output Drive Enable (5 V-Tolerant Input with Internal Pull-up)
This is the output enable control for STio0 - 31 and the
output-driven-high control for STOHZ0 - 15. When it is high, STio0
- 31 and STOHZ0 - 15 are enabled. When it is low, STio0 - 31 are
tristated and STOHZ0 - 15 are driven high.
M4, N6, R6,
P7, R7, N7,
M8, N8, P8,
R8, M9, N9,
R9, N10, P9,
R10
16, 18,
20, 22,
23, 24,
25, 26,
27, 28,
30, 32,
34, 36,
37, 38
D0 - 15
Data Bus 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state
I/Os)
These pins form the 16-bit data bus of the microprocessor port.
N12
44
DTA_RDY
Data Transfer Acknowledgment_Ready (5 V-Tolerant
Three-state Output)
This active low output indicates that a data bus transfer is
complete for the Motorola interface. For the Intel interface, it
indicates a transfer is completed when this pin goes from low to
high. An external pull-up resistor MUST hold this pin at HIGH level
for the Motorola mode. An external pull-down resistor MUST hold
this pin at LOW level for the Intel mode.
R11
N11
40
39
CS
Chip Select (5 V-Tolerant Input)
Active low input used by the Motorola or Intel microprocessor to
enable the microprocessor port access.
R/W_WR
Read/Write_Write (5 V-Tolerant Input)
This input controls the direction of the data bus lines (D0 - 15)
during a microprocessor access. For the Motorola interface, this
pin is set high and low for the read and write access respectively.
For the Intel interface, a write access is indicated when this pin
goes low.
R12
42
DS_RD
A0 - 13
Data Strobe_Read (5 V-Tolerant Input)
This active low input works in conjunction with CS to enable the
microprocessor port read and write operations for the Motorola
interface. A read access is indicated when it goes low for the Intel
interface.
K13, K15,
K14, J11,
J12, J13,
J15, H11,
J14, H12,
H13, H15,
G12, G13
82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,
98, 99
Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.
18
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
M13
41
MOT_INTEL
Motorola_Intel (5 V-Tolerant Input with Enabled Internal
Pull-up)
This pin selects the Motorola or Intel microprocessor interface to
be connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin is
connected to ground, Intel interface should be used.
P10
G2
43
IRQ
Interrupt (5 V-Tolerant Three-state Output)
This programmable active low output indicates that the internal
operating status of the DPLL has changed. An external pull-up
resistor MUST hold this pin at HIGH level.
211
RESET
Device Reset (5 V-Tolerant Input with Internal Pull-up)
This input (active LOW) puts the device in its reset state that
disables the STio0 - 31 drivers and drives the STOHZ0 - 15
outputs to high. It also preloads registers with default values and
clears all internal counters. To ensure proper reset action, the reset
pin must be low for longer than 1 µs. Upon releasing the reset
signal to the device, the first microprocessor access cannot take
place for at least 600 µs due to the time required to stabilize the
device and the crystal oscillator from the power-down state. Refer
to Section Section 18.2 on page 42 for details.
4.0 Device Overview
The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31).
STio0 - 31 can also be configured as bi-directional pins, in which case STi0 - 31 will be ignored. It is a non-blocking
digital switch with 2048 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus
inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates
of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs
deliver serial data streams with data rates of 2.048 Mbps, 4.096 Mbps and, 8.192 Mbps and 16.384 Mbps on a
per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ0 - 15) to support the
use of external ST-BUS/GCI-Bus tristate drivers for the first sixteen ST-BUS/GCI-Bus outputs (STio0 -15).
By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.
The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi in Divided Slave mode. In
Multiplied Slave mode, the output data streams will be driven by an internally generated clock, which is multiplied
from CKi internally. In Master mode, the on-chip DPLL will drive the output data streams and provide output clocks
and frame pulses. Refer to Application Note ZLAN-120 (Mid Density Digital Switches Timing Modes) for further
explanation of the different modes of operation.
When the device is in Master mode, the DPLL is phase-locked to one of four DPLL reference signals, REF0 - 3,
which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz reference signal. The on-chip DPLL also offers jitter attenuation, reference switching, reference
monitoring, freerun and holdover functions. The jitter performance exceeds the Stratum 4E specification. The
intrinsic jitter of all output clocks is less than 1 ns (except for the 1.544 MHz output).
19
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
There are two slave modes for this device:
The first is the Divided Slave mode. In this mode, output streams are clocked by input CKi. Therefore the output
streams have exactly the same jitter as the input streams. The output data rate can be the same as or lower than
the input data rate, but the output data rate cannot be higher than what CKi can drive. For example, if CKi is
4.096 MHz, the output data rate cannot be higher than 2.048 Mbps. For the Divided Slave mode, the core master
clock can be either 98.304 MHz, which is multiplied from CKi, or 100 MHz, which is multiplied from a 20 MHz
oscillator. The Divided Slave mode with 98.304 MHz core master clock is called Divided Slave with CKi mode, and
the mode with 100 MHz core master clock is called Divided Slave with OSC mode.
The second slave mode is called Multiplied Slave mode. In this mode, CKi is used to generate a 16.384 MHz clock
internally, and output streams are driven by this 16.384 MHz clock. In Multiplied Slave mode, the data rate of output
streams can be any rate, but output jitter may not be exactly the same as input jitter.
A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate
in various modes under different switching configurations. Users can use the microprocessor port to perform
internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit
address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY).
The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
5.0 Data Rates and Timing
The ZL50019 has 32 serial data inputs and 32 serial data outputs. Each stream can be individually programmed to
operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32
channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 µs frame.
The output streams can be programmed to operate as bi-directional streams. The output streams are divided into
two groups to be programmed into bi-directional mode. By setting BDL (bit 6) in the Internal Mode Selection (IMS)
register, input streams 0 - 15 (STi0 - 15) are internally tied low, and output streams 0 - 15 (STio0 - 15) are set to
operate in a bi-directional mode. Similarly, when BDH (bit 7) in the Internal Mode Selection (IMS) register is set,
input streams 16 - 31 (STi16 - 31) are internally tied low, and output streams 16 - 31 (STio16 - 31) are set to operate
in bi-directional mode. The groups do not have to be set into the same mode. Therefore it is possible to have half of
the streams operating in bi-directional mode while the other half is operating in normal input/output mode.
The input data rate is set on a per-stream basis by programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input
Control Register 0 - 31 (SICR0 - 31). The output data rate is set on a per-stream basis by programming STO[n]DR3
- 0 (bits 3 - 0) in the Stream Output Control Register 0 - 31 (SOCR0 - 31). The output data rates do not have to
match or follow the input data rates. The maximum number of channels switched is limited to 2048 channels. If all
32 input streams were operating at 16.384 Mbps (256 channels per stream), this would result in 8192 channels.
Memory limitations prevent the device from operating at this capacity. A maximum capacity of 2048 channels will
occur if eight of the streams are operating at 16.384 Mbps, half of the streams are operating at 8.192 Mbps or all
streams operating at 4.096 Mbps. With all streams operating at 2.048 Mbps, the capacity will be reduced to 1024
channels. However, as each stream can be programmed to a different data rate, any combination of data rates can
be achieved, as long as the total channel count does not exceed 2048 channels. It should be noted that only full
stream can be programmed for use. The device does not allow fractional streams.
5.1 External High Impedance Control, STOHZ0 - 15
There are 16 external high impedance control signals, STOHZ0 - 15, that are used to control the external drivers for
per-channel high impedance operations. Only the first sixteen ST-BUS/GCI-Bus (STio0 - 15) outputs are provided
with corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot
channels based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin
is high and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 15 are enabled. When the ODE pin,
OSB (bit 2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 15 are driven high, together with all the
ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
unused ST-BUS/GCI-Bus channel (high impedance) are driven high. Refer to Figure 18 on page 32 for a
diagrammatical explanation.
5.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The input clock for the ZL50019 can be arranged in one of three different ways. These different ways will be
explained further in Section 12.1 to Section 12.3 on page 37. Depending on the mode of operation, the input clock,
CKi, will be based on the highest data rate of either the input or both the input and output data rates. The user has
to program the CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) to indicate the width of the input frame pulse and
the frequency of the input clock supplied to the device.
In Master mode and Divided Slave mode, the input clock, CKi, must be at least twice the highest input or output
data rate. For example, if the highest input data rate is 4.096 Mbps and the highest output data rate is 8.192 Mbps,
the input clock, CKi, must be 16.384 MHz, which is twice the highest overall data rate. The only exception to this is
for 16.384 Mbps input or output data. In this case, the input clock, CKi, is equal to the data rate. The input frame
pulse, FPi, must always follow CKi.
In Master mode, CKo2 and FPo2 can be programmed to be used as CKi and FPi by setting CKi_LP (bit 10) in the
Control Register (CR). This will internally loop back the CKo2 and FPo2 timing. When this bit is set, CKi and FPi
must be tied low or high externally.
Highest Input or Output
CKIN 1-0 Bits
Input Clock Rate (CKi)
Input Frame Pulse (FPi)
Data Rate
16.384 Mbps or 8.192 Mbps
4.096 Mbps
00
01
10
16.384 MHz
8.192 MHz
4.096 MHz
8 kHz (61 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (244 ns wide pulse)
2.048 Mbps
Table 1 - CKi and FPi Configurations for Master and Divided Slave Modes
In Multiplied Slave mode, the input clock, CKi, must be at least twice the highest input data rate, regardless of the
output data rate. Following the example above, if the highest input data rate is 4.096 Mbps, the input clock, CKi,
must be 8.192 MHz, regardless of the output data rate. The only exception to this is for 16.384 Mbps input data. In
this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi.
Highest Input Data Rate
CKIN 1-0 Bits
Input Clock Rate (CKi)
Input Frame Pulse (FPi)
16.384 Mbps or 8.192 Mbps
4.096 Mbps
00
01
10
16.384 MHz
8.192 MHz
4.096 MHz
8 kHz (61 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (244 ns wide pulse)
2.048 Mbps
Table 2 - CKi and FPi Configurations for Multiplied Slave Mode
The ZL50019 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the
programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the
negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going
clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be
used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
FPi (244 ns)
FPINP = 0
FPINPOS = 0
FPi (244 ns)
FPINP = 1
FPINPOS = 0
FPi (244 ns)
FPINP = 0
FPINPOS = 1
FPi (244 ns)
FPINP = 1
FPINPOS = 1
CKi
(4.096 MHz)
CKINP = 0
CKi
(4.096 MHz)
CKINP = 1
Channel 0
Channel 31
STi
0
7
6
1
0
7
(2.048 Mbps)
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR
FPi (122 ns)
FPINP = 0
FPINPOS = 0
FPi (122 ns)
FPINP = 1
FPINPOS = 0
FPi (122 ns)
FPINP = 0
FPINPOS = 1
FPi (122 ns)
FPINP = 1
FPINPOS = 1
CKi
(8.192 MHz)
CKINP = 0
CKi
(8.192 MHz)
CKINP = 1
Channel 0
Channel 63
STi
1
0
7
6
5
4
2
1
0
7
6
(4.096 Mbps)
Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
FPi (61 ns)
FPINP = 0
FPINPOS = 0
FPi (61 ns)
FPINP = 1
FPINPOS = 0
FPi (61 ns)
FPINP = 0
FPINPOS = 1
FPi (61 ns)
FPINP = 1
FPINPOS = 1
CKi
(16.384 MHz)
CKINP = 0
CKi
(16.384 MHz)
CKINP = 1
Channel N = 127
Channel 0
STi
1
4 3 2 1
5
3
5
2 1 0 7 6
0 7 6 5
4
(8.192 Mbps)
Channel 0
Channel N = 255
STi
321076543210765432
321076543210765432
(16.384 Mbps)
Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR
6.0 ST-BUS and GCI-Bus Timing
The ZL50019 is capable of operating using either the ST-BUS or GCI-Bus standards. The output timing that the
device generates is defined by the bus standard. In the ST-BUS standard, the output frame boundary is defined by
the falling edge of CKo while FPo is low. In the GCI-Bus standard, the frame boundary is defined by the rising edge
of CKo while FPo goes high. The data rates define the number of channels that are available in a 125 µs frame
pulse period.
By default, the ZL50019 is configured for ST-BUS input and output timing. To set the input timing to conform to the
GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. To set output timing
to conform to the GCI-Bus standard, FPO[n]P and FPO[n]POS must be set in the Output Clock and Frame Pulse
Selection Register (OCFSR). The CKO[n]P bits in the Output Clock and Frame Pulse Selection Register control the
polarity (positive-going or negative-going) of the output clocks.
7.0 Output Timing Generation
The ZL50019 generates frame pulse and clock timing. There are five output frame pulse pins (FPo0 - 3, 5) and six
output clock pins (CKo0 - 5). All output frame pulses are 8 kHz output signals. By default, the output frame
boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1,
CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low. At the
output frame boundary, CKo4 will by default have a falling edge while FPo0 is low (CKo4 has no corresponding
output frame pulse). At the output frame boundary, CKo5 will by default have a rising edge while FPo5 (FPo_OFF2)
will be low. The duration of the frame pulse low cycle and the frequency of the corresponding output clock are
shown in Table 3 on page 24. Every frame pulse and clock output can be tristated by programming the enable bits
in the Internal Mode Selection (IMS) register.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
Pin Name
Output Timing Rate
Output Timing Unit
FPo0 pulse width
CKo0
244
ns
MHz
ns
4.096
FPo1 pulse width
CKo1
122
8.192
MHz
ns
FPo2 pulse width
CKo2
61
16.384
244, 122, 61 or 30
4.096, 8.192, 16.384 or 32.768
1.544 or 2.048
MHz
ns
FPo3 pulse width
CKo3
MHz
MHz
ns
CKo4
FPo5 pulse width
CKo5
51
19.44
MHz
Table 3 - Output Timing Generation
The output timing is dependent on the timing mode that is selected. When the device is in Divided Slave mode, the
frequencies on CKo0 - 3 cannot be greater than the input clock, CKi. For example, if the input clock is 8.192 MHz,
the CKo2 pin will not produce a valid output clock and the CKo3 pin can only be programmed to output a
4.096 MHz or 8.192 MHz clock signal. The output clocks CKo4 - 5 will not generate valid outputs unless the
SLV_DPLLEN (bit 13) of the Control Register (CR) is set.
In Master mode there are programmable output frame pulse, FPo3, and clock pins, CKo3 and CKo4. The outputs
from FPo3 and CKo3 are programmed by the CKOFPO3SEL1 - 0 (bits 13 - 12) in the Output Clock and Frame
Pulse Selection (OCFSR) register. The output clock pin, CKo4, is controlled by setting the CKO4SEL (bit 14) in the
OCFSR register.
In Multiplied Slave mode, CKo4 and CKo5 are not available unless SLV_DPLLEN is set in the Control Register. All
other clocks and frame pulses correspond to the timing shown in Table 3 above.
The device also delivers positive or negative output frame pulse and ST-BUS/GCI-Bus output clock formats via the
programming of various bits in the Output Clock and Frame Pulse Selection Register (OCFSR). By default, the
device delivers the negative output clock format. The ZL50019 can also deliver GCI-Bus format output frame pulses
by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit
setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in
GCI-Bus mode.
The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P, CKO3P,
CKO4P and CKO5P bits to generate the FPo0 - 3 and CKo0 - 5 timing. FPo_OFF2 is configured to provide the
non-offset frame pulse corresponding to the 19.44 MHz clock on CKo5 by setting the FP19EN (bit 10) in the
FPOFF2 register. In this instance, FPo_OFF2 can be labeled as FPo5.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
CKOFPO0EN = 1
FPO0P = 0
FPO0POS = 0
CKOFPO0EN = 1
FPO0P = 1
FPO0POS = 0
CKOFPO0EN = 1
FPO0P = 0
FPO0POS = 1
CKOFPO0EN = 1
FPO0P = 1
FPO0POS = 1
CKOFPO0EN = 1
CKO0P = 0
CKo0 = 4.096 MHz
CKOFPO0EN = 1
CKO0P = 1
CKo0 = 4.096 MHz
Figure 7 - Output Timing for CKo0 and FPo0
CKOFPO1EN = 1
FPO1P = 0
FPO1POS = 0
CKOFPO1EN = 1
FPO1P = 1
FPO1POS = 0
CKOFPO1EN = 1
FPO1P = 0
FPO1POS = 1
CKOFPO1EN = 1
FPO1P = 1
FPO1POS = 1
CKOFPO1EN = 1
CKO1P = 0
CKo1 = 8.192 MHz
CKOFPO1EN = 1
CKO1P = 1
CKo1 = 8.192 MHz
Figure 8 - Output Timing for CKo1 and FPo1
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
CKOFPO2EN = 1
FPO2P = 0
FPO2POS = 0
CKOFPO2EN = 1
FPO2P = 1
FPO2POS = 0
CKOFPO2EN = 1
FPO2P = 0
FPO2POS = 1
CKOFPO2EN = 1
FPO2P = 1
FPO2POS = 1
CKOFPO2EN = 1
CKO2P = 0
CKo2 = 16.384 MHz
CKOFPO2EN = 1
CKO2P = 1
CKo2 = 16.384 MHz
Figure 9 - Output Timing for CKo2 and FPo2
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
FPO3P = 0
FPO3POS = 0
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
FPO3P = 1
FPO3POS = 0
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
FPO3P = 0
FPO3POS = 1
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
FPO3P = 1
FPO3POS = 1
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
CKO3P = 0
CKo3 = 32.768 MHz
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
CKO3P = 1
CKo3 = 32.768 MHz
NOTE:
When CKOFPO3SEL1-0 = “00,” the output for FPo3 and CKo3 follow the same as Figure 7: Output Timing for CKo0 and FPo0
When CKOFPO3SEL1-0 = “01,” the output for FPo3 and CKo3 follow the same as Figure 8: Output Timing for CKo1 and FPo1
When CKOFPO3SEL1-0 = “10,” the output for FPo3 and CKo3 follow the same as Figure 9: Output Timing for CKo2 and FPo2
Figure 10 - Output Timing for CKo3 and FPo3 with CK0FPo3SEL1-0=”11”
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
CKOFPO0EN = 1
FPO0P = 0
FPO0POS = 0
CKOFPO0EN = 1
FPO0P = 1
FPO0POS = 0
CKOFPO0EN = 1
FPO0P = 0
FPO0POS = 1
CKOFPO0EN = 1
FPO0P = 1
FPO0POS = 1
CKOFPO4EN = 1
CKO4P = 0
CKO4SEL = 0
CKo4 = 2.048 MHz
CKO4EN = 1
CKO4P = 1
CKO4SEL = 0
CKo4 = 2.048 MHz
CKOFPO4EN = 1
CKO4P = 0
CKO4SEL = 1
CKo4 = 1.544 MHz
CKO4EN = 1
CKO4P = 1
CKO4SEL = 1
CKo4 = 1.544 MHz
Note:
While there is no frame pulse output directly tied to the CKo4, the output clocks are based on the frame pulse generated by FPo0
Figure 11 - Output Timing for CKo4
FPo5 (FPo_OFF2)
FP19EN = 1
CKO5EN = 1
CK5 = 19.44 MHz
Figure 12 - Output Timing for CKo5 and FPo5 (FPo_OFF2)
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
8.0 Data Input Delay and Data Output Advancement
Various registers are provided to adjust the input delay and output advancement for each input and output data
stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream.
If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The
sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams, unless the stream is operating
at 16.384 Mbps, in which case the fractional bit delay has a 1/2-bit increment. By default, the sampling point is set
to the 3/4-bit location for non-16.384 Mbps data rates and the 1/2-bit location for the 16.384 Mbps data rate.
The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4-bit increment unless the output
stream is operating at 16.384 Mbps, in which case the output bit advancement has a 1/2-bit increment from 0 to 1/2
bit. By default, there is 0 output bit advancement.
Although input delay or output advancement features are available on streams which are operating in bi-directional
mode it is not recommended, as it can easily cause bus contention. If users require this function, special attention
must be given to the timing to ensure contention is minimized.
8.1 Input Bit Delay Programming
The input bit delay programming feature provides users with the flexibility of handling different wire delays when
designing with source streams for different devices.
By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame
boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream
Input Control Register 0 - 31 (SICR0 - 31) as described in Section 44 on page 73. The input bit delay can range
from 0 to 7 bits.
FPi
Channel 2
Last Channel
Channel 0
Channel 1
STi[n]
7
0
5
7
0
5
7
0
5
4 3
4 3
1
6
7
4 3
1
2
6
7
4 3
1
2
6
7
2
0
1
2
0
1
2
0
1
2
Bit Delay = 0
(Default)
Bit Delay = 1
Last Channel
Channel 2
Channel 0
Channel 1
STi[n]
5
5
5
6 4 3
4 3
6
4 3
6
4 3
2
5
Bit Delay = 1
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 13 - Input Bit Delay Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
8.2 Input Bit Sampling Point Programming
In addition to the input bit delay feature, the ZL50019 allows users to change the sampling point of the input bit by
programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 31 (SICR0 - 31). For input
streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the
sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. When the stream is operating at 16.384 Mbps, the default
sampling point is 1/2 bit and can be adjusted to a 4/4 bit position.
FPi
Sampling Point = 3/4 Bit
Channel 0
6
STi[n]
Last Channel
STIN[n]SMP1-0 = 00
1
5
2
0
7
(2,
4
or 8 Mbps
-
Default)
Sampling Point = 1/4 Bit
Channel 0
Last Channel
STi[n]
STIN[n]SMP1-0 = 01
(2, 4 or 8 Mbps)
1
5
6
0
7
Sampling Point = 1/2 Bit
Channel 0
STi[n]
Last Channel
STIN[n]SMP1-0 = 10
(2, 4 or 8 Mbps)
STIN[n]SMP1-0 = 00
(16 Mbps - Default)
1
5
6
0
7
Sampling Point = 4/4 Bit
Channel 0
Last Channel
STi[n]
STIN[n]SMP1-0 = 11
(2, 4 or 8 Mbps)
STIN[n]SMP1-0 = 10
(16 Mbps)
1
5
2
6
0
7
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively
Figure 14 - Input Bit Sampling Point Programming
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to
control the sampling point in the Stream Input Control Register 0 - 31 (SICR0 - 31).
Nominal Channel n Boundary
Nominal Channel n+1 Boundary
STi[n]
0
7
6
5
4
3
2
1
0
7
000 01
111 11
111 00
111 10
111 01
110 11
110 00
110 10
110 01
101 11
101 00
101 10
101 01
100 11
100 00
100 10
100 01
000 10
000 00 (Default)
000 11
001 01
001 10
001 00
001 11
010 01
010 10
010 00
010 11
011 01
011 10
011 00
011 11
The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay
The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset
Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point
Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point)
Figure 15 - Input Bit Delay and Factional Sampling Point
8.3 Output Advancement Programming
This feature is used to advance the output data of individual output streams with respect to the output frame
boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output
Control Register 0 - 31 (SOCR0 - 31).
By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4)
of the Stream Output Control Register 0 - 31 (SOCR0 - 31) as described in Table 46 on page 77. The output bit
advancement can vary from 0 to 7 bits.
FPi
Channel 2
Last Channel
Channel 0
Channel 1
STio[n]
7
6
5
4 3
4
1
6
1
2
2
0
7
7
6
5
7
6
5
4 3
3
6
5
4 3
1
0
6
5
0
7
2
1
0
7
2
1
Bit Adv = 0
(Default)
Bit Advancement = 1
Channel 0
Channel 2
Last Channel
Channel 1
STio[n]
5
3
1
4 3
1
4 3
2
4 3 2
Bit Adv = 1
2
0
2
0
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
8.4 Fractional Output Bit Advancement Programming
In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers
better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the
serial data output pins.
By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the
output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the
Stream Output Control Register 0 - 31 (SOCR0 - 31). For all streams running at any data rate except 16.384 Mbps
the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. For streams operating at 16.384 Mbps, the
fractional bit advancement can be set to either 0 or 1/2 bit.
FPi
Last Channel
Channel 0
STio[n]
7
5
0
6
1
STo[n]FA1-0 = 00
(Default 2, 4, 8 or
16Mb/s)
2
Fractional Bit Advancement = 1/4 Bit
Channel 0
Last Channel
STio[n]
7
5
0
6
4
1
STo[n]FA1-0
=
01
(2, 4 or 8 Mbps)
Fractional Bit Advancement = 1/2 Bit
Channel 0
STio[n]
Last Channel
STo[n]FA1-0
=
10
(2,
4
or 8Mbps)
7
5
4
0
6
1
STo[n]FA1-0 = 01
(16 Mbps)
Fractional Bit Advancement = 3/4 Bit
Channel 0
Last Channel
STio[n]
7
5
4
0
6
1
STo[n]FA1-0 = 11
(2, 4 or 8 Mbps)
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
8.5 External High Impedance Control Advancement
The external high impedance signals can be programmed to better match the timing required by the external
buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit offset of
their corresponding ST-BUS/GCI-Bus output streams. In addition, for all high impedance streams operating at any
data rate except 16.384 Mbps, the user can advance the STOHZ signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by
programming STOHZ[n]A 2 - 0 (bit 11 - 9) in the Stream Output Control Register. When the stream is operating at
16.384 Mbps, the additional STOHZ advancement can be set to 0, 1/2 or 4/4 bits by programming the same
register.
FPi
HiZ
CH2
STio[n]
Last
CH0
CH1
CH3
Last-1
Last
CH0
Last-2
STOHZ Advancement (Programmable in 4 steps of 1/4 bit
for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps
Programmable in 2 steps of 1/2 bit for 16.384 Mbps)
STOHZ[n]
(Default = No Advancement)
STOHZ[n]
(with Advancement)
Output Frame Boundary
Note: n = 0 to 15
Note: Last = Last Channel of 31, 63, 127 and 255 for 2.048 Mbps, 4.096 Mbps. 8.192 Mbps and 16.384 Mbps modes respectively.
Figure 18 - Channel Switching External High Impedance Control Timing
9.0 Data Delay Through the Switching Paths
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant delay to maintain the frame
integrity of the information through the switch. The delay through the device varies according to the type of
throughput delay selected by the V/C (bit 14) in the Connection Memory Low when CMM = 0.
9.1 Variable Delay Mode
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for
voice applications where the minimum throughput delay is more important than frame integrity. The delay through
the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN
(bit 4) in the Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0.
If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the
output stream will not be valid.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
In variable delay mode, the delay depends on the combination of the source and destination channels of the input
and output streams.
m = input channel number
n = output channel number
n-m <= 0
0 < n-m < 7
n-m = 7
STio >= STi
n-m
n-m > 7
STio < STi
1 frame + (n-m)
Table 4 - Delay for Variable Delay Mode
T = Delay between input and output 1 frame - (m-n)
For example, if Stream 4 Channel 2 is switched to Stream 5 Channel 9 with variable delay, the data will be output in
the same 125 µs frame. Contrarily, if Stream 6 Channel 1 is switched to Stream 9 Channel 3, the information will
appear in the following frame.
Frame N + 1
Frame N
STi4
CH2
L-2 L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2 L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2 L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2 L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
STio5
CH9
STi6
CH1
STio9
CH3
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps 8.192 Mbps, or 16.384 Mbps respectively
Figure 19 - Data Throughput Delay for Variable Delay
9.2 Constant Delay Mode
In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames -
Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 channel delay if the last channel on a
stream is switched to the first channel of a stream. The maximum delay is 3 frames - 1 channel. This occurs when
the first channel of a stream is switched to the last channel of a stream. The constant delay mode is available for all
output channels.
The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (m) and
output channel number (n). The data throughput delay (T) is:
T = 2 frames + (n - m)
The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit
is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable
variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay
mode.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
Frame N + 2
Frame N
Frame N + 1
STi L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
STio L-2 L-1 CH0 CH1 CH2 CH3
STi L-2 L-1 CH0 CH1 CH2 CH3
STio L-2 L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps 8.192 Mbps, or 16.384 Mbps respectively
Figure 20 - Data Throughput Delay for Constant Delay
10.0 Connection Memory Description
The connection memory consists of two blocks, Connection Memory Low (CM_L) and Connection Memory High
(CM_H). The CM_L is 16-bits wide and is used for channel switching and other special modes. The CM_H is 5-bits
wide and is used for the voice coding function. When UAEN (bit 15) of the Connection Memory Low (CM_L) is low,
µ-law/A-law conversion will be turned off and the contents of CM_H will be ignored. Each connection memory
location of the CM_L or CM_H can be read or written via the 16 bit microprocessor port within one microprocessor
access cycle. See Table 51 on page 80 for the address mapping of the connection memory. Any unused bits will be
reset to zero on the 16-bit data bus.
For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed
low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source
(input) stream address. The 5-bit contents of the CM_H will be ignored during the normal channel switching mode
without the µ-law/A-law conversion when UAEN (bit 15) of the Connection Memory Low (CM_L) is set to zero. If
µ-law/A-law conversion is required, the CM_H bits must be programmed first to provide the voice/data information,
the input coding law and the output coding law before the assertion of UAEN (bit 15) in the Connection Memory
Low.
When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50019 will operate in one of
the special modes described in Table 53 on page 81. When the per-channel message mode is enabled, MSG7 - 0
(bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial data stream as message output data.
When the per-channel message mode is enabled, the µ-law/A-law conversion can also be enabled as required.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
11.0 Connection Memory Block Programming
This feature allows for fast initialization of the connection memory after power up.
11.1 Memory Block Programming Procedure
1. Set MBPE (bit 3) in the Control Register (CR) from low to high.
2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded
into CM_L.
3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The val-
ues stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15
- 3) and the programmable values in the CM_H (bits 4 - 0) will be loaded with zero values.
The following tables show the resulting values that are in the CM_L and CM_H connection memory locations.
Bit
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
Value
BPD2 BPD1 BPD0
Table 5 - Connection Memory Low After Block Programming
Bit
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Value
Table 6 - Connection Memory High After Block Programming
Note: Bits 15 to 5 are reserved in Connection Memory High and should always be 0.
It takes at least two frame periods (250 µs) to complete a block program cycle.
MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming
process has completed.
MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block
programming process. This is not an automatic action taken by the device and must be performed manually.
Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting
MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low. If the
MBPE bit was used to terminate the block programming, the MBPS bit will have to be set low before enabling other
device operations.
12.0 Device Performance in Master Mode and Slave Modes
This device has two main operating modes - Master mode and Slave mode.
If the device is programmed to work in Master mode, it is expected that the input clock and frame pulse will be
supplied from the embedded DPLL, either directly (using loopback mode) or outside the device. Sources and
destinations of the device’s serial input and output data, respectively, have to be synchronized with the device’s
output clock and frame pulse. In Master mode, output clocks and frame pulses are driven by the DPLL and they are
always available with any of the specified frequencies.
In addition to Master mode, there are two main Slave modes: Divided Slave mode and Multiplied Slave mode. If the
device is in Slave mode, output clocks and frame pulses are generated based on CKi and FPi. In Divided Slave
mode, output clocks and frame pulses are directly divided from CKi/FPi; therefore, the output clock rate cannot
exceed the CKi rate. In Multiplied Slave mode, the output clocks and frame pulses are generated from a clock
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
internal to the device and are synchronized to CKi and FPi. All specified frequencies are available on CKo[0:3] in
Multiplied Slave mode.
By default, the DPLL is disabled if the device is in Slave mode. However, the DPLL can be activated by
programming the SLV_DPLLEN bit in the Control Register. When the DPLL is enabled, CKo4, CKo5 and FPo5 will
be generated from the DPLL, while the other clocks and frame pulses will be generated based on CKi/FPi. In this
case the DPLL will be fully functional, including its capability of reference monitoring.
Note that an external oscillator is required whenever the DPLL is used.
Table 7, “ZL50019 Operating Modes” on page 36 summarizes the different modes of operation available within the
ZL50019. Each Major mode (explained below) has an associated Minor mode that is determined by setting the
relevant Input Control pins and Control Register bits (Table 16, “Control Register (CR) Bits” on page 48) indicated in
the table.
Device
Input Pins
CR Register
Bits
Output Clock Pins
Reference Lock Enabled
Data Pins
Operating Mode
Control
Signal
OSCi CKi
Clock Source
Major
Minor
OSC_EN MODE_4M
[1:0]
OPM SLV_DPLLEN CKi_LP
[1:0]
CKo0-3 CKo4-5 CKo0-3 CKo4-5 STi
STo
Master
CKi
Loopback
4 M
1
1
0
1
0
00
2 0MHz 4/8/16 M 00
X
X
1
0
1
0
0
1
X
Freerun, Holdover
or REF0-3
Yes
Yes
Yes
No
CKi*
Cko2
CKi
Cko2
(DPLL)
Divided
Slave
11
00
11
00
11
00
11
00
20 MHz
4 M
8/16 M
4 M
01
X0
11
CKi
REF0-3
CKo0-3
(CKi)
8/16 M
4 M
X
20 MHz
X
X
8/16 M
4 M
8/16 M
4 M
Multiplied
Slave
CKi MULT REF0-3
X
Yes
No
CKo0-3
(CKi MULT)
8/16 M
4 M
8/16 M
4 M
X1
8/16 M
8/16 M
Legend:
X
Don’t care or not applicable.
Reference Lock
Refers to what signal the output pins are locked to:
REF0-3 = Normal
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
* CKi must be phase aligned (edge synchronous) to CLo0-3.
Clock Source
Refers to which clock samples STi and which clock outputs STo; STi applies when STio is input; STo applies when STio is output.
Table 7 - ZL50019 Operating Modes
12.1 Master Mode Performance
When the device is in Master mode, the DPLL is phase-locked to the one of four DPLL reference signals, REF0 to
REF3, which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz signal. The on-chip DPLL also offers reference switching and monitoring, jitter attenuation, freerun and
holdover functions. In this mode, STio0 - 31 are driven by a clock generated by the DPLL, which also provides all
the output clocks (CKo0 - 5) and frame pulses (FPo0 - 3 and FPo_OFF0 - 2).
12.2 Divided Slave Mode Performance
When the device is in Divided Slave mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same amount of jitter as the input clock (CKi), but the output data rate cannot exceed the input data
rate defined by CKi. For example, if CKi is 4.096 MHz, the output data rate cannot be higher than 2.048 Mbps, and
the generated output clock rates cannot exceed 4.096 MHz. If the DPLL is not enabled, an external oscillator is
optional in Divided Slave mode.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
12.3 Multiplied Slave Mode Performance
When the device is in Multiplied Slave mode, device hardware is used to multiply CKi internally. STio0 - 31 are
driven by this internally generated clock. In this mode, the output data rate can be any specified data rate, but the
output streams and clocks may have different jitter characteristics from the input clock (CKi). If the DPLL is not
enabled, an external oscillator is not required in Multiplied Slave mode.
13.0 Overall Operation of the DPLL
The DPLL accepts four input references and delivers six output clocks and five output frame pulses. The DPLL
meets or exceeds all of the requirements of the Telcordia GR-1244-CORE standard for a Stratum 4E compliant
PLL. This includes the freerun, reference switching and monitoring, jitter/wander attenuation and holdover
functions. The intrinsic output jitter of the DPLL does not exceed 1 ns (except for the 1.544 MHz output).
The DPLL is able to lock to an input reference presented on the REF0 - 3 inputs. It is possible to force the DPLL
module to lock to a selected reference, to prefer one reference, to enter holdover mode or to freerun.
13.1 DPLL Functional Modes
There are four functional modes for the DPLL: normal, holdover, automatic and freerun modes. In addition to these
four functional modes, the DPLL can also be programmed to internal reset mode.
13.1.1 Normal Operating Mode
In the normal operating mode, the DPLL generates clocks and frame pulses that are phase locked to the active
input reference. Jitter on the input clock is attenuated by the DPLL.
13.1.2 Holdover Mode
In holdover mode, the DPLL no longer synchronizes the output clock to any input reference. It maintains the
frequency that it was at prior to entering holdover mode. The holdover operation typically happens when the input
clock becomes unreliable or is lost altogether. It takes some time for the system to realize that the input clock is
unreliable. Meanwhile, the DPLL tracks an unreliable clock. Therefore the DPLL could hold to an invalid frequency
when it enters holdover mode. In order to prevent this situation, the DPLL stores the current frequency at regular
intervals in holdover memory so that it can restore the frequency of the input clock just after the input clock became
unreliable.
13.1.3 Automatic Mode
In this mode, the state machine controls the DPLL based on the settings in the registers and the quality of the
reference input clocks. The DPLL is internally either in normal or in holdover mode.
13.1.4 Freerun Mode
In freerun mode, the DPLL generates a fixed output frequency based on the crystal oscillator frequency. To meet
Stratum 4E, the accuracy of the circuitry for the freerunning output clock must be 32 ppm or better.
13.1.5 DPLL Internal Reset Mode
DPLL_IRM (bit 0) in the DPLL Control Register (DPLLCR) enables the internal reset mode. In the internal reset
mode, the DPLL module is disabled to save power. The circuit will be reset continuously and no output clocks will
be generated. When the internal DPLL module is in the internal reset mode, all registers remain accessible. Note
that applying the DPLL reset does not reset the DPLL registers: they preserve the values that they had prior to
entering reset.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
14.0 DPLL Frequency Behaviour
14.1 Input Frequencies
The DPLL is capable of synchronizing to one of the following input frequencies:
8 kHz
1.544 MHz (DS1)
2.048 MHz (E1)
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Table 8 - DPLL Input Reference Frequencies
14.2 Input Frequencies Selection
The input frequencies of REF 0 - 3 can be automatically detected or programmed independently by the Reference
Frequency Register (RFR) if RFRE (bit 1) in the DPLL Control Register (DPLLCR) is set. The detected frequency of
the selected reference is indicated in the Reference Change Status Register (RCSR). In addition, the detected
frequencies of all four references are indicated in the Reference Frequency Status Register (RFSR). See Table 27
on page 58, Table 28 on page 59, Table 36 on page 65 and Table 42 on page 71 for the detailed bit description of
the DPLL Control Register (DPLLCR), Reference Frequency Register (RFR), Reference Change Status Register
(RCSR) and Reference Frequency Status Register (RFSR), respectively.
14.3 Output Frequencies
The DPLL generates a limited number of output signals. All signals are synchronous to each other and in the
normal operating mode, are locked to the selected input reference. The DPLL provides outputs with the following
frequencies:
CKo0
CKo1
CKo2
CKo3
CKo4
CKo5
FPo0
FPo1
FPo2
FPo3
FPo5
4.096 MHz
8.192 MHz
16.384 MHz
4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
1.544 MHz or 2.048 MHz
19.44 MHz
8 kHz (244 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (61 ns wide pulse)
8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse)
8 kHz (51 ns wide pulse)
Table 9 - Generated Output Frequencies
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
14.4 Pull-In/Hold-In Range (also called Locking Range)
The widest tolerance required for any of the given input clock frequencies is ±130 ppm for the T1 clock
(1.544 MHz). If the system clock (crystal/oscillator) accuracy is ±30 ppm, it requires a minimum pull-in range of
±160 ppm. Users who do not require the ±30 ppm freerun accuracy of the DPLL can use a ±100 ppm system clock.
Therefore the pull-in range is a minimal ±230 ppm. The pull-in range of this device is ±260 ppm.
15.0 Jitter Performance
15.1 Input Clock Cycle to Cycle Timing Variation Tolerance
The ZL50019 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50019
to synchronize off a low cost DPLL when it is in either Divided Slave mode or Multiplied Slave mode.
15.2 Input Jitter Acceptance
The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the
input clock that the DPLL must accept without making cycle slips or losing lock. The lower the jitter frequency, the
larger the jitter acceptance. For jitter frequencies below a tenth of the cut-off frequency of the DPLL's jitter transfer
function, any input jitter will be followed by the DPLL. The maximum value of jitter tolerance for the DPLL is
±1023UIp-p
.
15.3 Jitter Transfer Function
The corner frequency (-3 dB) of the Stratum 4E DPLL is 15.2 Hz.
16.0 DPLL Specific Functions and Requirements
16.1 Lock Detector
To determine if the DPLL is locked to the input clock, a lock detector monitors the phase value output of the phase
detector, which represents the difference between input reference and output feedback clock. If the phase value is
below a certain threshold for a certain interval, the DPLL is pronounced locked to the input clock. The monitoring is
done in intervals of 4 ms. The lock detector threshold and the interval are programmable by the user through the
Lock Detector Threshold Register (LDTR) and the Lock Detector Interval Register (LDIR) respectively. See
Table 32 on page 62 and Table 33 on page 63 for the bit descriptions of the Lock Detector Threshold Register
(LDTR) and Lock Detector Interval Register (LDIR) respectively. The value of the Lock Detector Threshold Register
(LDTR) should be programmed with respect to the maximum expected jitter frequency and amplitude on the
selected input references.
The lock status can be monitored through the Reference Change Status Register (RCSR). See Table 36 on
page 65 for the bit description of the Reference Change Status Register (RCSR).
16.2 Maximum Time Interval Error (MTIE)
Several standards require that the output clock of the DPLL may not move in phase more than a certain amount. In
order to meet those standards, a special circuit maintains the phase of the DPLL output clock during reference and
mode rearrangements. The total output phase change or Maximum Timing Interval Error (MTIE) during
rearrangements is less than 31 ns per rearrangement, exceeding Stratum 4E requirements. After a large number of
reference switches, the accumulated phase error can become significant, so it is recommended to use MTIE reset
in such situations, to realign outputs to the nearest edge of the selected reference. The MTIE reset can be
programmed by setting MTR (bit 7) in the Reference Change Control Register (RCCR), as described in Table 35 on
page 63.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
16.3 Phase Alignment Speed (Phase Slope)
Besides total phase change, standards also require a certain rate of the phase change of the output clock. The
phase alignment speed is programmable by the user through a value in the Slew Rate Limit Register (SRLR) as
described in Table 34 on page 63. Stratum 4E requires that the phase alignment speed not exceed 81 ns per
1.326 ms (61ppm). The width of the register and the limiter circuitry provide a maximum phase change alignment
speed of 186 ppm. The phase alignment speed default value is 56 ppm.
16.4 Reference Monitoring
The quality of the four input reference clocks is continuously monitored by the reference monitors. There are
separate reference monitor circuits for the four DPLL references. References are checked for short phase (single
period) deviations as well as for frequency (multi-period) deviations with hysteresis.
The Reference Status Register (RSR) reports the status of the reference monitors. The register bits are described
in Table 40 on page 68. The Reference Mask Register (RMR) allows users to ignore the monitoring features of the
reference monitors. See Table 41 on page 69 for details.
16.5 Single Period Reference Monitoring
Values for short phase deviations (upper and lower limit) are programmable through registers. The unit of the binary
values of these numbers is 100 MHz clock period (10 ns). Single period deviation limits are more relaxed than multi
period limits, and are used for early detection of the reference loss, or huge phase jumps.
The values for the upper and lower limits are shown in the following table:
Reference
Frequency
Comment
8 kHz
10 UIp-p
0.3 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Table 10 - Values for Single Period Limits
16.6 Multiple Period Reference Monitoring
To monitor reference failure based on frequency offset, multi period checking is performed. Reference validation
time is prescribed by Telcordia GR-1244-CORE and is between 10 and 30 seconds. To meet the criteria for
reference validation time, the time base for multi period monitoring has to be big enough. To implement hysteresis,
the upper limits are split into near upper and far upper limits and the lower limits are split into near lower and far
lower limits. The reference failure is detectable only when the reference passes far limits, but passing is not
detected until the reference is within near limits. The zone between near and far limits, called the “grey zone”, is
required by standards and prevents unnecessary reference switching when the selected reference is close to the
boundary of failure.
The monitor makes a decision about reference validity after two consecutive measurements with respect to its time
base. The time base for multi-period monitoring is 10 seconds. The time base is defined in the number of reference
clock cycles.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
The device has two sets of limits the Stratum 4E default limits and the Relaxed Stratum 4E limits (see Table 11 on
page 41). The ST4_LIM bit in Table 27, DPLL Control Register (DPLLCR) Bits is used to select between the two
sets of limits.
Stratum 4E Default Limits
(in 10 ns units)
Relaxed Stratum 4E Limits
(in 10 ns units)
Far Upper Limit
Near Upper Limit
Nominal Value
-82.487 ppm
-64.713 ppm
-250 ppm
-240 ppm
0 ppm
Near Lower Limit
Far Lower Limit
64.713 ppm
82.487 ppm
240 ppm
250 ppm
Table 11 - Multi-Period Hysteresis Limits
17.0 Microprocessor Port
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 -
0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Refer to Figure 24 on page 88, Figure 25 on page 89, Figure 26 on page 90 and Figure 27 on page 91 for the
microprocessor timing.
18.0 Device Reset and Initialization
The RESET pin is used to reset the ZL50019. When this pin is low, the following functions are performed:
•
•
•
•
•
synchronously puts the microprocessor port in a reset state
tristates the STio0 - 31 outputs
drives the STOHZ0 - 15 outputs to high
preloads all internal registers with their default values (refer to the individual registers for default values)
clears all internal counters
18.1 Power-up Sequence
The recommended power-up sequence is for the VDD_IO supply (normally +3.3 V) to be established before the
power-up of the VDD_CORE supply (normally +1.8 V). The VDD_CORE supply may be powered up at the same time
as VDD_IO, but should not “lead” the VDD_IO supply by more than 0.3 V.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
18.2 Device Initialization on Reset
Upon power up, the ZL50019 should be initialized as follows:
•
•
•
•
Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high
Set the TRST pin to low to disable the JTAG TAP controller
Reset the device by pulsing the RESET pin to zero for longer than 1 µs
After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the
device to stabilize from the power down state before the first microprocessor port access can occur
•
•
•
•
Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs
Wait at least 500 µs prior to the next microport access (see Note below)
Use the block programming mode to initialize the connection memory
Release the ODE pin from low to high after the connection memory is programmed
Note: If an external oscillator is used, the waiting time is 500 µs. Without the external oscillator, if CKi is
16.384 MHz, the waiting time is 500 µs; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the
waiting time is 2 ms.
18.3 Software Reset
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset. There
are two software reset bits in the Software Reset Register (SRR). SRSTDPLL (bit 0) is used to reset the DPLL while
SRSTSW (bit 1) resets the rest of the switch.
19.0 Pseudo Random Bit Generation and Error Detection
The ZL50019 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output
streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input
streams. Each transmitter can generate a BER sequence with a pattern of 215-1 pseudorandom code (ITU O.151).
Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1
frame time (125 µs). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and
TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled.
(This is the default state.)
Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be
transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER
receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies
has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how
many BER channels are to be monitored by the BER receiver.
For each input stream, there is a set of registers for the BER test. The registers are as follows:
•
•
•
BER Receiver Control Register (BRCR) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register
(BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver.
BER Receiver Start Register (BRSR) - ST[n]BRS7 - 0 (bit 7 - 0) defines the input channel from which the
BER sequence will start to be compared.
BER Receiver Length Register (BRLR) - ST[n]BL8 - 0 (bit 8 - 0) define how many channels the sequence
will last. Depending on the data rate being used, the BER test can last for a maximum of 32, 64, 128 or 256
channels at the data rates of 2.048, 4.096, 8.192 or 16.384 Mbps, respectively. The minimum length of the
BER test is a single channel. The user must take care to program the correct channel length for the BER test
so that the channel length does not exceed the total number of channels available in the stream.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
•
BER Receiver Error Register (BRER) - This read-only register contains the number of counted errors. When
the error count reaches 0xFFFF, the BER counter will stop updating so that it will not overflow. ST[n]CBER
(bit 1) in the BER Receiver Control Register is used to reset the BRER register.
For normal BER operation, CMM (bit 0) must be 1 in the Connection Memory Low (CM_L). PCC1 - 0 (bits 2 - 1) in
the Connection Memory Low must be programmed to “10” to enable the per-stream based BER transmitters. For
each stream, the length (or total number of channels) of BER testing can be as long as one whole frame, but the
channels MUST be consecutive. Upon completion of programming the connection memory, the corresponding BER
receiver can be started by setting ST[n]SBER (bit 0) in the BRCR to high. There must be at least 2 frames (250 µs)
between completion of connection memory programming and starting the BER receiver before the BER receiver
can correctly identify BER errors. A 16 bit BER counter is used to count the number of bit errors.
20.0 PCM A-law/µ-law Translation
The ZL50019 provides per-channel code translation to be used to adapt pulse code modulation (PCM) voice or
data traffic between networks which use different encoding laws. Code translation is valid in both Connection Mode
and Message Mode.
In order to use this feature, the Connection Memory High (CM_H) entry for the output channel must be
programmed. V/D (bit 4) defines if the traffic in the channel is voice or data. Setting ICL1 - 0 (bits 3 - 2) programs the
input coding law and OCL1 - 0 (bits 1- 0) programs the output coding law as shown in Table 12.
The different code options are:
Input Coding
(ICL1- 0)
Output Coding
(OCL1 - 0)
Voice Coding
(V/D bit = 0)
Data Coding
(V/D bit = 1)
00
01
10
00
01
10
ITU-T G.711 A-law
ITU-T G.711 µ-law
A-law without Alternate Bit
Inversion (ABI)
No code
Alternate Bit Inversion (ABI)
Inverted Alternate Bit
Inversion (ABI)
11
11
µ-law without Magnitude
All bits inverted
Inversion (MI)
Table 12 - Input and Output Voice and Data Coding
For voice coding options, the ITU-T G.711 A-law and ITU-T G.711 µ-law are the standard rules for encoding. A-law
without Alternate Bit Inversion (ABI) is an alternative code that does not invert the even bits (6, 4, 2, 0). µ-law
without Magnitude Inversion (MI) is an alternative code that does not perform inversion of magnitude bits (6, 5, 4, 3,
2, 1, 0).
When transferring data code, the option “no code” does not invert the bits. The Alternate Bit Inversion (ABI) option
inverts the even bits (6, 4, 2, 0) while the Inverted Alternate Bit Inversion (ABI) inverts the odd bits (7, 5, 3, 1). When
the “All bits inverted” option is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted.
The input channel and output channel encoding law are configured independently. If the output channel coding is
set to be different from the input channel, the ZL50019 performs translation between the two standards. If the input
and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection
Memory High (CM_H) must be set on a per-channel basis, it is not possible to translate between voice and data
encoding laws.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
21.0 Quadrant Frame Programming
By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 31), users can divide one frame of input
data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or
zero for robbed-bit signaling. The four quadrant frames are defined as follows:
Data Rate
Quadrant 0
Quadrant 1
Quadrant 2
Quadrant 3
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
Channel 0 - 7
Channel 0 - 15
Channel 0 - 31
Channel 0 - 63
Channel 8 - 15
Channel 16 - 31
Channel 32 - 63
Channel 16 - 23
Channel 32 - 47
Channel 64 - 95
Channel 24 - 31
Channel 48 - 63
Channel 96 - 127
Channel 64 - 127 Channel 128 - 191 Channel 192 - 255
Table 13 - Definition of the Four Quadrant Frames
When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit
5 - 3) or STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or MSB of every input channel in the quadrant is forced to “1”
or “0” as shown by the following table:
STIN[n]Q[y]C[2:0]
Action
0xx
Normal Operation
100
101
110
111
Replaces LSB of every channel in Quadrant y with ‘0’
Replaces LSB of every channel in Quadrant y with ‘1’
Replaces MSB of every channel in Quadrant y with ‘0’
Replaces MSB of every channel in Quadrant y with ‘1’
Note: y = 0, 1, 2, 3
Table 14 - Quadrant Frame Bit Replacement
Note that Quadrant Frame Programming and BER reception cannot be used simultaneously on the same input
stream.
22.0 JTAG Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The
operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
22.1 Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50019 test functions. It consists of three input pins and one output pin
as follows:
•
•
Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of
the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
Test Mode Selection Inputs (TMS) - The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to high when it is not driven from an external source.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
•
•
•
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. The registers are
described in a subsequent section. The received input data is sampled at the rising edge of the TCK pulse.
This pin is internally pulled to high when it is not driven from an external source.
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or test data register are serially shifted out towards TDo. The data from TDo is
clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the
TDo driver is set to a high impedance state.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to high when it is not
driven from an external source.
22.2 Instruction Register
The ZL50019 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a
four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP
Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDi and TDo during data register scanning.
22.3 Test Data Registers
As specified in the IEEE-1149.1 standard, the ZL50019 JTAG interface contains three test data registers:
•
•
•
The Boundary-Scan Register - The Boundary-Scan register consists of a series of boundary-scan cells
arranged to form a scan path around the boundary of the ZL50019 core logic.
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo.
The Device Identification Register - The JTAG device ID for the ZL50019 is 0C36314BH
Version
<31:28>
<27:12>
<11:1>
<0>
0000
Part Number
Manufacturer ID
LSB
1100 0011 0110 0011
0001 0100 101
1
22.4 BSDL
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE-1149.1 test interface.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
23.0 Register Address Mapping
Address
A13 - A0
CPU
Access
Register
Name
Abbreviation
Reset By
0000H
0001H
0002H
0003H
0004H
R/W
R/W
R/W
R/W
R/W
Control Register
CR
Switch/Hardware
Switch/Hardware
Hardware Only
DPLL/Hardware
DPLL/Hardware
Internal Mode Selection Register
Software Reset Register
IMS
SRR
Output Clock and Frame Pulse Control Register OCFCR
Output Clock and Frame Pulse Selection
Register
OCFSR
0005H
0006H
0007H
0010H
0011H
0012H
0013H
0014H
0040H
0041H
0042H
0043H
0045H
0047H
0048H
0049H
004BH
004CH
0066H
0067H
0068H
0069H
006AH
006BH
006CH
R/W
FPo_OFF0 Register
FPOFF0
FPOFF1
FPOFF2
IFR
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
Switch/Hardware
Switch/Hardware
Switch/Hardware
Switch/Hardware
Switch/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
R/W
FPo_OFF1 Register
R/W
FPo_OFF2 Register
R Only
R Only
R Only
R Only
R Only
R/W
Internal Flag Register
BER Error Flag Register 0
BER Error Flag Register 1
BER Receiver Lock Register 0
BER Receiver Lock Register 1
DPLL Control Register
BERFR0
BERFR1
BERLR0
BERLR1
DPLLCR
RFR
R/W
Reference Frequency Register
Centre Frequency Register - Lower 16 Bits
Centre Frequency Register - Upper 10 Bits
Frequency Offset Register
Lock Detector Threshold Register
Lock Detector Interval Register
Slew Rate Limit Register
R/W
CFRL
CFRU
FOR
R/W
R Only
R/W
LDTR
LDIR
R/W
R/W
SRLR
RCCR
RCSR
IR
R/W
Reference Change Control Register
Reference Change Status Register
Interrupt Register
R Only
R Only
R/W
Interrupt Mask Register
IMR
R/W
Interrupt Clear Register
ICR
R Only
R/W
Reference Failure Status Register
Reference Mask Register
RSR
RMR
R Only
R/W
Reference Frequency Status Register
Output Jitter Control Register
RFSR
OJCR
Table 15 - Address Map for Registers (A13 = 0)
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
Address
A13 - A0
CPU
Access
Register
Name
Abbreviation
Reset By
0100H -
011FH
R/W
R/W
R/W
R/W
R/W
R/W
R Only
Stream Input Control Registers 0 - 31
SICR0 - 31
SIQFR0 - 31
SOCR0 - 31
BRSR0 - 31
BRLR0 - 31
BRCR0 - 31
BRER0 - 31
Switch/Hardware
Switch/Hardware
Switch/Hardware
Switch/Hardware
Switch/Hardware
Switch/Hardware
Switch/Hardware
0120H -
013FH
Stream Input Quadrant Frame Registers 0 - 31
Stream Output Control Registers 0 - 31
BER Receiver Start Registers 0 - 31
BER Receiver Length Registers 0 - 31
BER Receiver Control Registers 0 - 31
BER Receiver Error Registers 0 - 31
0200H -
021FH
0300H -
031FH
0320H -
033FH
0340H -
035FH
0360H -
037FH
Table 15 - Address Map for Registers (A13 = 0) (continued)
47
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
24.0 Detailed Register Description
External Read/Write Address: 0000H
Reset Value: 0000H
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SLV_
OPM
1
OPM
0
CKi_
LP
FPIN
POS
CKINP
FPINP
CKIN
1
CKIN
0
VAR
EN
MBPE
OSB
MS1
MS0
DPLLEN
Bit
Name
Description
15 - 14
13
Unused
Reserved. In normal functional mode, these bits MUST be set to zero.
SLV_
DPLL Enable in Slave Mode (ignored in Master Mode).
When this bit is low, DPLL is disabled in Slave mode.
DPLLEN
When this bit is high and OSC_EN = 1, the DPLL is enabled in Slave mode.
When SLV_DPLLEN is set in Slave mode, CKo[3:0] and FPo[3:0] are generated from
CKi and FPi. CKo[5:4] and FPo[5] are locked to the selected input reference (one of
REF[3:0]). In this mode of operation, the DPLL retains its functionality, including the
generation of the REF_FAIL[3:0] output signals. See Table 7, “ZL50019 Operating
Modes” on page 36 for more details.
12 - 11 OPM1 - 0 Operation Mode.
These bits are used to set the device in Master/Slave operation. Refer to Table 7,
“ZL50019 Operating Modes” on page 36 for more details.
10
CKi_LP
CKi and FPi Loopback (Ignored in Slave mode)
When this bit is low, CKi and FPi are used as input pins.
When this bit is high, CKi and FPi are internally looped back from CKo2 (16.384 MHz)
and FPo2 respectively, and CKi pin and FPi pin should be tied low or high externally;
CKIN1 - 0 (bits 6 - 5) of this register should be programmed to be 00. See Table 7,
“ZL50019 Operating Modes” on page 36 for more details.
9
8
FPINPOS Input Frame Pulse (FPi) Position
When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)
CKINP
FPINP
Clock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
7
Frame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.
6 - 5
CKIN1 - 0 Input Clock (CKi) and Frame Pulse (FPi) Selection
CKIN1 - 0
FPi Active Period
CKi
00
01
10
11
61 ns
122 ns
244 ns
16.384 MHz
8.192 MHz
4.096 MHz
Reserved
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 12,
should also be set to define the input clock mode.
Table 16 - Control Register (CR) Bits
48
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0000H
Reset Value: 0000H
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SLV_
OPM
1
OPM
0
CKi_
LP
FPIN
POS
CKINP
FPINP
CKIN
1
CKIN
0
VAR
EN
MBPE
OSB
MS1
MS0
DPLLEN
Bit
Name
Description
4
VAREN
Variable Delay Mode Enable
When this bit is low, the variable delay mode is disabled on a device-wide basis.
When this bit is high, the variable delay mode is enabled on a device-wide basis.
3
2
MBPE
Memory Block Programming Enable
When this bit is high, the connection memory block programming mode is enabled to
program the connection memory. When it is low, the memory block programming mode is
disabled.
OSB
Output Stand By Bit:
This bit enables the STio0 - 31 and the STOHZ0 -15 serial outputs. The following table
describes the HiZ control of the serial data outputs:
RESET SRSTSW ODE
OSB
Bit
STio0 - 31
STOHZ0 - 15
Pin
(in SRR)
Pin
0
1
1
1
1
X
1
0
0
0
X
X
0
1
1
X
X
X
0
HiZ
HiZ
HiZ
HiZ
Driven High
Driven High
Driven High
Driven High
1
Active
(Controlled by CM)
Active
(Controlled by CM)
Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to
SOCR0 - 31 (bit 2 - 0).
1 - 0
MS1 - 0
Memory Select Bits
These two bits are used to select connection memory low, connection high or data mem-
ory for access by CPU:
MS1 - 0
Memory Selection
00
01
10
11
Connection Memory Low Read/Write
Connection Memory High Read/Write
Data Memory Read
Reserved
Table 16 - Control Register (CR) Bits (continued)
49
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0001H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
STIO_
BDH
BDL
RBER
EN
TBER
EN
BPD
2
BPD
1
BPD
0
MBPS
PD_EN
Bit
Name
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
15 - 9
8
Unused
STIO_PD_ STio Pull-down Enable
EN
When this bit is low, the pull-down resistors on all STio pads will be disabled.
When this bit is high, the pull-down resistors on all STio pads will be enabled.
7
BDH
Bi-directional Control for Streams 16-31
BDH
STio16 - 31 Operation
0
normal operation:
STi16-31 are inputs
STio16-31 are outputs
1
bi-directional operation:
STi16-31 tied low internally
STio16-31 are bi-directional
6
BDL
Bi-directional Control for Streams 0-15
BDL
STio0 - 15 Operation
0
normal operation:
STi0-15 are inputs
STio0-15 are outputs
1
bi-directional operation:
STi0-15 tied low internally
STio0-15 are bi-directional
5
4
RBEREN
TBEREN
BPD2 - 0
PRBS Receiver Enable
When this bit is low, all the BER receivers are disabled. To enable any BER receivers,
this bit MUST be high.
PRBS Transmitter Enable
When this bit is low, all the BER transmitters are disabled. To enable any BER
transmitters, this bit MUST be high.
3 - 1
Block Programming Data
These bits refer to the value to be loaded into the connection memory, whenever the
memory block programming feature is activated. After the MBPE bit in the Control
Register is set to high and the MBPS bit in this register is set to high, the contents of
the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3
of the Connection Memory Low and bits 15 - 0 of Connection Memory High are
zeroed.
Table 17 - Internal Mode Selection Register (IMS) Bits
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0001H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
STIO_
BDH
BDL
RBER
EN
TBER
EN
BPD
2
BPD
1
BPD
0
MBPS
PD_EN
Bit
Name
Description
Memory Block Programming Start:
0
MBPS
A zero to one transition of this bit starts the memory block programming function. The
MBPS and BPD2 - 0 bits in this register must be defined in the same write operation.
Once the MBPE bit in the Control Register is set to high, the device requires two
frames to complete the block programming. After the programming function has fin-
ished, the MBPS bit returns to low, indicating the operation is completed. When MBPS
is high, MBPS or MBPE can be set to low to abort the programming operation.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started. As long as this bit is high, the user must maintain the same logical
value to the other bits in this register to avoid any change in the device setting.
Table 17 - Internal Mode Selection Register (IMS) Bits (continued)
External Read/Write Address: 0002H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SRST
SW
SRST
DPLL
Bit
Name
Description
15 - 2
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
1
0
SRSTSW
Software Reset Bit for Switch
When this bit is low, switching blocks are in normal operation. When this bit is high,
switching blocks are in software reset state. Refer to Table 15, “Address Map for
Registers (A13 = 0)” on page 46 for details regarding which registers are affected.
SRSTDPLL Software Reset Bit for DPLL
When this bit is low, the DPLL block is in normal operation. When this bit is high, the
DPLL block is in software reset state. Refer to Table 15, “Address Map for Registers
(A13 = 0)” on page 46 for details regarding which registers are affected.
Table 18 - Software Reset Register (SRR) Bits
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0003H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
FPOF2
EN
FPOF1
EN
FPOF0
EN
CKO5
EN
CKO4
EN
CKO
FPO3
EN
CKO
FPO2
EN
CKO
FPO1
EN
CKO
FPO0
EN
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
8
7
6
5
FPOF2EN
FPOF1EN
FPOF0EN
CKO5EN
FPo_OFF2/FPo5 Enable
When this bit is high, output frame pulse FPo_OFF2/FPo5 is enabled.
When this bit is low, output frame pulse FPo_OFF2/FPo5 is in high impedance state.
FPo_OFF1 Enable
When this bit is high, output frame pulse FPo_OFF1 is enabled.
When this bit is low, output frame pulse FPo_OFF1 is in high impedance state.
FPo_OFF0 Enable
When this bit is high, output frame pulse FPo_OFF0 is enabled.
When this bit is low, output frame pulse FPo_OFF0 is in high impedance state.
CKo5 Enable
When this bit is high, output clock CKo5 is enabled.
When this bit is low, output clock CKo5 is in high impedance state.
CKo5 is available in Master mode or in Slave mode with SLV_DPLLEN set.
4
CKO4EN
CKo4 Enable
When this bit is high, output clock CKo4 is enabled.
When this bit is low, output clock CKo4 is in high impedance state.
CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set.
3
2
1
0
CKOFPO3 CKo3 and FPo3 Enable
When this bit is high, output clock CKo3 and output frame pulse FPo3 are enabled.
When this bit is low, CKo3 and FPo3 are in high impedance state.
EN
CKOFPO2 CKo2 and FPo2 Enable
When this bit is high, output clock CKo2 and output frame pulse FPo2 are enabled.
When this bit is low, CKo2 and FPo2 are in high impedance state.
EN
CKOFPO1 CKo1 and FPo1 Enable
When this bit is high, output clock CKo1 and output frame pulse FPo1 are enabled.
When this bit is low, CKo1 and FPo1 are in high impedance state.
EN
CKOFPO0 CKo0 and FPo0 Enable
When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled.
When this bit is low, CKo0 and FPo0 are in high impedance state.
EN
Table 19 - Output Clock and Frame Pulse Control Register (OCFCR) Bits
52
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0004H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CKO4
P
CKO4
SEL
CKO
FPO3
SEL1
CKO
FPO3
SEL0
CKO3
P
FPO3
P
FPO3
POS
CKO2
P
FPO2
P
FPO2
POS
CKO1
P
FPO1
P
FPO1
POS
CKO0
P
FPO0
P
FPO0
POS
Bit
Name
Description
Output Clock (CKo4) Polarity Selection
15
CKO4P
When this bit is low, the output clock CKo4 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo4 rising edge aligns with the
frame boundary.
CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set.
14
CKO4SEL
Output Clock (CKo4) Frequency Selection
When this bit is low, the output clock CKo4 is 2.048 MHz.
When this bit is high, the output clock CKo4 is 1.544 MHz.
CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set.
13 - 12
CKOFPO3 Output Clock (CKo3) Frequency and Output Frame Pulse (FPo3) Pulse Cycle
SEL1 - 0 Selection
CKOFPO3
FPo3
CKo3
SEL1 - 0
00
01
10
11
244 ns
122 ns
61 ns
4.096 MHz
8.192 MHz
16.384 MHz
32.768 MHz
30 ns
11
CKO3P
Output Clock (CKo3) Polarity Selection
When this bit is low, the output clock CKo3 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo3 rising edge aligns with the
frame boundary.
10
9
FPO3P
FPO3POS
CKO2P
Output Frame Pulse (FPo3) Polarity Selection
When this bit is low, the output frame pulse FPo3 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo3 has the positive frame pulse format.
Output Frame Pulse (FPo3) Position
When this bit is low, FPo3 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo3 starts from frame boundary (as defined by GCI-Bus).
8
Output Clock (CKo2) Polarity Selection
When this bit is low, the output clock CKo2 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo2 rising edge aligns with the
frame boundary.
7
FPO2P
Output Frame Pulse (FPo2) Polarity Selection
When this bit is low, the output frame pulse FPo2 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo2 has the positive frame pulse format.
Table 20 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits
53
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0004H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CKO4
P
CKO4
SEL
CKO
FPO3
SEL1
CKO
FPO3
SEL0
CKO3
P
FPO3
P
FPO3
POS
CKO2
P
FPO2
P
FPO2
POS
CKO1
P
FPO1
P
FPO1
POS
CKO0
P
FPO0
P
FPO0
POS
Bit
Name
Description
6
FPO2POS
Output Frame Pulse (FPo2) Position
When this bit is low, FPo2 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo2 starts from frame boundary (as defined by GCI-Bus).
5
CKO1P
Output Clock (CKo1) Polarity Selection
When this bit is low, the output clock CKo1 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo1 rising edge aligns with the
frame boundary.
4
3
2
FPO1P
FPO1POS
CKO0P
Output Frame Pulse (FPo1) Polarity Selection
When this bit is low, the output frame pulse FPo1 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo1 has the positive frame pulse format.
Output Frame Pulse (FPo1) Position
When this bit is low, FPo1 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo1 starts from frame boundary (as defined by GCI-Bus).
Output Clock (CKo0) Polarity Selection
When this bit is low, the output clock CKo0 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo0 rising edge aligns with the
frame boundary.
1
0
FPO0P
Output Frame Pulse (FPo0) Polarity Selection
When this bit is low, the output frame pulse FPo0 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo0 has the positive frame pulse format.
FPO0POS
Output Frame Pulse (FPo0) Position
When this bit is low, FPo0 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus).
Note: In Divided Slave modes, CKo3 - 1 cannot exceed frequency of CKi.
Note: CKo[5:4] are available in Master mode or in Slave mode with SLV_DPLLEN set.
Table 20 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued)
54
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0005H - 0007H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
9
8
7
6
5
4
3
2
1
0
FP19
EN
FOF[n]
OFF7
FOF[n]
OFF6
FOF[n]
OFF5
FOF[n]
OFF4
FOF[n]
OFF3
FOF[n]
OFF2
FOF[n]
OFF1
FOF[n]
OFF0
FOF[n]
C1
FOF[n]
C0
Bit
Name
Description
15 - 11
10
Unused
FP19EN
Reserved. In normal functional mode, these bits MUST be set to zero.
19.44 MHz Frame Pulse Output Enable. (For FPo_OFF2 only)
This bit is a reserved bit for FPo_OFF0 and FPo_OFF1, and MUST be set to zero.
When this bit is high, FPo_OFF2 is negative frame pulse output corresponding to
19.44 MHz without channel offset.
When this bit is low, FPo_OFF2 is output frame pulse with channel offset.
FOF[n]OFF7 - 0
FOF[n]C1 - 0
9 - 2
1 - 0
FPo_OFF[n] Channel Offset
The binary value of these bits refers to the channel offset from original frame bound-
ary. Permitted channel offset values depend on bits 1-0 of this register.
FPo_OFF[n] Control bits
FOF[n]OFF7 - 0
FOF[n]C
1-0
Data Rate
(Mbps)
FPo_OFF[n]
Polarity
Control
Position
Control
Permitted
Pulse Cycle Width
Channel Offset
00
01
10
2.048
4.096
8.192
one 4.096 MHz clock
one 8.192 MHz clock
one 16.384 MHz
clock
0 - 31
0 - 63
0 - 127
FPO0P FPO0POS
FPO1P FPO1POS
FPO2P FPO2POS
11
16.384
one 16.384 MHz
clock
0 - 255
FPO2P FPO2POS
Note: [n] denotes output offset frame pulse from 0 to 2.
Table 21 - FPo_OFF[n] Register (FPo_OFF[n]) Bits
55
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read Address: 0010H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
OUT
ERR
IN
ERR
Bit
Name
Description
15 - 2
Unused
Reserved
In normal functional mode, these bits are zero.
1
0
OUTERR
INERR
Output Error (Read Only)
This bit is set high when the total number of output channels is programmed to be
more than the maximum capacity of 2048, in which case the output channels beyond
the maximum capacity should be disabled.
This bit will be cleared automatically after programming is corrected.
Input Error (Read Only)
This bit is set high when the total number of input channels is programmed to be more
than the maximum capacity of 2048, in which case the input channels beyond the
maximum capacity should be disabled.This bit will be cleared automatically after pro-
gramming is corrected.
Table 22 - Internal Flag Register (IFR) Bits - Read Only
External Read Address: 00011H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
F15
BER
F14
BER
F13
BER
F12
BER
F11
BER
F10
BER
F9
BER
F8
BER
F7
BER
F6
BER
F5
BER
F4
BER
F3
BER
F2
BER
F1
BER
F0
Bit
15 - 0
Name
Description
BERF[n]
BER Error Flag[n]:
If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not
zero.
If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Note: [n] denotes input stream from 0 - 15.
Table 23 - BER Error Flag Register 0 (BERFR0) Bits - Read Only
56
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 00012H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
F31
BER
F30
BER
F29
BER
F28
BER
F27
BER
F26
BER
F25
BER
F24
BER
F23
BER
F22
BER
F21
BER
F20
BER
F19
BER
F18
BER
F17
BER
F16
Bit
15 - 0
Name
Description
BERF[n]
BER Error Flag[n]:
If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not
zero.
If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Note: [n] denotes input stream from 16 - 31.
Table 24 - BER Error Flag Register 1 (BERFR1) Bits - Read Only
External Read Address: 00013H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
L15
BER
L14
BER
L13
BER
L12
BER
L11
BER
L10
BER
L9
BER
L8
BER
L7
BER
L6
BER
L5
BER
L4
BER
L3
BER
L2
BER
L1
BER
L0
Bit
15 - 0
Name
Description
BERL[n]
BER Receiver Lock[n]
If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked.
If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 0 - 15.
Table 25 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only
57
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read Address: 00014H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
L31
BER
L30
BER
L29
BER
L28
BER
L27
BER
L26
BER
L25
BER
L24
BER
L23
BER
L22
BER
L21
BER
L20
BER
L19
BER
L18
BER
L17
BER
L16
Bit
15 - 0
Name
Description
BERL[n]
BER Receiver Lock[n]:
If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked.
If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 16 - 31.
Table 26 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only
External Read/Write Address: 0040H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
0
3
0
2
0
1
0
ST4_
LIM
RFRE
DPLL
_IRM
Bit
Name
Description
15-6
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
5
ST4_LIM Stratum 4E Limits Select Bit
When this bit is high, the stratum 4E limits are used for reference monitoring (i.e.,
+/-64.713 ppm and +/-82.487 ppm over 10 seconds).When this bit is low, more relaxed
Relaxed Stratum 4E limits are used for reference monitoring (i.e., +/-240 ppm and
+/-250 ppm over 10 seconds). This is used in applications where a low quality clock
(+/-100 ppm) is used as a reference.
4-2
1
Unused
RFRE
Reserved
In normal functional mode, these bits MUST be set to zero.
Reference Frequency Register Enable
When this bit is low, the reference frequency value used in the DPLL comes from
appropriate reference frequency detector. When this bit is high, the reference frequency
value comes from Reference Frequency Register (RFR).
0
DPLL_
IRM
DPLL Internal Reset Mode
When this bit is low, the DPLL module is in the operational state. When this bit is high,
the DPLL module is in the power saving mode. Registers are not reset and are still
accessible in the power saving mode.
Table 27 - DPLL Control Register (DPLLCR) Bits
58
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0041H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
R3F2
R3F1
R3F0
R2F2
R2F1
R2F0
R1F2
R1F1
R1F0
R0F2
R0F1
R0F0
Bit
Name
Description
15-12
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
11 - 9
R3F2 - 0
Reference 3 Frequency Bits
When the RFRE bit of the DPLLCR register is high, these bits are used to select the
REF3 input frequency. When the RFRE bit is low, these bits are ignored.
R3F2
R3F1
R3F0
REF 3 Input Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Reserved
8 - 6
R2F2 - 0
Reference 2 Frequency Bits: When the RFRE bit of the DPLLCR register is high, these
bits are used to select the REF2 input frequency. When the RFRE bit is low, these bits
are ignored.
R2F2
R2F1
R2F0
REF 2 Input Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Reserved
Table 28 - Reference Frequency Register (RFR) Bits
59
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0041H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
R3F2
R3F1
R3F0
R2F2
R2F1
R2F0
R1F2
R1F1
R1F0
R0F2
R0F1
R0F0
Bit
Name
Description
5 - 3
R1F2 - 0
Reference 1 Frequency Bits
When the RFRE bit of the DPLLCR register is high, these bits are used to select the
REF1 input frequency. When the RFRE bit is low, these bits are ignored.
R1F2
R1F1
R1F0
REF 1 Input Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Reserved
2 - 0
R0F2 - 0
Reference 0 Frequency Bits
When the RFRE bit of the DPLLCR register is high, these bits are used to select the
REF0 input frequency. When the RFRE bit is low, these bits are ignored.
R0F2
R0F1
R0F0
REF 0 Input Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Reserved
Table 28 - Reference Frequency Register (RFR) Bits (continued)
60
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0042H
Reset Value: 16B1H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFN
15
CFN
14
CFN
13
CFN
12
CFN
11
CFN
10
CFN
9
CFN
8
CFN
7
CFN
6
CFN
5
CFN
4
CFN
3
CFN
2
CFN
1
CFN
0
Bit
Name
Description
15 - 0
CFN15 - 0 Center Frequency Number (CFN) Lower 16 Bits: The total binary value of these bits
and the CFRU register bits defines the output center frequency number according to the
following formula:
CFN
-----------
fOUT =
× fMCLK
226
where, fOUT is desired output center frequency, while fMCLK is frequency of DPLL master
clock. For given master clock frequency of 100 MHz, and desired output center fre-
quency of 65.536 MHz, the CFN has the value of:
26
26
65.536MHz
-------------------------------
CFN = 2
×
= 2 × 0.65536 = 43980465 = 29F16B1H
100MHz
The register contents should be changed only if compensation for input oscillator (or
crystal) frequency offset is required.
e.g., if master clock frequency is off by +20 ppm (100.002 MHz -> 5 times multiplied c20i
of 20.0004 MHz), the CFN should be programmed to be:
26
26
65.536MHz
----------------------------------
CFN = 2
×
= 2 × 0.65534689 = 43979585 = 29F1341H
100.002MHz
The default value of this register SHOULD NOT be changed in any other circumstances.
Table 29 - Centre Frequency Register - Lower 16 Bits (CFRL)
External Read/Write Address: 0043H
Reset Value: 029FH
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
CFN
25
CFN
24
CFN
23
CFN
22
CFN
21
CFN
20
CFN
19
CFN
18
CFN
17
CFN
16
Bit
Name
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
15 - 10
9 - 0
Unused
CFN25 - 16 Center Frequency Number (CFN) Upper 10 Bits: The total binary value of these bits
and the CFRL register bits represents the center frequency number (CFN) explained
under CFRL register bits explanation.
The default value of this register should be changed only if compensation for input oscil-
lator (or crystal) frequency offset is required, and SHOULD NOT be changed in any other
circumstances.
Table 30 - Centre Frequency Register - Upper 10 Bits (CFRU)
61
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read Only Address: 0045H
15
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FOF
14
FOF
13
FOF
12
FOF
11
FOF
10
FOF
9
FOF
8
FOF
7
FOF
6
FOF
5
FOF
4
FOF
3
FOF
2
FOF
1
FOF
0
Bit
Name
Unused
Description
Reserved. In normal functional mode, this bit is zero.
15
14 - 0
FOF14 - 0 Frequency Offset Bits: The binary value of these bits represents the current deviation
of the DPLL output from its center frequency. Defined in same units as CFN in the 2's
complement format.
Note 1: Output frequency offset, relative to master clock, will be represented as the following:
+10 ppm: CFN x 0.00001 = 440 = 01B8H
-10 ppm: CFN x (-0.00001) = -440 = 7E48H
Table 31 - Frequency Offset Register (FOR) Bits - Read Only
External Read/Write Address: 0047H
Reset Value: 000FH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDT
15
LDT
14
LDT
13
LDT
12
LDT
11
LDT
10
LDT
9
LDT
8
LDT
7
LDT
6
LDT
5
LDT
4
LDT
3
LDT
2
LDT
1
LDT
0
Bit
Name
LDT15 - 0 Lock Detect Threshold Bits
Description
15 - 0
The binary value of these bits defines the upper limit of the absolute phase from the
phase detector output for lock detection.
When the value of the absolute phase is less than or equal to LDT for duration of time
defined by the LDIR register, the DPLL locks.
When the value of the absolute phase is greater than LDT for duration of time defined by
the LDIR register divided by 256, the DPLL does not lock.
Note: LDT should be calculated as per the maximum expected amplitude of jitter on the active input reference
using the following formula:
LDT = MAX_EXP_JITTER (ms) x 2
1.52 (ms)
Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e., 10 x 488.2 ns = 4882 ns)
(assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15.2)
x 2 = 642 = 0282H
Table 32 - Lock Detector Threshold Register (LDTR) Bits
62
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0048H
Reset Value: 2C00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDI
15
LDI
14
LDI
13
LDI
12
LDI
11
LDI
10
LDI
9
LDI
8
LDI
7
LDI
6
LDI
5
LDI
4
LDI
3
LDI
2
LDI
1
LDI
0
Bit
Name
Description
15 - 0
LDI15 - 0 Lock Detector Interval Bits
The binary value of these bits defines the time interval that the output phase detector
must be below the lock detect threshold to declare lock. Unsigned representation of the
LDI bits is defined in 4 ms intervals.
Table 33 - Lock Detector Interval Register (LDIR) Bits
External Read/Write Address: 0049H
Reset Value: 099FH (see Note)
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
3
2
1
0
SRL
12
SRL
11
SRL
10
SRL
9
SRL
8
SRL
7
SRL
6
SRL
5
SRL
4
SRL
3
SRL
2
SRL
1
SRL
0
Bit
Name
Description
15 - 13
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
12 - 0
SRL12 - 0 Slew Rate Limit Bits
The binary value of these bits defines the maximum rate of DPLL phase change (phase
slope), where the phase represents difference between the input reference and output
feedback clock. Defined in same units as CFN (unsigned).
Note: The default value is ±56 ppm (’h099F/CFN = 56 ppm).
Table 34 - Slew Rate Limit Register (SRLR) Bits
External Read/Write Address: 004BH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
MTR
PRS
1
PRS
0
PMS
2
PMS
1
PMS
0
FDM
1
FDM
0
Bit
Name
Description
15 - 8
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
Table 35 - Reference Change Control Register (RCCR) Bits
63
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 004BH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
MTR
PRS
1
PRS
0
PMS
2
PMS
1
PMS
0
FDM
1
FDM
0
Bit
Name
Description
7
MTR
MTIE Reset
When this bit is low, the MTIE circuit applies a phase offset between the reference input
clock and the DPLL output clock and the phase offset value is maintained. When this bit
is high, MTIE circuit is in its reset state and the phase offset value is reset to zero,
causing alignment of the DPLL output clocks to nearest edge of the selected input
reference.
6 - 5
PRS1 - 0 Preferred Reference Selection Bits
These bits select the preferred reference from one of the input references.
PRS1
PRS0
Preferred Reference Selection
0
0
1
1
0
1
0
1
REF0
REF1
REF2
REF3
4 - 2
PMS2 - 0 Preference Mode Selection Bits
These bits select one of the preference modes:
PMS2
PMS1
PMS0
Preference Mode
No Preference
Preference as per the setting
of the PRS1 - 0 bits
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
1
Force REF0
Force REF1
Force REF2
Force REF3
Reserved
110 - 111
1 - 0
FDM1 - 0 Force DPLL Mode
These bits force the DPLL into one of the valid operation modes.
FDM1
FDM0
Operation Mode
0
0
1
1
0
1
0
1
Automatic
Normal
Holdover
Freerun
Table 35 - Reference Change Control Register (RCCR) Bits (continued)
64
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read Only Address: 004CH
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
SLM
LST
RFR2
RFR1
RFR0
RES1
RES0
DPM1
DPM0
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits are zero.
8
7
SLM
LST
Slew Rate Limiter Status Bit
If the device sets this bit to high, the DPLL phase difference between the input and output
clocks is changing at the slew rate limit defined in the Slew Rate Limit Register (SRLR).
Lock Status Bit
If the device sets this bit to high, while the LDTR and LDIR registers are programmed
properly, the DPLL output clocks are locked to the selected input reference.
If this bit is low, the DPLL output clocks are not yet locked to the selected input reference.
6 - 4
RFR2 - 0 Reference Frequency Indicator Bits
These bits represent the frequency of the selected reference indicated by the reference
bits (RES1 - 0) in this register.
Frequency of the Selected
RFR2
RFR1
RFR0
Reference
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44MHz
Reserved
3 - 2
RES1 - 0 Reference Select Indicator Bits: These bits indicate which one of the four reference
inputs (REF0 - 3 pins) is being selected by the device.
RES1
RES0
Input Reference in use
0
0
1
1
0
1
0
1
REF 0
REF 1
REF 2
REF 3
Table 36 - Reference Change Status Register (RCSR) Bits - Read Only
65
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read Only Address: 004CH
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
SLM
LST
RFR2
RFR1
RFR0
RES1
RES0
DPM1
DPM0
Bit
Name
Description
1 - 0
DPM1 - 0 DPLL Mode Bits
These bits indicate the DPLL operation mode.
DPM1
DPM0
DPLL Operation Mode
0
0
1
1
0
1
0
1
MTIE
Normal
Holdover
Freerun
Table 36 - Reference Change Status Register (RCSR) Bits - Read Only (continued)
External Read Only Address: 0066H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
0
LCI
RCI
HOI
Bit
Name
Description
15 - 4
Unused
Reserved
In normal functional mode, this bit is zero.
3
2
1
LCI
RCI
HOI
Lock Change Interrupt Bit
If the device sets this bit to high, the device lock status has changed.
Reference Change Interrupt Bit
If the device sets this bit to high, the selected reference has changed.
Holdover Interrupt Bit
If the device sets this bit to high, the device has entered or recovered from the
holdover/MTIE mode.
0
Unused
Reserved
In normal functional mode, this bit is zero.
Note 1: If any of these bits are set, the interrupt output will become active unless the Interrupt Mask Register (IMR) has a high
value for that particular bit.
Note 2: Any of these bits can be cleared by setting the appropriate bit in the Interrupt Clear Register.
Table 37 - Interrupt Register (IR) Bits - Read Only
66
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0067H
Reset Value: 000FH
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
LIM
RIM
HIM
1
Bit
Name
Description
15 - 4
Unused Reserved
In normal functional mode, these bits MUST be set to zero.
3
2
1
0
LIM
RIM
HIM
Lock Interrupt Mask Bit
When this bit is high, it masks the lock status change interrupt.
Reference Change Interrupt Mask Bit
When this bit is high, it masks the reference change interrupt.
Holdover Interrupt Mask Bit
When this bit is high, it masks the holdover entry/exit interrupt.
Unused Reserved
In normal functional mode, this bit MUST be set to one.
Table 38 - Interrupt Mask Register (IMR) Bits
External Read/Write Address: 0068H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
1
ICB
3
ICB
2
ICB
1
Bit
Name
Description
15 - 4
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
3 - 1
0
ICB3 - 1
Unused
Interrupt Clear Bits
Writing a “1” to any bit in this register will clear the corresponding bit in the Interrupt
Register (IR). The Interrupt Clear Register is self-clearing, i.e. once it has completed
its action, the ICR register bit returns to 0.
Reserved
In normal functional mode, this bit MUST be set to one.
Table 39 - Interrupt Clear Register (ICR) Bits
67
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read Only Address: 0069H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
FL
R3
FU
R2
R2
R2
FL
R2
FU
R1
R1
R1
FL
R1
FU
R0
R0
R0
FL
R0
FU
FML
FMU
FML
FMU
FML
FMU
FML
FMU
Bit
Name
Description
15
14
13
12
11
10
9
R3FML
Reference 3 Multi-period Lower Limit Fail Bit
f the device sets this bit to high, the input REF3 fails the multi-period lower limit check.
(See Table 11, “Multi-Period Hysteresis Limits” on page 41)
R3FMU
R3FL
Reference 3 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the multi-period upper limit
check. (See Table 11, “Multi-Period Hysteresis Limits” on page 41)
Reference 3 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the single-period lower limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
R3FU
Reference 3 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the single-period upper limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
R2FML
R2FMU
R2FL
Reference 2 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the multi-period lower limit check.
(See Table 11, “Multi-Period Hysteresis Limits” on page 41)
Reference 2 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the multi-period upper limit
check. (See Table 11, “Multi-Period Hysteresis Limits” on page 41)
Reference 2 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the single-period lower limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
8
R2FU
Reference 2 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the single-period upper limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
7
R1FML
R1FMU
R1FL
Reference 1 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the multi-period lower limit check.
(See Table 11, “Multi-Period Hysteresis Limits” on page 41)
6
Reference 1 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the multi-period upper limit
check. (See Table 11, “Multi-Period Hysteresis Limits” on page 41)
5
Reference 1 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the single-period lower limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
4
R1FU
Reference 1 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the single-period upper limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
Table 40 - Reference Failure Status Register (RSR) Bits - Read Only
68
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read Only Address: 0069H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
FL
R3
FU
R2
R2
R2
FL
R2
FU
R1
R1
R1
FL
R1
FU
R0
R0
R0
FL
R0
FU
FML
FMU
FML
FMU
FML
FMU
FML
FMU
Bit
Name
Description
3
2
1
0
R0FML
Reference 0 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF0 fails the multi-period lower limit check.
(See Table 11, “Multi-Period Hysteresis Limits” on page 41)
R0FMU
R0FL
Reference 0 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF0 fails the multi-period upper limit
check. (See Table 11, “Multi-Period Hysteresis Limits” on page 41)
Reference 0 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF0 fails the single-period lower limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
R0FU
Reference 0 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF0 fails the single-period upper limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
Table 40 - Reference Failure Status Register (RSR) Bits - Read Only (continued)
External Read/Write Address: 006AH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
ML
R3
R2
R2
R2
ML
R2
R1
R1
R1
ML
R1
R0
R0
R0
ML
R0
MML
MMU
MU
MML
MMU
MU
MML
MMU
MU
MML
MMU
MU
Bit
Name
Description
15
14
13
12
R3MML
Reference 3 Multi-period Lower Limit Mask Bit
When this bit is high, it masks the multi-period lower limit check (or forces pass) for
REF3.
R3MMU
R3ML
Reference 3 Multi-period Upper Limit Mask Bit
When this bit is high, it masks the multi-period upper limit check (or forces pass) for
REF3.
Reference 3 Single-period Lower Limit Mask Bit
When this bit is high, it masks the single-period lower limit check (or forces pass) for
REF3.
R3MU
Reference 3 Single-period Upper Limit Mask Bit
When this bit is high, it masks the single-period upper limit check (or forces pass) for
REF3.
Table 41 - Reference Mask Register (RMR) Bits
69
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 006AH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
ML
R3
R2
R2
R2
ML
R2
R1
R1
R1
ML
R1
R0
R0
R0
ML
R0
MML
MMU
MU
MML
MMU
MU
MML
MMU
MU
MML
MMU
MU
Bit
Name
Description
11
10
9
R2MML
Reference 2 Multi-period Lower Limit Mask Bit
When this bit is high, it masks the multi-period lower limit check (or forces pass) for
REF2.
R2MMU
R2ML
Reference 2 Multi-period Upper Limit Mask Bit
When this bit is high, it masks the multi-period upper limit check (or forces pass) for
REF2.
Reference 2 Single-period Lower Limit Mask Bit
When this bit is high, it masks the single-period lower limit check (or forces pass) for
REF2.
8
R2MU
Reference 2 Single-period Upper Limit Mask Bit
When this bit is high, it masks the single-period upper limit check (or forces pass) for
REF2.
7
R1MML
R1MMU
R1ML
Reference 1 Multi-period Lower Limit Mask Bit
When this bit is high, it masks the multi-period lower limit check (or forces pass) for
REF1.
6
Reference 1 Multi-period Upper Limit Mask Bit
When this bit is high, it masks the multi-period upper limit check (or forces pass) for
REF1.
5
Reference 1 Single-period Lower Limit Mask Bit
When this bit is high, it masks the single-period lower limit check (or forces pass) for
REF1.
4
R1MU
Reference 1 Single-period Upper Limit Mask Bit
When this bit is high, it masks the single-period upper limit check (or forces pass) for
REF1.
3
R0MML
R0MMU
R0ML
Reference 0 Multi-period Lower Limit Mask Bit
When this bit is high, it masks the multi-period lower limit check (or forces pass) for
REF0.
2
Reference 0 Multi-period Upper Limit Mask Bit
When this bit is high, it masks the multi-period upper limit check (or forces pass) for
REF0.
1
Reference 0 Single-period Lower Limit Mask Bit
When this bit is high, it masks the single-period lower limit check (or forces pass) for
REF0.
Table 41 - Reference Mask Register (RMR) Bits (continued)
70
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 006AH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
ML
R3
R2
R2
R2
ML
R2
R1
R1
R1
ML
R1
R0
R0
R0
ML
R0
MML
MMU
MU
MML
MMU
MU
MML
MMU
MU
MML
MMU
MU
Bit
Name
Description
0
R0MU
Reference 0 Single-period Upper Limit Mask Bit
When this bit is high, it masks the single-period upper limit check (or forces pass) for
REF0.
Table 41 - Reference Mask Register (RMR) Bits (continued)
External Read Only Address: 006BH
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
R3FS
2
R3FS
1
R3FS
0
R2FS
2
R2FS
1
R2FS
0
R1FS
2
R1FS
1
R1FS
0
R0FS
2
R0FS
1
R0FS
0
Bit
Name
Description
Reserved. In normal functional mode, these bits are zero.
15 - 12
11 - 9
Unused
R3FS2 - 0 Reference 3 Frequency Status Bits
These bits report detected frequency of REF3.
R3FS2
R3FS1
R3FS0
REF3 Frequency Measurement
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Reserved
Table 42 - Reference Frequency Status Register (RFSR) Bits - Read only
71
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read Only Address: 006BH
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
R3FS
2
R3FS
1
R3FS
0
R2FS
2
R2FS
1
R2FS
0
R1FS
2
R1FS
1
R1FS
0
R0FS
2
R0FS
1
R0FS
0
Bit
Name
Description
8 - 6
R2FS2 - 0 Reference 2 Frequency Status Bits: These bits report detected frequency of REF2.
R2FS2
R2FS1
R2FS0
REF 2 Frequency Measurement
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Reserved
5 - 3
R1FS2 - 0 Reference 1 Frequency Status Bits: These bits report detected frequency of REF1.
R1FS2
R1FS1
R1FS0
REF1 Frequency Measurement
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Reserved
2 - 0
R0FS2 - 0 Reference 0 Frequency Status Bits: These bits report detected frequency of REF0.
R0FS2
R0FS1
R0FS0
REF0 Frequency Measurement
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Reserved
Table 42 - Reference Frequency Status Register (RFSR) Bits - Read only (continued)
72
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 006CH
Reset Value: 0002H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
OJP2
OJP1
OJP0
Bit
Name
Description
15 - 3
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
2 - 0
OJP2 - 0
Output Jitter Performance Bits
These bits are used to control the DPLL output jitter performance with respect to the
noise received through the output pins. The higher value (unsigned) means more
filtering, while zero means filter bypass. The default value of 2H gives the best
performance for most circumstances.
Table 43 - Output Jitter Control Register (OJCR) Bits
External Read/Write Address: 0100H - 011FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
0
STIN[n]
BD2
STIN[n]
BD1
STIN[n]
BD0
STIN[n]
SMP1
STIN[n]
SMP0
STIN[n]
DR3
STIN[n]
DR2
STIN[n]
DR1
STIN[n]
DR0
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
8 - 6
STIN[n]BD2 - 0
Input Stream[n] Bit Delay Bits.
The binary value of these bits refers to the number of bits that the input stream
will be delayed relative to FPi. The maximum value is 7. Zero means no delay.
Input Data Sampling Point Selection Bits
5 - 4
STIN[n]SMP1 - 0
Sampling Point
(2.048 Mbps, 4.096 Mbps, 8.192 Mbps
streams)
Sampling Point
(16.384 Mbps
streams)
STIN[n]SMP1-0
00
01
10
11
3/4 point
1/4 point
2/4 point
4/4 point
2/4 point
4/4 point
Table 44 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits
73
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0100H - 011FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
0
STIN[n]
BD2
STIN[n]
BD1
STIN[n]
BD0
STIN[n]
SMP1
STIN[n]
SMP0
STIN[n]
DR3
STIN[n]
DR2
STIN[n]
DR1
STIN[n]
DR0
Bit
3 - 0
Name
Description
STIN[n]DR3 - 0
Input Data Rate Selection Bits:
STIN[n]DR3-0
Data Rate
0000
0001
0010
0011
0100
Stream Unused
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
Reserved
0101 - 1111
Note: [n] denotes input stream from 0 - 31.
Table 44 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits (continued)
74
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0120H - 013FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
STIN[n]
Q3C2
STIN[n]
Q3C1
STIN[n]
Q3C0
STIN[n]
Q2C2
STIN[n]
Q2C1
STIN[n]
Q2C0
STIN[n]
Q1C2
STIN[n]
Q1C1
STIN[n]
Q1C0
STIN[n]
Q0C2
STIN[n]
Q0C1
STIN[n]
Q0C0
Bit
Name
Description
15 - 12
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
11 - 9
STIN[n]Q3C2 - 0 Quadrant Frame 3 Control Bits
These three bits are used to control STi[n]’s quadrant frame 3, which is defined
as Ch24 to 31, Ch48 to 63, Ch96 to 127 and Ch192 to 255 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q3C
Operation
2-0
0xx
100
101
110
111
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
8 - 6
STIN[n]Q2C2 - 0 Quadrant Frame 2 Control Bits
These three bits are used to control STi[n]’s quadrant frame 2, which is defined
as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps,
4.096 Mbps 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q2C
Operation
2-0
0xx
100
101
110
111
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
Table 45 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits
75
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0120H - 013FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
STIN[n]
Q3C2
STIN[n]
Q3C1
STIN[n]
Q3C0
STIN[n]
Q2C2
STIN[n]
Q2C1
STIN[n]
Q2C0
STIN[n]
Q1C2
STIN[n]
Q1C1
STIN[n]
Q1C0
STIN[n]
Q0C2
STIN[n]
Q0C1
STIN[n]
Q0C0
Bit
5 - 3
Name
Description
STIN[n]Q1C2 - 0 Quadrant Frame 1 Control Bits
These three bits are used to control STi[n]’s quadrant frame 1, which is defined
as Ch8 to 15, Ch16 to 31, Ch32 to 63 and Ch64 to 127 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q1C
Operation
2-0
0xx
100
101
110
111
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
2 - 0
STIN[n]Q0C2 - 0 Quadrant Frame 0 Control Bits
These three bits are used to control STi[n]’s quadrant frame 0, which is defined
as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q0C2-0
Operation
0xx
100
101
110
111
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
Note: [n] denotes input stream from 0 - 31.
Table 45 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits (continued)
76
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0200H - 021FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
STOHZ
[n]A2
STOHZ
[n]A1
STOHZ
[n]A0
STO[n]
FA1
STO[n]
FA0
STO[n]
AD2
STO[n]
AD1
STO[n]
AD0
STO[n]
DR3
STO[n]
DR2
STO[n]
DR1
STO[n]
DR0
Bit
Name
Description
15 - 12
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
STOHZ Additional Advancement Bits
11 - 9
STOHZ[n]A2 - 0
Additional Advancement
(2.048 Mbps, 4.096 Mbps,
8.192 Mbps)
Additional Advancement
(16.384 Mbps streams)
(Valid only for
STio0-15)
STOHZ[n]A2-0
000
001
0 bit
1/4 bit
0 bit
2/4 bit
010
011
2/4 bit
3/4 bit
4/4 bit
Reserved
100
101-111
4/4 bit
Reserved
Output Stream[n] Fractional Advancement Bits
8 - 7
STO[n]FA1 - 0
Advancement
(2.048 Mbps, 4.096 Mbps,
8.192 Mbps streams)
Advancement
(16.384 Mbps streams)
STO[n]FA1-0
00
01
10
11
0
0
2/4
Reserved
1/4 bit
2/4 bit
3/4 bit
6 - 4
3 - 0
STO[n]AD2 - 0
STO[n]DR3 - 0
Output Stream[n] Bit Advancement Selection Bits
The binary value of these bits refers to the number of bits that the output stream
is to be advanced relative to FPo. The maximum value is 7. Zero means no
advancement.
Output Data Rate Selection Bits
Data Rate
STIN[n]DR3 - 0
0000
disabled: STio HiZ
(STOHZ driven high)
0001
0010
0011
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
Reserved
0100
0101 - 1111
Note: [n] denotes output stream from 0 - 31.
Table 46 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits
77
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0300H - 031FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
ST[n]
BRS7
ST[n]
BRS6
ST[n]
BRS5
ST[n]
BRS4
ST[n]
BRS3
ST[n]
BRS2
ST[n]
BRS1
ST[n]
BRS0
Bit
Name
Description
15 - 8
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
7 - 0
ST[n]
Stream[n] BER Receive Start Bits
BRS7 - 0
The binary value of these bits refers to the input channel in which the BER data starts
to be compared.
Note: [n] denotes input stream from 0 - 31.
Table 47 - BER Receiver Start Register [n] (BRSR[n]) Bits
External Read/Write Address: 0320H - 033FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
ST[n]
BL8
ST[n]
BL7
ST[n]
BL6
ST[n]
BL5
ST[n]
BL4
ST[n]
BL3
ST[n]
BL2
ST[n]
BL1
ST[n]
BL0
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
8 - 0
ST[n]
Stream[n] BER Length Bits
The binary value of these bits refers to the number of consecutive channels expected
to receive the BER pattern. The maximum number of BER channels is 32, 64, 128 and
256 for the data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps
respectively. The minimum number of BER channels is 1. If these bits are set to zero,
no BER test will be performed.
BL8 - 0
Note: [n] denotes input stream from 0 - 31.
Table 48 - BER Receiver Length Register [n] (BRLR[n]) Bits
78
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
External Read/Write Address: 0340H - 035FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
ST[n]
ST[n]
SBER
CBER
Bit
Name
Description
15 - 2
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
1
0
ST[n]
Stream[n] Bit Error Rate Counter Clear
When this bit is high, it resets the internal bit error counter and the stream BER
Receiver Error Register to zero.
CBER
ST[n]
Stream[n] Bit Error Rate Test Start
When this bit is high, it enables the BER receiver; starts the bit error rate test. The bit
error test result is kept in the BER Receiver Error (BRER[n]) register. Upon the
completion of the BER test, set this bit to zero. Note that the RBEREB bit must be set
in the IMS Register first.
SBER
Note: [n] denotes input stream from 0 - 31.
Table 49 - BER Receiver Control Register [n] (BRCR[n]) Bits
External Read Address: 0360H - 037FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ST[n]
BC15
ST[n]
BC14
ST[n]
BC13
ST[n]
BC12
ST[n]
BC11
ST[n]
BC10
ST[n]
BC9
ST[n]
BC8
ST[n]
BC7
ST[n]
BC6
ST[n]
BC5
ST[n]
BC4
ST[n]
BC3
ST[n]
BC2
ST[n]
BC1
ST[n]
BC0
Bit
Name
Description
15 - 0
ST[n]
Stream[n] BER Count Bits (Read Only)
BC15 - 0
The binary value of these bits refers to the bit error counts. When it reaches its maxi-
mum value of 0xFFFF, the value will be held and will not rollover.
Note: [n] denotes input stream from 0 - 31.
Table 50 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only
79
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
25.0 Memory
25.1 Memory Address Mappings
When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the
Control Register determine the access to the data or connection memory (CM_L or CM_H).
MSB
Stream Address
(St0 - 31)
Channel Address
(Ch0 - 255)
(Note 1)
A12
A11
A10
A9
A8
Stream [n]
A7
A6
A5
A4
A3
A2
A1
A0
Channel [n]
A13
1
1
1
1
1
1
1
1
1
.
0
0
0
0
0
0
0
0
0
.
0
0
0
0
0
0
0
0
1
.
0
0
0
0
1
1
1
1
0
.
0
0
1
1
0
0
1
1
0
.
0
1
0
1
0
1
0
1
0
.
Stream 0
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Ch 0
Stream 1
Ch 1
Stream 2
.
Stream 3
.
.
.
.
.
.
.
.
.
Stream 4
0
0
0
0
.
0
0
0
0
.
0
0
1
1
.
1
1
0
0
1
1
0
0
.
1
1
0
0
.
1
1
0
0
0
1
0
1
.
Ch 30
Stream 5
Ch 31 (Note 2)
Stream 6
Ch 32
Stream 7
Ch 33
Stream 8
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
.
0
0
.
1
1
.
1
1
.
1
1
.
1
1
.
1
1
.
0
1
.
Ch 62
.
.
.
.
.
.
.
Ch 63 (Note 3)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
.
0
0
.
1
1
.
1
1
.
1
1
.
0
1
.
Stream 14
.
.
.
.
.
.
.
.
.
Stream 15
.
.
.
.
.
.
.
.
.
.
0
0
.
1
1
.
1
1
.
1
1
.
1
1
.
1
1
.
1
1
.
0
1
.
Ch126
.
.
.
.
.
.
.
Ch 127 (Note 4)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
0
1
Stream 30
Stream 31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Ch 254
Ch 255 (Note 5)
Notes:
1. A13 must be high for access to data and connection memory positions. A13 must be low to access internal registers.
2. Channels 0 to 31 are used when serial stream is at 2.048 Mbps.
3. Channels 0 to 63 are used when serial stream is at 4.096 Mbps.
4. Channels 0 to 127 are used when serial stream is at 8.192 Mbps.
5. Channels 0 to 255 are used when serial stream is at 16.384 Mbps.
Table 51 - Address Map for Memory Locations (A13 = 1)
25.2 Connection Memory Low (CM_L) Bit Assignment
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal
channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in
Table 52 on page 80.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UA
EN
V/C
SSA
4
SSA
3
SSA
2
SSA
1
SSA
0
SCA
7
SCA
6
SCA
5
SCA
4
SCA
3
SCA
2
SCA
1
SCA
0
CMM
=0
Bit
Name
Description
15
UAEN
Conversion between µ-law and A-law Enable
When this bit is low, normal switch without µ-law/A-law conversion. Connec-
tion memory high will be ignored.
When this bit is high, switch with µ-law/A-law conversion, and connection
memory high controls the conversion method.
Table 52 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
80
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UA
EN
V/C
SSA
4
SSA
3
SSA
2
SSA
1
SSA
0
SCA
7
SCA
6
SCA
5
SCA
4
SCA
3
SCA
2
SCA
1
SCA
0
CMM
=0
Bit
Name
Description
14
V/C
Variable/Constant Delay Control
When this bit is low, the output data for this channel will be taken from con-
stant delay memory.
When this bit is set to high, the output data for this channel will be taken from
variable delay memory. Note that VAREN must be set in Control Register
first.
13 - 9
8 - 1
0
SSA4 - 0 Source Stream Address
The binary value of these 5 bits represents the input stream number.
SCA7 - 0 Source Channel Address
The binary value of these 8 bits represents the input channel number.
CMM = 0 Connection Memory Mode = 0
If this is low, the connection memory is in the normal switching mode. Bit13 -
1 are the source stream number and channel number.
Note: For proper µ-law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 52 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits
PCC0 and PCC1 from connection memory are used to select the per-channel tristate, message or BER test mode
as shown in Table 53 on page 81.
15
14
0
13
0
12
0
11
0
10
9
8
7
6
5
4
3
2
1
0
UA
EN
MSG
7
MSG
6
MSG
5
MSG
4
MSG
3
MSG
2
MSG
1
MSG
0
PCC
1
PCC
0
CMM
=1
Bit
Name
Description
15
UAEN
Conversion between µ-law and A-law Enable (Message mode only)
When this bit is low, message mode has no µ-law/A-law conversion. Connec-
tion memory high will be ignored.
When this bit is high, message mode has µ-law/A-law conversion, and con-
nection memory high controls the conversion method.
14 - 11
10 - 3
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
MSG7 - 0 Message Data Bits
8-bit data for the message mode. Not used in the per-channel tristate and
BER test modes.
Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
81
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
15
14
0
13
0
12
0
11
0
10
9
8
7
6
5
4
3
2
1
0
UA
EN
MSG
7
MSG
6
MSG
5
MSG
4
MSG
3
MSG
2
MSG
1
MSG
0
PCC
1
PCC
0
CMM
=1
Bit
2 - 1
Name
Description
PCC1 - 0
Per-Channel Control Bits
These two bits control the corresponding entry’s value on the STio stream.
PC
C1
PC
C0
Channel Output Mode
0
0
1
1
0
1
0
1
Per Channel Tristate
Message Mode
BER Test Mode
Reserved
0
CMM = 1
Connection Memory Mode = 1
If this is high, the connection memory is in the per-channel control mode
which is per-channel tristate, per-channel message mode or per-channel BER
mode.
Note: For proper µ-law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
82
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
25.3 Connection Memory High (CM_H) Bit Assignment
Connection memory high provides the detailed information required for µ-law and A-law conversion. ICL and OCL
bits describe the Input Coding Law and the Output Coding Law, respectively. They are used to select the expected
PCM coding laws for the connection, on the TDM inputs, and on the TDM outputs. The V/D bit is used to select the
class of coding law. If the V/D bit is cleared (to select a voice connection), the ICL and OCL bits select between
A-law and µ-law specifications related to G.711 voice coding. If the V/D bit is set (to select a data connection), the
ICL and OCL bits select between various bit inverting protocols. These coding laws are illustrated in the following
table. If the ICL is different than the OCL, all data bytes passing through the switch on that particular connection are
translated between the indicated laws. If the ICL and the OCL are the same, no coding law translation is performed.
The ICL, the OCL bits and V/D bit only have an effect on PCM code translations for constant delay connections,
variable delay connections and per-channel message mode.
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
V/D
ICL
1
ICL
0
OCL
1
OCL
0
Bit
Name
Description
15 - 5
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
4
V/D
Voice/Data Control
When this bit is low, the corresponding channel is for voice.
When this bit is high, the corresponding channel is for data.
3 - 2
ICL1 - 0
Input Coding Law.
Input Coding Law
ICL1-0
For Voice (V/D bit = 0)
For Data (V/D bit = 1)
00
01
10
11
CCITT.ITU A-law
CCITT.ITU µ-law
A-law w/o ABI
No code
ABI
Inverted ABI
All Bits Inverted
µ-law w/o Magnitude
Inversion
1 - 0
OCL1 - 0 Output Coding Law
Output Coding Law
OCL1-0
For Voice (V/D bit = 0)
For Data (V/D bit = 1)
00
01
10
11
CCITT.ITU A-law
CCITT.ITU µ-law
A-law w/o ABI
No code
ABI
Inverted ABI
All Bits Inverted
µ-law w/o Magnitude
Inversion
Note 1: For proper µ-law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high.
Note 2: Refer to G.711 standard for detail information of different laws.
Table 54 - Connection Memory High (CM_H) Bit Assignment
83
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
26.0 Applications
This section contains application-specific details for clock and crystal operation and power supply decoupling.
26.1 OSCi Master Clock Requirement
The device requires a 20 MHz master clock source at the OSCi pin when operating in Master mode or in Divided
Slave with OSC mode. The clock source may be either an external clock oscillator connected to the OSCi pin, or an
external crystal connected between the OSCi and OSCo pins. If an external clock source is present, OSC_EN must
be tied high.
Note that using a crystal is only suitable for wider tolerance applications (i.e., ±100 ppm). For stratum 4E
applications a clock oscillator with a tolerance of ±32 ppm should be used. See Application Note ZLAN-68 for a list
of Oscillators and Crystals that can be used with Zarlink PLL’s and Digital Switches with embedded PLL’s.
26.1.1 External Crystal Oscillator
When an external crystal oscillator is used, a complete oscillator circuit made up of a crystal, resistor and capacitors
is shown in Figure 21 on page 84. XC is a buffered version of the 20 MHz input clock connected to the internal
circuitry.
OSCi
2 K DX
20 MHz
1 MΩ
25 pF
25 pF
OSCo
XC
Figure 21 - Crystal Oscillator Circuit
The accuracy of a crystal oscillator circuit depends on the crystal tolerance as well as the load capacitance
tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load
capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and
stray capacitances have a major effect on the accuracy of the oscillator frequency. The trimmer capacitor shown in
Figure 21 on page 84 may be used to compensate for capacitive effects.
The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler
oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal
accuracy only affects the output clock accuracy in the freerun or the holdover mode. The crystal specification is as
follows:
Frequency
20 MHz
Tolerance
As required
Fundamental
Parallel
Oscillation Mode
Resonance Mode
Load Capacitance
20 pF - 32 pF
84
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
Maximum Series Resistance
Approximate Drive Level
35 Ω
1 mW
26.1.2 External Clock Oscillator
When an external clock oscillator is used, numerous parameters must be considered. They include absolute
frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
The output clock should be connected directly (not AC coupled) to the OSCi input of the device, and the OSCo
output should be left open as shown in Figure 22 on page 85. XC is a buffered version of the 20 MHz input clock
connected to the internal circuitry.
+3.3 V
OSCi
2 K DX
+3.3 V
20 MHz OUT
GND
0.1 uF
OSCo
XC
No Connection
Figure 22 - Clock Oscillator Circuit
For applications requiring ±32 ppm clock accuracy, the following requirements should be met:
Frequency
20.000 MHz
±32 ppm
Tolerance
Rise and Fall Time
Duty Cycle
10 ns
40% to 60%
85
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
27.0 DC Parameters
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
1
2
3
4
5
6
7
I/O Supply Voltage
Core Supply Voltage
Input Voltage
Input Voltage (5 V-tolerant inputs)
Continuous Current at Digital Outputs
Package Power Dissipation
Storage Temperature
VDD_IO
VDD_CORE
VI_3V
VI_5V
Io
-0.5
-0.5
-0.5
-0.5
5.0
2.5
VDD + 0.5
7.0
V
V
V
V
mA
W
°C
15
1.5
+125
PD
TS
- 55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Operating Temperature
Positive Supply
Positive Supply
Input Voltage
Sym.
Min.
Typ.‡
Max.
Units
1
2
3
4
5
TOP
VDD_IO
VDD_CORE
VI
-40
3.0
1.71
0
25
3.3
1.8
3.3
5.0
+85
3.6
1.89
VDD_IO
5.5
°C
V
V
V
V
Input Voltage on 5 V-Tolerant Inputs
VI_5V
0
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
2
3
4
5
Supply Current - VDD_CORE
Supply Current - VDD_IO
Input High Voltage
IDD_CORE
IDD_IO
VIH
165
75
mA
mA CL = 30 pF
V
V
µA
µA
2.0
Input Low Voltage
VIL
0.8
5
5
Input Leakage (input pins)
IIL
0≤<VIN≤VDD_IO
Input Leakage (bi-directional pins)
IBL
See Note 1
6
7
8
9
Weak Pullup Current
Weak Pulldown Current
Input Pin Capacitance
Output High Voltage
IPU
IPD
CI
VOH
VOL
IOZ
CO
-33
33
3
µA
µA
pF
V
V
µA
pF
Input at 0 V
Input at VDD_IO
2.4
IOH = 10 mA
IOL = 10 mA
0 < V < VDD
10 Output Low Voltage
11 Output High Impedance Leakage
12 Output Pin Capacitance
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
0.4
5
10
5
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
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Data Sheet
28.0 AC Parameters
AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels
Characteristics
CMOS Threshold
Rise/Fall Threshold Voltage High
Rise/Fall Threshold Voltage Low
Sym.
Level
Units
Conditions
1
2
3
VCT
VHM
VLM
0.5 VDD_IO
0.7 VDD_IO
0.3 VDD_IO
V
V
V
† Characteristics are over recommended operating conditions unless otherwise stated.
Timing Reference Points
VHM
VCT
VLM
ALL SIGNALS
Figure 23 - Timing Parameter Measurement Voltage Levels
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode - Read Access
Characteristics
CS de-asserted time
Sym.
Min.
Typ.
Max.
Units
Test Conditions2
1
2
3
4
5
6
7
8
9
tCSD
tDSD
tCSS
tRWS
tAS
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS de-asserted time
CS setup to DS falling
R/W setup to DS falling
Address setup to DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup to DTA Low
10
5
0
0
0
tCSH
tRWH
tAH
tDS
8
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
10 Data hold after DS rising
tDH
7
11 Acknowledgement delay time.
From DS low to DTA low:
Registers
tAKD
Memory
CL = 50 pF
CL = 50 pF
75
185
ns
ns
12 Acknowledgement hold time.
From DS high to DTA high
13 DTA drive high to HiZ
tAKH
tAKZ
4
12
ns
CL = 50 pF, RL = 1 K
(Note 1)
8
ns
Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to
discharge CL.
Note 2: A delay of 500 µs to 2 ms (see Section 18.2 on page 42) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
tCSS
tCSH
CS
VCT
tDSD
VCT
VCT
DS
t
RWS
tRWH
R/W
tAS
tAH
tDH
VALID READ DATA
VCT
VALID ADDRESS
A0-A13
D0-D15
VCT
tDS
tAKZ
VCT
DTA
tAKH
tAKD
Figure 24 - Motorola Non-Multiplexed Bus Timing - Read Access
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode - Write Access
Characteristics
CS de-asserted time
DS de-asserted time
CS setup to DS falling
R/W setup to DS falling
Address setup to DS falling
Data setup to DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Sym.
Min.
Typ.
Max.
Units
Test Conditions2
1
2
3
4
5
6
7
8
9
tCSD
tDSD
tCSS
tRWS
tAS
15
15
0
10
5
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDS
CL = 50 pF
tCSH
tRWH
tAH
10 Data hold from DS rising
tDH
5
CL = 50 pF, RL = 1 K
(Note 1)
11 Acknowledgement delay time.
From DS low to DTA low:
Registers
tAKD
Memory
CL = 50 pF
CL = 50 pF
55
150
ns
ns
12 Acknowledgement hold time.
From DS high to DTA high
13 DTA drive high to HiZ
tAKH
tAKZ
4
12
ns
CL = 50 pF, RL = 1 K
(Note 1)
8
ns
Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to
discharge CL.
Note 2: A delay of 500 µs to 2 ms (see Section 18.2 on page 42) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
tCSS
tCSH
CS
VCT
tDSD
VCT
VCT
DS
tRWH
tRWS
R/W
tAH
tAS
VCT
VALID ADDRESS
A0-A13
D0-D15
tDS
tDH
VCT
VALID WRITE DATA
tAKZ
VCT
DTA
tAKH
tAKD
Figure 25 - Motorola Non-Multiplexed Bus Timing - Write Access
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics† - Intel Non-Multiplexed Bus Mode - Read Access
Characteristics
CS de-asserted time
Sym.
Min.
Typ.
Max.
Units
Test Conditions2
1
2
3
4
5
6
7
8
9
tCSD
tRS
tWS
tAS
15
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD setup to CS falling
WR setup to CS falling
Address setup to CS falling
RD hold after CS rising
WR hold after CS rising
Address hold after CS rising
Data setup to RDY high
Data hold after CS rising
tRH
tWH
tAH
tDS
tDH
0
0
0
8
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
7
10 Acknowledgement delay time.
From CS low to RDY high:
Registers
tAKD
Memory
CL = 50 pF
CL = 50 pF
75
185
ns
ns
11 Acknowledgement hold time.
From CS high to RDY low
12 RDY drive low to HiZ
tAKH
tAKZ
4
12
ns
CL = 50 pF, RL = 1 K
(Note 1)
8
ns
Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to
discharge CL.
Note 2: A delay of 500 µs to 2 ms (see Section 18.2 on page 42) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
VCT
CS
RD
tRH
tRS
VCT
tWH
tWS
VCT
WR
tAH
tAS
VCT
VALID ADDRESS
A0-A13
D0-D15
tDH
VALID READ DATA
VCT
tDS
tAKZ
VCT
RDY
tAKD
tAKH
Figure 26 - Intel Non-Multiplexed Bus Timing - Read Access
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
AC Electrical Characteristics† - Intel Non-Multiplexed Bus Mode - Write Access
Characteristics
CS de-asserted time
Sym.
Min.
Typ.
Max.
Units
Test Conditions2
1
2
3
4
5
6
7
8
9
tCSD
tWS
tRS
tAS
15
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR setup to CS falling
RD setup to CS falling
Address setup to CS falling
Data setup to CS falling
WR hold after CS rising
RD hold after CS rising
Address hold after CS rising
Data hold after CS rising
tDS
tWH
tRH
tAH
tDH
0
0
0
10
5
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
10 Acknowledgement delay time.
From CS low to RDY high:
Registers
tAKD
Memory
CL = 50 pF
CL = 50 pF
55
150
ns
ns
11 Acknowledgement hold time.
From CS high to RDY low
12 RDY drive low to HiZ
tAKH
tAKZ
4
12
ns
CL = 50 pF, RL = 1 K
(Note 1)
8
ns
Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to
discharge CL.
Note 2: A delay of 500 µs to 2 ms (Section 18.2 on page 42) must be applied before the first microprocessor access is performed
after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
VCT
CS
tWH
tWS
VCT
WR
tRH
tRS
VCT
RD
tAH
tAS
VCT
VALID ADDRESS
A0-A13
D0-D15
tDH
tDS
VCT
VALID WRITE DATA
tAKZ
VCT
RDY
tAKD
tAKH
Figure 27 - Intel Non-Multiplexed Bus Timing - Write Access
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics† - JTAG Test Port Timing
Characteristic
TCK Clock Period
TCK Clock Pulse Width High
TCK Clock Pulse Width Low
TMS Set-up Time
Sym.
Min.
Typ. Max.
Units
Notes
1
2
3
4
5
6
7
8
9
tTCKP
tTCKH
tTCKL
tTMSS
tTMSH
tTDIS
100
20
20
10
10
20
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
TMS Hold Time
TDi Input Set-up Time
TDi Input Hold Time
TDo Output Delay
tTDIH
tTDOD
30
CL = 30 pF
TRST pulse width
tTRSTW
200
† Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL
tTCKH
tTCKP
TCK
TMS
tTMSH
tTMSS
tTDIS
tTDIH
TDi
tTDOD
TDo
tTRSTW
TRST
Figure 28 - JTAG Test Port Timing Diagram
AC Electrical Characteristics† - OSCi 20 MHz Input Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes‡
Stratum 4E
1
Input frequency accuracy
-32
-100
32
100
ppm
ppm
Relaxed Stratum 4E
2
3
Duty cycle
Input rise or fall time
40
60
3
%
ns
1
14
tIR, IF
t
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ See “Performance Characteristics Notes” on page 112.
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
AC Electrical Characteristics† - FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz)
Characteristic
FPi Input Frame Pulse Width
FPi Input Frame Pulse Setup Time
FPi Input Frame Pulse Hold Time
CKi Input Clock Period
CKi Input Clock High Time
CKi Input Clock Low Time
CKi Input Clock Rise/Fall Time
CKi Input Clock Cycle to Cycle Variation
Sym.
Min. Typ.‡ Max. Units Notes
1
2
3
4
5
6
7
8
tFPIW
tFPIS
tFPIH
tCKIP
tCKIH
40
20
20
55
27
27
61
115
ns
ns
ns
ns
ns
ns
ns
ns
61
67
34
34
3
tCKIL
trCKi, tfCKi
tCVC
0
20
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPi and CKi Timing when CKIN1-0 bits = 01 (8.192 MHz)
Characteristic
Sym.
Min. Typ.‡ Max. Units Notes
1
2
3
4
5
6
7
8
FPi Input Frame Pulse Width
tFPIW
tFPIS
tFPIH
tCKIP
tCKIH
90
45
45
110
55
55
122
220
ns
ns
ns
ns
ns
ns
ns
ns
FPi Input Frame Pulse Setup Time
FPi Input Frame Pulse Hold Time
CKi Input Clock Period
CKi Input Clock High Time
CKi Input Clock Low Time
122
135
69
69
3
tCKIL
trCKi, tfCKi
tCVC
CKi Input Clock Rise/Fall Time
CKi Input Clock Cycle to Cycle Variation
0
20
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPi and CKi Timing when CKIN1-0 bits = 10 (4.096 MHz)
Characteristic
FPi Input Frame Pulse Width
FPi Input Frame Pulse Setup Time
FPi Input Frame Pulse Hold Time
CKi Input Clock Period
CKi Input Clock High Time
CKi Input Clock Low Time
CKi Input Clock Rise/Fall Time
CKi Input Clock Cycle to Cycle Variation
Sym.
Min. Typ.‡ Max. Units Notes
1
2
3
4
5
6
7
8
tFPIW
tFPIS
tFPIH
tCKIP
tCKIH
90
244
420
ns
ns
ns
ns
ns
ns
ns
ns
110
110
220
110
110
244
270
135
135
3
tCKIL
trCKi, tfCKi
tCVC
0
20
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
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Data Sheet
tFPIW
FPi
CKi
tFPIS
tFPIH
tCKIP
tCKIH
tCKIL
trCKI
tfCKI
Input Frame Boundary
Figure 29 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS)
tFPIW
FPi
tFPIS
tFPIH
tCKIP
tCKIH
tCKIL
CKi
trCKI
tfCKI
Input Frame Boundary
Figure 30 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus)
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics† - ST-BUS/GCI-Bus Input Timing
Characteristic
STi Setup Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
tSIS2
tSIS4
tSIS8
tSIS16
5
5
5
5
ns
ns
ns
ns
2
STi Hold Time
tSIH2
tSIH4
tSIH8
tSIH16
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
8
8
8
8
ns
ns
ns
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
FPi
CKi
(16.384 MHz)
FPi
CKi
(8.192 MHz)
FPi
CKi
(4.096 MHz)
tSIS2
tSIH2
STi0 - 31
Bit0
Bit6
Ch0
Bit7
Ch0
tSIS4
tSIH4
VCT
Ch31
2.048 Mbps
STi0 - 31
Bit0
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
VCT
Ch63
4.096 Mbps
tSIS8
tSIH8
STi0 - 31
Bit1
Ch127
Bit0
Ch127
Bit7
Ch0
Bit6
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
VCT
Ch0
8.192 Mbps
Input Frame Boundary
Figure 31 - ST-BUS Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps
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Zarlink Semiconductor Inc.
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Data Sheet
FPi
CKi
(16.384 MHz)
tSIS16
tSIH16
STi0 - 31
Bit1
Bit0
Bit7
Ch0
Bit6
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
VCT
Ch255
Ch255
Ch0
16.384 Mbps
Input Frame Boundary
Figure 32 - ST-BUS Input Timing Diagram when Operated at 16 Mbps
FPi
CKi
(16.384 MHz)
FPi
CKi
(8.192 MHz)
FPi
CKi
(4.096 MHz)
tSIS2
tSIH2
STi0 - 31
Bit7
Bit1
Ch0
Bit0
Ch0
tSIS4
tSIH4
VCT
Ch31
2.048 Mbps
STi0 - 31
Bit7
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
VCT
Ch63
4.096 Mbps
tSIS8
tSIH8
STi0 - 31
Bit7
Ch127
Bit6
Ch127
Bit0
Ch0
Bit1
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
VCT
Ch0
8.192 Mbps
Input Frame Boundary
Figure 33 - GCI-Bus Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
FPi
CKi
(16.384 MHz)
tSIS16
tSIH16
STi0 - 31
Bit6
Bit7
Bit0
Ch0
Bit1
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
VCT
Ch255
Ch255
Ch0
16.384 Mbps
Input Frame Boundary
Figure 34 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics† - ST-BUS/GCI-Bus Output Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
CL = 30 pF
Master Mode
1
STio Delay - Active to Active
@2.048 Mbps
@4.096 Mbps
@8.192 Mbps
@16.384 Mbps
tSOD2
tSOD4
tSOD8
tSOD16
1
1
1
1
8
8
8
8
ns
ns
ns
ns
@2.048 Mbps
@4.096 Mbps
@8.192 Mbps
@16.384 Mbps
tSOD2
tSOD4
tSOD8
tSOD16
0
0
0
0
6
6
6
6
ns
ns
ns
ns
Multiplied Slave Mode
Divided Slave Mode
@2.048 Mbps
@4.096 Mbps
@8.192 Mbps
@16.384 Mbps
tSOD2
tSOD4
tSOD8
tSOD16
-6
-6
-6
-6
0
0
0
0
ns
ns
ns
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
FPo0
CKo0
(4.096 MHz)
tSOD2
STio0 - 31
Bit0
Bit7
Ch0
Bit6
Ch0
VCT
Ch31
2.048 Mbps
tSOD4
STio0 - 31
Bit0
Ch63
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
VCT
4.096 Mbps
tSOD8
STio0 - 31
Bit0
Ch127
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
VCT
8.192 Mbps
tSOD16
STio0 - 31
Bit2 Bit1
Bit0 Bit7
Bit6 Bit5
Bit4 Bit3
Bit2 Bit1 Bit0 Bit7
Bit6 Bit5 Bit4
Bit3 Bit2
Bit1
VCT
Ch255Ch255 Ch255 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch1 Ch1 Ch1 Ch1 Ch1 Ch1 Ch1
16.384 Mbps
Output Frame Boundary
Figure 35 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps
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Zarlink Semiconductor Inc.
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Data Sheet
FPo0
CKo0
(4.096 MHz)
tSOD2
STio0 - 31
Bit7
Bit0
Ch0
Bit1
Ch0
VCT
Ch31
2.048 Mbps
tSOD4
STio0 - 31
Bit7
Ch63
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
VCT
4.096 Mbps
tSOD8
STio0 - 31
Bit7
Ch127
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
VCT
8.192 Mbps
tSOD16
STio0 - 31
Bit5 Bit6
Bit7 Bit0
Bit1 Bit2
Bit3 Bit4
Bit5 Bit6 Bit7 Bit0
Bit1 Bit2 Bit3
Bit4 Bit5
Bit6
VCT
Ch255Ch255 Ch255 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch1 Ch1 Ch1 Ch1 Ch1 Ch1 Ch1
16.384 Mbps
Output Frame Boundary
Figure 36 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics† - ST-BUS/GCI-Bus Output Tristate Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions*
1
2
3
STio Delay - Active to High-Z
tDZ
-2
-3
-8
-2
-3
-8
8
7
0
8
7
0
ns
ns
ns
ns
ns
ns
Master Mode
Multiplied Slave Mode
Divided Slave Mode
STio Delay - High-Z to Active
tZD
Master Mode
Multiplied Slave Mode
Divided Slave Mode
Output Drive Enable (ODE) Delay
- High-Z to Active
tZD_ODE
Master or
77
ns
Multiplied Slave Mode
CKi @ 4.096 MHz
CKi @ 8.192 MHz
CKi @ 16.384 MHz
260
138
77
ns
ns
ns
Divided Slave Mode
4
Output Drive Enable (ODE) Delay
- Active to High-Z
tDZ_ODE
Master or
77
ns
Multiplied Slave Mode
CKi @ 4.096 MHz
CKi @ 8.192 MHz
CKi @ 16.384 MHz
260
138
77
ns
ns
ns
Divided Slave Mode
† Characteristics are over recommended operating conditions unless otherwise stated.
* Test condition is RL = 1 k, CL = 30 pF; high impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel
the time taken to discharge CL.
VCT
FPo0
CKo0
VCT
tDZ
VCT
Tristate
Valid Data
STio
STio
tZD
VCT
Tristate
Valid Data
Figure 37 - Serial Output and External Control
VCT
ODE
STio
tZD_ODE
HiZ
tDZ_ODE
Valid Data
VCT
HiZ
Figure 38 - Output Drive Enable (ODE)
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics† - Slave Mode Input/Output Frame Boundary Alignment
Characteristic
Sym.
Min. Typ.
Max.
Units
Notes
t
1
2
Input and Output Frame Offset in
Divided Slave Mode
5
13
ns
FBOS
t
Input and Output Frame Offset in
2
10
ns
Input reference jitter is
equal to zero.
FBOS
Multiplied Slave Mode
† Characteristics are over recommended operating conditions unless otherwise stated.
FPi
CKi
(16.384 MHz)
FPi
CKi
(8.192 MHz)
FPi
CKi
(4.096 MHz)
Input Frame Boundary
t
FBOS
Output Frame Boundary
FPo0
CKo0
(4.096 MHz)
Figure 39 - Input and Output Frame Boundary Offset
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Zarlink Semiconductor Inc.
ZL50019
Data Sheet
tFPW0
VCT
FPo0/FPo3
CKo0/CKo3
tFODF0
tFODR0
tCKP0
tCKH0
tCKL0
VCT
trCK0
tfCK0
Output Frame Boundary
Figure 40 - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing Diagram
AC Electrical Characteristics† - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Master Mode,
Divided Slave Mode, or Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
FPo0 Output Pulse Width
FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary
tFPW0
tFODF0
239
117
244
249
127
ns
ns
CL = 30 pF
3
FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge
tFODR0
117
127
ns
4
5
6
7
CKo0 Output Clock Period
CKo0 Output High Time
CKo0 Output Low Time
CKo0 Output Rise/Fall Time
tCKP0
tCKH0
tCKL0
239
117
117
244
249
127
127
5
ns
ns
ns
ns
CL = 30 pF
t
rCK0, tfCK0
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Multiplied Slave
Mode with more than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo0 Output Pulse Width
FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW0
tFODF0
218
117
244
270
127
ns
ns
CL = 30 pF
3
FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge
tFODR0
97
146
ns
4
5
6
7
CKo0 Output Clock Period
CKo0 Output High Time
CKo0 Output Low Time
CKo0 Output Rise/Fall Time
tCKP0
tCKH0
tCKL0
218
117
97
244
270
127
146
5
ns
ns
ns
ns
CL = 30 pF
t
rCK0, tfCK0
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
102
Zarlink Semiconductor Inc.
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Data Sheet
tFPW1
VCT
FPo1/FPo3
CKo1/CKo3
tFODF1
tFODR1
tCKP1
tCKH1
tCKL1
VCT
trCK1
tfCK1
Output Frame Boundary
Figure 41 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram
AC Electrical Characteristics† - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Master Mode,
Divided Slave Mode, or Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
FPo1 Output Pulse Width
FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
tFPW1
tFODF1
117
56
122
127
66
ns
ns
CL = 30 pF
3
FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR1
56
66
ns
4
5
6
7
CKo1 Output Clock Period
CKo1 Output High Time
CKo1 Output Low Time
CKo1 Output Rise/Fall Time
tCKP1
tCKH1
tCKL1
117
56
56
122
127
66
66
5
ns
ns
ns
ns
CL = 30 pF
t
rCK1, tfCK1
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Multiplied Slave
Mode with more than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo1 Output Pulse Width
FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW1
tFODF1
106
56
122
127
66
ns
ns
CL = 30 pF
3
FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR1
46
66
ns
4
5
6
7
CKo1 Output Clock Period
CKo1 Output High Time
CKo1 Output Low Time
CKo1 Output Rise/Fall Time
tCKP1
tCKH1
tCKL1
106
46
46
122
148
87
66
5
ns
ns
ns
ns
CL = 30 pF
t
rCK1, tfCK1
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
103
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
tFPW2
VCT
FPo2/FPo3
CKo2/CKo3
tFODF2
tFODR2
tCKP2
tCKH2
tCKL2
VCT
trCK2
tfCK2
Output Frame Boundary
Figure 42 - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing Diagram
AC Electrical Characteristics† - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing (Master Mode,
Divided Slave Mode, or Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
FPo2 Output Pulse Width
FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary
tFPW2
tFODF2
56
25
61
66
36
ns
ns
CL = 30 pF
3
FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge
tFODR2
25
36
ns
4
5
6
7
CKo2 Output Clock Period
CKo2 Output High Time
CKo2 Output Low Time
CKo2 Output Rise/Fall Time
tCKP2
tCKH2
tCKL2
56
25
25
61
66
36
36
5
ns
ns
ns
ns
CL = 30 pF
t
rCK2, tfCK2
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing (Multiplied Slave
Mode with more than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo2 Output Pulse Width
FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW2
tFODF2
56
25
61
66
36
ns
ns
CL = 30 pF
3
FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge
tFODR2
25
36
ns
4
5
6
7
CKo2 Output Clock Period
CKo2 Output High Time
CKo2 Output Low Time
CKo2 Output Rise/Fall Time
tCKP2
tCKH2
tCKL2
47
17
17
61
76
43
43
5
ns
ns
ns
ns
CL = 30 pF
t
rCK2, tfCK2
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
104
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Data Sheet
tFPW3
VCT
FPo3
CKo3
tFODF3
tFODR3
tCKP3
tCKH3
tCKL3
VCT
trCK3
tfCK3
Output Frame Boundary
Figure 43 - FPo3 and CKo3 (32.768 MHz) Timing Diagram
AC Electrical Characteristics† - FPo3 and CKo3 (32.768 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
FPo3 Output Pulse Width
FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
tFPW3
tFODF3
27
10
30.5
34
18
ns
ns
CL = 30 pF
3
FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
tFODR3
12
21
ns
4
5
6
7
CKo3 Output Clock Period
CKo3 Output High Time
CKo3 Output Low Time
CKo3 Output Rise/Fall Time
tCKP3
tCKH3
tCKL3
27
12
12
30.5
34
19
19
5
ns
ns
ns
ns
CL = 30 pF
t
rCK3, tfCK3
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo3 and CKo3 (32.768 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi
Characteristic
FPo3 Output Pulse Width
FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW3
tFODF3
27
12
30.5
34
19
ns
ns
CL = 30 pF
3
FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
tFODR3
12
19
ns
4
5
6
7
CKo3 Output Clock Period
CKo3 Output High Time
CKo3 Output Low Time
CKo3 Output Rise/Fall Time
tCKP3
tCKH3
tCKL3
17
5
12
30.5
44
29
18
5
ns
ns
ns
ns
CL = 30 pF
t
rCK3, tfCK3
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
105
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
FPo0
CKo4
VCT
tCKP4
tCKH4
tCKL4
VCT
trCK4
tfCK4
Output Frame Boundary
Figure 44 - FPo4 and CKo4 Timing Diagram (1.544/2.048 MHz)
AC Electrical Characteristics† - CKo4 (1.544 MHz) Timing (Only when DPLL is active)
Characteristic
CKo4 Output Clock Period
CKo4 Output High Time
CKo4 Output Low Time
CKo4 Output Rise/Fall Time
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
3
4
tCKP4
tCKH4
tCKL4
645
320
320
648
324
324
650
327
327
5
ns
ns
ns
ns
CL = 30 pF
trCK4, tfCK4
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - CKo4 (2.048 MHz) Timing (Only when DPLL is active)
Characteristic
CKo4 Output Clock Period
CKo4 Output High Time
CKo4 Output Low Time
CKo4 Output Rise/Fall Time
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
3
4
tCKP4
tCKH4
tCKL4
485
241
241
488
244
244
492
247
247
5
ns
ns
ns
ns
CL = 30 pF
t
rCK4, tfCK4
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tFPW5
FPo5
VCT
(shares output pin
with FPo_OFF2)
tFODF5
tFODR5
tCKP5
tCKH5
tCKL5
VCT
CKo5
trCK5
tfCK5
Output Frame Boundary
Figure 45 - CKo5 Timing Diagram (19.44 MHz)
106
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
AC Electrical Characteristics† - CKo5 (19.44 MHz) Timing (Only when DPLL is active)
Characteristic
FPo5 Output Pulse Width
FPo5 Output Delay from the FPo5 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW5
tFODF5
49
22
51
25
55
28
ns
ns
CL = 30 pF
3
FPo5 Output Delay from the output frame
boundary to the FPo5 rising edge
tFODR5
21
25
32
ns
4
5
6
7
CKo5 Output Clock Period
CKo5 Output High Time
CKo5 Output Low Time
CKo5 Output Rise/Fall Time
tCKP5
tCKH5
tCKL5
50
23
24
51
25
25
53
27
28
5
ns
ns
ns
ns
t
rCK5, tfCK5
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
107
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
AC Electrical Characteristics† - REF0-3 Reference Input to CKo Output Timing
Characteristic
Sym.
Min.
Max.
Units
Notes‡
1
2
3
Minimum Input Pulse Width High or Low
Input Rise or Fall Time
tRPMIN
tIR, (or tIF)
tRD
16
ns
ns
1,2,3,14
5
REF input to CKo0 output delay (no input jitter)
REF @ 8 kHz, 2.048, 4.096, 8.192, 16.384 MHz
REF @ 1.544 MHz
-7
6
0
ns
ns
ns
15
-2
REF @ 19.44 MHz
-10
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ See “Performance Characteristics Notes” on page 112.
t
RPMIN
t
RD
REF0-3
FPo[n]
CKo[n]
V
CT
tIR
V
CT
V
CT
Figure 46 - REF0 - 3 Reference Input/Output Timing
108
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
AC Electrical Characteristics† - Master Mode Output Timing
Characteristic
Sym.
Min.
Max.
Units Notes‡
1
2
3
CKo0 to CKo1 (8.192 MHz) delay
CKo0 to CKo2 (16.384 MHz) delay
tC1D
tC2D
tC3D
-1
-1
-4
2
3
0
ns
ns
ns
1-5,14
CKo0 to CKo3
(32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay
4
CKo0 to CKo4 (1.544 MHz/2.048 MHz) delay
CKo4 @ 1.544 MHz
tC4D
-12
-2
-7
3
ns
ns
CKo4 @ 2.048 MHz
5
CKo0 to CKo5 (19.44 MHz) delay
tC5D
6
12
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ See “Performance Characteristics Notes” on page 112.
AC Electrical Characteristics† - Divided Slave Mode Output Timing
Characteristic Sym.
CKo0 to CKo1 (8.192 MHz) delay
Min.
Max.
Units Notes‡
1
2
3
tC1D
tC2D
tC3D
-1
-1
-2
2
3
2
ns
ns
ns
1-5,14
CKo0 to CKo2 (16.384 MHz) delay
CKo0 to CKo3
(16.384 MHz/8.192 MHz/4.096 MHz) delay
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ See “Performance Characteristics Notes” on page 112.
AC Electrical Characteristics† - Multiplied Slave Mode Output Timing
Characteristic Sym.
CKo0 to CKo1 (8.192 MHz) delay
Min.
Max.
Units Notes‡
1
2
3
tC1D
tC2D
tC3D
-1
-1
-1
2
3
3
ns
ns
ns
1-5,14
CKo0 to CKo2 (16.384 MHz) delay
CKo0 to CKo3
(32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ See “Performance Characteristics Notes” on page 112.
109
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
FPo0
V
CT
CKo0
(4.096 MHz)
V
V
V
CT
CT
CT
t
C4D
CKo4
(1.544 MHz)
t
t
t
C1D
C2D
C5D
CKo1
(8.192 MHz)
V
V
V
CKo2
CT
CT
CT
(16.384 MHz)
CKo5
(19.44 MHz)
t
C3D
CKo3
(32.768 MHz)
Figure 47 - Output Timing (ST-BUS Format)
110
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
DPLL Performance Characteristics† - Accuracy & Switching
Characteristics
Conditions/
Min.
Max.
Units
Notes‡
1
2
3
4
5
6
7
8
9
Freerun Accuracy
-0.003
-0.03
-260
0
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ns
1,5,7
1,4,8
Initial Holdover Frequency Stability
0.03
260
82.5
64.5
248
242
31
Pull-in/Hold-in Range (Stratum 4E)
1,3,7,9
1,3,7,9,12
Reference Far Hysteresis Limit (Stratum 4E)
Reference Near Hysteresis Limit (Stratum 4E)
Reference Far Hysteresis Limit (Relaxed Stratum 4E)
Reference Near Hysteresis Limit (Relaxed Stratum 4E)
Output phase continuity for reference switch1
Normal output phase alignment speed (phase slope)
-82.5
-64.5
-248
1,3,7,9,13
-242
11
10
56
µs/s
s
10 Normal phase lock time2
75
1,3,7,9,10
1. Reference switching to normal, holdover, or freerun mode
2. -32 to +32 ppm locking
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ See “Performance Characteristics Notes” on page 112.
DPLL Performance Characteristics† - Output Jitter Generation (Unfiltered except for CKo5)
Typ.‡
Characteristics
Units
Conditions/Notes*
1
2
3
4
5
Jitter at CKo0 and CKo3 (4.096 MHz)
810
800
710
670
ps-pp
ps-pp
ps-pp
ps-pp
1-6,14
Jitter at CKo1 and CKo3 (8.192 MHz)
Jitter at CKo2 and CKo3 (16.384 MHz)
Jitter at CKo3 (4.096, 8.192, 16.384, or 32.768 MHz)
Jitter at CKo4 (1.544 MHz or 2.048 MHz)
1.544 MHz
2.048 MHz
1060
630
ps-pp
ps-pp
6
Jitter at CKo5 (19.44 MHz)
unfiltered jitter
770
540
460
510
ps-pp
ps-pp
ps-pp
ps-pp
500 Hz - 1.3 MHz jitter
65 kHz - 1.3 MHz jitter
12 kHz - 1.3 MHz jitter
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* See “Performance Characteristics Notes” on page 112
111
Zarlink Semiconductor Inc.
ZL50019
Data Sheet
Performance Characteristics Notes
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production
testing.
1. Jitter on master clock input (XIN) is 100 ps pp or less.
2. Jitter on reference input (REF0-3) is 2 ns pp or less.
3. Normal Mode selected.
4. Holdover Mode selected.
5. Freerun Mode selected.
6. Jitter is measured without an output filter.
7. Accuracy of master clock input (XIN) is 0 ppm.
8. Accuracy of master clock input (XIN) is 100 ppm.
9. Capture range is +/-260 ppm; inaccuracy of XIN shifts this range.
10. Phase alignment speed (phase slope) is programmed to 7 ns/125µs.
11. Any input reference switch or state switch (i.e. REF0 to REF3, Normal to Holdover, etc.).
12. Multi-period near limits and far limits are programmed to +/-64.713 ppm & +/-82.487 ppm respectively. (ST4_LIM = 1)
13. Multi-period near limits and far limits are programmed to +/-240 ppm & +/-250 ppm respectively. (ST4_LIM = 0)
14. 30 pF load on output pin.
112
Zarlink Semiconductor Inc.
b
Package Code
c
Zarlink Semiconductor 2003 All rights reserved.
Previous package codes
1
ISSUE
ACN
214440
26June03
DATE
APPRD.
Package Code
c
Zarlink Semiconductor 2003 All rights reserved.
Previous package codes
ISSUE
ACN
DATE
APPRD.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
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