ZL50075GAC [ZARLINK]
32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs; 32 K通道数字开关高抖动容限，转换率每2流（ 8 ， 16 ， 32或64 Mbps）和64个输入和64个输出组
| 型号： | ZL50075GAC |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs |
| 文件： | 总60页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL50075
32 K Channel Digital Switch with High Jitter
Tolerance, Rate Conversion per Group of
2 Streams (8, 16, 32 or 64 Mbps),
and 64 Inputs and 64 Outputs
Data Sheet
January 2006
Features
•
32,768 channel x 32,768 channel non-blocking
Ordering Information
digital Time Division Multiplex (TDM) switch at
65.536 Mbps or 32.768 Mbps or using a
combination of rates
ZL50075GAC
324 Ball PBGA
Trays
ZL50075GAG2 324 Ball PBGA** Trays
**Pb Free Tin/Silver/Copper
•
•
•
•
•
•
16,384 channel x 16,384 channel non-blocking
digital TDM switch at 16.384 Mbps
-40°C to +85°C
8,192 channel x 8,192 channel non-blocking
digital TDM switch at 8.192 Mbps
•
•
Per-channel A-Law/µ-Law Translation
Per-channel constant or variable throughput delay
for frame integrity and low latency applications
High jitter tolerance with multiple input clock
sources and frequencies
Up to 64 serial TDM input streams, divided into
32 groups with 2 input streams per group
•
•
•
•
•
Per-stream Bit Error Rate (BER) test circuits
Per-channel high impedance output control
Per-channel force high output control
Per-channel message mode
Up to 64 serial TDM output streams, divided into
32 groups with 2 output streams per group
Per-group input and output data rate conversion
selection at 65.536 Mbps, 32.768 Mbps,
16.384 Mbps and 8.192 Mbps. Input and output
data group rates can differ
Control interface compatible with Intel and
Motorola 16 bit non-multiplexed buses
•
•
Connection memory block programming
•
Per-group input bit delay for flexible sampling
point selection
Per-group output fractional bit advancement
Supports ST-BUS and GCI-Bus standards for
input and output timing
•
•
•
•
IEEE 1149.1 (JTAG) test port
Two sets of output timing signals for interfacing
additional devices
3.3 V I/O with 5V tolerant inputs; 1.8 V core
voltage
VDD_CORE
VDD_IO
VSS
ODE
PWR
STiA0
STiB0
SToA0
SToB0
Data Memory
P/S
Converter
:
:
S/P
Converter
:
:
STiA31
STiB31
Connection Memory
SToA31
SToB31
Input
Timing
Output
Timing
FPi0
CKi0
CK_SEL1-0
Timing
Test Access
Port
Microprocessor Interface
and Control Registers
FPo1-0
CKo1-0
Figure 1 - ZL50075 Functional Block Diagram
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50075
Data Sheet
Applications
•
•
•
•
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Large Switching Platforms
Central Office Switches
Wireless Base Stations
Multi-service Access Platforms
Media Gateways
Description
The ZL50075 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The
device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. With a
number of enhanced features, the ZL50075 is designed for high capacity voice and data switching applications.
The ZL50075 has 64 input and 64 output data streams which can operate at 8.192 Mbps, 16.384 Mbps,
32.768 Mbps or 65.536 Mbps. The large number of inputs and outputs maintains full 32 K x 32 K channel switching
capacity at bit rates of 65 Mbps and 32 Mbps. Up to 32 input and output data streams may operate at 65 Mbps. Up
to 64 input and output data streams may operate at 32 Mbps, 16 Mbps or 8 Mbps. The data rate can be
independently set in groups of 2 input or output streams. In this way it is possible to provide rate conversion from
input data channel to output data channel.
The ZL50075 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary
and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams
can independently reference their timings to the input clock or to the internal system clock.
The ZL50075 has a variety of user configurable options designed to provide flexibility when data streams are
connected to multiple TDM components or circuits. These include:
•
•
•
Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams
connected through different data paths
Two timing outputs, CKo1 - 0 and FPo1 - 0, which can be configured independently to provide a variety of
clock and frame pulse options
Support of both ST-BUS and GCI-Bus formats
The ZL50075 also has a number of value added features for voice and data applications:
•
Per-channel variable delay mode for low latency applications and constant delay mode for frame integrity
applications
•
•
Per-channel A-Law/µ-Law Conversions for both voice and data
64 separate Pseudo-random Bit Sequence (PRBS) test circuits; one per stream. This provides an integrated Bit
Error Rate (BER) test capability to facilitate data path integrity checking
The ZL50075 has two major modes of operation: Connection Mode (normal) and Message Mode. In Connection
Mode, data bytes received at the TDM inputs are switched to timeslots in the output data streams, with mapping
controlled by the Connection Memories. Using Zarlink's Message Mode capability, microprocessor data can be
broadcast to the output data streams on a per-channel basis. This feature is useful for transferring control and
status information to external circuits or other TDM devices.
A non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and
Control Registers used to program ZL50075 options. The port is configurable to interface with either 16 bit Motorola
or Intel-type microprocessors.
The mandatory requirements of IEEE 1149.1 standard are supported via the dedicated Test Access Port.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Switch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Stream Provisioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.1 Per Group Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 Rate Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.0 Input Clock (CKi) and Input Frame Pulse (FPi) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.0 Output Clock (CKo) and Output Frame Pulse (FPo) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0 Output Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Input Sampling Point Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Fractional Bit Advancement on Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.0 Message Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Data Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.0 Per-Channel A-Law/m-Law Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.0 Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.1 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.1.1 Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.1.2 Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.0 Power-up and Initialization of the ZL50075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11.1 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11.2 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.0 IEEE 1149.1 Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.3 Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.4 Boundary Scan Description Language (BSDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.0 Memory Map of ZL50075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.0 Detailed Memory and Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.1 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.1.1 Connection Memory Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
14.1.2 Connection Memory LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14.2 Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
14.3 BER Control Memory and Error Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14.3.1 Input BER Enable Control Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14.3.2 BER Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14.4 Group Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
14.5 Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
14.6 Output Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Table of Contents
14.7 Block Init Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
14.8 Block Init Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15.0 DC/AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
List of Figures
Figure 1 - ZL50075 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - 32 K x 32 K Channel Basic Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3 - Input and Output Data Rate Conversion Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4 - Input Sampling Point Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5 - Output Bit Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8 - Example PRBS Timeslot Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9 - Read Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10 - Write Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11 - Frame Pulse Input and Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12 - ST-Bus Frame Pulse and Clock Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 13 - GCI Frame Pulse and Clock Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 14 - Serial Data Timing to CKi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 15 - Serial Data Timing to CKo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 16 - Microprocessor Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 17 - Intel Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 18 - IEEE 1149.1 Test Port & PWR Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
List of Tables
Table 1 - Data Rate and Maximum Switch Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2 - TDM Stream Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5 - Example of Address and Byte Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6 - Byte Enable Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7 - Memory Data Word Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8 - Data Bus Word Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9 - Byte Address Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10 - Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11 - Connection Memory Group Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12 - Connection Memory Stream Address Offset at Various Output Rates . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13 - Connection Memory Timeslot Address Offset Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14 - Connection Memory Bits (CMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15 - Connection Memory LSB Group Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16 - Connection Memory LSB Stream Address Offset at Various Output Rates . . . . . . . . . . . . . . . . . . . . . 35
Table 17 - Data Memory Group Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 18 - Data Memory Stream Address Offset at Various Output Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19 - BER Enable Control Memory Group Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20 - BER Enable Control Memory Stream Address Offset at Various Output Rates . . . . . . . . . . . . . . . . . . 38
Table 21 - BER Counter Group and Stream Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22 - Group Control Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23 - Group Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24 - Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 25 - Output Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 26 - Block and Power-up Initialization Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Change Summary
The following table captures the changes from the April 2005 issue.
Page
25
Item
10.1.1, “Read Cycle“
Change
Clarified WAIT signal description in Read Cycle.
Corrected WAIT signal tristate timing in Read Cycle.
Clarified WAIT signal description in Write Cycle.
Corrected WAIT signal tristate timing in Write Cycle.
26
Figure 9 "Read Cycle Operation"
10.1.2, “Write Cycle“
26
27
Figure 10 "Write Cycle Operation"
38
Table 21 “BER Counter Group and
Stream Address Mapping“
Corrected BER Counter Group and Stream Mapping
Addresses.
The following table captures the changes from the July 2004 issue.
Page
Item
Change
10
"Pin Description" - CKo0-1
Added special requirement for using output clock at
65.536 MHz.
11
48
50
"Pin Description" - DTA, WAIT
Added more detailed description to the DTA and WAIT
pins.
“AC Electrical Characteristics1 - FPi0
and CKi0 Timing“
Added tFPIS, tFPIH (input frame pulse setup and hold)
maximum values.
(1) “AC Electrical Characteristics1 -
FPO0-1 and CKO0-1 (65.536 MHz)
Timing“
Added CKO0-1 and FPO0-1 setup and hold parameters for
all different clock rates.
(2) “AC Electrical Characteristics1 -
FPO0-1 and CKO0-1 (32.768 MHz)
Timing“
(3) “AC Electrical Characteristics1 -
FPO0-1 and CKO0-1 (16.384 MHz)
Timing“
(4) “AC Electrical Characteristics1 -
FPO0-1 and CKO0-1 (8.192 MHz)
Timing“
51
52
“AC Electrical Characteristics - Output
Clock Jitter Generation“
Added this table to specify CKO0-1 jitter generation.
“AC Electrical Characteristics1 - Serial
Data Timing2 to CKi“
(1) Values of parameters tSIPS, tSIPH, tSINS, tSINH, tSIPV,
tSINV, SIPZ and tSINZ are revised.
t
(2) Separated parameter tCKD into tCKDP and tCKDN.
Added more detail to figure.
53
54
Figure 14 "Serial Data Timing to CKi"
“AC Electrical Characteristics - Serial
Data Timing1 to CKo2“
(1) Values of parameters tSOPS, tSOPH, tSONS, tSONH, tSOPV,
tSONV, SOPZ and tSONZ are revised.
t
(2) Added CKO skew parameter, tCKOS, (clock source to
internal APLL).
55
Figure 15 "Serial Data Timing to CKo"
Added more detail and tCKOS to figure.
7
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Pin Diagram - ZL50075 19 mm x 19 mm 324 Ball PBGA (as viewed through top of package)
A1 corner identified by metallized marking.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
D[15] D[14] D[5] D[4] D[3] A[18] A[17] A[13] A[12] A[11] A[8]
A[4]
A[2]
A[0] R/W
DS
IC
DTA
A
B
C
D
E
F
STOA IM
[1]
D[11] D[10] D[8] D[7] D[6] D[1] A[15] A[10] A[5]
A[1]
NC
CS SIZ[0] PWR STOA SIZ[1]
[31]
STIA STIB STIA STIB STOA D[13] D[9] D[0] A[14] A[9]
A[6] BERR WAIT STIB TDO STIA TRST NC
[31] [31]
[2]
[1]
[0]
[0]
[0]
STOB CKO STIA STOB VDD_ D[12] D[2] VDD_ A[16] VDD_ A[7]
[2] [0] [1] [0] CORE CORE IO
A[3] VDD_ TCK VDD_ TMS STOB STOB
IO CORE [30] [31]
STIA STIB STOB FPO VSS VSS VDD_ VDD_ VSS VDD_ VDD_ VSS VDD_ VDD_ TDI STOA STIB STIA
[3] [2] [1] [0] CORE IO CORE IO CORE IO [30] [30] [30]
STOB STIB STOA VDD_ VDD_ VSS VSS VDD_ VDD_ VSS VDD_ VDD_ VSS VDD_ STOB STIB STOA STIA
[3] [3] [2] CORE IO CORE IO CORE IO CORE [29] [29] [29] [29]
STOA STIB STIA VDD_ VDD_ VDD_ VSS VSS VSS VSS VSS
VSS VDD_ VSS VDD_ STIB STOB STOA
G
H
J
[3] [4] [4] IO CORE IO IO IO [28] [28] [28]
VSS VSS STOA STOB VSS VDD_ VSS VSS VSS VSS VSS
VSS VDD_ VDD_ VSS STOA STOB STIA
[4] [4] CORE CORE IO [27] [27] [28]
STIA STOA STIB STOB VDD_ VSS VSS VSS VSS VSS VSS
VSS
VSS VDD_ STOA STOB VSS STIB
[5] [5] [5] [5] IO CORE [26] [26] [27]
ODE STIA STIA STOA VDD_ VDD_ VSS VSS VSS VSS VSS
VSS VDD_ VSS STIB
IC STOA STIA
K
L
[6]
[7]
[6] CORE IO
IO [25] [25] [27]
STIB STOB IC
STIA VSS VDD_ VSS VSS VSS VSS VSS
VSS VDD_ VDD_ STIA STOA STOB IC
CORE IO [24] [24] [24]
[6] [6]
[8]
CORE
STIB STOA STOB VDD_ VDD_ VDD_ VSS VSS VSS VSS VSS
[7] [7] [8] CORE IO IO
VSS VDD_ VDD_ VDD_ STIA STOB STIB
IO CORE CORE [23] [23] [26]
M
N
P
R
T
STOB STIB STIB VDD_ VDD_ VSS VSS VDD_ VDD_ VSS VDD_ VDD_ VSS
VSS VDD_ STOA STOB STIA
IO [22] [22] [26]
[7]
IC
[8]
[9]
IO CORE
CORE IO
CORE
IO
STIA STIA STOB VSS VSS VDD_ VDD_ VSS VDD_ VSS
VSS VDD_ VDD_ STOA STOB NC STOB
CORE IO [21] [21] [25]
[9] [10] [10] CORE IO CORE
STOA STOB STOA STIA VDD_ STOA STIA VDD_ STOA VDD_ STIB
[8] [9] [10] [12] IO [13] [15] CORE [15] IO [17]
IC
VDD_ STIB VDD_ STIA STIA STIA
IO [19] CORE [21] [22] [25]
STOA STIB STIA STOA STOA STIA STOB STIB STOB FPI STIA
[9] [10] [11] [11] [12] [13] [13] [15] [16] [0] [17]
IC
STIA STIA STIA STOA NC STIB
[18] [19] [20] [20] [24]
STIB STOB STIB CKO STIA STIB STOB STIA STOA IC
NC STOB CK_ STOB STOB STOB STIB STOA
[17] SEL[0 [18] [19] [20] [21] [23]
U
V
[11]
[11]
[12]
[1]
[14]
[14]
[15]
[16]
NC
[16]
IC
STOB FPO STIB STOA STOB STIB CKI
IC STOA CK_
STIB STOA STOA STIB STIB STIB
[12] [1] [13] [14] [14] [16] [0]
[17] SEL[1] [18] [18] [19] [20] [22] [23]
8
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Pin Description
Pin
Name
Description
TDM Interface
C3, D3, C1, E1,
G3, J1, K2, K3,
L4, P2, P3, T3,
STiA0-31 Serial TDM Input Data ’A’ Streams (5 V Tolerant Input with
Internal Pull-down)
The data rate of these input streams can be selected in a group of 2
to be either 8.192 Mbps, 16.384 Mbps, 32.678 Mbps or
65.536 Mbps. Refer to Section 1.4 for rate programming options.
The data streams can be selected to be either inverted or
non-inverted, programmed by the Group Control Registers (Section
14.4).
R4, T6, U5, R7,
U8, T11, T13, T14, T15, R16,
R17, M16, L15, R18, N18,
K18, H18, F18, E18, C16,
Unused inputs are pulled low by internal pull-down resistors and
may be left unconnected.
C4, C2, E2, F2,
G2, J3, L1, M1,
N2, N3, T2, U1,
STiB0-31 Serial TDM Input Data ’B’ Streams (5 V Tolerant Input with
Internal Pull-down)
The data rate of these input streams can be selected in a group of 2
to be either 8.192 Mbps, 16.384 Mbps, or 32.678 Mbps. The stream
is unused when its input group rate is 65.536 Mbps. Refer to
Section 1.4 for rate programming options.
U3, V3, U6, T8,
V6, R11, V13, R14, V16,
U17, V17, V18, T18, K15,
M18, J18, G16, F16, E17,
C14
The data streams can be selected to be either inverted or
non-inverted, programmed by the Group Control Registers (Section
14.4).
Unused inputs are pulled low by internal pull-down resistors and
may be left unconnected.
C5, B1, F3, G1,
H3, J2, K4, M2,
R1, T1, R3, T4,
SToA0-31 Serial TDM Output Data ’A’ Streams (5 V Tolerant, 3.3 V
Tri-state Slew-Rate Controlled Outputs)
The data rate of these output streams can be selected in a group of
2 to be either 8.192 Mbps, 16.384 Mbps, 32.678 Mbps or
65.536 Mbps. Refer to Section 1.4 for rate programming options.
The data streams can be selected to be either inverted or
non-inverted, programmed by the Group Control Registers (Section
14.4).
T5, R6, V4, R9,
U9, V11, V14, V15, T16,
P15, N16, U18, L16, K17,
J15, H16, G18, F17, E16,
B17
D4, E3, D1, F1,
H4, J4, L2, N1,
M3, R2, P4, U2,
SToB0-31 Serial TDM Output Data ’B’ Streams (5 V Tolerant, 3.3 V
Tri-state Slew-Rate Controlled Outputs)
The data rate of these output streams can be selected in a group of
2 to be either 8.192 Mbps, 16.384 Mbps or 32.678 Mbps. The
stream is unused when its output group rate is 65.536 Mbps. Refer
to Section 1.4 for rate programming options.
V1, T7, V5, U7,
T9, U12, U14, U15, U16,
P16, N17, M17, L17, P18,
J16, H17, G17, F15, D17,
D18
The data streams can be selected to be either inverted or
non-inverted, programmed by the Group Control Registers (Section
14.4).
Unused outputs are tristated and may be left unconnected.
V7
CKi0
ST-BUS/GCI-Bus Clock Input (5 V Tolerant Schmitt-Triggered
Input)
This pin accepts an 8.192 MHz, 16.384 MHz, 32.678 MHz or
65.536 MHz clock. This clock must be provided for correct
operation of the ZL50075. The frequency of the CKi0 input is
selected by the CK_SEL1-0 inputs. The active clock edge may be
either rising or falling, programmed by the Input Clock Control
Register (Section 14.5).
9
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Pin Description (continued)
Pin
Name
Description
T10
FPi0
ST-BUS/GCI-Bus Frame Pulse Input (5 V Tolerant Input)
This pin accepts the 8 kHz frame pulse which marks the frame
boundary of the TDM data streams. The pulse width is nominally
one CKi0 clock period (assuming ST-BUS mode) selected by the
CK_SEL1-0 inputs. The active state of the frame pulse may be
either high or low, programmed by the Input Clock Control Register
(Section 14.5).
D2, U4
CKo0-1
ST-BUS/GCI-Bus Clock Outputs (3.3 V Outputs with Slew-Rate
Control)
These clock outputs can be programmed to generate 8.192 MHz,
16.384 MHz, 32.678 MHz or 65.536 MHz TDM clock outputs. The
active edge can be programmed to be either rising or falling. The
source of the clock outputs can be derived from either the CKi0
inputs or the internal system clock. The frequency, active edge and
source of each clock output can be programmed independently by
the Output Clock Control Register (Section 14.6). For 65.536 MHz
output clock, the total loading on the output should not be larger
than 10pF.
E4, V2
U13, V12
K1
FPo0-1
ST-BUS/GCI-Bus Frame Pulse Outputs (3.3 V Outputs with
Slew-Rate Control)
These 8 kHz output pulses mark the frame boundary of the TDM
data streams. The pulse width is nominally one clock period of the
corresponding CKo output. The active state of each frame pulse
may be either high or low, independently programmed by the
Output Clock Control Register (Section 14.6).
CK_SEL0-1 TDM Master Clock Input Select
Inputs used to select the frequency and frame alignment of CKi0
and FPi0:
CK_SEL1 = 0, CK_SEL0 = 0, 8.192 MHz
CK_SEL1 = 0, CK_SEL0 = 1, 16.384 MHz
CK_SEL1 = 1, CK_SEL0 = 0, 32.768 MHz
CK_SEL1 = 1, CK_SEL0 = 1, 65.536 MHz
ODE
Output Drive Enable (5 V Tolerant Input with Internal Pull-up)
This is the asynchronous output enable control for the output
streams. When it is high, the streams are enabled. When it is low,
the output streams are tristated.
Microprocessor Port and Reset
A1, A2, C6, D6,
B3, B4, C7, B5,
B6, B7, A3, A4,
A5, D7, B8, C8
D15-0
Microprocessor Port Data Bus (5 V Tolerant Bi-directional with
Slew-Rate Output Control)
16 bit bi-directional data bus. Used for microprocessor access to
internal memories and registers.
A6, A7, D9, B9, C9, A8, A9,
A10, B10, C10, A11, D11,
C11, B11, A12, D12, A13,
B12, A14
A18-0
Microprocessor Port Address Bus (5 V Tolerant Inputs)
19 bit address bus for the internal memories and registers. Note A0
is not used and should be connected to a defined logic level.
10
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Pin Description (continued)
Pin
Name
Description
B14
CS
Chip Select Input (5 V Tolerant Input)
Active low input used with DS to enable read and write access to
the ZL50075.
A16
A15
DS
Data Strobe Input (5 V Tolerant Input)
Active low input used with CS to enable read and write access to
the ZL50075.
R/W
Read/Write Input (5 V Tolerant Input)
Input signal that controls the type of microprocessor access:
0 - Microprocessor write to the ZL50075
1 - Microprocessor read from the ZL50075
A18
C12
DTA
Data Transfer Acknowledge (5 V Tolerant, 3.3 V Tri-state Output
with Slew-Rate)
Active low output which indicates that a data bus transfer is
complete. An external pull-up resistor is required to hold this pin
HIGH when output is high-impedance.
BERR
Transfer Bus Error Output with Slew Rate Control (5 V Tolerant,
3.3 V Tri-state Outputs with Slew-Rate Control)
This pin goes low whenever the microprocessor attempts to access
an invalid memory space inside the device. In Motorola bus mode, if
this bus error signal is activated, the data transfer acknowledge
signal, DTA, will not be generated. In Intel bus mode, the generation
of the DTA is not affected by this BERR signal. An external pull-up
resistor is required to hold a HIGH level when output is
high-impedance.
C13
WAIT
Data Transfer Wait Output (5 V Tolerant, 3.3 V Tri-state Output
with Slew Rate)
Active low wait signal output. An external pull-up resistor is required
to hold a HIGH level when output is high-impedance.
B15, B18
SIZ0-1
Data Transfer Size/Upper and Lower Data Strobe Inputs (5 V
Tolerant Inputs)
Motorola mode: SIZ0 - LDS, SIZ1 - UDS.
Active low upper and lower data strobes, UDS and LDS, indicate
whether the upper byte, D15-8, and/or lower byte, D7-0, is being
transferred.
Intel mode: SIZ0 - BE0, SIZ1 - BE1.
Active low Intel type bus-enable signal BE1 and BE0 signals
B2
IM
Microprocessor Port Bus Mode Select (5 V Tolerant Input)
Control input:
0 = Motorola mode
1 = Intel mode
B16
PWR
Device Reset (5 V Tolerant Schmitt-Triggered Input)
Asynchronous reset input used to initialize the ZL50075.
0 = Reset
1 = Normal
See Section 11.0, Power-up and Initialization of the ZL50075 for
detailed description of Reset state.
11
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Pin Description (continued)
Pin
Name
Description
IEEE 1149.1 (JTAG) Test Access Port (TAP)
E15
TDI
Test Data (5 V Tolerant Input with Internal Pull-up)
Serial test data input. When not used, this input may be left
unconnected.
C15
D14
TDO
TCK
Test Data (3.3 V Output)
Serial test data output.
Test Clock (5 V Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Clock input used by TAP Controller. When not used, this input may
be left unconnected.
D16
C17
TMS
Test Reset (5 V Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Input which controls the state transitions of the TAP Controller.
When not used, this pin is pulled high by an internal pull-up resistor
and may be left unconnected.
TRST
Test Mode Select (5 V Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional mode.
When JTAG is not being used, this pin should be pulled low during
normal operation.
Unused
U10, V9, V10, R12, L18,
A17, L3, P1, T12, K16
IC
Internal Connections
In normal mode these pins MUST be connected low.
B13, C18, P17, T17, U11, V8
NC
No Connection
In normal mode these pins MUST be left unconnected.
Power
E5, E6, E9, E12, F6, F7, F10,
F13, G7, G8, G9, G10, G11,
G12, G14, H1, H2, H5, H7,
H8, H9, H10, H11, H12, H15,
J6, J7, J8, J9, J10, J11, J12,
J13, J17, K7, K8, K9, K10,
K11, K12, K14, L5, L7, L8,
L9, L10, L11, L12, M7, M8,
M9, M10, M11, M12, N6, N7,
N10, N13, N14, P5, P6, P9,
P11, P12
VSS
Ground
D5, D8, D15, E7, E10, E13,
F4, F8, F11, F14, G5, H6,
H13, J14, K5, L13, L6, M4,
M14, M15, N5, N8, N11, P7,
P10, P13, R8, R15
VDD_CORE Power Supply for the Core Logic: +1.8 V
12
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Pin Description (continued)
Pin
Name
Description
Power Supply for the I/O: +3.3 V
D10, D13, E8, E11, E14, F5,
F9, F12, G4, G6, G13, G15,
H14, J5, K6, K13, L14, M5,
M6, M13, N4, N9, N12, N15,
P8, P14, R5, R10, R13
VDD_IO
1.0 Functional Description
1.1 Overview
The device has 64 ST-BUS/GCI-Bus inputs (STiA0 - 31 and STiB0 - 31) and 64 ST-BUS/GCI-Bus outputs (SToA0 -
31 and SToB0 - 31). It is a non-blocking digital switch with 32,768 64 kbps channels and is capable of performing
rate conversion between groups of 2 inputs and 2 outputs. The inputs accept serial input data streams with data
rates of 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 32 input groups with each group
consisting of 2 streams (‘A’ and ‘B’). Each group can be set to any of the data rates. The outputs deliver serial data
streams with data rates of 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 32 output groups
with each group consisting of 2 streams (‘A’ and ‘B’). Each group can be set to any of the data rates.
By using Zarlink’s message mode capability, the microprocessor can store data in the connection memory which
can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other ST-BUS/GCI-Bus devices.
The ZL50075 uses the ST-BUS/GCI-Bus master input frame pulse (FPi0) and the ST-BUS/GCI-Bus master input
clock (CKi0) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with
various data rates (8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps). The rate of the input clock is defined
by setting the CK_SEL1 - 0 pins.
A selectable Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device
to operate in various modes under different switching configurations. Users can use the microprocessor port to
perform internal register and memory read and write operations. The microprocessor port has 16 bit data bus and
17 bit address bus (in A18-0, A0 is not used, and A1 is used for word alignment). There are seven control signals
(CS, DS, R/W, DTA, WAIT, BERR and IM).
The device supports the mandatory requirements for the IEEE 1149.1 (JTAG) standard via the test port.
1.2 Switch Operation
The ZL50075 switches 64 kbps and Nx64 kbps data and voice channels from the TDM input streams, to timeslots
in the TDM output streams. The device is non-blocking; all 32 K input channels can be switched through to the
outputs. Any input channel can be switched to any available output channel.
13
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
STiA0
STiB0
SToA0
SToB0
Output Group 0
Input Group 0
32 K x 32 K
TDM INPUT
64 Streams
TDM OUTPUT
64 Streams
SToA31
SToB31
STiA31
STiB31
Output Group 31
Input Group 31
ZL50075
Figure 2 - 32 K x 32 K Channel Basic Switch Configuration
The maximum channel switching capacity is determined by the number of streams and their rate of operation, as
shown in Table 1.
MaximumNumber MaximumNumber
Number of
64 kbps Channels
per Stream
Maximum Switch
Capacity† (streams
x channels = total)
TDM Group
Data Rate
of Input TDM Data
Streams
of Output TDM
Data Streams
65.536 Mbps
32.768 Mbps
16.384 Mbps
8.192 Mbps
32
64
64
64
32
64
64
64
1024
512
256
128
32 x 1024 = 32,768
64 x 512 = 32,768
64 x 256 = 16,384‡
64 x 128 = 8,192‡
Table 1 - Data Rate and Maximum Switch Size
† The maximum capacity shown is when all streams are at the same rate, and none are operating at 16.384 Mbps or 8.192 Mbps.
‡ Switch capacity is limited to less than 32 K channels, only when streams are provisioned at 16 Mbps or 8 Mbps. The maximum switch capac-
ity in this case is given by 32,768 - (M x 256) - (N x 384), where M is the number of 16 Mbps input or output streams, and N is the number of
8 Mbps input or output streams.
1.3 Stream Provisioning
The ZL50075 is a large switch with a comprehensive list of user configurable, ’per-group’ programmable features.
In order to facilitate ease of use, the ZL50075 offers a simple programming model. Streams are grouped in sets of
two, with each group sharing the same configured characteristics. In this way it is possible to reduce programming
complexity, while still maintaining flexible ’per-stream’ configuration options:
•
•
•
•
•
•
Input and output rate selection, see Section 1.4
Input stream clock source selection, see Section 2.0
Output stream clock source selection, see Section 2.0
Input stream sampling point selection, see Section 5.1
Output stream fractional bit advance, see Section 5.2
Input and output stream inversion control, see Section 14.4
The streams are grouped, one from the TDM ’A’ streams, combined with the corresponding ’B’ streams. For
example, input stream group #12 is STiA12 and STiB12, and output stream group #4 is SToA4 and SToB4. There
are 32 input and 32 output groups. Depending on the data rate set for the group there will be between 1 and 2
streams activated. If the data rate is set for 65.536 Mbps, the ‘A’ stream will be activated and the ‘B’ stream will not
be activated. If the data rate is set for 32.768 Mbps, 16.384 Mbps or 8.192 Mbps, the ‘A’ and ‘B’ streams will be
activated. The maximum channel capacity of a group is 1024 channels when operating at 65 Mbps or 32 Mbps. The
14
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
switch capacity is reduced to 512 channels when operating at 16 Mbps and to 256 channels when operating at
8 Mbps.
1.4 Input and Output Rate Selection
Table 1 shows the maximum number of streams available at different bit rates. The ZL50075 deactivates unused
streams when operating at the higher bit rates as shown in Table 2.
Input or Output Group n
65 Mbps
32 Mbps
16 Mbps
8 Mbps
(n = 0 - 31)
STiAn / SToAn
STiBn / SToBn
Active
Not Active
Active
Active
Active
Active
Active
Active
Table 2 - TDM Stream Bit Rates
For 65 Mbps operation, only those inputs and outputs in the TDM ’A’ streams are active. For 32 Mbps, 16 Mbps and
8 Mbps operation, the inputs and outputs in the TDM ’A’ and ’B’ streams are active.
Note that if the internal system clock is not used as the clock source, there are limitations on the maximum data
rate. See Section 2.0 for more details.
1.4.1 Per Group Rate Selection
See Section 14.4, Group Control Registers, for programming details. The data rates are set with the Input Stream
Bit Rate (bits 3 - 2) and the Output Stream Bit Rate (bits 19 - 18) in the Group Control Registers 0 - 31 (GCR0 - 31).
For the ZL50075, the bit rates of the inputs and outputs are programmed independently, in groups of 2 streams.
Depending on the rate programmed, the active streams in the group will be as indicated in Table 2.
For example:
•
•
if input stream group #1 is programmed for 65 Mbps: STiA1 is active; STiB1 is not active
if output stream group #15 is programmed for 32 Mbps, 16 Mbps or 8 Mbps: SToA15 and SToB15 are active
1.5 Rate Conversion
The ZL50075 supports rate conversion from any input stream rate to any output stream rate.
An example of ZL50075 rate conversion is given in Figure 3. The output stream rates do not have to follow the input
stream rates. In this example, on the input side of the switch you can have 24 streams operating at 65.536 Mbps
(24,576 channels - 24 groups with 1 stream in each group), 8 streams operating at 32.768 Mbps (4096 channels - 4
groups with 2 streams in each group) and 8 streams operating at 16.384 Mbps (2048 channels - 4 groups with 2
streams in each group) with no streams operating at 8.192 Mbps. This results in an input capacity of 30,720 input
channels. This is less than the full capacity of the device as some groups are operating at less than 32 Mbps. As
the output streams do not have to follow the input streams, they can be configured so that 15 streams operate at
65.536 Mbps (15,360 channels - 15 groups with 1 stream in each group), 28 streams operate at 32.768 Mbps
(14,336 channels - 14 groups with 2 streams in each group), 2 streams operate at 16.384 Mbps (512 channels - 1
group with 2 streams in the group) and 4 streams operate at 8.192 Mbps (512 channels - 2 groups with 2 streams in
each group). This results in an output capacity of 30,720 output channels. This is less than the full capacity of the
device as some groups are operating at less than 32 Mbps.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
STiA0 - 23 at 65 Mbps
STiB0 - 23 Not Active
SToA0 - 14 at 65 Mbps
SToB0 - 14 Not Active
Output Groups
0 - 14 at 65 Mbps
Input Groups
0 - 23 at 65 Mbps
SToA15 - 28 at 32 Mbps
SToB15 - 28 at 32 Mbps
Output Groups
15 - 28 at 32 Mbps
STiA24 - 27 at 32 Mbps
STiB24 - 27 at 32 Mbps
Input Groups
24 - 27 at 32 Mbps
SToA29 at 16 Mbps
SToB29 at 16 Mbps
Output Group
29 at 16 Mbps
STiA28 - 31 at 16 Mbps
STiB28 - 31 at 16 Mbps
Input Groups
SToA30 - 31 at 8 Mbps
SToB30 - 31 at 8 Mbps
28 - 31 at 16 Mbps
Output Groups
30 - 31 at 8 Mbps
Example:
Input Groups 0 - 23 at 65 Mbps; Output Groups 0 - 14 at 65 Mbps
Input Groups 24 - 27 at 32 Mbps; Output Groups 15 - 28 at 32 Mbps
Input Groups 28 - 31 at 16 Mbps; Output Group 29 at 16 Mbps
Output Groups 30 - 31 at 8 Mbps
Figure 3 - Input and Output Data Rate Conversion Example
2.0 Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The input timing for the ZL50075 can be set for one of four different frequencies. They can also be set for ST-BUS
or GCI-Bus mode with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the
device to be used. CKi0 is used to generate the internal clock. This clock is used for all the internal logic and can be
used as one of the clocks that defines the timing for the input and output data. The input stream clock source is
selected by the ISSRC1 - 0 (bits 1 - 0) in the Group Control Register. The output stream clock source is selected by
the OSSRC1 - 0 (bits 17 - 16) in the Group Control Register.
The CKi0 and FPi0 input frequency is set via the CK_SEL1 - 0 pins as shown in Table 3. By default the CKi0 and
FPi0 pins accept ST-BUS, negative input timing. The input frame pulse format (ST-BUS/GCI-Bus), frame pulse
polarity, and clock polarity can be programmed by the GCISEL0 (bit 2), FPIPOL0 (bit 1), and CKIPSL0 (bit 0) in the
Input Clock Control Register (ICCR), as described in Section 14.5.
CK_SEL1
CK_SEL0
Input CKi0 and FPi0
0
0
1
1
0
1
0
1
8.192 MHz
16.384 MHz
32.768 MHz
65.536 MHz
Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0
The input streams, output streams, and output clocks / frame pulses can use either the internal system clock or the
input CKi0 and FPi0 as clock sources. The input streams’ clock sources are controlled by the ISSRC1-0 (bits 1 - 0)
in the Group Control Registers (GCR). The output streams’ clock sources are controlled by the OSSRC1-0 (bits 17
- 16) in the Group Control Registers (GCR). The output clocks’ / frame pulses’ clock sources are controlled by the
CKO1SRC1-0 (bits 8-7) and CKO0SRC1-0 (bits 1-0) in the Output Clock Control Register (OCCR). Using the input
CKi0 and FPi0 as clock source provides a direct interface to jittery peripherals, while using the internal system clock
as clock source provides the best data rate and clock rate flexibility.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
When the internal system clock is not used as the clock source, there are limitations to the data rate and the output
clock rate. For all the input and output stream groups that do not use the internal system clock as their clock source,
the data rate is limited to be no higher than the selected clock source’s rate (e.g., if CKi0 runs at 16.384 MHz and it
is selected as the clock source for input stream group 3, then the maximum data rate of STiA3 and STiB3 is
16.384 Mbps). Similarly, for all the output clocks that do not use the internal system clock as their clock source, the
clock rate is limited to be no higher than the selected clock source’s rate (e.g., if CKi0 runs at 32.768 MHz and it is
selected as the clock source for output clock CKo0, then the maximum clock rate of CKo0 is 32.768 MHz).
3.0 Output Clock (CKo) and Output Frame Pulse (FPo) Timing
There are two output timing pairs, CKo1 - 0 and FPo1 - 0. By default these signals generate ST-BUS, negative
timing, and use the internal system clock as reference clock source. Their default clock rates are 65.536 MHz for
CKo0 and 32.768 MHz for CKo1. Their properties can also be individually programmed in the Output Clock Control
Register (OCCR) to control the frame pulse format (ST-BUS/GCI-Bus), frame pulse polarity, clock polarity, clock
rate (8.192 MHz, 16.384 MHz, 32.768 MHz or 65.536 MHz), and reference clock source. Refer to Section 14.6 for
programming details. Note that the reference clock source can be set to either the internal system clock or the input
CKi0 and FPi0 signals. If the input CKi0 and FPi0 is selected as the reference source, the output clock cannot be
programmed to generate a higher clock frequency than the reference source. As each output timing pair has its
own bit settings, they can be set to provide different output timings. For 65.536 MHz output clock, the total
loading on the output should not be larger than 10pF.
4.0 Output Channel Control
To be able to interface with external buffers, the output signals can be set to enter a high impedance or drive high
state on a per-channel basis. The Per Channel Function (bits 31 - 29) in the Connection Memory Bits can be set to
001 to drive the channel output high, or to 000, 110 or 111 to set the channel into a high impedance state.
5.0 Data Input Delay and Data Output Advancement
The Group Control Registers (GCR) are used to adjust the input delay and output advancement for each input and
output data groups. Each group is independently programmed.
5.1 Input Sampling Point Delay Programming
The input sampling point delay programming feature provides users with the flexibility of handling different wire
delays when incoming traffic is from different sources.
By default, all input streams have zero delay, such that bit 7 is the first bit that appears after the input frame
boundary (assuming ST-BUS formatting). The nominal input sampling point with zero delay is at the 3/4 bit time.
The input delay is enabled by the Input Sample Point Delay (bit 8 - 4) in the Group Control Registers 0 - 31 (GCR0
- 31) as described in Section 14.4 on page 39. The input sampling point delay can range from 0 to 7 3/4 bit delay
with a 1/4 bit resolution on a per group basis.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Nominal Channel n Boundary
Nominal Channel n+1 Boundary
STi[n]
0
7
6
5
4
3
2
1
0
7
6
00000 (Default)
00001
11111
11110
11101
00010
00011
00100
11100
11011
00101
00110
00111
01000
01001
11010
11001
11000
10111
10110
01010
01011
10101
10100
01100
01101
01110
01111
10011
10010
10001
10000
Example: With a setting of 01111 the sampling point for bit 7 will be 3 1/2 bits
Figure 4 - Input Sampling Point Delay Programming
There are limitations when the ZL50075 is programmed to use CKi0 as the input stream clock source as opposed
to the internal clock:
•
•
The granularity of the delay becomes 1/2 the selected reference clock period, or 1/4 bit, whichever is longer
If the selected reference clock frequency is the same as the stream bit rate, the granularity of the delay is 1/2 bit.
In this case, the least significant bit of the ISPD register is not used; the remaining 4 bits select the total delay in
1/2 bit increments, to a maximum of 7 1/2 bits. Also, the 0 bit delay reference point changes from the 3/4 bit
position to the 1/2 bit position.
5.2 Fractional Bit Advancement on Output
See Section 14.4, Group Control Registers, for programming details.
This feature is used to advance the output data with respect to the output frame boundary. Each group has its own
bit advancement value which can be programmed in the Group Control Registers 0 - 31 (GCR0 - 31).
By default all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by the Output Stream Bit
Advancement (bits 21 - 20) of the Group Control Registers 0 - 31 (GCR0 - 31), as described in Section 14.4. The
output delay can vary from 0 to 22.8 ns with a 7.6 ns increment. The exception to this is output streams
programmed at 65 Mbps, in which case the increment is 3.8 ns with a total advancement of 11.4 ns.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Nominal 8 MHz
Clock
Nominal 16 MHz
Clock
Nominal 32/65 MHz
Clock
Nominal Output
Bit Timing
OSBA = 00
OSBA = 01
7.6ns (~3.8 ns at 65 Mbps)
Level 1
Advance
15.2ns (~7.6 ns at 65 Mbps)
22.8ns (~11.4 ns at 65 Mbps)
Level 2
Advance
OSBA = 10
OSBA = 11
Level 3
Advance
Figure 5 - Output Bit Advancement Timing
This programming feature is provided to assist in designs where per stream routing delays are significant and
different.
The OSBA bits in the Group Control Registers are used to set the bit-advancement for each of the corresponding
serial output stream groups. Figure 5 illustrates the effect of the OSBA settings on the output timing.
There are limitations when the ZL50075 is programmed to use CKi0 as the output stream clock source:
•
If the selected reference clock frequency is 65 MHz or 32 MHz, the granularity of the advancement is
reduced to 1/2 the clock period
•
If the selected reference clock frequency is 16 MHz or 8 MHz, bit advancement is not available and the
output streams are driven at the nominal times
6.0 Message Mode
In Message Mode (MSG), microprocessor data can be broadcast to the output data streams on a per-channel
basis. This feature is useful for transferring control and status information to external circuits or other TDM devices.
For a given output channel, when the corresponding Per Channel Function (bits 31 - 29) in the Connection Memory
are set to Message Mode (010), the Connection Memory’s lowest data byte (bits 7 - 0) is output in the timeslot.
Refer to Section 14.1.1, Connection Memory Bit Functions, for programming details
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
To increase programming bandwidth, the ZL50075 has separate addressable 32 bit memory locations, called
Connection Memory Least Significant Bytes (LSB), which provide direct access to the Connection Memories’
Lowest data bytes (bits 7 - 0). Up to four consecutive message mode channels can be set with one Connection
Memory LSB access. Refer to Section 14.1.2, Connection Memory LSB, for programming details.
6.1 Data Memory Read
All TDM input channels can be read via the microprocessor port. This feature is useful for receiving control and
status information from external circuits or other TDM devices. Each 32 bit Data Memory access enables up to four
consecutive input channels to be monitored. The Data Memory field is read only; any attempt to write to this
address range will result in a bus error condition signalled back to the host processor. Refer to Section 14.2, Data
Memory, for programming details.
The latency of data reads is up to 3 frames, depending on when the input timeslots are sampled.
6.2 Connection Memory Block Programming
See Section 14.7, Block Init Register, and Section 14.8, Block Init Enable Register, for programming details.
This feature allows for fast initialization of the connection memory after power up. When the block programming
mode is enabled, the contents of Block Init Register are written to all Connection Memory Bits. This operation
completes in one 125 µs frame. During Connection Memory initialization, all TDM output streams are set to high
impedance.
7.0 Data Delay Through the Switching Paths
See Section 14.1.1, Connection Memory Bit Functions, for programming details.
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data application, select constant delay to maintain the frame
integrity of the information through the switch. The delay through the device varies according to the type of
throughput delay selected by programming the Per Channel Function (bits 31 - 29) in the Connection Memories.
When these bits are set to 011, the channel is in variable delay mode. When they are set to 100, the channel is in
constant delay mode.
7.1 Constant Delay Mode
In this mode the frame integrity is maintained in all switching configurations. The delay though the switch is 2
frames - Input Channel + Output Channel. This can result in a minimum delay of 1 frame + 1 channel if the last
channel of a stream is switched to the first channel of a stream. The maximum delay is 1 channel short of 3 frames
delay. This occurs when the first channel of a stream is switched to the last channel of a stream.
The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (n) and
output channel number (m). The data throughput delay (T) is:
T = 2 frames + (n - m)
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
Figure 6 - Data Throughput Delay for Constant Delay
7.2 Variable Delay Mode
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for
voice applications where the minimum throughput delay is more important than data integrity. The delay through the
switch is minimum 3 channels and maximum 1 frame + 2 channels.
N-2 N-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
N-2 N-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
N-2 N-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
N-2 N-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
Figure 7 - Data Throughput Delay for Variable Delay
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
8.0 Per-Channel A-Law/µ-Law Translation
The ZL50075 provides per channel code translation to be used to adapt pulse code modulation (PCM) voice or data
traffic between networks which use different encoding laws. Code translation is available in both Connection Mode
and Message Mode.
This feature is controlled by the Connection Memories. The V/D (bit 28) defines if the traffic in the channel is voice
or data. The ICL1 - 0 (bits 27 - 26) define the input coding law and the OCL1 - 0 (bits 25 - 24) define the output
coding law. The different coding options are shown in Table 4:
Input Coding
(ICL1- 0)
Output Coding
(OCL1 - 0)
Voice Coding
(V/D bit = 0)
Data Coding
(V/D bit = 1)
00
01
10
00
01
10
ITU-T G.711 A-Law
ITU-T G.711 µ-Law
A-Law without Alternate Bit
Inversion (ABI)
No Code
Alternate Bit Inversion (ABI)
Inverted Alternate Bit
Inversion (ABI)
11
11
µ-Law without Magnitude
All Bits Inverted
Inversion (MI)
Table 4 - Input and Output Voice and Data Coding
For voice coding options, the ITU-T G.711 A-Law and ITU-T G.711 µ-Law are the standard rules for encoding. The
A-Law without Alternate Bit Inversion (ABI) is an alternative code that does not invert the even bits (6, 4, 2, 0). The
µ-Law without Magnitude Inversion (MI) is an alternative code that does not perform Inversion of magnitude bits (6,
5, 4, 3, 2, 1, 0).
When performing data code options, No Code does not invert the bits. The Alternate Bit Inversion (ABI) option
inverts the even bits (6, 4, 2, 0) while the Inverted Alternate Bit Inversion (ABI) inverts the odd bits (7, 5, 3, 1). When
All Bits Inverted is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted.
The input channel and output channel encoding law are configured independently. If the output channel coding is
set to be different from the input channel, the ZL50075 performs translation between the two standards. If the input
and output encoding laws are set to the same standard, no translation occurs.
9.0 Bit Error Rate Tester
The ZL50075 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output
streams, resulting in 64 transmitters connected to the output streams and 64 receivers associated with the input
streams. Each transmitter can generate a BER sequence with a pattern of 215-1 Pseudo-Random Code (ITU
O.151). Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a
maximum of 1 frame time (125 µs). The BER transmitters are enabled by programming the Per Channel Function
(bit 31 - 29) to 101 (PRBS Generator mode) in the Connection Memories.
Multiple Connection Memory locations can be programmed for BER tests. These locations are not required to be
consecutive. However, when read back, the BER locations must be received in the same order that they were
transmitted. If the BER locations are not received in the same order, the BER test will produce errors.
The PRBS bit pattern is sequentially loaded into the output timeslots. An example is shown in Figure 8.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
‘
Example segment of serial bit pattern
from Stream N PRBS Generator
..010111001101101111001010110110001011111011010011100001101...
Stream N with Channels
a, b and c enabled
for PRBS insertion
a
b
c
a
b
c
Frame m
Frame m+1
Figure 8 - Example PRBS Timeslot Insertion
Each PRBS detector can be configured to monitor for bit errors in one or more timeslots. The selection of timeslots
is configured by the Input BER Enable Control Memory (IBERECM). See Section 14.3.1 for programming details,
Each detector has an associated 16 bit error counter accessible via the microprocessor interface, as described in
Section 14.3.2, BER Counters. The value of the counter represents the total number of errors detected on the
corresponding input stream. Bit errors are accumulated until the counter is either reset (by writing to the counter or
by resetting the device), or the counter reaches its maximum value, 65,535 (decimal). If more than 65,535 errors
are detected, the counter will hold at the maximum value until reset.
Any number of timeslots may be configured for bit error rate testing; however the user must ensure the following for
correct operation of the BER test function:
1. The number of timeslots enabled for PRBS detection on the input stream must equal the number of timeslots
enabled for PRBS generation on the source output stream
2. The arrival order of timeslots at the PRBS detector must be the same as the order in which timeslots were trans-
mitted by the PRBS generator. For example, in Figure 8 above, the timeslot order a, b, c must be maintained
through the external path from source TDM output stream to destination TDM input stream.
10.0 Microprocessor Port
The ZL50075 has a generic 16-bit microprocessor port that provides access to the 32-bit internal Data Memory
(read access only), Connection Memory and Control Registers. D15 on the bus maps to Bit 31 and Bit 15 of the
internal 32 bit memory or register, D14 maps to Bit 30 and Bit 14, etc.
The IM pin is used to select between Motorola bus control and Intel bus control. If the IM input is low, then a
Motorola control is selected. If the IM bit is high, then an Intel control is selected. Regardless of which bus
configuration is selected, the bus cycle termination signals WAIT & DTA are both provided.
The Data Memory, Connection Memory and Control Registers are assigned 32 bit fields in the ZL50075 memory
space. Each 32 bit memory or register location spans 4 consecutive addresses. Example:
•
The 32 bit Group Control Register for TDM Group 0 is located at address range 40200 - 40203 Hex
The Least Significant address identifies the Most Significant Byte (MSB) in the 32 bit field, as illustrated in Table 5.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Address (Hex)
Memory/Register Bits
40200
40201
40202
40203
Bits 31:24 (MSB)
Bits 23:16
Bits 15:8
Bits 7:0 (LSB)
Table 5 - Example of Address and Byte Significance
The Address Bus, A18 - 0, controls access to each 32 bit location. A0 is not used and must be connected to defined
logic level. Address bit A1 and the Data Transfer Size inputs, SIZ1 - 0, identify which bytes are being accessed.
In Motorola Bus Mode (IM = 0), SIZ1 - 0 form active low data strobe signals, consistent with UDS and LDS available
on the MC68000 and MC68302 processors, as shown in Table 6.
In Intel Bus Mode (IM = 1), SIZ1 - 0 form active low byte enable signals, consistent with BE1 and BE0 available on
the Intel i960 processor, as shown in Table 6.
Motorola Mode MC68000, MC68302
Equivalent Function
IM = 0
Intel Mode i960
Equivalent Function
IM = 1
Pin Name
Data Bus Bytes Enabled
SIZ1
SIZ0
UDS
LDS
BE1
BE0
D15-8
D7-0
Table 6 - Byte Enable Signals
In both Intel and Motorola modes, the A1 address input is used to identify the word alignment in internal memory, as
shown in Table 7.
A1
Memory Data Word Alignment
0
1
Bits 31:16
Bits 15:0
Table 7 - Memory Data Word Alignment
Data bus word alignments are shown in Table 8. An example of byte addressing is given in Table 9.
Microprocessor
16 Bit Data Bus
Internal 32-Bit Memory
SIZ1
SIZ0
A1
or Register
D15 - 8
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
1
0
Bits 31:24
Bits 15:8
Bits 23:16
Bits 7:0
Bits 31:16
Bits 15:0
No access
D7 - 0
D15 - 0
1
X1
Table 8 - Data Bus Word Alignment
1. X - Don’t Care
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Address
(Hex)
Register
Register
Byte
A18 - 0 (binary)
SIZ1 SIZ0
Comments
Description
40200 or
40201
40282 or
40283
40286 or
40287
40284 or
40285
Group Control
Bits 23:16 100 0000 0010 0000 000X†
1
0
0
0
0
1
0
0
8 bit transfer
Register (Group 0)
Input Clock Control
Register
Bits 15:8
Bits 15:0
100 0000 0010 1000 001X†
100 0000 0010 1000 011X†
8 bit transfer
16 bit transfer
16 bit transfer
Output Clock
Control Register
Output Clock
Bits 31:16 100 0000 0010 1000 010X†
Control Register
Table 9 - Byte Address Examples
† - Don’t Care. A0 is not used.
10.1 Bus Operation
10.1.1 Read Cycle
The operation of a read cycle is illustrated in Figure 9.
•
The microprocessor asserts the R/W control signal high, to signal a read cycle. It also drives the address A,
transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL50075
•
The microprocessor then drives the DS signal active low, to signal the start of the bus cycle. The DS signal
is held low for the duration of the bus cycle
•
•
WAIT is asserted active low
The ZL50075 accesses the requested memory or register location(s), and places the requested data onto
the data bus, D15 - 0. All data bus pins are driven, whether or not they are being used for the specific data
transfer. Unused pins will present unknown data. If the address is to an unused area of the memory space,
unknown data is presented on the data bus
•
•
•
•
The ZL50075 then de-asserts WAIT, and asserts either DTA or BERR, depending on the validity of the data
transfer
When the microprocessor observes the active low state of the DTA or the BERR signal or the low-to-high
transition of the WAIT signal, it terminates the bus cycle by driving the DS pin inactive high
When the ZL50075 sees the DS signal go inactive high, it removes the assertions on the DTA or BERR
signals by driving them inactive high
When the ZL50075 sees the CS signal go inactive high, it tri-states the data bus, D15 - 0 and the DTA,
BERR and WAIT signals. However, if CS goes inactive high before DS goes inactive high, the DTA, BERR
and WAIT signals are driven inactive high before they are tri-stated
•
In Intel mode, DTA is always driven to signal the end of a bus cycle, regardless of BERR
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Address A,
SIZ1 - 0
CS
R/W
DS
Hi-Z
Data
Hi-Z
DTA
BERR
Hi-Z
Hi-Z
WAIT
The cycle termination signals WAIT & DTA are provided for all bus configurations.
Figure 9 - Read Cycle Operation
10.1.2 Write Cycle
The operation of the write cycle is illustrated in Figure 10.
•
The microprocessor asserts the R/W control signal low, to signal a write cycle. It also drives the address A,
data transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL50075
•
The microprocessor then drives the data bus, D15 - 0 with the data to be written, and then drives the DS
signal active low, to signal the start of the bus cycle. The DS signal is held low for the duration of the bus
cycle
•
•
WAIT is asserted active low
The ZL50075 transfers the data presented on the data bus pins into the indicated memory or register
location(s). If the address is to an unused area of the memory space, or to the data memory, no data is
transferred. The microprocessor port cannot write to the Data Memory
•
•
•
•
The ZL50075 then de-asserts WAIT, and asserts either DTA or BERR, depending on the validity of the data
transfer
When the microprocessor observes the active low state of the DTA or the BERR signal or the low-to-high
transition of the WAIT signal, it terminates the bus cycle by driving the DS pin inactive high
When the ZL50075 sees the DS signal go inactive high, it removes the assertions on the DTA or BERR
signals by driving them inactive high
When the ZL50075 sees the CS signal go inactive high, it tri-states the DTA, BERR and WAIT signals.
However, if CS goes inactive high before DS goes inactive high, the DTA, BERR and WAIT signals are
driven inactive high before they are tri-stated
•
In Intel mode, DTA is always driven to signal the end of a bus cycle, regardless of BERR
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Address
SIZ1 - 0
CS
R/W
DS
Data
DTA
BERR
Hi-Z
Hi-Z
Hi-Z
WAIT
The cycle termination signals WAIT & DTA are provided for all bus configurations.
Figure 10 - Write Cycle Operation
11.0 Power-up and Initialization of the ZL50075
11.1 Device Reset and Initialization
The PWR pin is used to reset the ZL50075. When this pin is low, the following functions are performed:
•
•
•
•
Asynchronously puts the microprocessor port in a reset state
Tristates all of the output streams (SToA0 - 31, SToB0 - 31)
Preloads all of the registers with their default values (refer to the individual registers for default values)
Clears all internal counters
11.2 Power Supply Sequencing
The ZL50075 has two separate power supplies: VDD_IO (3.3 V) and VDD_CORE (1.8 V). The recommended
power-up sequence is for VDD_IO to be applied first, followed by the VDD_CORE supply. VDD_CORE should not lead
VDD_IO supply by more than 0.3 V. Both supplies may be powered-down simultaneously.
11.3 Initialization
Upon power up, the ZL50075 should be initialized as follows:
•
•
•
•
Assert PWR to low immediately after power is applied
Set the TRST pin low to disable the JTAG TAP controller
Deassert the PWR pin.
Apply the Master Clock Input (CKi0) and Master Frame Pulse Input (FPi0) to the values defined by the
CK_SEL1 - 0 pins
•
Set the ODE pin low to disable the output streams
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Note: After the PWR reset is removed, and on the application of a suitable master clock input, it takes
approximately 1 ms for the internal initialization to complete
•
•
•
Automatic block initialization of the Connection Memory to all zeros occurs, without microprocessor
intervention
All Group Control Registers are preset to 000C000C hex, corresponding to rates of 65 Mbps, no link
inversions, no fractional output bit advancements, internal clock source, and no input sample point delays
The Input Clock Control Register is preset to 0DB hex, corresponding to:
-
-
-
All clock inputs set to negative logic sense
All frame pulse inputs set to negative logic sense
All input frame pulses set to ST-BUS timing
•
The Output Clock Control Register is pre-set to 060D1C3C hex, corresponding to:
-
-
-
-
-
All clock outputs set to negative logic sense
All frame pulse outputs set to negative logic sense
All output frame pulses set to ST-BUS timing
All output clock source selections to internal
Clock outputs, CKo0 - 1 are preset to rates of 65 MHz and 32 MHz, respectively
Note: If the master clock input, CKi0, is not available, the microprocessor port will assert BERR on all accesses and
read cycles.
12.0 IEEE 1149.1 Test Access Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE 1149.1 (JTAG) standard. The
operation of the boundary-scan circuity is controlled by an external Test Access Port (TAP) Controller.
The ZL50075 uses the public instructions defined in IEEE 1149.1, with the provision of a 16-bit Instruction Register,
and three scannable Test Data Registers: Boundary Scan Register, Bypass Register and Device Identification
Register.
12.1 Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50075 test functions. The interface consists of 4 input and 1 output
signal. as follows:
•
Test Clock (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or out
of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
•
•
Test Mode Select (TMS) - The TAP Controller uses the logic signals received at the TMS input to control
test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally
pulled to VDD_IO when it is not driven from an external source.
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to VDD_IO when it is not driven from an external source.
•
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDo. The data out of the
TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDo driver is set to a high impedance state.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
•
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to VDD_IO when it is not
driven from an external source. When JTAG is not in use, this pin must be tied low for normal operation.
The TAP signals are only applied when the ZL50075 is required to be in test mode. When in normal, non-test mode,
TRST must be connected low to disable the test logic. The remaining test pins may be left unconnected.
12.2 Instruction Register
The ZL50075 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG interface contains a
16-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP
controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDi and TDo during register scanning.
12.3 Test Data Register
As specified in the IEEE 1149.1 standard, the ZL50075 JTAG Interface contains three test data registers:
•
•
•
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50075 core logic.
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo.
The Device Identification Register - The JTAG device ID for the ZL50075 is C39B14BH
Version
<31:28>
<27:12>
<11:1>
<0>
0000
Part Number
Manufacturer ID
LSB
1100 0011 1001 1011
0001 0100 101
1
12.4 Boundary Scan Description Language (BSDL)
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
13.0 Memory Map of ZL50075
The memory map for the ZL50075 is given in Table 10.
Address (Hex)
Description
00000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 401FF
40200 - 4027F
40280 - 40283
40284 - 40287
40288 - 4028B
4028C - 4028F
40290- 7FFFF
Connection Memory
Connection Memory LSB
Data Memory: Read only; Bus error on write (BERR)
Input BER Enable Control Memory
Invalid Address. Access causes Bus error (BERR)
BER Counters
Group Control Registers
Input Clock Control Register
Output Clock Control Register
Block Init Register
Block Init Enable
Invalid Address. Access causes Bus error (BERR)
Table 10 - Memory Map
14.0 Detailed Memory and Register Descriptions
This section describes all the memories and registers that are used in this device.
14.1 Connection Memory
Address range 00000 - 1FFFF hex.
On power-up, all Connection Memory locations are initialized automatically to 00000000 hex, using the Block
Initialization feature, as described in Section 14.7 and Section 14.8.
The 32 bit Connection Memory has 32,768 locations. Each 32 bit long-word is used to program the desired source
data and any other per-channel characteristics of one output time-slot.
The memory map for the Connection Memory is sub-divided into 32 blocks, each corresponding to one of the
possible 32 output stream group numbers. The address ranges for these blocks are illustrated in Table 11.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Start
Address
(Hex)
Start
Address
(Hex)
Output
Group
Address Range
Output
Group
Address Range
(Hex)
(Hex)
0
1
2
3
4
5
6
7
8
000000
001000
002000
003000
004000
005000
006000
007000
008000
009000
00A000
00B000
00C000
00D000
00E000
00F000
000000 - 000FFF
001000 - 001FFF
002000 - 002FFF
003000 - 003FFF
004000 - 004FFF
005000 - 005FFF
006000 - 006FFF
007000 - 007FFF
008000 - 008FFF
009000 - 009FFF
00A000 - 00AFFF
00B000 - 00BFFF
00C000 - 00CFFF
00D000 - 00DFFF
00E000 - 00EFFF
00F000 - 00FFFF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
010000
011000
012000
013000
014000
015000
016000
017000
018000
019000
01A000
01B000
01C000
01D000
01E000
01F000
010000 - 010FFF
011000 - 011FFF
012000 - 012FFF
013000 - 013FFF
014000 - 014FFF
015000 - 015FFF
016000 - 016FFF
017000 - 017FFF
018000 - 018FFF
019000 - 019FFF
01A000 - 01AFFF
01B000 - 01BFFF
01C000 - 01CFFF
01D000 - 01DFFF
01E000 - 01EFFF
01F000 - 01FFFF
9
10
11
12
13
14
15
Table 11 - Connection Memory Group Address Mapping
The mapping of each output stream, SToAn and SToBn, depends on the programmed bit rate. The address offset
range for each stream is illustrated in Table 12.
Output Group Data Rate
Timeslot Range
Output Stream
Stream Address Offset Range (Hex)
65 Mbps
0 - 1023
SToAn
SToBn
SToAn
SToBn
SToAn
SToBn
BERR
SToAn
SToBn
BERR
00000 - 00FFF
N/A
32 Mbps
16 Mbps
0 - 511
0 - 255
00000 - 007FF
00800 - 00FFF
00000 - 003FF
00400 - 007FF
00800 - 00FFF
00000 - 001FF
00200 - 003FF
00400 - 00FFF
N/A
0 - 127
8 Mbps
N/A
Table 12 - Connection Memory Stream Address Offset at Various Output Rates
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
The address range for a particular stream is given by adding the group start address, as indicated in Table 11, to the
appropriate stream offset range, as indicated in Table 12. For example, the Connection Memory address range for
SToB12 operating at 32 Mbps is 00C800-00CFFF.
Each output channel timeslot occupies a range of 4 addresses in the Connection Memories. The timeslot address
offset is illustrated in Table 13. It shows the maximum number of timeslots that a stream can have, but the actual
number of timeslots available depends on the output data rates, as illustrated in Table 1 and Table 12.
Timeslot
SToAn
Address Offset
hex
SToBn
0
1
2
0
1
2
000
004
008
-
-
-
510
511
512
513
-
510
511
7F8
7FC
800
804
-
1021
1022
1023
FF4
FF8
FFC
Table 13 - Connection Memory Timeslot Address Offset Range
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
14.1.1 Connection Memory Bit Functions
The bit functions of the connection memory are illustrated in Table 14.
External Read/Write Address: 000000H
Reset Value: 0000H
31
30
29
28
V/D
12
27
26
25
24
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
PCF
2
PCF
1
PCF
0
ICL
1
ICL
0
OCL
1
OCL
0
15
0
14
13
11
10
9
8
7
6
5
4
3
2
1
0
GP
4
GP
3
GP
2
GP
1
GP
0
STCH
9
STCH
8
STCH
7
STCH STCH STCH
STCH
3
STCH STCH STCH
6
5
4
2
1
0
Bit
Name
Description
31 - 29
PCF2 - 0 Per Channel Function
PCF2 - 0
Function
Description
000
001
010
011
100
101
110
111
OT
FH
MSG
VAR
CD
PRBS
OT
OT
Output is tri-stated
Output drives high always
Output is in message mode
Variable delay connection mode
Constant delay connection mode
PRBS Generator
Output is tri-stated
Output is tri-stated
28
V/D
Voice/Data Control
When this bit is low, the corresponding channel is for voice.
When this bit is high, the corresponding channel is for data.
27 - 26
ICL1 - 0
Input Coding Law
Input Coding Law
ICL1 - 0
For Voice (V/D bit = 0)
For Data (V/D bit = 1)
00
01
10
11
CCITT.ITU A-Law
CCITT.ITU µ-Law
A-Law w/o ABI
No Code
ABI
Inverted ABI
All Bits Inverted
µ-Law w/o Mag. Inv
Table 14 - Connection Memory Bits (CMB)
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
External Read/Write Address: 000000H
Reset Value: 0000H
31
30
29
28
V/D
12
27
26
25
24
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
PCF
2
PCF
1
PCF
0
ICL
1
ICL
0
OCL
1
OCL
0
15
0
14
13
11
10
9
8
7
6
5
4
3
2
1
0
GP
4
GP
3
GP
2
GP
1
GP
0
STCH
9
STCH
8
STCH
7
STCH STCH STCH
STCH
3
STCH STCH STCH
6
5
4
2
1
0
Bit
Name
Description
25 - 24
OCL1 - 0 Output Coding Law
Output Coding Law
OCL1 - 0
For Voice (V/D bit = 0)
For Data (V/D bit = 1)
00
01
10
11
CCITT.ITU A-Law
CCITT.ITU µ-Law
A-Law w/o ABI
No Code
ABI
Inverted ABI
All Bits Inverted
µ-Law w/o Mag. Inv
23 - 15
14 - 10
9 - 0
Unused
GP4 - 0
Reserved. In normal functional mode, these bits MUST be set to zero.
Source Group Selection. These bits define the input/source group number (31 - 0)
Source Stream and Channel Selection / Message Mode Data
STCH
9 - 0
In connection mode (constant/variable delay), these bits define the input/source stream
and channel number, depending on the data rate.
For 65.536 Mbps, bits 9 - 0 select the input channel (0 - 1023).
For 32.768 Mbps, bits 9 - 1 select the input channel (0 - 511). Bit 0 selects stream STiA
(0) or STiB (1).
For 16.869 Mbps, bits 9 - 2 select the input channel (0 - 255). Bit 0 selects stream STiA
(0) or STiB (1). Bit 1 MUST be set to 0.
For 8.192 Mbps, bits 9 - 3 select the input channel (0 - 127). Bit 0 selects stream STiA (0)
or STiB (1). Bit 2-1 MUST be set to 00.
In message mode, bits 7 - 0 define the output data. The data is output sequentially with
bit 7 being output first. Bits 9 - 8 are not used.
Table 14 - Connection Memory Bits (CMB) (continued)
14.1.2 Connection Memory LSB
The Connection Memory Least Significant Byte field is provided to give a convenient alternative way to modify the
output data for a stream in message mode. In this memory address range, all of the connection memory least
significant bytes (bits 7 - 0) are available for read/write in consecutive address locations. This feature is provided for
programming convenience. It can allow higher programming bandwidth on message mode streams. For example,
one longword access to this memory space can read or set the message bytes in four consecutive connection
memory locations. Access to this memory space is big-endian, with the most significant bytes on the data bus
accessing the lower address of the connection memory. Addressing into each of the streams is illustrated in Table
15.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Start
Address
(Hex)
Start
Address
(Hex)
Output
Group
Address Range
Output
Group
Address Range
(Hex)
(Hex)
0
1
2
3
4
5
6
7
8
020000
020400
020800
020C00
021000
021400
021800
021C00
022000
022400
022800
022C00
023000
023400
023800
023C00
020000 - 0203FF
020400 - 0207FF
020800 - 020BFF
020C00 - 020FFF
021000 - 0213FF
021400 - 0217FF
021800 - 021BFF
021C00 - 021FFF
022000 - 0223FF
022400 - 0227FF
022800 - 022BFF
022C00 - 022FFF
023000 - 0233FF
023400 - 0237FF
023800 - 023BFF
023C00 - 023FFF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
024000
024400
024800
024C00
025000
025400
025800
025C00
026000
026400
026800
026C00
027000
027400
027800
027C00
024000 - 0243FF
024400 - 0247FF
024800 - 024BFF
024C00 - 024FFF
025000 - 0253FF
025400 - 0257FF
025800 - 025BFF
025C00 - 025FFF
026000 - 0263FF
026400 - 0267FF
026800 - 026BFF
026C00 - 026FFF
027000 - 0273FF
027400 - 0277FF
027800 - 027BFF
027C00 - 027FFF
9
10
11
12
13
14
15
Table 15 - Connection Memory LSB Group Address Mapping
Output Group Data Rate
Timeslot Range
Output Stream
Stream Address Offset Range (Hex)
65 Mbps
0 - 1023
SToAn
SToBn
SToAn
SToBn
SToAn
SToBn
BERR
SToAn
SToBn
BERR
00000 - 003FF
N/A
32 Mbps
16 Mbps
0 - 511
0 - 255
00000 - 001FF
00200 - 003FF
00000 - 000FF
00100 - 001FF
00200 - 003FF
00000 - 0007F
00080 - 000FF
00100 - 003FF
N/A
8 Mbps
0 - 127
N/A
Table 16 - Connection Memory LSB Stream Address Offset at Various Output Rates
Within each stream group, the mapping of each of the actual output streams, SToAn and SToBn, depends on the
output rate programmed into the Group Control Registers. The address offsets to these control areas for each of
the output streams are illustrated in Table 16.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
14.2 Data Memory
The data memory field is a read only address range used to monitor the data being received by the input streams.
Addressing into each of the streams is illustrated in Table 17.
Start
Address
(Hex)
Start
Address
(Hex)
Input
Group
Address Range
(Hex)
Input
Group
Address Range
(Hex)
0
1
2
3
4
5
6
7
8
028000
028400
028800
028C00
029000
029400
029800
029C00
02A000
02A400
02A800
02AC00
02B000
02B400
02B800
02BC00
028000 - 0283FF
028400 - 0287FF
028800 - 028BFF
028C00 - 028FFF
029000 - 0293FF
029400 - 0297FF
029800 - 029BFF
029C00 - 029FFF
02A000 - 02A3FF
02A400 - 02A7FF
02A800 - 02ABFF
02AC00 - 02AFFF
02B000 - 02B3FF
02B400 - 02B7FF
02B800 - 02BBFF
02BC00 - 02BFFF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
02C000
02C400
02C800
02CC00
02D000
02D400
02D800
02DC00
02E000
02E400
02E800
02EC00
02F000
02F400
02F800
02FC00
02C000 - 02C3FF
02C400 - 02C7FF
02C800 - 02CBFF
02CC00 - 02CFFF
02D000 - 02D3FF
02D400 - 02D7FF
02D800 - 02DBFF
02DC00 - 02DFFF
02E000 - 02E3FF
02E400 - 02E7FF
02E800 - 02EBFF
02EC00 - 02EFFF
02F000 - 02F3FF
02F400 - 02F7FF
02F800 - 02FBFF
02FC00 - 02FFFF
9
10
11
12
13
14
15
Table 17 - Data Memory Group Address Mapping
Within each stream group, the mapping of each of the actual input streams, STiAn and STiBn, depends on the input
rate programmed into the Group Control Registers. The address offsets to these data areas for each of the input
streams are illustrated in Table 18.
Input Group Data Rate Time-slot Range
Input Streams
Address Offset Range (Hex)
65 Mbps
32 Mbps
16 Mbps
0 - 1023
0 - 511
0 - 255
STiAn
STiBn
STiAn
STiBn
STiAn
STiBn
BERR
STiAn
STiBn
BERR
00000 - 003FF
N/A
00000 - 001FF
00200 - 003FF
00000 - 000FF
00100 - 001FF
00200 - 003FF
00000 - 0007F
00080 - 000FF
00100 - 003FF
N/A
8 Mbps
0 - 127
N/A
Table 18 - Data Memory Stream Address Offset at Various Output Rates
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
The address ranges for the data memory portion corresponding to each of the actual input streams, STiAn and
STiBn, for any particular input group number is calculated by adding the Start Address for the particular group, as
indicated in Table 17, to the appropriate Address Offset Range, as indicated in Table 18. The time-slots map linearly
into the appropriate address offset range. (i.e., timeslots 0, 1, 2,... map into addresses 00000, 00001, 00002,...)
The entire data memory is a read only structure. Any write attempts will result in a bus error. BERR is driven active
low to terminate the bus cycle.
14.3 BER Control Memory and Error Counters
14.3.1 Input BER Enable Control Memory
The BER Enable Control Memory (IBERECM) is a read/write memory block. Each memory location is used to
control the BER counter of one incoming timeslot. Addressing into each of the streams is illustrated in Table 19.
Start
Address
(Hex)
Start
Address
(Hex)
Input
Group
Address Range
(Hex)
Input
Group
Address Range
(Hex)
0
1
2
3
4
5
6
7
8
030000
030400
030800
030C00
031000
031400
031800
031C00
032000
032400
032800
032C00
033000
033400
033800
033C00
030000 - 0303FF
030400 - 0307FF
030800 - 030BFF
030C00 - 030FFF
031000 - 0313FF
031400 - 0317FF
031800 - 031BFF
031C00 - 031FFF
032000 - 0323FF
032400 - 0327FF
032800 - 032BFF
032C00 - 032FFF
033000 - 0333FF
033400 - 0337FF
033800 - 033BFF
033C00 - 033FFF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
034000
034400
034800
034C00
035000
035400
035800
035C00
036000
036400
036800
036C00
037000
037400
037800
037C00
034000 - 0343FF
034400 - 0347FF
034800 - 034BFF
034C00 - 034FFF
035000 - 0353FF
035400 - 0357FF
035800 - 035BFF
035C00 - 035FFF
036000 - 0363FF
036400 - 0367FF
036800 - 036BFF
036C00 - 036FFF
037000 - 0373FF
037400 - 0377FF
037800 - 037BFF
037C00 - 037FFF
9
10
11
12
13
14
15
Table 19 - BER Enable Control Memory Group Address Mapping
Each byte location of the BER Enable Memory contains one read/write BER counter enable (BCE) bit, mapped into
the D0 location. If the BCE bit is set, then the BER counter for the corresponding stream and timeslot is enabled for
the duration of that timeslot. If the BCE bit is cleared the counter is disabled.
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Zarlink Semiconductor Inc.
ZL50075
Data Sheet
Input Group Data Rate
Time-slot Range
Input Streams
Address Offset Range (Hex)
65 Mbps
0 - 1023
STiAn
STiBn
STiAn
STiBn
STiAn
STiBn
BERR
STiAn
STiBn
BERR
00000 - 003FF
N/A
32 Mbps
16 Mbps
0 - 511
0 - 255
00000 - 001FF
00200 - 003FF
00000 - 000FF
00100 - 001FF
00200 - 003FF
00000 - 0007F
00080 - 000FF
00100 - 003FF
N/A
0 - 127
8 Mbps
N/A
Table 20 - BER Enable Control Memory Stream Address Offset at Various Output Rates
14.3.2 BER Counters
There are a total of 64 Bit Error Counters, corresponding to the 64 serial input streams. Each count value is 32 bits
wide, but only the least significant 16 bits are used. The most significant 16 bits of the bit error counters will always
read back zero. A write operation to any byte of the counter, including the 16 most significant bits, will clear that
counter.
Each bit error counter contains the number of single bit errors detected on the corresponding stream, since the
counter was last cleared. If the number of bit errors detected exceeds 65535 (decimal), the counter will hold that
value until it is cleared.
BER Input Group
0
BER Input Stream
Start Address (Hex)
End Address (Hex)
STiA0
STiB0
N/A
40000
40080
BERR - 40100
40004
40003
40083
BERR - 40183
40007
1
2
STiA1
STiB1
N/A
40084
BERR - 40104
40008
40087
BERR - 40187
4000B
STiA2
STiB2
N/A
40088
BERR - 40108
4008B
BERR - 4018B
.
.
.
.
.
.
.
.
.
.
.
.
31
STiA31
STiB31
N/A
4007C
400FC
BERR - 4017C
4007F
400FF
BERR - 401FF
Table 21 - BER Counter Group and Stream Address Mapping
38
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
14.4 Group Control Registers
The ZL50075 addresses the issues of a simple programming model and automatic stream configuration by defining
a basic switching bit rate of 65.536 Mbps and by grouping the I/O streams. Each TDM I/O group contains 2 input
and 2 output streams. The 2 input streams in the same group have identical input characteristics, and similarly, the
2 output streams in the same group have identical output characteristics. However, input and output streams in the
same group can have different input and output operation characteristics.
The Group Control Registers are provided for setting the operating characteristics of the TDM input and output
streams. All of the Group Control Registers are mapped long-word aligned on 32 bit boundaries in the memory
space. Each of the 32 registers is used to control one group. The mapping of the Group Control Registers to the I/O
group numbers is illustrated in Table 22. The bit functions of each of the Group Control Registers are illustrated in
Table 23.
TDM Group
Group Control Register Address (Hex)
0
1
2
3
:
40200 - 40203
40204 - 40207
40208 - 4020B
4020C - 4020F
:
:
:
29
30
31
40274 - 40277
40278 - 4027B
4027C - 4027F
Table 22 - Group Control Register Addressing
External Read/Write Address: 40200H - 4027FH
Reset Value: 000C000CH
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
OSI
6
21
20
19
18
17
16
OSBA
1
OSBA
0
OSBR
1
OSBR
0
OSSRC
1
OSSRC
0
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
5
4
3
2
1
0
ISI
ISPD
4
ISPD
3
ISPD
2
ISPD
1
ISPD
0
ISBR
1
ISBR
0
ISSRC
1
ISSRC
0
Bit
Name
Description
31 - 23
22
Unused
OSI
Reserved. In normal functional mode, these bits MUST be set to zero.
Output Stream Inversion
For normal operation, this bit is set low.
To invert the output stream, set this bit high.
Table 23 - Group Control Register
39
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
External Read/Write Address: 40200H - 4027FH
Reset Value: 000C000CH
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
OSI
6
21
20
19
18
17
16
OSBA
1
OSBA
0
OSBR
1
OSBR
0
OSSRC
1
OSSRC
0
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
5
4
3
2
1
0
ISI
ISPD
4
ISPD
3
ISPD
2
ISPD
1
ISPD
0
ISBR
1
ISBR
0
ISSRC
1
ISSRC
0
Bit
Name
Description
21 - 20
OSBA1 - 0
Output Stream Bit Advancement
OSBA1 - 0
Non-65 Mbps
65 Mbps
00
01
10
11
0 ns
0 ns
3.8 ns
7.6 ns
11.4 ns
7.6 ns
15.2 ns
22.8 ns
19 - 18
OSBR1 - 0
Output Stream Bit Rate
Bit Rates Per Group
OSBR1 - 0
SToA
SToB
00
01
10
11
8.192 Mbps
16.384 Mbps
32.768 Mbps
65.536 Mbps
8.192 Mbps
16.384 Mbps
32.768 Mbps
Not Used
Unused streams are tri-stated.
If the internal system clock is used as the clock source, all the above data rates are
available. Otherwise, the data rate cannot exceed the selected clock source’s rate.
17 - 16
OSSRC1 - 0 Output Stream Clock Source Select
OSSRC1 - 0
Output Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
Reserved
Reserved
15 - 10
9
Unused
ISI
Reserved. In normal functional mode, these bits MUST be set to zero.
Input Stream Inversion
For normal operation, this bit is set low.
To invert the input stream, set this bit high.
8 - 4
ISPD4 - 0
Input Sampling Point Delay
Default Sampling Point is 3/4. Adjust according to Figure on page 18.
Table 23 - Group Control Register (continued)
40
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
External Read/Write Address: 40200H - 4027FH
Reset Value: 000C000CH
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
OSI
6
21
20
19
18
17
16
OSBA
1
OSBA
0
OSBR
1
OSBR
0
OSSRC
1
OSSRC
0
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
5
4
3
2
1
0
ISI
ISPD
4
ISPD
3
ISPD
2
ISPD
1
ISPD
0
ISBR
1
ISBR
0
ISSRC
1
ISSRC
0
Bit
Name
Description
3 - 2
ISBR1 - 0
Input Stream Bit Rate
Bit Rates Per Group
ISBR1 - 0
STiA
STiB
00
01
10
11
8.192 Mbps
16.384 Mbps
32.768 Mbps
65.536 Mbps
8.192 Mbps
16.384 Mbps
32.768 Mbps
Not Used
Unused streams must be connected to ground.
If the internal system clock is used as the clock source, all the above data rates are
available. Otherwise, the data rate cannot exceed the selected clock source’s rate.
1 - 0
ISSRC1 - 0
Input Stream Clock Source Select
ISSRC1 - 0
Input Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
Reserved
Reserved
Table 23 - Group Control Register (continued)
The Group Control Register is a static control register. Changes to bit settings may disrupt data flow on the selected
port for a maximum of 2 frames.
41
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
14.5 Input Clock Control Register
The Input Clock Control Register is used to select the logic sense of the input clock.
External Read/Write Address: 40280H
Reset Value: 0DBH
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
1
6
1
5
0
4
1
3
1
2
1
0
GCI
FPI
CKI
SEL0
POL0
POL0
Bit
Name
Description
31 - 9
8 - 3
2
Unused
Unused
Reserved. In normal functional mode, these bits MUST be set to zero.
Reserved. In normal functional mode, these bits MUST be set to 011011.
GCISEL0 GCI-Bus Selection for FPi0
When this bit is low, FPi0 is set for ST-BUS mode.
When this bit is high, FPi0 is set for GCI-Bus mode.
1
0
FPIPOL0 Frame Pulse Polarity Selection for FPi0
When this bit is low, FPi0 is set for active high.
When this bit is high, FPi0 is set for active low.
CKIPOL0 Clock Polarity Selection for CKi0
When this bit is low, CKi0 is set for the positive clock edge.
When this bit is high, CKi0 is set for the negative clock edge.
Table 24 - Input Clock Control Register
42
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
14.6 Output Clock Control Register
The Output Clock Control Register is used to select the desired source, frequency, and logic sense of the output
clocks. The bit functions of the Output Clock Control Register are illustrated in Table 25.
External Read/Write Address: 40284H
Reset Value: 060D1C3CH
31
0
30
0
29
0
28
0
27
0
26
1
25
1
24
0
23
0
22
0
21
0
20
0
19
1
18
1
17
0
16
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GCO
SEL1
FPO
CKO
CKO1
CKO1
CKO1
CKO1
SRC0
GCO
SEL0
FPO
CKO
CKO0
CKO0 CKO0 CKO0
0
0
POL1
POL1
RATE1 RATE0 SRC1
POL0
POL0
RATE1 RATE0 SRC1 SRC0
Bit
Name
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
31 - 28
27 - 14
13
Unused
Unused
Reserved. In normal functional mode, these bits MUST be set to 01100000110100.
GCO
SEL1
GCI-Bus Selection for FPo1
When this bit is low, FPo1 is set for ST-BUS mode.
When this bit is high, FPo1 is set for GCI-Bus mode.
12
11
FPO
Frame Pulse Polarity Selection for FPo1
When this bit is low, FPo1 is set for active high.
When this bit is high, FPo1 is set for active low.
POL1
CKO
Clock Polarity Selection for CKo1
POL1
When this bit is low, CKo1 is set for the positive clock edge.
When this bit is high, CKo1 is set for the negative clock edge.
10 - 9
CKO1
RATE
1 - 0
Output Clock Rate for CKo1 and FPo1
The output clock rate can not exceed the selected clock source rate. All rates are avail-
able when the internal system clock is selected as clock source.
CKO1RATE1 - 0
CKo1
FPo1
00
01
10
11
8.192 MHz
16.384 MHz
32.768 MHz
65.536 MHz
120 ns
60 ns
30 ns
15 ns
8 - 7
CKO1
SRC
1 - 0
Output Clock Source for CKo1 and FPo1
CKO1SRC1 - 0
Output Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
Reserved
Reserved
Table 25 - Output Clock Control Register
43
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
External Read/Write Address: 40284H
Reset Value: 060D1C3CH
31
0
30
0
29
0
28
0
27
0
26
1
25
1
24
0
23
0
22
0
21
0
20
0
19
1
18
1
17
0
16
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GCO
SEL1
FPO
CKO
CKO1
CKO1
CKO1
CKO1
SRC0
GCO
SEL0
FPO
CKO
CKO0
CKO0 CKO0 CKO0
0
0
POL1
POL1
RATE1 RATE0 SRC1
POL0
POL0
RATE1 RATE0 SRC1 SRC0
Bit
Name
Description
6
GCO
SEL0
GCI-Bus Selection for FPo0
When this bit is low, FPo0 is set for ST-BUS mode.
When this bit is high, FPo0 is set for GCI-Bus mode.
5
4
FPO
Frame Pulse Polarity Selection for FPo0
When this bit is low, FPo0 is set for active high.
When this bit is high, FPo0 is set for active low.
POL0
CKO
Clock Polarity Selection for CKo0
POL0
When this bit is low, CKo0 is set for the positive clock edge.
When this bit is high, CKo0 is set for the negative clock edge.
3 - 2
CKO0
RATE
1 - 0
Output Clock Rate for CKo0 and FPo0
The output clock rate can not exceed the selected clock source rate. All rates are avail-
able when the internal system clock is selected as clock source.
CKO0RATE1 - 0
CKo0
FPo0
00
01
10
11
8.192 MHz
16.384 MHz
32.768 MHz
65.536 MHz
120 ns
60 ns
30 ns
15 ns
1 - 0
CKO0
SRC
1 - 0
Output Clock Source for CKo0 and FPo0
CKO0SRC1 - 0
Output Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
Reserved
Reserved
Table 25 - Output Clock Control Register (continued)
44
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
14.7 Block Init Register
The Block Init Register is a 32 bit read/write register at address 040288 - 04028BH.
The Block Init Register is used during block initialization of the connection memory. A block initialization
automatically occurs at power-up. However, it is possible to perform a block initialization at any time. During Block
Initialization, the value of the Block Init Register is copied to all connection memory locations in an operation that
runs in about 120 µs. If the Block Init Register is modified during a block initialization, the new value used is
ignored.
14.8 Block Init Enable Register
The Block Init Enable Register is a 32 bit read/write register at address 04028C - 04028FH.
The Block Init Enable Register is used to initiate a block initialization of the connection memory. A block initialization
automatically occurs at power-up. Since the Block Init Register is cleared at power-up this automatic block
initialization will write all zeros to all Connection Memory Bits. However, it is possible to perform a block initialization
at any time. To begin a block initialization, the hex value 31415926 must be written to the Block Init Enable Register.
If a block initialization is signaled while one is in progress, the signal is ignored, and the currently active block
initialization is allowed to complete.
The value read back from the Block Init Enable Register is different from the value written. It represents both the
block initialization status, and the power-up reset initialization status. The meaning of the initialization status bits is
illustrated in Table 26. The bits 31 - 2 always read back 0.
Bit
Name
Description
0
Block Init Status
0 if Block initialization is completed;
1 if Block initialization is in progress
1
Reset Init Status
0 if Reset initialization is completed
1 if Reset initialization is in progress
Table 26 - Block and Power-up Initialization Status Bits
Any access to the connection memory or the data memory during a block initialization or a reset initialization will
result in a bus error, BERR. All TDM outputs are tri-stated during any block initialization.
45
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
15.0 DC/AC Electrical Characteristics
Absolute Maximum Ratings1 - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.2
Max.
Unit
1
2
3
Chip I/O Supply Voltage
VDD_IO
VDD_CORE
VI_3V
-0.5
-0.5
-0.5
5.0
5.0
V
V
V
Chip Core Supply Voltage
Input Voltage (non-5 V tolerant inputs)
VDD_IO
0.5
+
4
5
6
7
Input Voltage (5 V tolerant inputs)
Continuous Current at digital outputs
Package power dissipation
Storage temperature
VI_5V
Io
-0.5
7.0
15
V
mA
W
PD
TS
2.1
- 55
+125
°C
Note 1: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Note 2: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Operating Temperature
Sym.
Min.
Typ.1
Max.
Unit
1
2
3
4
5
TOP
VDD_CORE
VDD_IO
VI_3V
-40
1.71
3.0
0
25
1.8
3.3
+85
1.89
3.6
°C
V
Positive Supply Core
Positive Supply I/O
V
Input Voltage (non-5 V tolerant inputs)
Input Voltage (5 V tolerant inputs)
VDD_IO
5.5
V
VI_5V
0
Note 1: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
46
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.1
Max.
Unit
Test Conditions
1
2
3
4
5
6
7
8
9
Core Supply Current2
IDD_CORE
IDD_IO
IDDQ
PDD
VIH
500
62
mA
mA
µA
W
I/O Supply Current
Outputs Unloaded
Outputs Unloaded
Leakage Current
105
Dynamic Power Dissipation
Input High Voltage
1.2
2.0
V
Input Low Voltage
VIL
0.8
5
V
Input Leakage-input pins3
Input Leakage-bidirectional pins
Pull-up Current
IIL
µA
µA
µA
µA
pF
V
0≤<VI ≤VDD_IO
0≤<VI ≤VDD_IO
Input at 0 V
IBL
5
IPU
-33
33
3
10 Pull-down Current
11 Input Pin Capacitance
12 Output High Voltage
13 Output Low Voltage
IPD
Input at VDD_IO
CI
VOH
VOL
2.4
IOH = 8 mA
IOL = 8 mA
0.4
V
Note 1: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
Note 2: StoA = 65 Mbps with random patterns. CKo0 = 65 MHz, CKo1 = 32 MHz.
Note 3: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (Vin).
AC Electrical Characteristics1 - Timing Parameter Measurement Voltage Levels - Voltages are with respect to ground
(VSS) unless otherwise stated.
Characteristics
CMOS Threshold
Sym.
Level
Unit
Test Conditions
1
2
3
VCT
VHM
VLM
0.5 VDD_IO
0.7 VDD_IO
0.3 VDD_IO
V
V
V
Rise/Fall Threshold Voltage High
Rise/Fall Threshold Voltage Low
1. Characteristics are over recommended operating conditions unless otherwise stated.
47
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
AC Electrical Characteristics1 - FPi0 and CKi0 Timing
No.
Characteristic (Figure 11)
Sym.
Min.
Typ.2
Max.
Units
Notes
1
FPi0 Input Frame Pulse Setup
Time
tFPIS
3
3
12
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKi0= 65.536 MHz
CKi0 = 32.768 MHz
CKi0 = 16.384 MHz
CKi0 = 8.192 MHz
CKi0= 65.536 MHz
CKi0 = 32.768 MHz
CKi0 = 16.384 MHz
CKi0 = 8.192 MHz
CKi0= 65.536 MHz
CKi0 = 32.768 MHz
CKi0 = 16.384 MHz
CKi0 = 8.192 MHz
65.536 MHz
3
55
3
115
12
2
3
4
FPi0 Input Frame Pulse Hold Time
FPi0 Input Frame Pulse width
tFPIH
tFPIW
tCKIP
2
2
25
2
55
2
115
24
5
5
50
5
110
230
15.5
31
5
CKi0 Input Clock Period (average
value, does not consider the
effects of jitter)
15
30
60
120
4
15.26
30.5
61.0
122
32.768 MHz
62
16.384 MHz
124
8.192 MHz
5
6
7
CKi0Input Clock High Time
CKi0 Input Clock Low Time
CKi0 Input Clock Rise/Fall Time
tCKIH
tCKIL
trCKI
4
,
0
6
2
tfCKI
tCVC
8
CKi0 Input Clock Cycle to Cycle
Variation
ns p-p Standard rating3.
STi at 65 Mbps
4
ns p-p Standard rating3.
STi at 32 Mbps
10
20
ns p-p Standard rating3.
STi at 16 Mbps
ns p-p Standard rating3.
STi at 8 Mbps
20%of
tCKIP
p-p
Extended rating.
With alternate clock
source4 or high
CKi0 rate5
Note 1: Characteristics are over recommended operating conditions unless otherwise stated.
Note 2: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
Note 3: When using internal APLL clock source and the CKi0 frequency is less than or equal to the data rate.
Note 4: When using input clock source CKi0 instead of the internal APLL clock source.
Note 5: When using internal APLL clock source and the CKi0 frequency is higher than or equal to twice the data rate.
48
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
tFPIW
FPi
tFPIS
tFPH
tCKIP
tCKIH
tCKIL
CKi
trCKI
tfCKI
Input Frame Boundary
Figure 11 - Frame Pulse Input and Clock Input
49
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
AC Electrical Characteristics1 - FPO0-1 and CKO0-1 (65.536 MHz) Timing
No.
Characteristic
Sym.
Min.
Typ.2
Max.
Units
Notes3
1
FPO0 Output Frame Pulse Setup
Time
tFPOS
5.5
9.5
ns
CL=30 pF
2
3
FPO0 Output Frame Pulse Hold
Time
tFPOH
tCKOP
5.5
9.5
ns
ns
CL=30 pF
CL=30 pF
CKO0 Output Clock Period
14.5
15.5
AC Electrical Characteristics1 - FPO0-1 and CKO0-1 (32.768 MHz) Timing
No.
Characteristic
Sym.
Min.
Typ.2
Max.
Units
Notes3
1
FPO0 Output Frame Pulse Setup
Time
tFPOS
14.0
16.5
ns
CL=30 pF
CL=30 pF
CL=30 pF
2
3
FPO0 Output Frame Pulse Hold
Time
tFPOH
tCKOP
14.0
30.0
16.5
31.0
ns
ns
CKO0 Output Clock Period
AC Electrical Characteristics1 - FPO0-1 and CKO0-1 (16.384 MHz) Timing
No.
Characteristic
Sym.
Min.
Typ.2
Max.
Units
Notes3
1
FPO0 Output Frame Pulse Setup
Time
tFPOS
29.0
31.0
ns
CL=30 pF
CL=30 pF
CL=30 pF
2
3
FPO0 Output Frame Pulse Hold
Time
tFPOH
tCKOP
29.0
60.5
31.0
61.5
ns
ns
CKO0 Output Clock Period
AC Electrical Characteristics1 - FPO0-1 and CKO0-1 (8.192 MHz) Timing
No.
Characteristic
Sym.
Min.
Typ.2
Max.
Units
Notes3
1
FPO0 Output Frame Pulse Setup
Time
tFPOS
60.0
62.0
ns
ns
ns
CL=30 pF
CL=30 pF
CL=30 pF
2
3
FPO0 Output Frame Pulse Hold
Time
tFPOH
tCKOP
60.0
62.0
CKO0 Output Clock Period
121.5
122.5
Note 1: Characteristics are over recommended operating conditions unless otherwise stated.
Note 2: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
Note 3: CKo clock source set to internal 131 MHz APLL, and CKi0 and FPi0 meet all the timing requirements.
Note 4: When CKo source is set to one of the CKi/FPi, its output timings directly follow its source.
50
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
FPo0
CKo0
tFPOS
tFPOH
tCKOP
Output Frame Boundary
Figure 12 - ST-Bus Frame Pulse and Clock Output Timing
FPo0
CKo0
tFPOS
tFPOH
tCKOP
Output Frame Boundary
Figure 13 - GCI Frame Pulse and Clock Output Timing
AC Electrical Characteristics - Output Clock Jitter Generation
No.
Characteristic
Max.
Units
Notes1,2
1
2
3
4
Jitter at CKO0-1 (8.192 MHz)
Jitter at CKO0-1 (16.384 MHz)
Jitter at CKO0-1 (32.768 MHz)
Jitter at CKO0-1 (65.536 MHz)
1050
1030
920
ps-pp
ps-pp
ps-pp
ps-pp
810
Note 1: CKi at 8 MHz, output clock source set to internal APLL. No jitter presented on the the Cki0 input.
Note 2: For 65.536 MHz output clock, the total loading on the output should not be larger than 10pF.
51
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
AC Electrical Characteristics1 - Serial Data Timing2 to CKi
No.
Characteristic (Figure 14)
Sym. Min. Typ.3
Max.
Units
Notes4
1
CKi to CKo Positive edge
Propagation Delay
tCKDP
3.5
8
ns
CKo clock source =
CKi
4.1
9.2
ns
CKo Clock source =
Internal 131 MHz
APLL output
2
CKi to CKo Negative edge
Propagation Delay
tCKDN
4.5
5
9.2
ns
ns
CKo clock source =
CKi
10.1
CKo Clock source =
Internal 131 MHz
APLL output
3
4
5
6
7
STi to posedge CKi setup
STi to posedge CKi hold
STi to negedge CKi setup
STi to negedge CKi hold
tSIPS
tSIPH
tSINS
tSINH
-0.8
5.9
-0.8
5.9
4.8
4.1
5.8
4.5
4.3
4.6
5.3
5.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Posedge CKi to Output Data Valid tSIPV
11.6
13.7
12.9
14.8
14.6
14.5
13
SToA5
SToB5
SToA5
SToB5
SToA5
SToB5
SToA5
SToB5
8
9
Negedge CKi to Output Data Valid tSINV
Posedge CKi to Output Data
tri-state
tSIPZ
tSINZ
tSOZ
10
11
Negedge CKi to Output Data
tri-state
13.6
10
ODE to Output Data tri-state
SToA
CL = 30 pF, RL = 1 K5
11
ns
SToB
CL = 30 pF, RL = 1 K5
12
ODE to Output Data Enable
tSOE
4.5
6
15
20
ns
ns
SToA5
SToB5
Note 1: Characteristics are over recommended operating conditions unless other wise stated.
Note 2: All of these specifications refer to ST-BUS inputs and outputs with clock source set to CKi.
Note 3: Typical figures are at 25°C, V
at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing. DD_CORE
Note 4: Loads on all serial outputs set to 30 pF.
Note 5: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge
CL.
52
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
FPi
(negative sense)
t
CKDN
CKo
(negative sense)
CKi
(negative sense)
tSINS
tSINH
STin
*
tSINV
VALID DATA
STon
STon
tSINZ
tSOZ
ODE
tSOE
FPi
(negative sense)
t
CKDP
CKo
(positive sense)
CKi
(positive sense)
tSIPS
tSIPH
STin
*
VALID DATA
tSIPV
STon
STon
tSIPZ
Note 1 : CKi frequency is assumed to be twice of the STin data rate, so that the sampling point is at the
3/4 point of the bit cell, or 1 1/2 clock period after the active clock edge
Note 2 : If CKi frequency is the same as the STin data rate, the sampling point moves to the 1/2 point of
the bit cell, or 1/2 clock period after the active clock edge.
Figure 14 - Serial Data Timing to CKi
53
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
AC Electrical Characteristics - Serial Data Timing1 to CKo2
No.
Characteristic (Figure 15)
Sym. Min. Typ.3 Max. Units
Notes4
1
2
3
4
5
STi to posedge CKo setup
STi to posedge CKo hold
STi to negedge CKo setup
STi to negedge CKo hold
Posedge CKo to Output Data Valid
tSOPS
tSOPH -2.0
tSONS 7.3
tSONH -2.0
7.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSOPV
0.1
0
2.7
4.6
1.7
3.7
4.9
5.1
4.7
4.8
1.2
SToA4
SToB4
SToA4
SToB4
SToA4
SToB4
SToA4
SToB4
6
7
8
9
Negedge CKo to Output Data Valid
Posedge CKo to Output Data tri-state
Negedge CKo to Output Data tri-state
CKo1 to CKo0 skew
tSONV -1.2
-1.6
tSOPZ
tSONZ
tCKOS
0.9
0.1
0.4
0
Note 1: Data Capture points vary with respect to CKo edge depending on clock rates & fractional delay settings.
Note 2: All of these specifications refer to ST-BUS inputs, ST-BUS outputs and CKo outputs set to internal clock source.
Note 3: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
Note 4: Loads on all serial outputs set to 30 pF.
54
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
CKo0
CKo1
t
CKOS
FPo
(negative sense)
CKo
(negative sense)
tSONS
tSONH
STin
*
VALID DATA
tSONV
STon
STon
tSONZ
FPo
(negative sense)
CKo
(positive sense)
tSOPS
tSOPH
STin
STon
STon
*
tSOPV
VALID DATA
tSOPZ
Note 1 : CKo frequency is assumed to be twice of the STin data rate, so that the sampling point is at the
3/4 point of the bit cell, or 1 1/2 clock period after the active clock edge
Note 2 : If CKo frequency is the same as the STin data rate, the sampling point moves to the 1/2 point of
the bit cell, or 1/2 clock period after the active clock edge.
Figure 15 - Serial Data Timing to CKo
55
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
AC Electrical Characteristics - Microprocessor Bus Interface
No
Characteristics (Figure , & Figure 17)
Sym. Min. Typ.1 Max. Units
Notes
tDSRE
tCSRE
tCSS
1
2
3
4
5
6
DS Recovery
5
0
0
0
0
0
ns
ns
ns
ns
ns
ns
CS Recovery
CS asserted setup to DS asserted
Address, SIZ1-0, R/W setup to DS asserted
CS hold from DS deasserted
tADS
tCSH
tADH
Address, SIZ0-1, R/W hold from DS
deasserted
tDSR
tDZ
7
8
Data valid to DTA asserted on read
0
ns
ns
CL = 50 pF,
RL = 1 k2
CS deasserted to Data tri-stated on read
5
9
CL = 50 pF,
RL = 1 k2
tWDS
9
Data setup to DS asserted on write
CS asserted to WAIT deasserted
0
0
ns
ns
tCSWA
10
CL = 30 pF,
RL = 1K2
tDHW
tWDD
11
12
Data hold from DTA asserted on write
DS asserted to WAIT Asserted
ns
ns
9
10
155
75
7
CL = 50 pF,
RL = 1 k2
tAKS
tAKD
13
14
WAIT deasserted to DTA/BERR asserted
skew
0
ns
ns
ns
ns
ns
ns
ns
CL = 50 pF,
RL = 1 k2
DS asserted to DTA Asserted
35
50
Connection
Memory
All other
registers
tAKH
tDTHZ
tWAHZ
15
16
17
DS deasserted to DTA Deasserted
CS deasserted to DTA tri-stated
CS deasserted to WAIT tri-stated
CL = 30 pF,
RL = 1 K2
13
6
CL = 30 pF,
RL = 1 K2
CL = 30 pF,
RL = 1 K2
tDSK
18
19
BE or UDS/LDS skew
20
tBEDS
BE or UDS/LDS to DS set-up
0
Note 1: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge
CL.
56
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
tDSRE
DS
CS
tCSRE
tCSS
tCSH
tADH
tADS
VALID
A18-A0
RWN,SIZ
tDZ
D31-D0
READ
VALID READ DATA
tWDS
VALID WRITE DATA
D31-D0
WRITE
tDTHZ
Hi-Z
tDSR
tDHW
Hi-Z
DTA
BERR
tAKD
tAKH
tAKS
tCSWA
tWDD
tWAHZ
Hi-Z
Hi-Z
WAIT
Figure 16 - Microprocessor Bus Interface Timing
tDSRE
DS
tBEDS
SIZ1-SIZ0
(BE1-BE0 or
UDS, LDS)
tDSK
Figure 17 - Intel Mode Timing
57
Zarlink Semiconductor Inc.
ZL50075
Data Sheet
AC Electrical Characteristics1 - IEEE 1149.1 Test Port and PWR Pin Timing
No.
Characteristic (Figure 18)
TCK Clock Period
Sym.
Min. Typ.2 Max.
Units
Notes
1
2
tTCKP
tTCKF
tTCKH
tTCKL
tTMSS
tTMSH
tTDIS
100
10
20
20
10
10
20
60
20
20
20
ns
MHz
ns
TCK Clock Frequency
TCK Clock Pulse Width High
TCK Clock Pulse Width Low
TMS Set-up Time
3
4
ns
5
ns
6
TMS Hold Time
ns
7
TDi Input Set-up Time
TDi Input Hold Time
TDo Output Delay
ns
8
tTDIH
ns
9
tTDOD
tTRSTW
tTPWR
ns
CL = 30 pF
10
11
TRST pulse width
ns
PWR pulse width
ns
Note 1: Characteristics are over recommended operating conditions unless otherwise stated.
Note 2: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
tTCKL
tTCKH
tTCKP
TCK
TMS
tTMSH
tTMSS
tTDIS
tTDIH
TDi
tTDOD
TDo
tTRSTW
TRST
tTPWR
PWR
Figure 18 - IEEE 1149.1 Test Port & PWR Reset Timing
58
Zarlink Semiconductor Inc.
Package Code
c
Zarlink Semiconductor 2003 All rights reserved.
Previous package codes
1
ISSUE
ACN
15 Jul 03
DATE
APPRD.
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