ZL50410GDG [ZARLINK]
Interface Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, MO-192, LBGA-208;
| 型号： | ZL50410GDG |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Interface Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, MO-192, LBGA-208 以太网 局域网（LAN）标准 |
| 文件： | 总138页 (文件大小：1408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL50410
Managed 8-Port 10/100M +
1-Port 10/100/1000M Ethernet Switch
Data Sheet
December 2004
Features
•
Integrated Single-Chip 10/100/1000 Ethernet
Switch
Ordering Information
•
•
•
Eight 10/100 Mbps auto-negotiating Fast
ZL50410GDC208 Pin LBGA
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
One 10/100/1000 Mbps auto-negotiating port
with GMII & MII interface options, that can be
used as a WAN uplink or as a 9th port
a 10/100 Mbps Fast Ethernet (FE) CPU port
with Reverse MII interface option
-40°C to +85°C
•
•
VLAN Support
•
•
•
Supports port-based VLAN and tagged-based
VLAN (IEEE 802.1Q), up to 4 K VLANs
Supports both shared VLAN learning (SVL)
and independent VLAN learning (IVL)
•
•
Operates stand-alone or can be cascaded with a
second ZL50410 to reach 16 ports
Embedded 2 Mbits (256 KBytes) internal memory
Supports Private VLAN Edge (Protected Ports)
•
supports up to 4 K byte frames
CPU access supports the following interface
options:
•
L2 switching
•
•
•
MAC address self learning, up to 4 K MAC
addresses using internal table
Supports IP Multicast with IGMP snooping, up
to 4 K IP Multicast groups
Supports the following spanning standards
•
8/16-bit parallel and Serial+MII interface in
managed mode
Serial interface in lightly managed mode, or in
unmanaged mode with optional I2C EEPROM
interface
•
-
-
IEEE 802.1D spanning tree
IEEE 802.1w rapid spanning tree
•
Failover Features
•
Rapid link failure detection using
hardware-generated heartbeat packets
•
Supports Ethernet multicasting and
broadcasting and flooding control
8/16-bit
or
Serial
C
P
U
ZL50410
10/100/
GMII / MII
MII
1000
PHY
8-Port 10/100M + 1G
Ethernet Switch
EEPROM
RMII / MII / GPSI
Quad
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50410
Data Sheet
•
link failover in less than 50 ms
•
Rate Control (both ingress and egress)
•
•
•
Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement)
Smooth out traffic to uplink port
Ingress Rate Control
-
-
-
Back pressure
Flow Control
WRED (Weighted Random Early Discard)
•
•
Egress Rate Control
Down to 16 kbps Rate Control granularity
•
•
Per queue traffic shaper on uplink port
Packet Filtering and Port Security
•
•
•
•
Static address filtering for source and/or destination MAC
Static MAC address not subject to aging
Secure mode freezes MAC address learning (each port may independently use this mode)
Supports port authentication (IEEE 802.1x)
•
QoS Support
•
Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for uplink port), with
strict priority and/or WFQ service disciplines
•
•
•
•
Provides 2 levels of dropping precedence with WRED mechanism
User controls the WRED thresholds.
Buffer management: per class and per port buffer reservations
Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID
•
•
Supports per-system option to enable flow control for best effort frames even on QoS enabled ports
Classification based on:
•
•
•
•
Port based priority
VLAN Priority field in VLAN tagged frame
DS/TOS field in IP packet
UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
•
•
The precedence of the above classifications is programmable
Supports IEEE 802.3ad link aggregation
•
•
•
Up to 8 trunk groups, with up to 8 ports per group
Allows trunking of ports located on cascaded chip
Supports load sharing among trunk ports based on:
-
-
Source port
Source and/or destination MAC address
•
•
•
•
•
•
•
•
Supports module hot swap on all ports
MIB Statistics counters for all ports
Full Duplex Ethernet IEEE 802.3x Flow Control
Backpressure flow control for Half Duplex ports
Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports
Built-in reset logic triggered by system malfunction
Built-In Self Test for internal SRAM
IEEE-1149.1 (JTAG) test port
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Description
The ZL50410 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 8 ports at 10/100 Mbps, 1 uplink port at 10/100/1000 Mbps, and a CPU interface for managed, lightly
managed and unmanaged switch applications. The chip supports up to 4 K MAC addresses and up to 4 K
tagged-based Virtual LANs (VLANs). It also supports the Private VLAN Edge feature, allowing the ability to set up
protected ports in a tagged-based VLAN system.
With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50410 provides
powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission
priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission
priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or
the UDP/TCP logical port fields in IP packets. The ZL50410 recognizes a total of 16 UDP/TCP logical ports, 8
hard-wired and 8 programmable (including one programmable range).
The ZL50410 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure
to the CPU. The CPU can then failover that link to an alternate link.
The ZL50410 supports up to 8 groups of port trunking/load sharing. Each group can contain up to 8 ports. Port
trunking/load sharing can be used to group ports between interlinked switches to increase the effective network
bandwidth.
In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50410 also supports a per-system
option to enable flow control for best effort frames, even on QoS-enabled ports.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.
SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network
management solution.
The ZL50410 is fabricated using 0.18 micron technology. The ZL50410 is packaged in a 208-pin Ball Grid Array
package.
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Table of Contents
1.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Power and Ground Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Ball Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Signal Mapping and Internal pull-up/Down Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5 Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.1 Recommended Default Boostrap Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6 Default Switch Configuration and Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1 Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2 MAC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1 RMII MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1.1 GPSI (7WS) Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.2 CPU MAC Module (CMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.3 MII MAC Module (MMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.4 PHY Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Management Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 Heartbeat Packet Generation and Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7 Timeout Reset Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.0 Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Register Configuration, Frame Transmission, and Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1 Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.2 Rx/Tx of Standard Ethernet Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.3 Control Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.2 Read Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.0 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Search, Learning, and Aging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4 MAC Address Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Table of Contents
5.8 Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.9 Port Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.5 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2.6 TxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 Two QoS Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.1 Strict Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.2 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4 Shaper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.5 Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6 Buffer Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6.1 Dropping When Buffers Are Scarce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.7 Flow Control Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.7.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.7.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.8 Mapping to IETF Diffserv Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.9 Failover Backplane Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.0 Traffic Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2 Using port mirroring for loop back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.0 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1.1 System Clock (SCLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1.2 RMAC Reference Clock (M_CLK) speed requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1.3 MMAC Reference Clock (REF_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1.4 JTAG Test Clock (TCK) speed requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2.1 MDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2.3 Ethernet Interface Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.0 Hardware Statistics Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.2 IEEE 802.3 HUB Management (RFC 1516) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.1.3 FCSErrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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11.2.1.5 FrameTooLongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.1.6 ShortEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.1.7 Runts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.1.8 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.1.9 LateEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.1.10 VeryLongEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.1.11 DataRateMisatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.1.12 AutoPartitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.1.13 TotalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3 IEEE 802.1 Bridge Management (RFC 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1.1 InFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1.2 OutFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1.3 InDiscards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1.4 DelayExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1.5 MtuExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.4 RMON – Ethernet Statistic Group (RFC 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.4.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.4.1.1 Drop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.4.1.2 Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.4.1.3 BroadcastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.4.1.4 MulticastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.4.1.5 CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.4.1.6 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.4.1.7 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.4.1.8 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.4.1.9 Jabbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.4.1.10 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.4.1.11 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.0 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.1 ZL50400 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.2.2 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.2.3 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.2.4 COMMAND&STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.2.5 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.2.6 Control Command Frame Buffer1 Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.2.7 Control Command Frame Buffer2 Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.3 Indirectly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.3.1 (Group 0 Address) MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.3.1.1 ECR1Pn: Port n Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.3.1.2 ECR2Pn: Port n Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.3.1.3 ECR3Pn: Port n Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.3.1.4 ECR4Pn: Port n Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.3.1.5 BUF_LIMIT – Frame Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.3.1.6 FCC – Flow Control Grant Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.3.2 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.2.1 AVTCL – VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.2.2 AVTCH – VLAN Type Code Register High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.2.3 PVMAP00_0 – Port 0 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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12.3.2.4 PVMAP00_1 – Port 0 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.2.5 PVMAP00_3 – Port 0 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.2.6 PVMAPnn_0,1,3 – Ports 1~9 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.3.2.7 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.3.3 (Group 2 Address) Port Trunking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.3.3.1 TRUNKn– Trunk Group 0~7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.3.3.2 TRUNKn_HASH10 – Trunk group n hash result 1/0 destination port number . . . . . . . . . . . 74
12.3.3.3 TRUNKn_HASH32 – Trunk group n hash result 3/2 destination port number . . . . . . . . . . . 74
12.3.3.4 TRUNKn_HASH54 – Trunk group n hash result 5/4 destination port number . . . . . . . . . . . 75
12.3.3.5 TRUNKn_HASH76 – Trunk group n hash result 7/6 destination port number . . . . . . . . . . . 75
Multicast Hash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.3.3.6 MULTICAST_HASHn-0 – Multicast hash result 0~7 mask byte 0 . . . . . . . . . . . . . . . . . . . . 76
12.3.3.7 MULTICAST_HASHn-1 – Multicast hash result 0~7 mask byte 1 . . . . . . . . . . . . . . . . . . . . 76
12.3.4 (Group 3 Address) CPU Port Configuration Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.3.4.1 MAC0 – CPU MAC address byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.3.4.2 MAC1 – CPU MAC address byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.3.4.3 MAC2 – CPU MAC address byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.3.4.4 MAC3 – CPU MAC address byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.3.4.5 MAC4 – CPU MAC address byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.3.4.6 MAC5 – CPU MAC address byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.3.4.7 INT_MASK0 – Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.3.4.8 INTP_MASK0 – Interrupt Mask for MAC Port 0,1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.3.4.9 INTP_MASKn – Interrupt Mask for MAC Ports 2~9 Registers . . . . . . . . . . . . . . . . . . . . . . . 78
12.3.4.10 RQS – Receive Queue Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.3.4.11 RQSS – Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.3.4.12 MAC01 – Increment MAC port 0,1 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.3.4.13 MAC23 – Increment MAC port 2,3 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.3.4.14 MAC45 – Increment MAC port 4,5 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.3.4.15 MAC67 – Increment MAC port 6,7 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.3.4.16 MAC9 – Increment MAC port 9 address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.3.4.17 CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command . . . . . . . . . . . . . . . . . . . . . . 80
12.3.4.18 CPUQINSRPT – CPU Queue Insertion Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.3.4.19 CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer . . . . . . . . . . . . . . . . . 81
12.3.4.20 CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . 81
12.3.4.21 CPUGRNCTR – CPU Granule Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.3.5 (Group 4 Address) Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.3.5.1 AGETIME_LOW – MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.3.5.2 AGETIME_HIGH –MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.3.5.3 SE_OPMODE – Search Engine Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.3.6 (Group 5 Address) Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12.3.6.1 QOSC – QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12.3.6.2 UCC – Unicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.3.6.3 MCC – Multicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.3.6.4 MCCTH – Multicast Threshold Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.3.6.5 RDRC0 – WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.3.6.6 RDRC1 – WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.3.6.7 RDRC2 – WRED Rate Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.3.6.8 SFCB – Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.3.6.9 C1RS – Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.3.6.10 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.3.6.11 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.3.6.12 AVPML – VLAN Tag Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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12.3.6.13 AVPMM – VLAN Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.3.6.14 AVPMH – VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.3.6.15 AVDM – VLAN Discard Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.3.6.16 TOSPML – TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.3.6.17 TOSPMM – TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.3.6.18 TOSPMH – TOS Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.3.6.19 TOSDML – TOS Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.3.6.20 USER_PROTOCOL_n – User Define Protocol 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.3.6.21 USER_PROTOCOL_FORCE_DISCARD – User Define Protocol 0~7 Force Discard. . . . 89
User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.3.6.22 WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . 90
12.3.6.23 WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . 90
12.3.6.24 WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . 90
12.3.6.25 WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority . . . . . . 90
12.3.6.26 WELL_KNOWN_PORT_ENABLE – Well Known Logic Port 0 to 7 Enables . . . . . . . . . . . 91
12.3.6.27 WELL_KNOWN_PORT_FORCE_DISCARD – Well Known Logic Port 0~7 Force Discard91
12.3.6.28 USER_PORT[7:0]_[LOwithHIGH] – User Define Logical Port 0~7 . . . . . . . . . . . . . . . . . . 92
12.3.6.29 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority. . . . . . . . . . . . . 92
12.3.6.30 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority. . . . . . . . . . . . . 92
12.3.6.31 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority. . . . . . . . . . . . . 92
12.3.6.32 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority. . . . . . . . . . . . . 93
12.3.6.33 USER_PORT_ENABLE[7:0] – User Define Logic Port 0 to 7 Enables . . . . . . . . . . . . . . . 93
12.3.6.34 USER_PORT_FORCE_DISCARD[7:0] – User Define Logic Port 0~7 Force Discard . . . . 93
12.3.6.35 RLOWL – User Define Range Low Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.6.36 RLOWH – User Define Range Low Bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.6.37 RHIGHL – User Define Range High Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.6.38 RHIGHH – User Define Range High Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.6.39 RPRIORITY – User Define Range Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.7 (Group 6 Address) MISC Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.7.1 MII_OP0 – MII Register Option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.7.2 MII_OP1 – MII Register Option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.7.3 FEN – Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.7.4 MIIC0 – MII Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.3.7.5 MIIC1 – MII Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.3.7.6 MIIC2 – MII Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.3.7.7 MIIC3 – MII Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.3.7.8 MIID0 – MII Data Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.3.7.9 MIID1 – MII Data Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.3.7.10 USD – One Micro Second Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.3.7.11 DEVICE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.3.7.12 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.3.7.13 LHBTimer – Link Heart Beat Timeout Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3.7.14 LHBReg0, LHBReg1 - Link Heart Beat OpCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3.7.15 fMACCReg0, fMACCReg1 - MAC Control Frame OpCode . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3.7.16 FCB Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3.7.17 FCB Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3.7.18 FCB Base Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3.8 (Group 7 Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.3.8.1 MIRROR CONTROL – Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.3.8.2 MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0~5 . . . . . . . . . . . . . . . . . 100
12.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0~5 . . . . . . . . . . . . . . . . . . . . . 100
12.3.8.4 RMAC_MIRROR0 – RMAC Mirror 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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12.3.8.5 RMAC_MIRROR1 – RMAC Mirror 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.3.9 (Group 8 Address) Per Port QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.3.9.1 FCRn – Port 0~9 Flooding Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.3.9.2 BMRCn - Port 0~9 Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.3.9.3 PR100_n – Port 0~7 Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.9.4 PR100_CPU – Port CPU Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.9.5 PRM – Port MMAC Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.9.6 PTH100_n – Port 0~7 Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.9.7 PTH100_CPU – Port CPU Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.9.8 PTHG – Port MMAC Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.9.9 QOSC00, QOSC01 - Classes Byte Limit port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.9.10 QOSC02, QOSC15 - Classes Byte Limit port 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.9.11 QOSC16 - QOSC21 - Classes Byte Limit CPU port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.9.12 QOSC22 - QOSC27 - Classes Byte Limit MMAC port . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.9.13 QOSC28 - QOSC31 - Classes WFQ Credit For MMAC. . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.9.14 QOSC36 - QOSC39 - Shaper Control Port MMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.3.10 (Group E Address) System Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.3.10.1 DTSRL – Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.3.10.2 DTSRM – Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.3.10.3 TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.3.10.4 MASK0-MASK4 – Timeout Reset Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.3.10.5 BOOTSTRAP0 – BOOTSTRAP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.3.10.6 PRTFSMST0~9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.3.10.7 PRTQOSST0-PRTQOSST7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.3.10.8 PRTQOSST8A, PRTQOSST8B (CPU port). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.3.10.9 PRTQOSST9A, PRTQOSST9B (MMAC port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12.3.10.10 CLASSQOSST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12.3.10.11 PRTINTCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
12.3.10.12 QMCTRL0~9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
12.3.10.13 QCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
12.3.10.14 BMBISTR0, BMBISTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
12.3.10.15 BMControl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
12.3.10.16 BUFF_RST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
12.3.10.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.3.10.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.3.10.19 FCB_NUM0, FCB_NUM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.3.10.20 BM_RLSFF_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3.10.21 BM_RSLFF_INFO[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3.11 (Group F Address) CPU Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.3.11.1 GCR - Global Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.3.11.2 DCR - Device Status and Signature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.3.11.3 DCR1 - Device Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.3.11.4 DPST – Device Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.3.11.5 DTST – Data read back register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.11.6 DA – Dead or Alive Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.0 Characteristics and Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.2 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.4.2 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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13.4.3 Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.4.4 General Purpose Serial Interface (7-wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.4.5 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.4.6 I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.4.7 Serial Interface Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.4.8 JTAG (IEEE 1149.1-2001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.0 Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.1 July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.2 November 2003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.3 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.4 August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.5 November 2004. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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1.0 BGA and Ball Signal Descriptions
1.1 BGA Views (Top-View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
SCLK
P_CS#
P_A0
P_RD#
P_A1
P_WE
#
P_DAT
A1
P_DAT
A3
P_DAT
A5
P_DAT
A7
P_DAT
A9
P_DAT
A11
P_DAT
A13
P_DAT
A15
GREF_
CLK
M9_TX
CLK
M9_M
TXCLK
M9_TX
EN
A
B
C
D
E
P_INT
#
P_A2
P_DAT
A0
P_DAT
A2
P_DAT
A4
P_DAT
A6
P_DAT
A8
P_DAT
A10
P_DAT
A12
P_DAT
A14
TCK
TDI
TMS
M9_TX
ER
M9_RX
CK
RESET
OUT#
TSTO
UT1
TSTO
UT3
TSTO
UT5
TSTO
UT6
TSTO
UT7
TSTO
UT9
TSTO
UT11
TSTO
UT12
TSTO
UT14
TSTO
UT15
TRST#
3.3V
M9_RX
D7
M9_C
RS
M9_C
OL
RESIN
#
TSTO
UT0
TSTO
UT2
TSTO
UT4
3.3V
SCAN_
EN
TSTO
UT8
TSTO
UT10
1.8V
TSTO
UT13
TDO
M9_RX
D5
M9_RX
D6
M9_RX
DV
M9_RX
ER
M2_C
OL
M0_C
OL
M1_C
OL
3.3V
3.3V
M9_RX
D4
M9_TX
D6
M9_TX
D7
F
G
H
J
M_MD
C
M_MDI
O
M0_RX
D2
M0_RX
D3
M9_RX
D2
M9_RX
D3
M9_TX
D4
M9_TX
D5
F
G
H
J
M0_RX
D0
M0_RX
D1
M0_RX
CK
M0_TX
D3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M9_RX
D0
M9_RX
D1
M9_TX
D2
M9_TX
D3
M0_C
RS
M0_TX
EN
M0_TX
D2
1.8V
1.8V
M7_C
OL
M9_TX
D0
M9_TX
D1
M0_TX
D0
M0_TX
D1
M0_TX
CK
M1_RX
D3
M7_TX
D3
M7_TX
CK
M7_TX
D1
M7_TX
D0
K
L
M1_RX
D0
M1_RX
D1
M1_RX
D2
M1_RX
CK
M7_TX
D2
M7_RX
D2
M7_TX
EN
M7_C
RS
K
L
M1_C
RS
M1_TX
EN
M1_TX
D2
M1_TX
D3
M7_RX
D3
M7_RX
CK
M7_RX
D1
M7_RX
D0
M
M1_TX
D0
M1_TX
D1
M1_TX
CK
3.3V
3.3V
M6_C
OL
M5_C
OL
M4_C
OL
M
N
P
R
T
M2_RX
D3
M2_TX
CK
M2_TX
D3
M3_RX
D3
3.3V
M3_TX
D3
1.8V
M4_RX
D3
M4_TX
CK
M4_TX
D3
M5_RX
D3
M5_TX
CK
M5_TX
D3
M6_RX
D3
M6_TX
CK
M6_TX
D3
N
P
R
T
M2_RX
D2
M2_RX
CK
M2_TX
D2
M3_RX
D2
M3_RX
CK
M3_TX
D2
M3_C
OL
M4_RX
D2
M4_RX
CK
M4_TX
D2
M5_RX
D2
M5_RX
CK
M5_TX
D2
M6_RX
D2
M6_RX
CK
M6_TX
D2
M2_RX
D1
M2_TX
EN
M2_TX
D1
M3_RX
D1
M3_TX
EN
M3_TX
D1
M_CLK
M4_RX
D1
M4_TX
EN
M4_TX
D1
M5_RX
D1
M5_TX
EN
M5_TX
D1
M6_RX
D1
M6_TX
EN
M6_TX
D1
M2_RX
D0
M2_C
RS
M2_TX
D0
M3_RX
D0
M3_C
RS
M3_TX
D0
M3_TX
CK
M4_RX
D0
M4_C
RS
M4_TX
D0
M5_RX
D0
M5_C
RS
M5_TX
D0
M6_RX
D0
M6_C
RS
M6_TX
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1.2 Power and Ground Distribution
G7-10, H7-10, J7-10, K7-10
GND
3.3V
V
V
Ground
SS
CC
D5, D12, E4, E13, M4, M13,
N5
I/O Power
D9, H4, H13, N7
1.8V
V
Core Power
DD
11
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
1.3 Ball Signal Descriptions
All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive.
Notes
# =
Active low signal
Input =
Input signal
Input-ST =
Output =
I/O-TS =
pull-up =
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Input & Output signal with Tri-State driver
Weak internal pull-up (nominal 100K ohm)
(refer to Section 1.4 on page 17 as some internal
pull-ups are not enabled in certain configurations)
pull-down =
Weak internal pull-down (nominal 100K ohm)
(refer to Section 1.4 on page 17 as some internal
pull-downs are not enabled in certain configurations)
Ball Signal Description Table
Ball No(s)
Symbol
I/O
Description
16-Bit CPU Bus Interface
A12, B12, A11, B11,
A10, B10, A9, B9, A8,
B8, A7, B7, A6, B6,
A5, B5
P_DATA[15:0]
I/O-TS
with pull-up
Processor Bus Data Bit [15:0]. P_DATA[7:0] is
used in 8-bit mode.
B4, B3, B2
P_A[2:0]
P_WE#
Input
with pull-up
Processor Bus Address Bit [2:0]
CPU Bus-Write Enable
A4
Input
with pull-up
A3
A2
P_RD#
P_CS#
Input
CPU Bus-Read Enable
Chip Select
Input
with pull-up
B1
P_INT#
Output
CPU Interrupt
Fast Ethernet Access Ports [7:0] MII
L13, K14, L15, L16,
N14, P14, R14, T14,
N11, P11, R11, T11,
N8, P8, R8, T8, N4,
P4, R4, T4, N1, P1,
R1, T1, J4, K3, K2,
K1, F4, F3, G2, G1
M[7:0]_RXD[3:0] Input
Ports [7:0] – Receive Data Bit [3:0]
with pull-up
K16, T15, T12, T9, T5, M[7:0]_CRS_DV Input
T2, L1, H1 with pull-up
Ports [7:0] – Carrier Sense and Receive Data
Valid
12
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Ball Signal Description Table (continued)
Ball No(s)
Symbol
I/O
Description
K15, R15, R12, R9,
R5, R2, L2, H2
M[7:0]_TXEN
Output, slew
Ports [7:0] – Transmit Enable
This pin also serves as a bootstrap pin.
J13, K13, J15, J16,
N16, P16, R16, T16,
N13, P13, R13, T13,
N10, P10, R10, T10,
N6, P6, R6, T6, N3,
P3, R3, T3, L4, L3,
M2, M1, G4, H3, J2,
J1
M[7:0]_TXD[3:0] Output, slew
Ports [7:0] – Transmit Data Bit [3:0]
H14, M14, M15, M16, M[7:0]_COL
Input
Ports[7:0] – Collision
P7, E1, E3, E2
with pull-down
J14, N15, N12, N9,
T7, N2, M3, J3
M[7:0]_TXCLK
M[7:0]_RXCLK
Input or Output
with pull-up
Ports[7:0] – Transmit Clock
This pin in an output if ECR4Pn[0]='1'
L14, P15, P12, P9,
P5, P2, K4, G3
Input or Output
with pull-up
Ports[7:0] – Receive Clock
This pin in an output if ECR4Pn[1]='1'
Gigabit Ethernet Uplink Port GMII
E16, E15, F16, F15,
G16, G15, H16, H15
M9_TXD[7:0]
M9_RXDV
M9_RXER
M9_CRS
Output
Transmit Data Bit [7:0]
Receive Data Valid
Receive Error
D15
D16
C15
C16
B16
Input
with pull-up
Input
with pull-up
Input
with pull-down
Carrier Sense
M9_COL
Input
with pull-down
Collision Detected
Receive Clock
M9_RXCLK
Input or Output
with pull-up
In MII mode, this pin in an output if
ECR4P9[1]='1'
C14, D14, D13, E14,
F14, F13, G14, G13
M9_RXD[7:0]
M9_TXEN
Input
with pull-up
Receive Data Bit [7:0]
A16
Output
Transmit Data Enable
with pull-up
This pin also serves as a bootstrap pin.
Transmit Error
B15
M9_TXER
Output
with pull-up
This pin also serves as a bootstrap pin.
13
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Ball Signal Description Table (continued)
Ball No(s)
Symbol
I/O
Description
A15
A14
M9_MTXCLK
Input
with pull-up
Transmit Clock
M9_TXCLK
Output
Gigabit Transmit Clock
Test Interface
C11, C10, D10, C9,
C8, D8, C7, D7, C6,
C5, C4, D4, C3, D3,
C2, D2
TSTOUT[15:0]
Output
[15:4] Reserved
[3] EEPROM checksum is good
[2] Initialization Completed
[1] Memory Self Test in progress
[0] Initialization started
These pins also serve as bootstrap pins.
Test Facility
C13
TDI
Input
with pull-up
JTAG - Test Data In
JTAG - Test Reset
JTAG - Test Clock
C12
B13
B14
TRST#
TCK
Input
with pull-up
Input
with pull-up
TMS
Input
JTAG - Test Mode State
with pull-up
D11
D6
TDO
Output
Input
JTAG - Test Data Out
SCAN_EN
Scan Enable. Manufacturing test option.
Must be externally
pulled-down
Should be externally pulled-down for proper
operation.
System Clock, Power, and Ground Pins
A1
SCLK
Input
System Clock. Based on system requirement,
SCLK needs to operate at difference
frequency.
SCLK requires 40/60% duty cycle clock.
D9, H4, H13, N7,
V
V
Power
Power
+1.8 Volt DC Supply
+3.3 Volt DC Supply
DD
CC
D5, D12, E4, E13, M4,
M13, N5,
G7-10, H7-10, J7-10,
K7-10
V
Power Ground
Ground
SS
Misc.
D1
RESIN#
Input
Reset Input
Reset PHY
C1
RESETOUT#
Output
14
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Ball Signal Description Table (continued)
Ball No(s) Symbol
M_MDC
I/O
Description
F1
F2
Output
I/O-TS
MII Management Data Clock
MII Management Data I/O
M_MDIO
with pull-up
R7
M_CLK
Input
RMAC Reference Clock
GMAC Reference Clock
A13
GREF_CLK
Input
with pull-up
1
Bootstrap Pins (1= pull-up 0= pull-down)
(See “Bootstrap Options” on page 20)
D2
TSTOUT[0]
Input (Reset Only)
Input (Reset Only)
Enable Debounce of STROBE signal
Pullup – Enabled
Pulldown - Disabled
C3, D3, C2
TSTOUT[3:1]
Management interface operation mode:
000 – 16-bit parallel interface
001 – 8-bit parallel interface
010 – Serial with MII as Ethernet frame
transfer interface.
011 – Serial only. CPU can transmit/receive
frames with the serial interface.
111 – Unmanaged Serial. No CPU packet can
be transmit or received with the serial
interface. EEPROM can be used to configure
the device at bootup.
A one (1) indicates pullup. A zero (0)
indicates pulldown. TSTOUT[1] is the Least
Significant Bit (LSB).
C5, C4, D4
TSTOUT[6:4]
Input (Reset Only)
Device ID. Default address of the device for
serial interface. Up to 8 device can be sharing
the serial management bus with different
device ID.
A one (1) indicates pullup. A zero (0)
indicates pulldown. TSTOUT[4] is the Least
Significant Bit (LSB).
C6
D7
TSTOUT[7]
TSTOUT[8]
Input (Reset Only)
Input (Reset Only)
EEPROM not installed.
Pullup: Not installed
Pulldown: Installed
Manufacturing Option. Must be pulled up.
Must be externally
pulled-up
15
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Ball Signal Description Table (continued)
Ball No(s)
Symbol
I/O
Description
C7
D8
TSTOUT[9]
Input (Reset Only)
Module Detect
Pullup: Enable. In this mode, the device will
detect the existence of a PHY (for hot swap
purpose).
Pulldown: Disable
TSTOUT[10]
Input (Reset Only)
Manufacturing Option. Must be pulled down.
Must be externally
pulled-down
C8
C9
TSTOUT[11]
TSTOUT[12]
Input (Reset Only)
Power Saving
Pullup: Enable MAC power saving mode
Pulldown: Disable MAC power saving mode
Input (Reset Only)
Timeout Reset Enable
Pullup: Enable
Pulldown: Disable
C11, C10, D10
TSTOUT[15:13] Input (Reset Only)
Manufacturing Options. Must be pulled-up.
Must be externally
pulled-up
K15, R15, R12, R9,
R5, R2, L2, H2
M[7:0]_TXEN
Input (Reset Only)
User Defined Bootstrap:
Usually used in conjuction with Module Detect
to determine what interface to use for the
inserted module. Can be read from
BOOTSTRAP2 register
A16, B15
M9_TXEN,
M9_TXER
Input with pull-up
(Reset Only)
User Defined Bootstrap:
Usually used in conjuction with Module Detect
to determine what interface to use for the
inserted module. Can be read from
BOOTSTRAP3 register
1. External pull-up/down resistors are required on all bootstrap pins for proper operation. Recommend 10K for pull-ups and 1K for
pull-downs.
16
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
1.4 Signal Mapping and Internal pull-up/Down Configuration
The ZL50410 Fast Ethernet access ports (0-7) support 3 interface options: RMII, MII & GPSI. The table below
summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name
shown in the “Ball Signal Description Table” on page 12. It also specifies whether the internal pull-up/down resistor
is present for each pin in the specific operating mode.
Notes:
I – Input
O – Output
U – Pullup
D - Pulldown
No
Fast Ethernet
RMII Mode
(ECR4Pn[4:3]='11')
MII Mode
(ECR4Pn[4:3]='01')
GPSI Mode
(ECR4Pn[4:3]='00')
Module
(Bootstrap
Access Ports
Pin Symbol
TSTOUT9=’1’)
M[7:0]_RXD0
(U)
(U)
(U)
(U)
(O)
(U)
(O)
(O)
(O)
(O)
(D)
(U)
(U)
M[7:0]_RXD0 (I)
M[7:0]_RXD1 (I)
NC (U)
M[7:0]_RXD0 (I)
M[7:0]_RXD1 (I)
M[7:0]_RXD2 (I)
M[7:0]_RXD3 (I)
M[7:0]_TXEN (O)
M[7:0]_DV (I)
M[7:0]_RXD (I)
NC (U)
M[7:0]_RXD1
M[7:0]_RXD2
M[7:0]_RXD3
M[7:0]_TXEN
M[7:0]_CRS_DV
M[7:0]_TXD0
M[7:0]_TXD1
M[7:0]_TXD2
M[7:0]_TXD3
M[7:0]_COL
NC (U)
NC (U)
NC (U)
M[7:0]_TXEN (O)
M[7:0]_CRS_DV (I)
M[7:0]_TXD0 (O)
M[7:0]_TXD1 (O)
NC (O)
M[7:0]_TXEN (O)
M[7:0]_CRS (I)
M[7:0]_TXD (O)
NC (O)
M[7:0]_TXD0 (O)
M[7:0]_TXD1 (O)
M[7:0]_TXD2 (O)
M[7:0]_TXD3 (O)
M[7:0]_COL (I)
NC (O)
NC (O)
NC (O)
NC (D)
M[7:0]_COL (I)
M[7:0]_TXCLK (IO)
M[7:0]_RXCLK (IO)
M[7:0]_TXCLK
M[7:0]_RXCLK
NC (U)
M[7:0]_TXCLK (IO)
M[7:0]_RXCLK (IO)
NC (U)
Table 1 - Signal Mapping In Different Operation Mode
17
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
The ZL50410 Gigabit Ethernet uplink port (port 9) supports 2 interface options: GMII & MII. The table below
summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name
shown in “Ball Signal Description Table” on page 12.
No
Gigabit Ethernet
GMII Mode
(ECR4P9[4:3]='11')
MII Mode
(ECR4P9[4:3]='00')
Module
(Bootstrap
Uplink Port
Pin Symbol
TSTOUT9=’1’)
M9_RXD0
(U)
(U)
(U)
(U)
(U)
(U)
(U)
(U)
(U)
(U)
(D)
(D)
(U)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(U)
(U)
(O)
(U)
(U)
M9_RXD0 (I)
M9_RXD0 (I)
M9_RXD1
M9_RXD2
M9_RXD3
M9_RXD4
M9_RXD5
M9_RXD6
M9_RXD7
M9_RXDV
M9_RXER
M9_CRS
M9_RXD1 (I)
M9_RXD2 (I)
M9_RXD3 (I)
M9_RXD4 (I)
M9_RXD5 (I)
M9_RXD6 (I)
M9_RXD7 (I)
M9_RXDV (I)
M9_RXER (I)
M9_CRS (I)
M9_RXD1 (I)
M9_RXD2 (I)
M9_RXD3 (I)
NC (U)
NC (U)
NC (U)
NC (U)
M9_RXDV (I)
NC (U)
M9_CRS (I)
M9_COL (I)
M9_RXCLK (IO)
M9_TXD0 (O)
M9_TXD1 (O)
M9_TXD2 (O)
M9_TXD3 (O)
NC (O)
M9_COL
M9_COL (I)
M9_RXCLK
M9_TXD0
M9_TXD1
M9_TXD2
M9_TXD3
M9_TXD4
M9_TXD5
M9_TXD6
M9_TXD7
M9_TXEN
M9_TXER
M9_TXCLK
GREF_CLK
M9_MTXCLK
M9_RXCLK (I)
M9_TXD0 (O)
M9_TXD1 (O)
M9_TXD2 (O)
M9_TXD3 (O)
M9_TXD4 (O)
M9_TXD5 (O)
M9_TXD6 (O)
M9_TXD7 (O)
M9_TXEN (O)
M9_TXER (O)
M9_TXCLK (O)
GREF_CLK (I)
M9_MTXCLK (I)
NC (O)
NC (O)
NC (O)
M9_TXEN (O)
NC (O)
NC (O)
REF_CLK (I)
M9_MTXCLK (I)
Table 2 - Signal Mapping In Different Operation Mode
18
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
The ZL50410 CPU access support 5 interface options: 8 or 16-bit parallel, serial+MII (port 8), serial only, and
unmanaged serial (with optional EEPROM). The table below summarizes the interface signals required for each
interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12.
Management
8-bit CPU
Serial with MII
16-bit CPU
(TSTOUT[3:1]=’000’)
Serial Only
(TSTOUT[3:1]=’011’ or ‘111’)
Interface
(TSTOUT[3:1]=’001’)
(TSTOUT[3:1]=’010’)
Pin Symbol
P_A[0]
P_A[0] (I)
P_A[0] (I)
NC (U)
SDA (IOU) (111 only)
SCL (OU) (111 only)
NC (U)
P_A[1]
P_A[1] (I)
P_A[1] (I)
NC (U)
P_A[2]
P_A[2] (I)
P_A[2] (I)
NC (U)
P_WE#
P_WE# (I)
P_WE# (I)
P_RD# (I)
STROBE (IU)
DATAOUT (O)
DATAIN (IU)
STROBE (IU)
DATAOUT (O)
DATAIN (IU)
P_INT# (O)
NC (U)
P_RD#
P_RD# (I)
P_CS#
P_CS# (I)
P_CS# (I)
P_INT#
P_INT# (O)
P_INT# (O)
P_DATA0 (IOU)
P_DATA1 (IOU)
P_DATA2 (IOU)
P_DATA3 (IOU)
P_DATA4 (IOU)
P_DATA5 (IOU)
P_DATA6 (IOU)
P_DATA7 (IOU)
NC (U)
P_INT# (O)
P_DATA0
P_DATA1
P_DATA2
P_DATA3
P_DATA4
P_DATA5
P_DATA6
P_DATA7
P_DATA8
P_DATA9
P_DATA10
P_DATA11
P_DATA12
P_DATA13
P_DATA14
P_DATA15
P_DATA0 (IOU)
P_DATA1 (IOU)
P_DATA2 (IOU)
P_DATA3 (IOU)
P_DATA4 (IOU)
P_DATA5 (IOU)
P_DATA6 (IOU)
P_DATA7 (IOU)
P_DATA8 (IOU)
P_DATA9 (IOU)
P_DATA10 (IOU)
P_DATA11 (IOU)
P_DATA12 (IOU)
P_DATA13 (IOU)
P_DATA14 (IOU)
P_DATA15 (IOU)
CPU_MII_TXD0 (O)
CPU_MII_TXD1 (O)
CPU_MII_TXD2 (O)
CPU_MII_TXD3 (O)
NC (U)
NC (U)
NC (U)
CPU_MII_TXCLK (O) NC (U)
CPU_MII_TXEN (O)
NC (U)
NC (U)
NC (U)
NC (U)
NC (U)
NC (U)
NC (U)
NC (U)
NC (U)
CPU_MII_RXD0 (I)
CPU_MII_RXD1 (I)
CPU_MII_RXD2 (I)
CPU_MII_RXD3 (I)
NC (U)
NC (U)
NC (U)
NC (U)
CPU_MII_RXCLK (O) NC (U)
NC (U)
CPU_MII_RXDV (I)
NC (U)
NC (U)
NC (U)
NC (U)
NC (U)
NC (U)
NC (U)
Table 3 - Signal Mapping In Different Operation Mode
19
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
1.5 Bootstrap Options
TSTOUT[15:0], M[7:0]_TXEN, M9_TXEN and M9_TXER pins serve as bootstrap pins during device power-up or
reset. Please refer to “Typical Reset & Bootstrap Timing Diagram” on page 124 for more information on when the
bootstrap pins are sampled. The bootstrap pins require external pull-up/down resistors for proper operation.
The table below summarizes the bootstrap options.
Feature
CPU Interface
Description
The ZL50410 allows the selection of 5 different management interfaces:
8/16-bit parallel, serial with MII, serial only and unmanaged serial with I2C
EEPROM.
TSTOUT[3:1] is used to select the interface options mentioned above. If the
serial interface is selected, addition bootstrap options are required:
•
TSTOUT[0] enables or disables the DEBOUNCE feature (refer to
“Synchronous Serial Interface” on page 32)
•
TSTOUT[6:4] selects the device ID
2
Also, in unmanaged mode, an optional I C EEPROM can be used to configure
the device at power-up or reset. TSTOUT[7] selects the EEPROM option.
Ethernet Interface
The ZL50410 supports module hotswap on all it's ports. This is enabled via
TSTOUT[9]. When enabled, bootstrap pins M[7:0]_TXEN (ports 0-7) and
M9-TXEN & M9_TXER (port 9) are used to specify the module type to support
multiple ethernet interfaces during module hotswap.
Another feature is the MAC power savings mode. When enabled via
TSTOUT[11], each port's MAC will detect inactivity on the port and go into a
power savings state. When activity is detected once again on the port, the MAC
will come out of this state.
Misc. Features
One other feature selected via bootstrap is Timeout Reset Enable
(TSTOUT[12]). This enables a monitoring block with the device which will
detect if any hardware state machine is in a non-idle state for more than 5
seconds.
Refer to section 2.7 for more details on this feature.
Table 4 - Bootstrap Features
1.5.1 Recommended Default Bootstrap Settings
The following are the recommended default settings for the bootstrap options:
•
Unmanaged/Lightly Managed
•
Reserved/Manufacturing bootstraps
-
-
TSTOUT[15:13,8] must be pulled-up
TSTOUT[10] must be pulled-down
•
CPU Interface:
-
Strobe debounce bootstrap, TSTOUT[0], should be normally pulled-up, unless you wish to disable the
debounce logic
-
CPU Interface bootstrap, TSTOUT[3:1], should be pulled-up to indicate unmanaged SSI CPU
interface. To enable SSI-only lightly managed mode, pulled-down TSTOUT[3]. To enable SSI+MII
lightly managed mode, pulled-down TSTOUT[3,1]
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
-
-
SSI Device ID bootstrap, TSTOUT[6:4], should be pulled-down to indicate device ID 0x0 for the SSI
interface. Can be changed to whatever device ID required if more than one device on the SSI bus.
EEPROM bootstrap, TSTOUT[7], should be pulled-up to disable until the system is debugged. You
can pull-down this bootstrap if using the optional EEPROM in unmanaged mode (NOTE: this bootstrap
is not valid in any other CPU mode)
•
Module Detect bootstrap, TSTOUT[9], should be pulled-down
-
-
In lightly managed mode, you can enable the optional Module Detect feature
If enabled, need to use Mn_TXEN to indicate module type
•
•
Power Saving bootstrap, TSTOUT[11], should be normally pulled-up
Timeout Reset bootstrap, TSTOUT[12], should be pull-down
-
Once system is debugged, you can enable the optional feature with pull-up (Refer to section 2.7 for
more details on this feature)
•
Managed
•
•
•
Reserved/Manufacturing bootstraps
-
-
TSTOUT[15:13,6:4,8,7,0] must be pulled-up
TSTOUT[10] must be pulled-down
CPU Interface
-
-
TSTOUT[3:1], should be pulled-down to indicate 16-bit CPU mode
For 8-bit CPU mode, pull-up TSTOUT[1]
Module Detect bootstrap, TSTOUT[9], should be pulled-down, unless using the Module Detect feature
If enabled, need to use Mn_TXEN to indicate module type
-
•
•
Power Saving bootstrap, TSTOUT[11], should be normally pulled-up
Timeout Reset bootstrap, TSTOUT[12], should be pull-down
-
Once system is debugged, you can enable the optional feature with pull-up (Refer to section 2.7 for
more details on this feature)
1.6 Default Switch Configuration and Initialization Sequence
The ZL50410 will come out of reset in a default configuration, which will allow for basic L2 switching and automatic
MAC address learning.
In unmanaged mode, the default configuration will take effect immediately after reset. The default settings can be
changed using the optional EEPROM.
•
System Defaults
•
•
•
•
•
•
•
Port-based VLAN
MAC address 00-00-00-00-00-00 not learned
Drop MAC addresses 01-80-C2-00-00-01~F
No IP Multicast switching support
Trunking and mirroring disabled
MAC address agetime is 300 seconds
VLAN 802.1p prioritization
-
All priority bits mapped to priority 0 (lowest)
•
•
•
•
96 queued unicast/multicast frames will trigger flow control
All WRED drop percentages equal to 0%
Unicast/multicast/broadcast flood control disabled
No shared or per-class buffer pools
•
Per-port Defaults
•
•
•
•
Disable per-port fixed priority and drop precedence
Disable asynchronous flow control
Spanning Tree per-port state equal to forwarding
Don’t filter tagged/untagged VLAN frames
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
•
•
•
•
•
•
•
Automatic learning enabled
Per-port security disabled
Support frame size 64 <= n <= 1522
Pad transmit frames < 64B
Standard preamble
Strict Priority scheduling
FE Ports
-
-
-
-
RMII mode
Auto-negotiate 100M/Full Duplex/Flow Control
Rate control disabled
per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers
•
Uplink Port
-
-
-
GMII mode
Auto-negotiate 1000M/Full Duplex/Flow Control
per-source port buffer pool of 384 buffers, with flow control threshold of 192 buffers
In lightly managed/managed mode, the default configuration can be used as well, however, the device needs to be
told when to start switching. This is done via the “Init Complete” bit, set in GCR[4]. The default settings can be
overridden using the CPU interface, but should be done before setting of GCR[4]. One thing to note is after reset,
the device will start to initialize the control tables. Therefore, a short delay (100us~1ms) is necessary before
changing the register settings and/or control tables, and before setting GCR[4].
•
System Defaults
•
•
CPU MAC address is 00-00-00-00-00-00
Forward MAC addresses 01-80-C2-00-00-00~FF to CPU port
-
Except 01-80-C2-00-00-01~F, which are dropped
•
•
•
•
•
All interrupts enabled
MAC address learn report to CPU disabled
Statistics counters disabled
DiffServ EF code support disabled
No VLAN ID hashing
•
Per-port Defaults
•
FE Ports
-
Link heart beat disabled
•
CPU Port
-
-
-
100M/Full Duplex/Flow Control
8-byte header padding
per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers
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ZL50410
Data Sheet
2.0 Block Functionality
8
RMAC X
GGMAC
Other Internal
Memory Block
Frame Engine
Search Engine
Management
Module
Internal Memory
Figure 2 - Functional Block Diagram
2.1 Internal Memory
Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB), storing of MAC Control Table
database (MCT), and the Network Management (NM) Database statistics counters and MIB.
The MCT is used for storing MAC addresses and their physical port number. The FDB is used for storing the
received frame data contents. The contents are stored in this memory until it is ready to be transmitted to the
egress port.
A memory arbiter is used to arbitrary the memory access requests from various sources. A Built In Self Test (BIST)
is used to detect any error in the memory array when the device is powered up. The BIST can also be requested by
the writing to the GCR register.
2.2 MAC Modules
2.2.1 RMII MAC Module (RMAC)
The RMII Media Access Control (RMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M),
Reverse MII, or Reverse GPSI (only for 10M).
The RMAC of the ZL50410 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full
Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon
collision for up to 16 total transmissions.
These eight ports are denoted as ports 0 to 7. The PHY addresses for the PHY devices connected to the 8 RMAC
ports has to be from 08h (port 0) to 0Fh (port 7).
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
2.2.1.1 GPSI (7WS) Interface
The RMAC ethernet port can function in GPSI (7WS) mode. In this mode, the TXD[0], RXD[0] serve as TX data, RX
data and respectively. The link and duplex of the port can be controlled by programming the ECR1Pn register. Only
port-based VLAN is supported with GPSI interface.
2.2.2 CPU MAC Module (CMAC)
The CPU Media Access Control (CMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external CPU device. It support either a Reverse MII interface, providing the necessary
interface TX and RX clocks to the CPU, or a register access mechanism via the 8/16-bit or serial interface.
Using the MII interface, the CMAC of the ZL50410 device meets the IEEE 802.3 specification. It is able to operate
in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically
retransmit upon collision for up to 16 total transmissions.
This port is denoted as port 8.
2.2.3 GMII MAC Module (GMAC)
The GMII Media Access Control (GMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). The GMAC implements both GMII and MII interface,
which offers a simple migration from 10/100 to 1G.
The GMAC of the ZL50410 device meets the IEEE 802.3Z specification. It is able to operate in 10M/100M either
Half or Full Duplex mode with a back pressure/flow control mechanism or in 1G Full duplex mode with flow control
mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions.
This port is denoted as port 9. The PHY address for the PHY device connected to the GMAC port has to be 10h.
2.2.4 PHY Addresses
The table below provides an overview of the PHY addresses required for each port in order for the MDIO
auto-negotiation to work between the ZL50410 MAC and the PHY device. If a different PHY address is used, then
the port must be manually brought up and the PHY will need to be polled for link status via the MIIC/D registers.
MAC Port
PHY Address
RMAC Port 0
RMAC Port 1
...
0x08
0x09
...
RMAC Port 7
CMAC Port 8
GMAC Port 9
0x0F
NA
0x10
Table 5 - PHY Addresses
2.3 Management Module
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
This module is only active in managed mode. In unmanaged mode, no control frame is accepted by the device.
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
2.4 Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the
search engine, to resolve the destination port. The arriving frame is moved to the internal memory. After receiving a
switch response from the search engine, the frame engine performs transmission scheduling based on the frame’s
priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
2.5 Search Engine
The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2) or
IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority
assignment, and trunking functions.
2.6 Heartbeat Packet Generation and Response
The ZL50410 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet
generation module allows simultaneous tracking of all the RMAC ports.
Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time
period, If a reply is not received in a specified amount of time, the failover detection module will identify a
point-to-point failure for that link. The failover detection module will then interrupt the CPU.
The LHB packet response module can also reply to LHB messages initiated by other ZL50410 devices in the
system, or by non-ZL50410 devices which use a conventional and recognizable LHB message format.
2.7 Timeout Reset Monitor
The ZL50410 supports a state machine monitoring block which can trigger a reset or interrupt if any state machine
is determined to be stuck in a non-idle state for more than 5 seconds. This feature is enabled via a bootstrap pin
(TSTOUT12). It also requires some register configuration via the CPU interface.
See Programming Timeout Reset application note, ZLAN-41, for more information.
2.8 JTAG
An IEEE1149.1 compliant test interface is provided for boundary scan.
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
3.0 Management and Configuration
One extra port is dedicated to the CPU via the CPU interface module. Three modes this port can operate:
managed, lightly managed or unmanaged mode. The different between these modes is tx/rx Ethernet frame, tx/rx
control frame and receiving interrupt due to the lack of constant attention or processing power from the CPU.
2
The CPU interface utilizes a 8/16-bit bus in managed mode. It also supports a serial+MII, serial only, and an I C
interface, which provides an easy and lower cost way to configure the system for reduced management.
Supported CPU interface modes are
Operation Mode
16-bit CPU
ISA Interface
Serial
MII
I²C
16-bit
8-bit
NA
NA
NA
NA
Yes
No
No
NA
NA
No
No
Yes
8-bit CPU
NA
Serial with MII interface
Lightly Managed Serial
Unmanaged Serial
Yes
Yes
Yes
NA
NA
Table 6 - Supported CPU interface modes
1. 16-bit CPU interface similar to the Industry Standard Architecture (ISA) specification.
2. 8-bit CPU interface similar to ISA.
3. Serial with MII. A synchronous serial interface (SSI) bus is used for accessing the configuration register and
control frame. MII is used for sending and receiving CPU packets.
4. Lightly Managed Serial. Configuration registers access, Control frame and CPU transmit/receive packets are
sent through a synchronous serial interface (SSI) bus.
5. Unmanaged Serial. The device can be configured by EEPROM using an I²C interface at bootup, or via a syn-
chronous serial interface (SSI) otherwise. All configuration registers and internal control blocks are accessible
by the interface. However, the CPU cannot receive or transmit frames nor will it receive any interrupt informa-
tion.
The CPU interface provides for easy and effective management of the switching system.
Figure 3 on page 27 provides an overview of the 8/16-bit interface. Figure 4 on page 28 provides an overview of the
SSI interface. Figure 5 on page 29 provides an overview of the SSI+MII interface.
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Processor
3-bit Address Bus 8/16-bit Data Bus
Address
I/O Data MUX
Control
Command 2
Reg
Config Data
Reg
(Addr = 2)
Command/
Status Reg
(Addr = 4)
Interrupt
Reg
(Addr = 5)
Control
Command 1 Reg
(Addr = 6)
Index Reg 1
(Addr = 1)
Index Reg 0
(Addr = 0)
CPU Frame Reg
(Addr = 3)
(Addr = 7)
8/16-bit Data Bus
16-bit Address
8-bit Data Bus
8/16-bit Data Bus
Control
Command 1
Transmit
FIFO
frame
Internal
Registers
Inderect
Access
Contro
Control
Command 2
Transmit
FIFO
nsmit
CPU frame
Receive
FIFO
Comman
Receiv
FIFO
IFO
Interrupt
Figure 3 - Overview of the 8/16-bit Interface
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Processor
Serial Out Serial In
Strobe Interrupt
Synchronous Serial Interface
3-bit Address Bus
INT CS W R
16-bit Data Bus
Address
I/O Data MUX
Control
Command 2
Reg
Config Data
Reg
(Addr = 2)
Command/
Status Reg
(Addr = 4)
Interrupt
Reg
(Addr = 5)
Control
Command 1 Reg
(Addr = 6)
Index Reg 1
(Addr = 1)
Index Reg 0
(Addr = 0)
CPU Frame Reg
(Addr = 3)
(Addr = 7)
8/16-bit Data Bus
16-bit Address
8-bit Data Bus
8/16-bit Data Bus
Control
Command 1
Transmit
FIFO
frame
Internal
Registers
Inderect
Access
Contro
Control
Command 2
Transmit
FIFO
nsmit
CPU frame
Receive
FIFO
Comman
Receiv
FIFO
IFO
Interrupt
Figure 4 - Overview of the SSI Interface
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
Processor
Interrupt
Tclk Txd Txen
Rxd Rxdv Rclk
Serial Out Serial In
Strobe
MII Interface
Synchronous Serial Interface
3-bit Address Bus
INT CS W R
16-bit Data Bus
Address
I/O Data MUX
Control
Command 2
Reg
Config Data
Reg
(Addr = 2)
Command/
Status Reg
(Addr = 4)
Interrupt
Reg
(Addr = 5)
Control
Command 1 Reg
(Addr = 6)
Index Reg 1
(Addr = 1)
Index Reg 0
(Addr = 0)
(Addr = 7)
8-bit Data Bus
8/16-bit Data Bus
Control
8/16-bit Data Bus
frame
16-bit Address
Internal
Registers
Inderect
Access
Contro
Control
Command 2
Transmit
FIFO
Command 1
nsmit
CPU frame
Receive
FIFO
Comman
Receiv
FIFO
Transmit
FIFO
IFO
Interrupt
Figure 5 - Overview of the SSI+MII Interface
3.1 Register Configuration, Frame Transmission, and Frame Reception
3.1.1 Register Configuration
The ZL50410 has many programmable parameters, covering such functions as QoS weights, VLAN control, and
port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters.
The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers,
as follows:
•
If operating in 8-bit interface mode, two “index” registers (addresses 000b and 001b) need to be written, to
indicate the desired 16-bit register address. In 16-bit mode, only one register (address 000b) needs to be
written for the desired 16-bit register address.
•
In serial mode, the address, command and data are shifted in serially. To access the configuration registers,
only one “index” register (addresses 000b) needs to be written with the configuration register address. The
desired data can be written into or read from the “data” register (address 010b).
•
For example, if “XX” is required to be written to register “YY”, a write of “YY” is required to write to
address “000b” (Index register). Then, a write of “XX” is required to write to address “010b” (Data
Register). This completes the register write and register “YY” will contain the value of “XX”.
•
To indirectly configure the register addressed by the index register(s), a “data” register (address 010b) must
be written with the desired 8-bit data.
•
The ZL50410 supports special register-write in serial and 16-bit mode. This allows CPU to write to two
consecutive configuration registers in a single write operation. By writing to bit[14] of configuration
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
register address, CPU can write 16-bit data to address 010b. Lower 8 bit of data is for the address
specified in index register and upper 8 bit of data is for the address + 1. In 8-bit mode, this special feature
will be ignored.
15
14
0
13
12
11
INC
R/W
SP
W
Reserved
12 Bit Register Address
•
•
Similarly, to read the value in the register addressed by the index register(s), the “data” register can now
simply be read.
The ZL50410 supports an incremental read/write. If CPU requires to read or write to the configuration
registers incrementally, CPU only has to write to index register once with the MSB of configuration register
address set and then CPU can continuously reading or writing to “data” register (010b).
In summary, access to the many internal registers is carried out simply by directly accessing only two registers –
one register to indicate the index of the desired parameter, and one register to read or write a value. Of course,
because there is only one bus master, there can never be any conflict between reading and writing the
configuration registers.
3.1.2 Rx/Tx of Standard Ethernet Frames
In serial mode with MII, the MII interface is used for CPU to transmit and receive Ethernet frames. In 8/16-bit or
serial only mode, the Ethernet frame is transmitted and received through the CPU interface. There is no ability to
send/receive Ethernet frames in unmanaged mode.
To transmit a frame from the CPU in 8/16-bit or serial only mode:
•
The CPU writes to the “data frame” register (address 011) with the frame size, destination port number, and
frame status. After writing all the transmitting status bytes, it then writes the data it wants to transmit
(minimum 64 bytes).
•
The ZL50410 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact
that the frame originated from the CPU.
To receive a frame into the CPU in 8/16-bit or serial only mode:
•
•
The CPU receives an interrupt when an Ethernet frame is available to be received.
Frame information arrives first in the data frame register. This includes source port number, frame size, and
VLAN tag.
•
The actual data follows the frame information. The CPU uses the frame size information to read the frame
out.
To transmit a frame from the CPU with MII interface:
•
•
•
ZL50410 acts as a PHY to provide receive clock (RXCLK) to CPU so the CPU will depend on this receive
clock to send packets to ZL50410
ZL50410 has the ability to halt the receive clock if the receive FIFO of ZL50410 is overflow. Transmitting from
CPU to ZL50410 will resume once the receive FIFO of ZL50410 is no longer overflow
Follow the standard Ethernet transmission format. CPU assert receive data valid (RXDV) before transmitting
data to ZL50410 and de-assert RXDV after transmitting the last data
To receive a frame into the CPU with MII interface:
•
•
•
ZL50410 acts as a PHY to provide transmit clock (TXCLK) to CPU so the CPU will depend on the transmit
clock to receive packets from ZL50410
ZL50410 has the ability to halt the transmit clock if the transmit FIFO of ZL50410 is under-run. CPU will
resume receiving packets from ZL50410 once the transmit FIFO of ZL50410 is no longer under-run
Follow the standard Ethernet transmission format. CPU will see transmit enable (TXEN) be asserted by
ZL50410 and CPU can start receiving data. CPU will stop receiving data once TXEN is de-asserted by
ZL50410.
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Data Sheet
In summary, in 8/16-bit or serial only mode, receiving and transmitting frames to and from the CPU is a simple
process that uses one direct access register only. In serial mode with MII interface, the CPU will be allowed to
transmit and receive frames using standard IEEE 802.3 Ethernet transmission format.
The details of sending an Ethernet Frame via the CPU interface is described in the Processor Interface Application
Note, ZLAN-26.
3.1.3 Control Frames
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle
special “Control frames,” generated by the ZL50410 and sent to the CPU. These proprietary frames are related to
such tasks as statistics collection, MAC address learning, and aging, etc… All Control frames are up to 40 bytes
long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that
the register accessed is the “Control frame data” register (address 111).
Specifically, there are the following types of control frames generated by the CPU and sent to the ZL50410:
•
•
•
•
•
•
•
•
•
•
•
Memory read request
Memory write request
Learn Unicast MAC address
Delete Unicast MAC address
Search Unicast MAC address
Learn IP Multicast address
Delete IP Multicast address
Search IP Multicast address
Learn Multicast MAC address
Delete Multicast MAC address
Search Multicast MAC address
Note: Memory read and write requests by the CPU may include all internal memories which include statistic
counters, MAC address control link table and the 2Mbit (256KB) memory block.
In addition, the following types of Control frames are generated by the ZL50410 and sent to the CPU:
•
•
•
•
•
•
•
•
•
Interrupt CPU when statistics counter rolls over
Response to memory read request from CPU
Learn Unicast MAC address
Delete Unicast MAC address
Delete Multicast MAC address
Delete IP Multicast address
Response to search Unicast MAC address request from CPU
Response to search IP Multicast address request from CPU
Response to search Multicast MAC address request from CPU
The format of the Control Frame is described in the Processor Interface application note, ZLAN-26.
3.2 I2C Interface
The I²C interface serves the function of configuring the ZL50410 at boot time. The master is the ZL50410, and the
slave is the EEPROM memory.
The I²C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure
6 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to “ZL50410
Register Description” on page 60 for I²C address for each register.
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ZL50410
Data Sheet
START
SLAVE ADDRESS
R/W
ACK
DATA 1 (8bits)
ACK
DATA 2
ACK
DATA M
ACK
STOP
Figure 6 - Data Transfer Format for I²C Interface
3.2.1 Start Condition
Generated by the master (in our case, the ZL50410). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I²C bus is
free, both lines are High.
3.2.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
3.2.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
3.2.4 Acknowledgment
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull-down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let
the master generate the Stop condition.
3.2.5 Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB first.
3.2.6 Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition
occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
3.3 Synchronous Serial Interface
The synchronous serial interface (SSI) serves the function of configuring the ZL50410 not at boot time but via a PC.
The PC serves as master and the ZL50410 serves as slave. The protocol for the synchronous serial interface is
nearly identical to the I²C protocol. The main difference is that there is no acknowledgment bit after each byte of
data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time.
3 ID bits are used to allow up to eight ZL50410 devices to share the same synchronous serial interface. The ID of
each device can be setup by bootstrap.
To reduce the number of signals required, the register address, command and data are shifted in serially through
the DATAIN pin. STROBE- pin is used as the shift clock. DATAOUT pin is used as data return path.
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Data Sheet
Each command consists of four parts.
•
•
•
•
START pulse
Register Address
Read or Write command
Data to be written or read back
Write operation can be aborted in the middle by sending an ABORT pulse to the ZL50410. Read operation can only
be aborted before issuing the read command to the ZL50410.
A START command is detected when DATAIN is sampled high when STROBE- rise and DATAIN is sampled low
when STROBE- fall.
An ABORT command is detected when DATAIN is sampled low when STROBE- rise and DATAIN is sampled high
when STROBE- fall.
3.3.1 Write Command
All registers in ZL50410 can be modified through this synchronous serial interface. Once the data has been sent,
two extra STOBE clocks must be generated to indicate the end of the write command. The DATAIN line should be
held high for these two pulses.
STROBE-
2 Extra clocks after last
transfer
DATAIN
ID0 ID1 ID2
D12 D13 D14 D15
A0 A1 A2
ADDR
W
D0 D1 D2 D3 ...
START
ID
CMD
DATA
Figure 7 - Serial Interface Write Command Functional Timing
3.3.2 Read Command
All registers in ZL50410 can be read through this synchronous serial interface.
STROBE-
DATAIN
ID0 ID1 ID2
A0 A1 A2
ADDR
R
START
CMD
DATA
...
ID
DATAOUT
D12 D13 D14 D15
D0 D1 D2
Figure 8 - Serial Interface Read Command Functional Timing
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4.0 Data Forwarding Protocol
4.1 Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available, because of advance buffer reservations.
The memory (SRAM) interface is a 64-bit bus, connected to internal memory block. The Receive DMA (RxDMA) is
responsible for multiplexing the data and the address. On a port’s “turn”, the RxDMA will move 8 bytes (or up to the
end-of-frame) from the port’s associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response
queue of the frame engine when done. Among other information, the search engine will have resolved the
destination port of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward. But first, the TxQ manager has to decide
whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the
destination. If the frame is not dropped, then the TxQ manager links the frame’s FCB to the correct
per-port-per-class TxQ. The switch response will come with 8 classified results. The TxQ manager will map this
result into the per-port-per-class queue. Unicast TxQ’s are linked lists of transmission jobs, represented by their
associated frames’ FCB’s. There is one linked list for each transmission class for each port. There are 2
transmission classes for each of the 8 RMAC ports, and 4 classes for the GMAC and CPU ports – a total of 24
unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a
port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for
another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among
the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling
algorithm.
The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port’s turn, the
TxDMA will move 8 bytes (or up to the EOF) from memory into the port’s associated TxFIFO. After reading the EOF,
the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release
requests.
The frame is transmitted from the TxFIFO to the line.
4.2 Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop
can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is
dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of
the multicast packet’s destinations. If so, then the frame is dropped at some destinations but not others, and the
FCB is not released.
If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast
queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames).
There are 2 multicast queues for each of the 8 RMAC ports. There are 4 multicast queues for the GMAC and CPU
ports. The mapping from the classified result to the priority queue is the same as the unicast traffic. By default, for
the RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the GMAC
and CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping
can be modified through memory configuration command. The multicast queue that is in FIFO format shares the
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Data Sheet
space in the internal memory block. The size and starting address can also be programmed through memory
configuration command.
During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one
logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release
only after the EOF for the multicast frame has been read by all ports to which the frame is destined.
4.3 Frame Forwarding To and From CPU
Frame forwarding from the CPU port to a regular transmission port is nearly the same as forwarding between
transmission ports. The only difference is that the physical destination port must be indicated in addition to the
destination MAC address.
Frame forwarding to the CPU port is nearly the same as forwarding to a regular transmission port. The only
difference is in frame scheduling.
Instead of using the patent-pending Zarlink Semiconductor scheduling
algorithms, scheduling for the CPU port is simply based on strict priority. That is, a frame in a high priority queue will
always be transmitted before a frame in a lower priority queue. There are four output queues to the CPU and one
receive queue.
5.0 Search Engine
5.1 Search Engine Overview
The ZL50410 search engine is optimized for high throughput searching, with enhanced features to support:
•
•
•
•
•
•
•
•
•
•
Up to 4 K of Unicast/Multicast MAC addresses and IP Multicast MAC addresses
Up to 4 K VLANs
Private VLAN Edge (protected ports) support
Up to 8 groups of port trunking
Traffic classification into 2 (or 4 for GMAC) transmission priorities, and 2 drop precedence levels
Packet filtering based on MAC address, Protocol or Logical Port number
Security
Up to 4 K IP Multicast groups
Individual Flooding, Broadcast, Multicast Storm Control
MAC address learning and aging
5.2 Basic Flow
Shortly after a frame enters the ZL50410 and is written to the Frame Data Buffer (FDB), the frame engine generates
a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame,
which contain all the necessary information for the search engine to perform its task. When the search engine is
done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for
scheduling and forwarding.
In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch
request. Among the information extracted are the source and destination MAC addresses, the packet’s VLAN ID,
and whether the frame is unicast or multicast or broadcast. Requests are sent to the SRAM to locate the associated
entries in the MCT table.
When all the information has been collected from the SRAM, the search engine has to compare the MAC address
on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on
the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If
the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or
flooding (destination MAC address unknown).
In addition, VLAN information is used to select the correct set of destination ports for the frame (for multicast), or to
verify that the frame’s destination port is associated with the VLAN (for unicast).
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If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port
number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the
source and destination MAC addresses.
When all the information is compiled, the switch response is generated, as stated earlier. The search engine also
interacts with the CPU with regard to learning and aging.
5.3 Search, Learning, and Aging
5.3.1 MAC Search
The search block performs source MAC address and destination MAC address (or destination IP address for IP
multicast) searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be
examined, and so on until a match is found or the end of the list is reached.
In tag-based VLAN mode, if the frame is unicast, and the frame's destination port is recognized as a member of the
VLAN, then the frame is forwarded to that port; otherwise, the frame is forwarded to all the members in the VLAN
domain. If the frame is multicast or broadcast, the frame is forwarded to all the members in the VLAN. Moreover, if
port trunking is enabled, this block selects the destination port (among those in the trunk group). In private VLAN
Edge (protected ports) mode, the private VLAN domain is used for final qualification at the egress port.
In port based VLAN mode, a bit map is used to determine whether the frame should be forwarded to the outgoing
port. The main difference in this mode is that the bit map is not dynamic. Ports cannot enter and exit groups
because of real-time learning made by a CPU.
The MAC search block is also responsible for updating the source MAC address timestamp used for aging.
5.3.2 Learning
The learning module learns new MAC addresses and performs port change operations on the MCT database. The
goal of learning is to update this database as the networking environment changes over time.
When CPU reporting is enabled, learning and port change will be performed when the CPU request queue has
room, and a “Learn MAC Address” message is sent to the CPU.
5.3.3 Aging
Aging time is controlled by register 400h and 401h.
The aging module scans and ages MCT entries based on a programmable “age out” time interval. As we indicated
earlier, the search module updates the source MAC address timestamps for each frame it processes. When an
entry is ready to be aged, the entry is removed from the table, and a “Delete MAC Address” message is sent to
inform the CPU.
Supported MAC entry types are: dynamic, static, source filter, destination filter, IP multicast, source and destination
filter, secure and multicast MAC address. Only dynamic entries can be aged; all others are static. The MAC entry
type is stored in the “status” field of the MCT data structure.
5.4 MAC Address Filtering
The ZL50410's implementation of intelligent traffic switching provides filters for source and destination MAC
addresses. This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and
broadcast traffic.
Broadcast, unknown unicast or unknown multicast MAC address and unknown IP multicast address can also be
filter on per VLAN basis.
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MAC address filtering allows the ZL50410 to block an incoming packet to an interface when it sees a specified MAC
address in either the source address or destination address of the incoming packet. For example, if your network is
congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address
and restore network flow, while you troubleshoot the problem.
5.5 Protocol Filtering
Packet filtering can be performed based on protocol type field in the packets. Up to eight protocols can be
programmed to filter or allow packet to pass through the switch.
5.6 Logical Port Filtering
Similar to protocol filtering, if the packet’s logical ports match the programmable registers, the packet can be filtered
or passed through the switch. Up to eight programmable ports and one ranges can be assigned.
5.7 Quality of Service
Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over
various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by
some real-time and interactive traffic), and improved loss characteristics.
Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate
traffic, a service level known as “best effort” attempts to get all the packets to their intended destinations with
minimum delay; however, there are no guarantees. In a congested network or when a low-performance
switch/router is overloaded, “best effort” becomes unsuitable for delay-sensitive traffic and mission-critical data
transmission.
The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and
multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously
plagued such “best effort” networking systems. QoS provides Ethernet networks with the breakthrough technology
to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth.
Extensive core QoS mechanisms are built into the ZL50410 architecture to ensure policy enforcement and
buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port.
In the ZL50410, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly.
The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is
provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which
the frames and packets belong. For example, the overall service given to frames and packets in the premium class
will be better than that given to the standard class; the premium class is expected to experience lower loss rate or
delay.
The ZL50410 supports the following QoS techniques:
•
•
•
In a port-based setup, any station connected to the same physical port of the switch will have the same
transmit priority.
In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be
mapped to different queues in the switch to provide QoS.
In a TOS/DS-based set up, TOS stands for “Type of Service” that may include “minimize delay,” “maximize
throughput,” or “maximize reliability.” Network nodes may select routing paths or forwarding behaviours that
are suitably engineered to satisfy the service request.
•
In a logical port-based set up, a logical port provides the application information of the packet. Certain
applications are more sensitive to delays than others; using logical ports to classify packets can help speed
up delay sensitive applications, such as VoIP.
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5.8 Priority Classification Rule
Figure 9 shows the ZL50410 priority classification rule.
Yes
Fix Port Priority?
Use Default port settings
No
TOS Precedence over VLAN?
Yes
(QOSC Register bit 5)
No
Yes
No
Use VLAN
priority
VLAN Tag?
IP Frame?
No
Yes
Yes
No
IP Frame?
Use Logical Port?
Use TOS
No
Yes
Use Default port settings
Use logical port
Figure 9 - Priority Classification Rule
5.9 Port and Tag Based VLAN
The ZL50410 supports two models for determining and controlling how a packet gets assigned to a VLAN: port
priority and tag -based VLAN.
5.9.1 Port-Based VLAN
An administrator can use the PVMAP Registers to configure the ZL50410 for port-based VLAN (see “Register
Definition” on page 60). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the
Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50410 determines the VLAN membership of
each packet by noting the port on which it arrives. From there, the ZL50410 determines which outgoing port(s)
is/are eligible to transmit each packet, or whether the packet should be discarded.
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Data Sheet
Destination Port Numbers Bit Map
Port Registers
9
0
…
2
1
1
1
0
0
Register for Port #0
PVMAP00_0[7:0] to PVMAP00_1[1:0]
Register for Port #1
PVMAP01_0[7:0] to PVMAP01_1[1:0]
0
0
1
0
0
0
1
0
Register for Port #2
PVMAP02_0[7:0] to PVMAP02_1[1:0]
…
Register for Port #9
0
0
0
0
PVMAP09_0[7:0] to PVMAP09_1[1:0]
Table 7 - Port-Based VLAN Mapping
For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming
port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port.
In this example:
•
•
•
Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2.
Data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2.
Data packets received at port #2 are NOT eligible to be sent to ports 0 and 1.
5.9.2 Tag-Based VLAN
The ZL50410 supports the IEEE 802.1q specification for “tagging” frames. The specification defines a way to
coordinate VLANs across multiple switches. In the specification, an additional 4-octet header (or “tag”) is inserted in
a frame after the source MAC address and before the frame type. 12 bits of the tag are used to define the VLAN ID.
Packets are then switched through the network with each ZL50410 simply swapping the incoming tag for an
appropriate forwarding tag rather than processing each packet's contents to determine the path. This approach
minimizes the processing needed once the packet enters the tag-switched network. In addition, coordinating VLAN
IDs across multiple switches enables VLANs to extend to multiple switches.
Up to 4 K VLANs are supported in the ZL50410. When tag-based VLAN is enabled, each MAC address is learned
with it associated VLAN.
See IEEE 802.1Q VLAN Setup application note, ZLAN-51, for more information.
5.9.3 VLAN Stacking (Q-in-Q)
The ZL50410 partially supports VLAN stacking, also called IEEE 802.1Q-in-Q. This technology allows an additional
VLAN tag, called a provider VLAN tag, to be inserted into an existing IEEE 802.1Q tagged Ethernet frame. This
technology has been widely adapted in Metro Ethernet applications since it provides a very cost-effective solution
to transport multiple customers' VLAN across the service provider's MAN/WAN without interfering each other. The
below figure illustrates the IEEE 802.1Q frame and the Q-in-Q frame, where the provider VLAN tag is inserted in
front of the IEEE 802.1Q tag.
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Data Sheet
IEEE 802.1Q Tagged
Ethernet Frame
IEEE
802.1Q Tag
VLAN
Dest MAC
(6 Bytes)
Source MAC
(6 Bytes)
VLAN TCI
(2 Bytes)
Type/Length
(2 Byte)
Tag Protocol ID
Data
(0x8100)
Provider
IEEE 802.1Q-in-Q Tagged
Ethernet Frame
Tag
(P-VLAN)
IEEE
802.1Q Tag
VLAN
VLAN
Dest MAC
(6 Bytes)
Source MAC
(6 Bytes)
VLAN TCI
(2 Bytes)
VLAN TCI
(2 Bytes)
Type/Length
(2 Byte)
Tag Protocol ID
Tag Protocol ID
Data
(0x88A8*)
(0x8100)
IEEE 802.1Q Tag TPID = 0x8100
* Provider Tag TPID = Configurable on per device basis
Figure 10 - Q-in-Q Tagged Ethernet Frame
The value of the TPID of the Provider VLAN tag is not assigned in the IEEE 802.1ad standard. The ZL50410
provides a global configurable TPID but only supports the Extreme EtherType TPID (i.e. the stacked VLAN tag
cannot equal 0x81-00).
See Stacked VLAN application note, ZLAN-82, for more information.
5.9.4 Private VLAN Edge
The PVLAN Edge (protected port) is a feature that has only local significance to the switch (unlike Private VLANs),
and there is no isolation provided between two protected ports located on different L2 switches. A protected port
does not forward any traffic (unicast, multicast, or broadcast) to any other port that is also a protected port in the
same switch. Traffic cannot be forwarded between protected ports at L2, thus, all traffic passing between protected
ports must be forwarded through a Layer 3 (L3) device.
The ZL50410 supports private VLAN Edge by allowing each of the RMAC ports to setup a private VLAN domain,
defined by registers PVLAN_Pn. The private VLAN domain is used for final qualification at the egress port.
See Private VLAN Edge application note, ZLAN-130, for more information.
5.10 IP Multicast Switching
The ZL50410 supports IP Multicast Filtering by:
•
Passively snooping on the IGMP Query and IGMP Report packets transferred between IP Multicast Routers
and IP Multicast host groups to learn IP Multicast group members, and
•
Actively sending IGMP Query messages to solicit IP Multicast group members.
The purpose of IP multicast filtering is to optimize a switched network performance, so multicast packets will only
be forwarded to those ports containing multicast group hosts members and routers instead of flooding to all ports in
the subnet (VLAN).
The ZL50410 with IP multicast filtering/switching capability not only passively monitor IGMP Query and Report
messages, DVMRP Probe messages, PIM, and MOSPF Hello messages; they also actively send IGMP Query
messages to learn locations of multicast routers and member hosts in multicast groups within each VLAN.
See IP Multicast Switching application note, ZLAN-52, for more information.
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6.0 Frame Engine
6.1 Data Forwarding Summary
When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB.
Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast, and its
destination port or ports. On receiving the response, the Frame Engine will check all the QoS related information
and decide if this frame can be forwarded.
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a
Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling
Queue (TxSch Q) or Queues. There are 2 TxSch Q for each RMAC port (and 4 per GMAC and CPU ports), one for
each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or
adding an entry to a physical queue if multicast.
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of
the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service).
(The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The
older HOL between the two queues goes first.
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the
destination port.
6.2 Frame Engine Details
This section briefly describes the functions of each of the modules of the ZL50410 frame engine.
6.2.1 FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure.
The FCB manager is also responsible for enforcing buffer reservations and limits that will be used for QoS control
and source port flow control. The default values can be determined by referring to Section 7.6 on page 45. The
frame buffer is managed in a 128bytes block unit. During initialization, this block will link all the available blocks in a
free buffer list. When each port is ready to receive, this module hands the buffer handle to each requesting port.
The FCB manager will also link the released buffer back into the free buffer list.
The maximum buffer size can be increased from the standard 1518 bytes (1522 with VLAN tag) to up to 4 K bytes.
This is done using BUF_LIMIT, and is enabled on a per port basis via bit [1] in ECR3Pn. See Buffer Allocation
application note, ZLAN-47, for more information.
6.2.2 Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch
request.
6.2.3 RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each
frame for use by the search engine when the switch request has been made.
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6.2.4 TxQ Manager
First, the TxQ manager checks the per-class queue status and global reserved resource situation, and using this
information, makes the frame dropping decision after receiving a switch response. The dropping decision includes
the head-of-link blocking avoidance if the source port is not flow control enabled. If the decision is not to drop, the
TxQ manager links the unicast frame’s FCB to the correct per-port-per-class TxQ and updates the FCB information.
If multicast, the TxQ manager writes to the multicast queue for that port and class and also update the FCB
information including the duplicate count for this multicast frame. The TxQ manager can also trigger source port
flow control for the incoming frame’s source if that port is flow control enabled. Second, the TxQ manager handles
transmission scheduling; it schedules transmission among the queues representing different classes for a port.
Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port
control module. The detail of the QoS decision guideline is described in chapter 5.
6.2.5 Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes
start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control
module requests that the buffer be released.
6.2.6 TxDMA
The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the
port control modules.
7.0 Quality of Service and Flow Control
7.1 Model
Quality of service is an all-encompassing term for which different people have different interpretations. In general,
the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also
assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager
knows his applications, such as voice, file transfer, or web browsing, and their relative importance. The manager
can then subdivide the applications into classes and set up a service contract with each. The contract may consist
of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to
the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic
is policed or shaped, we may be able to provide additional assurances about our switch’s performance.
Table 8 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form
a fourth class with no bandwidth or latency assurances. GMAC port actually has four total transmission priorities.
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Data Sheet
TotalAssured
Bandwidth
Low Drop Probability
(low-drop)
High Drop Probability
(high-drop)
Goals
(user defined)
Highest
transmission
priority, P3
50 Mbps
Apps: phone calls, circuit
emulation.
Latency: < 1 ms.
Drop: No drop if P3 not
oversubscribed.
Apps: training video.
Latency: < 1 ms.
Drop: No drop if P3 not
oversubscribed; first P3 to drop
otherwise.
Middle
transmission
priority, P2
37.5 Mbps
12.5 Mbps
Apps: interactive apps, Web
business.
Latency: < 4-5 ms.
Drop: No drop if P2 not
oversubscribed.
Apps: non-critical interactive apps.
Latency: < 4-5 ms.
Drop: No drop if P2 not
oversubscribed; firstP2 to drop
otherwise.
Low transmission
priority, P1
Apps: emails, file backups.
Latency: < 16 ms desired, but
not critical.
Apps: casual web browsing.
Latency: < 16 ms desired, but not
critical.
Drop: No drop if P1 not
oversubscribed.
Drop: No drop if P1 not
oversubscribed; first to drop
otherwise.
Total
100 Mbps
Table 8 - Two-dimensional World Traffic
A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a
rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the
agreed-upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high
link utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade
the quality of service (QoS) received by well-behaved classes.
As Table 8 illustrates, the six traffic types may each have their own distinct properties and applications. As shown,
classes may receive bandwidth assurances or latency bounds. In the table, P3, the highest transmission class,
requires that all frames be transmitted within 1 ms, and receives 50% of the 100 Mbps of bandwidth at that port.
Best-effort (P0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any
traffic to offer. It is also possible to add a fourth class that has strict priority over the other three; if this class has
even one frame to transmit, then it goes first. In the ZL50410, each RMAC port will support two total classes, and
the GMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next
section.
In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely
lose packets. But poorly behaved users–users who send frames at too high a rate – will encounter frame loss, and
the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some
low-drop frames are dropped, and then all frames in the worst case.
Table 8 shows that different types of applications may be placed in different boxes in the traffic table. For example,
casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the
category of low-loss, low-latency traffic.
7.2 Two QoS Configurations
There are two basic pieces to QoS scheduling in the GMAC port of ZL50410: strict priority (SP) or weighted fair
queuing (WFQ). The only configuration for a RMAC and CPU port is strict priority between the queues.
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Data Sheet
7.2.1 Strict Priority
When strict priority is part of the scheduling algorithm, if a queue has any frame to transmit, it goes first. For RMAC
ports, this is an easy way to provide the different service. For all recognizable traffic, the bandwidth is guaranteed to
100% of the line rate. This scheme works as long as the overall high priority bandwidth is not over the line rate and
the latency on all the low priority traffic is don’t care. The strict priority queue in the GMAC and CPU ports is similar
to RMAC ports other than having 4 queues instead of 2 queues. The priority queue P0 can be scheduled only if the
priority queue P1 is empty, so as to priority queues P2 and P3. The lowest priority queue is treated as best effort
queue.
Because we do not provide any assurances for best effort traffic, we do not enforce latency by dropping best effort
traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the
ZL50410, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to
enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best
effort and strict priority queues when queue size is too long or global / class buffer resources become scarce.
7.2.2 Weighted Fair Queuing
In some environments – for example, in an environment in which delay assurances are not required, but precise
bandwidth partitioning on small time scales is essential, WFQ may be preferable to a strict assurance scheduling
discipline. The ZL50410 provides this kind of scheduling algorithm on GMAC port only. The user sets four WFQ
“weights” such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning
with granular within 2%.
In WFQ mode, though we do not assure frame latency, the ZL50410 still retains a set of dropping rules that helps to
prevent congestion and trigger higher level protocol end-to-end flow control.
7.3 WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified
parameters. The following table summarizes the behavior of the WRED logic.
Px > WRED_L1
Px > WRED_L2
BM Reject
High Drop
Low Drop
X%
Y%
100%
Z%
100%
100%
Table 9 - WRED Logic Behaviour
Px is the total byte count, in the priority queue x, can be the strict priority queue of RMAC ports and higher 3 priority
queues for GMAC port. The WRED logic has two drop levels, depending on the value of Px. Each drop level has
defined high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data
that can be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. All packets will be
dropped only if the system runs out of the specific buffer resource, per class buffer or per source port buffer. The
WRED thresholds of each queue can be programmed by the QOS control registers (refer to the register group 8).
See Programming QoS Registers application note, ZLAN-42, for more information.
7.4 Shaper
Although traffic shaping is not a primary function of the ZL50410, the chip does implement a shaper for every queue
in the GMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50410. If shaper is
enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict
priority scheduling.
Traffic rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then
the traffic rate transmit out of the shaped queue is 32/64 * 1000 Mbps = 500 Mbps. See Programming QoS Register
application note, ZLAN-42, for more information.
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Also, when shaping is enabled, it is possible for a queue to explode in length if fed by a greedy source. The reason
is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line
is idle. Though we do have global resource management, we do nothing other than per port WRED to prevent this
situation locally. We assume the traffic is policed at a prior stage to the ZL50410 or WRED dropping is fine and shall
restrain this situation.
7.5 Rate Control
The ZL50410 provides a rate control function on its RMAC ports. The concept is much the same as shaping, except
that it applies to both ingress and egress directions and the control is per port rather than per queue. It provides a
way of reducing the total bandwidth of all frames received from or transmitted to a port, to a rate below wire speed.
As with shaping, the maximum burst size can also be configured.
Rate control may be a valuable feature on RMAC ports in access applications where the service provider would like
to limit the traffic received and transmitted by each port independently of each other, and independently of the
physical line rate. The service provider can then provide differential pricing, based on the negotiated bandwidth
requirements for each user. In such applications of the ZL50410, the GMAC port is viewed as an uplink port, where
rate control is not desired.
See Rate Control application note, ZLAN-33, for more information.
7.6 Buffer Management
Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving
source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept
of buffer management into the ZL50410. Our buffer management scheme is designed to divide the total buffer
space into numerous reserved regions and one shared pool, as shown in Figure 11 on page 46.
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the ZL50410, its destination port and class are as yet unknown, and so the decision to drop or not needs to
be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame
drop discipline after classifying.
Three priority sections, one for each pair of the first six priority classes, ensure a programmable number of FDB
slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, a frame is stored in the
region of the FDB corresponding to its class. As we have indicated, the eight classes use only two transmission
scheduling queues for RMAC ports (four queues for the GMAC & CPU ports), but as far as buffer usage is
concerned, there are still eight distinguishable classes.
Another segment of the FDB reserves space for each of the 10 ports — 9 ports for Ethernet and one CPU port (port
number 8). Each port has it’s own programmable source port reservation. These 10 reserved regions make sure
that no well-behaved source port can be blocked by another misbehaving source port.
In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in
the three priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in
the shared pool. Once the shared pool is full the frames are allocated in the section reserved for the source port.
The following registers define the size of each section of the Frame data Buffer:
-
-
-
-
-
-
-
PR100_N - Port Reservation for RMAC Ports
PR100_CPU - Port Reservation for CPU Port
PRG - Port Reservation for GMAC Port
SFCB - Share FCB Size
C1RS - Class 1 Reserve Size (priority 2 & 3)
C2RS - Class 2 Reserve Size (priority 4 & 5)
C3RS - Class 3 Reserve Size (priority 6 & 7)
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Temporary reservation
Rpri3 Shared Pool S
Rpri1
Rpri2
Per Class
Reservation
Rp0
Rp1
Rp2
Rp3
Rp4
Rp5
Rp6
Rp7
Rp8
Rp9
Per Source Port
Reservation
(CPU)
Figure 11 - Buffer Partition Scheme
See Buffer Allocation application note, ZLAN-47, for more information.
7.6.1 Dropping When Buffers Are Scarce
As already discussed, the WRED mechanism may drop frames on output queue status. In addition to these
reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer
management is to make sure that such dropping causes as little blocking as possible. If a received frame is
dispatched to the best effort queue, the buffer management will check on the overall buffer situation plus the output
queue status to decide the frame drop condition. If the source port has not enough buffer for it, the frame will be
dropped. If the output queue reach the UCC (unicast congest control) and the shared buffer has run out, the frame
will be dropped by b%. If the output queue reach the UCC and the source port reservation is lower than the buffer
low threshold, the frame will be dropped. All the dropping functions are disabled if the source port is flow control
capable.
7.7 Flow Control Basics
Because frame loss is unacceptable for some applications, the ZL50410 provides a flow control option. When flow
control is enabled, scarcity of source port buffer space may trigger a flow control signal; this signal tells a source
port sending a packet to this switch, to temporarily hold off.
While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When
a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not,
are halted. A single packet destined for a congested output can block other packets destined for un-congested
outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high
confidence when flow control is enabled.
On the other hand, the ZL50410 will still prioritize the received frame disregarding the outgoing port flow control
capability. If a frame is classified as high priority, it is still subjected to the WRED, which means the no-loss on the
high priority queue is not guaranteed. To resolve this situation, the user may set the output port WRED threshold so
high that may never be reached, or program the priority mapping table in the queue manager to map all the traffic to
best effort queue on the flow control capable port. The first method has side impact on the global resource
management since the port may hold too much per class resource that is scarce in the system. The second
method, by nature, lost the benefit of prioritization.
See Programming Flow Control Registers application note, ZLAN-44, for more information.
7.7.1 Unicast Flow Control
For unicast frames, flow control is triggered by source port resource availability. Recall that the ZL50410’s buffer
management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a
source port’s reserved FDB slots have been used, then flow control Xoff is triggered.
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Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been
released.
Note that the ZL50410’s per-source-port FDB reservations assure that a source port that sends a single frame to a
congested destination will not be flow controlled.
7.7.2 Multicast Flow Control
Flow control for multicast frames is triggered by a global buffer counter. When the system exceeds a programmable
threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns below this threshold.
Note: If per-port flow control is on, QoS performance will be affected.
7.8 Mapping to IETF Diffserv Classes
The mapping between priority classes discussed in this chapter and elsewhere is shown below.
ZL50410
IETF
P3
P2
P1
P0
BE
NM+EF
AF0
AF1
Table 10 - Mapping to IETF Diffserv Classes for GMAC & CPU Ports
As the table illustrates, the classes of Table 10 are merged in pairs— P3 is used for network management (NM) and
expedited forwarding service (EF) frames. Classes P2 and P1 correspond to an assured forwarding (AF) group of
size 2. Finally, P0 is for best effort (BE) class.
Features of the ZL50410 that correspond to the requirements of their associated IETF classes are summarized in
the table below.
Network management (NM) and Global buffer reservation for NM and EF
Expedited forwarding (EF)
Shaper for traffic on uplink port
No dropping if admission controlled
Assured forwarding (AF)
Global buffer reservation for two AF classes
Shaper for traffic on uplink port
Random early discard, with programmable levels
Best effort (BE)
Service only when other queues are idle means that QoS not
adversely affected
Shaper for traffic on uplink port
Random early discard, with programmable levels
Traffic from flow control enabled ports automatically classified as BE
Table 11 - ZL50410 Features Enabling IETF Diffserv Standards
7.9 Failover Backplane Feature
The ZL50410 implements a hardware assisted link failure detection mechanism utilizing a Link Heart Beat (LHB)
packet. The LHB packet format is defined as a 64-byte MAC control frame with a user defined opcode. The packet
format is illustrated below:
01-80-C2-00-00-01
xx-xx-xx-xx-xx-xx
88-08
yy-yy
00-00-...
CRC
Where “xx-xx-xx-xx-xx-xx” is the source port MAC address and “yy-yy” is the special opcode defined by register
setup (LHBReg0,1). The opcode “00-01” is reserved for the flow control packet. We recommend opcode “00-12” for
the LHB packet.
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The LHB is done between two compatible MACs providing this function. A timer parameter will be set for both the
receiver and transmitter (LHBTimer).
On the transmission side, the MAC will monitor the transmission activities. If there is no activity for more than the
set period, a LHB packet will be sent to its link partner. Therefore, there should always be at least one packet
transmitted from the MAC for every period specified.
On the receiving side, the MAC will also monitor the activity. If there is no good packet received for more than 2X
the set period, an alarm will be raised to the CPU. The LHB packet is only used by the ZL50410 to reset the timeout
counter, it is ignored otherwise (i.e. not passed on within the system).
See the Failover Protection Application Note, ZLAN-43, for more information.
8.0 Port Trunking
See Port Trunking application note, ZLAN-48, for more information.
8.1 Features and Restrictions
A port group (i.e. trunk) can include up to 8 physical ports, all of the ports in a group can be in the same ZL50410 or
in multiple ZL50410 to form a fault tolerant link. There are eight trunk groups total.
Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address
and destination MAC address. Three other options include source MAC address only, destination MAC address
only, and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly.
If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN
member map.
The ZL50410 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking
group goes down, the ZL50410 can redistribute the traffic over to the remaining ports in the trunk with software
assistance.
8.2 Unicast Packet Forwarding
The search engine finds the destination MCT entry, and if the status field says that the destination port found
belongs to a trunk, then the trunk group number is retrieved.
The source port of the packet is checked against the destination trunk group. If the source port belongs to the
destination trunk group, the packet is discarded.
A hash key, based on some combination of the source and destination MAC addresses for the current packet,
selects the appropriate forwarding port, as specified in the Trunk_Hash registers. Each trunk has eight trunk_hash
registers which selects one of the potential eight outgoing ports. The hash key provides a pseudo flow identifier
which force the same flow to the same destination flow. As a result, the packet will always arrive in order.
8.3 Multicast Packet Forwarding
For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the
packet based on the VLAN and hash key.
Three functions are required in order to distribute multicast packets to the appropriate destination ports in a port
trunking environment.
•
•
•
Determining the VLAN group it is forwarding port per group.
The source port/group must be excluded from the forwarding.
Select one port per trunk group to forward the packet to. This selection is based on hash key described in
previous section.
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For example, port 0,1 and 2 belong to trunk group 0 and port 3 and 4 belong to trunk group 1. A single VLAN is
established in this system with port 0,1,2,3,4,5 and 6 as the members in the VLAN. When a multicast packet is sent
in from port 3, the ZL50410 select port 0,1,2,3,4,5 and 6 as potential destination based on the VLAN. Then port 3
and 4 are removed because they belong to the source port group (trunk group 1). Two ports from trunk group 0 will
be removed based on the hash key. In this example, we assume port 0 and 1 are removed. As a result, port 2,5 and
6 are the only outgoing ports for this multicast packet.
9.0 Traffic Mirroring
See Traffic Mirroring application note, ZLAN-50, for more information.
9.1 Mirroring Features
Packets can be mirrored (duplicated) for network monitor purpose and/or network debug purpose. Three types of
mirroring is available in ZL50410.
1. Source or Destination MAC address based
2. Flow based
3. Port based
In source or destination mac address based mirroring, the “M” bit of the mirroring MAC address in the MCT is set.
Also, the user need to specify the mirroring MAC address is source or destination of the packet. If source is
selected, any packet received with the mirroring MAC address as source MAC address will be copied to the
mirrored port. In the same way, if destination is selected, any packet received with mirroring MAC address as
destination MAC address will be copied to the mirrored port.
In flow based mirroring, a flow is established based on the source and destination mac address pair. When
enabled, a packet with source and destination address match the pre-programmed source and destination mac
address pair will be copied to the mirrored port. In reverse direction (source and destination match pre programmed
destination and source), the flow can also be enabled and the frame will be copied to the mirrored port.
In port based mirroring, traffic from any RMAC port can be mirrored to any RMAC port. The traffic from the source
port can be either ingress or egress traffic. Up to two ports can be setup as mirrored ports. As a result, the traffic
(both ingress and egress) of a specific port can be monitored by setting up both mirrored ports. Once a port is setup
as mirrored port, it cannot be used for regular traffic.
The mirrored port can be any port in the ZL50410.
9.2 Using port mirroring for loop back
To perform remote loop back test, port mirroring can be used to bounce back the packet to the source port to check
the data path.
The CPU needs to setup the remote device through the command channel to enable port mirroring in the remote
device. A CPU packet is send to the port in test in Device A. The packet will be forwarded to the test port, external
cable, the destination port in Device B, and loop back to itself, back to the cable and go back to Device A and the
CPU. This way, the whole channel can be tested.
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CPU
DEVICE B
DEVICE A
Figure 12 - Remote Loopback Test
10.0 Clocks
10.1 Clock Requirements
10.1.1 System Clock (SCLK) speed requirement
SCLK is the primary clock for the ZL50410 device. The speed requirement is based on the system configuration.
Below is a table for a few configuration.
Minimum SCLK speed
Configuration
required
8 Port 10/100M + 1 port 1000M
6-9 ports 10/100M
100 MHz
50 MHz
25 Mhz
1-5 ports 10/100M
Table 12 - SCLK Speed Requirements
10.1.2 RMAC Reference Clock (M_CLK) speed requirement
M_CLK is a 50 MHz clock used for the RMAC ports (ports 0-7) and CPU port (port 8).
If none of the RMAC ports are configured in RMII mode or Reverse MII mode, a different clock frequency can be
applied to M_CLK, as long as it's less than 50 MHz. In this case, register USD must be set to provide an internal
1usec timing.
10.1.3 GMAC Reference Clock (GREF_CLK) speed requirement
GREF_CLK is a 125 MHz reference clock required for the GMAC port (port 9).
If the device is in a 9 port 10/100 configuration only, GREF_CLK can be a lower frequency clock and can be
connected to M_CLK to reduce the number of clock sources.
If port 9 is not being used, GREF_CLK can be left unconnected.
10.1.4 JTAG Test Clock (TCK) speed requirements
TCK is a clock used for the JTAG port. The frequency on this clock can vary. Refer to “JTAG (IEEE 1149.1-2001)”
on page 135 for the frequency range.
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10.2 Clock Generation
10.2.1 MDC
MDC is used for the MII Management Interface and clocks data on MDIO. It is generated by the device from
M_CLK and is equal to 500 kHz (M_CLK/100). If a different speed clock other than 50MHz is used on M_CLK, the
USD register must be programmed to reset MDC.
10.2.2 SCL
SCL is used for the I2C interface and clocks data on SDA. It is generated by the device from M_CLK and is equal to
50kHz (M_CLK/1000). If a different speed clock other than 50MHz is used on M_CLK, the USD register must be
programmed to reset SCL.
10.2.3 Ethernet Interface Clocks
If the RMAC ports are configured in Reverse MII mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 100M mode or M_CLK/20 for 10M mode. M_CLK needs to be a 50 MHz clock in this mode.
If the RMAC ports are configured in Reverse GPSI mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 10M mode. M_CLK needs to be a 20 MHz clock in this mode and USD must be programmed
accordingly.
For the CPU port in serial+MII mode, TXCLK and RXCLK are generated from M_CLK and are equal to M_CLK/2 for
100M mode or M_CLK/20 for 10M mode. M_CLK needs to be a 50MHz clock in this mode.
The gigabit port generates an external TXCLK interface clock in GMII mode. It is equal to the 125 MHz GREF_CLK.
If the GMAC port is configured in Reverse MII mode, RXCLK is generated from GREF_CLK and is equal to
GREF_CLK/2 for 100M mode (no support for 10M Reverse MII mode). GREF_CLK needs to be a 50 MHz clock in
this mode.
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11.0 Hardware Statistics Counters
11.1 Hardware Statistics Counters List
ZL50410 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these
counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the
CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay
exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager). The
following is the wrapped signal sent to the CPU through the command block.
63
30 29
Status Wrapped Signal
0
Other Status Bits
Bytes Sent (D)
B[0]
0-d
1-L
1-U
2-I
Unicast Frame Sent
B[1]
Frame Send Fail
B[2]
Flow Control Frames Sent
Non-Unicast Frames Sent
Bytes Received (Good and Bad) (D)
Frames Received (Good and Bad) (D)
Total Bytes Received (D)
B[3]
B[4]
2-u
3-d
4-d
5-d
6-L
6-U
7-l
B[5]
B[6]
B[7]
Total Frames Received
B[8]
Flow Control Frames Received
Multicast Frames Received
Broadcast Frames Received
Frames with Length of 64 Bytes
Jabber Frames
B9]
B[10]
B[11]
B[12]
B[13]
B[14]
B[15]
B[16]
B[17]
B[18]
B[19]
7-u
8-L
8-U
9-L
9-U
A-l
Frames with Length Between 65-127 Bytes
Oversize Frames
Frames with Length Between 128-255 Bytes
A-u
B-l
Frames with Length Between 256-511 Bytes
Frames with Length Between 512-1023 Bytes
Frames with Length Between 1024-1528 Bytes
B-u
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Fragments
Alignment Error
Undersize Frames
CRC
B[20]
B[21]
B[22]
B[23]
B[24]
B[25]
B[26]
B[27]
B[28]
B[29]
C-l
C-U1
C-U
D-l
Short Event
Collision
D-u
E-l
Drop
E-u
F-l
Filtering Counter
Delay Exceed Discard Counter
Late Collision
F-U1
F-U
Notation: X-Y
Address in the contain memory
Size and bits for the counter
X:
Y:
D Word counter
d:
24 bits counter bit [23:0]
8 bits counter bit [31:24]
8 bits counter bit [23:16]
16 bits counter bit [15:0]
16 bits counter bit [31:16]
L:
U:
U1:
l:
u:
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11.2 IEEE 802.3 HUB Management (RFC 1516)
11.2.1 Event Counters
11.2.1.1 ReadableOctet
Counts number of bytes (i.e. octets) contained in good valid frames received.
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
(< 1518 bytes if not VLAN Tagged)
(< BUF_LIMIT if enabled for this port)
No FCS (i.e. checksum) error
No collisions
11.2.1.2 ReadableFrame
Counts number of good valid frames received.
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
(< 1518 bytes if not VLAN Tagged)
(< BUF_LIMIT if enabled for this port)
No FCS error
No collisions
11.2.1.3 FCSErrors
Counts number of valid frames received with bad FCS.
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
(< 1518 bytes if not VLAN Tagged)
(< BUF_LIMIT if enabled for this port)
No framing error
No collisions
11.2.1.4 AlignmentErrors
Counts number of valid frames received with bad alignment (not byte-aligned).
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
(< 1518 bytes if not VLAN Tagged)
(< BUF_LIMIT if enabled for this port)
No framing error
No collisions
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11.2.1.5 FrameTooLongs
Counts number of frames received with size exceeding the maximum allowable frame size.
Frame size:
> 64 bytes,
> 1522 bytes if VLAN Tagged;
(> 1518 bytes if not VLAN Tagged)
(> BUF_LIMIT if enabled for this port)
FCS error:
don’t care
don’t care
Framing error:
No collisions
11.2.1.6 ShortEvents
Counts number of frames received with size less than the length of a short event.
Frame size:
< 10 bytes
FCS error:
don’t care
don’t care
Framing error:
No collisions
11.2.1.7 Runts
Counts number of frames received with size under 64 bytes, but greater than the length of a short event.
Frame size:
> 10 bytes,
< 64 bytes
FCS error:
don’t care
don’t care
Framing error:
No collisions
11.2.1.8 Collisions
Counts number of collision events.
Frame size:
any size
11.2.1.9 LateEvents
Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes).
Frame size:
any size
Events are also counted by collision counter
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11.2.1.10 VeryLongEvents
Counts number of frames received with size larger than Jabber Lockup Protection Timer (TW3).
Frame size:
> Jabber
11.2.1.11 DataRateMisatches
For repeaters or HUB application only.
11.2.1.12 AutoPartitions
For repeaters or HUB application only.
11.2.1.13 TotalErrors
Sum of the following errors:
•
•
•
•
•
•
•
FCSErrors
AlignmentErrors
FrameTooLong
ShortEvents
LateEvents
VeryLongEvents
DataRateMisatches
11.3 IEEE 802.1 Bridge Management (RFC 1286)
11.3.1 Event Counters
11.3.1.1 InFrames
Counts number of frames received by this port or segment.
Note: A frame received by this port is only counted by this counter if and only if it is for a protocol being processed
by the local bridge function.
11.3.1.2 OutFrames
Counts number of frames transmitted by this port.
Note: A frame transmitted by this port is only counted by this counter if and only if it is for a protocol being
processed by the local bridge function.
11.3.1.3 InDiscards
Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process.
11.3.1.4 DelayExceededDiscards
Counts number of frames discarded due to excessive transmit delay through the bridge.
11.3.1.5 MtuExceededDiscards
Counts number of frames discarded due to excessive size.
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11.4 RMON – Ethernet Statistic Group (RFC 1757)
11.4.1 Event Counters
11.4.1.1 Drop Events
Counts number of times a packet is dropped, because of lack of available resources. DOES NOT include all packet
dropping -- for example, random early drop for quality of service support.
11.4.1.2 Octets
Counts the total number of octets (i.e. bytes) in any frames received.
11.4.1.3 BroadcastPkts
Counts the number of good frames received and forwarded with broadcast address.
Does not include non-broadcast multicast frames.
11.4.1.4 MulticastPkts
Counts the number of good frames received and forwarded with multicast address.
Does not include broadcast frames.
11.4.1.5 CRCAlignErrors
Counts number of frames received with FCS or alignment errors
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
(< 1518 bytes if not VLAN Tagged)
(< BUF_LIMIT if enabled for this port)
No collisions:
11.4.1.6 UndersizePkts
Counts number of frames received with size less than 64 bytes.
Frame size:
< 64 bytes,
No FCS error
No framing error
No collisions
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
11.4.1.7 OversizePkts
Counts number of frames received with size exceeding the maximum allowable frame size.
Frame size:
> 1522 bytes if VLAN Tagged;
(> 1518 bytes if not VLAN Tagged)
(> BUF_LIMIT if enabled for this port)
don’t care
FCS error
Framing error
No collisions
don’t care
11.4.1.8 Fragments
Counts number of frames received with size less than 64 bytes and with bad FCS.
Frame size:
< 64 bytes
Framing error
No collisions
don’t care
11.4.1.9 Jabbers
Counts number of frames received with size exceeding maximum frame size and with bad FCS.
Frame size:
> 1522 bytes if VLAN Tagged;
(> 1518 bytes if not VLAN Tagged)
(> BUF_LIMIT if enabled for this port)
don’t care
Framing error
No collisions
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
11.4.1.10 Collisions
Counts number of collision events detected.
Only a best estimate since collisions can only be detected while in transmit mode, but not while in receive mode.
Frame size: any size
11.4.1.11 Packet Count for Different Size Groups
Six different size groups – one counter for each:
Pkts64Octets
for any packet with size = 64 bytes
Pkts65to127Octets
Pkts128to255Octets
Pkts256to511Octets
Pkts512to1023Octets
Pkts1024to1518Octets
for any packet with size from 65 bytes to 127 bytes
or any packet with size from 128 bytes to 255 bytes
for any packet with size from 256 bytes to 511 bytes
for any packet with size from 512 bytes to 1023 bytes
for any packet with size from 1024 bytes to 1518 bytes
(to 1522 with VLAN tag; to BUF_LIMIT if enabled for this port)
Counts both good and bad packets.
11.5 Miscellaneous Counters
In addition to the statistics groups defined in previous sections, the ZL50410 has other statistics counters for its own
purposes. We have two counters for flow control – one counting the number of flow control frames received, and
another counting the number of flow control frames sent. We also have two counters, one for unicast frames sent,
and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we
have a counter called “frame send fail.” This keeps track of FIFO under-runs, late collisions, and collisions that have
occurred 16 times.
59
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
12.0 Register Definition
12.1 ZL50410 Register Description
I²C
CPU Addr
(Hex)
Register
Description
R/W
Addr
(Hex)
Default
Notes
0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..9))
ECR1Pn
ECR2Pn
ECR3Pn
ECR4Pn
Port Control Register 1 for
Port n
000+2n
001+2n
080+2n
081+2n
R/W
R/W
R/W
R/W
000+n
00A+n
014+n
01E+n
0C0
000
000
018
Port Control Register 2 for
Port n
Port Control Register 3 for
Port n
Port Control Register 4 for
Port n
BUF_LIMIT
FCC
Frame Buffer Limit
036
037
R/W
R/W
NA
NA
040
003
Flow Control Grant Period
1. VLAN Control Registers (Substitute [n] with Port number (0..9))
AVTCL
VLAN Type Code Register
Low
100
R/W
R/W
R/W
R/W
R/W
R/W
028
029
000
081
0FF
0FF
000
000
AVTCH
VLAN Type Code Register
High
101
PVMAPn_0
PVMAPn_1
PVMAPn_3
PVMODE
Port n Configuration
Register 0
102+4n
103+4n
105+4n
170
02A+n
034+n
03E+n
048
Port n Configuration
Register 1
Port n Configuration
Register 3
VLAN Operating Mode
2. TRUNK Control Registers (Substitute [n] with Trunk Group number (0..7))
TRUNKn
Trunk Group n
200+n
R/W
R/W
NA
NA
000
000
TRUNKn_HASH10
Trunk Group n Hash 10
Destination Port
208+4n
TRUNKn_HASH32
TRUNKn_HASH54
TRUNKn_HASH76
Trunk Group n Hash 32
Destination Port
209+4n
20A+4n
20B+4n
R/W
R/W
R/W
NA
NA
NA
000
000
000
Trunk Group n Hash 54
Destination Port
Trunk Group n Hash 76
Destination Port
Table 13 - Register Description
60
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
I²C
CPU Addr
Register
Description
R/W
Addr
(Hex)
Default
Notes
(Hex)
PVLAN_Pn
Private VLAN Edge
(protected ports) Port n
Egress Portmap
220+n
R/W
NA
000
MULTICAST_HASHn-0
MULTICAST_HASHn-1
Multicast hash result n
mask byte 0
228+2n
229+2n
R/W
R/W
NA
NA
0FF
0FF
Multicast hash result n
mask byte 1
3. CPU Port Configuration
MAC0
CPU MAC Address byte 0
CPU MAC Address byte 1
CPU MAC Address byte 2
CPU MAC Address byte 3
CPU MAC Address byte 4
CPU MAC Address byte 5
Interrupt Mask 0
300
301
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NA
NA
NA
NA
NA
NA
NA
NA
000
000
000
000
000
000
000
000
MAC1
MAC2
302
MAC3
303
MAC4
304
MAC5
305
INT_MASK0
INTP_MASKn
306
Interrupt Mask for MAC
Port 2n, 2n+1
310+n
(n=0..4)
RQS
Receive Queue Select
Receive Queue Status
323
324
325
R/W
RO
NA
NA
NA
000
NA
RQSS
MAC01
Increment MAC port 0,1
address
R/W
000
MAC23
MAC45
MAC67
Increment MAC port 2,3
address
326
327
328
R/W
R/W
R/W
NA
NA
NA
000
000
000
Increment MAC port 4,5
address
Increment MAC port 6,7
address
MAC9
Port 9 MAC address byte 5
329
330-336
337
R/W
R/W
RO
NA
NA
NA
NA
NA
NA
000
000
NA
CPUQINS[6:0]
CPUQINSRPT
CPUGRNHDL[1:0]
CPURLSINFO[4:0]
CPUGRNCTR
338-339
33A-33E
33F
RO
NA
R/W
R/W
000
000
4. Search Engine Configurations
AGETIME_LOW MAC Address Aging Time
400
R/W
049
05C
Low
Table 13 - Register Description (continued)
61
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
I²C
CPU Addr
Register
Description
R/W
Addr
(Hex)
Default
Notes
(Hex)
AGETIME_HIGH
SE_OPMODE
MAC Address Aging Time
High
401
R/W
R/W
04A
000
000
Search Engine Operating
Mode
403
NA
5. Global QOS Control
QOSC
UCC
QOS Control
500
510
R/W
R/W
04B
068
000
006
Unicast Congestion
Control
MCC
Multicast Congestion
Control
511
512
513
514
515
R/W
R/W
R/W
R/W
R/W
069
NA
006
003
000
000
000
MCCTH
RDRC0
RDRC1
RDRC2
Multicast Congestion
Threshold
WRED Drop Rate Control
0
090
091
NA
WRED Drop Rate Control
1
WRED Drop Rate Control
2
SFCB
Share FCB Size
518
519
51A
51B
530
531
532
533
540
541
542
543
550+n
558
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
074
075
000
000
000
000
000
000
000
000
000
000
000
000
000
000
C1RS
Class 1 Reserve Size
Class 2 Reserve Size
Class 3 Reserve Size
VLAN Priority Map Low
VLAN Priority Map Middle
VLAN Priority Map High
VLAN Discard Map
C2RS
076
C3RS
077
AVPML
056
AVPMM
AVPMH
057
058
AVDM
05C
059
TOSPML
TOSPMM
TOSPMH
TOSDML
USER_PROTOCOL_n
TOS Priority Map Low
TOS Priority Map Middle
TOS Priority Map High
TOS Discard Map
05A
05B
05D
0B3+n
0BB
User Define Protocol n
(n=0..7)
USER_PROTOCOL_
FORCE_DISCARD
User Define Protocol 0 To
7 Force Discard Enable
WLPP10
Well Known Logic Port 0
and 1 Priority
560
R/W
0A8
000
Table 13 - Register Description (continued)
62
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
I²C
CPU Addr
Register
Description
R/W
Addr
(Hex)
Default
Notes
(Hex)
WLPP32
Well Known Logic Port 2
and 3 Priority
561
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0A9
0AA
0AB
0AC
0AD
092+n
09A+n
0A2
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
WLPP54
Well Known Logic Port 4
and 5 Priority
562
563
WLPP76
Well Known Logic Port 6
and 7 Priority
WLPE
Well Known Logic Port 0 To
7 Enable
564
WLPFD
Well Known Logic Port 0 To
7 Force Discard Enable
565
USER_PORTn_LOW
USER_PORTn_HIGH
User Define Logical Port n
Low
570+2n
571+2n
590
(n=0..7)
User Define Logical Port n
High
USER_PORT1:0_
PRIORITY
User Define Logic Port 0
and 1 Priority
USER_PORT3:2_
PRIORITY
User Define Logic Port 2
and 3 Priority
591
0A3
USER_PORT5:4_
PRIORITY
User Define Logic Port 4
and 5 Priority
592
0A4
USER_PORT7:6_
PRI ORITY
User Define Logic Port 6
and 7 Priority
593
0A5
USER_PORT_
ENABLE[7:0]
User Define Logic Port 0
To 7 Enable
594
0A6
USER_PORT_
FORCE_DISCARD[7:0] To 7 Force Discard Enable
User Define Logic Port 0
595
0A7
RLOWL
User Define Range Low Bit
[7:0]
5A0
5A1
5A2
5A3
5A4
0AE
0AF
0B0
RLOWH
RHIGHL
RHIGHH
RPRIORITY
User Define Range Low Bit
[15:8]
User Define Range High
Bit [7:0]
User Define Range High
Bit [15:8]
0B1
User Define Range Priority
0B2
6. MISC Configuration Register
MII_OP0
MII_OP1
MII Register Option 0
MII Register Option 1
600
601
R/W
R/W
0BC
0BD
000
000
Table 13 - Register Description (continued)
63
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
I²C
CPU Addr
Register
Description
R/W
Addr
(Hex)
Default
Notes
(Hex)
FEN
Feature Registers
602
603
604
605
606
607
608
609
60A
60B
R/W
R/W
R/W
R/W
R/W
RO
0BE
NA
NA
NA
NA
NA
NA
NA
NA
0FF
010
000
000
000
000
NA
MIIC0
MIIC1
MIIC2
MIIC3
MIID0
MIID1
USD
MII Command Register 0
MII Command Register 1
MII Command Register 2
MII Command Register 3
MII Data Register 0
MII Data Register 1
RO
NA
One micro second divider
Device id and test
R/W
R/W
R/W
000
002
000
DEVICE
SUM
EEPROM Checksum
Register
LHBTimer
Link heart beat time out
timer
610
R/W
NA
000
LHBReg0
LHBReg1
LHB control field value[7:0]
611
612
R/W
R/W
NA
NA
000
000
LHB control field value
[15:8]
fMACCReg0
Forced MAC control field
value [7:0]
613
614
620
621
622
R/W
R/W
R/W
R/W
R/W
NA
NA
000
000
000
060
000
fMACCReg1
Forced MAC control field
value [15:8]
FCB_BASE_ADDR0
FCB_BASE_ADDR1
FCB_BASE_ADDR2
7. Port Mirroring Controls
FCB Base Address
Register 0
0BF
0C0
0C1
FCB Base Address
Register 1
FCB Base Address
Register 2
MIRROR_DEST_MAC0 Mirror Destination MAC
Address 0
700
701
702
703
704
R/W
R/W
R/W
R/W
R/W
NA
NA
NA
NA
NA
000
000
000
000
000
MIRROR_DEST_MAC1 Mirror Destination MAC
Address 1
MIRROR_DEST_MAC2 Mirror Destination MAC
Address 2
MIRROR_DEST_MAC3 Mirror Destination MAC
Address 3
MIRROR_DEST_MAC4 Mirror Destination MAC
Address 4
Table 13 - Register Description (continued)
64
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
I²C
CPU Addr
Register
Description
R/W
Addr
(Hex)
Default
Notes
(Hex)
MIRROR_DEST_MAC5 Mirror Destination MAC
Address 5
705
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NA
NA
NA
NA
NA
NA
NA
NA
000
000
000
000
000
000
000
000
MIRROR_SRC_MAC0
MIRROR_SRC_MAC1
MIRROR_SRC_MAC2
MIRROR_SRC_MAC3
MIRROR_SRC_MAC4
MIRROR_SRC_MAC5
MIRROR_CONTROL
Mirror Source MAC
Address 0
706
707
708
709
70A
70B
70C
Mirror Source MAC
Address 1
Mirror Source MAC
Address 2
Mirror Source MAC
Address 3
Mirror Source MAC
Address 4
Mirror Source MAC
Address 5
Port Mirror Control
Register
RMAC_MIRROR0
RMAC_MIRROR1
8. Per Port QOS Control
FCRn
RMAC Mirror 0
RMAC Mirror 1
710
711
R/W
R/W
NA
NA
000
000
Flooding Control Register
n
800+n
820+n
840+n
R/W
R/W
R/W
04C+n
05E+n
06A+n
000
000
006
(n=0..9)
BMRCn
Broadcast/Multicast Rate
Control n
PR100_n
Port Reservation for RMAC
Ports (n=0..7)
‘d1536/1
6=‘d96,
‘d96>>4=
’h6
PR100_CPU
PRG
Port Reservation for CPU
Port
848
849
R/W
R/W
073
072
006
024
‘d96
Port Reservation for
GMAC Port
‘d96x6=‘
d576,
‘d576>>4
=’h24
PTH100_n
PTH100_CPU
PTHG
Port Threshold for RMAC
Ports (n=0..7)
860+n
868
R/W
R/W
R/W
0C2+n
0CB
003
003
012
½
½
½
Port Threshold for CPU
Port
Port Threshold for GMAC
Port
869
0CA
Table 13 - Register Description (continued)
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Zarlink Semiconductor Inc.
ZL50410
Data Sheet
I²C
CPU Addr
Register
Description
R/W
Addr
(Hex)
Default
Notes
(Hex)
QOSCn
QOS Control n
880+n
R/W 078-08F
NA
000
(n=0..39)
E. System Diagnostic
DTSRL
Test Register Low
Test Register Medium
Testmux Output [7:0]
Testmux Output [15:8]
MASK Timeout 0
E00
E01
R/W
R/W
R/O
R/O
R/W
R/W
R/W
R/W
R/W
RO
NA
NA
000
001
NA
DTSRM
TESTOUT0
TESTOUT1
MASK0
E02
NA
E03
NA
NA
E10
0F6
0F7
0F8
0F9
0FA
NA
000
000
000
000
000
NA
MASK1
MASK Timeout 1
E11
MASK2
MASK Timeout 2
E12
MASK3
MASK Timeout 3
E13
MASK4
MASK Timeout 4
E14
BOOTSTRAP[2:0]
PRTFSMSTn
BOOTSTRAP Read Back
E80-E82
E90+n
Ethernet Port n Status
Read Back
RO
NA
NA
(n=0..9)
(n=0..7)
PRTQOSSTn
PRTQOSST8A
PRTQOSST8B
PRTQOSST9A
PRTQUSST9B
RMAC Port n QOS and
Queue Status
EA0+n
EA8
RO
RO
RO
RO
RO
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CPU Port QOS and Queue
Status A
CPU Port QOS and Queue
Status B
EA9
GMAC Port QOS and
Queue Status A
EAA
EAB
GMAC Port QOS and
Queue Status B
CLASSQOSST
PRTINTCTR
QMCTRLn
Class Buffer Status
Buffer Interrupt Status
Ports Queue Control Status
Ports Queue Control
Memory bist result
Memory bist result
Memory control
EAC
EAD
EB0+n
EBA
EBB
EBC
EBD
EC0
RO
R/W
R/W
R/W
R/O
R/O
R/W
R/W
R/W
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
000
000
000
NA
(n=0..9)
QCTRL
BMBISTR0
BMBISTR1
BMControl
NA
00F
000
000
BUFF_RST
FCBHEADPTR0
Buffer Reset Pool
FCB Head Pointer [7:0]
EC1
Table 13 - Register Description (continued)
66
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
I²C
CPU Addr
Register
Description
R/W
Addr
(Hex)
Default
Notes
(Hex)
FCB_HEAD_PTR1
FCB_TAIL_PTR0
FCB_TAIL_PTR1
FCB_NUM0
FCB Head Pointer [15:8]
FCB Tail Pointer [7:0]
FCB Tail Pointer [15:8]
FCB Number [7:0]
EC2
EC3
EC4
EC5
EC6
R/W
R/W
R/W
R/W
R/W
NA
NA
NA
NA
NA
000
000
000
000
006
FCB_NUM1
FCB Init Start and FCB
Number [14:8]
BM_RLSFF_CTRL
BM_RLSFF_INFO0
BM_RLSFF_INFO1
BM_RLSFF_INFO2
BM_RLSFF_INFO3
BM_RLSFF_INFO4
BM_RLSFF_INFO5
Read control register
Bm_rlsfifo_info[7:0]
Bm_rlsfifo_info[15:8]
Bm_rlsfifo_info[23:16]
Bm_rlsfifo_info[31:24]
Bm_rlsfifo_info[39:32]
EC7
EC8
EC9
ECA
ECB
ECC
ECD
R/W
RO
RO
RO
RO
RO
RO
NA
NA
NA
NA
NA
NA
NA
000
NA
NA
NA
NA
NA
NA
Fifo_cnt[2:0],Bm_rlsfifo_inf
o[44:40]
F. System Control
GCR
DCR
Global Control Register
Device Control Register
Device Control Register 1
F00
F01
F02
F03
R/W
RO
NA
NA
NA
NA
000
NA
DCR1
DPST
RO
NA
Device Port Status
Register
R/W
000
DTST
DA
Data read back register
DA Register
F04
FFF
RO
RO
NA
NA
NA
0DA
Table 13 - Register Description (continued)
12.2 Directly Accessed Registers
12.2.1 INDEX_REG0
•
•
Address for indirectly accessed register addresses (8/16 bits)
Address = 0 (write only)
•
•
In 16-bit or serial mode: Address bits [15:0]
In 8-bit mode: Address bits [7:0]
12.2.2 INDEX_REG1 (only needed for 8-bit mode)
•
•
Address for indirectly accessed register addresses (8 bits)
Address = 1 (write only)
•
•
In 16-bit or serial mode: NA
In 8-bit mode: Address bits [15:8]
67
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
12.2.3 DATA_FRAME_REG
•
•
Data of indirectly accessed registers (8 bits)
Address = 2 (read/write)
12.2.4 CONTROL_FRAME_REG
•
•
•
CPU transmit/receive switch frames (8/16 bits)
Address = 3 (read/write)
Format:
8-byte of Frame status (Frame size, Source port #, VLAN tag)
Frame Data (size should be in multiple of 8-byte)
12.2.5 COMMAND&STATUS Register
•
•
•
CPU interface commands and status (8 bits)
Address = 4 (read/write)
When the CPU writes to this register
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Set Control Frame Receive buffer ready, after CPU writes a complete frame into the buffer. This bit
is self-cleared.
Set Control Frame Transmit buffer1 ready, after CPU reads out a complete frame from the buffer.
This bit is self-cleared.
Set Control Frame Transmit buffer2 ready, after CPU reads out a complete frame from the buffer.
This bit is self-cleared.
Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and
flushed the rest of frame fragment, If occurs. This bit will be self-cleared.
Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit
will be self-cleared.
Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature
can be used for software debug. For normal operation must be '0'.
Bits [7:6]: Reserved. Must be '0'
•
When the CPU reads this register:
Bit [0]:
Bit [1]:
Bit [2]:
Control Frame receive buffer ready, CPU can write a new frame
1 – CPU can write a new control command 1
0 – CPU has to wait until this bit is 1 to write a new control command 1
Control Frame transmit buffer1 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control command
Control Frame transmit buffer2 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control command
Bit [3]:
Transmit FIFO has data for CPU to read (TXFIFO_RDY)
Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK)
Transmit FIFO End Of Frame (TXFIFO_EOF)
Reserved
Bit [4]:
Bit [5]:
Bits [7:6]:
68
Zarlink Semiconductor Inc.
ZL50410
Data Sheet
12.2.6 Interrupt Register
•
•
Interrupt sources (8 bits)
Address = 5 (read/write)
Bit [0]:
Bit [1]:
Bit [2]:
Bits [6:3]:
Bit [7]:
CPU frame interrupt
Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU to read
Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read
Reserved
Device Timeout Detected interrupt
Note: This bit is not self-cleared. After reading, the CPU has to clear the bit writing 0 to it.
12.2.7 Control Command Frame Buffer1 Access Register
•
•
•
CPU transmit/receive control frames (8/16 bits)
Address = 6 (read/write)
When CPU writes to this register:
Data is written to the Control Command Frame Receive Buffer
•
When CPU reads this register:
Data is read from the Control Command Frame Transmit Buffer1
12.2.8 Control Command Frame Buffer2 Access Register
•
•
•
CPU receive control frames (8/16 bits)
Address = 7 (read only)
When CPU reads this register:
Data is read from the Control Command Frame Transmit Buffer2
12.3 Indirectly Accessed Registers
12.3.1 (Group 0 Address) MAC Ports Group
12.3.1.1 ECR1Pn: Port n Control Register
I²C Address 000+n; CPU Address:0000+2n (n = port number)
Accessed by CPU and I²C (R/W)
Port 0 – 7 & 9: (RMAC & GMAC Ports)
Bit [0]
Bit [1]
Bit [2]
Flow Control
0 - Enable (Default)
1 - Disable
Duplex Mode
0 - Full Duplex (Default)
1 - Half Duplex - Only in 10/100 mode
Speed
0 - 100 Mbps (Default)
1 - 10 Mbps
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Bits [4:3] 00 - Enable Auto-Negotiation (Default)
This enables hardware state machine for auto-negotiation.
01 - Limited Disable Auto-Negotiation
This disables hardware state machine for speed auto-negotiation (use
ECR1Pn[2:0] for configuration). Hardware will still poll PHY for link status.
10 - Force Link Down
Disable the port. Hardware does not talk to PHY.
11 - Force Link Up
The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control)
setup. Hardware does not talk to PHY.
Bit [5]
Asymmetric Flow Control Enable.
0 – Disable asymmetric flow control (Default)
1 – Enable Asymmetric flow control
When this bit is set and flow control is on (bit [0] = 0), the device does not send out
flow control frames, but it’s receiver interprets and processes flow control frames.
Bits [7:6] SS - Spanning tree state (IEEE 802.1D spanning tree protocol)
00 - Blocking:
01 - Listening:
10 - Learning:
Frame is dropped
Frame is dropped
Frame is dropped. Source MAC address is learned.
11 - Forwarding: Frame is forwarded. Source MAC address is learned. (Default)
Port 8: (CPU Port)
Bit [5:0]
8/16-bit or Serial Only Modes
Reserved
Bits [7:6] SS - Spanning tree state (IEEE 802.1D spanning tree protocol)
00 - Blocking:
01 - Listening:
10 - Learning:
Frame is dropped
Frame is dropped
Frame is dropped. Source MAC address is learned.
11 - Forwarding: Frame is forwarded. Source MAC address is learned. (Default)
Serial + MII Mode
Bit [0]
Flow Control
0 - Enable (Default)
1 - Disable
Bit [1]
Bit [2]
Duplex Mode
Must be 0 - Full Duplex (Default)
Speed
0 - 100 Mbps (Default)
1 - 10 Mbps
Bit [3]
1 - MII Port Up
The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control)
setup.
0 - MII Port Down
Note: Bit [4] must be ‘1’.
Must be ‘1’.
Bit [4]
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Bit [5]
Asymmetric Flow Control Enable.
0 – Disable asymmetric flow control (Default)
1 – Enable Asymmetric flow control
When this bit is set and flow control is on (bit [0] = 0), the device does not send out
flow control frames, but it’s receiver interprets and processes flow control frames.
Bits [7:6] SS - Spanning tree state (IEEE 802.1D spanning tree protocol)
00 - Blocking:
01 - Listening:
10 - Learning:
Frame is dropped
Frame is dropped
Frame is dropped. Source MAC address is learned.
11 - Forwarding: Frame is forwarded. Source MAC address is learned. (Default)
12.3.1.2 ECR2Pn: Port n Control Register
I²C Address: 00A+n; CPU Address:0001+2n (n = port number)
Accessed by CPU and I²C (R/W)
Bit [0]:
Filter untagged frame
0: Disable (Default)
1: All untagged frames from this port are discarded or follow security option when
security is enable
Bit [1]:
Filter Tag frame
0: Disable (Default)
1: All tagged frames from this port are discarded or follow security option when
security is enable
Bit [2]:
Bit [3]:
Bit [4]
Learning Disable
0: Learning is enabled on this port (Default)
1: Learning is disabled on this port
Rate control timer select (RMAC ports only)
0: 10 microsecond refreshing time (Default)
1: 1 millisecond refreshing time
Force VLAN Tag Out
0: Disable (Default)
1: Enable
If this feature is enabled, a packet leaving the device will ALWAYS have a VLAN
tag. Only applicable in tagged-based VLAN mode (PVMODE[0]=’1’). In port-based
VLAN mode (PVMODE[0]=’0’), this bit must be 0.
Bit [5]
Do not change VLAN tag. This overrides PVMAPnn_3 bit [2]. If this bit is set, no
tag will be replaced nor removed.
0: Disable (Default)
1: Enable
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Bits [7:6] Security Enable. The ZL50410 checks the incoming data for one of the following
conditions:
•
If the source MAC address of the incoming packet is in the MAC table and is
defined as secure address but the ingress port is not the same as the port
associated with the MAC address in the MAC table.
•
A MAC address is defined as secure when its entry at MAC table has
static status and bit 0 is set to 1. MAC address bit 0 (the first bit
transmitted) indicates whether the address is unicast or multicast. As
source addresses are always unicast bit 0 is not used (always 0).
ZL50410 uses this bit to define secure MAC addresses.
•
If the port is set as learning disable and the source MAC address of the
incoming packet is not defined in the MAC address table or the MAC
address is not associated to the ingress port.
If any one of the conditions is met, the packet is forwarded based on these setting.
00 – Disable port security, forward packets as usual. (Default)
01 – Discard violating packets
10 – Forward violating packets as usual and also to the CPU for inspection
11 – Forward violating packets to the CPU for inspection
It also checks for one of the following additional conditions:
•
If the port is configured to filter untagged frames and an untagged frame
arrives, or
•
•
If the port is configured to filter tagged frames and a tagged frame arrives, or
If the packet has the source mac address on the source mac address filter
list, or
•
If the packet has the destination mac address on the destination mac
address filter list
If any one of the conditions is met, the packet will be handled according to:
0X – Discard violating packets
1X – Forward violating packets to CPU for inspection
12.3.1.3 ECR3Pn: Port n Control Register
I²C Address: 014+n; CPU Address:0080+2n (n = port number)
Accessed by CPU and I²C (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Enable receiving short frame < 64B
0: Disable (Default)
1: Allow receiving short frame with correct CRC.
Enable receiving long frame > 1522
0: Disable (Default)
1: Allow receiving long frame that are <= BUF_LIMIT value
Enable pad frame to 64B when transmitted
0: Allow padding to 64B (Default)
1: Disable
Enable compress preamble
0: Send standard preamble (Default)
1: Only one byte preamble+SFD
Bits [6:4] Number of bytes removed from the Inter-Frame Gap (IFG). (Default 0x0)
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Bit [7]
Link Heart Beat Transmit (RMAC ports only)
0: Disable (Default)
1: Enable
12.3.1.4 ECR4Pn: Port n Control Register
I²C Address: 01E+n; CPU Address:0081+2n (n = port number)
Accessed by CPU and I²C (R/W)
Port 0 – 7: (RMAC Ports)
Bit [0]:
Bit [1]:
Bit [2]:
Enable TXCLK output. Active high
0: Disable (Default)
1: Mn_TXCLK pin becomes output in GPSI or MII mode
Enable RXCLK output. Active high
0: Disable (Default)
1: Mn_RXCLK pin becomes output in GPSI or MII mode
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Bits [4:3]: Interface mode:
00 - GPSI mode
01 - MII mode
10 - Reserved
11 - RMII mode (Default)
Bit [5]:
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Bit [6]:
Bit [7]:
Link Heart Beat Receive
0: Disable (Default). Also clears all MAC LHB status.
1: Enable
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
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Port 8: (CPU Port)
Bit [2]:
Bits [1:0]: Reserved
Enable special write to 2 registers in a single write operation.
0: Disable (Default)
1: Enable
Should be enabled only in serial mode and disabled in 8/16-bit mode.
Bits [4:3]: Enable insertion of 2-byte CPU information in CPU frame packet in Serial + MII
mode
00: No information is inserted
01: Insert 2-byte of CPU information
10: Reserved
11: Insert 6-byte of padding + 2-byte of CPU information (Default)
In port-based VLAN mode, the CPU MII interface must be in “No information is
inserted” mode (ECR4P8[4:3]='00'). In tagged-based VLAN mode, the CPU MII
interface supports all three modes (0,2,8 bytes insertion).
Bit [5]:
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Bit [6]:
Bit [7]:
Reserved
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
Port 9: (GMAC Port)
Bit [0]:
Bit [1]:
Reserved
Enable RXCLK output. Active high
0: Disable (Default)
1: M9_RXCLK pin becomes output in MII mode
Note: To configure port 9 with the device providing the interface clocks, you need
to tie M9_RXCLK to M9_MTXCLK externally as M9_MTXCLK is not a bidirectional
clock.
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Bit [2]:
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Bits [4:3]: Interface mode:
00 - MII mode
11 - GMII mode (Default)
Bit [5]:
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Bit [6]:
Bit [7]:
Reserved
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
12.3.1.5 BUF_LIMIT – Frame Buffer Limit
CPU Address:h036
Accessed by CPU (R/W)
Bits [6:0]: Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40)
Bit [7]:
Reserved
12.3.1.6 FCC – Flow Control Grant Period
CPU Address:h037
Accessed by CPU (R/W)
Bits [2:0]:
Bits [7:3]:
Flow Control Grant Period (Default 0x3)
Reserved
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12.3.2 (Group 1 Address) VLAN Group
12.3.2.1 AVTCL – VLAN Type Code Register Low
I²C Address 028; CPU Address:h100
Accessed by CPU and I²C (R/W)
Bits [7:0]: VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0x00)
12.3.2.2 AVTCH – VLAN Type Code Register High
I²C Address 029; CPU Address:h101
Accessed by CPU and I²C (R/W)
Bits [7:0]:
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 0x81)
12.3.2.3 PVMAP00_0 – Port 0 Configuration Register 0
I²C Address 02A, CPU Address:h102
Accessed by CPU and I²C (R/W)
In Port Based VLAN Mode
Bits [7:0]:
VLAN Mask for port 0 (Default 0xFF)
This register indicates the legal egress ports. A “1” on bit 3 means that the packet can be sent to port 3. A “0” on bit
3 means that any packet destined to port 3 will be discarded. This register works with registers 1 to form a 10 bit
mask to all egress ports.
In Tag based VLAN Mode
Bits [7:0]:
PVID [7:0] (Default is 0xFF)
This is the default VLAN tag. It works with configuration register PVMAP00_1 [7:5] [3:0] to form a default VLAN tag.
If the received packet is untagged, then the packet is classified with the default VLAN tag. If the received packet has
a VLAN ID of 0, then PVID is used to replace the packet’s VLAN ID.
12.3.2.4 PVMAP00_1 – Port 0 Configuration Register 1
I²C Address h34, CPU Address:h103
Accessed by CPU and I²C (R/W)
In Port based VLAN Mode
Bits [1:0]:
Bits [7:2]:
VLAN Mask for ports 9 to 8 (Default 0x3)
Reserved (Default 0x3F)
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In Tag based VLAN Mode
Bits [3:0]:
Bit [4]:
PVID [11:8] (Default is 0xF)
Untrusted Port.
This register is used to change the VLAN priority field of a packet to a
predetermined priority.
1: VLAN priority field is changed to Bit [7:5] at ingress port (Default)
0: Keep VLAN priority field
Bits [7:5]:
Untag Port Priority (Default 0x7)
12.3.2.5 PVMAP00_3 – Port 0 Configuration Register 3
I²C Address h3E, CPU Address:h105
Accessed by CPU and I²C (R/W)
In Port Based VLAN Mode
Bits [2:0]:
Bits [5:3]:
Reserved
Default Transmit priority. Used when Bit [7]=1 (Default 0)
Transmit Priority Level 0 (Lowest)
Transmit Priority Level 1
Transmit Priority Level 2
Transmit Priority Level 3 (Highest)
Bit [6]:
Bit [7]:
Default Discard priority. Used when Bit [7]=1
0 – Discard Priority Level 0 (Lowest) (Default)
1 – Discard Priority Level 1(Highest)
Enable Fix Priority (Default 0)
0 - Disable. All frames are analysed. Transmit Priority and Discard Priority are
based on VLAN Tag, TOS or Logical Port.
1 - Enable. Transmit Priority and Discard Priority are based on values
programmed in bit [6:3]
In Tag-based VLAN Mode
Bit [0]:
Bit [1]:
Not used
Ingress Filter Enable
0 - Disable Ingress Filter. Packets with VLAN not belonging to source port are
forwarded, if destination port belongs to the VLAN. Symmetric VLAN. (Default)
1 - Enable Ingress Filter. Packets with VLAN not belonging to source port are
filtered. Asymmetric VLAN.
Bit [2]:
Force untag out (VLAN tagging is based on IEEE 802.1Q rule).
0 - Disable (Default)
1 - Force untagged output. All packets transmitted from this port are untagged.
This bit is used when this port is connected to legacy equipment that does not
support VLAN tagging.
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Bits [5:3]:
Default Transmit priority. Used when Bit [7]=1 (Default 0)
Transmit Priority Level 0 (Lowest)
Transmit Priority Level 1
Transmit Priority Level 2
Transmit Priority Level 3 (Highest)
Bit [6]:
Bit [7]:
Default Discard priority. Used when Bit [7]=1
0 – Discard Priority Level 0 (Lowest) (Default)
1 – Discard Priority Level 1(Highest)
Enable Fix Priority (Default 0)
0 - Disable. All frames are analysed. Transmit Priority and Discard Priority are
based on VLAN Tag, TOS or Logical Port.
1 - Enable. Transmit Priority and Discard Priority are based on values
programmed in bit [6:3]
12.3.2.6 PVMAPnn_0,1,3 – Ports 1~9 Configuration Registers
PVMAP01_0,1,3 I²C Address h2B,35,3F; CPU Address:h106,107,109 (Port 1)
PVMAP02_0,1,3 I²C Address h2C,36,40; CPU Address:h10A, 10B, 10D (Port 2)
PVMAP03_0,1,3 I²C Address h2D,37,41; CPU Address:h10E, 10F, 111 (Port 3)
PVMAP04_0,1,3 I²C Address h2E,38,42; CPU Address:h112, 113, 115 (Port 4)
PVMAP05_0,1,3 I²C Address h2F,39,43; CPU Address:h116, 117, 119 (Port 5)
PVMAP06_0,1,3 I²C Address h30,3A,44; CPU Address:h11A, 11B, 11D (Port 6)
PVMAP07_0,1,3 I²C Address h31,3B,45; CPU Address:h11E, 11F, 121 (Port 7)
PVMAP08_0,1,3 I²C Address h32,3C,46; CPU Address:h122, 123, 125 (Port CPU)
PVMAP09_0,1,3 I²C Address h33,3D,47; CPU Address:h126, 127, 129 (Port GMAC)
12.3.2.7 PVMODE
I²C Address: h048, CPU Address:h170
Accessed by CPU and I²C (R/W)
Bit [0]:
Bit [1]:
VLAN Mode
0: Port based VLAN Mode (Default)
1: Tag based VLAN Mode
Slow learning (Default = 0)
Same function as SE_OPMODE bit [7]. Either bit can enable the function; both need to
be turned off to disable the feature.
Bit [2]:
Disable dropping of frames with destination MAC addresses 01-80-C2-00-00-01 to
0x01-80-C2-00-00-0F.
0: Drop all frames in this range (Default)
1: Disable dropping of frames in this range
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Bit [3]:
Bit [4]:
Flooding control in secure mode
0: Enable - Learning disabled port will not receive any flooding packets (Default)
1: Disable
Support MAC address 0
0: MAC address 0 is not learned. (Default)
This means packet with destination MAC address 0 is forwarded as unknown
destination. It is subjected to unicast to multicast rate control.
1: MAC address 0 is learned.
Bit [5]:
Disable IEEE multicast control frame (01-80-C2-00-00-00 to 01-80-C2-00-00-FF) to
CPU in managed mode. In unmanaged mode, frame is forwarded as multicast (except
PAUSE frame).
0: Frame is forwarded to CPU (Default)
1: Frame is forwarded as multicast (except PAUSE frame)
Bit [6]:
Bit [7]:
IP Multicast Enable
0: Disable (default)
1: Enable
In general, this bit is equal to ^FEN[4].
Enable logical port match in secure mode
0: Disable (Default)
1: Enable - When Well Known or User Define logical port force discard enabled, force
any IP packet with logical port number matching logical port numbers to CPU.
12.3.3 (Group 2 Address) Port Trunking Groups
Trunk Group – Up to eight RMAC ports can be selected for each trunk group.
12.3.3.1 TRUNKn– Trunk Group 0~7
CPU Address:h200+n (n = trunk group)
Accessed by CPU (R/W)
Bit [7:0] Port 7-0 bit map of trunk n. (Default 0)
B
i
B
i
t
t
7
0
TRUNK0
P
o
r
P
o
r
t
t
7
0
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12.3.3.2 TRUNKn_HASH10 – Trunk group n hash result 1/0 destination port number
CPU Address:h208+4n (n = trunk group)
Accessed by CPU (R/W)
Bits [3:0]
Bits [7:4]
Hash result 0 destination port number (Default 0)
Hash result 1 destination port number (Default 0)
12.3.3.3 TRUNKn_HASH32 – Trunk group n hash result 3/2 destination port number
CPU Address:h209+4n (n = trunk group)
Accessed by CPU (R/W)
Bits [3:0]
Bits [7:4]
Hash result 2 destination port number (Default 0)
Hash result 3 destination port number (Default 0)
12.3.3.4 TRUNKn_HASH54 – Trunk group n hash result 5/4 destination port number
CPU Address:h20A+4n (n = trunk group)
Accessed by CPU (R/W)
Bits [3:0]
Bits [7:4]
Hash result 4 destination port number (Default 0)
Hash result 5 destination port number (Default 0)
12.3.3.5 TRUNKn_HASH76 – Trunk group n hash result 7/6 destination port number
CPU Address:h20B+4n (n = trunk group)
Accessed by CPU (R/W)
Bits [3:0]
Bits [7:4]
Hash result 6 destination port number (Default 0)
Hash result 7 destination port number (Default 0)
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12.3.3.6 PVLAN_Pn – Per-Port Private VLAN Edge (Protected Ports)
CPU Address:h220+n (n = RMAC port number)
Accessed by CPU (R/W)
Only applicable if Private VLAN Edge feature is enable (FEN[1]=’1’).
NOTE: These registers overlap TRUNK6/7_HASHxy registers, thus, trunk groups 6 and 7 must be disabled
(TRUNK6=TRUNK7=0x00) if the PVLAN feature is enabled.
Bits [7:0]
Port 9,7-0 bit map of protected port n (Default 0x00)
Bits [7:0] represent ports 9,7-0, excluding the source port. For example:
For port 0, [7:0] represent ports 9,7..1
For port 1, [7:0] represent ports 9,7..2,0
For port 2, [7:0] represent ports 9,7..3,1..0
Multicast Hash Registers
Multicast Hash registers are used to distribute multicast traffic. 16 registers are used to form a 8-entry array; each
entry has 10 bits, with each bit representing one port. Any port not belonging to a trunk group should be
programmed with 1. Ports belonging to the same trunk group should only have a single port set to “1” per entry. The
port set to “1” is picked to transmit the multicast frame when the hash value is met.
Hash Value =0 HASH0-1
Hash Value =1 HASH1-1
Hash Value =2 HASH2-1
Hash Value =3 HASH3-1
Hash Value =4 HASH4-1
Hash Value =5 HASH5-1
Hash Value =6 HASH6-1
Hash Value =7 HASH7-1
HASH0-0
HASH1-0
HASH2-0
HASH3-0
HASH4-0
HASH5-0
HASH6-0
HASH7-0
P
o
r
P P
o o
P
o
r
r
t
r
t
t
t
9
8 7
0
12.3.3.7 MULTICAST_HASHn-0 – Multicast hash result 0~7 mask byte 0
CPU Address:h228+2n (n = hash value)
Accessed by CPU (R/W)
Bits [7:0]:
Port 7-0 bit map for multicast hash. (Default 0xFF)
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12.3.3.8 MULTICAST_HASHn-1 – Multicast hash result 0~7 mask byte 1
CPU Address:h229+2n (n = hash value)
Accessed by CPU (R/W)
Bits [1:0]: Port 9-8 bit map for multicast hash. (Default 0x3)
Bit [2]:
MULTICAST_HASH1-1
Unknown IP Multicast Filter Enable
1: Enable (default)
0: Disable
If this feature is enabled, unknown IP multicast packets or unknown multicast
packets can be either filtered or sent to the CPU, based on bits [13:12] in the per
VLAN Port Association table.
This feature is only applicable in tagged-based VLAN mode (PVMODE[0]=’1’). In
port-based VLAN mode (PVMODE[0]=’0’), this bit is ignored.
MULTICAST_HASH[7:2,0]-1
Reserved (Default 0x1)
Bits [5:3]: Reserved (Default 0x7)
Bits [7:6]: MULTICAST_HASH0-1
Hash Select. The hash algorithm selected is valid for all trunks
00 - Use Source and Destination MAC Address for hashing
01 - Use Source MAC Address for hashing
10 - Use Destination MAC Address for hashing
11 - Use Source Port Number for hashing (Default)
MULTICAST_HASH[7:1]-1
Reserved (Default 0x3)
12.3.4 (Group 3 Address) CPU Port Configuration Group
47
0
(MC bit)
MAC5
MAC4
MAC3
MAC2
MAC1
MAC0
MAC5 to MAC0 registers form the CPU MAC address. When a packet with destination MAC address match MAC
[5:0], the packet is forwarded to the CPU. The default MAC address is 00-00-00-00-00-00.
12.3.4.1 MAC0 – CPU MAC address byte 0
CPU Address:h300
Accessed by CPU (R/W)
Bits [7:0]:
Byte 0 (bits [7:0]) of the CPU MAC address (Default 0)
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12.3.4.2 MAC1 – CPU MAC address byte 1
CPU Address:h301
Accessed by CPU (R/W)
Bits [7:0]: Byte 1 (bits [15:8]) of the CPU MAC address (Default 0)
12.3.4.3 MAC2 – CPU MAC address byte 2
CPU Address:h302
Accessed by CPU (R/W)
Bits [7:0]: Byte 2 (bits [23:16]) of the CPU MAC address (Default 0)
12.3.4.4 MAC3 – CPU MAC address byte 3
CPU Address:h303
Accessed by CPU (R/W)
Bits [7:0]:
Byte 3 (bits [31:24]) of the CPU MAC address (Default 0)
12.3.4.5 MAC4 – CPU MAC address byte 4
CPU Address:h304
Accessed by CPU (R/W)
Bits [7:0]: Byte 4 (bits [39:32]) of the CPU MAC address (Default 0)
12.3.4.6 MAC5 – CPU MAC address byte 5
CPU Address:h305
Accessed by CPU (R/W)
Bits [7:0]: Byte 5 (bits [47:40]) of the CPU MAC address (Default 0)
Note: Bits [42:40] are set on a per port basis using MAC01, MAC23, MAC45,
MAC67 registers. For port 9, this register is ignored and MAC9 is used for bits
[47:40].
12.3.4.7 INT_MASK0 – Interrupt Mask
CPU Address:h306
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00)
-
-
1: Mask the interrupt
0: Unmask the interrupt (Enable interrupt) (Default)
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Bit [0]:
Bit [1]:
Bit [2]:
CPU frame interrupt. CPU frame buffer has data for CPU to read
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read
Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read
Bits [6:3]: Reserved
Bit [7]:
Device Timeout Detected interrupt
12.3.4.8 INTP_MASK0 – Interrupt Mask for MAC Port 0,1
CPU Address:h310
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0x00)
-
-
1: Mask the interrupt
0: Unmask the interrupt (Default)
Bit [0]: Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources
Bit [1]: Port 0 link change mask
Bit [2]: Port 0 module detect mask
Bit [3]: Reserved
Bit [4]: Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources.
Bit [5]: Port 1 link change mask
Bit [6]: Port 1 module detect mask
Bit [7]
Reserved
12.3.4.9 INTP_MASKn – Interrupt Mask for MAC Ports 2~9 Registers
INTP_MASK1 CPU Address:h311 (Ports 2,3)
INTP_MASK2 CPU Address:h312 (Ports 4,5)
INTP_MASK3 CPU Address:h313 (Ports 6,7)
INTP_MASK4 CPU Address:h314 (Port CPU,GMAC)
12.3.4.10 RQS – Receive Queue Select
CPU Address:h323
Accessed by CPU (RW)
Select which receive queue is being used by the CPU port.
Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0).
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Bit [0]:
Select Queue 0
0: Not selected (Default)
1: Selected
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Select Queue 1
Select Queue 2
Select Queue 3
Select Multicast Queue 0
Select Multicast Queue 1
Select Multicast Queue 2
Select Multicast Queue 3
12.3.4.11 RQSS – Receive Queue Status
CPU Address:h324
Accessed by CPU (RO)
CPU receive queue status
Bits [3:0]:
Bits [7:4]:
Unicast Queue 3 to 0 not empty
0: Empty
1: Not Empty
Multicast Queue 3 to 0 not empty
12.3.4.12 MAC01 – Increment MAC port 0,1 address
CPU Address:h325
Accessed by CPU (RW)
Bits [2:0]:
Bit [3]:
Bits [42:40] of Port 0 CPU MAC address
Reserved
Bits [6:4]:
Bit [7]:
Bits [42:40] of Port 1 CPU MAC address
Reserved
MAC01, MAC23, MAC45, MAC67, and MAC9 registers are used with the MAC0~5 registers to form the CPU MAC
address on a per port basis.
12.3.4.13 MAC23 – Increment MAC port 2,3 address
CPU Address:h326
Accessed by CPU (RW)
Bits [2:0]: Bits [42:40] of Port 2 CPU MAC address
Bit [3]:
Reserved
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Bits [6:4]: Bits [42:40] of Port 3 CPU MAC address
Bit [7]:
Reserved
12.3.4.14 MAC45 – Increment MAC port 4,5 address
CPU Address:h327
Accessed by CPU (RW)
Bits [2:0]:
Bit [3]:
Bits [42:40] of Port 4 CPU MAC address
Reserved
Bits [6:4]:
Bit [7]:
Bits [42:40] of Port 5 CPU MAC address
Reserved
12.3.4.15 MAC67 – Increment MAC port 6,7 address
CPU Address:h328
Accessed by CPU (RW)
Bits [2:0]:
Bit [3]:
Bits [42:40] of Port 6 CPU MAC address
Reserved
Bits [6:4]:
Bit [7]:
Bits [42:40] of Port 7 CPU MAC address
Reserved
12.3.4.16 MAC9 – Increment MAC port 9 address
CPU Address:h329
Accessed by CPU (RW)
Bits [7:0]:
Bits [47:40] of Port 9 CPU MAC address
12.3.4.17 CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command
CPU Address:h330-336
Accessed by CPU, (R/W)
55
0
CQ6
CQ5
CQ4
CQ3
CQ2
CQ1
CQ0
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CPU Queue insertion command
Bits [9:0]:
Bits [13:10]
Bits [20:14]
Bits [35:21]
Bits [50:36]
Bit [51]
Destination Map (GMAC, CPU, port 7-0).
Priority
Number of granules for the frame
Tail pointer
Header Pointer
Multicast frame (has to be one if more than one destination port)
Reserved
Bits [54:52]
Bit [55]
Command valid (will be processed on the rising edge of the signal)
12.3.4.18 CPUQINSRPT – CPU Queue Insertion Report
CPU Address:h337
Accessed by CPU, (RO)
CPU command queue status
The command is under processing.
Bit [0]:
Bit [1]:
Insertion Fail (May be due to queue full, WRED or filtering)
12.3.4.19 CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer
CPU Address:h338-339
Accessed by CPU, (RO)
15
0
CG1
CG0
CPU Queue insertion command
Granule pointer.
Pointer valid
Bits [14:0]:
Bit [15]:
12.3.4.20 CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status
CPU Address:h33A-33E
Accessed by CPU, (R/W)
0
CR4
CR3
CR2
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CPU Queue insertion command
Header pointer
Tail pointer
Number of granules for the release
Bits [14:0]:
Bits [30:15]
Bits [38:32]
12.3.4.21 CPUGRNCTR – CPU Granule Control
CPU Address:h33f
Accessed by CPU, (R/W)
CPU receive queue status
Allocate granule to the CPU if set to one. Otherwise, do not allocate any resource.
Bit [0]:
Bit [1]:
Bit [2]:
Read allocated granule (at rising edge only)
Release info valid (will be processed at rising edge only)
12.3.5 (Group 4 Address) Search Engine Group
12.3.5.1 AGETIME_LOW – MAC address aging time Low
I²C Address h049; CPU Address:h400
Accessed by CPU and I²C (R/W)
Used in conjuction with AGETIME_HIGH. The ZL50410 removes the MAC address from the data base and sends a
Delete MAC Address Control Command to the CPU.
Bits [7:0]:
Low byte of the MAC address aging timer (Default 0x5C)
12.3.5.2 AGETIME_HIGH –MAC address aging time High
I²C Address h04A; CPU Address h401
Accessed by CPU and I²C (R/W)
Bits [7:0]:
High byte of the MAC address aging timer (Default 0x00)
The default setting of AGETIME_LOW/HIGH provides 300 seconds aging time. Aging time is based on the
following equation:
{AGETIME_HIGH,AGETIME_LOW} X (# of MAC entries in the memory X 800 µsec). Number of MAC entries = 4 K.
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12.3.5.3 SE_OPMODE – Search Engine Operation Mode
CPU Address:h403
Accessed by CPU (R/W)
Note: ECR2[2] enable/disable learning for each port.
Bit [0]:
Bit [1]:
Reserved. Must be 0.
Protocol filtering mode
0 – Inclusive (Default)
1 – Exclusive
Bit [2]:
Bit [3]:
Delete MAC report control
0 – Report MAC address deletion (MAC address is deleted from MCT after
aging time) (Default)
1 – Disable report MAC address deletion
Delete Control
0 – MAC address entry is removed when it is old enough to be aged (Default)
1 – Disable aging logic from removing MAC during aging
However, a report is still sent to the CPU in both cases, when bit [2] = 0
Bit [4]:
Enable RSVP Packet trapping
0 - Disable RSVP Packet trapping. (Default)
1 - Enable RSVP Packet trapping. IP Multicast also needs to be enabled for
this function.
Bit [5]
Bit [6]:
Bit [7]:
ARP report control
0 - No ARP packet reporting (Default)
1 - Report ARP packet to CPU
Disable MCT speed-up aging
0 – Enable speed-up aging when MCT resource is low. (Default)
1 – Disable speed-up aging when MCT resource is low.
Slow Learning
0 – Learning is performed independent of search demand (Default)
1 – Enable slow learning. Learning is temporary disabled when search
demand is high
12.3.6 (Group 5 Address) Buffer Control/QOS Group
12.3.6.1 QOSC – QOS Control
I²C Address h04B; CPU Address:h500
Accessed by CPU and I2C (R/W)
Bit [0]:
Enable TX rate control (on RMAC ports only)
0 – Disable (Default)
1 – Enable
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Bit [1]:
Enable RX rate control (on RMAC ports only)
0 – Disable (Default)
1 – Enable
Bits [4:2]:
Bit [5]:
Reserved
Select VLAN tag or TOS (IP packets) to be preferentially picked to map
transmit priority and drop priority
0 – Select VLAN Tag priority field over TOS (Default)
1 – Select TOS over VLAN tag priority field
Bit [6]:
Bit [7]:
Select TOS bits for Priority
0 – Use TOS [4:2] bits to map the transmit priority (Default)
1 – Use TOS [7:5] bits to map the transmit priority
Select TOS bits for Drop priority
0 – Use TOS [4:2] bits to map the drop priority (Default)
1 – Use TOS [7:5] bits to map the drop priority
12.3.6.2 UCC – Unicast Congestion Control
I2C Address h068, CPU Address: 510
Accessed by CPU and I2C (R/W)
Bits [7:0]:
Number of frame count. Used for best effort dropping at B% when destination
port’s best effort queue reaches UCC threshold and shared pool is all in use.
Granularity is 16 granule (Default 0x6)
12.3.6.3 MCC – Multicast Congestion Control
I²C Address h069, CPU Address: 511
Accessed by CPU and I²C (R/W)
Bits [7:0]:
In multiples of 16 granules (granularity). Used for triggering MC flow control
when destination port’s multicast best effort queue reaches MCC threshold.
(Default 0x6)
12.3.6.4 MCCTH – Multicast Threshold Control
CPU Address: 512
Accessed by CPU (R/W)
Threshold on the multicast granule count. Exceeding the threshold consider as
multicast resource low and the new multicast will be dropped at B% or flow con-
trol is triggered if enabled. (Default: 0x3)
Bits [7:0]:
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12.3.6.5 RDRC0 – WRED Rate Control 0
I²C Address 090, CPU Address 513
Accessed by CPU and I2C (R/W)
Bits [3:0]:
Bits [7:4]:
Corresponds to the frame drop percentage Y% for WRED. Granularity
6.25%.
Corresponds to the frame drop percentage X% for WRED. Granularity
6.25%.
See Programming QoS Registers application note, ZLAN-42, for more information
12.3.6.6 RDRC1 – WRED Rate Control 1
I²C Address 091, CPU Address 514
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Corresponds to the best effort frame drop percentage B%, when shared pool
is all in use and destination port best effort queue reaches UCC. Granularity
6.25%.
Corresponds to the frame drop percentage Z% for WRED. Granularity
6.25%.
See Programming QoS Registers application note, ZLAN-42, for more information
12.3.6.7 RDRC2 – WRED Rate Control 2
CPU Address 515
Accessed by CPU (R/W)
Bits [3:0]:
Bits [7:4]:
Corresponds to the frame drop percentage RB% for ingress rate control.
Granularity 6.25%.
Corresponds to the frame drop percentage RA% for ingress rate control.
Granularity 6.25%.
12.3.6.8 SFCB – Share FCB Size
I²C Address h074, CPU Address 518
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Expressed in multiples of 16 granules. Buffer reservation for shared pool.
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12.3.6.9 C1RS – Class 1 Reserve Size
I²C Address h075, CPU Address 519
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Class 1 FCB Reservation
Buffer reservation for class 1. Granularity 16 granules. (Default 0)
12.3.6.10 C2RS – Class 2 Reserve Size
I²C Address h076, CPU Address 51A
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Class 2 FCB Reservation
Buffer reservation for class 2. Granularity 16 granules. (Default 0)
12.3.6.11 C3RS – Class 3 Reserve Size
I²C Address h077, CPU Address 51B
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Class 3 FCB Reservation
Buffer reservation for class 3. Granularity 16 granules. (Default 0)
12.3.6.12 AVPML – VLAN Tag Priority Map
I²C Address h056; CPU Address:h530
Accessed by CPU and I²C (R/W)
Registers AVPML, AVPMM, and AVPMH allow the eight VLAN Tag priorities to map into eight Internal level transmit
priorities. Under the Internal transmit priority, seven is the highest priority where as zero is the lowest. This feature
allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0
of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used
inside the ZL50410. When the packet goes out it carries the original priority.
Bits [2:0]:
Bits [5:3]:
Bits [7:6]:
Priority when the VLAN tag priority field is 0 (Default 0)
Priority when the VLAN tag priority field is 1 (Default 0)
Priority when the VLAN tag priority field is 2 (Default 0)
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12.3.6.13 AVPMM – VLAN Priority Map
I²C Address h057, CPU Address:h531
Accessed by CPU and I²C (R/W)
Map VLAN priority into eight level transmit priorities:
Bit [0]:
Priority when the VLAN tag priority field is 2 (Default 0)
Priority when the VLAN tag priority field is 3 (Default 0)
Priority when the VLAN tag priority field is 4 (Default 0)
Priority when the VLAN tag priority field is 5 (Default 0)
Bits [3:1]:
Bits [6:4]:
Bit [7]:
12.3.6.14 AVPMH – VLAN Priority Map
I²C Address h058, CPU Address:h532
Accessed by CPU and I²C (R/W)
Map VLAN priority into eight level transmit priorities:
Bits [1:0]:
Bits [4:2]:
Bits [7:5]:
Priority when the VLAN tag priority field is 5 (Default 0)
Priority when the VLAN tag priority field is 6 (Default 0)
Priority when the VLAN tag priority field is 7 (Default 0)
12.3.6.15 AVDM – VLAN Discard Map
I²C Address h05C, CPU Address:h533
Accessed by CPU and I²C (R/W)
Map VLAN priority into frame discard when low priority buffer usage is above threshold
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Frame drop priority when VLAN Tag priority field is 0 (Default 0)
Frame drop priority when VLAN Tag priority field is 1 (Default 0)
Frame drop priority when VLAN Tag priority field is 2 (Default 0)
Frame drop priority when VLAN Tag priority field is 3 (Default 0)
Frame drop priority when VLAN Tag priority field is 4 (Default 0)
Frame drop priority when VLAN Tag priority field is 5 (Default 0)
Frame drop priority when VLAN Tag priority field is 6 (Default 0)
Frame drop priority when VLAN Tag priority field is 7 (Default 0)
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12.3.6.16 TOSPML – TOS Priority Map
I²C Address h059, CPU Address:h540
Accessed by CPU and I²C (R/W)
Map TOS field in IP packet into eight level transmit priorities
Bits [2:0]:
Bits [5:3]:
Bits [7:6]:
Priority when the TOS field is 0 (Default 0)
Priority when the TOS field is 1 (Default 0)
Priority when the TOS field is 2 (Default 0)
12.3.6.17 TOSPMM – TOS Priority Map
I²C Address h05A, CPU Address:h541
Accessed by CPU and I²C (R/W)
Map TOS field in IP packet into eight level transmit priorities
Bit [0]:
Priority when the TOS field is 2 (Default 0)
Priority when the TOS field is 3 (Default 0)
Priority when the TOS field is 4 (Default 0)
Priority when the TOS field is 5 (Default 0)
Bits [3:1]:
Bits [6:4]:
Bit [7]:
12.3.6.18 TOSPMH – TOS Priority Map
I²C Address h05B, CPU Address:h542
Accessed by CPU and I²C (R/W)
Map TOS field in IP packet into eight level transmit priorities:
Bits [1:0]:
Bits [4:2]:
Bits [7:5]:
Priority when the TOS field is 5 (Default 0)
Priority when the TOS field is 6 (Default 0)
Priority when the TOS field is 7 (Default 0)
12.3.6.19 TOSDML – TOS Discard Map
I²C Address h05D, CPU Address:h543
Accessed by CPU and I²C (R/W)
Map TOS into frame discard when low priority buffer usage is above threshold
Bit [0]:
Bit [1]:
Bit [2]:
Frame drop priority when TOS field is 0 (Default 0)
Frame drop priority when TOS field is 1 (Default 0)
Frame drop priority when TOS field is 2 (Default 0)
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Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Frame drop priority when TOS field is 3 (Default 0)
Frame drop priority when TOS field is 4 (Default 0)
Frame drop priority when TOS field is 5 (Default 0)
Frame drop priority when TOS field is 6 (Default 0)
Frame drop priority when TOS field is 7 (Default 0)
12.3.6.20 USER_PROTOCOL_n – User Define Protocol 0~7
I²C Address h0B3+n, CPU Address:h550+n
Accessed by CPU and I²C (R/W)
(Default 00) This register is duplicated eight times from PROTOCOL 0~7 and allows the CPU to define eight
separate protocols.
Bits [7:0]:
User Define Protocol
12.3.6.21 USER_PROTOCOL_FORCE_DISCARD – User Define Protocol 0~7 Force Discard
I²C Address h0BB, CPU Address 558
Accessed by CPU and I²C (R/W)
Bit [0]:
Enable Protocol 0 Force Discard
1 – Enable
0 – Disable
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Enable Protocol 1 Force Discard
Enable Protocol 2 Force Discard
Enable Protocol 3 Force Discard
Enable Protocol 4 Force Discard
Enable Protocol 5 Force Discard
Enable Protocol 6 Force Discard
Enable Protocol 7 Force Discard
User Defined Logical Ports and Well Known Ports
The ZL50410 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well
Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are:
•
•
•
•
•
23
512
6000
443
111
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•
•
•
22555
22
554
Their respective priority can be programmed via WELL_KNOWN_PORT[7:0]_PRIORITY register.
WELL_KNOWN_PORT[_ENABLE can individually turn on/off each Well Known Port if desired.
Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select
specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7
registers. Two registers are required to be programmed for the logical port number. The respective priority can be
programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via
User_Port_Enable register.
The User Defined Range provides a range of logical port numbers with the same priority level. Programming is
similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need
to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit
is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the
upper limit and more than the lower limit will use the priority specified in RPRIORITY.
12.3.6.22 WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority
I²C Address h0A8, CPU Address 560
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for Well known port 0 (23 for telnet)
Priority setting, transmission + dropping, for Well known port 1 (512 for
TCP/UDP)
12.3.6.23 WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority
I²C Address h0A9, CPU Address 561
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for Well known port 2 (6000 for
XWIN)
Priority setting, transmission + dropping, for Well known port 3 (443 for HTTP
sec)
12.3.6.24 WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority
I²C Address h0AA, CPU Address 562
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for Well known port 4 (111 for sun
remote procedure call)
Priority setting, transmission + dropping, for Well known port 5 (22555 for IP
Phone call setup)
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12.3.6.25 WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority
I²C Address h0AB, CPU Address 563
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for Well known port 6 (22 for ssh)
Priority setting, transmission + dropping, for Well known port 7 (554 for rtsp)
12.3.6.26 WELL_KNOWN_PORT_ENABLE – Well Known Logic Port 0 to 7 Enables
I²C Address h0AC, CPU Address 564
Accessed by CPU and I²C (R/W)
Bit [0]:
Enable Well Known Port 0 Priority
1 – Enable
0 – Disable
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Enable Well Known Port 1 Priority
Enable Well Known Port 2 Priority
Enable Well Known Port 3 Priority
Enable Well Known Port 4 Priority
Enable Well Known Port 5 Priority
Enable Well Known Port 6 Priority
Enable Well Known Port 7 Priority
12.3.6.27 WELL_KNOWN_PORT_FORCE_DISCARD – Well Known Logic Port 0~7 Force
Discard
I²C Address h0AD, CPU Address 565
Accessed by CPU and I²C (R/W)
Bit [0]:
Enable Well Known Port 0 Force Discard
1 – Enable
0 – Disable
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Enable Well Known Port 1 Force Discard
Enable Well Known Port 2 Force Discard
Enable Well Known Port 3 Force Discard
Enable Well Known Port 4 Force Discard
Enable Well Known Port 5 Force Discard
Enable Well Known Port 6 Force Discard
Enable Well Known Port 7 Force Discard
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12.3.6.28 USER_PORT[7:0]_[LOwithHIGH] – User Define Logical Port 0~7
I²C Address h092+n(Low); CPU Address 570+2n(Low) (n = logical port number)
I²C Address h09A+n(High); CPU Address 571+2n(High)
Accessed by CPU and I²C (R/W)
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define
eight separate ports.
7
7
0
0
TCP/UDP Logic Port Low
TCP/UDP Logic Port High
12.3.6.29 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
I²C Address h0A2, CPU Address 590
Accessed by CPU and I²C (R/W)
The chip allows the CPU to define the priority
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for logic port 0
Priority setting, transmission + dropping, for logic port 1 (Default 00)
12.3.6.30 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
I²C Address h0A3, CPU Address 591
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for logic port 2
Priority setting, transmission + dropping, for logic port 3 (Default 00)
12.3.6.31 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
I²C Address h0A4, CPU Address 592
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for logic port 4
Priority setting, transmission + dropping, for logic port 5 (Default 00)
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12.3.6.32 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority
I²C Address h0A5, CPU Address 593
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for logic port 6
Priority setting, transmission + dropping, for logic port 7 (Default 00)
12.3.6.33 USER_PORT_ENABLE[7:0] – User Define Logic Port 0 to 7 Enables
I²C Address h0A6, CPU Address 594
Accessed by CPU and I²C (R/W)
Bit [0]:
Enable User Port 0 Priority
1 – Enable
0 – Disable
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Enable User Port 1 Priority
Enable User Port 2 Priority
Enable User Port 3 Priority
Enable User Port 4 Priority
Enable User Port 5 Priority
Enable User Port 6 Priority
Enable User Port 7 Priority
12.3.6.34 USER_PORT_FORCE_DISCARD[7:0] – User Define Logic Port 0~7 Force Discard
I²C Address h0A7, CPU Address 595
Accessed by CPU and I²C (R/W)
Bit [0]:
Enable User Port 0 Force Discard
1 – Enable
0 – Disable
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Enable User Port 1 Force Discard
Enable User Port 2 Force Discard
Enable User Port 3 Force Discard
Enable User Port 4 Force Discard
Enable User Port 5 Force Discard
Enable User Port 6 Force Discard
Enable User Port 7 Force Discard
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12.3.6.35 RLOWL – User Define Range Low Bit 7:0
I²C Address h0AE, CPU Address: 5A0
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Lower 8 bit of the User Define Logical Port Low Range
12.3.6.36 RLOWH – User Define Range Low Bit 15:8
I²C Address h0AF, CPU Address: 5A1
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Upper 8 bit of the User Define Logical Port Low Range
12.3.6.37 RHIGHL – User Define Range High Bit 7:0
I²C Address h0B0, CPU Address: 5A2
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Lower 8 bit of the User Define Logical Port High Range
12.3.6.38 RHIGHH – User Define Range High Bit 15:8
I²C Address h0B1, CPU Address: 5A3
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Upper 8 bit of the User Define Logical Port High Range
12.3.6.39 RPRIORITY – User Define Range Priority
I²C Address h0B2, CPU Address: 5A4
Accessed by CPU and I²C (R/W)
RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY.
Bit [0]:
Drop Priority (inclusive only)
Transmit Priority (inclusive only)
Reserved
Bits [3:1]
Bits [5:4]
Bits [7:6]
00 - No Filtering
01 - Exclusive Filtering (x<=RLOW or x>=RHIGH)
10 - Inclusive Filtering (RLOW<x<RHIGH)
11 - Invalid
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12.3.7 (Group 6 Address) MISC Group
12.3.7.1 MII_OP0 – MII Register Option 0
I²C Address 0BC, CPU Address:h600
Accessed by CPU and I²C (R/W)
Bits [4:0]:
Bits [5]
Vendor specified link status register address (null value means don’t use it)
(Default 00). This is used if the Linkup bit position in the PHY is non-standard
Disable jabber detection. This is for HomePNA applications or any serial
operation slower than 10 Mbps.
0 = Enable
1 = Disable
Bits [6]
Bit [7]:
Reserved
Half duplex flow control feature
0 = Half duplex flow control always enable
1 = Half duplex flow control by negotiation
12.3.7.2 MII_OP1 – MII Register Option 1
I²C Address 0BD, CPU Address:h601
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Duplex bit location in vendor specified register
Speed bit location in vendor specified register
(Default 00)
12.3.7.3 FEN – Feature Register
I²C Address 0BE, CPU Address:h602)
Accessed by CPU and I²C (R/W)
Bit [0]:
Statistic Counter
0 – Disable (Default)
1 – Enable (all ports)
When statistic counter is enable, an interrupt control frame is generated to
the CPU, every time a counter wraps around. This feature requires an
external CPU.
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Data Sheet
Bit [1]:
Private VLAN Edge Support
0: Disable (default)
1: Enable
If this feature is enabled, use registers PVLAN_Pn to set up the egress
protected port map. This feature is only applicable in tagged-based VLAN
mode (PVMODE[0]=’1’). In port-based VLAN mode (PVMODE[0]=’0’), this bit
must be 0.
See Private VLAN Edge application note, ZLAN-130, for more information.
Bit [2]:
Support DS EF Code.
0 – Disable (Default)
1 – Enable (all ports)
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for
110 and drop is set for 0.
Bit [3]:
Bit [4]:
Enable VLAN ID hashing
0 – Disable (Default)
1 – Enable
Disable IP Multicast Support
0 – Enable IP Multicast Support (Must also set PVMODE[6]=1)
1 – Disable IP Multicast Support (Default)
When enable, IGMP packets are identified by search engine and are passed
to the CPU for processing. IP multicast packets are forwarded to the IP
multicast group members according to the VLAN port mapping table.
Bit [5]:
Report to CPU
0 – Disable (Default)
1 – Enable
When disable new VLAN port association report, new MAC address report or
aging reports are disable for all ports. When enable, register SE_OPMODE is
used to enable/disable selectively each function.
Bit [6]:
Bit [7]:
MII Management State Machine
0: Enable (Default)
1: Disable
This bit must be set so that there is no contention on the MDIO bus between
MII Management state machine and MIIC & MIID PHY register accesses.
MCT Link List structure
0 – Enable (Default)
1 – Disable
12.3.7.4 MIIC0 – MII Command Register 0
CPU Address:h603
Accessed by CPU (R/W)
Bits [7:0]:
MII Command Data [7:0]
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Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then
program MII command.
12.3.7.5 MIIC1 – MII Command Register 1
CPU Address:h604
Accessed by CPU (R/W)
Bits [7:0]:
MII Command Data [15:8]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
12.3.7.6 MIIC2 – MII Command Register 2
CPU Address:h605
Accessed by CPU (R/W)
Bits [4:0]
Bits [6:5]
Bits [7]
REG_AD – Register PHY Address
OP – Operation code “10” for read command and “01” for write command
Reserved
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
12.3.7.7 MIIC3 – MII Command Register 3
CPU Address:h606
Accessed by CPU (R/W)
Bits [4:0]
Bit [5]
PHY_AD – 5 Bit PHY Address
Reserved
Bit [6]
VALID – Data Valid from PHY (Read Only)
RDY – Data is returned from PHY (Read Only)
Bit [7]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command. Writing this register will initiate a serial management cycle to the MII management
interface.
12.3.7.8 MIID0 – MII Data Register 0
CPU Address:h607
Accessed by CPU (RO)
Bits [7:0]:
MII Data [7:0]
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12.3.7.9 MIID1 – MII Data Register 1
CPU Address:h608
Accessed by CPU (RO)
Bits [7:0]:
MII Data [15:8]
12.3.7.10 USD – One Micro Second Divider
CPU Address:h609
Accessed by CPU (R/W)
Bits [5:0]: Divider to get one micro second from M_CLK (only used when not in standard RMII mode)
In a MII or GPSI system, a 50MHz M_CLK may not be available. The system designer can
decide to use another frequency on the M_CLK signal. To compensate for this, this register
is required to be programmed.
For example. If 20MHz is used on M_CLK, to compensate for the difference, this register is
programmed with 20 to provide 1usec for internal reference.
Bits [7:6]: Reserved
12.3.7.11 DEVICE Mode
CPU Address:h60A
Accessed by CPU (R/W)
Bit [0]:
Bit [1]:
Reserved
CPU Interrupt Polarity
0: Negative Polarity
1: Positive Polarity (Default)
Bits [4:2]:
Bits [7:5]:
Reserved
DEVICE ID (Default 0). This is for stacking operation. This is the stack ID for
loop topology.
12.3.7.12 CHECKSUM - EEPROM Checksum
I²C Address 0FF, CPU Address:h60B
Accessed by CPU and I²C (R/W)
Bits [7:0]:
Checksum content (Default 0)
This register is used in unmanaged mode only. Before requesting that the ZL50410 updates the EEPROM device,
the correct checksum needs to be calculated and written into this checksum register.
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The checksum formula is:
FF
Σ
I²C register = 0
i = 0
When the ZL50410 boots from the EEPROM the checksum is calculated and the value must be zero. If the
checksum is not zeroed the ZL50410 does not start and pin CHECKSUM_OK is set to zero.
12.3.7.13 LHBTimer – Link Heart Beat Timeout Timer
CPU Address:h610
Accessed by CPU (R/W)
In slot time (512 bit time). LHB packet will be sent out to the remote device if no other packet is transmitted in half
this period. The receiver will trigger LHB timeout interrupt if not receiving any good packet in this period.
12.3.7.14 LHBReg0, LHBReg1 - Link Heart Beat OpCode
CPU Address:h611, h612
Accessed by CPU (R/W)
The LHB frame uses MAC control frame format (same as flow control frame.) The register here defines the
operation code (we recommend h00-12).
12.3.7.15 fMACCReg0, fMACCReg1 - MAC Control Frame OpCode
CPU Address:h613, h614
Accessed by CPU (R/W)
The registers define the operation code if MAC control frame is forced out by processor.
12.3.7.16 FCB Base Address Register 0
I²C Address 0BF, CPU Address:h620
Accessed by CPU and I²C (R/W)
Bits [7:0]
FCB Base address bit 7:0 (Default 0)
12.3.7.17 FCB Base Address Register 1
I²C Address 0C0, CPU Address:h621
Accessed by CPU and I²C (R/W)
Bits [7:0]
FCB Base address bit 15:8 (Default 0x60)
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Data Sheet
12.3.7.18 FCB Base Address Register 2
I²C Address 0C1, CPU Address:h622
Accessed by CPU and I²C (R/W)
Bits [7:0]
FCB Base address bit 23:16 (Default 0)
12.3.8 (Group 7 Address) Port Mirroring Group
12.3.8.1 MIRROR CONTROL – Port Mirror Control Register
CPU Address 70C
Accessed by CPU (R/W) (Default 00)
Bits [3:0]:
Bit [4]
Destination port to be mirrored to.
Mirror Flow from MIRROR_SRC_MAC[5:0] to MIRROR_DEST_MAC[5:0]
Mirror Flow from MIRROR_DEST_MAC[5:0] to MIRROR_SRC_MAC[5:0]
Mirror when address is destination
Bit [5]
Bit [6]:
Bit [7]:
Mirror when address is source
12.3.8.2 MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0~5
CPU Address 700-705
Accessed by CPU (R/W)
DEST_MAC5 DEST_MAC4 DEST_MAC3 DEST_MAC2 DEST_MAC1 DEST_MAC0
[47:40]
[39:32]
[31:24]
[23:16]
[15:8]
[7:0]
(Default 00)
(Default 00)
(Default 00)
(Default 00)
(Default 00)
(Default 00)
12.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0~5
CPU Address 706-70B
Accessed by CPU (R/W)
SRC_MAC5
SRC_MAC4
SRC_MAC3
SRC_MAC2
SRC_MAC1
SRC_MAC0
[47:40]
[39:32]
[31:24]
[23:16]
[15:8]
[7:0]
(Default 00)
(Default 00)
(Default 00)
(Default 00)
(Default 00)
(Default 00)
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12.3.8.4 RMAC_MIRROR0 – RMAC Mirror 0
CPU Address 710
Accessed by CPU (R/W)
Bits [2:0]:
Bit [3]:
Source port to be mirrored
Mirror path
0: Receive
1: Transmit
Bits [6:4]:
Bit [7]:
Destination port for mirrored traffic
Mirror enable
12.3.8.5 RMAC_MIRROR1 – RMAC Mirror 1
CPU Address 711
Accessed by CPU (R/W)
Bits [2:0]:
Bit [3]:
Source port to be mirrored
Mirror path
0: Receive
1: Transmit
Bits [6:4]:
Bit [7]:
Destination port for mirrored traffic
Mirror enable
12.3.9 (Group 8 Address) Per Port QOS Control
12.3.9.1 FCRn – Port 0~9 Flooding Control Register
I²C Address h04C+n; CPU Address:h800+n (n = port number)
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [6:4]:
U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits
[6:4]. This is used to limit the amount of flooding traffic from Port n. The value
in U2MR specifies how many packets are allowed to flood within the time
specified by bit [6:4]. To disable this function, program U2MR to 0.
(Default = 0)
Time Base for Unicast to Multicast, Multicast and Broadcast rate control of
Port n: (Default = 000)
000 = 100 us
001 = 200 us
010 = 400 us
011 = 800 us
100 = 1.6 ms
101 = 3.2 ms
110 = 6.4 ms
111 = 12.8 ms
Bit [7]:
Reserved
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12.3.9.2 BMRCn - Port 0~9 Broadcast/Multicast Rate Control
I²C Address h05E+n, CPU Address:h820+n (n = port number)
Accessed by CPU and I²C (R/W)
This broadcast and multicast rate defines for Port n, the number of packets allowed to be forwarded within a
specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field
to 0. Time base is based on register FCR0 [6:4]
Bits [3:0]:
Bits [7:4]:
Multicast Rate Control. Number of multicast packets allowed within the time defined in
bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0).
Broadcast Rate Control. Number of broadcast packets allowed within the time defined
in bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0)
12.3.9.3 PR100_n – Port 0~7 Reservation
I²C Address h06A+n, CPU Address 840+n (n = port number)
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.4 PR100_CPU – Port CPU Reservation
I²C Address h073, CPU Address 848
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.5 PRG – Port GMAC Reservation
I²C Address h072, CPU Address 849
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. (Default 0x24)
12.3.9.6 PTH100_n – Port 0~7 Threshold
I²C Address h0C2+n, CPU Address 860+n (n = port number)
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x3)
12.3.9.7 PTH100_CPU – Port CPU Threshold
I²C Address h0CB, CPU Address 868
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x3)
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12.3.9.8 PTHG – Port GMAC Threshold
I²C Address h0CA, CPU Address 869
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x12)
12.3.9.9 QOSC00, QOSC01 - Classes Byte Limit port 0
Accessed by CPU and I²C (R/W)
•
•
QOSC00 – BYTE_L1 (I²C Address h078, CPU Address 880)
QOSC01 – BYTE_L2 (I²C Address h079, CPU Address 881)
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.10 QOSC02, QOSC15 - Classes Byte Limit port 1-7
I²C Address 07A-087, CPU Address:h882-88F
Accessed by CPU and I²C (R/W)
Same as QOSC00, QOSC01
12.3.9.11 QOSC16 - QOSC21 - Classes Byte Limit CPU port
Accessed by CPU and I2C (R/W):
•
•
•
•
•
•
QOSC16 – BYTE_L11 Level 1 for queue 1 (I2C Address h088, CPU Address 890)
QOSC17 – BYTE_L21 Level 2 for queue 1 (I2C Address h089, CPU Address 891)
QOSC18 – BYTE_L12 Level 1 for queue 2 (I2C Address h08A, CPU Address 892)
QOSC19 – BYTE_L22 Level 2 for queue 2 (I2C Address h08B, CPU Address 893)
QOSC20 – BYTE_L13 Level 1 for queue 3 (I2C Address h08C, CPU Address 894)
QOSC21 – BYTE_L23 Level 2 for queue 3 (I2C Address h08D, CPU Address 895)
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.12 QOSC22 - QOSC27 - Classes Byte Limit GMAC port
Accessed by CPU and I²C (R/W)
•
•
•
•
•
•
QOSC22 – BYTE_L11 Level 1 for queue 1 (I²C Address h08E, CPU Address 896)
QOSC23 – BYTE_L21 Level 2 for queue 1 (I²C Address h08F, CPU Address 897)
QOSC24 – BYTE_L12 Level 1 for queue 2 (CPU Address 898)
QOSC25 – BYTE_L22 Level 2 for queue 2 (CPU Address 899)
QOSC26 – BYTE_L13 Level 1 for queue 3 (CPU Address 89A)
QOSC27 – BYTE_L23 Level 2 for queue 3 (CPU Address 89B)
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
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12.3.9.13 QOSC28 - QOSC31 - Classes WFQ Credit For GMAC
Accessed by CPU (R/W)
W0 – QOSC28[5:0] – CREDIT_C00 (CPU Address 89C)
W1 – QOSC29[5:0] – CREDIT_C01 (CPU Address 89D)
W2 – QOSC30[5:0] – CREDIT_C02 (CPU Address 89E)
W3 – QOSC31[5:0] – CREDIT_C03 (CPU Address 89F)
QOSC28 through QOSC31 represents one set of WFQ parameters for GMAC port. The granularity of the numbers
is 1, and their sum must be 64. QOSC31 corresponds to W3 that is the highest priority, and QOSC27 corresponds
to W0. Default scheduling method will be strict priority across all queues. Only when the bit 7 in the class is set, the
queue will be scheduled as WFQ. The credit number also works as shaper credit if bit 6 is set. The queue with
shaper enabled will be scheduled by strict priority when the token is available. The shaper setting override the NS
setting.
Bits [5:0]:
Bit [6]:
Class scheduling credit
Shaper enable
Bit [7]:
Not strict priority apply
12.3.9.14 QOSC36 - QOSC39 - Shaper Control Port GMAC
Accessed by CPU (R/W)
W0 – QOSC36[7:0] – TOKEN_LIMIT_C00 (CPU Address 8A4)
W1 – QOSC37[7:0] – TOKEN_LIMIT_C01 (CPU Address 8A5)
W2 – QOSC38[7:0] – TOKEN_LIMIT_C02 (CPU Address 8A6)
W3 – QOSC39[7:0] – TOKEN_LIMIT_C03 (CPU Address 8A7)
QOSC36 through QOSC39 represents one set of token limit on the shaper of GMAC port. The granularity of the
numbers is 64 bytes. The shaper is implemented as leaky bucket and the limit here works as bucket size. Since the
hardware implementation can keep negative number, the limit can be as small as one and still can transmit
oversized frame, as long as one byte token is available.
12.3.10 (Group E Address) System Diagnostic
NOTE: Device Manufacturing test registers.
12.3.10.1 DTSRL – Test Output Selection
CPU Address E00
Accessed by CPU (R/W)
Test group selection for testout[7:0].
12.3.10.2 DTSRM – Test Output Selection
CPU Address E01
Accessed by CPU (R/W)
Test group selection for testout[15:8].
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12.3.10.3 TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8]
CPU Address E02, E03
Accessed by CPU (RO)
12.3.10.4 MASK0-MASK4 – Timeout Reset Mask
CPU Address E10-E14
Accessed by CPU (R/W)
Disable timeout reset on selected state machine status.
See Programming Timeout Reset application note, ZLAN-41, for more information.
12.3.10.5 BOOTSTRAP0 – BOOTSTRAP3
CPU Address E80-E83
Accessed by CPU (RO)
31
23
15
0
BT3
BT2
BT1
BT0
Bits [15:0]:
Bootstrap value from TSTOUT[15:0]:
Bit [6:0]: TSTOUT[6:0]
Bit [8:7]: Invert of TSTOUT[8:7]
Bit [9]: TSTOUT[11]
Bit [10]: TSTOUT[9]
Bit [11]: TSTOUT[10]
Bit [14:12]: TSTOUT[14:12]
Bit [15]: Always 0
Bits [23:16]:
Bootstrap value from M[7:0]_TXEN
Bit [16]: M0_TXEN
Bit [17]: M1_TXEN
...
Bit [23]: M7_TXEN
Bits [25:24]:
Bits [31:26]:
Bootstrap value from M9_TXEN, M9_TXER
Reserved
12.3.10.6 PRTFSMST0~9
CPU Address E90+n
Accessed by CPU (RO)
TX FSM NOT idle for 5 sec
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
TX FIFO control NOT idle for 5 sec
RX SFD detection NOT idle for 5 sec
RXINF NOT idle for 5 sec
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PTCTL NOT idle for 5 sec
Reserved
Bit [4]:
Bit [5]:
Bit [6]
Bit [7]:
LHB frame detected
LHB receiving timeout
12.3.10.7 PRTQOSST0-PRTQOSST7
CPU Address EA0+n
Accessed by CPU (RO)
Source port reservation low
No source port buffer left
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Unicast congestion detected on best effort queue
Reserved
High priority queue reach L1 WRED level
High priority queue reach L2 WRED level
Low priority MC queue full
High priority MC queue full
12.3.10.8 PRTQOSST8A, PRTQOSST8B (CPU port)
CPU Address EA8 – EA9
Accessed by CPU (RO)
0
15
PQSTB
PQSTA
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [8]:
Source port reservation low
No source port buffer left
Unicast congestion detected on best effort queue
Reserved
priority queue 1 reach L1 WRED level
priority queue 1 reach L2 WRED level
priority queue 2 reach L1 WRED level
priority queue 2 reach L2 WRED level
priority queue 3 reach L1 WRED level
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Bit [9]:
priority queue 3 reach L2 WRED level
priority 0 MC queue full
Bit [10]:
Bit [11]:
Bit [12]:
Bit [13]:
priority 1 MC queue full
priority 2 MC queue full
Priority 3 MC queue full
Bits [15:14]: Reserved
12.3.10.9 PRTQOSST9A, PRTQOSST9B (GMAC port)
CPU Address EAA – EAB
Accessed by CPU (RO)
0
15
PQSTB
PQSTA
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [8]:
Bit [9]:
Bit [10]:
Bit [11]:
Bit [12]:
Bit [13]:
Source port reservation low
No source port buffer left
Unicast congestion detected on best effort queue
Reserved
Priority queue 1 reach L1 WRED level
Priority queue 1 reach L2 WRED level
Priority queue 2 reach L1 WRED level
Priority queue 2 reach L2 WRED level
Priority queue 3 reach L1 WRED level
Priority queue 3 reach L2 WRED level
Priority 0 MC queue full
Priority 1 MC queue full
Priority 2 MC queue full
Priority 3 MC queue full
Bits [15:14]: Reserved
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12.3.10.10 CLASSQOSST
CPU Address EAC
Accessed by CPU (RO)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
No share buffer
No class 1 buffer
No class 2 buffer
No class 3 buffer
Bits [7:4]: Reserved
12.3.10.11 PRTINTCTR
CPU Address EAD
Accessed by CPU (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Interrupt when source buffer low
Interrupt when no source buffer
Interrupt when UC congest
Interrupt when L1 WRED level
Interrupt when L2 WRED level
Interrupt when MC queue full
Interrupt when LHB timeout
Interrupt when no class buffer
12.3.10.12 QMCTRL0~9
CPU Address EB0+n
Accessed by CPU (R/W)
Bit [0]:
Bit [1]:
Suspend port scheduling (no departure)
Reset queue
Bits [4:2]: Reserved
Bit [5]:
Bit [6]:
Bit [7]:
Force out MAC control frame
Force out XOFF flow control frame
Force out XON flow control frame
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Data Sheet
12.3.10.13 QCTRL
CPU Address EBA
Accessed by CPU (R/W)
Stop QM FSM at idle
Stop MCQ FSM at idle
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bits [7:4]:
Stop new granule grant to any source
Stop release granule from any source
Reserved
12.3.10.14 BMBISTR0, BMBISTR1
CPU Address EBB, EBC
Accessed by CPU (RO)
12.3.10.15 BMControl
CPU Address EBD
Accessed by CPU (R/W)
Bits [3:0]: Block Memory redundancy control
0: Use hardware detected value
All others: Overwrite the hardware detected memory swap map
Bits [7:4]: Reserved
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Data Sheet
12.3.10.16 BUFF_RST
CPU Address EC0
Accessed by CPU (R/W)
Bits [3:0] Assign a value that the pool to be reset
0: port 0 pool
1: port 1 pool
2: port 2 pool
3: port 3 pool
4: port 4 pool
5: port 5 pool
6: port 6 pool
7: port 7 pool
8: port GMAC pool
9: shared pool
10: class 1 pool
11: class 2 pool
12: class 3 pool
13: multicast pool
14: cpu pool
15: reserved
Bit [4]
Bit [5]
If this bit is 1, then all the pools are assigned
Set 1 to reset the pools that are assigned
Bits [7:6] Reserved
If CPU wants to reset pools again, CPU has to clear bit 5 and then set bit 5.
Note: Before CPU doing so, CPU should set QCTRL (CPU Address EBA) bit 2 and bit 3 to one. After reset the
pools, CPU shall reprogram free granule link list (CPU address EC1, EC2, EC3, EC4, EC5, EC6). Then clear
QCTRL (EBA).
12.3.10.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1
CPU address EC1
Accessed by CPU (R/W)
Fcb_head_ptr[7:0]. The head pointer of free granule link that CPU assigns.
Bits [7:0]
CPU address EC2
Accessed by CPU (R/W)
Fcb_head_ptr[14:8]. The head pointer of free granule link that CPU assigns.
Set 1 to write
Bits [6:0]
Bit [7]
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
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Data Sheet
12.3.10.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1
CPU address EC3
Accessed by CPU (R/W)
Bits [7:0]
Fcb_tail_ptr[7:0]. The tail pointer of free granule link that CPU assigns.
CPU address EC4
Accessed by CPU (R/W)
Bits [6:0]
Bit [7]
Fcb_tail_ptr[14:8]. The tail pointer of free granule link that CPU assigns.
Set 1 to write
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
12.3.10.19 FCB_NUM0, FCB_NUM1
CPU address EC5
Accessed by CPU (R/W)
Bits [7:0] Fcb_number[7:0]. The total number of granules that CPU assigns.
CPU address EC6
Accessed by CPU (R/W)
Bits [6:0] Fcb_number[14:8]. The total number of granules that CPU assigns.
Bit [7]
Set 1 to write
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
Note: There are two ways to reprogram the free granules.
1. CPU links all the granules: CPU writes memory directly, at last write head pointer (address EC1, EC2), tail
pointer (address EC3, EC4) and granule number (address EC5, EC6).
2. CPU tells Buffer Manager to link: CPU clear head pointer (address EC1, EC2), clear tail pointer (address EC3,
EC4), then write granule number that tells Buffer Manager to link (address EC5, EC6).
12.3.10.20 BM_RLSFF_CTRL
CPU address EC7
Accessed by CPU (R/W)
Bit [0]
Read BM release FIFO.
Bits [7:1] Reserved
The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA,
EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit
0 is changing from 0 to 1.
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Data Sheet
12.3.10.21 BM_RSLFF_INFO[5:0]
CPU address EC8
Accessed by CPU (RO)
Bits [7:0] Rls_head_ptr[7:0].
CPU address EC9
Accessed by CPU (RO)
Bits [6:0]
Bit [7]
Rls_head_ptr[14:8].
Rls_tail_ptr[0]
CPU address ECA
Accessed by CPU (RO)
Bits [7:0]
Rls_tail_ptr[8:1]
CPU address ECB
Accessed by CPU (RO)
Bits [5:0] Rls_tail_ptr[14:9]
Bits [7:6] Rls_count[1:0]
CPU address ECC
Accessed by CPU (RO)
Bits [4:0] Rls_count[6:2]
Bit [5] If 1, then It is multicast packet.
Bits [7:6] Rls_src_port[1:0[
CPU address ECD
Accessed by CPU (RO)
Bits [1:0] Rls_src_port[3:2]
Bits [3:2] Class[1:0]
Bit [4] This release request is from QM directly.
Bits [7:5] Entries count in release FIFO, 0 means FIFO is empty
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Data Sheet
12.3.11 (Group F Address) CPU Access Group
12.3.11.1 GCR - Global Control Register
CPU Address: hF00
Accessed by CPU (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is
found in the DCR register.
Bit [3]:
Bit [4]:
Soft Reset (Default = 0)
Write ‘1’ to reset chip
Initialization Completed (Default = 0)
This bit is reserved in unmanaged mode.
In managed mode, the CPU writes this bit with ‘1’ to indicate initialization is
completed and ready to forward packets. The ‘0' to '1' transition will toggle
TSTOUT[2] from low to high.
Bits [7:5]:
Reserved
12.3.11.2 DCR - Device Status and Signature Register
CPU Address: hF01
Accessed by CPU (RO)
Bit [0]:
1: Busy writing configuration to I²C
0: Not busy (not writing configuration to I²C)
Bit [1]:
1: Busy reading configuration from I²C
0: Not busy (not reading configuration from I²C)
Bit [2]:
1: BIST in progress
0: BIST not running
Bit [3]:
1: RAM Error
0: RAM OK
Bits [5:4]:
Bits [7:6]:
Device Signature
11: ZL50410 device
Revision
00: Initial Silicon
01: Second Silicon
10: Third Silicon
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Data Sheet
12.3.11.3 DCR1 - Device Status Register 1
CPU Address: hF02
Accessed by CPU (RO)
Bits [6:0]
Bit [7]
Reserved
Chip initialization completed
12.3.11.4 DPST – Device Port Status Register
CPU Address:hF03
Accessed by CPU (R/W)
Bits [4:0]:
Read back index register. This is used for selecting what to read back from
DTST. (Default 00)
-
-
-
-
-
-
-
-
-
-
5’b00000 - Port 0 Operating mode and Negotiation status
5’b00001 - Port 1 Operating mode and Negotiation status
5’b00010 - Port 2 Operating mode and Negotiation status
5’b00011 - Port 3 Operating mode and Negotiation status
5’b00100 - Port 4 Operating mode and Negotiation status
5’b00101 - Port 5 Operating mode and Negotiation status
5’b00110 - Port 6 Operating mode and Negotiation status
5’b00111 - Port 7 Operating mode and Negotiation status
5’b01000 - Port CPU Operating mode and Negotiation status
5’b01001 - Port GMAC Operating mode and Negotiation status
Bits [7:5]:
Reserved
12.3.11.5 DTST – Data read back register
CPU Address: hF04
Accessed by CPU (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Port Control
Application Note, ZLAN-37.
Bit [0]
Flow control enable
1: Flow control
0: No flow control
Bit [1]
Full duplex port
1: Full duplex
0: Half duplex
Bit [2]
Bit [3]
Fast Ethernet port (if bit [5] not set)
1: FE Port
Link is down
1: Link down
0: Link up
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Data Sheet
Bit [4]
Bit [5]
Auto negotiation disabled
1: Disable
0: Enable
Gigabit Ethernet port
1: GE Port
Bit [6]
Bit [7]
Reserved
Module detected (for hot swap purpose)
0: No module
1: Module detected
Note: If Module Detect feature is disabled (bootstrap TSTOUT[9]=’0’), this bit
will always be ‘1’.
12.3.11.6 DA – Dead or Alive Register
CPU Address: hFFF
Accessed by CPU (RO)
Always return 8’h DA. Indicate the CPU interface or serial port connection is good.
Bits [7:0]
Always return DA
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Data Sheet
13.0 Characteristics and Timing
13.1 Absolute Maximum Ratings
Storage Temperature
-65°C to +150°C
-40°C to +85°C
Operating Temperature
Maximum Junction Temperature
Supply Voltage VCC with Respect to VSS
Supply Voltage VDD with Respect to VSS
Voltage on 5 V Tolerant Input Pins
Voltage on Other Pins
+125°C
+2.95 V to +3.65 V
+1.60 V to +2.00 V
-0.5 V to (VCC + 2.5 V)
-0.5 V to (VDD + 0.3 V)
Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for
extended periods may affect device reliability. Functionality at or above these limits is not implied.
13.2 DC Electrical Characteristics
VCC = 3.3 V +/- 10%
DD = 1.8 V +/- 5%
TAMBIENT = -40 C to +85 C
V
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Data Sheet
13.3 Recommended Operating Conditions
Symbol
fosc
Parameter Description
Min.
Typ.
Max.
Unit
Frequency of Operation (SCLK)
100
100
105
350
MHz
mA
mA
V
ICC
IDD
VOH
VOL
VIH
VIL
IIL
VCC Supply Current – @ 100 MHz (full line rate)
VDD Supply Current – @ 100 MHz (full line rate)
Output High Voltage (CMOS)
2.4
2.0
Output Low Voltage (CMOS)
0.4
VCC + 2.0
0.8
V
Input High Voltage (TTL 5 V tolerant)
Input Low Voltage (TTL 5 V tolerant)
V
V
Input Leakage Current (0.1 V < VIN < VCC
(all pins except those with internal
pull-up/pull-down resistors)
)
10
µA
IOL
CIN
COUT
CI/O
θja
Output Leakage Current (0.1 V < VOUT < VCC
Input Capacitance
)
10
5
µA
pF
Output Capacitance
5
pF
I/O Capacitance
7
pF
Thermal resistance with 0 air flow
Thermal resistance with 1 m/s air flow
Thermal resistance with 2 m/s air flow
24.3
20.0
18.1
4.6
C/W
C/W
C/W
C/W
θja
θja
θjc
Thermal resistance between junction and case
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Data Sheet
13.4 AC Characteristics and Timing
13.4.1 Typical Reset & Bootstrap Timing Diagram
RESIN#
RESETOUT#
Tri-Stated
R1
R3
Bootstrap Pins
Outputs
Inputs
Outputs
R2
Figure 13 - Typical Reset & Bootstrap Timing Diagram
Symbol
Parameter
Min.
Typ.
Note:
R1
Delay until RESETOUT# is tri-stated
Bootstrap stabilization
10 ns
RESETOUT# state is then determined by
the external pull-up/down resistor
R2
R3
1 µs
10 µs
Bootstrap pins sampled on rising edge of
RESIN#
RESETOUT# assertion
2 ms
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Data Sheet
13.4.2 Typical CPU Timing Diagram for a CPU Write Cycle
ADDR0
ADDR1
P_A[2:0]
TWH
TWH
TWS
TWS
P_CS#
TWA
TWR
TWA
Activ eTime
Recov ery Time
Activ eTime
P_WE#
TDH
TDH
TDS
TDS
P_DATA
(todev ice)
DATA0
DATA1
Set uptime
Holdtime
Figure 14 - Typical CPU Timing Diagram for a CPU Write Cycle
Description
(SCLK=100 Mhz) (SCLK=50 Mhz)
Refer to Figure 14
Write Cycle
Symbol
Min.
Max.
Min.
Max.
Write Set up Time
TWS
10
10
P_A and P_CS# to falling
edge of P_WE#
Write Active Time
Write Hold Time
TWA
TWH
20
2
40
2
At least 2 SCLK cycles
P_A and P_CS# to rising
edge of P_WE#
Write Recovery time
Data Set Up time
TWR
TDS
30
10
60
10
At least 3 SCLK cycles
P_DATA to falling edge of
P_WE#
Data Hold time
TDH
2
2
P_DATA to rising edge of
P_WE#
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Data Sheet
13.4.3 Typical CPU Timing Diagram for a CPU Read Cycle
ADDR0
ADDR1
P_A[2:0]
TRH
TRH
TRS
TRS
P_CS#
TRA
Activ eTime
TRR
TRA
Activ eTime
Recov ery Time
P_RD#
TDI
TDI
TDV
TDV
P_DATA
(toCPU)
DATA0
DATA1
Valid time
Inv alidtime
Figure 15 - Typical CPU Timing Diagram for a CPU Read Cycle
Description
Read Cycle
(SCLK=100 Mhz)
(SCLK=50 Mhz)
Refer to Figure 15
Symbol
Min.
Max.
Min.
Max.
Read Set up Time
TRS
10
10
P_A and P_CS# to falling
edge of P_RD#
Read Active Time
Read Hold Time
TRA
TRH
20
2
40
2
At least 2 SCLK cycles
P_A and P_CS# to rising
edge of P_RD#
Read Recovery time
Data Valid time
TRR
TDV
30
60
At least 3 SCLK cycles
12
10
12
10
P_DATA to falling edge of
P_RD#
Data Invalid time
TDI
P_DATA to rising edge of
P_RD#
Table 14 - AC Characteristics - CPU Read Cycle
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Data Sheet
13.4.4 Reduced Media Independent Interface
M_CLK
Mn_TXEN
M6-max
M6-min
M7-max
M7-min
Mn_TXD[1:0]
Figure 16 - AC Characteristics – Reduced media independent Interface (TX)
M_CLK
M2
Mn_RXD
M3
M4
Mn_CRS_DV
M5
Figure 17 - AC Characteristics – Reduced Media Independent Interface (RX)
M_CLK=50 MHz
Symbol
Parameter
Note:
Min. (ns)
Max. (ns)
M2
M3
M4
M5
M6
M7
M[7:0]_RXD[1:0] Input Setup Time
M[7:0]_RXD[1:0] Input Hold Time
M[7:0]_CRS_DV Input Setup Time
M[7:0]_CRS_DV Input Hold Time
M[7:0]_TXEN Output Delay Time
M[7:0]_TXD[1:0] Output Delay Time
4
2
4
3
2
2
11
11
CL = 20 pF
CL = 20 pF
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Data Sheet
13.4.5 Media Independent Interface
Mn_TXCLK
MM6-max
MM6-min
Mn_TXEN
MM7-max
MM7-min
Mn _TXD[3:0]
Figure 18 - AC Characteristics – Media independent Interface (TX)
Mn_RXCLK
MM2
Mn_RXD[3:0]
MM
MM4
Mn_CRS_DV
MM
Figure 19 - AC Characteristics – Media Independent Interface (RX)
25 MHz
Symbol
Parameter
Note:
Min. (ns)
Max. (ns)
MM2
MM2
MM3
MM4
MM4
MM5
MM6
MM7
M[9,7:0]_RXD[3:0] Input Setup Time
M[8]_RXD[3:0] Input Setup Time
Mn_RXD[3:0] Input Hold Time
M[9,7:0]_CRS_DV Input Setup Time
M[8]_CRS_DV Input Setup Time
Mn_CRS_DV Input Hold Time
Mn_TXEN Output Delay Time
Mn_TXD[3:0] Output Delay Time
4
10
2
CPU MII Interface
4
10
2
CPU MII Interface
2
14
14
CL = 20 pF
CL = 20 pF
2
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Data Sheet
13.4.6 General Purpose Serial Interface (7-wire)
Mn_ TXCLK
Mn_TXEN
SM6-max
SM6-min
SM7-max
SM7-min
Mn_TXD
Figure 20 - AC Characteristics – General Purpose Serial Interface (TX)
Mn_RXCLK
SM2
Mn_RXD
SM3
SM4
Mn_CRS_DV
SM5
Figure 21 - AC Characteristics – General Purpose Serial Interface (RX)
10 MHz
Symbol
Parameter
Note:
Min. (ns)
Max. (ns)
SM2
SM3
SM4
SM5
SM6
SM7
M[7:0]_RXD Input Setup Time
M[7:0]_RXD Input Hold Time
4
2
4
2
2
2
M[7:0]_CRS_DV Input Setup Time
M[7:0]_CRS_DV Input Hold Time
M[7:0]_TXEN Output Delay Time
M[7:0]_TXD Output Delay Time
14
14
CL = 20 pF
CL = 20 pF
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Data Sheet
13.4.7 Gigabit Media Independent Interface
M9_TXCLK
M9_TXD [7:0]
M9_TXEN
G12-max
G12-min
G13-max
G13-min
G14-max
G14-min
M9_TXER
Figure 22 - AC Characteristics- Gigabit Media Independent Interface (TX)
M9_RXCLK
G1
G3
G2
G4
G6
G8
M9_RXD[7:0]
M9_RXDV
G5
G7
M9_RXER
M9_RX_CRS
Figure 23 - AC Characteristics – Gigabit Media Independent Interface (RX)
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Data Sheet
125 Mhz
Symbol
Parameter
Note:
Min. (ns)
Max. (ns)
G1
G2
M9_RXD[7:0] Input Setup Times
M9_RXD[7:0] Input Hold Times
M9_RXDV Input Setup Times
M9_RXDV Input Hold Times
M9_RXER Input Setup Times
M9_RXER Input Hold Times
M9_CRS Input Setup Times
M9_CRS Input Hold Times
2
1
2
1
2
1
2
1
1
1
1
G3
G4
G5
G6
G7
G8
G12
G13
G14
M9_TXD[7:0] Output Delay Times
M9_TXEN Output Delay Times
M9_TXER Output Delay Times
6
6.5
6
CL = 20 pf
CL = 20 pf
CL = 20 pf
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Data Sheet
13.4.8 MDIO Input Setup and Hold Timing
MDC
D1
D2
MDIO
Figure 24 - MDIO Input Setup and Hold Timing
MDC
D3-max
D3-min
MDIO
Figure 25 - MDIO Output Delay Timing
MDC=500 KHz
Parameter
Symbol
Note:
Min. (ns) Max. (ns)
D1
MDIO input setup time
10
D2
D3
MDIO input hold time
2
1
MDIO output delay time
20
CL = 50 pf
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Data Sheet
13.4.9 I²C Input Setup Timing
SCL
SDA
S2
S1
Figure 26 - I²C Input Setup Timing
SCL
S3-max
S3-min
SDA
Figure 27 - I²C Output Delay Timing
SCL=50 KHz
Symbol
Parameter
Note:
Min. (ns) Max. (ns)
S1
S2
SDA input setup time
SDA input hold time
SDA output delay time
20
1
S3*
4 usec
6 usec
CL = 30 pf
* Open Drain Output. Low to High transistor is controlled by external pullup resistor.
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Data Sheet
13.4.10 Serial Interface Setup Timing
STROBE
Datain
D4
D5
D2
D2
D1
D1
Figure 28 - Serial Interface Setup Timing
STROBE
D3-max
D3-min
Dataout
Figure 29 - Serial Interface Output Delay Timing
Symbol
Parameter
DATAIN setup time
Min. (ns) Max. (ns)
Note:
D1
D2
20
DATAIN hold time
3 µs
20 ns
Debounce on
Debounce off
CL = 100 pf
D3
D4
DATAOUT output delay time
STROBE low time
1
50
5 µs
50 ns
5 µs
50 ns
Debounce on
Debounce off
Debounce on
Debounce off
D5
STROBE high time
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Data Sheet
13.4.11 JTAG (IEEE 1149.1-2001)
TCK
TMS, TDI
J1
J2
J3-max
TDO
J3-min
Figure 30 - JTAG Timing Diagram
Symbol
Parameter
Min.
Typ.
Max.
Units
Note:
TCK frequency of operation
TCK cycle time
0
10
50
MHz
ns
20
10
20
TCK clock pulse width
TRST# assert time
ns
-
ns
TRST is an
asynchronous signal
J1
J2
J3
TMS, TDI data setup time
TMS, TDI data hold time
TCK to TDO data valid
3
7
0
ns
ns
ns
15
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Data Sheet
14.0 Document History
14.1 July 2003
•
Initial Release
14.2 November 2003
•
•
Clarified IP Multicast support is up to 4 K groups, as it wasn’t mentioned in the data sheets
Updated Ball Signal Description Table:
•
clarified the ball signal I/O description for Mn_TXCLK & Mn_RXCLK showing these signals are either
inputs OR outputs
•
clarified that M9_MTXCLK is an input only
•
Updated Section 1.4 on page 17 to indicate operation of the internal pull-up/down resistors in different
modes
•
•
•
Clarified Section 10.1.3 on page 50 on usage of GREF_CLK
Clarified PVMODE register bit description for bits [2] & [5]
Updated ECR4Pn register description as port 9 (uplink) operates differently than the RMAC ports for MII
bi-directional clocking (bits [1:0])
I2C address mapping was corrected for QOSCn registers
•
•
•
Added Maximum Junction Temperature to Section 13.1 on page 122
Updated I/O voltage levels to use TTL spec values rather than % of Vcc
14.3 February 2004
•
Added the following to the Feature List:
•
•
•
4 K jumbo frames
IEEE 802.3ad support
Reverse MII/GPSI
•
•
Added section on PHY addresses
Clarified that they are hard-coded
Fixed error in DS on sending Ethernet Frames via 8/16-bit or serial interface.
The Status Bytes is sent before the frame, for both Tx and Rx
•
•
•
•
Added more cross-references to available AppNotes
Added section on Stacked VLAN (Q-in-Q) and IP Multicast Switching since they weren’t really discussed in
the DS
•
•
Added more clock descriptions to “Clocks” on page 50
INT_MASK and INTP_MASK registers should state that the default register value is 0x00
14.4 August 2004
•
•
•
Added Errata List to document
Added section on SCL clock generation
Interrupt Register was incorrectly identified as read only, should be read/write
•
Clarified that only bit [7] is not self-clearing
•
Updated CPU timing diagrams to clarify timing
14.5 November 2004
•
•
•
Added section “Default Switch Configuration and Initialization Sequence” on page 21
Added Private VLAN Edge (protected ports), force VLAN tag out, and unknown IP Multicast filtering support
Updated CPU timing diagrams to clarify P_A timing
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Zarlink Semiconductor Inc.
BOTTOM VIEW
TOP VIEW
MIN
0.30
MAX
1.40
0.50
Dimension
A
A1
A2
D
E
b
0.53 REF
16.90
16.90
0.40
17.10
17.10
0.60
1.00
208
e
N
Conforms to JEDEC MO-192
b
SIDE VIEW
Package Code
c
Zarlink Semiconductor 2002 All rights reserved.
Previous package codes
1
ISSUE
ACN
213730
14Nov02
DATE
APPRD.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
ZL50410GDG2
LAN Switching Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
ZARLINK
ZL50415/GKC
DATACOM, LAN SWITCHING CIRCUIT, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553
MICROSEMI
ZL50415GKG
LAN Switching Circuit, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553
MICROSEMI
ZL50415GKG2
DATACOM, LAN SWITCHING CIRCUIT, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553
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ZL50416/GKC
DATACOM, LAN SWITCHING CIRCUIT, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553
MICROSEMI
ZL50416GKG
LAN Switching Circuit, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553
MICROSEMI
ZL50416GKG2
DATACOM, LAN SWITCHING CIRCUIT, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553
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ZL50417/GKC
DATACOM, LAN SWITCHING CIRCUIT, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553
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