ZNBG3011Q16 [ZETEX]
FET BIAS CONTROLLER AND POLARITY SWITCH; FET偏置控制器和极性开关
| 型号： | ZNBG3011Q16 |
| 厂家： | 
ZETEX SEMICONDUCTORS |
| 描述： | FET BIAS CONTROLLER AND POLARITY SWITCH |
| 文件： | 总10页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FET BIAS CONTROLLER AND
POLARITY SWITCH
ISSUE 1 - FEBRUARY 1998
ZNBG3010
ZNBG3011
DEVICE DESCRIPTION
These devices are unconditionally stable
over the full working temperature with the
FETs in place, subject to the inclusion of the
recommended gate and drain capacitors.
These ensure RF stability and minimal
injected noise.
The ZNBG series of devices are designed to
meet the bias requirements of GaAs and
HEMT FETs commonly used in satellite
receiver LNBs, PMR cellular telephones etc.
with a minimum of external components.
It is possible to use less than the devices full
complement of FET bias controls, unused
drain and gate connections can be left open
circuit without affecting operation of the
remaining bias circuits.
With the addition of two capacitors and a
resistor, the devices provide drain voltage
and current control for three external
grounded source FETs, generating the
regulated negative rail required for FET gate
biasingwhilstoperatingfromasinglesupply.
This negative bias, at -3 volts, can also be
used to supply other external circuits.
In order to protect the external FETs the
circuits have been designed to ensure that,
under any conditions including power
up/down transients, the gate drive from the
bias circuits cannot exceed the range -3.5V
to 1V. Furthermore if the negative rail
experiences a fault condition, such as
overload or short circuit, the drain supply to
the FETs will shut down avoiding excessive
current flow.
The ZNBG3010/11 includes bias circuits to
drive up to three external FETs. A control
input to the device selects either one of two
FETs as operational, the third FET is
permanently active. This feature is
particularly used as an LNB polarisation
switch.
The ZNBG3010/11 are available in QSOP16
for the minimum in device size. Device
operating temperature is -40 to 70°C to suit
a wide range of environmental conditions.
Drain current setting of the ZNBG3010/11 is
user selectable over the range 0 to 15mA,
this is achieved with addition of a single
resistor. The series also offers the choice of
drain voltage to be set for the FETs, the
ZNBG3010 gives 2.2 volts drain whilst the
ZNBG3011 gives 2 volts.
FEATURES
APPLICATIONS
Provides bias for GaAs and HEMT FETs
Satellite receiver LNBs
•
•
Drives up to three FETs
Private mobile radio (PMR)
•
•
Dynamic FET protection
Cellular telephones
•
•
Drain current set by external resistor
•
Regulated negative rail generator
requires only 2 external capacitors
•
Choice in drain voltage
•
Wide supply voltage range
•
Polarisation switch for LNBs
•
•
QSOP surface mount package
4-114
ZNBG3010
ZNBG3011
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Supply Current
Input Voltage (VPOL
-0.6V to 12V
100mA
25V Continuous
0 to 15mA
Power Dissipation (Tamb= 25°C)
QSOP16 500mW
)
Drain Current (per FET)
(set by RCAL
)
Operating Temperature
Storage Temperature
-40 to 70°C
-50 to 85°C
ELECTRICAL CHARACTERISTICS TEST CONDITIONS
(Unless otherwise stated):T
= 25°C,V =5V,I =10mA (R
=33kΩ)
amb
CC
D
CAL
LIMITS
SYMBOL PARAMETER
CONDITIONS
UNITS
V
MIN.
5
TYP.
MAX.
10
VCC
ICC
Supply Voltage
Supply Current
ID1 to ID3=0
ID2 and ID3=10mA, VPOL=14V
ID1 and ID3=10mA, VPOL=15.5V
10
30
30
mA
mA
mA
VSUB
Substrate Voltage
(Internally generated)
ISUB=0
ISUB=-200µA
-3.5
-3.0
350
-2
-2
V
V
Output Noise
Drain Voltage
Gate Voltage
END
ENG
CG=4.7nF, CD=10nF
CG=4.7nF, CD=10nF
0.02
0.005 Vpkpk
Vpkpk
fO
Oscillator Frequency
200
-30
800
kHz
GATE CHARACTERISTICS
IGO
Output Current Range
2000
µA
IDx
(mA)
VPOL
(V)
IGOx
(µA)
Output Voltage
VG1O
VG1L
VG1H
Gate 1
Off
Low
High
ID1=0 VPOL=14 IGO1=-10 -3.5
ID1=12 VPOL=15.5 IGO1=-10 -3.5
-2.9
-2.9
0.75
-2.0
-2.0
1.0
V
V
V
ID1=8 VPOL=15.5 IGO1=0
0.4
Output Voltage
VG2O
VG2L
VG2H
Gate 2
Off
Low
High
ID2=0 VPOL=15.5 IGO2=-10 -3.5
D2=12 VPOL=14 IGO2=-10 -3.5
ID2=8 VPOL=14 IGO2=0
0.4
-2.9
-2.9
0.75
-2.0
-2.0
1.0
V
V
V
I
Output Voltage
VG3L
VG3H
Gate 3
Low
High
I
D3=12
IGO3=-10 -3.5
IGO3=0 0.4
-2.9
0.75
-2.0
1.0
V
V
ID3=8
4-115
ZNBG3010
ZNBG3011
LIMITS
SYMBOL PARAMETER
CONDITIONS
UNITS
MIN.
8
TYP.
MAX.
12
DRAIN CHARACTERISTICS
ID
Current
10
mA
Current Change
with VCC
⌬IDV
⌬IDT
VCC= 5 to 10V
Tj=-40 to +70°C
0.2
0.05
%/V
%/°C
with Tj
VD1
VD2
VD3
Drain 1 Voltage:High
ZNBG3010
ZNBG3011
ID1=10mA, VPOL=15.5V
2.0
1.8
2.2
2.0
2.4
2.2
V
V
I
D1=10mA, VPOL=15.5V
Drain 2 Voltage:High
ZNBG3010
ZNBG3011
I
D2=10mA, VPOL=14V
2.0
1.8
2.2
2.0
2.4
2.2
V
V
ID2=10mA, VPOL=14V
ID3=10mA, VPOL=15.5V
Drain 3 Voltage:High
ZNBG3010
ZNBG3011
2.0
1.8
2.2
2.0
2.4
2.2
V
V
ID3=10mA, VPOL=15.5V
Voltage Change
with VCC
with Tj
⌬VDV
⌬VDT
VCC= 5 to 10V
Tj=-40 to +70°C
0.5
50
%/V
ppm
Leakage Current
Drain 1
IL1
IL2
VD1=0.1V, VPOL=14V
VD2=0.1V, VPOL=15.5V
10
10
µA
µA
Drain 2
POLARITY SWITCH CHARACTERISTICS
IPOL
Input Current
VPOL=25V
10
14
20
40
(Applied via RPOL=10kΩ
µA
V
VTPOL
TSPOL
Threshold Voltage
Switching Speed
14.75 15.5
100
(Applied via RPOL=10kΩ
µs
Notes:
1. The negative biasvoltagesspecifiedaregeneratedon-chipusinganinternal oscillator. Twoexternal
capacitors, CNB and CSUB, of 47nF are required for this purpose.
2. The characteristics are measured using an external reference resistor RCAL of value 33k wired from
pins RCAL to ground.
3. Noise voltage is not measured in production.
4. Noise voltage measurement is made with FETs and gate and drain capacitors in place on all
outputs. CG, 4.7nF, are connected between gate outputs and ground, CD, 10nF, are connected
between drain outputs and ground.
4-116
ZNBG3010
ZNBG3011
TYPICAL CHARACTERISTICS
16
14
12
10
8
Note:- Operation with loads > 200µA
is not guaranteed.
Vcc = 5V
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
Vcc = 5V
6V
8V
10V
6
4
2
0
0
20
40
Rcal (k)
60
80
100
0
0.2
0.4
0.6
0.8
1.0
External Vsub Load (mA)
JFET Drain Current v Rcal
Vsub v External Load
2.4
2.3
2.2
2.1
2.0
Vcc = 5V
6V
8V
10V
2
4
6
8
10
12
14
16
Drain Current (mA)
JFET Drain Voltage v Drain Current
4-117
ZNBG3010
ZNBG3011
FUNCTIONAL DIAGRAM
FUNCTIONAL DESCRIPTION
The ZNBG devices provide all the bias requirements for external FETs, including the generation
of the negative supply required for gate biasing, from the single supply voltage.The diagram
above shows a single stage from the ZNBG series. The ZNBG3010/11 contains 3 such stages. The
negative rail generator is common to both devices.
The drain voltage of the external FET QN is set by the ZNBG device to its normal operating voltage.
This is determined by the on board VD Set reference, for the ZNBG3010 this is nominally 2.2 volts
whilst the ZNBG3011 provides nominally 2 volts.
The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier
driving the gate of the FET adjusts the gate voltage of QN so that the drain current taken matches
the current called for by an external resistor RCAL
.
Since the FET is a depletion mode transistor, it is often necessary to drive its gate negative with
respect to ground to obtain the required drain current. To provide this capability powered from
a single positive supply, the device includes a low current negative supply generator. This
generator uses an internal oscillator and two external capacitors, CNB and CSUB
.
4-118
ZNBG3010
ZNBG3011
APPLICATIONS CIRCUIT
APPLICATIONS INFORMATION
The above is a partial application circuit for the ZNBG series showing all external components
required for appropriate biasing. The bias circuits are unconditionally stable over the full
temperature range with the associated FETs and gate and drain capacitors in circuit.
Capacitors CD and CG ensure that residual power supply and substrate generator noise is not
allowed to affect other external circuits which may be sensitive to RF interference. They also
serve to suppress any potential RF feedthrough between stages via the ZNBG device. These
capacitors are required for all stages used. Values of 10nF and 4.7nF respectively are
recommended however this is design dependent and any value between 1nF and 100nF could
be used.
The capacitors CNB and CSUB are an integral part of the ZNBGs negative supply generator. The
negative bias voltage is generated on-chip using an internal oscillator. The required value of
capacitors CNB and CSUB is 47nF. This generator produces a low current supply of approximately
-3 volts. Although this generator is intended purely to bias the external FETs, it can be used to
power other external circuits via the CSUB pin.
Resistor RCAL sets the drain current at which all external FETs are operated. If any bias control
circuit is not required, its related drain and gate connections may be left open circuit without
affecting the operation of the remaining bias circuits.
The ZNBG devices have been designed to protect the external FETs from adverse operating
conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit
can not exceed the range -3.5V to 1V, under any conditions including powerup and powerdown
transients. Should the negative bias generator be shorted or overloaded so that the drain current
of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid
damage to the FETs by excessive drain current.
4-120
ZNBG3010
ZNBG3011
The following schematic shows the function of the VPOL input. Only one of the two external FETs
numberd Q1 and Q2 are powered at any one time, their selection is controlled by the input VPOL
.
This input is designed to be wired to the power input of the LNB via a high value (10k) resistor.
With the input voltage of the LNB set at or below 14V, FET Q2 will be enabled. With the input
voltage at or above 15.5V, FET Q1 will be enabled. The disabled FET has its gate driven low and
its drain terminal is switched open circuit. It is permissible to connect the drain pins D1 and D2
together if required by the application circuit. FET number Q3 is always active regardless of the
voltage applied to VPOL
.
Control Input Switch Function
Input Sense Polarisation Select
Vertical
FET Q2
FET Q1
≤14 volts
Horizontal
≥ 15.5 volts
4-119
ZNBG3010
ZNBG3011
APPLICATIONS INFORMATION (Continued)
The following block diagram shows the main section of an LNB designed for use with the Astra
series of satellites. The ZNBG3010/11 is the core bias and control element of this circuit. The
ZNBG provides the negative rail, FET bias control and polarisation switch control, with the
minimum of external components. Compared to other discrete component solutions the ZNBG
circuit reduces component count and overall size required.
Single Standard/ Enhanced LNB block diagram.
4-121
ZNBG3010
ZNBG3011
CONNECTION DIAGRAM
ORDERING INFORMATION
Part Number
ZNBG3010Q16
ZNBG3011Q16
Package
QSOP16
QSOP16
Part Mark
ZNBG3010
ZNBG3011
4-122
ZNBG3010
ZNBG3011
PACKAGE DIMENSIONS
A
IDENTIFICATION
RECESS
C
B
FOR PIN 1
D
PIN No.1
K
PIN
Millimetres
Inches
MIN
4.80
MAX MIN
MAX
A
B
C
D
E
F
4.90
0.189 0.196
0.025 NOM
0.635
0.177 0.267 0.007 0.011
0.20
3.81
1.35
0.10
5.79
0°
0.30
3.99
1.75
0.25
6.20
8°
0.008 0.012
0.15 0.157
0.053 0.069
0.004 0.01
0.228 0.244
G
J
K
0°
8°
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