S3F94C8EZZ/F94C4EZZ_技术文档

S3 Family 8-Bit Microcontrollers

S3F94C8/S3F94C4

Product Specification

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S3F94C8/S3F94C4

Product Specification

ii

DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.

Warning:

LIFE SUPPORT POLICY

ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE

SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF

THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used herein

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)

support or sustain life and whose failure to perform when properly used in accordance with instructions for

use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-

cal component is any component in a life support device or system whose failure to perform can be reason-

ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

Document Disclaimer

or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES

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INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO

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S3F94C8/S3F94C4

Product Specification

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Revision History

Each instance in this document’s revision history reflects a change from its previous edi-

tion. For more details, refer to the corresponding page(s) or appropriate links furnished in

the table below.

Revision

Date Level

Description

Page

Aug

2013

01

Original Zilog issue. A table of contents and PDF bookmarks will appear in the All

next edition, due to be published on or before Winter 2013.

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S3F94C8/S3F94C4

Product Specification

1

PRODUCT OVERVIEW

SAM88RCRI MICROCONTROLLERS

Samsung's SAM88RCRI series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide

range of integrated peripherals, and various programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode released by interrupt

— Built-in basic timer with watchdog function

A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming

environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating

modes are included to support real-time operations.

S3F94C8/F94C4 MICROCONTROLLER

The S3F94C8/F94C4 single-chip 8-bit microcontroller is designed for useful A/D converter application field. The

S3F94C8/F94C4 single-chip CMOS micro-controller is fabricated using a highly advanced CMOS process and is

based on Samsung's powerful SAM88RCRI CPU architecture. Stop and idle (power-down) modes were

implemented to reduce power consumption.

The S3F94C8 is a micro-controller with a 8-Kbyte multi-time-programmable Full Flash ROM embedded.

The S3F94C4 is a micro-controller with a 4-Kbyte multi-time-programmable Full Flash ROM embedded.

The S3C94C8/F94C4 is a versatile general-purpose microcontrollers that is ideal for use in a wide range of

electronics applications requiring simple timer/counter, PWM. In addition, the S3F94C8/F94C4 advanced CMOS

technology provides for low power consumption and wide operating voltage range.

Using the SAM88RCRI design approach, the following peripherals were integrated with the powerful core:

— Three configurable I/O ports (18 pins)

— Four interrupt sources with One vectors and one interrupt level

— 0ne 8-bit timer/counter with time interval modes.

— Analog to digital converter with nine input channels (MAX) and 10-bit resolution

— One PWM output with three optional mode: 8-bit (6+2); 12-bit(6+6); 14-bit(8+6);

The S3F94C8/F94C4 microcontroller is ideal for use in a wide range of electronic applications requiring simple

timer/counter, PWM, ADC. They are currently available in 20 DIP Package, 20/16-pin SOP Package, 20 SSOP

Package and 16 TSSOP Package.

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Product Specification

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FEATURES

CPU

A/D Converter

ꢀ

SAM88RCRI CPU core

ꢀ

Nine analog input pins (MAX)

10-bit conversion resolution

Memory

ꢀ

Internal multi-time program Full-Flash memory:

Oscillation Frequency

– 8Kꢁ8 bits program memory(S3F94C8)

– 4Kꢁ8 bits program memory(S3F94C4)

Ĝ Sector size: 128 Bytes

ꢀ

0.4 MHz to 10 MHz external crystal oscillator

Typical 4MHz external RC oscillator

Ĝ User programmable by ‘LDC’ instruction

Ĝ Sector erase available

Ĝ Fast programming time

Ĝ External serial programming support

Ĝ Endurance: 10,000 erase/program cycles

Ĝ 10 Years data retention

Internal RC: 3.2 MHz (typ.), 0.5 MHz (typ.) in

VDD = 5 V

Built-in RESET Circuit (LVR)

ꢀ

Low-Voltage check to make system reset

= 1.9/2.3/3.0/3.6/3.9 V (by smart option)

V

LVR

ꢀ

208-byte general-purpose register area

Smart Option

Instruction Set

ꢀ

LVR enable/disable

Oscillator selection

ꢀ

41 instructions

Idle and Stop instructions added for power-down

modes

Operating Temperature Range

Instruction Execution Time

400 ns at 10 MHz f (minimum)

ꢂ

ꢀ

– 40 C to + 85 C

ꢀ

OSC

Operating Voltage Range

Interrupts

ꢀ

1.8 V to 5.5 V @ 0.4 - 4M Hz(LVR disable)

LVR to 5.5V @ 0.4 - 4M Hz(LVR enable)

2.7 V to 5.5V @ 0.4 -10M Hz

ꢀ

1 interrupt levels and 4 interrupt sources

(2 external interrupts and 2 internal interrupts)

General I/O

ꢀ

Three I/O ports (Max 18 pins)

Bit programmable ports

Package Types

S3F94C8/F94C4:

ꢀ

1-ch High-speed PWM with Three Selectable

Resolutions

–

20-DIP-300A

20-SOP-375

20-SSOP-225

16-SOP-225

16-TSSOP-0044

ꢀ

8-bit PWM: 6-bit base + 2-bit extension

12-bit PWM: 6-bit base + 6-bit extension

14-bit PWM: 8-bit base + 6-bit extension

Timer/Counters

ꢀ

One 8-bit basic timer for watchdog function

One 8-bit timer/counter with time interval modes

Device

Operating Temp. Range

Internal RC Temp. Range

Internal RC Tolerance

S3F94C8EZZ / F94C4EZZ

S3F94C8XZZ / F94C4XZZ

ꢂ

– 25ꢂC to + 85ꢂC

3%@5V,25ꢂC

– 40 C to + 85 C

ꢂ

1%@5V,25ꢂC

– 40 C to + 85 C

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Product Specification

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BLOCK DIAGRAM

P0.0/ADC0/INT0

X

IN

P0.1/ADC1/INT1

P0.2/ADC2

OSC

X

OUT

Port 0

P0.3/ADC3

Port I/O and

Interrupt Control

Basic

Timer

P0.7/ADC7

Timer 0

P1.0

P1.1

P1.2

Port 1

SAM88RCRI CPU

ADC

ADC0-ADC8

P0.6/PWM

P2.0/T0

P2.1

Port 2

208 Byte

Register File

4/8 KB ROM

P2.6/ADC8/CLO

PWM

IVC

LVR

NOTE:

1. P1.2 is used as input only.

2. IVC (Internal Voltage Converter) is not configurable.

Figure 1-1. Block Diagram

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PIN ASSIGNMENTS

V

SS

1

20

19

18

17

16

15

14

13

12

11

VDD

X

IN/P1.0

2

P0.0/ADC0/INT0 (SCLK)

P0.1/ADC1/INT1 (SDAT)

P0.2/ADC2

X

OUT/P1.1

3

(VPP) nRESET/P1.2

4

S3F94C8/F94C4

T0/P2.0

P2.1

5

P0.3/ADC3

6

P0.4/ADC4

(20-DIP-300A/

20-SOP-375 /

20-SSOP-225)

P2.2

7

P0.5/ADC5

P2.3

8

P0.6/ADC6/PWM

P0.7/ADC7

P2.4

9

P2.5

10

P2.6/ADC8/CLO

Figure 1-2. Pin Assignment Diagram (20-Pin DIP/SOP/SSOP Package)

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Product Specification

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V

SS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDD

X

IN/P1.0

P0.0/ADC0/INT0 (SCLK)

P0.1/ADC1/INT1 (SDAT)

P0.2/ADC2

X

OUT/P1.1

S3F94C8/F94C4

(VPP) nRESET/P1.2

(16-SOP-225 /

16-TSSOP-0044)

T0/P2.0

P2.1

P0.3/ADC3

P0.4/ADC4

P2.2

P0.5/ADC5

P2.3

P0.6/ADC6/PWM

Figure 1-3. Pin Assignment Diagram (16-Pin SOP/TSSOP Package)

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Product Specification

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PIN DESCRIPTIONS

Table 1-2. S3F94C8/F94C4 Pin Descriptions

Pin Description

Name

Input/

Output

Type

Share

Pins

P0.0–P0.7

I/O

Bit-programmable I/O port for Schmitt trigger input or

push-pull output. Pull-up resistors are assignable by

software. Port0 pins can also be used as A/D converter

input, PWM output or external interrupt input.

E-1

ADC0–ADC7

INT0/INT1/

PWM

X

P1.0–P1.1

I/O

Bit-programmable I/O port for Schmitt trigger input or

push-pull, open-drain output. Pull-up resistors or pull-down

resistors are assignable by software.

E-2

IN, OUT

P1.2

I

Schmitt trigger input port

B¹

E

RESET

–

ADC8/CLO

T0

P2.0–P2.6

I/O

Bit-programmable I/O port for Schmitt trigger input or

push-pull, open-drain output. Pull-up resistors are

assignable by software.

X

–

Crystal/Ceramic, or RC oscillator signal for system clock.

P1.0–P1.1

IN, OUT

nRESET

I

Internal LVR or external RESET

Voltage input pin and ground

B

P1.2

V

–

DD, SS

CLO

O

I

System clock output port

External interrupt input port

14-Bit high speed PWM output

Timer0 match output

E

P2.6

P0.0, P0.1

P0.6

INT0–INT1

PWM

E-1

O

I

T0

P2.0

ADC0–ADC8

A/D converter input

E-1

E

P0.0–P0.7

P2.6

Table 1-3. Descriptions of Pins Used to Read/Write the Flash ROM

During Programming

Main Chip

Pin Name

P0.1

Pin Name

Pin No.

I/O

Function

SDAT

18 (20-pin)

14 (16-pin)

I/O

Serial data pin (output when reading, Input

when writing) Input and push-pull output port

can be assigned

P0.0

SCLK

19 (20-pin)

15 (16-pin)

I

Serial clock pin (input only pin)

V

RESET/P1.2

4

Power supply pin for Tool mode entering

(indicates that MTP enters into the Tool

mode). When 11 V is applied, MTP is in

Tool mode.

PP

V

/V

V

/V

20 (20-pin), 16 (16-pin)

1 (20-pin), 1 (16-pin)

I

Logic power supply pin.

DD SS

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PIN CIRCUITS

VDD

P-channel

N-channel

IN

Figure 1-5. Pin Circuit Type B (P1.2)

Figure 1-4. Pin Circuit Type A

VDD

Pull-up

Enable

Data

Out

Circuit

Type C

I/O

Output

Disable

Output

DIsable

Digital

Input

Figure 1-6. Pin Circuit Type C

Figure 1-7. Pin Circuit Type D

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Product Specification

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VDD

Open-drain

Enable

Pull-up

enable

P2CONH

P2CONL

VDD

P-CH

N-CH

Alternative

Output

M

U

X

Data

I/O

P2.x

Output Disable

(Input Mode)

Digital

Input

Analog Input

Enable

ADC

Figure 1-8. Pin Circuit Type E (Port2)

VDD

Pull-up

enable

VDD

P0CONH

P-CH

N-CH

Alternative

Output

M

U

X

Data

I/O

P0.x

Output Disable

(Input Mode)

Digital Input

Interrupt Input

Analog Input

Enable

ADC

Figure 1-9. Pin Circuit Type E-1 (Port0)

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Product Specification

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VDD

Open-drain

Enable

Pull-up

enable

VDD

P1.x

I/O

Output Disable

(Input Mode)

Pull-down

enable

Digital

Input

X

IN

OUT

X

Figure 1-10. Pin Circuit Type E-2 (P1.0-P1.1)

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NOTES

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Product Specification

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2

ADDRESS SPACES

OVERVIEW

The S3F94C8/F94C4 microcontroller has two kinds of address space:

— Internal full flash program memory (ROM)

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and

data between the CPU and the internal register file.

The S3F94C8/F94C4 have 8-Kbytes and 4-Kbytes of multi-time-programmable full flash program memory: which

is configured as the Internal ROM mode, all of the 4K/8K internal program memory is used.

The S3F94C8/F94C4 microcontroller has 208 general-purpose registers in its internal register file. 32 bytes in the

register file are mapped for system and peripheral control functions.

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PROGRAM MEMORY (ROM)

Normal Operating Mode

The S3F94C8/F94C4 has 8-Kbytes and 4-Kbytes of internal multi-time-programmable full flash program memory.

The program memory address range is therefore 0H–1FFFH and 0H-0FFFH.

The first 2-bytes of the ROM (0000H–0001H) are interrupt vector address.

Unused locations (0002H–00FFH except 3CH, 3DH, 3EH, and 3FH) can be used as normal program memory.

3CH, 3DH, 3EH, 3FH is used as smart option ROM cell.

The program Reset address in the ROM is 0100H.

(HEX)

1FFFH

(Decimal)

8.191

(S3F94C8)

8-Kbyte

Program

Memory

(Flash)

0FFFH

4.095

(S3F94C4)

4-Kbyte

Program

Memory

(Flash)

256

0100H

Program Start

64

60

2

0040H

003CH

0002H

0001H

0000H

Smart option ROM cell

Interrupt Vector

1

0

Figure 2-1. Program Memory Address Space

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Smart Option

Smart option is the ROM option for starting condition of the chip.

The ROM addresses used by smart option are from 003CH to 003FH. The S3F94C8/F94C4 only use 003EH,

003FH. Not used ROM address 003CH, 003DH should be initialized to be initialized to 00H. The default values of

ROM 003EH, 003FH are FFH (LVR enable, internal RC oscillator).

ROM Address: 003CH

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Must be initialized to 00H.

ROM Address: 003DH

.5

.4

.3

.2

Must be initialized to 00H.

ROM Address: 003EH

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

LVR enable/disable bit:

0 = Disable

LVR level selection bits:

10100 = 1.9 V

Not used

1 = Enable

11001 = 2.3 V

10010 = 3.0 V

00111 = 3.6 V

01100 = 3.9 V

ROM Address: 003FH

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used.

Oscillator selection bits:

00 = External crystal/

ceramic oscillator

01 = External RC

10 = Internal RC (0.5 MHz in VDD = 5 V)

11 = Internal RC (3.2 MHz in VDD = 5 V)

NOTES:

1. When you use external oscillator, P1.0, P1.1 must be set to output

port to prevent current consumption.

2. The value of unused bits of 3EH, 3FH is don't care.

3. When LVR is enabled: P1.2/nRESET is used as input port; and LVR level

must be set to appropriate value, not default value;

Figure 2-2. Smart Option

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ꢀ

PROGRAMMING TIP — Smart Option Setting

;

<< Interrupt Vector Address >>

ORG

Vector

0000H

00H, INT_94C8

; S3F94C8/F94C4 has only one interrupt vector

;

<< Smart Option Setting >>

ORG

DB

003CH

00H

; 003CH, must be initialized to 0.

; 003DH, must be initialized to 0.

; 003EH, enable LVR (2.3 V)

DB

00H

DB

0E4H

03H

; 003FH, Internal RC (3.2 MHz in V = 5 V)

DD

<< Reset >>

ORG

RESET:

0100H

DI

•

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REGISTER ARCHITECTURE

The upper 64-bytes of the S3F94C8/F94C4’s internal register file are addressed as working registers, system

control registers and peripheral control registers. The lower 192-bytes of internal register file (00H–BFH) is called

the general purpose register space.

240 registers in this space can be accessed; 208 are available for general-purpose use.

In case of S3F94C8/F94C4 the total number of addressable 8-bit registers is 240. Of these 240 registers, 32 bytes

are for CPU and system control registers and peripheral control and data registers, 16 bytes are used as shared

working registers, and 192 registers are for general-purpose use.

For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by

additional register pages at the general purpose register space (00H–BFH: page0). This register file expansion is

not implemented in the S3F94C8/F94C4, however.

The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in

Table 2-1.

Table 2-1. Register Type Summary

Register Type

Number of Bytes

CPU and system control registers

11

21

Peripheral, I/O, and clock control and data registers

General-purpose registers (including the 16-bit

common working register area)

208

Total Addressable Bytes

240

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FFH

Peripheral Control

Registers

E0H

DFH

64 Bytes of

Common Area

System Control

Registers

D0H

CFH

Working Registers

C0H

BFH

General Purpose

Register File

and Stack Area

192 Bytes

~

00H

Figure 2-3. Internal Register File Organization

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COMMON WORKING REGISTER AREA (C0H–CFH)

The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full

advantage of shorter instruction formats to reduce execution time.

This16-byte address range is called common area. That is, locations in this area can be used as working registers

by operations that address any location on any page in the register file. Typically, these working registers serve as

temporary buffers for data operations between different pages. However, because the S3F94C8/F94C4 uses only

page 0, you can use the common area for any internal data operation.

The working register addressing mode and indirect register addressing mode can be used to access this area.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the

address of the first 8-bit register is always an even number and the address of the next register is an odd number.

The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant

byte is always stored in the next (+ 1) odd-numbered register.

MSB

Rn

LSB

n = Even address

Rn+1

Figure 2-4. 16-Bit Register Pairs

ꢀ

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH,

using working register addressing mode and indirect register addressing.

Examples: 1. LD

0C2H, 40H

; Invalid addressing mode!

Use working register addressing instead:

LD

R2, 40H

; R2 (C2H) ꢃ the value in location 40H

2. ADD

0C3H, #45H

; Invalid addressing mode!

Use working register addressing instead:

ADD

R3, #45H

; R3 (C3H) ꢃ R3 + 45H

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SYSTEM STACK

S3F9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH

and POP instructions are used to control system stack operations. The S3F94C8/F94C4 architecture supports

stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are

saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents

of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to

their original locations. The stack address is always decremented before a push operation and incremented after a

pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in

Figure 2-5.

High Address

PCL

PCH

Top of

PCH

Top of

stack

Flags

Stack contents

after a call

instruction

Stack contents

after an

Low Address

interrupt

Figure 2-5. Stack Operations

Stack Pointer (SP)

Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset,

the SP value is undetermined.

Because only internal memory 192 bytes space is implemented in the S3F94C8/F94C4, the SP must be initialized

to an 8-bit value in the range 00H–0C0H.

NOTE

In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This

means that a Stack Pointer access invalid stack area. We recommend that a stack pointer is initialized to

C0H to set upper address of stack to BFH.

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ꢀ

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

LD

SP,#0C0H

; SP ꢃꢄ C0H (Normally, the SP is set to C0H by the

; initialization routine)

•

PUSH

•

SYM

R15

20H

R3

; Stack address 0BFH ꢃꢄ SYM

; Stack address 0BEH ꢃꢄ R15

; Stack address 0BDH ꢃꢄ 20H

; Stack address 0BCH ꢃꢄ R3

•

POP

R3

; R3 ꢃꢄ Stack address 0BCH

; 20H ꢃꢄ Stack address 0BDH

; R15 ꢃꢄ Stack address 0BEH

; SYM ꢃꢄ Stack address 0BFH

20H

R15

SYM

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NOTES

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3

ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions

indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to

determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition

codes, immediate data, or a location in the register file, program memory, or data memory.

The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are

available for each instruction. The addressing modes and their symbols are as follows:

— Register (R)

— Indirect Register (IR)

— Indexed (X)

— Direct Address (DA)

— Relative Address (RA)

— Immediate (IM)

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REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register

addressing differs from Register addressing because it uses an 16-byte working register space in the register file

and an 4-bit register within that space (see Figure 3-2).

Program Memory

Register File

OPERAND

8-Bit Register

File Address

dst

OPCODE

Point to one

register in register

file

One-Operand

Instruction

Value used in

Instruction Execution

(Example)

Sample Instruction:

DEC

CNTR

;

Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

Register File

CFH

.

Program Memory

4-Bit

Working Register

4 LSBs

OPERAND

dst

src

Point to the

working register

(1 of 16)

OPCODE

C0H

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD

R1, R2

;

Where R1 and R2 are registers in the currently selected

working register area.

Figure 3-2. Working Register Addressing

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INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the

operand. Depending on the instruction used, the actual address may point to a register in the register file, to

program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to

indirectly address another memory location.

Program Memory

Register File

ADDRESS

8-Bit Register

File Address

dst

OPCODE

Point to one

register in register

file

One-Operand

Instruction (Example)

Address of operand

used by instruction

OPERAND

Value used in

instruction execution

Sample Instruction:

RL

@SHIFT

;

Where SHIFT is the label of an 8-bit register ddress

Figure 3-3. Indirect Register Addressing to Register File

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INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

Program Memory

Example

REGISTER

PAIR

dst

Instruction

References

Program

Point to

register pair

OPCODE

16-bit

Memory

address

pointsto

program

memory

Program Memory

OPERAND

Value used in

instruction

Sample Instructions:

CALL

JP

@RR2

Figure 3-4. Indirect Register Addressing to Program Memory

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INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

CFH

.

Program Memory

4-Bit

4 LSBs

Working

Register

Address

OPERAND

dst

src

Point to the

working register

(1 of 16)

OPCODE

C0H

Sample Instruction:

OR R6, @R2

Value used in

instruction

OPERAND

Figure 3-5. Indirect Working Register Addressing to Register File

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INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

CFH

.

Program Memory

4-Bit Working

Register Address

dst

src

Register

Pair

Next 3 Bits Point

to working

OPCODE

Example instruction

references either

program memory or

data memory

C0H

register pair

(1 of 8)

16-Bit

address

points to

program

memory

or data

Program Memory

or

Data Memory

LSB Selects

memory

Value used in

instruction

OPERAND

Sample Instructions:

LCD

LDE

R5,@RR6

R3,@RR14

@RR4, R8

; Program memory access

; External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

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INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to

calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access

locations in the internal register file or in external memory.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range

– 128 to + 127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained

in a working register. For external memory accesses, the base address is stored in the working register pair

designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address

(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external

program memory, and for external data memory, when implemented.

Register File

~

Value used in

instruction

OPERAND

INDEX

+

Program Memory

X (OFFSET)

4 LSBs

dst

src

Two-Operand

Instruction

Example

Point to one of the

working register

(1 of 16)

OPCODE

Sample Instruction:

LD R0, #BASE[R1]

;

Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

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INDEXED ADDRESSING MODE (Continued)

Program Memory

Register File

XS (OFFSET)

4-Bit Working

NEXT 3 Bits

Register

Pair

dst

src

Register Address

Point to working

register pair

(1 of 8)

OPCODE

16-Bit

address

added to

offset

LSB Selects

+

16-Bit

8-Bit

Program Memory

or

Data memory

Value used in

instruction

OPERAND

16-Bit

Sample Instructions:

LDC

LDE

R4, #04H[RR2]

R4,#04H[RR2]

;

The values in the program address (RR2 + #04H)

are loaded into register R4.

Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

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INDEXED ADDRESSING MODE (Continued)

Program Memory

XLH (OFFSET)

Register File

XLL (OFFSET)

4-Bit Working

Register

Pair

NEXT 3 Bits

dst

src

Register Address

Point to working

register pair

(1 of 8)

OPCODE

16-Bit

address

added to

offset

LSB Selects

+

16-Bit

Program Memory

or

Datamemory

Value used in

instruction

OPERAND

16-Bit

Sample Instructions:

LDC

LDE

R4, #1000H[RR2]

; The values in the program address (RR2 + #1000H)

are loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset

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DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC

whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load

operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Memory

Address

Used

Program Memory

Upper Address Byte

Lower Address Byte

LSB Selects Program

dst/src

"0" or "1"

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory

OPCODE

Sample Instructions:

LDC

LDE

R5,1234H; The values in the program address (1234H)are loaded

into register R5.

R5,1234H; Identical operation to LDC example, except that

external program memory isaccessed.

Figure 3-10. Direct Addressing for Load Instructions

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DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Program

Memory

Address

Used

Lower Address Byte

Upper Address Byte

OPCODE

Sample Instructions:

JP

CALL

C,JOB1

DISPLAY

;

Where JOB1 isa 16-bit immediate address

Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

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RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in

the instruction. The displacement value is then added to the current PC value. The result is the address of the next

instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately

following the current instruction.

The instruction that support RA addressing is JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current

PC Value

+

Displacement

OPCODE

Current Instruction

Signed

Displacement Value

Sample Instructions:

JR

ULT,$ + OFFSET

;

Where OFFSET isa value in the range + 127 to - 128

Figure 3-12. Relative Addressing

IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand

field itself. Immediate addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction: LD

R0,#0AAH

Figure 3-13. Immediate Addressing

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4

CONTROL REGISTERS

OVERVIEW

In this section, detailed descriptions of the S3F94C8/F94C4 control registers are presented in an easy-to-read

format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use

them as a quick-reference source when writing application programs.

System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the

standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More information

about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this

manual.

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Table 4-1. System and Peripheral Control Registers

Register name

Mnemonic

Address & Location

RESET value (Bit)

Address

D0H

R/W

R

7

0

1

0

6

0

1

0

5

0

1

–

4

0

1

–

3

0

1

0

2

0

1

–

1

0

1

0

1

0

Timer 0 counter register

Timer 0 data register

Timer 0 control register

T0CNT

T0DATA

T0CON

D1H

R/W

D2H

Location D3H is not mapped

Clock control register

System flags register

CLKCON

FLAGS

D4H

D5H

R/W

0

x

–

0

x

0

–

x

–

Locations D6H–D8H are not mapped

Stack pointer register

SP

D9H

R/W

x

Location DAH is not mapped

MDS special register

MDSREG

BTCON

BTCNT

FTSTCON

SYM

DBH

DCH

DDH

DEH

DFH

R/W

R

0

–

0

–

0

–

0

–

0

Basic timer control register

Basic timer counter

Test mode control register

System mode register

W

R/W

NOTES:

1. – : Not mapped or not used, x: Undefined

2. The register, FTSTCON, is no use. Its value should always be '00H' during the normal operation.

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Table 4-1. System and Peripheral Control Registers (Continued)

Register Name

Mnemonic

Address

Hex

R/W

Bit Values After RESET

7

0

–

6

0

–

0

5

0

–

0

4

0

–

0

3

0

–

0

2

0

1

0

Port 0 data register

P0

P1

P2

E0H

R/W

Port 1 data register

Port 2 data register

E1H

E2H

Locations E3H–E5H are not mapped

Port 0 control register (High byte)

Port 0 control register

P0CONH

P0CONL

P0PND

E6H

E7H

E8H

E9H

EAH

EBH

R/W

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

Port 0 interrupt pending register

Port 1 control register

P1CON

Port 2 control register (High byte)

Port 2 control register (Low byte)

Flash memory control register

P2CONH

P2CONL

FMCON

FMUSR

ECH

EDH

Flash memory user programming

enable register

EEH

EFH

R/W

Flash memory sector address register

(high byte)

FMSECH

FMSECL

0

Flash memory sector address register

(low byte)

PWM data register 1

PWM extension register

PWM data register

PWMDATA1

PWMEX

F0H

F1H

F2H

F3H

F4H

R/W

0

–

0

PWMDATA

PWMCON

STOPCON

PWM control register

STOP control register

Locations F5H–F6H are not mapped

A/D control register

ADCON

ADDATAH

ADDATAL

F7H

F8H

F9H

R/W

R

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

A/D converter data register ( High )

A/D converter data register ( Low )

R

Locations FAH–FFH are not mapped

NOTE: – : Not mapped or not used, x: Undefined

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Bit number(s) that is/are appended to the

register name for bit addressing

Name of individual

bit or related bits

Register address

(hexadecimal)

Register

Register name

ID

D5H

FLAGS - System Flags Register

.7

.6

.5

.4

.3

.2

.1

.0

Bit Identifier

RESET Value

Read/Write

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

0

R/W

0

R/W

.7

Carry Flag (C)

0

1

Operation dose not generate a carry or borrow condition

Operation generates carry-out or borrow into high-order bit7

.6

Zero Flag

0

1

Operation result is a non-zero value

Operation result is zero

.5

Sign Flag

0

1

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

R = Read-only

W = Write-only

R/W = Read/write

' - ' = Not used

Description of the

effect of specific

bit settings

RESET value notation:

'-' = Not used

'x' = Undetermind value

'0' = Logic zero

'1' = Logic one

Bit number:

MSB = Bit 7

LSB = Bit 0

Figure 4-1. Register Description Format

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ADCON — A/D Converter Control Register

F7H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.4

A/D Converter Input Pin Selection Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ADC0 (P0.0)

ADC1 (P0.1)

ADC2 (P0.2)

ADC3 (P0.3)

ADC4 (P0.4)

ADC5 (P0.5)

ADC6 (P0.6)

ADC7 (P0.7)

ADC8 (P2.6)

Connected with GND internally

.3

End-of-Conversion Status Bit

0

1

A/D conversion is in progress

A/D conversion complete

(note)

.2–.1

Clock Source Selection Bit

0

1

0

1

0

1

f

/16 (f

ꢅ 10 MHz)

OSC

/8 (f

/4 (f

/1 (f

ꢅ 10 MHz)

ꢅ 4 MHz)

OSC

.0

Conversion Start Bit

0

1

No meaning

A/D conversion start

NOTE: Maximum ADC clock input = 4 MHz.

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BTCON — Basic Timer Control Register

DCH

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.4

Watchdog Timer Function Enable Bit

1

0

1

0

Disable watchdog timer function

Enable watchdog timer function

Others

.3–.2

Basic Timer Input Clock Selection Code

f

/4096

/1024

/128

0

1

0

1

0

1

OSC

Invalid setting

.1

.0

Basic Timer 8-Bit Counter Clear Bit

0

1

No effect

Clear the basic timer counter value

Basic Timer and Timer 0 Divider Clear Bit

0

1

No effect

Clear both dividers

NOTE: When you write a "1" to BTCON.0 (or BTCON.1), the basic timer divider and timer 0 divider (or basic timer counter) are

cleared. The bit is then cleared automatically to "0".

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CLKCON — Clock Control Register

D4H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

–

.5

–

.4

0

.3

0

.2

–

.1

–

.0

–

R/W

–

R/W

–

.7

Oscillator IRQ Wake-up Function Enable Bit

0

1

Enable IRQ for main system oscillator wake-up function

Disable IRQ for main system oscillator wake-up function

.6–.5

.4–.3

Not used for S3F94C8/F94C4

Divided by Selection Bits for CPU Clock frequency

Divide by 16 (f

/16)

0

1

0

1

0

1

OSC

Divide by 8 (f

/8)

OSC

Divide by 2 (f

/2)

OSC

Non-divided clock (f

)

OSC

.2–.0

Not used for S3F94C8/F94C4

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FLAGS — System Flags Register

D5H

Bit Identifier

RESET Value

Read/Write

.7

x

.6

x

.5

x

.4

x

.3

–

.2

–

.1

–

.0

–

R/W

–

.7

Carry Flag (C)

0

1

Operation does not generate a carry or borrow condition

Operation generates a carry-out or borrow into high-order bit 7

.6

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

.5

Sign Flag (S)

0

1

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

.4

Overflow Flag (V)

0

1

Operation result is ꢅ + 127 or ꢆ – 128

Operation result is > + 127 or < – 128

.3–.0

Not used for S3F94C8/F94C4

NOTE: The unused bits .3-.0 should always be kept as ‘0’ in normal operation; otherwise it may be cause error execution.

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FMCON — Flash Memory Control Register

ECH

Bit Identifier

Reset Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

–

.2

–

.1

–

.0

0

R/W

–

R/W

.7–.4

Flash Memory Mode Selection Bits

0

1

0

1

0

1

0

1

0

Programming mode

Sector erase mode

Hard lock mode

Not available

Other values

.3–.1

Not used for the S3F94C8/F94C4

.0

Flash Operation Start Bit

0

1

Operation stop

Operation start (This bit will be cleared automatically just after the corresponding

operator completed).

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FMSECH — Flash Memory Sector Address Register (High Byte)

EEH

Bit Identifier

Reset Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.0

Flash Memory Sector Address Bits (High Byte)

The 15th - 8th bits to select a sector of flash ROM

NOTE: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.

FMSECL — Flash Memory Sector Address Register (Low Byte)

EFH

Bit Identifier

Reset Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7

Flash Memory Sector Address Bit (Low Byte)

th

The 7 bit to select a sector of flash ROM

.6–.0

Bits 6–0

Don't care

NOTE: The low-byte flash memory sector address pointer value is the lower eight bits of the 16-bit pointer address.

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FMUSR — Flash Memory User Programming Enable Register

EDH

Bit Identifier

Reset Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.0

Flash Memory User Programming Enable Bits

1 0 1 0 0 1 0 1 Enable user programming mode

Other values Disable user programming mode

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P0CONH — Port 0 Control Register (High Byte)

E6H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.6

.5–.4

.3–.2

.1–.0

Port 0, P0.7/ADC7 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

A/D converter input (ADC7); Schmitt trigger input off

Port 0, P0.6/ADC6/PWM Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Alternative function (PWM output)

Push-pull output

A/D converter input (ADC6); Schmitt trigger input off

Port 0, P0.5/ADC5 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

A/D converter input (ADC5); Schmitt trigger input off

Port 0, P0.4/ADC4 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

A/D converter input (ADC4); Schmitt trigger input off

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P0CONL — Port 0 Control Register (Low Byte)

E7H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.6

.5–.4

.3–.2

.1–.0

Port 0, P0.3/ADC3 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input; pull-up enable

Push-pull output

A/D converter input (ADC3); Schmitt trigger input off

Port 0, P0.2/ADC2 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input; pull-up enable

Push-pull output

A/D converter input (ADC2); Schmitt trigger input off

Port 0, P0.1/ADC1/INT1 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input/falling edge interrupt input

Schmitt trigger input; pull-up enable/falling edge interrupt input

Push-pull output

A/D converter input (ADC1); Schmitt trigger input off

Port 0, P0.0/ADC0/INT0 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input/falling edge interrupt input

Schmitt trigger input; pull-up enable/falling edge interrupt input

Push-pull output

A/D converter input (ADC0); Schmitt trigger input off

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P0PND — Port 0 Interrupt Pending Register

E8H

Bit Identifier

RESET Value

Read/Write

.7

–

.6

–

.5

–

.4

–

.3

0

.2

0

.1

0

.0

0

–

R/W

.7–.4

Not used for the S3F94C8/F94C4

Port 0.1/ADC1/INT1 Interrupt Enable Bit

.3

0

1

INT1 falling edge interrupt disable

INT1 falling edge interrupt enable

.2

Port 0.1/ADC1/INT1 Interrupt Pending Bit

0

1

No interrupt pending (when read)

Pending bit clear (when write)

Interrupt is pending (when read)

No effect (when write)

.1

.0

Port 0.0/ADC0/INT0 Interrupt Enable Bit

0

1

INT0 falling edge interrupt disable

INT0 falling edge interrupt enable

Port 0.0/ADC0/INT0 Interrupt Pending Bit

0

1

No interrupt pending (when read)

Pending bit clear (when write)

Interrupt pending (when read)

No effect (when write)

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P1CON — Port 1 Control Register

E9H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

–

.4

–

.3

0

.2

0

.1

0

.0

0

R/W

–

R/W

.7

Part 1.1 N-channel open-drain Enable Bit

0

1

Configure P1.1 as a push-pull output

Configure P1.1 as a n-channel open-drain output

.6

Port 1.0 N-channel open-drain Enable Bit

0

1

Configure P1.0 as a push-pull output

Configure P1.0 as a n-channel open-drain output

.5–.4

.3–.2

Not used for S3F94C8/F94C4

Port 1, P1.1 Interrupt Pending Bits

0

1

0

1

0

1

Schmitt trigger input;

Schmitt trigger input; pull-up enable

Output

Schmitt trigger input; pull-down enable

.1–.0

Port 1, P1.0 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input;

Schmitt trigger input; pull-up enable

Output

Schmitt trigger input; pull-down enable

NOTE: When you use external oscillator, P1.0, P1.1 must be set to output port to prevent current consumption.

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P2CONH — Port 2 Control Register (High Byte)

EAH

Bit Identifier

RESET Value

Read/Write

.7

–

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

–

R/W

.7

Not used for the S3F94C8/F94C4

Port 2, P2.6/ADC8/CLO Configuration Bits

.6–.4

0

1

0

1

0

1

0

1

x

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

ADC input

Push-pull output

Open-drain output; pull-up enable

Open-drain output

Alternative function; CLO output

.3–.2

.1–.0

Port 2, 2.5 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

Open-drain output

Port 2, 2.4 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

Open-drain output

NOTE: When noise problem is important issue, you had better not use CLO output.

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P2CONL — Port 2 Control Register (Low Byte)

EBH

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.6

.5–.4

.3–.2

.1–.0

Part 2, P2.3 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

Open-drain output

Port 2, P2.2 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

Open-drain output

Port 2, P2.1 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

Open-drain output

Port 2, P2.0 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input; pull-up enable

Schmitt trigger input

Push-pull output

T0 match output

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PWMCON — PWM Control Register

F3H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

–

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

–

R/W

.7–.6

PWM Input Clock Selection Bits

f

/64

0

1

0

1

0

1

OSC

/8

/2

/1

.5

.4

Not used for S3F94C8/F94C4

PWMDATA Reload Interval Selection Bit

0

1

Reload from extension up counter overflow

Reload from base up counter overflow

.3

.2

.1

.0

PWM Counter Clear Bit

0

1

No effect

Clear the PWM counter (when write)

PWM Counter Enable Bit

0

1

Stop counter

Start (Resume countering)

PWM Overflow Interrupt Enable Bit (8-Bit Overflow)

0

1

Disable interrupt

Enable interrupt

PWM Overflow Interrupt Pending Bit

0

1

No interrupt pending (when read)

Clear pending bit (when write)

Interrupt is pending (when read)

No effect (when write)

NOTE: 1. PWMCON.3 is not auto-cleared. You must pay attention when clear pending bit. (refer to page 11-12).

2. PWMCON.5 should always be set to ‘0’

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PWMEX — PWM Extension Register

F1H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.2

.1–.0

PWM Extension Bits

PWM extension bits for 6+6 resolution and 8+6 resolution; Not used in 6+2 resolution

PWM Base/extension Control bits:

0

1

0

1

0

1

Base 6-bit (PWMDATA.7-.2 ) + Extension 2-bit (PWMDATA.1-.0)

Base 6-bit (PWMDATA1.5-.0 ) + Extension 6-bit (PWMEX.7-.2)

Base 8-bit (PWMDATA1.7-.0 ) + Extension 6-bit (PWMEX.7-.2)

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STOPCON — STOP Mode Control Register

E4H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

.7–.0

Watchdog Timer Function Enable Bit

10100101 Enable STOP instruction

Other value Disable STOP instruction

NOTE: When STOPCON register is not #0A5H value, if you use STOP instruction, PC is changed to reset address.

SYM ^{— System Mode Register}

DFH

Bit Identifier

RESET Value

Read/Write

.7

–

.6

–

.5

–

.4

–

.3

0

.2

0

.1

0

.0

0

–

R/W

.7–.4

Not used for S3F94C8/F94C4

.3

Global Interrupt Enable Bit

0

1

Disable all interrupts

Enable all interrupt

.2–.0

Page Select Bits

0

1

0

1

0

1

Page 0

Page 1 (Not used for S3F94C8/F94C4)

Page 2 (Not used for S3F94C8/F94C4)

Page 3 (Not used for S3F94C8/F94C4)

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T0CON — TIMER 0 Control Register

D2H

Bit Identifier

RESET Value

Read/Write

.7

0

.6

0

.5

–

.4

–

.3

0

.2

–

.1

0

.0

0

R/W

–

R/W

–

R/W

.7–.6

Timer 0 Input Clock Selection Bits

f

/4096

/256

/8

0

1

0

1

0

1

OSC

/1

.5–.4

Not used for the S3F94C8/F94C4

.3

Timer 0 Counter Clear Bit

0

1

No effect

Clear the timer 0 counter (when write)

.2

.1

Not used for the S3F94C8/F94C4

Timer 0 Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

.0

Timer 0 Interrupt Pending Bit (Match interrupt)

0

1

No interrupt pending (when read)

Clear pending bit (when write)

Interrupt is pending (when read)

No effect (when write)

NOTES:

1. T0CON.3 is not auto-cleared. You must pay attention when clear pending bit. (refer to page 10-12)

2. To use T0 match output, you set T0CON.3 to "1". (refer to page 10-7)

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NOTES

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5

INTERRUPT STRUCTURE

OVERVIEW

The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt

sources can be serviced through an interrupt vector which is assigned in ROM address 0000H.

VECTOR

SOURCES

S1

0000H

0001H

S2

S3

Sn

NOTES:

1. The SAM88RCRI interrupt has only one vector address (0000H-0001H).

2. The number of Sn value is expandable.

Figure 5-1. S3F9-Series Interrupt Type

INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can be controlled in two ways: either globally, or by specific interrupt source.

The system-level control points in the interrupt structure are therefore:

— Global interrupt enable and disable (by EI and DI instructions)

— Interrupt source enable and disable settings in the corresponding peripheral control register(s)

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ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

The system mode register, SYM (DFH), is used to enable and disable interrupt processing.

SYM.3 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.3.

NOTE

The system initialization routine executed after a reset must always contain an EI instruction to globally

enable the interrupt structure.

Although you can manipulate SYM.3 directly to enable and disable interrupts during normal operation, we

recommend that you use the EI and DI instructions for this purpose.

INTERRUPT PENDING FUNCTION TYPES

When the interrupt service routine has executed, the application program's service routine must clear the

appropriate pending bit before the return from interrupt subroutine (IRET) occurs.

INTERRUPT PRIORITY

Because there is not an interrupt priority register in SAM88RCRI, the order of service is determined by a sequence

of source which is executed in interrupt service routine.

"EI" Instruction

Execution

Interrupt Pending

Register

S

R

Q

RESET

Source Interrupts

Enable

Source Interrupts

Interrpt priority

is determind by

software polling

method

Vector

Interrupt

Cycle

Global Interrupt

Control (EI, DI instruction)

Figure 5-2. Interrupt Function Diagram

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INTERRUPT SOURCE SERVICE SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request pending bit to "1".

2. The CPU generates an interrupt acknowledge signal.

3. The service routine starts and the source's pending flag is cleared to "0" by software.

4. Interrupt priority must be determined by software polling method.

INTERRUPT SERVICE ROUTINES

Before an interrupt request can be serviced, the following conditions must be met:

— Interrupt processing must be enabled (EI, SYM.3 = "1")

— Interrupt must be enabled at the interrupt's source (peripheral control register)

If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The

CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0")

to disable all subsequent interrupts.

2. Save the program counter and status flags to stack.

3. Branch to the interrupt vector to fetch the service routine's address.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores

the PC and status flags and sets SYM.3 to "1" (EI), allowing the CPU to process the next interrupt request.

GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt

processing follows this sequence:

1. Push the program counter's low-byte value to stack.

2. Push the program counter's high-byte value to stack.

3. Push the FLAGS register values to stack.

4. Fetch the service routine's high-byte address from the vector address 0000H.

5. Fetch the service routine's low-byte address from the vector address 0001H.

6. Branch to the service routine specified by the 16-bit vector address.

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S3F94C8/F94C4 INTERRUPT STRUCTURE

The S3F94C8/F94C4 microcontroller has four peripheral interrupt sources:

— PWM overflow

— Timer 0 match

— P0.0 external interrupt

— P0.1 external interrupt

Enable/Disable

T0CON.1

Pending Bits

T0CON.0

Vector

Source

Timer 0 Match

PWM Overflow

PWMCON.0

P0PND.0

PWMCON.1

0000H

0001H

P0.0 External Interrupt

P0.1 External Interrupt

P0PND.1

P0PND.3

SYM.3

(EI, DI)

P0PND.2

Figure 5-3. S3F94C8/F94C4 Interrupt Structure

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PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the

interrupt generated by the related peripheral (see Table 5-1).

Table 5-1. Interrupt Source Control and Data Registers

Interrupt Source

Register(s)

Register Location(s)

P0.0 external interrupt

P0.1 external interrupt

P0CONL

P0PND

E7H

E8H

Timer 0 match interrupt

PWM overflow interrupt

T0CON

T0DATA

D2H

D1H

PWMCON

PWMDATA

F3H

F2H

PWMDATA1

F0H

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NOTES

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6

SAM88RCRI INSTRUCTION SET

OVERVIEW

The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of

8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because

I/O control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate,

and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set.

REGISTER ADDRESSING

To access an individual register, an 8-bit address in the range 0–255 or the 4-bit address of a working register is

specified. Paired registers can be used to construct 16-bit program memory or data memory addresses. For detailed

information about register addressing, please refer to Chapter 2, "Address Spaces".

ADDRESSING MODES

There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and

Immediate (IM). For detailed descriptions of these addressing modes, please refer to Chapter 3, "Addressing

Modes".

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Table 6-1. Instruction Group Summary

Operands Instruction

Mnemonic

Load Instructions

CLR

LD

dst

Clear

dst,src

dst

Load

LDC

LDE

Load program memory

Load external data memory

LDCD

LDED

LDCI

LDEI

POP

PUSH

Load program memory and decrement

Load external data memory and decrement

Load program memory and increment

Load external data memory and increment

Pop from stack

src

Push to stack

Arithmetic Instructions

ADC

ADD

CP

dst,src

dst

Add with carry

Add

Compare

DEC

INC

Decrement

Increment

Subtract with carry

Subtract

dst

SBC

SUB

dst,src

Logic Instructions

AND

COM

OR

dst,src

dst

Logical AND

Complement

dst,src

Logical OR

XOR

Logical exclusive OR

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Table 6-1. Instruction Group Summary (Continued)

Operands Instruction

Mnemonic

Program Control Instructions

CALL

IRET

JP

dst

Call procedure

Interrupt return

cc,dst

dst

Jump on condition code

Jump unconditional

JP

JR

cc,dst

Jump relative on condition code

Return

RET

Bit Manipulation Instructions

TCM

TM

dst,src

Test complement under mask

Test under mask

Rotate and Shift Instructions

RL

dst

Rotate left

RLC

RR

Rotate left through carry

Rotate right

RRC

SRA

Rotate right through carry

Shift right arithmetic

CPU Control Instructions

CCF

DI

Complement carry flag

Disable interrupts

Enable interrupts

Enter Idle mode

No operation

EI

IDLE

NOP

RCF

SCF

STOP

Reset carry flag

Set carry flag

Enter stop mode

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FLAGS REGISTER (FLAGS)

The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits,

FLAGS.4–FLAGS.7, can be tested and used with conditional jump instructions;

FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load

instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register.

For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND

instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur

to the Flags register producing an unpredictable result.

System Flags Register (FLAGS)

D5H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Carry flag (C)

Not mapped

Zero flag (Z)

Sign flag (S)

Overflow flag (V)

Figure 6-1. System Flags Register (FLAGS)

FLAG DESCRIPTIONS

Overflow Flag (FLAGS.4, V)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than – 128. It is

also cleared to "0" following logic operations.

Sign Flag (FLAGS.5, S)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic

zero indicates a positive number and a logic one indicates a negative number.

Zero Flag (FLAGS.6, Z)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test

register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.

Carry Flag (FLAGS.7, C)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7

position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.

Program instructions can set, clear, or complement the carry flag.

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INSTRUCTION SET NOTATION

Table 6-2. Flag Notation Conventions

Flag

C

Z

Description

Carry flag

Zero flag

S

V

0

Sign flag

Overflow flag

Cleared to logic zero

Set to logic one

1

*

Set or cleared according to operation

Value is unaffected

Value is undefined

–

x

Table 6-3. Instruction Set Symbols

Symbol

Description

Destination operand

dst

src

@

Source operand

Indirect register address prefix

Program counter

PC

FLAGS

#

Flags register (D5H)

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

H

D

B

Binary number suffix

opc

Opcode

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Table 6-4. Instruction Notation Conventions

Description Actual Operand Range

Notation

cc

r

Condition code

See list of condition codes in Table 6-6.

Rn (n = 0–15)

Working register only

rr

Working register pair

RRp (p = 0, 2, 4, ..., 14)

R

Register or working register

Register pair or working register pair

reg or Rn (reg = 0–255, n = 0–15)

RR

reg or RRp (reg = 0–254, even number only, where

p = 0, 2, ..., 14)

Ir

IR

Indirect working register only

@Rn (n = 0–15)

Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)

Irr

Indirect working register pair only

@RRp (p = 0, 2, ..., 14)

IRR

Indirect register pair or indirect working

register pair

@RRp or @reg (reg = 0–254, even only, where

p = 0, 2, ..., 14)

X

Indexed addressing mode

#reg[Rn] (reg = 0–255, n = 0–15)

XS

Indexed (short offset) addressing mode

#addr[RRp] (addr = range – 128 to + 127, where

p = 0, 2, ..., 14)

XL

Indexed (long offset) addressing mode

#addr [RRp] (addr = range 0–8191, where

p = 0, 2, ..., 14)

DA

RA

Direct addressing mode

Relative addressing mode

addr (addr = range 0–8191)

addr (addr = number in the range + 127 to – 128 that is

an offset relative to the address of the next instruction)

IM

Immediate addressing mode

#data (data = 0–255)

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Table 6-5. Opcode Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

–

0

1

2

3

4

5

6

7

U

P

E

R

0

DEC

R1

DEC

IR1

ADD

r1,r2

ADD

r1,Ir2

R2,R1

IR2,R1

R1,IM

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

RLC

R1

RLC

IR1

ADC

r1,r2

ADC

r1,Ir2

ADC

R2,R1

ADC

IR2,R1

ADC

R1,IM

INC

R1

INC

IR1

SUB

r1,r2

SUB

r1,Ir2

SUB

R2,R1

SUB

IR2,R1

SUB

R1,IM

JP

IRR1

SBC

r1,r2

SBC

r1,Ir2

SBC

R2,R1

SBC

IR2,R1

SBC

R1,IM

OR

r1,r2

OR

r1,Ir2

OR

R2,R1

OR

IR2,R1

OR

R1,IM

POP

R1

POP

IR1

AND

r1,r2

AND

r1,Ir2

AND

R2,R1

AND

IR2,R1

AND

R1,IM

N

I

COM

R1

COM

IR1

TCM

r1,r2

TCM

r1,Ir2

TCM

R2,R1

TCM

IR2,R1

TCM

R1,IM

PUSH

R2

PUSH

IR2

TM

r1,r2

TM

r1,Ir2

TM

R2,R1

TM

IR2,R1

TM

R1,IM

B

L

E

LD

r1, x, r2

RL

R1

RL

IR1

LD

r2, x, r1

CP

r1,r2

CP

r1,Ir2

CP

R2,R1

CP

IR2,R1

CP

R1,IM

LDC

r1, Irr2, xL

CLR

R1

CLR

IR1

XOR

r1,r2

XOR

r1,Ir2

XOR

R2,R1

XOR

IR2,R1

XOR

R1,IM

LDC

r2, Irr2, xL

RRC

R1

RRC

IR1

LDC

r1,Irr2

LD

r1, Ir2

H

E

X

SRA

R1

SRA

IR1

LDC

r2,Irr1

LD

IR1,IM

LD

Ir1, r2

RR

R1

RR

IR1

LDCD

r1,Irr2

LDCI

r1,Irr2

LD

R2,R1

LD

R2,IR1

LD

R1,IM

LDC

r1, Irr2, xs

CALL

IRR1

LD

IR2,R1

CALL

DA1

LDC

r2, Irr1, xs

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Product Specification

68

Table 6-5. Opcode Quick Reference (Continued)

OPCODE MAP

LOWER NIBBLE (HEX)

–

8

9

A

B

C

D

E

F

U

P

0

LD

JR

LD

JP

INC

r1

r1,R2

r2,R1

cc,RA

r1,IM

cc,DA

1

ꢇ

P

E

R

2

3

4

5

N

I

6

IDLE

STOP

DI

7

B

L

E

8

9

EI

A

B

C

D

E

F

RET

IRET

RCF

SCF

CCF

NOP

H

E

X

LD

r1,R2

LD

r2,R1

JR

cc,RA

LD

r1,IM

JP

cc,DA

INC

r1

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P R E L I M I N A R Y

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Product Specification

69

CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under

which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a

compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump

instructions.

Table 6-6. Condition Codes

Binary

0000

Mnemonic

Description

Always false

Flags Set

F

T

C

–

1000

Always true

(1)

Carry

C = 1

C = 0

Z = 1

Z = 0

S = 0

S = 1

V = 1

V = 0

Z = 1

Z = 0

0111

(1)

NC

Z

No carry

1111

(1)

Zero

0110

(1)

NZ

Not zero

1110

PL

1101

0101

0100

1100

Plus

MI

Minus

OV

NOV

EQ

NE

GE

LT

Overflow

No overflow

Equal

(1)

0110

(1)

Not equal

1110

1001

0001

1010

0010

Greater than or equal

Less than

(S XOR V) = 0

(S XOR V) = 1

(Z OR (S XOR V)) = 0

(Z OR (S XOR V)) = 1

C = 0

GT

LE

Greater than

Less than or equal

Unsigned greater than or equal

Unsigned less than

Unsigned greater than

Unsigned less than or equal

(1)

UGE

ULT

UGT

ULE

1111

(1)

C = 1

0111

1011

0011

(C = 0 AND Z = 0) = 1

(C OR Z) = 1

NOTES:

1. It indicates condition codes that are related to two different mnemonics but which test the same flag.

For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;

after a CP instruction, however, EQ would probably be used.

2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

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Product Specification

70

INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction in the SAM87RI

instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The

following information is included in each instruction description:

— Instruction name (mnemonic)

— Full instruction name

— Source/destination format of the instruction operand

— Shorthand notation of the instruction's operation

— Textual description of the instruction's effect

— Specific flag settings affected by the instruction

— Detailed description of the instruction's format, execution time, and addressing mode(s)

— Programming example(s) explaining how to use the instruction

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Product Specification

71

ADC — Add with Carry

ADC

dst,src

Operation:

dst ꢃ dst + src + c

The source operand, along with the setting of the carry flag, is added to the destination operand and

the sum is stored in the destination. The contents of the source are unaffected.

Two's-complement addition is performed. In multiple precision arithmetic, this instruction permits

the carry from the addition of low-order operands to be carried into the addition of high-order

operands.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

12

13

r

lr

dst

src

3

6

14

15

R

IR

dst

6

16

R

IM

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register

03H = 0AH:

ADC

R1,R2

ꢈ

R1 = 14H, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#11H

R1 = 1BH, R2 = 03H

Register 01H = 24H, register 02H = 03H

Register 01H = 2BH, register 02H = 03H

Register 01H = 32H

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and

the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and

the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

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P R E L I M I N A R Y

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Product Specification

72

ADD — Add

ADD

dst,src

Operation:

dst ꢃ dst + src

The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. Two's-complement addition is performed.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is

of the opposite sign; cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

02

03

r

lr

dst

src

3

6

04

05

R

IR

dst

6

06

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD

R1,R2

ꢈ

R1 = 15H, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#25H

R1 = 1CH, R2 = 03H

Register 01H = 24H, register 02H = 03H

Register 01H = 2BH, register 02H = 03H

Register 01H = 46H

In the first example, destination working register R1 contains 12H and the source working register

R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register

R1.

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P R E L I M I N A R Y

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Product Specification

73

AND — Logical AND

AND

dst,src

Operation:

dst ꢃ dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the

destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in

the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source

are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

52

53

r

lr

dst

src

3

6

54

55

R

IR

dst

6

56

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

AND

R1,R2

ꢈ

R1 = 02H, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#25H

R1 = 02H, R2 = 03H

Register 01H = 01H, register 02H = 03H

Register 01H = 00H, register 02H = 03H

Register 01H = 21H

In the first example, destination working register R1 contains the value 12H and the source working

register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with

the destination operand value 12H, leaving the value 02H in register R1.

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P R E L I M I N A R Y

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Product Specification

74

CALL — Call Procedure

CALL

dst

Operation:

SP

ꢃꢄ

SP – 1

PCL

SP –1

PCH

dst

@SP ꢃꢄ

SP ꢃꢄ

@SP ꢃꢄ

PC ꢃꢄ

The current contents of the program counter are pushed onto the top of the stack. The program

counter value used is the address of the first instruction following the CALL instruction. The

specified destination address is then loaded into the program counter and points to the first

instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to

return to the original program flow. RET pops the top of the stack back into the program counter.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

3

14

F6

DA

dst

2

12

F4

IRR

Examples:

Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H:

CALL

1521H

ꢈ

SP = 0B0H

(Memory locations 00H = 1AH, 01H = 4AH, where 4AH

is the address that follows the instruction.)

CALL

@RR0

ꢈ

SP = 0B0H (00H = 1AH, 01H = 49H)

In the first example, if the program counter value is 1A47H and the stack pointer contains the value

0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The

stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the

address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the

statement "CALL @RR0" produces the same result except that the 49H is stored in stack location

01H (because the two-byte instruction format was used). The PC is then loaded with the value

1521H, the address of the first instruction in the program sequence to be executed.

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Product Specification

75

CCF — Complement Carry Flag

CCF

Operation:

C ꢃꢄꢄNOT C

The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero;

if C = "0", the value of the carry flag is changed to logic one.

Flags:

C: Complemented.

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

EF

Example:

Given: The carry flag = "0":

CCF

If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing

its value from logic zero to logic one.

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Product Specification

76

CLR — Clear

CLR

dst

Operation:

dst ꢃꢄꢄ"0"

The destination location is cleared to "0".

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

B0

B1

R

IR

Examples:

Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:

CLR

00H

ꢈ

Register 00H = 00H

@01H

Register 01H = 02H, register 02H = 00H

In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H

value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)

addressing mode to clear the 02H register value to 00H.

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Product Specification

77

COM — Complement

COM

dst

Operation:

dst ꢃꢄ NOT dst

The contents of the destination location are complemented (one's complement); all "1s" are

changed to "0s", and vice-versa.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

R

opc

dst

2

4

60

61

IR

Examples:

Given: R1 = 07H and register 07H = 0F1H:

COM

R1

ꢈ

R1 = 0F8H

R1 = 07H, register 07H = 0EH

@R1

In the first example, destination working register R1 contains the value 07H (00000111B). The

statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and

vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value of

destination register 07H (11110001B), leaving the new value 0EH (00001110B).

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Product Specification

78

CP — Compare

CP

dst,src

Operation:

dst – src

The source operand is compared to (subtracted from) the destination operand, and the appropriate

flags are set accordingly. The contents of both operands are unaffected by the comparison.

Flags:

C: Set if a "borrow" occurred (src > dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of

the result is of the same as the sign of the source operand; cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

A2

A3

r

lr

dst

src

3

6

A4

A5

R

IR

dst

6

A6

R

IM

Examples:

1. Given: R1 = 02H and R2 = 03H:

CP R1,R2 ꢈꢄ Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the

value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1

value (destination/minuend). Because a "borrow" occurs and the difference is negative,

C and S are "1".

2. Given: R1 = 05H and R2 = 0AH:

CP

JP

INC

LD

R1,R2

UGE,SKIP

R1

SKIP

R3,R1

In this example, destination working register R1 contains the value 05H which is less than the

contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C =

"1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"

executes, the value 06H remains in working register R3.

PS031501-0813

P R E L I M I N A R Y

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Product Specification

79

DEC — Decrement

DEC

dst

Operation:

dst ꢃꢄꢄdst – 1

The contents of the destination operand are decremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, dst value is – 128 (80H) and result value is

+ 127 (7FH); cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

R

opc

dst

2

4

00

01

IR

Examples:

Given: R1 = 03H and register 03H = 10H:

DEC

R1

ꢈ

R1 = 02H

Register 03H = 0FH

@R1

In the first example, if working register R1 contains the value 03H, the statement "DEC R1"

decrements the hexadecimal value by one, leaving the value 02H. In the second example, the

statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one,

leaving the value 0FH.

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P R E L I M I N A R Y

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Product Specification

80

DI — Disable Interrupts

DI

Operation:

SYM (3) ꢃꢄꢄ0

Bit zero of the system mode register, SYM.3, is cleared to "0", globally disabling all interrupt

processing. Interrupt requests will continue to set their respective interrupt pending bits, but the

CPU will not service them while interrupt processing is disabled.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

8F

Example:

Given: SYM = 08H:

DI

If the value of the SYM register is 08H, the statement "DI" leaves the new value 00H in the register

and clears SYM.3 to "0", disabling interrupt processing.

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81

EI — Enable Interrupts

EI

Operation:

SYM (3) ꢃꢄꢄ1

An EI instruction sets bit 2 of the system mode register, SYM.3 to "1". This allows interrupts to be

serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled

(by executing a DI instruction), it will be serviced when you execute the EI instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

9F

Example:

Given: SYM = 00H:

EI

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement

"EI" sets the SYM register to 08H, enabling all interrupts. (SYM.3 is the enable bit for global interrupt

processing.)

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82

IDLE — Idle Operation

IDLE

Operation:

The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle

mode can be released by an interrupt request (IRQ) or an external reset operation.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

1

4

6F

–

Example:

The instruction

IDLE

NOP

stops the CPU clock but not the system clock.

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Product Specification

83

INC — Increment

INC

dst

Operation:

dst ꢃꢄꢄdst + 1

The contents of the destination operand are incremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is dst value is + 127 (7FH) and result is – 128 (80H);

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

dst | opc

opc

1

4

rE

r

r = 0 to F

dst

2

4

20

21

R

IR

Examples:

Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

INC

R0

ꢈ

R0 = 1CH

00H

@R0

Register 00H = 0DH

R0 = 1BH, register 01H = 10H

In the first example, if destination working register R0 contains the value 1BH, the statement "INC

R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it contains

the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of

register 1BH from 0FH to 10H.

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Product Specification

84

IRET — Interrupt Return

IRET

Operation:

FLAGS ꢃꢄꢄ@SP

SP ꢃꢄꢄSP + 1

PC ꢃꢄꢄ@SP

SP ꢃꢄꢄSP + 2

SYM(2) ꢃꢄꢄ1

This instruction is used at the end of an interrupt service routine. It restores the flag register and the

program counter. It also re-enables global interrupts.

Flags:

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Format:

IRET

(Normal)

Bytes

Cycles

Opcode

(Hex)

opc

1

10

12

BF

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P R E L I M I N A R Y

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Product Specification

85

JP — Jump

JP

cc,dst

(Conditional)

JP

dst

(Unconditional)

Operation:

If cc is true, PC ꢃꢄꢄdst

The conditional JUMP instruction transfers program control to the destination address if the

condition specified by the condition code (cc) is true; otherwise, the instruction following the JP

instruction is executed. The unconditional JP simply replaces the contents of the PC with the

contents of the specified register pair. Control then passes to the statement addressed by the PC.

Flags:

No flags are affected.

(1)

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

(2)

cc | opc

dst

3

8

ccD

DA

cc = 0 to F

opc

dst

2

8

30

IRR

NOTES:

1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the

op code are both four bits.

Examples:

Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:

JP

C,LABEL_W

@00H

ꢈ

LABEL_W = 1000H, PC = 1000H

PC = 0120H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement

"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to

that location. Had the carry flag not been set, control would then have passed to the statement

immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents of

the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

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P R E L I M I N A R Y

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Product Specification

86

JR — Jump Relative

JR

cc,dst

Operation:

If cc is true, PC ꢃꢄꢄPC + dst

If the condition specified by the condition code (cc) is true, the relative address is added to the

program counter and control passes to the statement whose address is now in the program counter;

otherwise, the instruction following the JR instruction is executed (See list of condition codes).

The range of the relative address is + 127, – 128, and the original value of the program counter is

taken to be the address of the first instruction byte following the JR statement.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

(note)

cc | opc

dst

2

6

ccB

RA

cc = 0 to F

NOTE: In the first byte of the two-byte instruction format, the condition code and the op code are each

four bits.

Example:

Given: The carry flag = "1" and LABEL_X = 1FF7H:

JR

C,LABEL_X

ꢈ

PC = 1FF7H

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass

control to the statement whose address is now in the PC. Otherwise, the program instruction

following the JR would be executed.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

87

LD — Load

LD

dst,src

Operation:

dst ꢃꢄꢄsrc

The contents of the source are loaded into the destination. The source's contents are unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

IM

R

dst | opc

src | opc

opc

src

dst

2

4

rC

r8

r

2

3

4

r9

R

r

r = 0 to F

dst | src

src

4

C7

D7

r

lr

r

Ir

opc

dst

src

6

E4

E5

R

IR

opc

dst

6

E6

D6

R

IM

IR

opc

src

dst

x

3

6

F5

87

97

IR

r

R

x [r]

r

dst | src

src | dst

x

x [r]

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

88

LD — Load

LD

(Continued)

Examples:

Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,

register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:

LD

R0,#10H

ꢈ

R0 = 10H

R0,01H

R0 = 20H, register 01H = 20H

Register 01H = 01H, R0 = 01H

R1 = 20H, R0 = 01H

01H,R0

R1,@R0

@R0,R1

R0 = 01H, R1 = 0AH, register 01H = 0AH

Register 00H = 20H, register 01H = 20H

Register 02H = 20H, register 00H = 01H

Register 00H = 0AH

00H,01H

02H,@00H

00H,#0AH

@00H,#10H

@00H,02H

R0,#LOOP[R1]

#LOOP[R0],R1

Register 00H = 01H, register 01H = 10H

Register 00H = 01H, register 01H = 02, register 02H = 02H

R0 = 0FFH, R1 = 0AH

Register 31H = 0AH, R0 = 01H, R1 = 0AH

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

89

LDC/LDE — Load Memory

LDC/LDE

dst,src

Operation:

dst ꢃꢄꢄsrc

This instruction loads a byte from program or data memory into a working register or vice-versa.

The source values are unaffected. LDC refers to program memory and LDE to data memory. The

assembler makes "Irr" or "rr" values an even number for program memory and odd an odd number

for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

1.

2.

3.

4.

5.

opc

dst | src

src | dst

dst | src

src | dst

dst | src

2

10

C3

D3

E7

F7

A7

r

Irr

2

3

4

10

12

14

Irr

r

XS

XL

r

XS [rr]

r

XS [rr]

r

XL

XL [rr]

L

H

XL

6.

7.

opc

src | dst

dst | 0000

src | 0000

dst | 0001

src | 0001

4

14

B7

A7

B7

A7

B7

XL [rr]

r

DA

r

L

H

DA

r

L

H

8.

DA

r

9.

DA

r

10.

opc

DA

NOTES:

1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.

2. For formats 3 and 4, the destination address "XS [rr]" and the source address "XS [rr]" are each one

byte.

3. For formats 5 and 6, the destination address "XL [rr]" and the source address "XL [rr]" are each two

bytes.

4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set

of values, used in formats 9 and 10, are used to address data memory.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

90

LDC/LDE — Load Memory

LDC/LDE

(Continued)

Examples:

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory

locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External

data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H

= 98H:

LDC

LDE

LDC

R0,@RR2

@RR2,R0

; R0 ꢃ contents of program memory location 0104H

; R0 = 1AH, R2 = 01H, R3 = 04H

; R0 ꢃ contents of external data memory location 0104H

; R0 = 2AH, R2 = 01H, R3 = 04H

(note)

; 11H (contents of R0) is loaded into program memory

; location 0104H (RR2),

; working registers R0, R2, R3 ꢈ no change

LDE

LDC

@RR2,R0

; 11H (contents of R0) is loaded into external data memory

; location 0104H (RR2),

; working registers R0, R2, R3 ꢈ no change

R0,#01H[RR4]

; R0 ꢃ contents of program memory location 0061H

; (01H + RR4),

; R0 = AAH, R2 = 00H, R3 = 60H

LDE

LDC

LDE

LDC

LDE

R0,#01H[RR4]

#01H[RR4],R0

; R0 ꢃ contents of external data memory location 0061H

; (01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H

(note)

; 11H (contents of R0) is loaded into program memory location

; 0061H (01H + 0060H)

; 11H (contents of R0) is loaded into external data memory

; location 0061H (01H + 0060H)

R0,#1000H[RR2] ; R0 ꢃ contents of program memory location 1104H

; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H

R0,#1000H[RR2] ; R0 ꢃ contents of external data memory location 1104H

; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H

LDC

LDE

R0,1104H

; R0 ꢃ contents of program memory location 1104H, R0 = 88H

; R0 ꢃ contents of external data memory location 1104H,

; R0 = 98H

(note)

LDC

LDE

1105H,R0

; 11H (contents of R0) is loaded into program memory location

; 1105H, (1105H) ꢃ 11H

; 11H (contents of R0) is loaded into external data memory

; location 1105H, (1105H) ꢃ 11H

NOTE: These instructions are not supported by masked ROM type devices.

PS031501-0813 P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

91

LDCD/LDED — Load Memory and Decrement

LDCD/LDED dst,src

Operation:

dst ꢃꢄꢄsrc

rr ꢃꢄꢄrr – 1

These instructions are used for user stacks or block transfers of data from program or data memory

to the register file. The address of the memory location is specified by a working register pair. The

contents of the source location are loaded into the destination location. The memory address is then

decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler

makes "Irr" an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

2

10

E2

r

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and

external data memory location 1033H = 0DDH:

LDCD

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is decremented by one

; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ꢃꢄꢄRR6 – 1)

LDED

R8,@RR6

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is decremented by one (RR6 ꢃꢄꢄRR6 – 1)

; R8 = 0DDH, R6 = 10H, R7 = 32H

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

92

LDCI/LDEI — Load Memory and Increment

LDCI/LDEI

dst,src

Operation:

dst ꢃꢄꢄsrc

rr ꢃꢄꢄrr + 1

These instructions are used for user stacks or block transfers of data from program or data memory

to the register file. The address of the memory location is specified by a working register pair. The

contents of the source location are loaded into the destination location. The memory address is then

incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler makes

"Irr" even for program memory and odd for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

2

10

E3

r

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and

1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6 ꢃꢄꢄRR6 + 1)

; R8 = 0CDH, R6 = 10H, R7 = 34H

LDEI

R8,@RR6

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6 ꢃꢄꢄRR6 + 1)

; R8 = 0DDH, R6 = 10H, R7 = 34H

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

93

NOP — No Operation

NOP

Operation:

No action is performed when the CPU executes this instruction. Typically, one or more NOPs are

executed in sequence in order to effect a timing delay of variable duration.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

FF

Example:

When the instruction

NOP

is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution

time.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

94

OR — Logical OR

OR

dst,src

Operation:

dst ꢃꢄꢄdst OR src

The source operand is logically ORed with the destination operand and the result is stored in the

destination. The contents of the source are unaffected. The OR operation results in a "1" being

stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is

stored.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

42

43

r

lr

dst

src

3

6

44

45

R

IR

dst

6

46

R

IM

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register

08H = 8AH:

OR

R0,R1

ꢈ

R0 = 3FH, R1 = 2AH

R0,@R2

00H,01H

01H,@00H

00H,#02H

R0 = 37H, R2 = 01H, register 01H = 37H

Register 00H = 3FH, register 01H = 37H

Register 00H = 08H, register 01H = 0BFH

Register 00H = 0AH

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH,

the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH)

in destination register R0.

The other examples show the use of the logical OR instruction with the various addressing modes

and formats.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

95

POP — Pop From Stack

POP

dst

Operation:

dst ꢃꢄꢄ@SP

SP ꢃꢄꢄSP + 1

The contents of the location addressed by the stack pointer are loaded into the destination. The

stack pointer is then incremented by one.

Flags:

No flags affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

8

50

51

R

IR

Examples:

Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH

= 55H:

POP

00H

ꢈ

Register 00H = 55H, SP = 0BCH

@00H

Register 00H = 01H, register 01H = 55H, SP = 0BCH

In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads

the contents of location 0BBH (55H) into destination register 00H and then increments the stack

pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

96

PUSH — Push To Stack

PUSH

src

Operation:

SP ꢃꢄꢄSP – 1

@SP ꢃꢄꢄsrc

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)

into the location addressed by the decremented stack pointer. The operation then adds the new

value to the top of the stack.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

src

2

8

70

71

R

IR

Examples:

Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H:

PUSH

40H

ꢈ

Register 40H = 4FH, stack register 0BFH = 4FH,

SP = 0BFH

PUSH

@40H

ꢈ

Register 40H = 4FH, register 4FH = 0AAH, stack register

0BFH = 0AAH, SP = 0BFH

In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value

4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the

contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP

points to location 0BFH.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

97

RCF — Reset Carry Flag

RCF

Operation:

C ꢃꢄꢄ0

The carry flag is cleared to logic zero, regardless of its previous value.

Flags:

C: Cleared to "0".

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

CF

Example:

Given: C = "1" or "0":

The instruction RCF clears the carry flag (C) to logic zero.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

98

RET — Return

RET

Operation:

PC ꢃꢄꢄ@SP

SP ꢃꢄꢄSP + 2

The RET instruction is normally used to return to the previously executing procedure at the end of a

procedure entered by a CALL instruction. The contents of the location addressed by the stack

pointer are popped into the program counter. The next statement that is executed is the one that is

addressed by the new program counter value.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

8

AF

10

Example:

Given: SP = 0BCH, (SP) = 101AH, and PC = 1234:

RET PC = 101AH, SP = 0BEH

ꢈ

The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of

the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's

low byte and the instruction at location 101AH is executed. The stack pointer now points to memory

location 0BEH.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

99

RL — Rotate Left

RL

dst

Operation:

C ꢃꢄꢄdst (7)

dst (0) ꢃꢄꢄdst (7)

dst (n + 1) ꢃꢄꢄdst (n), n = 0–6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is

moved to the bit zero (LSB) position and also replaces the carry flag.

7

0

C

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

90

91

R

IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

RL

00H

ꢈ

Register 00H = 55H, C = "1"

Register 01H = 02H, register 02H = 2EH, C = "0"

@01H

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement

"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and

setting the carry and overflow flags.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

100

RLC — Rotate Left Through Carry

RLC

dst

Operation:

dst (0) ꢃꢄꢄC

C ꢃꢄꢄdst (7)

dst (n + 1) ꢃꢄꢄdst (n), n = 0–6

The contents of the destination operand with the carry flag are rotated left one bit position. The initial

value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

7

0

C

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

10

11

R

IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

RLC

00H

ꢈ

Register 00H = 54H, C = "1"

@01H

Register 01H = 02H, register 02H = 2EH, C = "0"

In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC

00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the

initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The

MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

101

RR — Rotate Right

RR

dst

Operation:

C ꢃꢄꢄdst (0)

dst (7) ꢃꢄꢄdst (0)

dst (n) ꢃꢄꢄdst (n + 1), n = 0–6

The contents of the destination operand are rotated right one bit position. The initial value of bit zero

(LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

7

0

C

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

E0

E1

R

IR

Examples:

Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:

RR

00H

ꢈ

Register 00H = 98H, C = "1"

Register 01H = 02H, register 02H = 8BH, C = "1"

@01H

In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR

00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7,

leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets

the C flag to "1" and the sign flag and overflow flag are also set to "1".

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

102

RRC — Rotate Right Through Carry

RRC

dst

Operation:

dst (7) ꢃꢄꢄC

C ꢃꢄꢄdst (0)

dst (n) ꢃꢄꢄdst (n + 1), n = 0–6

The contents of the destination operand and the carry flag are rotated right one bit position. The

initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7

(MSB).

7

0

C

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0" cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

C0

C1

R

IR

Examples:

Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

RRC

00H

ꢈ

Register 00H = 2AH, C = "1"

@01H

Register 01H = 02H, register 02H = 0BH, C = "1"

In the first example, if general register 00H contains the value 55H (01010101B), the statement

"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces

the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH

(00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

103

SBC — Subtract With Carry

SBC

dst,src

Operation:

dst ꢃꢄꢄdst – src – c

The source operand, along with the current value of the carry flag, is subtracted from the destination

operand and the result is stored in the destination. The contents of the source are unaffected.

Subtraction is performed by adding the two's-complement of the source operand to the destination

operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the

subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.

Flags:

C: Set if a borrow occurred (src ꢉ dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of

the result is the same as the sign of the source; cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

32

33

r

lr

dst

src

3

6

34

35

R

IR

dst

6

36

R

IM

Examples:

Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register

03H = 0AH:

SBC

R1,R2

ꢈ

R1 = 0CH, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#8AH

R1 = 05H, R2 = 03H, register 03H = 0AH

Register 01H = 1CH, register 02H = 03H

Register 01H = 15H,register 02H = 03H, register 03H = 0AH

Register 01H = 95H; C, S, and V = "1"

In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the

statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the

destination (10H) and then stores the result (0CH) in register R1.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

104

SCF — Set Carry Flag

SCF

Operation:

C ꢃꢄꢄ1

The carry flag (C) is set to logic one, regardless of its previous value.

Flags:

C: Set to "1".

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

DF

Example:

The statement

SCF

sets the carry flag to logic one.

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Product Specification

105

SRA — Shift Right Arithmetic

SRA

dst

Operation:

dst (7) ꢃꢄꢄdst (7)

C ꢃꢄꢄdst (0)

dst (n) ꢃꢄꢄdst (n + 1), n = 0–6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the

LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit

position 6.

7 6

0

C

Flags:

C: Set if the bit shifted from the LSB position (bit zero) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Always cleared to "0".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

D0

D1

R

IR

Examples:

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

SRA

00H

ꢈ

Register 00H = 0CD, C = "0"

@02H

Register 02H = 03H, register 03H = 0DEH, C = "0"

In the first example, if general register 00H contains the value 9AH (10011010B), the statement

"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag

and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value

0CDH (11001101B) in destination register 00H.

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Product Specification

106

STOP— Stop Operation

STOP

Operation:

The STOP instruction stops the both the CPU clock and system clock and causes the

microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,

peripheral registers, and I/O port control and data registers are retained. Stop mode can be

released by an external reset operation or External interrupt input. For the reset operation, the

RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

1

4

7F

–

Example:

The statement

LD

STOPCON, #0A5H

STOP

NOP

halts all microcontroller operations. When STOPCON register is not #0A5H value, if you use STOP

instruction, PC is changed to reset address.

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Product Specification

107

SUB — Subtract

SUB

dst,src

Operation:

dst ꢃꢄꢄdst – src

The source operand is subtracted from the destination operand and the result is stored in the

destination. The contents of the source are unaffected. Subtraction is performed by adding the

two's complement of the source operand to the destination operand.

Flags:

C: Set if a "borrow" occurred; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of

the result is of the same as the sign of the source operand; cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

22

23

r

lr

dst

src

3

6

24

25

R

IR

dst

6

26

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

SUB

R1,R2

ꢈ

R1 = 0FH, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#90H

01H,#65H

R1 = 08H, R2 = 03H

Register 01H = 1EH, register 02H = 03H

Register 01H = 17H, register 02H = 03H

Register 01H = 91H; C, S, and V = "1"

Register 01H = 0BCH; C and S = "1", V = "0"

In the first example, if working register R1 contains the value 12H and if register R2 contains the

value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value

(12H) and stores the result (0FH) in destination register R1.

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Product Specification

108

TCM — Test Complement Under Mask

TCM

dst,src

Operation:

(NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).

The TCM statement complements the destination operand, which is then ANDed with the source

mask. The zero (Z) flag can then be checked to determine the result. The destination and source

operands are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

62

63

r

lr

dst

src

3

6

64

65

R

IR

dst

6

66

R

IM

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register

02H = 23H:

TCM

R0,R1

ꢈ

R0 = 0C7H, R1 = 02H, Z = "1"

R0,@R1

00H,01H

00H,@01H

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, register 01H = 02H, Z = "1"

Register 00H = 2BH, register 01H = 02H,

register 02H = 23H, Z = "1"

TCM

00H,#34

ꢈ

Register 00H = 2BH, Z = "0"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1

the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for

a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and

can be tested to determine the result of the TCM operation.

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Product Specification

109

TM — Test Under Mask

TM

dst,src

Operation:

dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand (mask),

which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine

the result. The destination and source operands are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

72

73

r

lr

dst

src

3

6

74

75

R

IR

dst

6

76

R

IM

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register

02H = 23H:

TM

R0,R1

ꢈ

R0 = 0C7H, R1 = 02H, Z = "0"

R0,@R1

00H,01H

00H,@01H

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, register 01H = 02H, Z = "0"

Register 00H = 2BH, register 01H = 02H,

register 02H = 23H, Z = "0"

TM

00H,#54H

ꢈ

Register 00H = 2BH, Z = "1"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1

the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a

"0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and

can be tested to determine the result of the TM operation.

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Product Specification

110

XOR — Logical Exclusive OR

XOR

dst,src

Operation:

dst ꢃꢄꢄdst XOR src

The source operand is logically exclusive-ORed with the destination operand and the result is

stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the

corresponding bits in the operands are different; otherwise, a "0" bit is stored.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

B2

B3

r

lr

dst

src

3

6

B4

B5

R

IR

dst

6

B6

R

IM

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register

02H = 23H:

XOR

R0,R1

ꢈ

R0 = 0C5H, R1 = 02H

R0,@R1

00H,01H

00H,@01H

00H,#54H

R0 = 0E4H, R1 = 02H, register 02H = 23H

Register 00H = 29H, register 01H = 02H

Register 00H = 08H, register 01H = 02H, register 02H = 23H

Register 00H = 7FH

In the first example, if working register R0 contains the value 0C7H and if register R1 contains the

value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and

stores the result (0C5H) in the destination register R0.

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Product Specification

111

NOTES

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Product Specification

112

7

CLOCK CIRCUIT

OVERVIEW

By smart option (3FH.1 – .0 in ROM), user can select internal RC oscillator, external RC oscillator, or external

oscillator. In using internal oscillator, XIN (P1.0), XOUT (P1.1) can be used by normal I/O pins. An internal RC

oscillator source provides a typical 3.2 MHz or 0.5 MHz (in VDD = 5 V) depending on smart option.

An external RC oscillation source provides a typical 4MHz clock for S3F94C8/F94C4. An internal capacitor

supports the RC oscillator circuit. An external crystal or ceramic oscillation source provides a maximum 10 MHz

clock. The XIN and XOUT pins connect the oscillation source to the on-chip clock circuit. Simplified external RC

oscillator and crystal/ceramic oscillator circuits are shown in Figures 7-1 and 7-2. When you use external oscillator,

P1.0, P1.1 must be set to output port to prevent current consumption.

X_IN

C1

C2

XIN

R

S3F94C8/F94C4

XOUT

Figure 7-2. Main Oscillator Circuit

(Crystal/Ceramic Oscillator)

Figure 7-1. Main Oscillator Circuit

(RC Oscillator with Internal Capacitor)

MAIN OSCILLATOR LOGIC

To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator

circuit. For this reason, very high-resolution waveforms (square signal edges) must be generated in order for the

CPU to efficiently process logic operations.

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113

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows:

— In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file

and current system register values are retained. Stop mode is released, and the oscillator started, by a reset

operation or by an external interrupt with RC-delay noise filter (for S3F94C8/F94C4, INT0–INT1).

— In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The

current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file is

retained. Idle mode is released by a reset or by an interrupt (external or internally-generated).

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the

following functions:

— Oscillator IRQ wake-up function enable/disable (CLKCON.7)

— Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3)

The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release

(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7.

After a reset, the external interrupt oscillator wake-up function is enabled, and the f_OSC/16 (the slowest clock speed)

is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to f

, f

/2 or f

/8.

OSC OSC

OSC

System Clock Control Register (CLKCON)

D4H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Oscillator IRQ wake-up enable bit:

0 = Enable IRQ for main system

oscillator wake-up function in

power down mode.

1 = Disable IRQ for main system

oscillator wake-up function in

power down mode.

Not used for S3F94C8/F94C4

Divide-by selection bits for

CPU clock frequency:

00 = fosc/16

01 = fosc/8

10 = fosc/2

11 = fosc (non-divided)

Not used for S3F94C8/F94C4

Figure 7-3. System Clock Control Register (CLKCON)

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114

Smart Option

(3F.1-0 in ROM)

Stop

Instruction

CLKCON.4-.3

Internal RC

Oscillator (3.2MHz)

Oscillator

Stop

Internal RC

Oscillator (0.5 MHz)

1/2

1/8

M

U

X

Selected

OSC

MUX

CPU Clock

P2.6/CLO

External

Crystal/Ceramic

Oscillator

Wake-up

1/16

External RC

Oscillator

Noise

Filter

CLKCON.7

P2CONH.6-.4

INT Pin

NOTE:

An external interrupt (with RC-delay noise filter) can be used to release stop mode

and "wake-up" the main oscillator.

In the S3F94C8/F94C4, the INT0-INT1 external interrupts are of this type.

Figure 7-4. System Clock Circuit Diagram

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Product Specification

115

NOTES

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Product Specification

116

8

RESET AND POWER-DOWN

SYSTEM RESET

OVERVIEW

By smart option (3EH.7 in ROM), user can select internal RESET (LVR) or external RESET. In using internal

RESET (LVR), nRESET pin (P1.2) can be used by normal I/O pin.

The S3F94C8/F94C4 can be RESET in four ways:

— by external power-on-reset

— by the external nRESET input pin pulled low

— by the digital watchdog peripheral timing out

— by Low Voltage Reset (LVR)

During a external power-on reset, the voltage at V is High level and the nRESET pin is forced to Low level. The

DD

nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This

brings the S3F94C8/F94C4 into a known operating status. To ensure correct start-up, the user should take care

that nRESET signal is not released before the V level is sufficient to allow MCU operation at the chosen

DD

frequency.

The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within

tolerance in order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation

19

stabilization time for a reset is approximately 52.4 ms (@ 2 /f

, f

= 10 MHz).

OSC OSC

When a reset occurs during normal operation (with both V and nRESET at High level), the signal at the nRESET

DD

pin is forced Low and the Reset operation starts. All system and peripheral control registers are then set to their

default hardware Reset values (see Table 8-1).

The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction. If

watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be

activated.

The on-chip Low Voltage Reset, features static Reset when supply voltage is below a reference value (Typ. 1.9,

2.3, 3.0, 3.6, 3.9 V). Thanks to this feature, external reset circuit can be removed while keeping the application

safety. As long as the supply voltage is below the reference value, there is a internal and static RESET. The MCU

can start only when the supply voltage rises over the reference value.

When you calculate power consumption, please remember that a static current of LVR circuit should be added a

CPU operating current in any operating modes such as Stop, Idle, and normal RUN mode when LVR enable in

Smart Option.

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Product Specification

117

Watchdog RESET

RESET

N.F

Internal System

RESETB

Longger than 1us

VDD

Comparator

+

V

IN

When the VDD level

is lower than V^LVR

N.F

V

REF

-

Longger than 1us

V

DD

Smart Option 3EH.7

V

REF

BGR

NOTES:

1. The target of voltage detection level is the one you selected at smart option3EH.

2. BGR is Band Gap voltage Reference

Figure 8-1. Low Voltage Reset Circuit

NOTE

To program the duration of the oscillation stabilization interval, you must make the appropriate settings to

the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the

basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you

can disable it by writing "1010B" to the upper nibble of BTCON.

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118

External RESET pin

When the nRESET pin transiting from V (low input level of reset pin) to V (high input level of reset pin), the

IL

IH

reset pulse is generated.

VDD

XIN

R

C

X

OUT

nRESET

S3F94C8/F94C4

VSS

Notes:

1. R < 100Kohm is recommended to make sure that the voltage drop across R

does not violate the detection of reset pulse.

Figure 8-2. Recommended External RESET Circuit

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119

MCU Initialization Sequence

The following sequence of events occurs during a Reset operation:

— All interrupts are disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0–2 are set to input mode

— Peripheral control and data registers are disabled and reset to their initial values (see Table 8-1).

— The program counter is loaded with the ROM reset address, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location

0100H (and 0101H) is fetched and executed.

Smart Option

(3EH.7)

nRESET

MUX

Internal nRESET

LVR nRESET

Watchdog nRESET

Figure 8-3. Reset Block Diagram

Oscillation Stabilization Wait Time (52.4 ms/at 10 MHz)

nRESET Input

Operation Mode

Idle Mode

Normal Mode or

Power-Down Mode

RESET Operation

Figure 8-4. Timing for S3F94C8/F94C4 After RESET

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120

POWER-DOWN MODES

STOP MODE

Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all

peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 4ꢊA

except that the LVR(Low Voltage Reset) is enable. All system functions are halted when the clock "freezes", but

data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a nRESET

signal or by an external interrupt.

NOTE: Before execute the STOP instruction, must set the STPCON register as “10100101b”.

Using RESET to Release Stop Mode

Stop mode is released when the nRESET signal is released and returns to High level. All system and peripheral

control registers are then Reset to their default values and the contents of all data registers are retained. A Reset

operation automatically selects a slow clock (f

/16) because CLKCON.3 and CLKCON.4 are cleared to "00B".

OSC

After the oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by fetching

the 16-bit address stored in ROM locations 0100H and 0101H.

Using an External Interrupt to Release Stop Mode

External interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related external

interrupts cannot be used). External interrupts INT0-INT1 in the S3F94C8/F94C4 interrupt structure meet this

criterion.

Note that when Stop mode is released by an external interrupt, the current values in system and peripheral control

registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and CLKCON.4

register values remain unchanged, and the currently selected clock value is used. If you use an external interrupt

for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you

must put the appropriate value to BTCON register before entering Stop mode.

The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine,

the instruction immediately following the one that initiated Stop mode is executed.

IDLE MODE

Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select

peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt

logic and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered.

There are two ways to release Idle mode:

1. Execute a Reset. All system and peripheral control registers are Reset to their default values and the contents

of all data registers are retained. The Reset automatically selects a slow clock (f

/16) because CLKCON.3

OSC

and CLKCON.4 are cleared to "00B". If interrupts are masked, a Reset is the only way to release Idle mode.

2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle

mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock

value is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction

immediately following the one that initiated Idle mode is executed.

NOTES

1. Only external interrupts that are not clock-related can be used to release stop mode. To release Idle

mode, however, any type of interrupt (that is, internal or external) can be used.

2. Before enter the STOP or IDLE mode, the ADC must be disabled. Otherwise, the STOP or IDLE

current will be increased significantly.

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121

HARDWARE RESET VALUES

Table 8-1 lists the values for CPU and system registers, peripheral control registers, and peripheral data registers

following a Reset operation in normal operating mode.

— A "1" or a "0" shows the Reset bit value as logic one or logic zero, respectively.

— An "x" means that the bit value is undefined following a reset.

— A dash ("–") means that the bit is either not used or not mapped.

Table 8-1. Register Values After a Reset

Register Name

Mnemonic

Address & Location

RESET Value (Bit)

Address

D0H

R/W

R

7

0

1

0

6

0

1

0

5

0

1

–

4

0

1

–

3

0

1

0

2

0

1

–

1

0

1

0

Timer 0 counter register

Timer 0 data register

Timer 0 control register

T0CNT

T0DATA

T0CON

0

1

0

D1H

R/W

D2H

Location D3H is not mapped

Clock control register

System flags register

CLKCON

FLAGS

D4H

D5H

R/W

0

x

–

0

x

0

–

x

–

Locations D6H–D8H are not mapped

Stack pointer register

SP

D9H

R/W

x

Location DAH is not mapped

MDS special register

MDSREG

BTCON

BTCNT

FTSTCON

SYM

DBH

DCH

DDH

DEH

DFH

R/W

R

0

–

0

–

0

–

0

–

0

Basic timer control register

Basic timer counter

Test mode control register

System mode register

W

R/W

NOTE: – : Not mapped or not used, x: undefined

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Bit Values After RESET

Table 8-1. Register Values After a Reset (Continued)

Register Name

Mnemonic

Address

Hex

R/W

7

0

–

6

0

–

0

5

0

–

0

4

0

–

0

3

0

–

0

2

0

1

0

Port 0 data register

P0

P1

P2

E0H

R/W

Port 1 data register

Port 2 data register

E1H

E2H

Locations E3H–E5H are not mapped

0

–

0

–

0

–

0

–

0

–

0

Port 0 control register (High byte)

Port 0 control register

P0CONH

P0CON

P0PND

E6H

E7H

E8H

E9H

EAH

EBH

R/W

0

–

0

–

0

Port 0 interrupt pending register

Port 1 control register

P1CON

P2CONH

P2CONL

FMCON

FMUSR

Port 2 control register (High byte)

Port 2 control register (Low byte)

Flash memory control register

ECH

EDH

Flash memory user programming

enable register

EEH

EFH

R/W

Flash memory sector address register

(high byte)

FMSECH

FMSECL

0

Flash memory sector address register

(low byte)

PWM data register 1

PWM extension register

PWM data register

PWMDATA1

PWMEX

F0H

F1H

F2H

F3H

F4H

R/W

0

–

0

PWMDATA

PWMCON

STOPCON

PWM control register

STOP control register

Locations F5H–F6H are not mapped

0

x

0

x

0

x

0

x

0

x

0

x

0

x

A/D control register

ADCON

ADDATAH

ADDATAL

F7H

F8H

F9H

R/W

R

0

x

0

A/D converter data register (High)

A/D converter data register (Low)

R

Locations FAH–FFH are not mapped

NOTE: – : Not mapped or not used, x: undefined

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ꢀ

PROGRAMMING TIP — Sample S3F94C8/F94C4 Initialization Routine

;--------------<< Interrupt Vector Address >>

ORG

0000H

VECTOR

00H,INT_94C4

; S3F94C8/F94C4 has only one interrupt vector

;--------------<< Smart Option >>

ORG

DB

003CH

00H

0E7H

03H

; 003CH, must be initialized to 0

; 003DH, must be initialized to 0

; 003EH, enable LVR (2.3 V)

DB

; 003FH, internal RC (3.2 MHz in V = 5 V )

DD

;--------------<< Initialize System and Peripherals >>

ORG

DI

0100H

RESET:

; disable interrupt

LD

BTCON,#10100011B

CLKCON,#00011000B

SP,#0C0H

; Watch-dog disable

LD

; Select non-divided CPU clock

; Stack pointer must be set

LD

P0CONH,#10101010B

P0CONL,#10101010B

P1CON,#00001010B

P2CONH,#01001010B

P2CONL,#10101010B

;

; P0.0–P0.7 push-pull output

; P1.0–P1.1 push-pull output

;

; P2.0–P2.6 push-pull output

;--------------<< Timer 0 settings >>

LD

T0DATA,#50H

T0CON,#01001010B

; CPU = 3.2 MHz, interrupt interval = 6.4 msec

; f

/256, Timer 0 interrupt enable

OSC

;--------------<< Clear all data registers from 00h to 5FH >>

LD

R0,#0

; RAM clear

RAM_CLR: CLR

@R0

;

INC

CP

JP

R0

R0,#0BFH

ULE,RAM_CLR

;--------------<< Initialize other registers >>

ꢀ

EI

; Enable interrupt

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124

ꢀ

PROGRAMMING TIP — Sample S3F94C8/F94C4 Initialization Routine (Continued)

;--------------<< Main loop >>

MAIN:

NOP

LD

; Start main loop

BTCON,#02H

KEY_SCAN

LED_DISPLAY

JOB

; Enable watchdog function

; Basic counter (BTCNT) clear

ꢀ

CALL

ꢀ

;

ꢀ

CALL

ꢀ

;

ꢀ

CALL

ꢀ

JR

T,MAIN

;--------------<< Subroutines >>

KEY_SCAN: NOP

ꢀ

RET

LED_DISPLAY: NOP

;

ꢀ

RET

JOB:

NOP

ꢀ

RET

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ꢀ

PROGRAMMING TIP — Sample S3F94C8/F94C4 Initialization Routine (Continued)

;--------------<< Interrupt Service Routines >> ; Interrupt enable bit and pending bit check

INT_94C4: TM

T0CON,#00000010B

Z,NEXT_CHK1

T0CON,#00000001B

NZ,INT_TIMER0

; Timer0 interrupt enable check

;

; If timer0 interrupt was occurred,

; T0CON.0 bit would be set.

JR

TM

JP

NEXT_CHK1:

TM

JR

TM

JP

PWMCOM,#00000010B ; PWM overflow interrupt enable check

Z,NEXT_CHK2

;

P0PND,#00000001B

NZ,PWMOVF_INT

NEXT_CHK2:

TM

JR

TM

JP

P0PND,#00000010B

Z,NEXT_CHK3

P0PND,#00000001B

NZ,INT0_INT

; INT0 interrupt enable check

;

NEXT_CHK3:

TM

JP

TM

JP

IRET

P0PND,#00001000B

Z,END_INT

P0PND,#00000100B

NZ,INT1_INT

; INT1 interrupt enable check

;

; Interrupt return

END_INT

; IRET

;--------------< Timer0 interrupt service routine >

INT_TIMER0:

ꢀ

;

AND

IRET

T0CON,#11110110B

; Pending bit clear

; Interrupt return

;--------------< PWM overflow interrupt service routine >

PWMOVF_INT:

ꢀ

AND

IRET

PWMCON,#11110110B ; Pending bit clear

; Interrupt return

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ꢀ

PROGRAMMING TIP — Sample S3F94C8/F94C4 Initialization Routine (Continued)

;--------------< External interrupt0 service routine >

INT0_INT:

ꢀ

AND

IRET

P0PND,#11111110B

; INT0 Pending bit clear

; Interrupt return

;--------------< External interrupt1 service routine >

INT1_INT:

ꢀ

AND

IRET

ꢀ

P0PND,#11111011B

; INT1 Pending bit clear

; Interrupt return

ꢀ

END

;

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NOTES

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9

I/O PORTS

OVERVIEW

The S3F94C8/F94C4 has three I/O ports: with 18 pins total. You access these ports directly by writing or reading

port data register addresses.

All ports can be configured as LED drive. (High current output: typical 10 mA)

Table 9-1. S3F94C8/F94C4 Port Configuration Overview

Port

Function Description

Programmability

0

Bit-programmable I/O port for Schmitt trigger input or push-pull output.

Pull-up resistors are assignable by software. Port 0 pins can also be used

as alternative function. (ADC input, external interrupt input).

Bit

1

2

Bit-programmable I/O port for Schmitt trigger input or push-pull, open-

drain output. Pull-up or pull-down resistors are assignable by software.

Port 1 pins can also oscillator input/output or reset input by smart option.

P1.2 is input only.

Bit

Bit-programmable I/O port for Schmitt trigger input or push-pull, open-

drain output. Pull-up resistor are assignable by software. Port 2 can also

be used as alternative function (ADC input, CLO, T0 clock output)

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PORT DATA REGISTERS

Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. Data

registers for ports 0-2 have the structure shown in Figure 9-1.

Table 9-2. Port Data Register Summary

Register Name

Port 0 data register

Port 1 data register

Port 2 data register

Mnemonic

Hex

E0H

E1H

E2H

R/W

P0

P1

P2

NOTE: A reset operation clears the P0–P2 data register to "00H".

I/O Port n Data Register (n = 0-2)

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pn.0

Pn.1

Pn.2

Pn.3

Pn.4

Pn.5

Pn.6

Pn.7

Figure 9-1. Port Data Register Format

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PORT 0

Port 0 is a bit-programmable, general-purpose, I/O ports. You can select normal input or push-pull output mode. In

addition, you can configure a pull-up resistor to individual pins using control register settings.

It is designed for high-current functions such as LED direct drive. Part 0 pins can also be used as alternative

functions (ADC input, external interrupt input and PWM output).

Two control resisters are used to control Port 0: P0CONH (E6H) and P0CONL (E7H).

You access port 0 directly by writing or reading the corresponding port data register, P0 (E0H).

V

DD

Pull-up

Enable

Pull-up register

(50 kꢋ typical)

V

DD

P0CONH

M

U

X

PWM

In/Out

P0 Data

Output DIsable

(input mode)

D1

D0

Input Data

MUX

Circuit type A

External

Interrupt Input

Noise

Filter

To ADC

Mode

Output

Input

Input Data

NOTE: I/O pins have protection diodes

through VDD and VSS

.

D0

D1

Figure 9-2. Port 0 Circuit Diagram

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Port 0 Control Register (High Byte)

E6H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

[.7-.6] Port, P0.7/ADC7 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = A/D converter input (ADC7); schmitt trigger input off

[.5-.4] Port 0, P0.6/ADC6/PWM Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Alternative function (PWM output)

1 0 = Push-pull output

1 1 = A/D converter input (ADC6); schmitt trigger input off

[.3-.2] Port 0, P0.5/ADC5 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = A/D converter input (ADC5); schmitt trigger input off

[.1-.0] Port 0, P0.4/ADC4 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = A/D converter input (ADC4); schmitt trigger input off

Figure 9-3. Port 0 Control Register (P0CONH, High Byte)

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Port 0 Control Register (Low Byte)

E7H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

[.7-.6] Port 0, P0.3/ADC3 Configuration Bits

0 0 = Schmitt trigger input

0 1 = Schmitt trigger input; pull-up enable

1 0 = Push-pull output

1 1 = A/D converter input (ADC3); Schmitt trigger input off

[.5-.4] Port 0, P0.2/ADC2 Configuration Bits

0 0 = Schmitt trigger input

0 1 = Schmitt trigger input; pull-up enable

1 0 = Push-pull output

1 1 = A/D converter input (ADC2); Schmitt trigger input off

[.3-.2] Port 0, P0.1/ADC1/INT1 Configuration Bits

0 0 = Schmitt trigger input/falling edge interrupt input

0 1 = Schmitt trigger input; pull-up enable/falling edge interrupt inp

1 0 = Push-pull output

1 1 = A/D converter input (ADC1); Schmitt trigger input off

[.1-.0] Port 0, P0.0/ADC0/INT0 Configuration Bits

0 0 = Schmitt trigger input/falling edge interrupt input

0 1 = Schmitt trigger input; pull-up enable/falling edge interrupt inp

1 0 = Push-pull output

1 1 = A/D converter input (ADC0); Schmitt trigger input off

Figure 9-4. Port 0 Control Register (P0CONL, Low Byte)

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Port 0 Interrupt Pending Register

E8H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

[.7-.4] Not used for S3F94C8/F94C4

[.3] Port 0.1/ADC1/INT1, Interrupt Enable Bit

0 = INT1 falling edge interrupt disable

1 = INT1 falling edge interrupt enable

[.2] Port 0.1/ADC1/INT1, Interrupt Pending Bit

0 = No interrupt pending (when read)

0 = Pending bit clear (when write)

1 = Interrupt is pending (when read)

1 = No effect (when write)

[.1] Port 0.0/ADC0/INT0, Interrupt Enable Bit

0 = INT0 falling edge interrupt disable

1 = INT0 falling edge interrupt enable

[.0] Port 0.0/ADC0/INT0, Interrupt Pending Bit

0 = No interrupt pending (when read)

0 = Pending bit clear (when write)

1 = Interrupt is pending (when read)

1 = No effect (when write)

Figure 9-5. Port 0 Interrupt Pending Registers (P0PND)

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PORT 1

Port 1, is a 3-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input

mode, push-pull output mode or n-channel open-drain output mode). In addition, you can configure a pull-up and

pull-down resistor to individual pin using control register settings. It is designed for high-current functions such as

LED direct drive.P1.0, P1.1 are used for oscillator input/output by smart option. Also, P1.2 is used for RESET pin

by smart option (LVR disable ).

NOTE: When P1.2 is configured as a general I/O port, it can be used only for Schmitt trigger input. P1.2 is also

shared with VPP pin for Flash Programming, so it have intrinsic internal pull-down resistor (about 300Kohm),

Please consider about the pull-down resistor when it used as I/O port.

One control register is used to control port 1: P1CON (E9H).You address port 1 bits directly by writing or reading

the port 1 data register, P1 (E1H). When you use external oscillator, P1.0, P1.1 must be set to output port to

prevent current consumption.

VDD

Pull-Up Register

(50 kꢋ typical)

Pull-up

Enable

Open-Drain

V

DD

Smart option

MUX

P1 Data

In/Out

Output DIsable

(input mode)

D1

MUX

Input Data

D0

Circuit type A

XIN, XOUT or RESET

Pull-Down

Enable

Pull-Down Register

(50 kꢋ typical)

Mode

Output

Input

Input Data

NOTE: I/O pins have protection diodes

through VDD and VSS

D0

D1

.

Figure 9-6. Port 1 Circuit Diagram

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Port 1 Control Register

E9H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

[.7] Port 1.1 N-Channel Open-Drain Enable Bit

0 = Configure P1.1 as a push-pull output

1 = Configure P1.1 as a n-channel open-drain output

[.6] Port 1.0 N-Channel Open-Drain Enable Bit

0 = Configure P1.0 as a push-pull output

1 = Configure P1.0 as a N-channel open-drain output

[.5-.4] Not used for S3F94C8/F94C4

[.3-.2] Port 1, P1.1 Configuration Bits

0 0 = Schmitt trigger input;

0 1 = Schmitt trigger input; pull-up enable

1 0 = Push-pull output

1 1 = Schmitt trigger input; pull-down enable

[.1-.0] Port 1, P1.0 Configuration Bits

0 0 = Schmitt trigger input;

0 1 = Schmitt trigger input; pull-up enable

1 0 = Push-pull output

1 1 = Schmitt trigger input; pull-down enable

NOTE:

1.When you use external oscillator, P1.0, P1.1 must be set to

output port to prevent current consumption.

2. when you enable LVR in smart option, P1.2(nRESET/VPP)

can be and can only be used as input port.

Figure 9-7. Port 1 Control Register (P1CON)

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PORT 2

Port 2 is a 7-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input

mode, push-pull output mode or N-channel open-drain output mode). You can also use some pins of port 2 ADC

input, CLO output and T0 clock output. In addition, you can configure a pull-up resistor to individual pins using

control register settings. It is designed for high-current functions such as LED direct drive.

You address port 2 bits directly by writing or reading the port 2 data register, P2 (E2H). The port 2 control register,

P2CONH and P2CONL is located at addresses EAH, EBH respectively.

VDD

Pull-up

Enable

Pull-up register

(50 kꢋ typical)

Open-Drain

V

DD

P2CONH/L

CLO, T0

P0 Data

M

U

X

In/Out

Output DIsable

(input mode)

D1

MUX

Input Data

to ADC

D0

Circuit Type A

NOTE: I/O pins have protection diodes

through VDD and VSS

Mode

Output

Input

Input Data

.

D0

D1

Figure 9-8. Port 2 Circuit Diagram

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Port 2 Control Register (High Byte)

EAH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

[.7] Not sued for S3F94C8/F94C4

[.6-.4] Port 2, P2.6/ADC8/CLO Configuration Bits

0 0 0 = Schmitt trigger input; pull-up enable

0 0 1 = Schmitt trigger input

0 1 x = ADC input

1 0 0 = Push-pull output

1 0 1 = Open-drain output; pull-up enable

1 1 0 = Open-drain output

1 1 1 = Alternative function; CLO output

[.3-.2] Port 2, P2.5 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = Open-drain output

[.1-.0] Port 2, P2.4 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = Open-drain output

NOTE:

When noise problem is important issue, you had better not

use CLO output

Figure 9-9. Port 2 Control Register (P2CONH, High Byte)

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Port 2 Control Register (Low Byte)

EBH, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

[.7-.6] Port 2, P2.3 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = Open-drain output

[.5-.4] Port 2, P2.2 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = Open-drain output

[.3-.2] Port 2, P2.1 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = Open-drain output

[.1-.0] Port 2, P2.0 Configuration Bits

0 0 = Schmitt trigger input; pull-up enable

0 1 = Schmitt trigger input

1 0 = Push-pull output

1 1 = T0 match output

Figure 9-10. Port 2 Control Register (P2CONL, Low Byte)

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NOTES

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10 BASIC TIMER and TIMER 0

MODULE OVERVIEW

The S3F94C8/F94C4 has two default timers: an 8-bit basic timer, one 8-bit general-purpose timer/counter, called

timer 0.

Basic Timer (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer to provide an automatic Reset mechanism in the event of a system malfunction.

— To signal the end of the required oscillation stabilization interval after a Reset or a Stop mode release.

The functional components of the basic timer block are:

— Clock frequency divider (f

divided by 4096, 1024, or 128) with multiplexer

OSC

— 8-bit basic timer counter, BTCNT (DDH, read-only)

— Basic timer control register, BTCON (DCH, read/write)

Timer 0

Timer 0 has the following functional components:

— Clock frequency divider (f

divided by 4096, 256, 8, or f

) with multiplexer

OSC

— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit data register (T0DATA)

— Timer 0 control register (T0CON)

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BASIC TIMER (BT)

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer

counter and frequency dividers, and to enable or disable the watchdog timer function.

A Reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of

/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register

f

OSC

control bits BTCON.7–BTCON.4.

The 8-bit basic timer counter, BTCNT, can be cleared during normal operation by writing a "1" to BTCON.1. To

clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to BTCON.0.

Basic Timer Control Register (BTCON)

DCH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Divider clear bit for basic

timer and timer 0:

0 = No effect

Watchdog timer enable bits:

1010B = Disable watchdog function

Other value = Enable watchdog

function

1 = Clear both dividers

Basic timer counter clear bits:

0 = No effect

1 = Clear basic timer counter

Basic timer input clock selection bits:

00 = fosc/4096

01 = fosc/1024

10 = fosc/128

11 = Invalid selection

NOTE: When you write a 1 to BTCON.0 (or BTCON.1), the basic timer

divider (or basic timer counter) is cleared. The bit is then cleared

automatically to 0.

Figure 10-1. Basic Timer Control Register (BTCON)

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BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a Reset by setting BTCON.7–BTCON.4 to

any value other than "1010B" (The "1010B" value disables the watchdog function). A Reset clears BTCON to

"00H", automatically enabling the watchdog timer function. A Reset also selects the oscillator clock divided by

4096 as the BT clock.

A Reset whenever a basic timer counter overflow occurs. During normal operation, the application program must

prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be

cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation

will not be executed and a basic timer overflow will occur, initiating a Reset. In other words, during normal

operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken

by a BTCNT clear instruction. If a malfunction does occur, a Reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval following a Reset or when

Stop mode has been released by an external interrupt.

In Stop mode, whenever a Reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts

increasing at the rate of f

/4096 (for Reset), or at the rate of the preset clock source (for an external interrupt).

OSC

When BTCNT.7 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the

clock signal off to the CPU so that it can resume normal operation.

In summary, the following events occur when Stop mode is released:

1. During Stop mode, an external power-on Reset or an external interrupt occurs to trigger the Stop mode

release and oscillation starts.

2. If an external power-on Reset occurred, the basic timer counter will increase at the rate of f

/4096. If an

OSC

external interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock

source.

3. Clock oscillation stabilization interval begins and continues until bit 7 of the basic timer counter is set.

4. When a BTCNT.7 is set, normal CPU operation resumes.

Figure 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release

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Oscillation Stabilization Time

Normal Operating mode

0.8 VDD

VDD

Reset Release

Voltage

RESET

trst

~

RC

~

Internal

Reset

0.8 V DD

Release

Oscillator

(X OUT

)

Oscillator Stabilization Time

BTCNT

clock

10000000B

BTCNT

value

00000000B

t

WAIT

= (4096x128)/fOSC

Basic timer increment and

CPU operations are IDLE mode

NOTE: Duration of the oscillator stabilization wait time, t WAIT , when it is released by a

.

Power-on-reset is 4096 x 128/fOSC

RC (R and C are value of external power on Reset)

t

RST

~

Figure 10-2. Oscillation Stabilization Time on RESET

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Normal

Operating

Mode

STOP Mode

Oscillation Stabilization Time

Normal

Operating

Mode

VDD

STOP

Instruction

Execution

STOP Mode

Release Signal

External

Interrupt

RESET

STOP

Release

Signal

Oscillator

(X OUT

)

BTCNT

clock

10000000B

BTCNT

Value

00000000B

t

WAIT

Basic Timer Increment

NOTE: Duration of the oscillator stabilzation wait time, t WAIT , it is released by an

interrupt is determined by the setting in basic timer control register, BTCON.

BTCON.3

BTCON.2

t

WAIT

t

WAIT (When fOSC is 10 MHz)

0

1

0

1

0

1

(4096 x 128)/fosc

(1024 x 128)/fosc

(128 x 128)/fosc

Invalid setting

52.4 ms

13.1 ms

1.63 ms

Figure 10-3. Oscillation Stabilization Time on STOP Mode Release

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145

ꢀ

PROGRAMMING TIP — Configuring the Basic Timer

This example shows how to configure the basic timer to sample specification.

ORG

VECTOR

0000H

00H, INT_94C4

; S3F94C8/F94C4 has only one interrupt vector

;--------------<< Smart Option >>

ORG

DB

003CH

00H

0E7H

03H

; 003CH, must be initialized to 0

; 003DH, must be initialized to 0

; 003EH, enable LVR (2.3 V)

DB

; 003FH, internal RC (3.2 MHz in V = 5 V)

DD

;--------------<< Initialize System and Peripherals >>

ORG

0100H

RESET:

DI

LD

ꢀ

; Disable interrupt

; Select non-divided CPU clock

; Stack pointer must be set

CLKCON, #00011000B

SP, #0C0H

ꢀ

LD

BTCON,#02H

; Enable watchdog function

; Basic timer clock: f

/4096

OSC

; Basic counter (BTCNT) clear

ꢀ

EI

; Enable interrupt

;--------------<< Main loop >>

MAIN:

ꢀ

LD

BTCON, #02H

; Enable watchdog function

; Basic counter (BTCNT) clear

ꢀ

JR

T, MAIN

;

;--------------<< Interrupt Service Routines >>

INT_94C4:

ꢀ

; Interrupt enable bit and pending bit check

ꢀ

;

ꢀ

; Pending bit clear

;

IRET

ꢀ

END

;

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146

TIMER 0

TIMER 0 CONTROL REGISTERS (T0CON)

The timer 0 control register, T0CON, is used to select the timer 0 operating mode (interval timer) and input clock

frequency, to clear the timer 0 counter, and to enable the T0 match interrupt. It also contains a pending bit for T0

match interrupts.

A Reset clears T0CON to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency

of f

/4096, and disables the T0 match interrupts. The T0 counter can be cleared at any time during normal

OSC

operation by writing a "1" to T0CON.3.

Timer 0 Control Register (T0CON)

D2H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 0 input clock selection bits:

00 = fosc/4096

01 = fosc/256

10 = fosc/8

11 = fosc

Timer 0 interrupt pending bit:

0 = No T0 interrupt pending (when read)

0 = Clear T0 pending bit (when write)

1 = Interrupt is pending (when read)

1 = No effect (when write)

Timer 0 interrupt enable bit:

0 = Disable T0 interrupt

1 = Enable T0 interrupt

Not used for S3F94C8/F94C4

Timer 0 counter clear bit:

0 = No effect

1 = Clear the Timer 0 counter (when write)

NOTE: To use T0 match output(P2.0), T0CON.3 must be set to "1".

In this case, there can be same delay in the timer operation

In case time interval is very important, make T0CON.3 "0".

Figure 10-4. Timer 0 Control Registers (T0CON)

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TIMER 0 FUNCTION DESCRIPTION

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the

Timer 0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt (T0INT, vector

00H) and then clears the counter. If, for example, you write the value "10H" to T0DATA, the counter will increment

until it reaches "10H". At this point, the Timer 0 interrupt request is generated; the counter value is reset and

counting resumes.

T0CON.3

Counter (T0CNT)

Comparator

R (clear)

Match

CLK

Timer 0 counter clear

PND

T0INT

Data Register (T0DATA)

T0CON.1

Interrupt Enable/Disable

NOTE:

T0CON.3 is not auto-cleared, you must pay attention when clear pending bit

(refer to P10-12)

Figure 10-5. Simplified Timer 0 Function Diagram (Interval Timer Mode)

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Match MatchMatch

Clear Clear

Compare Value

(T0DATA)

Match Match MatchMatch

Up Counter Value

(T0CNT)

00H

Clear

Count start

T0CON.3

1

T0DATA

Value change

Counter Clear

(T0CON.3)

Interrupt Request

(T0CON.0)

T0 Match Output

(P2.0)

Figure 10-6. Timer 0 Timing Diagram

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Bit 1

RESET or

STOP

Basic Timer Control Register

(Write '1010xxxxB' to disable.)

Bits 3, 2

MUX

Data Bus

MUX

Clear

1/4096

1/1024

1/128

8-Bit Up Counter

(BTCNT, Read-Only)

RESET

OVF

X

IN

DIV

R

When BTCNT.7 is set after

releasing from RESET or STOP

mode, CPU clock starts.

Bit 0

Data Bus

Bits 7, 6

MUX

R

1/4096

1/256

1/8

Clear

Bit 3

Bit 1

Bit 0

T0CNT (D0H)

(Read-Only)

DIV

X

IN

1

Match

8-Bit Comparator

T0DATA Buffer

IRQ0

P2.0

P2CONL.1-.0

Bit 3

Match Signal

T0DATA (D1H)

(Read/Write)

Basic Timer Control Register

Timer 0 Control Register

Data Bus

NOTE:

During a power-on Reset operation, the CPU is idle during the required oscillation stabilization interval

(until bit 7 the basic timer counter is set).

Figure 10-7. Basic Timer and Timer 0 Block Diagram

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ꢀ

PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode)

The following sample program sets Timer 0 to interval timer mode.

ORG

VECTOR

0000H

00H, INT_94C4

; S3F94C8/F94C4 has only one interrupt vector

ORG

DB

003CH

00H

; 003CH, must be initialized to 0

; 003DH, must be initialized to 0

; 003EH, enable LVR (2.3 V)

DB

00H

DB

0E7H

03H

; 003FH, internal RC (3.2 MHz in V = 5 V)

DD

ORG

0100H

RESET:

DI

; Disable interrupt

; Watchdog disable

; Select non-divided CPU clock

; Set stack pointer

;

LD

BTCON,#10100011B

CLKCON,#00011000B

SP,#0C0H

P0CONH,#10101010B

P0CONL,#10101010B

P1CON,#00001010B

P2CONH,#01001010B

P2CONL,#10101010B

; P0.0–0.7 push-pull output

; P1.0–P1.1 push-pull output

;

; P2.0–P2.6 push-pull output

;--------------<< Timer 0 settings >>

LD

T0DATA, #50H

T0CON, #01001010B

; CPU = 3.2 MHz, interrupt interval = 4 msec

; f

/256, Timer 0 interrupt enable

OSC

ꢀ

EI

; Enable interrupt

; Start main loop

;--------------<< Main loop >>

MAIN:

NOP

ꢀ

CALL

LED_DISPLAY

JOB

; Sub-block module

ꢀ

CALL

ꢀ

; Sub-block module

ꢀ

JR

T, MAIN

;

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151

ꢀ

PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode) (Continued)

LED_DISPLAY: NOP

;

ꢀ

RET

JOB:

NOP

;

ꢀ

RET

;--------------<< Interrupt Service Routines >>

INT_94C4:

TM

JR

T0CON,#00000010B

Z,NEXT_CHK1

; Interrupt enable check

;

TM

JP

T0CON, #00000001B

NZ,INT_TIMER0

; If timer 0 interrupt was occurred,

; T0CON.0 bit would be set.

NEXT_CHK1:

INT_TIMER0:

ꢀ

; Interrupt enable bit and pending bit check

ꢀ

;

ꢀ

IRET

; Timer 0 interrupt service routine

ꢀ

AND

IRET

ꢀ

T0CON, #11110110B

;

Pending bit clear

ꢀ

END

;

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152

11 PWM (PULSE WIDTH MODULATION)

OVERVIEW

This microcontroller has the PWM circuit. The PWM can be configured as one of these three resolutions:

— 8bit resolution: 6-bit base + 2-bit extension

— 12bit resolution: 6-bit base + 6-bit extension

— 14bit resolution: 8-bit base + 6-bit extension

These three resolutions are mutually exclusive; only one resolution can work at any time. And which resolution is

used is selected by PWMEX.1-.0.

The operation of all PWM circuit is controlled by a single control register, PWMCON.

The PWM counter is an incrementing counter. It is used by the PWM circuits. To start the counter and enable the

PWM circuits, you set PWMCON.2 to "1". If the counter is stopped, it retains its current count value; when re-

started, it resumes counting from the retained count value. When there is a need to clear the counter you set

PWMCON.3 to "1".

You can select a clock for the PWM counter by set PWMCON.6-.7. Clocks which you can select are f

/64,

OSC

f

/8, f

/2, f

/1.

OSC

FUNCTION DESCRIPTION

PWM

The PWM circuits have the following components:

— PWM mode selection (PWMEX.1-.0)

— Base comparator and extension cycle circuit

— Base reference data registers (PWMDATA, PWMDATA1)

— Extension data registers (PWMEX)

— PWM output pins (P0.6/PWM)

PWM Counter

The PWM counter is an incrementing counter comprised of a lower base counter and an upper extension counter.

To determine the PWM module's base operating frequency, the lower base counter is compared to the PWM

base data register value. In order to achieve higher resolutions, the extension bits of the upper counter can be

used to modulate the "stretch" cycle. To control the "stretching" of the PWM output duty cycle at specific intervals,

the extended counter value is compared with the value that you write to the module's extension bits.

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PWM Data and Extension Registers

PWM (duty) data consist of base data bits and extension data bits; determine the output value generated by the

PWM circuit. For each PWM resolution, the location of base data bits and extension data bits are different

combination of register PWMDATA (F2H), PWMDATA1 (F0H) and PWMEX (F1H):

— 8bit resolution, 6-bit base + 2-bit extension:

Base 6 data bits: PWMDATA.7-.2

Extension 2 bits: PWMDATA.1-.0

— 12bit resolution, 6-bit base + 6-bit extension:

Base 6 data bits: PWMDATA1.5-.0

Extension 6 bits: PWMEX.7-.2

— 14bit resolution, 8-bit base + 6-bit extension:

Base 8 data bits: PWMDATA1.7-.0.

Extension 6 bits: PWMEX.7-.2

BBase 1 (for 12-bit PWM)

.7

.6

.5

.4

.3

.2

.1

.0

LSB

PWMDATA1

F0H, Reset: 00H

Base 2 (for 14-bit PWM)

PWMDATA

F2H, Reset: 00H

.5

.4

.3

.2

.1

Base 0 (for 8-bit PWM)

.6 .5 .4 .3

Ext 1 (for 12/14-bit PWM)

Ext 0 (for 8-bit PWM)

.1 .0 LSB

Base/Ext Control

PWMEX

F1H, Reset: 00H

PWMEX.1-.0 (base/ext control):

‘x0’ = 8-bit resolution: Base 0 (PWMDATA.7-.2) + Ext 0 (PWMDATA.1-.0)

‘01’ = 12-bit resolution: Base 1 (PWMDATA1.5-.0) + Ext 1 (PWMEX.7-.2)

‘11’ = 14-bit resolution: Base 2 (PWMDATA1.7-.0) + Ext 1 (PWMEX.7-.2)

Reset Value = ‘00’(8-bit resolution selected).

Figure 11-1. PWM Data and Extension Registers

To program the required PWM output, you load the appropriate initialization values into the data registers

(PWMDATA) and the extension registers (PWMEX). To start the PWM counter, or to resume counting, you set

PWMCON.2 to "1".

A reset operation disables all PWM output. The current counter value is retained when the counter stops. When

the counter starts, counting resumes at the retained value.

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clock frequency. The PWM counter clock value is

PWM Clock Rate

The timing characteristic of PWM output is based on the f

OSC

determined by the setting of PWMCON.6–.7.

Table 11-1. PWM Control and Data Registers

Register Name

Mnemonic

PWMDATA

PWMDATA1

PWMEX

Address

F2H

Function

PWM data registers

PWM waveform output setting registers.

F0H

F1H

PWM control registers

PWMCON

F3H

PWM counter stop/start (resume), and

OSC

f

clock settings

PWM Function Description

The PWM output signal toggles to Low level whenever the lower base counter matches the reference value

stored in the module's data register (PWMDATA). If the value in the PWMDATA register is not zero, an overflow

of the lower counter causes the PWM output to toggle to High level. In this way, the reference value written to the

data register determines the module's base duty cycle.

The value in the extension counter is compared with the extension settings in the extension data bits. This

extension counter value, together with extension logic and the PWM module's extension bits, is then used to

"stretch" the duty cycle of the PWM output. The "stretch" value is one extra clock period at specific intervals, or

cycles (see Table 11-2).

If, for example, in 8-bit base + 6-bit extension mode, the value in the extension register is '04H', the 32nd cycle

will be one pulse longer than the other 63 cycles. If the base duty cycle is 50 %, the duty of the 32nd cycle will

therefore be "stretched" to approximately 51% duty. For example, if you write 80H to the extension register, all

odd-numbered cycles will be one pulse longer. If you write FCH to the extension register, all cycles will be

stretched by one pulse except the 64th cycle. PWM output goes to an output buffer and then to the corresponding

PWM output pin. In this way, you can obtain high output resolution at high frequencies.

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PWM Output Waveform

— 6-bit base + 2-bit extension mode:

Table 11-2. PWM output "stretch" Values for Extension Data bits Ext0 (PWMDATA.1–.0)

PWMDATA Bit (Bit1–Bit0)

"Stretched" Cycle Number

00

01

10

11

–

2

1, 3

1, 2, 3

0H

40H

80H

PWM

4 MHz

Clock:

000000xxB

250 ns

000001xxB

100000xxB

111111xxB

PWM

Data

Register

Values:

(PWMDATA)

8 us

250 ns

Figure 11-2. PWM Basic Waveform (6-bit base)

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0H

40H

PWM Clock: 4 MHz

000010xxB

500 ns

PWMDATA

: 0000 1001B

Basic Extended

waveform waveform

1st 2nd 3th 4th 1st 2nd 3th 4th

0H

40H

4 MHz

750 ns

Figure 11-3. Extended PWM Waveform (6-bit base + 2-bit extension)

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— 6-bit base + 6-bit extension mode:

Table 11-3. PWM output "stretch" Values for Extension Data bits Ext1 (PWMEX.7-.2)

PWMEX Bit

"Stretched" Cycle Number

7

6

5

4

3

2

1, 3, 5, 7, 9, . . . , 55, 57, 59, 61, 63

2, 6, 10, 14, . . . , 50, 54, 58, 62

4, 12, 20, . . . , 44, 52, 60

8, 24, 40, 56

16, 48

32

0H

4MHz

40H

80H

PWM

Clock:

0H

1H

PWMDATA1

Register

250ns

Values:

20H

3FH

8 μs

250ns

Figure 11-4. PWM Basic Waveform (6-bit base)

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0H

4MHz

40H

PWM

Clock:

PWMDATA1

Register

500ns

2H

Values: 02H

PWMEX

Register

1st

64th 1st

32th

64th

Values:

000100 01B

(Extended

Value is 04H)

32th

40H

0H

4MHz

750ns

Figure 11-5. Extended PWM Waveform (6-bit base + 6-bit extension)

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— 8-bit base + 6-bit extension mode:

Table 11-4. PWM output "stretch" Values for Extension Data bits Ext1 (PWMEX.7-.2)

PWMEX Bit

"Stretched" Cycle Number

7

6

5

4

3

2

1, 3, 5, 7, 9, . . . , 55, 57, 59, 61, 63

2, 6, 10, 14, . . . , 50, 54, 58, 62

4, 12, 20, . . . , 44, 52, 60

8, 24, 40, 56

16, 48

32

0H

4MHz

100H

200H

Cycle

PWM

Clock:

Pulse

0H

1H

PWMDATA1

Register

250ns

Values:

80H

EFH

32 s

250ns

Figure 11-6. PWM Basic Waveform (8-bit base)

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0H

4MHz

100H

PWM

Clock:

PWMDATA1

Register

500ns

2H

Values: 02H

PWMEX

Register

1st

64th 1st

32th

64th

Values:

000100 11B

(Extended

Value is 04H)

32th

100H

0H

4MHz

750ns

Figure 11-7. PWM Basic Waveform (8-bit base + 6-bit extension)

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PWM CONTROL REGISTER (PWMCON)

The control register for the PWM module, PWMCON, is located at register address F3H. PWMCON is used for all

three PWM resolutions. Bit settings in the PWMCON register control the following functions:

— PWM counter clock selection

— PWM data reload interval selection

— PWM counter clear

— PWM counter stop/start (or resume) operation

— PWM counter overflow (upper counter overflow) interrupt control

A reset clears all PWMCON bits to logic zero, disabling the entire PWM module.

PWM Control Registers (PWMCON)

F3H, R/W, Reset: 00H

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

PWM extension counter OVF

Interrupt pending bit:

0 = No interrupt pending

0 = Clear pending condition

(when write)

PWM input clock

selection bits:

00 = fosc/64

01 = fosc/8

10 = fosc/2

11 = fosc/1

1 = Interrupt is pending

PWM counter interrupt enable bit:

0 = Disable PWM OVF interrupt

1 = Enable PWM OVF interrupt

Not Used

PWM counter enable bit:

0 = Stop counter

1 = Start (resume countering)

PWMDATA reload interval selection bit:

0 = Reload from extension up counter

overflow

PWM counter clear bit:

0 = No effect

1 = Reload from base up counter

overflow

1 = Clear the PWM counter (When write)

Note: 1.PWMCON.3 is not auto-cleared. You must pay attention when

clear pending bit. (refer to page 11-12).

2. PWMCON.5 should always be set to ‘0’.

Figure 11-8. PWM Control Register (PWMCON)

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PWM EXTENSION REGISTER (PWMEX)

The extension register for the PWM module, PWMEX, is located at register address F1H. PWMEX are used for

resolution selection and extension bits of 6+6 and 8+6 resolution. Bit settings in the PWMEX register control the

following functions:

— PWM Extension bits for 6+6 resolution and 8+6 resolution mode

— PWM resolution selection.

A reset clears all PWMEX bits to logic zero, choose 6+2 as default resolution, no extension.

PWM Extension Registers (PWMEX)

F1H, R/W, Reset: 00H

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

PWM Extension bits for 6+6

and 8+6 resolution

PWM resolution selection bits:

x0 = 8-bit PWM: 6+2 resolution

10 = 12-bit PWM: 6+6 resolution

11 = 14-bit PWM: 8+6 resolution

Note: Only one resolution mode can work at any time

.

Figure 11-9. PWM Extension Register (PWMEX)

PWMDATA

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Base data for 6+2 resolution

Extension data for 6+2 resolution

Base data for 6+6 resolution

.1

.0

LSB

PWMDATA1

.6

.5

.4

.3

.2

Base data for 8+6 resolution

Figure 11-10. PWM Data Register (PWMDATA)

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fOSC/8 fOSC

fOSC/64 fOSC/2

MUX

PWMCON.6-.7

From extension-bit up counter

extension-bit

From base-bit up counter

base-bit

Counter

PENDING

PWMCON.0

PWMCON.1

Counter

OVFINT

PWMCON.2

"1" When base data > Counter

"0" When base data <= Counter

base-bit

Comparator

P0.6/PWM

"1" When base data = Counter

base-bit Data

Buffer

Extension

Control Logic

base-bit PWM Data

Register (F2H/F0H)

F2H/F0H

PWM Extension

Data Register

F1H

PWMCON.3 (clear)

base or extension up

counter overflow

DATA BUS (7:0)

Figure 11-12. PWM Module Functional Block Diagram

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ꢀ

PROGRAMMING TIP — Programming the PWM Module to Sample Specifications

;--------------<< Interrupt Vector Address >>

VECTOR 00H, INT_94C4

; S3F94C8/F94C4 interrupt vector

;--------------<< Smart Option >>

ORG

DB

003CH

000H

0FFH

000H

; 003CH, must be initialized to 1.

; 003DH, must be initialized to 1.

; 003EH, Enable LVR (2.3)

DB

; 003FH, External Crystal oscillator

;--------------<< Initialize System and Peripherals >>

ORG

0100H

RESET:

DI

LD

ꢀ

; disable interrupt

; Watchdog disable

BTCON,#10100011B

ꢀ

LD

PWMEX,#00000000B

P0CONH,#10011010B

; Configure PWM as 6-bit base +2-bit extension

; Configure P0.6 PWM output

PWMCON,#00000110B ; f

/64, counter/interrupt enable

OSC

AND

LD

ꢀ

PWMEX,#00000011B

PWMDATA,#80H

;

set extension bits as 00( basic output)

ꢀ

EI

; Enable interrupt

;--------------<< Main loop >>

MAIN:

;

ꢀ

JR

t,MAIN

INT_94C4:

; 94C4 interrupt service routine

ꢀ

AND

IRET

ꢀ

PWMCON,#11110110B ; pending bit clear

;

ꢀ

END

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NOTES

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12 A/D CONVERTER

OVERVIEW

The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at

one of the nine input channels to equivalent 10-bit digital values. The analog input level must lie between the V

DD

and V values. The A/D converter has the following components:

SS

— Analog comparator with successive approximation logic

— D/A converter logic

— ADC control register (ADCON)

— Nine multiplexed analog data input pins (ADC0–ADC8)

— 10-bit A/D conversion data output register (ADDATAH/L):

To initiate an analog-to-digital conversion procedure, you write the channel selection data in the A/D converter

control register ADCON to select one of the nine analog input pins (ADCn, n = 0–8) and set the conversion start or

enable bit, ADCON.0. The read-write ADCON register is located at address F7H.

During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the

approximate half-way point of a 10-bit register). This register is then updated automatically during each conversion

step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can

dynamically select different channels by manipulating the channel selection bit value (ADCON.7–4) in the ADCON

register. To start the A/D conversion, you should set a the enable bit, ADCON.0. When a conversion is completed,

ACON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATA

register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of

ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the next

conversion result.

NOTE

Because the ADC does not use sample-and-hold circuitry, it is important that any fluctuations in the analog

level at the ADC0–ADC8 input pins during a conversion procedure be kept to an absolute minimum. Any

change in the input level, perhaps due to circuit noise, will invalidate the result.

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

USING A/D PINS FOR STANDARD DIGITAL INPUT

167

The ADC module's input pins are alternatively used as digital input in port 0 and P2.6.

A/D CONVERTER CONTROL REGISTER (ADCON)

The A/D converter control register, ADCON, is located at address F7H. ADCON has four functions:

— Bits 7-4 select an analog input pin (ADC0–ADC8).

— Bit 3 indicates the status of the A/D conversion.

— Bits 2-1 select a conversion speed.

— Bit 0 starts the A/D conversion.

Only one analog input channel can be selected at a time. You can dynamically select any one of the nine analog

input pins (ADC0–ADC8) by manipulating the 4-bit value for ADCON.7–ADCON.4.

A/D Converter Control Register (ADCON)

F7H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

A/D Conversion input pin selection bits

Conversion start bit:

0 = No effect

1 = A/D conversion start

0000

ADC0 (P0.0)

ADC1 (P0.1)

ADC2 (P0.2)

ADC3 (P0.3)

ADC4 (P0.4)

ADC5 (P0.5)

ADC6 (P0.6)

ADC7 (P0.7)

ADC8 (P2.6)

0001

0010

0011

0100

0101

0110

0111

1000

1001

...

Conversion speed selection bits: ^(note)

00 = fOSC/16 (fOSC < 10 MHz)

01 = fOSC/8 (fOSC < 10 MHz)

10 = fOSC/4 (fOSC < 10 MHz)

11 = fOSC/1 (fOSC < 4 MHz)

Connect to GND internally.

1111

End-of-conversion (EOC) status bit:

0 = A/D conversion is in progress

1 = A/D conversion complete

NOTE:

1. Maximum ADC clock input = 4 MHz

Figure 12-1. A/D Converter Control Register (ADCON)

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

INTERNAL REFERENCE VOLTAGE LEVELS

In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input

168

level must remain within the range V to V

SS

DD.

Different reference voltage levels are generated internally along the resistor tree during the analog conversion

process for each conversion step. The reference voltage level for the first bit conversion is always 1/2 V

DD.

A/D Converter Control Register

ADCON (F7H)

ADCON.0 (ADEN)

ADCON.7-.4

Control

Circuit

Clock

Selector

ADCON.3

(EOC Flag)

M

U

L

ADCON.2-.1

ADC0/P0.0

ADC1/P0.1

ADC2/P0.2

Successive

+

-

Approximation

Circuit

T

I

Analog

Comparator

P

L

E

X

E

R

ADC7/P0.7

ADC8/P2.6

Conversion Result

V

DD

ADDATAH ADDATAL

D/A Converter

(F8H)

(F9H)

V

SS

To data bus

Figure 12-2. A/D Converter Circuit Diagram

MSB

.7

-

.6

-

.5

-

.4

-

.3

-

.2

-

.1

.0

LSB

ADDATAH

ADDATAL

LSB

Figure 12-3. A/D Converter Data Register (ADDATAH/L)

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Product Specification

169

ADCON.0

1

50 ADC Clock

Conversion

Start

EOC

. . .

ADDATA

9

8

7

6

5

4

3

2

1

0

Valid

Data

ADDATAH (8-Bit) + ADDATAL (2-Bit)

40 Clock

Set up

time

10 clock

Figure 12-4. A/D Converter Timing Diagram

CONVERSION TIMING

The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D

conversion. Therefore, total of 50 clocks is required to complete a 10-bit conversion: With a 10 MHz CPU clock

frequency, one clock cycle is 400 ns (4/fxx). If each bit conversion requires 4 clocks, the conversion rate is

calculated as follows:

4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks

50 clock x 400 ns = 20 ꢊs at 10 MHz, 1 clock time = 4/fxx (assuming ADCON.2–.1 = 10)

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

INTERNAL A/D CONVERSION PROCEDURE

1. Analog input must remain between the voltage range of V and V

170

SS

DD.

2. Configure the analog input pins to input mode by making the appropriate settings in P0CONH, P0CONL and

P2CONH registers.

3. Before the conversion operation starts, you must first select one of the nine input pins (ADC0–ADC8) by

writing the appropriate value to the ADCON register.

4. When conversion has been completed, (50 clocks have elapsed), the EOC flag is set to “1”, so that a check

can be made to verify that the conversion was successful.

5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit), and then

the ADC module enters an idle state.

6. The digital conversion result can now be read from the ADDATAH and ADDATAL register.

VDD

XIN

Analog

Input Pin

ADC0-ADC8

XOUT

101

S3F94C8/F94C4

VSS

Figure 12-5. Recommended A/D Converter Circuit for Highest Absolute Accuracy

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171

ꢀ

PROGRAMMING TIP – Configuring A/D Converter

;-----------------<< Interrupt Vector Address >>

VECTOR 00H, INT_TIMER0

;--------------<< Smart Option >>

; S3F94C8/F94C4 has only one interrupt vector

ORG

DB

003CH

000H

0FFH

003H

; 003CH, must be initialized to 0

; 003DH, must be initialized to 0

; 003EH, enable LVR

DB

; 003FH, internal RC oscillator

ORG

DI

LD

ꢀ

0100H

RESET:

; disable interrupt

; Watchdog disable

BTCON,#10100011B

ꢀ

LD

EI

P0CONH,#11111111B

P0CONL,#11111111B

P2CONH,#00100000B

; Configure P0.4–P0.7 AD input

; Configure P0.0–P0.3 AD input

; Configure P2.6 AD input

; Enable interrupt

;--------------<< Main loop >>

MAIN:

ꢀ

CALL

ꢀ

AD_CONV

; Subroutine for AD conversion

ꢀ

JR

t, MAIN

;

AD_CONV:

LD

ADCON, #00000001B

; Select analog input channel ꢈ P0.0

; select conversion speed ꢈ f

/16

OSC

; set conversion start bit

NOP

; If you select conversion speed to f

/16

OSC

; at least one NOP must be included

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Product Specification

172

ꢀ

PROGRAMMING TIP – Configuring A/D Converter (Continued)

CONV_LOOP: TM

ADCON,#00001000B

Z,CONV_LOOP

R0,ADDATAH

; Check EOC flag

JR

LD

; If EOC flag=0, jump to CONV_LOOP until EOC flag=1

; High 8 bits of conversion result are stored

; to ADDATAH register

LD

R1,ADDATAL

; Low 2 bits of conversion result are stored

; to ADDATAL register

; Select analog input channel ꢈ P0.1

ADCON,#00010011B

; Select conversion speed ꢈ f

/8

OSC

; Set conversion start bit

CONV_LOOP2:TM

ADCON,#00001000B

Z,CONV_LOOP2

R2,ADDATAH

; Check EOC flag

JR

LD

ꢀ

R3,ADDATAL

ꢀ

RET

;

INT_TIMER0:

ꢀ

;

ꢀ

; Pending bit clear

;

IRET

ꢀ

END

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

NOTES

173

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Product Specification

174

13 EMBEDDED FLASH MEMROY INTERFACE

OVERVIEW

The S3F94C8/F94C4 has an on-chip flash memory internally instead of masked ROM. The flash memory is

accessed by instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the

data in a flash memory area any time you want. The S3F94C8/F94C04‘s embedded 8K/4K-byte memory has two

operating features as below:

— Tool Program Mode: Refer to the chapter 16. S3F94C8/F94C4 FLASH MCU

— User Program Mode

Flash ROM Configuration

The S3F94C8/F94C4 flash memory consists of 64 sectors (S3F94C8) or 32sectors (S3F94C4). Each sector

consists of 128bytes. So, the total size of flash memory is 64 x128 (8KB) or 32x128 bytes (4KB). User can erase

the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time.

— 8K/ 4Kbyte Internal flash memory

— Sector size: 128-Bytes

— 10years data retention

— Fast programming Time:

Sector Erase: 8ms (min)

Byte Program: 25us (min)

— Byte programmable

— User programmable by ‘LDC’ instruction

— Sector (128-Bytes) erase available

— Endurance: 10,000 Erase/Program cycles (min)

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Product Specification

Tool Program Mode

175

This mode is for erasing and programming full area of flash memory by external programming tools. The 5 pins of

S3F94C8/F94C4 are connected to a programming tool and then internal flash memory of S3F94C8/F94C4 can be

programmed by Serial OTP/MTP Tools, SPW2 plus single programmer or GW-PRO2 gang programmer and so

on. The other modules except flash memory module are at a reset state. This mode doesn’t support the sector

erase but chip erase (all flash memory erased at a time) and two protection modes (Hard lock protection/ Read

protection). The read protection mode is available only in tool program mode. So in order to make a chip into read

protection, you need to select a read protection option when you write a program code to a chip in tool program

mode by using a programming tool. After read protect, all data of flash memory read “00”. This protection is

released by chip erase execution in the tool program mode.

Table 13-1. Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode

Main Chip

Pin Name

During Programming

I/O

Pin Name

Pin No.

Function

P0.1

SDAT

18 (20-pin)

14 (16-pin)

I/O

Serial data pin (output when reading, Input

when writing) Input and push-pull output port

can be assigned

P0.0

SCLK

19 (20-pin)

15 (16-pin)

I

Serial clock pin (input only pin)

V

RESET/P1.2

4

Power supply pin for Tool mode entering

(indicates that MTP enters into the Tool

mode). When 11 V is applied, MTP is in Tool

mode.

PP

V

/V

V

/V

20 (20-pin), 16 (16-pin)

1 (20-pin), 1 (16-pin)

I

Logic power supply pin.

DD SS

User Program Mode

This mode supports sector erase, byte programming, byte read and one protection mode (Hard Lock Protection).

The S3F94C8/F94C4 has the internal pumping circuit to generate high voltage. To program a flash memory in this

mode several control registers will be used.

There are four kind functions in user program mode – programming, reading, sector erase, and one protection

mode (Hard lock protection).

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Product Specification

FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE)

176

FLASH MEMORY CONTROL REGISTER (FMCON)

FMCON register is available only in user program mode to select the flash memory operation mode; sector erase,

byte programming, and to make the flash memory into a hard lock protection.

Flash Memory Control Register (FMCON)

ECH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash (Erase or Hard Lock Protection)

Operation Start Bit

Flash Memory Mode Selection Bits

0101: Programming mode

1010: Erase mode

0110: Hard lock mode

others: Not used for S3F94C8/F94C4

0 = Operation stop

1 = Operation start

(This bit will be cleared automatically just

after erase operation.)

Not used for S3F94C8/F94C4.

Figure 13-1. Flash Memory Control Register (FMCON)

The bit 0 of FMCON register (FMCON.0) is a bit for the operation start of Erase and Hard Lock Protection.

Therefore, operation of Erase and Hard Lock Protection is activated when you set FMCON.0 to “1”. If you write

FMCON.0 to 1 for erasing, CPU is stopped automatically for erasing time (min.4ms). After erasing time, CPU is

restarted automatically. When you read or program a byte data from or into flash memory, this bit is not needed to

manipulate.

FLASH MEMORY USER PROGRAMMING ENABLE REGISTER (FMUSR)

The FMUSR register is used for a safe operation of the flash memory. This register will protect undesired erase or

program operation from malfunctioning of CPU caused by an electrical noise. After reset, the user-programming

mode is disabled, because the value of FMUSR is “00000000B” by reset operation. If necessary to operate the

flash memory, you can use the user programming mode by setting the value of FMUSR to “10100101B”. The

other value of “10100101B”, user program mode is disabled.

Flash Memory User Programming Enable Register (FMUSR)

EDH, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash Memory User Programming Enable Bits

10100101: Enable user programming mode

Other values: Disable user programming mode

Figure 13-2. Flash Memory User Programming Enable Register (FMUSR)

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Product Specification

FLASH MEMORY SECTOR ADDRESS REGISTERS

177

There are two sector address registers for the erase or programming flash memory. The FMSECL (Flash Memory

Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Address

Sector Register High Byte) indicates the high byte of sector address. The FMSECH is needed for S3F94C8/F94C4

because it has 64/32 sectors.

One sector consists of 128-bytes. Each sector’s address starts XX00H or XX80H, that is, a base address of sector

is XX00H or XX80H. So bit .6-.0 of FMSECL don’t mean whether the value is ‘1’ or ‘0’. We recommend that it is

the simplest way to load the sector base address into FMSECH and FMSECL register. When programming the

flash memory, user should program after loading a sector base address, which is located in the destination

address to write data into FMSECH and FMSECL register. If the next operation is also to write one byte data, user

should check whether next destination address is located in the same sector or not. In case of other sectors, user

should load sector address to FMSECH and FMSECL Register according to the sector. (Refer to page 13-12

PROGRAMMING TIP — Programming)

Flash Memory Sector Address Register (FMSECH)

EEH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash Memory Sector Address(High Byte)

NOTE:

The High- Byte flash memory sector address pointer value is the

higher eight bits of the 16-bit pointer address.

Figure 13-3. Flash Memory Sector Address Register (FMSECH)

Flash Memory Sector Address Register (FMSECL)

EFH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Don't Care

Flash Memory Sector Address(Low Byte)

NOTE:

The Low- Byte flash memory sector address pointer value is the

lower eight bits of the 16-bit pointer address.

Figure 13-4. Flash Memory Sector Address Register (FMSECL)

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Product Specification

SECTOR ERASE

178

User can erase a flash memory partially by using sector erase function only in user program mode. The only unit

of flash memory to be erased in the user program mode is a sector.

The program memory of S3F94C8/F94C4 8K/4Kbytes flash memory is divided into 64/32 sectors. Every sector

has all 128-byte sizes. So the sector to be located destination address should be erased first to program a new

data (one byte) into flash memory. Minimum 4ms’ delay time for the erase is required after setting sector address

and triggering erase start bit (FMCON.0). Sector erase is not supported in tool program modes (MDS mode tool or

programming tool).

(S3F94C8)

1FFFH

1F7FH

Sector 63

(128 byte)

Sector 32

(128 byte)

(S3F94C4)

0FFFH

0F7FH

Sector 31

(128 byte)

007FH

0000H

Sector 0

(128 byte)

Figure 13-5. Sector Configurations in User Program Mode

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P R E L I M I N A R Y

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Product Specification

The Sector Erase Procedure in User Program Mode

179

1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.

2. Set Flash Memory Sector Address Register (FMSECH and FMSECL).

3. Set Flash Memory Control Register (FMCON) to “10100001B”.

4. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.

Start

FMUSR

#0A5H

; User Programimg Mode Enable

FMSECH

FMSECL

High Address of Sector

Low Address of Sector

; Set Sector Base Address

FMCON

FMUSR

#10100001B

#00H

; Mode Select & Start Erase

; User Prgramming Mode Disable

Finish One Sector Erase

Figure 13-6. Sector Erase Flowchart in User Program Mode

NOTES

1. If user erases a sector selected by Flash Memory Sector Address Register FMSECH and FMSECL,

FMUSR should be enabled just before starting sector erase operation. And to erase a sector, Flash

Operation Start Bit of FMCON register is written from operation stop ‘0’ to operation start ‘1’. That bit

will be cleared automatically just after the corresponding operation completed. In other words, when

S3F94C8/F94C4 is in the condition that flash memory user programming enable bits is enabled and

executes start operation of sector erase, it will get the result of erasing selected sector as user’s a

purpose and Flash Operation Start Bit of FMCON register is also clear automatically.

2. If user executes sector erase operation with FMUSR disabled, FMCON.0 bit, Flash Operation Start

Bit, remains 'high', which means start operation, and is not cleared even though next instruction is

executed. So user should be careful to set FMUSR when executing sector erase, for no effect on

other flash sectors.

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P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

180

ꢀ

PROGRAMMING TIP — Sector Erase

Case1. Erase one sector

ꢀ

ERASE_ONESECTOR:

LD

FMUSR,#0A5H

FMSECH,#04H

FMSECL,#00H

; User program mode enable

; Set sector address 0400H, sector 8,

; among sector 0~32

LD

FMCON,#10100001B ; Select erase mode enable & Start sector erase

ERASE_STOP:

LD

FMUSR,#00H ; User program mode disable

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P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

PROGRAMMING

181

A flash memory is programmed in one-byte unit after sector erase. The write operation of programming starts by

‘LDC’ instruction.

The program procedure in user program mode

1. Must erase target sectors before programming.

2. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.

3. Set Flash Memory Control Register (FMCON) to “0101000XB”.

4. Set Flash Memory Sector Address Register (FMSECH and FMSECL) to the sector base address of

destination address to write data.

5. Load a transmission data into a working register.

6. Load a flash memory upper address into upper register of pair working register.

7. Load a flash memory lower address into lower register of pair working register.

8. Load transmission data to flash memory location area on ‘LDC’ instruction by indirectly addressing mode

9. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.

NOTE

In programming mode, it doesn’t care whether FMCON.0’s value is “0” or “1”.

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182

Start

FMSECH

FMSECL

High Address of Sector

Low Address of Sector

; Set Secotr Base Address

R(n)

R(n+1)

R(data)

High Address to Write

Low Address to Write

8-bit Data

; Set Address and Data

FMUSR

#0A5H

#01010000B

@RR(n),R(data)

#00H

; User Program Mode Enable

; Mode Select

FMCON

LDC

; Write data at flash

FMUSR

; User Program Mode Disable

Finish 1-BYTE Writing

Figure 13-7. Byte Program Flowchart in a User Program Mode

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Product Specification

183

Start

; Set Secotr Base Address

; Set Address and Data

FMSECH

FMSECL

High Address of Sector

Low Address of Sector

R(n)

R(n+1)

R(data)

High Address to Write

Low Address to Write

8-bit Data

FMUSR

FMCON

#0A5H

; User Program Mode Enable

#01010000B

; Mode Select

; Write data at flash

LDC

@RR(n),R(data)

; User Program Mode Disable

YES

Write again?

NO

#00H

NO

FMUSR

; User Program Mode Disable

;; Check Sector

Same Sector?

YES

Finish Writing

NO

Continuous address?

;; Check Address

;; Increse Address

YES

INC R(n+1)

YES

Different Data?

;; Update Data to Write

R(data)

New 8-bit Data

NO

Figure 13-8. Program Flowchart in a User Program Mode

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Product Specification

184

ꢀ

PROGRAMMING TIP — Programming

Case1. 1-Byte Programming

ꢀ

WR_BYTE:

; Write data “AAH” to destination address 0310H

; User program mode enable

LD

FMUSR,#0A5H

FMCON,#01010000B ; Selection programming mode

FMSECH, #03H

FMSECL, #00H

R9,#0AAH

; Set the base address of sector (0300H)

; Load data “AA” to write

R10,#03H

; Load flash memory upper address into upper register of pair working

; register

LD

R11,#10H

; Load flash memory lower address into lower register of pair working

; register

LDC

LD

@RR10,R9

FMUSR,#00H

; Write data 'AAH' at flash memory location (0310H)

; User program mode disable

Case2. Programming in the same sector

ꢀ

WR_INSECTOR:

; RR10-->Address copy (R10 –high address,R11-low address)

LD

R0,#40H

LD

FMUSR,#0A5H

; User program mode enable

FMCON,#01010000B ; Selection programming mode and Start programming

FMSECH,#06H

FMSECL,#00H

R9,#33H

; Set the base address of sector located in target address to write data

; The sector 12’s base address is 0600H.

; Load data “33H” to write

; Load flash memory upper address into upper register of pair working

; register

; Load flash memory lower address into lower register of pair working

; register

R10,#06H

LD

R11,#00H

WR_BYTE:

LDC

@RR10,R9

; Write data '33H' at flash memory location

INC

R11

; Reset address in the same sector by INC instruction

DEC

ꢀꢀJP

R0

ꢀꢀꢀꢀNZୈWR_BYTE

; Check whether the end address for programming reach 0640H or not.

; User Program mode disable

LD

FMUSR,#00H

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S3F94C8/S3F94C4

Product Specification

Case3. Programming to the flash memory space located in other sectors

185

ꢀ

WR_INSECTOR2:

LD

R0,#40H

R1,#40H

LD

FMUSR,#0A5H

; User program mode enable

LD ꢀꢀꢀꢀꢀꢀꢀFMCON,#01010000B ; Selection programming mode and Start programming

LD

FMSECH,#01H

FMSECL,#00H

R9,#0CCH

; Set the base address of sector located in target address to write data

; The sector 2’s base address is 100H

; Load data “CCH” to write

; Load flash memory upper address into upper register of pair working

; register

; Load flash memory lower address into lower register of pair working

; register

R10,#01H

LD

R11,#40H

WR_BYTE

R0,#40H

CALL

LD

WR_INSECTOR5:

LD

FMSECH,#02H

; Set the base address of sector located in target address to write data

; The sector 5’s base address is 0280H

; Load data “55H” to write

; Load flash memory upper address into upper register of pair working

; register

; Load flash memory lower address into lower register of pair working

; register

FMSECL,#80H

R9,# 55H

R10,#02H

LD

R11,#90H

WR_BYTE

CALL

WR_INSECTOR12:

LD

FMSECH,#06H

; Set the base address of sector located in target address to write data

; The sector 12’s base address is 0600H

; Load data “A3H” to write

; Load flash memory upper address into upper register of pair working

; register

; Load flash memory lower address into lower register of pair working

; register

FMSECL,#00H

R9,#0A3H

R10,#06H

LD

R11,#40H

WR_BYTE1:

LDC

@RR10,R9

R11

; Write data 'A3H' at flash memory location

INC

DEC

R1

JP

NZ, WR_BYTE1

FMUSR,#00H

LD

; User Program mode disable

ꢀ

WR_BYTE:

LDC

INC

@RR10,R9

R11

; Write data written by R9 at flash memory location

DEC

JP

RET

R0

NZ, WR_BYTE

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P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

READING

186

The read operation starts by ‘LDC’ instruction.

The program procedure in user program mode

1. Load a flash memory upper address into upper register of pair working register.

2. Load a flash memory lower address into lower register of pair working register.

3. Load receive data from flash memory location area on ‘LDC’ instruction by indirectly addressing mode

ꢀ

PROGRAMMING TIP — Reading

ꢀ

LD

R2,#03H

R3,#00H

; Load flash memory’s upper address

; to upper register of pair working register

; Load flash memory’s lower address

; to lower register of pair working register

LD

LOOP:

LDC

R0,@RR2

; Read data from flash memory location

; (Between 300H and 3FFH)

INC

R3

CP

JP

ꢀ

R3,#0FFH

NZ,LOOP

ꢀ

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P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

HARD LOCK PROTECTION

187

User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This function prevents the changes of data in

a flash memory area. If this function is enabled, the user cannot write or erase the data in a flash memory area.

This protection can be released by the chip erase execution in the tool program mode. In terms of user program

mode, the procedure of setting Hard Lock Protection is following that. In tool mode, the manufacturer of serial tool

writer could support Hardware Protection. Please refer to the manual of serial program writer tool provided by the

manufacturer.

The program procedure in user program mode

1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.

2. Set Flash Memory Control Register (FMCON) to “01100001B”.

3. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.

ꢀ



ꢀ

LD

FMUSR,#0A5H

FMCON,#01100001B

FMUSR,#00H

; User program mode enable

; Select Hard Lock Mode and Start protection

; User program mode disable

ꢀ

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P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

NOTES

188

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Product Specification

189

14 ELECTRICAL DATA

OVERVIEW

In this section, the following S3F94C8/F94C4 electrical characteristics are presented in tables and graphs:

— Absolute maximum ratings

— D.C. electrical characteristics

— A.C. electrical characteristics

— Input timing measurement points

— Oscillator characteristics

— Oscillation stabilization time

— Operating voltage range

— Schmitt trigger input characteristics

— Data retention supply voltage in stop mode

— Stop mode release timing when initiated by a RESET

— A/D converter electrical characteristics

— LVR circuit characteristics

— LVR reset timing

— Full-Flash memory characteristics

— ESD Characteristics

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190

Table 14-1. Absolute Maximum Ratings

(T = 25 ꢂC)

A

Parameter

Symbol

Conditions

Rating

Unit

V

Supply voltage

Input voltage

–

– 0.3 to + 6.5

V

DD

V

– 0.3 to V + 0.3

All ports

V

I

O

DD

V

– 0.3 to V + 0.3

Output voltage

Output current high

All output ports

DD

I

One I/O pin active

– 25

mA

OH

All I/O pins active

One I/O pin active

– 80

I

Output current low

+ 30

mA

OL

All I/O pins active

+ 100

T

Operating temperature

Storage temperature

–

– 40 to + 85

ꢂC

A

T

–

– 65 to + 150

STG

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191

Table 14-2. DC Electrical Characteristics

(T = – 40 ꢂC to + 85 ꢂC, V

= 1.8 V to 5.5 V)

A

DD

Parameter

Symbol

Conditions

Min

Typ

–

Max

5.5

Unit

f_main=0.4 – 4 MHz

f_main=0.4 – 10 MHz

1.8

2.7

Operating

Voltage

V

DD

–

5.5

V

= 2.7 V to 5.5V

= 1.8 V to 2.7V

Main crystal or

ceramic

0.4

–

10

4

DD

f_main

MHz

V

frequency

V

0.8 V

V

Input high

voltage

Ports 0,1, 2 and

RESET

–

IH1

DD

V

= 1.8 to 5.5 V

DD

V

X

and X

V

- 0.1

IH2

IN

OUT

DD

V

0.2 V

Input low

voltage

Ports 0, 1, 2 and

RESET

–

V

IL1

DD

V

X

and X

0.1

IL2

IN

OUT

I

= – 10 mA

Ports 0,2,P1.0-P1.1

V

= 4.5 to 5.5 V

V

-1.5

V

- 0.4

Output high

voltage

–

V

OH

DD

V

I

= 25 mA

Ports 0,2,P1.0-P1.1

Output low

voltage

–

0.4

2.0

1

OL

DD

V

= V

Input high

leakage current

All input except

–

uA

LIH1

IN

DD

2

I

LIH2,P1.2

I

X

V

20

LIH2

IN

DD

I

= 0 V

Input low

leakage current

All input except

–

–1

uA

LIL1

IN

I

LIL2

I

X

V

= 0 V

= V

–20

LIL2

IN

I

Output high

leakage current

All output pins

–

2

uA

LOH

OUT

DD

I

V

= 0 V

= 5 V

Output low

leakage current

–

–2

uA

LOL

OUT

R

V

= 0 V,

Pull-up resistors

25

50

100

kꢋ

P1

IN

DD

Ports 0, 2, P1.0-P1.1 T =25ꢂC

A

R

V

= 0 V,

V

= 5 V

Pull-down

resistors

25

50

100

P2

IN

DD

P1.0-P1.1

T =25ꢂC

A

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192

Supply current¹

Run mode

–

2

5

mA

I

V

= 4.5 to 5.5 V

DD1

DD2

DD3

DD

10 MHz CPU clock

V

= 2.0V

3MHz CPU clock

1

2

DD

= 4.5 to 5.5 V

Idle mode

10 MHz CPU clock

1.5

3.0

DD

V

= 2.0V

3MHz CPU clock

Stop mode

0.5

0.3

1.5

2.0

DD

–

uA

= 4.5 to 5.5 V

DD

(LVR disable)

= 25 ꢂC

T

A

1

4.0

V

= 4.5 to 5.5 V

DD

(LVR disable)

T = – 40ꢂC to

A

+85ꢂC

–

40

30

80

60

V

= 4.5 to 5.5 V

DD

(LVR enable)

T = – 40ꢂC to

A

+85ꢂC

V

= 2.6 V

DD

(LVR enable)

T = – 40ꢂC to

A

+85ꢂC

NOTE: 1. Supply current does not include current drawn through internal pull-up resistors or external output

current loads and ADC module.

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S3F94C8/S3F94C4

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193

Table 14-3. AC Electrical Characteristics

(T = – 40 ꢂC to + 85 ꢂC, V

= 1.8 V to 5.5 V)

A

DD

Parameter

Symbol

Conditions

INT0, INT1

Min

Typ

Max

Unit

t

Interrupt input

high, low width

–

200

–

ns

INTH

V

= 5 V ꢌ 10 %

t

DD

INTL

t

RESET input

low width

1

–

us

Input

DD

RSL

V

= 5 V ꢌ 10 %

t

INTL

tINTH

0.8 VDD

0.2 VDD

XIN

Figure 14-1. Input Timing Measurement Points

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P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

194

Table 14-4. Crystal or Ceramic Oscillator Characteristics

(T = – 40ꢂC to + 85 ꢂC)

A

Oscillator

Clock Circuit

Test Condition

Min

Typ

Max

Unit

V

= 2.7 to 5.5 V

Main crystal or

ceramic

0.4

–

10

MHz

X

IN

DD

C1

C2

¹= 1.8 to 2.7 V

= 2.7 to 5.5 V

XOUT

V

0.4

–

4

MHz

DD

External clock

(Main System)

10

DD

XIN

V

= 1.8 to 2.7 V

0.4

–

4

MHz

DD

XOUT

NOTE: 1. Please refer to the figure of Operating Voltage Range.

Table 14-5. Oscillation Stabilization Time

°

(T = - 40 C to + 85 C, V

A

= 1.8 V to 5.5 V)

DD

Oscillator

Test Condition

Min

–

Typ

Max

20

Unit

ms

f

> 1.0 MHz

Main crystal

–

OSC

Main ceramic

–

10

ms

Oscillation stabilization occurs when V is equal

DD

to the minimum oscillator voltage range.

X

input high and low width (t , t )

External clock

(main system)

25

–

500

ns

IN

XH XL

2¹⁹/f

(1)

Oscillator

stabilization

wait time

–

ms

t

when released by a reset

OSC

WAIT

(2)

–

t

when released by an interrupt

NOTES:

1.

f

is the oscillator frequency.

OSC

t

2. The duration of the oscillator stabilization wait time,

settings in the basic timer control register, BTCON.

, when it is released by an interrupt is determined by the

WAIT

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Product Specification

195

Table 14-6. RC Oscillator Characteristics ( S3F94C8EZZ / F94C4EZZ )

(T = – 25 ꢂC to + 85 ꢂC, V = 1.8 V to 5.5 V)

A

DD

Oscillator

Clock Circuit

Test Condition

= 5 V

Min

Typ

Max

Unit

V

External RC

oscillator

–

4

–

MHz

DD

Internal RC

oscillator

–

3.2

–

500

–

KHz

%

V

= 5.0 V

Tolerance of

Internal RC

–

f3

DD

T = 25 ꢂC

A

V

= 5.0 V

–

f5

f8

%

DD

T = – 25ꢂC to + 85 ꢂC

A

V

= 2.0 to 5.5 V

DD

T = – 25ꢂC to + 85 ꢂC

A

Table 14-7 RC Oscillator Characteristics ( S3F94C8XZZ / F94C4XZZ )

(T = – 40 ꢂC to + 85 ꢂC, V = 1.8 V to 5.5 V)

A

DD

Oscillator

Clock Circuit

Test Condition

= 5 V

Min

Typ

Max

Unit

V

External RC

oscillator

–

4

–

MHz

DD

Internal RC

oscillator

–

3.2

–

MHz

–

500

–

KHz

%

V

= 1.8 to 5.0 V

Tolerance of

Internal RC

f0.5

f1

DD

TA = 25 ꢂC

= 1.8 to 5.5 V

V

–

f3.5

%

DD

T = – 40ꢂC to + 85 ꢂC

A

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Product Specification

196

CPU Clock

10 MHz

8 MHz

4 MHz

3 MHz

2 MHz

1 MHz

0.4 MHz

2.7

1

1.8

4 4.5 5 5.5 6

7

Supply Voltage (V)

Figure 14-2. Operating Voltage Range

VOUT

VDD

A = 0.2 VDD

B = 0.4 VDD

C = 0.6 VDD

D = 0.8 VDD

VSS

A

B

C

D

VIN

0.3 VDD

0.7 VDD

Figure 14-3. Schmitt Trigger Input Characteristics Diagram

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Product Specification

197

Table 14-8. Data Retention Supply Voltage in Stop Mode

(T = – 40 ꢂC to + 85 ꢂC, V = 1.8 V to 5.5 V)

A

DD

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V

Data retention supply

voltage

Stop mode

1.0

–

5.5

V

DDDR

I

Stop mode; V

= 2.0 V

Data retention supply

current

–

1

uA

DDDR

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

RESET

Occurs

Oscillator

Stabilization

Time

Stop

Mode

Data Retention

Mode

VDD

Normal

Operating

Mode

VDDDR

Execution Of

Stop Instrction

RESET

t

WAIT

_WAITis the same as 4096 x 128 x 1/f

t

NOTE:

OSC

Figure 14-4. Stop Mode Release Timing When Initiated by a RESET

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S3F94C8/S3F94C4

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198

Table 14-9. A/D Converter Electrical Characteristics

= 1.8 V to 5.5 V, V = 0 V)

(T = – 40 ꢂC to + 85 ꢂC, V

A

DD

SS

Parameter

Resolution

Symbol

Test Conditions

Min

–

Typ

Max

Unit

10

–

bit

V

= 5.12 V

(1)

Total accuracy

–

LSB

DD

ꢌ3

CPU clock = 10 MHz

V

= 0 V

SS

ILE

ꢍ

–

LSB

Integral linearity

error

–

ꢌ 2

ꢌ 1

DLE

–

Differential linearity

error

LSB

ꢊs

ꢌ 1

ꢌ 3

Offset error of top

EOT

EOB

ꢍ

–

Offset error of

bottom

t

Conversion

ꢍ

–

20

–

CON

(2)

time

V

Analog input

voltage

–

V

IAN

SS

DD

R

Analog input

impedance

2

–

1000

–

Mꢋ

ꢊA

AN

I

V

= 5 V

Analog input

current

10

1.5

ADIN

DD

I

Analog block

0.5

mA

DD

ADC

(3)

current

V

= 3 V

= 5 V

0.15

100

0.45

500

mA

nA

DD

power down mode

NOTES:

1. The total accuracy is 3LSB(max.) at V

= 2.7V – 5.5V, It’s for design guidance only and are not tested in production.

DD

2. “Conversion time” is the time required from the moment a conversion operation starts until it ends.

3. is operating current during A/D conversion.

I

ADC

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Product Specification

199

Table 14-10. LVR Circuit Characteristics

(T = – 40 ꢂC to + 85 ꢂC, V

A

= 1.8 V to 5.5 V)

DD

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

1.8

2.1

2.8

3.4

3.7

1.9

2.3

3.0

3.6

3.9

2.0

2.5

3.2

3.8

4.1

V

Low voltage reset

–

V

LVR

VDD

VLVR,MAX

VLVR

V

LVR,MIN

Figure 14-5. LVR Reset Timing

Table 14-11. Flash Memory AC Electrical Characteristics

ꢂ

(T = – 40 C to + 85 C at V = 1.8 V to 5.5 V)

A

DD

Parameter

Symbol

Fewrv

Ftp

Conditions

Min

1.8

20

Typ

5.0

–

Max

Unit

V

Flash Erase/Write/Read Voltage

Programming time(1)

V_DD

5.5

30

70

12

–

uS

Chip Erasing time (2)

Ftp1

32

–

mS

nS

Sector Erasing time (3)

Data Access Time

Ftp2

4

–

Ft_RS

V_DD= 2.0V

–

250

–

Number of writing/erasing

FNwe

–

10,000

–

Times

Data Retention

Ftdr

–

10

–

Years

Notes:

1. The programming time is the time during which one byte (8-bit) is programmed.

2. The Chip erasing time is the time during which entire program memory is erased.

3. The Sector erasing time is the time during which all 128byte block is erased.

4. The chip erasing is available in Tool Program Mode only.

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P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

200

104

VDD

VSS

S3F94C8/F94C4

Figure 14-6. The Circuit Diagram to Improve EFT Characteristics

NOTE: To improve EFT characteristics, we recommend using power capacitor near S3F94C8/F94C4 like Figure 14-6.

Table 14-12. ESD Characteristics

Parameter

Symbol

Conditions

HBM

Min

2000

200

Typ.

ꢎꢄ

Max

ꢎꢄ

Unit

V

Electrostatic discharge

ESD

MM

ꢎꢄ

V

CDM

500

ꢎꢄ

V

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S3F94C8/S3F94C4

Product Specification

201

NOTES

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Product Specification

202

15 MECHANICAL DATA

OVERVIEW

The S3F94C8/F94C4 is available in a 20-pin DIP package (Samsung: 20-DIP-300A), a 20-pin SOP package

(Samsung: 20-SOP-375), a 20-pin SSOP package (Samsung: 20-SSOP-225), a 16-pin SOP package (Samsung:

16-SOP-225) and a 16-pin TSSOP package(Samsung:16-TSSOP-0044). Package dimensions are shown in

Figure 15-1, 15-2, 15-3, 15-4, 15-5 and 15-6.

#20

#11

#10

0-15

20-DIP-300A

0

1

.

+ 0

0.05

-

25

0.

#1

26.80 MAX

26.40ꢄꢌ 0.20

0.46

ꢄ

ꢌ

ꢄ

0.10

2.54

(1.77)

1.52

ꢄ

NOTE : Dimensions are in millimeters.

Figure 15-1. 20-DIP-300A Package Dimensions

PS031501-0813

P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

203

0-8

#20

#11

20-SOP-375

0.203⁺- 0⁰.^.0¹5⁰

#1

#10

13.14 MAX

12.74ꢄꢌꢄ0.20

0.10 MAX

1.27

(0.66)

0.40⁺- 0⁰.^.105⁰

NOTE : Dimensionsare in millimeters.

Figure 15-2. 20-SOP-375 Package Dimensions

PS031501-0813

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Product Specification

204

0-8

#20

#11

20-SSOP-225

0.15 ⁺- ⁰0.^.0¹5⁰

#1

#10

6.90 MAX

6.50 ^ꢌꢄ0.20

0.10 MAX

(0.30)

0.65

+0.10

0.22 -0.05

NOTE: Dimensions are in millimeters.

Figure 15-3. 20-SSOP-225 Package Dimensions

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P R E L I M I N A R Y

S3F94C8/S3F94C4

Product Specification

205

10.10

9.70

0-8

#16

#9

0.10

0.05

16-SOP-225

0.30

0.15

#1

#8

0.9

0.5

0.70

0.65

x8⁰

1.65

1.45

1.27BSC

0.50

0.35

NOTE: Dimensions are in millimeters.

Figure 15-4. 16-SOP-225 Package Dimensions

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Product Specification

206

#16

#9

0.95

0.85

16-TSSOP-0044

#1

#8

0.25

5.10

4.90

0.10 MAX

0.65BSC

0.30

0.19

NOTE: Dimensions are in millimeters.

Figure 15-5. 16-TSSOP-0044 Package Dimensions

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Product Specification

207

16 S3F94C8/F94C4 FLASH MCU

OVERVIEW

The S3F94C8/F94C4 single-chip CMOS microcontroller is the Flash MCU. It has an on-chip Flash MCU ROM of

8K/4K bytes. The Flash ROM is accessed by serial data format.

The serial data is transformed by two pins of the chip: SCLK and SDAT, SCLK is the synchronize signal, and the

Flash Programmer Tool send data from the SDAT pin. The corresponding ports of SCLK and SDAT in

S3F94C8/F94C4 are P0.0 and P1.1. And there also need power supply for chip to work and higher power for

entering flash tool mode. So the VDD, VSS of chip must be connected to power and ground. The higher power

supply for the Flash operation is named as VPP port, the corresponding pin in S3F94C8/F94C4 is nRESET (P1.2)

pin. The detail description of the pin functions are listed in the table 16-1.The pin assignments of the

S3F94C8/F94C4 package types are shown in below figures.

NOTE

1. This chapter is about the Tool Program Mode of Flash MCU. If you want to know the User

Program Mode, refer to the chapter 13. Embedded Flash Memory Interface.

2. In S3F94C8/F94C4, there only 5 pins are used as flash operation pins, the nRESET pin is

used as VPP input and without TEST pin that different with other Samsung MCU products.

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Product Specification

208

V

SS

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VDD

X

IN/P1.0

P0.0/ADC0/INT0/SSCLK

P0.1/ADC1/INT1/SSDAT

P0.2/ADC2

X

OUT/P1.1

V

PP/nRESET/P1.2

T0/P2.0

P2.1

P0.3/ADC3

S3F94C8/F94C4

P0.4/ADC4

(20-DIP-300A/

20-SOP-375)

P2.2

P0.5/ADC5

P2.3

P0.6/ADC6/PWM

P0.7/ADC7

P2.4

P2.5

P2.6/ADC8/CLO

NOTE:

The bolds indicate MTP pin name.

Figure 16-1. S3F94C8/F94C4 Pin Assignments (20-DIP/20SOP)

V

SS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDD

X

IN/P1.0

P0.0/ADC0/INT0/SSCLK

P0.1/ADC1/INT1/SSDAT

P0.2/ADC2

X

OUT/P1.1

S3F94C8/F94C4

V

PP/nRESET/P1.2

T0/P2.0

P2.1

P0.3/ADC3

(16-SOP-225)

P0.4/ADC4

P2.2

P0.5/ADC5

P2.3

P0.6/ADC6/PWM

NOTE:

The bolds indicate MTP pin name.

Figure 16-2. S3F94C8/F94C4 Pin Assignments (16SOP)

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Table 16-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip

Pin Name

During Programming

I/O

Pin Name

Pin No.

Function

P0.1

SDAT

18 (20-pin)

14 (16-pin)

I/O

Serial data pin (output when reading, Input

when writing) Input and push-pull output port

can be assigned

P0.0

SCLK

19 (20-pin)

15 (16-pin)

I

Serial clock pin (input only pin)

V

RESET/P1.2

4

Power supply pin for Tool mode entering

(indicates that MTP enters into the Tool

mode). When 11 V is applied, MTP is in Tool

mode.

PP

V

/V

V

/V

20 (20-pin), 16 (16-pin)

1 (20-pin), 1 (16-pin)

I

Logic power supply pin.

DD SS

NOTES: Parentheses indicate pin number for 20-DIP-300A package.

Table 16-2. Comparison of S3F94C8/F94C4 Features

Characteristic

S3F94C8/F94C4

8K/4K-byte Flash ROM

2.0 V to 5.5 V

= 5.0 V, V (nRESET) = 11 V

Program memory

Operating voltage (V

)

DD

V

Flash MCU programming mode

DD

PP

Pin configuration

Programmability

20 DIP/20 SOP/20 SSOP /16SOP/16TSSOP

User program multi time

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ON BOARD WRITING

The S3F94C8/F94C4 needs only 5 signal lines including VDD and GND pins for writing internal flash memory with

serial protocol. Therefore the on-board writing is possible if the writing signal lines are considered when the PCB of

application board is designed.

Circuit design guide

At the flash writing, the writing tool needs 5 signal lines that are GND, VDD, VPP, SDAT and SCLK. When you

design the PCB circuits, you should consider the usage of these signal lines for the on-board writing.

In case of VPP (nRESET) pin, for the purpose of increase the noise effect, a capacitor should be inserted between

the VPP pin and GND.

Please be careful to design the related circuit of these signal pins because rising/falling timing of VPP, SCLK and

SDAT is very important for proper programming.

Applicatio

n

R

SCL

SDA

To

SCLK (I/O)

SDAT(I/O)

circuit

Applicatio

n

circuit

Applicatio

n

Vpp

To

(

)

nRESET

CVpp

C

RESET

circuit

VDD

Vpp

SDA

V

SS

C

Vpp are used to improve

SCL

Vdd

GND

the noise effect

SPW-uni , GW-uni , AS-pro, US-pro

Figure 16-3. PCB design guide for on board programming

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Table 16-3. Reference Table for Connection

Pin Name

I/O mode

Resistor

(need)

Required value

in Applications

Input

Vpp(nRESET)

SDAT(I/O)

Yes

C_Vppis 0.01uF ~ 0.02uF.

Input

R_SDATis 2 Kohm ~ 5 Kohm.

Output

Input

No(Note)

Yes

-

R_SCLKis 2 Kohm ~ 5 Kohm.

-

SCLK(I/O)

Output

No(Note)

NOTE1: In on-board writing mode, very high-speed signal will be provided to pin SCLK and SDAT. And it will

cause some damages to the application circuits connected to SCLK or SDAT port if the application circuit

is designed as high speed response such as relay control circuit. If possible, the I/O configuration of

SDAT, SCLK pins had better be set to input mode.

NOTE2: The value of R, C in this table is recommended value. It varies with circuit of system.

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INFORMATION BLOCK

The S3F94C8/94C4 provides a special flash area for storing chip ID or customer’s information into it, called

information block. This block is separated from the main flash ROM, the flash ROM memory erase/write/read/read

protection operation take none affect to this block. It can be erase/write/read by Flash Programmer Tools

individually and is not available in user mode.

The size of information block is 256Bytes. Since it is separated from flash ROM, the programming operation (chip

erase/write) will not erase/change the data in information block. User can write Chip ID into it, that different for

each chip, to distinguish every chip. This is very useful for anti-imitation by storing production related information in

this area.

Main Flash ROM

8.191

(S3F94C8)

Tool :

-Erase/write/read

-Hard lock

-Read protection

4.095

(S3F94C4)

User :

Information Block

-Erase/write/read

-Hard lock

255

(S3F94C8/C4)

Tool :

-Erase/write/read

0

Figure 16-4. S3F94C8/F94C4 Flash Architecture.

Table 16-4. Operation Results Comparison of Main ROM and Information Block

Mode

Operation

Erase MTP

Main Flash ROM Information Block

Tool Mode

Yes

No

Program ROM / Read ROM

Hard Lock / Read Protection

Information Block Erase

Information Block Write/Read

Sector erase

No

Yes

No

User Mode

Yes

Write Byte /Read Byte

Hard Lock

No

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NOTES

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17 DEVELOPMENT TOOLS

OVERVIEW

Samsung provide a powerful and ease-to-use development support system on a turnkey basis. The development

support system is composed of a host system, debugging tools, and supporting software. For a host system, any

standard computer that employs Win95/98/2000/XP as its operating system can be used. A sophisticated

debugging tool is provided both in hardware and software: the powerful in-circuit emulator, OPENice-i500/i2000

and SK-1200, for the S3F7-, S3F9-and S3F8- microcontroller families. Samsung also offers supporting software

that includes, debugger, an assembler, and a program for setting options.

TARGET BOARDS

Target boards are available for all the S3C9/S3F9-series microcontrollers. All the required target system cables

and adapters are included on the device-specific target board. TB94C8/94C4 is a specific target board for the

development of application systems using S3F94C8/F94C4.

PROGRAMMING SOCKET ADAPTER

When you program S3F94C8/F94C4’s flash memory by using an emulator or OTP/MTP writer, you need a specific

programming socket adapter for S3F94C8/F94C4.

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[Development System Configuration]

IBM-PC AT or Compatible

Emulator [ SK-1200(RS-232,USB) or OPENIce I-500(RS-232) or

RS-232C / USB

OPENIce I-2000(RS-232,USB)]

Target

Application

System

OTP/MTP Writer Block

RAM Break/Display Block

Trace/Timer Block

Probe

Adapter

TB94C8/94C4

Target

POD

SAM8 Base Block

Board

EVA

Chip

Power Supply Block

Figure 17-1. Development System Configuration

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TB94C8/94C4 TARGET BOARD

The TB94C8/94C4 target board is used for the S3F94C8/F94C4 microcontrollers. The TB94C8/94C4 target board

is operated as target CPU with Emulator (OPENIce I-500/2000, SK-1200).

TB94C8/94C4

To User_VCC

Stop

+

Idle

+

Off

On

JP5

RESET

SW1

J5

1

20

25

128 QFP

S3E94C0

EVA Chip

38

1

10

11

U1

Target System

Interface

1

S1

Emulator

Interfalce

PWM

Enable

ON

0

Board Clock

Main Mode

EVA Mode

JP1

Y1

Internal Clock

PWM

Disable

SMDS2

SMDS2+

JP4

Figure 17-2. TB94C8/94C4 Target Board Configuration

NOTE: TB94C8/94C4 should be supplied 5V normally. So the power supply from Emulator should be set 5V for the target

board operation.

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Table 17-1. Components of TB94C8/94C4

Symbols

Usage

100-pin connector

20-pin connector

8-pin switch

Description

S1

J5

Connection between emulator and TB94C8/94C4 target board.

Connection between target board and user application system

Smart Option setting for S3F94C8/94C4 EVA-chip

SW2

RESET

VCC, GND

Push button

Generation low active reset signal to S3F94C8/94C4 EVA-chip

External power connector for TB94C8/94C4

POWER connector

IDLE, STOP LED STOP/IDLE Display

Indicate the status of STOP or IDLE of S3F94C8/94C4 EVA-

chip on TB94C8/94C4 target board

JP1

JP2

JP3

JP4

JP5

Clock Source Selection

MODE Selection

Selection of SMDS2/SMDS2+ internal /external clock

Selection of Eva/Main-chip mode of S3F94C8/94C4 EVA-chip

Selection of PWM enable/disable

PWM selection

Emulator selection

User’s Power selection

Selection of SMDS2/SMDS2+

Selection of Power to User.

Table 17-2. Power Selection Settings for TB94C8/94C4

Operating Mode

"To User_Vcc" Settings

Comments

The SMDS2/SMDS2+ main

To user_Vcc

board supplies V to the

CC

External

TB94C8/94C4

off

on

Target

System

target board (evaluation chip)

and the target system.

VCC

VSS

VCC

SMDS2/SMDS2+

The SMDS2/SMDS2+ main

To user_Vcc

board supplies V only to the

CC

External

TB94C8/94C4

off

on

Target

System

target board (evaluation chip).

The target system must have

its own power supply.

VCC

VSS

VCC

SMDS2/SMDS2+

NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration:

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SMDS2+ Selection (SAM8)

In order to write data into program memory that is available in SMDS2+, the target board should be selected to be

for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.

Table 17-3. The SMDS2+ Tool Selection Setting

"JP4" Setting

Operating Mode

SMDS2 SMDS2+

R/W*

SMDS2+

R/W*

Target

System

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Table 17-4. Using Single Header Pins to Select Clock Source / PWM / Operation Mode

Target Board Part

Comments

Board CLK

JP1

Clock Source

Use SMDS2/SMDS2+ internal clock source as the system clock.

Default Setting

Inner CLK

Board CLK

JP1

Clock Source

Use external crystal or ceramic oscillator as the system clock.

Inner CLK

PWM Enable

JP3

PWM function is DISABLED.

PWM Disable

PWM Enable

JP3

PWM function is ENABLED.

Default Setting

PWM Disable

Main Mode

The S3E94C0 run in main mode, just same as S3F94C8/F94C4.

The debug interface is not available.

JP2

EVA Mode

Main Mode

JP2

The S3E94C0 run in EVA mode, available. When debug program,

please set the jumper in this mode.

Default Setting

EVA Mode

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Table 17-5. Using Single Header Pins as the Input Path for External Trigger Sources

Target Board Part

Comments

Connector from

External

Triggers

External Trigger

Sources of the

Application System

Ch1(TP3)

Ch2(TP4)

You can connect an external trigger source to one of the two

external trigger channels (CH1 or CH2) for the SK-1000/SMDS2+

breakpoint and trace functions.

0

ON

SW2

OFF

ON

OFF

Low

High (Default)

NOTE:

1. For EVA chip, smart option is determined by DIP switch not software.

2. Please keep the reserved bits as default value (high).

Figure 17-3. DIP Switch for Smart Option

ꢀ

IDLE LED

This is LED is ON when the evaluation chip (S3E94C0) is in idle mode.

STOP LED

This LED is ON when the evaluation chip (S3E94C0) is in stop mode.

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221

J5

V

SS

1

20

19

18

17

16

15

14

13

12

11

VDD

P1.0

P1.1

2

P0.0/ADC0/INT0

P0.1/ADC1/INT1

P0.2/ADC2

3

RESET/P1.2

T0/P2.0

P2.1

4

5

P0.3/ADC3

6

P0.4/ADC4

P2.2

7

P0.5/ADC5

P2.3

8

P0.6/ADC6/PWM

P0.7/ADC7

P2.4

9

P2.5

10

P2.6/ADC8/CLO

Figure 17-4. 20-Pin Connector for TB94C8/94C4

Target Board

Target System

1 20

J101

20

1

Target Cable for 20-Pin Connector

10 11

Figure 17-5. S3F94C8/F94C4 Probe Adapter for 20-DIP Package

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THIRD PARTIES FOR DEVELOPMENT TOOLS

SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience

in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-circuit

emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an

OTP/MTP programmer.

In-Circuit Emulator for SAM8 family

ꢀ

OPENice-i500/2000

SmartKit SK-1200

OTP/MTP Programmer

ꢀ

SPW-uni

GW-uni (8 - gang programmer)

AS-pro

Development Tools Suppliers

Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting

development tools.

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8-bit In-Circuit Emulator

OPENice - i500

AIJI System

ꢀ TEL: 82-31-223-6611

ꢀ FAX: 82-331-223-6613

ꢀ E-mail : openice@aijisystem.com

stroh@yicsystem.com

ꢀ URL : http://www.aijisystem.com

OPENice - i2000

AIJI System

ꢀ TEL: 82-31-223-6611

ꢀ FAX: 82-331-223-6613

ꢀ E-mail : openice@aijisystem.com

stroh@yicsystem.com

ꢀ URL : http://www.aijisystem.com

SK-1200

Seminix

ꢀ TEL: 82-2-539-7891

ꢀ FAX: 82-2-539-7819

ꢀ E-mail: sales@seminix.com

ꢀ URL: http://www.seminix.com

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OTP/MTP PROGRAMMER (WRITER)

SEMINIX

SPW-uni

ꢀ TEL: 82-2-539-7891

ꢀ FAX: 82-2-539-7819.

ꢀ E-mail:

Single OTP/ MTP/FLASH Programmer

ꢀ Download/Upload and data edit function

ꢀ PC-based operation with USB port

ꢀ Full function regarding OTP/MTP/FLASH MCU

programmer

sales@seminix.com

ꢀ URL:

http://www.seminix.com

(Read, Program, Verify, Blank, Protection..)

ꢀ Fast programming speed (4Kbyte/sec)

ꢀ Support all of SAMSUNG OTP/MTP/FLASH MCU

devices

ꢀ Low-cost

ꢀ NOR Flash memory (SST,Samsung…)

ꢀ NAND Flash memory (SLC)

ꢀ New devices will be supported just by adding

device files or upgrading the software.

SEMINIX

GW-uni

ꢀ TEL: 82-2-539-7891

ꢀ FAX: 82-2-539-7819.

ꢀ E-mail:

Gang Programmer for OTP/MTP/FLASH MCU

ꢀ 8 devices programming at one time

ꢀ Fast programming speed :OTP(2Kbps) /

MTP (10Kbps)

ꢀ Maximum buffer memory:100Mbyte

ꢀ Operation mode: PC base / Stand-alone(no PC)

ꢀ Support full functions of OTP/MTP

(Read, Program, Checksum, Verify, Erase, Read

protection, Smart option)

sales@seminix.com

ꢀ URL:

http://www.seminix.com

ꢀ Simple GUI(Graphical User Interface)

ꢀ Device information setting by a device part no.

ꢀ LCD display and touch key (Stand-alone mode

operation)

ꢀ System upgradable (Simple firmware upgrade by

user)

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225

OTP/MTP PROGRAMMER (WRITER) (Continued)

SEMINIX

AS-pro

ꢀ TEL: 82-2-539-7891

ꢀ FAX: 82-2-539-7819.

ꢀ E-mail:

On-board programmer for Samsung Flash MCU

ꢀ Portable & Stand alone Samsung

OTP/MTP/FLASH Programmer for After Service

ꢀ Small size and Light for the portable use

ꢀ Support all of SAMSUNG OTP/MTP/FLASH

devices

sales@seminix.com

ꢀ URL:

http://www.seminix.com

ꢀ HEX file download via USB port from PC

ꢀ Very fast program and verify time

( OTP:2Kbytes per second, MTP:10Kbytes per

second)

ꢀ Internal large buffer memory (118M Bytes)

ꢀ Driver software run under various O/S

(Windows 95/98/2000/XP)

ꢀ Full function regarding OTP/MTP programmer

(Read, Program, Verify, Blank, Protection..)

ꢀ Two kind of Power Supplies

(User system power or USB power adapter)

ꢀ Support Firmware upgrade

C&A technology

Flash writing adapter board

ꢀ TEL: 82-2-2612-9027

ꢀ FAX: 82-2-2612-9044

ꢀ E-mail:

ꢀ Special flash writing socket for S3F94C8/F94C4

- 20DIP,20SOP,20SSOP,16DIP,16SOP,16TSSOP

wisdom@cnatech.com

ꢀ URL:

http://www.cnatech.com

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NOTES

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型号：	S3F94C8EZZ/F94C4EZZ
厂家：	ZILOG, INC.
描述：	S3 Family 8-Bit Microcontrollers 微控制器
文件：	总229页 (文件大小：1143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3F94C8EZZ/F94C4EZZ [ZILOG]

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