Z16M17 [ZILOG]
PCMCIA Interface Solution; PCMCIA接口方案
| 型号： | Z16M17 |
| 厂家： | 
ZILOG, INC. |
| 描述： | PCMCIA Interface Solution |
| 文件： | 总138页 (文件大小：1062K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z86017/Z16017
PCMCIA Interface Solution
Product Specification
PS012002-1201
ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
Z86017/Z16017 PCMCIA Interface Solution
Reference Manual
This publication is subject to replacement by a later edition. To determine whether a later edition
exists, or to request copies of publications, contact
ZiLOG Worldwide Headquarters
910 E. Hamilton Avenue
Campbell, CA 95008
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Windows is a registered trademark of Microsoft Corporation.
Document Disclaimer
© 2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property
rights.
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
iii
Preface
Thank you for your interest in Zilog’s PCMCIA interface solution. This
Reference Manual describes the programming and operation of the
Z86017 and Z16017 PCMCIA adapter chips.
This Reference Manual is organized in the following way:
•
PCMCIA Interface Overview
This chapter is an introductory section that provides an overview of
the architecture of the device.
•
Addressing Modes
This chapter describes the addressing modes supported by the
Z86017/Z16017 architecture to ensure PCMCIA compatibility.
•
•
Programming Internal Registers
This chapter describes the serial interface modes.
Configuration Registers
This chapter describes the functions of the Z86017/Z16017 internal
registers.
•
•
Appendix A
This appendix gives an overview of the Z86017/Z16017
multifunction pins.
Appendix B
This appendix provides Absolute Maximum Ratings, DC Electrical
Characteristics, and Timing Specifications related to the Z86017/
Z1601.
•
Appendix C
This appendix provides various Z86017/Z16017 timing diagrams.
Preface
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
iv
•
•
Appendix D
This appendix provides part numbers and ordering information.
Appendix E
This appendix provides a description of the Z8601700ZCO PCMCIA
Interface Development Kit.
PS012002-1201
Preface
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
v
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
PCMCIA Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pin Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PCMCIA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Peripheral or ATA/IDE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Peripheral Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Programming Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
EEPROM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Word-to-Byte Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PS012002-1201
Table of Contents
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
vi
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Appendix A: Multifunction Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Overview of Multifunction Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Appendix B: Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . . . .93
internal attribute memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
017 Device Slew Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Appendix C: Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Appendix D: Packaging and Ordering Information . . . . . . . . . . . . . . . . . . .117
20 Mhz PCMCIA Adapter Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Appendix E: PCMCIA Interface Development Kit . . . . . . . . . . . . . . . . . . . .121
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Z86017 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Power Requirements: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ZPCMCIA0ZDP PCMCIA Extender Card . . . . . . . . . . . . . . . . . 122
PS012002-1201
Table of Contents
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
vii
List of Figures
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
PCMCIA Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1. ZX6017 Functional Block Diagram . . . . . . . . . . . . . . . . . . .3
Figure 2. Serial Port Master Mode Control . . . . . . . . . . . . . . . . . . . . .5
Figure 3. Serial Port Slave Mode Control . . . . . . . . . . . . . . . . . . . . . .7
Figure 4. EEPROM Programming Through the PCMCIA
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5. Connection Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 6. Serial Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 7. Attribute and Configuration Memory Diagram . . . . . . . . .11
Figure 8. ZX6017 100-Pin VQFP Pin Configuration . . . . . . . . . . . . .12
Figure 9. Z86M17 and Z16M17 (Mirror Image) 100-Pin VQFP
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Programming Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 10. Word-to-Byte Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 11. Word-to-Byte Mode Data Path . . . . . . . . . . . . . . . . . . . . . .77
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PS012002-1201
List of Figures
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
viii
Appendix A: Multifunction Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Figure 12. Z16017BA PC_RDY/BSY/IREQ/HINT Pin . . . . . . . . . . . 87
Figure 13. Z86017BA PC_WP//IOIS16//IOIS16 Pin . . . . . . . . . . . . . 88
Figure 14. Z16017BA PC_WP//IOIS16//IOIS16 Pin . . . . . . . . . . . . . 89
Figure 15. Z86017BA (Overview of Internal Structure) . . . . . . . . . . 90
Figure 16. Z16017BA (Overview of Internal Structure) . . . . . . . . . . 91
Appendix B: Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . . . .93
Figure 17. PCMCIA Read Memory Timing, No Wait States . . . . . . . 97
Figure 18. PCMCIA Read Memory Timing, Wait State Enabled . . . 98
Figure 19. PCMCIA Write Memory Timing, No Wait States . . . . . 101
Figure 20. PCMCIA Write Memory Timing, Wait State Enabled . . 102
Figure 21. I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 22. I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 23. Skew Timing Between PCMCIA and ATA/IDE or
Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 24. 017 Slew Delay Derating Curve (Typical) . . . . . . . . . . . 108
Figure 25. FMaster Mode Read EEPROM Timing . . . . . . . . . . . . . 110
Figure 26. Slave Interface Timing (Read) . . . . . . . . . . . . . . . . . . . . 111
Appendix C: Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Figure 27. Z16017BA Reset Timing PCMCIA Mode . . . . . . . . . . . 113
Figure 28. PCMCIA ATA/IDE 16-Bit I/O Write
(Register 24 = 01, Internal IOIS 16 is selected) . . . . . . . 114
Figure 29. PCMCIA ATA / IDE 8-Bit Long Read
(Reading 512-byte data plus 6-byte ECC) . . . . . . . . . . . . 115
Appendix D: Packaging and Ordering Information . . . . . . . . . . . . . . . . . . .117
Figure 30. Example Package Name . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 31. 100-Lead VQFP Package Diagram . . . . . . . . . . . . . . . . . 119
PS012002-1201
List of Figures
Z86017/Z16017 PCMCIA INterface Solution
Product Specification
ix
Appendix E: PCMCIA Interface Development Kit . . . . . . . . . . . . . . . . . . . .121
List of Figures
PS012001-0901
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
x
PS012002-1201
List of Figures
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
xi
List of Tables
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
PCMCIA Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1.
Table 2.
Table 3.
Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
100-Pin VQFP Pin Identification . . . . . . . . . . . . . . . . . . . .14
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 4.
Table 5.
ZX6017 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . .27
Programming PCMCIA_ATA ZX6017 Configuration Regis-
ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 6.
Table 7.
Table 8.
Table 9.
PCMCIA Common Memory Mode . . . . . . . . . . . . . . . . . .30
PCMCIA I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PCMCIA_ATA Memory Mapped Access . . . . . . . . . . . . .31
PCMCIA_ATA I/O Mapped Access . . . . . . . . . . . . . . . . .32
Programming Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 10. ZX6017 Card Configuration Registers . . . . . . . . . . . . . . . .33
Table 11. Interface Configuration Register: Address 00h . . . . . . . . .36
Table 12. Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 13. Interrupt Enable Register: Address 01h . . . . . . . . . . . . . . .39
PS012002-1201
List of Tables
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
xii
Table 14. Interface Configuration Register 1: Address 02h . . . . . . . 41
Table 15. PCMCIA PDIAG Pin Functions . . . . . . . . . . . . . . . . . . . . 42
Table 16. PCMCIA DASP Pin Functions . . . . . . . . . . . . . . . . . . . . . 43
Table 17. Host Chip Select Designations . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Audio Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 19. Interface Configuration Register 2: Address 03h . . . . . . . 45
Table 20. Interface Configuration Register 3: Address 04h . . . . . . . 46
Table 21. ATA Register Selection Designations . . . . . . . . . . . . . . . . 47
Table 22. Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 23. PCMCIA CCR Base Address Register: Address 05h . . . . 48
Table 24. CCR Location Examples, Register 5 . . . . . . . . . . . . . . . . . 49
Table 25. PCMCIA Interrupt Status Register: Address 06h . . . . . . . 50
Table 26. PCMCIA Exception Status Register: Address 07h . . . . . . 51
Table 27. ATA Sample Mode Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 28. Attribute Memory Address Register: Address 08h . . . . . . 52
Table 29. Attribute Memory Data Register: Address 09h . . . . . . . . . 53
Table 30. Window 1 Control Register: Address 10h . . . . . . . . . . . . . 54
Table 31. Window 1 Start Address LSB: Address 11h . . . . . . . . . . . 55
Table 32. Window 1 Start/Range Address MSB: Address 12h . . . . . 55
Table 33. Window 1 Range Address LSB: Address 13h . . . . . . . . . . 56
Table 34. Window 2 Control Register: Address 14h . . . . . . . . . . . . . 56
Table 35. Window 2 Start Address LSB: Address 15h . . . . . . . . . . . 57
Table 36. Window 2 Start/Range Address MSB: Address 16h . . . . . 58
Table 37. Window 2 Range Address LSB: Address 17h . . . . . . . . . . 58
Table 38. Window 3 Control Register: Address 18h . . . . . . . . . . . . . 59
Table 39. Window 3 Start Address LSB: Address 19h . . . . . . . . . . . 60
Table 40. Window 3 Start/Range Address MSB: Address 1Ah . . . . 60
Table 41. Window 3 Range Address LSB: Address 1Bh . . . . . . . . . 61
PS012002-1201
List of Tables
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
xiii
Table 42. EEPROM Valid flag Byte Register: Address 1Eh . . . . . . .61
Table 43. EEPROM Address/Status CCR5 Back Door: Address 20h 61
Table 44. EEPROM Data CCR6 Back Door: Address 21h . . . . . . . .62
Table 45. EEPROM Command CCR7 Back Door: Address 22h . . . .62
Table 46. Revision Control Register: Address 23h . . . . . . . . . . . . . . .63
Table 47. Revision Number Register: Address 24h . . . . . . . . . . . . . .63
Table 48. Bus Control 1 Register: Address 26h . . . . . . . . . . . . . . . . .64
Table 49. IOIS16 Address Control Register: Address 27h . . . . . . . . .66
Table 50. 16-Bit_Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 51. 8-Bit _CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 52. Power Management Timer Count Value: Address 2Ah . . .68
Table 53. Power Management control Register: Address 2Bh . . . . . .69
Table 54. Interface Configuration Register 4: Address 2Ch . . . . . . . .70
Table 55. Power Management Clock Select . . . . . . . . . . . . . . . . . . . .71
Table 56. Configuration Index Compare Register 1: Address 2Dh . .72
Table 57. Configuration Index Compare Register 2: Address 2Eh . .72
Table 58. Bus Control Register: Address 2Fh . . . . . . . . . . . . . . . . . .74
Table 59. Strobe Width and Access Delay . . . . . . . . . . . . . . . . . . . . .75
Table 60. PCMICA Host Read and Write Address Examples, . . . . . .78
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 61. PCMCIA Address xx0h to xx8h, Configuration Register De-
code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 62. ZiLOG EEPROM Programming Extensions . . . . . . . . . . .80
Table 63. PCMCIA Configuration Option Register
CCR0: Address 0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 64. PCMCIA Card Status Register CCR1: Address 0Bh . . . . .81
Table 65. PCMCIA Pin Replacement Register CCR2: Address 0Ch .82
Table 66. PCMCIA socket and Copy Register CCR3: Address 0Dh .83
List of Tables
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xiv
Table 67. PCMCIA I/O Event Indication CCR4: Address 1Fh . . . . . 84
Appendix A: Multifunction Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Appendix B: Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . . . .93
Table 68. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . 93
Table 69. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 94
Table 70. Internal Attribute Memory Timing . . . . . . . . . . . . . . . . . . 96
Table 71. PCMCIA Memory Write Timing . . . . . . . . . . . . . . . . . . . 99
Table 72. I/O Read Timing Specification . . . . . . . . . . . . . . . . . . . . 103
Table 73. I/O Write Timing Specification . . . . . . . . . . . . . . . . . . . . 105
Table 74. Skew Timing Between PCMCIA And ATA/IDE or
Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 75. Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Appendix C: Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Appendix D: Packaging and Ordering Information . . . . . . . . . . . . . . . . . . .117
Appendix E: PCMCIA Interface Development Kit . . . . . . . . . . . . . . . . . . . .121
PS012002-1201
List of Tables
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
1
PCMCIA Interface Overview
FEATURES
Table 1. Device Features
Device
RAM (Bytes)
Speed
Package
Z86017
256
256
256
256
20
20
20
20
100-Pin VQFP
100-Pin VQFP
100-Pin VQFP
100-Pin VQFP
Z86M171
Z16017
Z16M171
NOTES:
1.Mirror Image Bond-Out Options
•
•
PCMCIA Configuration Registers
Sequencer for programming attribute memory using EEPROM
content, MASTER mode
•
Serial Peripheral Interface (SPI) circuitry allows control through the
local microprocessor, SLAVE mode
•
•
•
•
•
•
•
•
PCMCIA to I/O peripheral
PCMCIA to ATA/IDE translation
ATA/IDE to ATA/IDE mapping, PASSHROUGH mode
Operates from a 3.0V to 5.5V power supply
Conforms to PCMCIA standards
Low power dissipation
Mirror image bond-out option (Z86M17/Z16M17)
On-chip generation of IOIS16 in I/O mode (Z16017)
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
2
General Description
The Z86017/Z16017 (ZX6017) are general-purpose PCMCIA adapter
chips used on the card side of the interface. For increased versatility,
“mirror image” bond-out versions, the Z86M17 and Z16M17, are also
available. These chips are easily configured to allow access to all types of
memory or I/O-mapping peripherals, such as Ethernet controllers,
Universal Asynchronous Receiver/Transmitters (UART), modems,
rotating disk memory, and so on. The ZX6017 can be used in a stand-
alone configuration without the use of a local processor when all
necessary data for Attribute Memory, Card Configuration Registers
(CCR), Memory/I/O maps, and so on, are being provided by a local serial
EEPROM. The serial EEPROM is read automatically using an internal
EEPROM sequencer. The ZX6017 can also be configured by a local
microprocessor, when one is being used on the card.
Throughout this document, references to the ZX6017 device applies
equally to the Z86017 and Z16017, unless otherwise specified.
Note:
All Signals with an overline ( ) are active Low, that is, B/W
(WORD is active Low); B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Table 2. Power Connections
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
The ZX6017 can be programmed by one of two ways: an external 256
byte serial EEPROM can be connected to the serial port interface, or a
microprocessor can be connected to this port to provide a higher level of
control. Figure 1 depicts the functional block diagram for the ZX6017.
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
3
Address
Decoder
PCMCIA
Configuration
Registers
ATA/IDE
Window
Decoder
or
Peripheral
Bus
PCMCIA
Interface
PCMCIA
Memory
and I/O
Peripheral Bus
Interface
PC_A[25:11]
(16-Bit)
(16-Bit)
Control
Registers
EEPROM
Sequencer
Attribute Memory
(256 Bytes)
Local Serial
EEPROM
SPI
Control
µP
SPI Port
Figure 1. ZX6017 Functional Block Diagram
Power-On Reset
The ZX6017 defaults to the Memory Only interface as outlined in the
PCMCIA specification upon deassertion of Power-On Reset /POR). The
hardware sets Busy on the PC_RDY/BSY pin and then addresses the
EE_MASTER pin. If the EE_MASTER pin is unconnected or pulled
High, the ZX6017 serial interface defaults to the Master mode and an
external EEPROM is required. If this pin is pulled Low, the SLAVE mode
is selected and an external microprocessor is required to configure the
ZX6017 through the serial interface pins.
Next, the hardware addresses the PC_ATA//HOE pin. If the PC_ATA/
HOE pin is held Low for 40 clocks (PC_MCLK_IN) after POR
deassertion, the ZX6017 is enabled for ATA/IDE to ATA/IDE
PASSTHROUGH mode. The PASSTHROUGH mode is for systems that
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
4
use the physical PCMCIA 68-pin connector but do not support PCMCIA
protocol. If this pin is held High (PC_ATA/HOE), the device is placed
into the PCMCIA mode. The override bits in register 00H determine what
mode(s) the user can support.
Serial Port Operation (Master) Mode
After the ZX6017 determines that an external EEPROM is present (see
Figure 2), the Ready/Busy pin on the PCMCIA interface is set to Busy.
The ZX6017 internal sequencer starts up and reads EEPROM address
1eh. If EEPROM address 1Eh is loaded with a 1Ch then the EEPROM’s
data is considered to be valid. After that, the internal sequencer resets its
address counter back to zero. Data from EEPROM’s addresses [00-2F] is
read out and put into the on-board registers of the ZX6017. The EEPROM
sequencer then reads EEPROM addresses 30h to FFh and each byte is
moved into the ZX6017 on-board attribute memory addresses 00-CFh.
After loading the registers and attribute memory, the sequencer completes
by clearing the Ready/Busy pin on the PCMCIA interface indicating 1
“Ready.” If EEPROM address 1Eh does not contain 1Ch, then the
sequencer stops. The PCMCIA Ready/Busy pin stays in the Busy state,
the on-board registers of the ZX6017 remain in their default state, and
attribute memory data is unknown. The user can program the off-board
EEPROM through the PCMCIA interface by means of three special
registers and ignore Busy.
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
5
PCMCIA Bus
Local Peripheral Bus
ATA_DATA 15:0
PC_DATA 15:0
Z86017
ATA_HCS0
ATA_HCS1
Chip Selects
Attribute
Memory
PC_HA 10:0
ATA_HA0
ATA_HA1
Address Selects
ATA_HA2
Window 1
PC_RDY//BSY/IREQ/HINT
PC_WAIT/IOCHRDY
PC_HCE1/HCS0
PC_HCE2/HCS1
PC_ATA/HOE
PC_HIOR
PC_HIOW
PC_HWE
PC_REG/DACK
PC_HRESET/HRESET
Start/Range
Decoder
ATA_HIOR
ATA_HIOW
I/O R/W
Strobes
General
Peripheral
Bus Interface
PCMCIA
Host
Window 2
Start/Range
Decoder
Memory R/W
Strobes
ATA_MRD
ATA_MWR
ATA_IOCHRDY
ATA_IREQ
ATA_IOCS16
ATA_RESET
ATA_DREQ/BVD1
Window 3
Start/Range
Decoder
ATA_PDASP/EXTP_WP
ATA_PDIAG/ATA_BHE/RING_IN
ATA_DACK/BVD2
ATA/IDE
Window
Decoder
PC_BVD1/STSCHG/PDIAG
PC_WP/IOIS16/IOCS16
PC_BVD2/SPKR/DASP/DREQ
PC_INPACK/DREQ
EXTP_PWDN
EXTP_AUDIO
CLK
EEPROM or µP
EXTP_STSCHG/RES2
Control
PC_MCLK_IN
POR
POR
EE_CS
EE_SK
µ
0.1
F
EE_DI
EE_MASTER
EE_DO
M_PINT
CS CK DO DI
EEPROM
GND ORG NC VCC
Figure 2. Serial Port Master Mode Control
Serial Port Operation (SLAVE) Mode
When the ZX6017 is placed in serial port SLAVE mode (EE_Master
signal grounded on POR), the EEPROM sequencer is disabled and the
user must provide external hardware (microprocessor) with serial
interface to program CCRs and attribute memory. Additionally, if the
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
6
POR signal is deasserted, the user must provide a clock source on the
PC_MCLK_IN pin in the range of 1-20MHz.
The external hardware can program the on-board registers and the
attribute memory by selecting the ZX6017 and pulling the EE_CS pin
High. The external hardware must set up the data to be sent to the
ZX6017 on the EE_DI pin and strobe the EE_SK pin. The first byte of
data is the address selected by the user, the second byte is the command
byte and the third byte is the data. The external hardware must provide 24
clocks in order to read or write to a location in the ZX6017 (see Figure 26,
Slave Interface Timing, in Appendix B).
To program the on-board attribute memory, the user must first write to it.
Accomplish this programming by writing the address location of the
attribute memory to be written (or read) in the attribute RAM data address
register at location 08h. When this step has been accomplished, the user
then writes (or reads) the attribute RAM data register 09h with the data to
be read or written at that location.
Note:
The attribute RAM address register auto-incriments after reading
or writing to the attribute RAM data register.
Figure 3 demonstrates programming the ZX6017 in SLAVE Mode. The
external user’s hardware writes to register 00 and selects the clock divide
by and the override mode (if needed). The READY/BUSY pin remains
set to 0 to indicate BUSY, and a local µP interrupt polarity is selected.
The user programs registers 01-05, followed by registers 0Ah-2Fh. The
user writes to the attribute memory by setting the address in the address
register 08h and in the loop on data register 09h with the user’s attribute
memory data. The user completes the operation by writing back to
register 00 to clear the READY/READY status.
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
7
PCMCIA Bus
Local Peripheral Bus
ATA_DATA 15:0
PC_DATA 15:0
Z86017
ATA_HCS0
ATA_HCS1
Attribute
Memory
Chip Selects
PC_HA 10:0
ATA_HA0
ATA_HA1
ATA_HA2
Address Selects
Window 1
Start/Range
Decoder
PC_RDY/BSY/IREQ/HINT
PC_WAIT/IOCHRDY
PC_HCE1/HCS0
ATA_HIOR
ATA_HIOW
General
Peripheral
Bus Interface
PCMCIA
Host
PC_HCE2/HCS1
PC_ATA/HOE
Window 2
Start/Range
Decoder
Memory R/W
Strobes
PC_HIOR
PC_HIOW
ATA_MRD
ATA_MWR
PC_HWE
PC_REG/DACK
PC_HRESET/HRESET
ATA_IOCHRDY
ATA_IREQ
ATA_IOCS16
ATA_RESET
ATA_DREQ/BVD1
Window 3
Start/Range
Decoder
ATA_PDASP/EXTP_WP
ATA_PDIAG/ATA_BHE/RING_IN
ATA_DACK/BVD2
ATA/IDE
Window
Decoder
PC_BVD1//STSCHG//PDIAG
PC_WP//IOIS16//IOCS16
PC_BVD2//SPKR//DASP/DREQ
PC_INPACK/DREQ
EXTP_PWDN
EXTP_AUDIO
EXTP_STSCHG/RES2
CLK
EEPROM or µP
Control
PC_MCLK_IN
/POR
POR
EE_CS
EE_SK
0.1 µF
EE_DI
EE_MASTER
EE_DO
M_PINT
µ
P
Local
Figure 3. Serial Port Slave Mode Control
EEPROM Programming Through the PCMCIA
Interface
The ZX6017 can program the serial EEPROM through the PCMCIA
interface. EEPROM programming is accomplished by means of three
special registers that are accessed identically to the CCR registers as
defined by the PCMCIA specification (Figure 4). These registers are
fixed at addresses 7F0, 7F2, and 7F4. The host software reads and writes
each byte of the EEPROM through these registers and configures the
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
8
ZX6017 device. After the host writes new values to the EEPROM
through these registers, the new values are loaded into the ZX6017 at
Power-On Reset (POR).
Note:
The values written register 05h offset the CCR registers and the
three special EEPROM programming registers on the next POR.
PCMCIA Bus
PC_DATA 15:0
Local Peripheral Bus
ATA_DATA 15:0
ATA_HCS0
Z86017
Attribute
Memory
Chip Selects
ATA_HCS1
PC_HA 10:0
ATA_HA0
ATA_HA1
ATA_HA2
Window 1
Address Selects
Start/Range
Decoder
PC_RDY/BSY/IREQ/HINT
PC_WAIT/IOCHRDY
PC_HCE1/HCS0
PC_HCE2/HCS1
PC_ATA/HOE
PC_HIOR
PC_HIOW
PC_HWE
PC_REG/DACK
PC_HRESET/HRESET
ATA_HIOR
ATAA_HIOW
I/O R/W
Strobes
General
Peripheral
Bus Interface
Window 2
Start/Range
Decoder
PCMCIA
Host
Memory R/W
Strobes
ATA_MRD
ATA_MWR
Window 3
Start/Range
Decoder
ATA_IOCHRDY
ATA_IREQ
ATA_IOCS16
ATA_RESET
ATA_DREQ/BVD1
ATA_PDASP/EXTP_WP
ATA_PDIAG/ATA_BHE/RING_IN
ATA_DACK/BVD2
ATA/IDE
Window
Decoder
EEPROM
Programming
Registers
PC_BVD1//STSCHG/PDIAG
PC_WP/IOIS16/IOCS16
EXTP_PWDN
CLK
PC_BVD2//SPKR/DASP/DREQ
PC_INPACK/DREQ
EXTP_AUDIO
EXTP_STSCHG/RES2
EEPROM Programming Registers
PC_MCLK_IN
7F0H
7F2H
7F4H
EEPROM Address/Status
EEPROM Data
EEPROM Command
POR
/POR
EE_CS
EE_SK
0.1 µF
EE_DI
EEPROM Commands
EE_MASTER
EE_DO
M_PINT
A8H Read
AAH Write
ABH Erase
ACH Disable Write
ADH Enable Write or Erase
CS CK DO DI
EEPROM
GNDORG NC VCC
Figure 4. EEPROM Programming Through the PCMCIA
Interface
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
9
Address Mapping Circuit
Internal Bus, IB7-IB0 and Controls
Window 0 Address 03, 04
ATA/IDE Map
- Special Register
Mapping Circuit
for ATA/IDE
PCMCIA Address
and Control Bus
Actual Address
And Strobes
Window 1 Address
Additional
Chip
Address Range 10, 11,12,13
Register
Select
and
Starting
HCS0
Range
Address Register
Chip Select
Address Control
Register
- Memory
- I/O
HCS1
Logic
and
Address
Logic
IOWR
IORD
- External Chip Select
Window 2 Address
MRD
Address Range 14,15,16,17
Register
MWR
Starting
Address Register
HA2-HA0
Address Control
Register
- Memory
- I/O
- External Chip Select
Window 3 Address
Address Range 18,19,1A,1B
Register
Starting
Address Register
Address Control
Register
- Memory
- I/O
- External Chip Select
Figure 5. Connection Block Diagram
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
10
EE_DI Serial Data In
Serial to Parallel
Shift Register
Parallel to Serial
Shift Register
EE_DO Serial Data Out
EE_Master
1 = Master
0 = Slave
Serial Bus Sequencer
- Master
- Slave
EE_SK Serial Clock
EE_CS Chip Select
PCMCIA EEPROM
ADDRESS Register
Address Register
Data Register
PCMCIA EEPROM
DATA Register
Internal Bus
IB7-IB0 and Controls
PCMCIA EEPROM
Command Register
Buffer
Control Register
- Read/Write, etc.
Figure 6. Serial Interface Diagram
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
11
Internal Bus
IB7-IB0
Internal Bus
IB7-IB0
Data
In
XCVR
256 Bytes of
Attribute Memory
Data
Out
PCMCIA
Output Bus
Bus
Mux
Address
PCMCIA
Address
Counter/
Latch
Configuration Option Register,
Register 0
PCMCIA
Bus
Internal
Bus
Card Configuration and Status,
Register 1
Bus
Mux
Bus
Mux
Pin Replacement Register,
Register 2
Internal Bus
IB7-IB0
Socket and Copy Register,
Register 3
Internal
Bus
I/O Event Register
Register 4
PCMCIA
Bus
EEPROM Extension Registers,
Address, Status, Command and Data
Revision Register
Read Only
Figure 7. Attribute and Configuration Memory Diagram
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
12
PIN DESCRIPTION
75
70
65
60
55
51
50
45
40
35
EE_SK
PC_HA10
VSS
76
80
ATA_MRD
ATA_DREQ/BVD1
ATA_DACK/BVD2
ATA_PDASP/EXTP_WP
ATA_PDIAG/ATA_BHE/RING_IN
VSS
PC_HCE2//HCS1
PC_ATA//HOE
PC_HIOR
PC_HIOW
VDD
ATA_HCS1
PC_HA9
PC_HA8
ATA_HCS0
ATA_HA2
85
90
95
PC_HWE
ATA_HA0
PC_RDY/BSY/IREQ/HINT
PC_HA7
ATA_HA1
Z86017/Z16017
100-Pin VQFP
VDD
ATA_IOCS16
VSS
PC_HA6
ATA_IREQ
ATA_IOCHRDY
PC_HA5
PC_HA4
PC_HRESET/HRESET
VDD
ATA_HIOR
ATA_HIOW
VSS
PC_WAIT/IOCHRDY
PC_HA3
ATA_DATA15
ATA_DATA0
30
26
PC_INPACK/DREQ
PC_HA2
ATA_DATA14
ATA_DATA1
ATA_DATA13
PC_REG//DACK
PC_HA1
ATA_DATA2
100
PC_BVD2/SPKR/DASP/DREQ
1
5
25
10
15
20
Pin 1
Figure 8. ZX6017 100-Pin VQFP Pin Configuration
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
13
75
70
65
60
55
51
50
ATA_DATA2
ATA_DATA13
ATA_DATA1
PC_BVD2//SPKR//DASP/DREQ
PC_HA1
76
80
PC_REG//DACK
ATA_DATA14
ATA_DATA0
ATA_DATA15
VSS
ATA_HIOW
ATA_HIOR
ATA_IOCHRDY
ATA_IREQ
ATA_IOCS16
VDD
PC_HA2
PC_INPACK/DREQ
PC_HA3
PC_WAIT/IOCHRDY
VDD
45
40
35
PC_HRESET/HRESET
PC_HA4
85
90
95
PC_HA5
PC_HA6
VSS
PC_HA7
Z86M17 and Z16M17
100-Pin VQFP
ATA_HA1
ATA_HA0
ATA_HA2
PC_RDY/BSY/IREQ/HINT
PC_HWE
PC_HA8
PC_HA9
ATA_HCSO
ATA_HCS1
VSS
VDD
PC_HIOW
PC_HIOR
ATA_PDIAG/ATA_BHE/RINNG_I
ATA_PDASP/EXTP_WP
ATA_DACK/BVD2
ATA_DREQ/BVD1
ATA_MRD
30
26
PC_ATA//HOE
PC_HCE2//HCS1
VSS
EE_SK
100
PC_HA10
1
5
25
10
15
20
Pin 1
Figure 9. Z86M17 and Z16M17 (Mirror Image) 100-Pin VQFP
Pin Configuration
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
14
PIN IDENTIFICATION
Table 3. 100-Pin VQFP Pin Identification
ZX6017 M17 Name
Description
PCMCIA Address, Bit 0
PC_BVD1//STSCHG//PDIAG Battery Voltage Detect 1, Status Change, PDiag
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
PC_HA0
PC_DATA0
PC_DATA8
VSS
PCMCIA Data, Bit 0
PCMCIA Data, Bit 8
Ground
PC_DATA1
PC_DATA9
PC_DATA2
PC_DATA10
PC_WP//IOIS16//IOCS16
ATA_HRESET
ATA_DATA7
ATA_DATA8/RES1
VDD
PCMCIA Data, Bit 1
PCMCIA Data, Bit 9
PCMCIA Data, Bit 2
PCMCIA Data, Bit 10
Write Protect PCMCIA I/O Is 16-Bit Transfers
AT Host RESET
AT Host Data, Bit 7
AT Host Data, Bit 8, Reserved Input 1
Supply Voltage
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
Ground
ATA_DATA6
ATA_DATA9/PACK_IN
ATA_DATA5
ATA_DATA10
VSS
AT Host Data, Bit 6
AT Host Data, Bit 9, PACK_IN
AT Host Data, Bit 5
AT Host Data, Bit 10
Ground
ATA_DATA4
ATA_DATA11
ATA_DATA3
VDD
AT Host Data, Bit 4
AT Host Data, Bit 11
AT Host Data, Bit 3
Supply Voltage
ATA_DATA12
ATA_DATA2
ATA_DATA13
ATA_DATA1
AT Host Data, Bit 12
AT Host Data, Bit 2
AT Host Data, Bit 13
AT Host Data, Bit 1
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
15
Table 3. 100-Pin VQFP Pin Identification (Continued)
ZX6017 M17 Name
Description
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
ATA_DATA14
ATA_DATA0
ATA_DATA15
VSS
ATA_HIOW
ATA_HIOR
ATA_IOCHRDY
ATA_IREQ
ATA_IOCS16
VDD
ATA_HA1
ATA_HA0
ATA_HA2
AT Host Data, Bit 14
AT Host Data, Bit 0
AT Host Data, Bit 15
Ground
AT Host I/O Write Strobe
AT Host I/O Read Strobe
AT Host I/O Channel Ready
AT Host Interrupt Request
AT Host I/O Is 16 Bits Wide
Supply Voltage
AT Host Address, Bit 1
AT Host Address, Bit 0
AT Host Address, Bit 2
AT Host Chip Select 0
AT Host Chip Select 1
Ground
ATA_HCS0
ATA_HCS1
VSS
ATA_PDIAG/ATA_BHE/
Ring_IN
PDIAG I/O, Byte High Enable, RING_IN
46
47
30
29
ATA_PDASP/EXTP_WP
ATA_DACK/BVD2
PDASP I/O or Write Protect In
AT Host DMA Acknowledge, Battery Voltage
Input 2
48
49
50
51
52
53
54
55
56
57
58
28
27
26
25
24
23
22
21
20
19
18
ATA_DREQ/BVD1
ATA_MRD
EE_SK
EE_MASTER
EE_CS
EE_DO
EE_DI
ATA_MWR
POR
M_PINT
AT Host DMA Request, Battery Voltage Input 1
AT Host Memory Read Strobe
EEPROM Data Clock
EEPROM Is Master
EEPROM Data Chip Select
EEPROM Data Out
EEPROM Data In
AT Host Memory Write Strobe
Power-On Reset
Local Processor Interrupt
Master Clock In
PC_MCLK_IN
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
16
Table 3. 100-Pin VQFP Pin Identification (Continued)
ZX6017 M17 Name
Description
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
17
16
15
14
13
12
11
10
9
8
7
6
5
EXTP_PWDN
EXTP_AUDIO
EXTP_STSCHG/RES2
VDD
PC_DATA3
PC_DATA4
PC_DATA11
PC_DATA5
PC_DATA12
VSS
PC_DATA6
PC_DATA13
PC_DATA7
PC_DATA14
VDD
Power Down Output
Audio Input
Status Change Input, Reserved Input 2
Supply Voltage
PCMCIA Data, Bit 3
PCMCIA Data, Bit 4
PCMCIA Data, Bit 11
PCMCIA Data, Bit 5
PCMCIA Data, Bit 12
Ground
PCMCIA Data, Bit 6
PCMCIA Data, Bit 13
PCMCIA Data, Bit 7
PCMCIA Data, Bit 14
Supply Voltage
PCMCIA Card Enable 1 ATA Chip Select 0
PCMCIA Data, Bit 15
PCMCIA Address, Bit 10
Ground
PCMCIA Card Enable 2 ATA Chip Select 1
Mode Select/PCMCIA Output Enable
PCMCIA I/O Read Strobe
PCMCIA I/O Write Strobe
Supply Voltage
4
3
2
1
PC_HCE1//HCS0
PC_DATA15
100 PC_HA10
99
98
97
96
95
94
93
92
91
90
89
88
87
86
VSS
PC_HCE2//HCS1
PC_ATA//HOE
PC_HIOR
PC_HIOW
VDD
PC_HA9
PC_HA8
PC_HWE
PCMCIA Address, Bit 9
PCMCIA Address, Bit 8
PCMCIA Write Enable
PC_RDY//BSY//IREQ/HINT PCMCIA Ready/Busy, Interrupt Request
PC_HA7
VSS
PC_HA6
PC_HA5
PCMCIA Address, Bit 7
Ground
PCMCIA Address, Bit 6
PCMCIA Address, Bit 5
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
17
Table 3. 100-Pin VQFP Pin Identification (Continued)
ZX6017 M17 Name
Description
91
92
93
94
95
96
97
98
99
100
85
84
83
82
81
80
79
78
77
76
PC_HA4
PC_HRESET//HRESET
VDD
PC_WAIT/IOCHRDY
PC_HA3
PC_INPACK/DREQ
PC_HA2
PC_REG//DACK
PC_HA1
PC_BVD2//SPKR//DASP/
DREQ
PCMCIA Address, Bit 4
PCMCIA Reset
Supply Voltage
PCMCIA Wait, /IOCHRDY
PCMCIA Address, Bit 3
PCMCIA Input Acknowledge, DREQ
PCMCIA Address, Bit 2
PCMCIA Register Signal, DACK
PCMCIA Address, Bit 1
PCMCIA Battery Voltage Detect 2, Speaker
Output, DASP, DREQ
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
18
PIN FUNCTIONS
PCMCIA Signals
•
•
•
•
•
•
PC_DATA<15:0> ( I/O, Tristate, 8 mA)
PCMCIA Mode: 16-bit host Data bus.
ATA/IDE Mode: 16-bit host Data bus.
PC_HA<10:3> (Input)
PCMCIA Mode: Host Address lines: 10,9,8,7,6,5,4,3.
ATA/IDE Mode: Not used.
PC_HA<2:0> I(nput)
PCMCIA Mode: Host Address lines: 2,1,0.
ATA/IDE Mode: Host Address lines: 2,1,0.
PC_HCE1//HCS0 (Input, 100K Pull-Up)
PCMCIA Mode: This signal is Card Enable 1 (active Low).
ATA/IDE Mode: Host Chip Select 0 (active Low).
PC_HCE2//HCS1 (Input, 100K Pull-Up)
PCMCIA Mode: This signal is Card Enable 2 (active Low).
ATA/IDE Mode: Host Chip Select 1 (active Low).
PC_REG/DACK (Input, 100K Pull-Up)
PCMCIA Mode: (/REG), Register bit is asserted when the host
selects I/O or Attribute Memory.
ATA/IDE Mode: Data acknowledge (/DACK) defined in ATA. Issued
during DMA data transfers on the data bus.
•
•
PC_ATA//HOE ( Input, 100K Pull-Up)
PCMCIA Mode: Memory Output Enable Strobe.
ATA/IDE Mode: When pulled Low on Power-On Reset, this signal
indicates ATA/IDE mode.
PC_HWE (Input, 100K Pull-Up)
PCMCIA Mode: Memory Write Enable Strobe.
ATA/IDE Mode: Not used.
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PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
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•
•
PC_HIOR (Input, 100K Pull-Up)
PCMCIA Mode: In PCMCIA I/O mode, this is the Input/Output Read
Strobe.
ATA/IDE Mode: Input/Output Read Strobe.
PC_HIOW (Input, 100K Pull-Up)
PCMCIA Mode: In PCMCIA I/O mode, this is the Input/Output
Write Strobe.
ATA/IDE Mode: Input/Output Write Strobe.
•
•
PC_HRESET/HRESET(Input, Schmitt-Triggered, 100K Pull-Up)
PCMCIA Mode: Active High input Reset signal.
ATA/IDE Mode: Active Low input Reset signal.
PC_RDY/BSY/IREQ/HINT (Output, 8 mA)
PCMCIA Mode: In PCMCIA memory mode, this signal is READY/
BUSY. This signal will be asserted BUSY by the RESET logic. In
PCMCIA I/O mode, this signal is /IREQ.
ATA/IDE Mode: When enabled, the HINT signal is used to interrupt
the host (active High).
•
PC_WP//IOIS16//IOCS16 (Output, Tri-State, 8 mA)
PCMCIA Mode: In PCMCIA memory mode, this signal is Write
Protected. In PCMCIA I/O mode, this signal is IOIS16 and indicates
that a 16-bit capable I/O device is being accessed on the PCMCIA
bus.
ATA/IDE Mode: I/O chip select 16 indicates that a 16- bit transfer is
active on the bus.
•
•
PC_WAIT/IOCHRDY (Output, Tri-State, 8 mA)
PCMCIA Mode: Insert Wait States when held active and the chip is
being selected in I/O or memory mode.
ATA/IDE Mode: Inserts Wait States when held active, and when the
chip is being selected.
PC_INPACK/DREQ (Output, Tri-State, 8 mA)
PCMCIA Mode: In PCMCIA I/O mode this signal is Input
Acknowledge. It is asserted by the card when the card is selected and
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
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can respond to an I/O cycle at the address on the address bus.
ATA/IDE Mode: This signal is Data request (DREQ), defined in ATA.
It is issued during DMA data transfers on the data bus.
•
•
PC_BVD1/STSCHG/PDIAG (I/O, 8 mA)
PCMCIA Memory Mode: Battery Voltage Detect 1, output.
PCMCIA I/O Mode: Status Changed. This signal is used to indicate
the change of status in the Pin Replacement Register (I/O Mode) or
state of the BVD1 input when in Memory Mode.
ATA/IDE Mode: Passed diagnostics.
PC_BVD2/SPKR/DASP/DREQ (I/O, Tri-State, 10 mA)
PCMCIA Memory Mode: Battery Voltage Detect 2, output.
PCMCIA I/O Mode: SPKR, inverted AUDIO_EXTP signal, output;
PCMCIA ATA Mode: ATA Data Request is the input pin for this
signal, when DMA Enable bit is set in Window Start/Range Address
registers.
ATA/IDE Mode: Drive active/Slave present DASP.
•
ATA_DATA<15:10> (I/O, Tri-State, 8 mA)
ATA/IDE Mode: Host Data Bus, bits: 15,14,13,12,11,10.
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PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
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Peripheral or ATA/IDE Signals
•
ATA_DATA<15:10> (I/O, Tri-State, 8 mA)
ATA/IDE Mode: Host Data Bus, bits: 15,14,13,12,11,10.
Peripheral Mode: Peripheral data bus, bits: 15, 14, 13, 12, 11,10.
•
ATA_DATA9/PACK_IN (I/O, Tri-State, 8 mA)
ATA/IDE Mode: Host Data Bus, bit: 9.
Peripheral Mode: When 8-bit mode is enabled (on the Local side)
ATA_DATA9 can be used as a PACK_IN input.
•
ATA_DATA8/RES1 (I/O, Tri-State, 8 mA)
ATA/IDE Mode: Host Data Bus, bit: 8.
Peripheral Mode: When 8-bit mode is enabled (on the Local side),
ATA_DATA8 can be used as a RES1 input.
•
•
ATA_DATA<7:0> (I/O, Tri-State, 8 mA)
ATA/IDE Mode: Host Data Bus, bits: 7,6,5,4,3,2,1,0.
Peripheral Mode: Peripheral Data Bus, bits: 7,6,5,4,3,2,1,0.
ATA_HA<2:0> (Output, 8 mA)
ATA/IDE Mode: ATA Host Address bits used to address the IDE
interface chip.
Peripheral Mode: Lower three bits offset from starting address.
•
•
ATA_HCS0 (Output, 8 mA)
ATA/IDE Mode: ATA Host Chip Select 0, used to select the IDE
interface chip.
Peripheral Mode: Chip Select 0 used as a chip select for an external
peripheral device as defined by the address range and offset register
definition.
ATA_HCS1 (Output, 8 mA)
ATA/IDE Mode: ATA Host Chip Select 1, used to select the IDE
interface chip.
Peripheral Mode: Chip Select 1 used as a chip select for an external
peripheral device as defined by the address range and offset register
definition.
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
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•
•
•
ATA_HIOR (Output, 8 mA)
ATA/IDE Mode: ATA Host I/O Read Strobe.
Peripheral Mode: I/O read strobe or memory read strobe, depending
on configuration.
ATA_HIOW (Output, 8 mA)
ATA/IDE Mode: ATA Host I/O Write Strobe.
Peripheral Mode: I/O Write Strobe or Memory Write Strobe,
depending on configuration.
ATA_IOCS16 (Input, 100K Pull-Up)
ATA/IDE Mode: I/O channel is 16 bits wide; input on the local ATA
bus.
Peripheral Mode: I/O access is 16 bits wide.
•
•
•
ATA_IREQ (Input)
ATA/IDE Mode: ATA/IDE host Interrupt Request.
Peripheral Mode: Interrupt Request.
ATA_IOCHRDY (Input, 100K Pull-Up)
ATA/IDE Mode: ATA/IDE I/O Channel Ready-Input.
Peripheral Mode: I/O Channel Ready.
ATA_HRESET (Output, 8 mA)
ATA/IDE Mode: ATA Host Reset-Output to the ATA/IDE controller
(programmable).
Peripheral Mode: Host reset output to the peripheral device if
PCMCIA signal is active (programmable).
•
•
ATA_DREQ/BVD1 (Input)
ATA/IDE Mode: ATA/IDE DMA request from the ATA/IDE
controller.
Peripheral Mode: Peripheral bus DMA Request or when in memory
mode Battery Voltage 1 Detect input.
ATA_DACK/BVD2 (I/O, 8 mA)
ATA/IDE Mode: ATA/IDE host DMA Acknowledge.
Peripheral Mode: Peripheral Bus DMA Acknowledge. DMA
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
23
acknowledge is generated by the ZX6017 whenever DMA
Acknowledge is enabled in the Window Start/Range Address
registers and the address corresponds to the DMA address; or Battery
Voltage 2 Detect input in memory mode.
•
•
ATA_PDASP/EXTP_WP (I/O, Tri-State, 8 mA)
ATA/IDE Mode: ATA/IDE bus side PDASP signal controlled by
internal bits ZEN_EXT_PDASP (Input) or ZEN_INT_PDASP
(Output).
Peripheral Mode: When configured as a Write Protect input, this pin
will disable Write on the peripheral bus side.
ATA_PDIAG/ATA_BHE/RING_IN (I/O, Tri-State, 8 mA)
ATA/IDE Mode: ATA/IDE bus side PDIAG signal controlled by
internal bits ZEN_EXT_PDIAG (Input) or ZEN_INT_PDIAG
(Output).
Peripheral Mode: When configured as Byte High Enable for memory
boards, ATA_BHE indicates High byte available, or it can be
configured to be the RING_IN input signal for the I/O event indicator
CCR4.
•
•
ATA_MRD (Output, 8 mA)
ATA/IDE Mode: Not used.
Peripheral Mode: External Memory Read Strobe.
ATA_MWR (Output, 8 mA)
ATA/IDE Mode: Not used.
Peripheral Mode: External Memory Write Strobe.
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
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Serial Interface Signals
•
•
•
EE_DO (Output, 8 mA, Tri-State)
Master Mode: EEPROM data out Serial data, valid during EE_SK
edge. In master mode, this signal is an output.
Slave Mode: In slave mode, this signal is an output.
EE_SK (I/O, 8 mA)
Master Mode: EEPROM data clock. This signal is an output in master
mode. It is active during R/W cycle only.
Slave Mode: In slave mode, this signal is an input.
EE_CS (I/O, 8 mA)
Master Mode: EEPROM data chip select. This signal is an output in
master mode.
Slave Mode: In slave mode this signal is an input. This signal is active
High.
•
•
EE_DI (Input, 100K Pull-Up)
Master Mode: EEPROM data in. This signal is an input in master
mode.
Slave Mode: In slave mode, this signal is an input.
EE_MASTER (Input, Schmitt-Triggered, 100K Pull-Up)
Master/Slave mode detect: When set Low, no EEPROM is present.
When set High EEPROM is present.
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Z86017/Z16017 PCMCIA Interface Solution
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Peripheral Control Signals
•
POR (Input, Schmitt-Triggered, 100K Pull-Up)
Local Power-On Reset signal. A 0.1mF capacitor is recommended on
this pin to GND to generate a POR.
•
•
M_PINT (Output, Tri-State, 8 mA)
Interrupt to local microprocessor
PC_MCLK_IN (Input, Schmitt-Triggered)
Master Clock In. This is an input signal. This clock signal is used to
generate all internal timing. All local bus signals are asynchronous to
this clock.
•
•
•
EXTP_STSCHG/RES2 (Input, 100K Pull-Up)
Status Change Input. This signal outputs the value of the status
changed line on the PCMCIA bus if enabled in the CCR register, or it
is an input for bit 7 (RSVDEVT3) in CCR4.
EXTP_AUDIO (Input 100K Pull-Up)
Audio Input. This input signal reflects the audio output. This signal is
active High, and the Speaker output on the PCMCIA bus is active
Low.
EXTP_PWDN (Output, 8 mA)
Power Down Output. This signal reflects the state of the Power Down
bit in the CCR.
•
•
V
(Input)
SS
Ground.
V
(Input)
DD
Supply Voltage.
PCMCIA Interface Overview
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
26
PS012002-1201
PCMCIA Interface Overview
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
27
Addressing Modes
•
•
•
•
•
The ZX6017 supports all PCMCIA Addressing Modes:
PCMCIA Common Memory Mode
PCMCIA I/O Mode
PCMCIA ATA_IDE Mode
Pass-through ATA/IDE-to-ATA/IDE Mode
Note:
This mode is for users who have a 68-pin PCMCIA connector,
but are using ATA/IDE protocol instead of PCMCIA protocol.
The overall ZX6017 mode of operation is controlled by the Interface
Configuration Register (00h) bits 3,2. 00 in these two bits sets the device
to ATA/IDE mode if the PC_ATA/HOE pin is Low on power-up and into
PCMCIA mode if the pin is High. The default for this register is 00 and
the PC_ATA/HOE pin determines the mode of operation, PCMCIA or
ATA/IDE. Table 4 describes these addressing modes.
Table 4. ZX6017 Addressing Modes
Mode/Bus
PCMCIA
Peripheral Bus
Comments
Memory
I/O
Memory
I/O
Memory
I/O
PCMCIA_ATA_Memory
PCMCIA_ATA_I/O
Memory
I/O
ATA
Primary ATA
Secondary ATA
Contiguous ATA
ATA/IDE
Contiguous block of at least
16 I/O registers is assigned to
one card.
Pass-Through Mode
ATA/IDE
To place the ZX6017 into proper Addressing mode, a set of Configuration
Registers and Memory Maps reside on-chip.
Addressing Modes
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
28
The four on-chip address maps are:
•
•
•
•
Memory_Map_1
Memory_Map_2
Memory_Map_3
PCMCIA_ATA/IDE Map
Memory_Map_1, _2 and _3 support PCMCIA Memory/IO Mode. The
chip can be configured in PCMCIA Mode either by:
•
Pulling the PC_ATA/HOE pin High during RESET;
or by
Writing 10 in Override bits (bits 3, 2) in the Interface Configuration
•
Register 0 (address 00h), and 0 in bits 0, 1, 2, 6 of the Interface
Configuration Register 02 (address 03h).
After placing the device into PCMCIA Mode, each Map can be
configured independently through its set of configuration registers.
Each Memory Map contains a set of Configuration Registers consisting
of:
•
•
•
•
Window Control Register
Window Start Address LSB Register
Window Start/Range Address MSB
Window Range Address LSB
The PCMCIA_ATA/IDE Map enables chip operation in PCMCIA_ATA/
IDE mode. When in this mode, the chip responds to different types of
accesses, depending on the content of the following registers:
•
•
•
Interface Configuration Register 02, address 03h (bits 0, 1, 6)
Interface Configuration Register 03, address 04h (bits 0, 1, 2, 3)
PCMCIA Exception Status Register, address 071h (bit 0)
PS012002-1201
Addressing Modes
Z86017/Z16017 PCMCIA Interface Solution
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29
Table 5 describes programming PCMCIA_ATA ZX6017 Configuration
Registers.
Table 5. Programming PCMCIA_ATA ZX6017 Configuration Registers
ICR_2
[1:0]
ICR_02[6] ICR_03[3:0] CICR_1[7:0] CICR_2[7:0] CCR0[5:0] addr
addr03
addr03
addr04
addr2DH
addr2EH
addr0AH 07[0} Description
x
x
xxxx
xxxxxxxx
xxxxxxxx
xxxxx
1
Chip operates
in ATA/IDE-
to-ATA/IDE
passthrough
mode
11
11
0
1
xxxx
1111
xxxxxxxx
FFH
xxxxxxxx
FFH
xxxxx
00011
0
0
PCMCIA
Mode
Enabled access
to Primary set
of IDE Task
File Registers
(1Fo-1F7)
11
11
1
1
1111
1111
FFH
FFH
FFH
FFH
00011
00010
0
0
Enabled access
to Primary set
of IDE Task
File Registers
(3F6-3F7)
Enabled access
to Secondary
set of IDE Task
File Registers
Addressing Modes
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
30
Table 5. Programming PCMCIA_ATA ZX6017 Configuration Registers (Continued)
ICR_2
[1:0]
ICR_02[6] ICR_03[3:0] CICR_1[7:0] CICR_2[7:0] CCR0[5:0] addr
addr03
addr03
addr04
addr2DH
addr2EH
addr0AH 07[0} Description
11
1
1111
FFH
FFH
00001
0
PCMCIA_AA
Independent
IO Mode. Chip
responds to
any 1/0 access
in the range
000 to 00Fh
PCMCIA
11
1
1111
FFH
FFH
00000
0
Independent
Memory
Mode.
Chip responds
to any Memory
access in the
range 000-
00Fh
Tables 6 through Table 9 provide ZX6017 addressing information in each
mode.
Table 6. PCMCIA Common Memory Mode
Function Mode
REG
CE2 CE1 A0
0E
WE
D15-D8
D7-D0
Standby Mode
Byte Access
X
H
H
H
H
H
H
H
L
H
L
L
L
H
X
L
H
Z
X
L
L
L
H
X
H
H
H
L
High-Z
High-Z
High-Z
Odd-Byte
Odd-Byte
High-Z
Even-Byte
Odd-Byte
Even-Byte
XX
Word Access
Odd-Byte only
access
L
X
PS012002-1201
Addressing Modes
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
31
Table 7. PCMCIA I/O Mode
Function Mode
REG CE2 CE1 A0
OE
WE
D15-D8
D7-D0
Standby Mode
Byte Access
X
H
H
H
H
L
H
H
H
L
X
L
H
L
L
L
X
H
X
L
H
Z
X
X
X
L
L
L
L
L
X
H
H
H
H
H
High-Z
High-Z
High-Z
Odd-byte
High-Z
Odd-byte
High-Z
Even-byte
Odd-byte
Even-byte
High-Z
Word Access
I/O Inhibit
Odd-byte only
access
High-Z
Byte Access
L
L
L
H
L
H
H
L
X
L
L
L
L
X
H
L
H
L
X
X
H
H
H
H
H
L
L
L
L
L
X
X
Even-byte
Odd-Byte
Even-byte
X
Word Access
I/O Inhibit
Odd-byte only
access
Odd-byte
X
Odd-byte
X
Table 8. PCMCIA_ATA Memory Mapped Access
REG# A10 A[9:4] A3 A2 A1 A0 OE#
WE#
H
H
H
H
H
H
H
L
L
L
L
L
L
L
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
Read Data
Error
Write Data
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Addressing Modes
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
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32
Table 8. PCMCIA_ATA Memory Mapped Access
REG# A10 A[9:4] A3 A2 A1 A0 OE#
WE#
H
H
L
L
X
X
L
H
H
L
H
L
H
L
Status
Duplicate Even
Read Data
Status
Duplicate Even
Write Data
H
L
X
H
L
L
H
Duplicate Odd
Read Data
Duplicate Odd
Write Data
H
H
H
H
H
L
L
L
H
H
X
X
X
X
X
H
H
H
X
X
H
H
H
X
X
L
H
L
H
L
Duplicate Error
Alt Status
Drive Address
Even Read Data
Odd Read Data
Duplicate Feature
Device Control
Reserved
Even Write Data
Odd Write Data
H
H
X
X
H
Table 9. PCMCIA_ATA I/O Mapped Access
Primary
REG# A[9:0]
Secondary
A[9:0]
Contiguous
A[3:0]
IORD# = L
IOWR# = L
L
L
L
L
L
L
L
L
L
1F0H
1F1H
1F2H
1F3H
1F4H
1F5H
1F6H
1F7H
–
170H
171H
172H
173H
174H
175H
176H
177
00H
01H
02H
03H
04H
05H
06H
07H
08H
Read Data
Error
Write Data
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Command
–
Duplicate Even
Read Data
Duplicate Even
Write Data
L
L
–
–
–
–
09H
Duplicate Odd
Read Data
Duplicate Error
Duplicate Odd
Write Data
Duplicate
0DH
Feature
L
L
1F6H
3F7H
376H
377H
0EH
0FH
Alt Status
Drive Access
Device Control
Reserved
PS012002-1201
Addressing Modes
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
33
Programming Internal Registers
INTRODUCTION
As stated in “Addressing Modes” on page 27, the ZX6017 devices feature
a set of on-chip programmable registers that can be programmed either by
using the on-board EEPROM Sequencer (MASTER Mode) or by Local
Microprocessor (SLAVE Mode). A set of Card Configuration Registers
can be accessed from the PCMCIA interface. Table 10 lists the
programmable registers.
Table 10. ZX6017 Card Configuration Registers
EEPROM PCMCIA
POR
Address
Address
Register’s Name
Access Value Comments
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
XX0h
Interface Configuration Rg 0
Interrupt Enable Rg
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
R/W
R/W
00h
00h
00h
00h
00h
00h
00h
00h
XX
XX
00h
Interface Configuration Rg 1
Interface Configuration Rg 2
Interface Configuration Rg 3
PCMCIA CCR’s Base Rg
PCMCIA Interrupt Status Rg
PCMCIA Exception Status Rg
Attribute RAM Address Rg
Attribute RAM Data Rg
PCMCIA Configuration Option Rg
(CCR0)
PCMCIA Card Configuration and
Status Rg (CCR1)
Note1
Note1
Note1
Note1
Note2
0Bh
XX2h
R/W
00h
Note2
0Ch
0Dh
0Eh–0Fh
10h
11h
XX4h
XX6h
PCMCIA Pin Replacement Rg (CCR2)
PCMCIA Socket and Copy Rg (CCR3)
Reserved
Window 1 Control Rg
Window 1 Start Address LSB Rg
R/W
R/W
00h
00h
XX
01h
00h
Note2
Note2
NA
NA
R/W
R/W
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
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Table 10. ZX6017 Card Configuration Registers (Continued)
EEPROM PCMCIA
POR
Address
Address
Register’s Name
Access Value Comments
12h
NA
Window 1 Start/Range Address MSB
Rg
R/W
00h
13h
14h
15h
16h
NA
NA
NA
NA
Window 1 Range Address LSB Rg
Window 2 Control Rg
Window 2 Start Address LSB Rg
Window 2 Start/Range Address MSB
Rg
R/W
R/W
R/W
R/W
00h
01h
00h
00h
17h
18h
19h
1Ah
NA
NA
NA
NA
Window 2 Range Address LSB Rg
Window 3 Control Rg
Window 3 Start Address LSB Rg
Window 3 Start/Range Address MSB
Rg
R/W
R/W
R/W
R/W
00h
01h
00h
00h
1Bh
1Ch–1Dh
1Eh
NA
Window 3 Range Address LSB Rg
Reserved
EEPROM Valid Flag Byte Rg (1Ch)
R/W
R/W
R/W
R/W
00h
XX
00h
NA
Master Mode
only
Note2, Note3
1Fh
20h
XX8h
7F0h
PCMCIA I/O Event Indication Rg
(CCR4)
EEPROM Addr/Status Rg (CCR5)
Back Door
00h
00h
Note1
21h
22h
7F2h
7F4h
EEPROM Data Rg (CCR6) Back Door
EEPROM Command Rg (CCR7) Back
Door
R/W
R/W
00h
00h
Note1
Note1
23h
24h
25h
26h
27h
NA
7F6h
Revision Control Rg
Revision Number Rg
Reserved
Bus Control Rg 1
IOIS16 Address Control Rg
R/W
R
R/W
R/W
R/W
00h
Note3
Note4
XX
00h
00h
NA
NA
Note5
Note5
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
35
Table 10. ZX6017 Card Configuration Registers (Continued)
EEPROM PCMCIA
POR
Address
Address
Register’s Name
Access Value Comments
28h
29h
2Ah
NA
ATA/IDE Dual Drive Control Rg
Reserved
Power Management Timer Count Value
Rg
R/W
R/W
R/W
00h
00h
00h
Note3
NA
Note3
2Bh
2Ch
2Dh
2Eh
2Fh
30h–FFh
NA
NA
NA
NA
NA
Power Management Control Rg
Interface Con•guration Rg 4
Con•guration Index Compare Rg 1
Con•guration Index Compare Rg 2
Bus Control Rg 2
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
XXh
Note3
Note3
Note3
Note3
Note3
Note6
User-Definable Attribute Memory
Location 00h–CFh (208-byte)
NOTES:
1. When the ZX6017 is in Master Mode, the user should program this location in EEPROM with 00h.
2. The PCMCIA base address for these registers could be set in the range of 000h–400h. At Power-On Reset
(POR), the base is set to 000h.
3. User must write the Revision Number (see ZX6017 top mark) to the Revision Control register to unlock these registers.
4. The Z86017 BA Revision Number is 10h (see device top mark).
5. These registers are only available on the Z16017.
6. When the ZX6017 is in Master Mode, data at EEPROM addresses 30h–FFh are written locations 00h–CFh of the on-board Attribute Memory.
In Slave Mode, Attribute Memory is programmed through registers 08h and 09h.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
36
EEPROM REGISTER
EEPROM Register
Address: SELECT 00h
Name: Interface Configuration Register 0
Type: Read/Write
Table 11. Interface Configuration Register: Address 00h
Bit Placement Bit Name Description
Bits 1–0
Set Internal
Internal Clock Divider. On Power-On Reset, clock divide-
by-32 selects the Master Clock. On Power-On Reset, set
these bits to 0 0. Table 12 describes Master Clock
Settings.
Bit 1
Bit 0
0
1
1
1
0
1
0
1
Slowest Clock, Clock In divide-by-32
Clock In divide-by-16
Clock In divide-by-4
Clock In
Bits 3–2
EN_OVERIDE
Overrides PCMCIA ATA mode bits, /PC_ATA//HOE
selection on the PCMCIA interface. On Power-On Reset,
both bits are set to 0. Sample /PC_ATA//HOE.
Bit 3
Bit 2
0
0
1
1
0
1
0
1
PC_ATA/HOE Sampled to Set Mode
Forces ATA/IDE Pass Through Mode
Forces PCMCIA Mode
Reserved
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
37
Table 11. Interface Configuration Register: Address 00h (Continued)
Bit Placement Bit Name
Description
Bit 4
EN_RDY_BSY
When this bit is set to 1, the PC_RDY/BSY/REQ/HINT
pin is configured as RDY//BSY. To con•gure this pin as an
IREQ/HINT, set this bit to 0. On Power-On Reset, the
ZX6017 automatically reads the EEPROM and also
determines if a PCMCIA device is connected. After the
entire attribute memory is loaded and the chip initialization
is complete, the READY/BSY signal on the PCMCIA bus
indicates READY. Without an EEPROM, the device
indicates READY whenever this bit is set and the ZX6017
has determined a PCMCIA bus is connected.
Bit 5
Bit 6
EN_CTR_IRQ
EN_INT_POL
Enables PCMCIA Interrupt Mode. Enables ATA_IREQ pin
to control PC_IREQ in I/O Mode. This bit is active when
set to 1. On Power-On Reset, this bit is set to 0.
Enable local (M_PINT) processor interrupt polarity active
Low. This bit is active when set to 1. On Power-On Reset,
this bit is set to 0. Interrupt is active High. M_PINT is a tri-
state driven signal. Whenever an interrupt is present and
enabled, M_PINT is driven. If the interrupt is programmed
active High, then M_PINT is driven from tri-state to High.
If the interrupt polarity selects active Low interrupts, then
the interrupt is driven from tri-state to active Low. Also see
Register 2Ch.
Bit 7
EN_ATA_BHE
When this bit is set to 1, it enables the ATA_PDIAG/
ATA_BHE/RING_IN pin to be used as a Byte High Enable
pin on a local interface side. Byte High Enable is used to
signify that a PCMCIA host is requesting or sending data
on the high byte bus pins ATA_DATA[15-8] of the local
bus. For ATA_BHE, also see Register 2Fh. When set to 0,
ATA_PDIAG/ATA_BHE/RING_IN is used as a local
bidirectional PDIAG pin. On Power-On Reset, this bit is
set to 0.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
38
Table 12. Master Clock
EEPROM
CLK
Timing
Interrupt
Pulse1Width Comments
Register 0
Bit 1
Register 0
Bit 9
Clock In
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50 ns
50 ns
50 ns
50 ns
100 ns
100 ns
100 ns
100 ns
6.4 µs
3.2 µs
800 ns
200 ns
12.8 µs
6.4 µs
1.6 µs
400 ns
204 µs
102 µs
25 µs
5.25 µs
404 µs
204 µs
50 µs
Recommended
12.5 µs
Recommended
NOTES:
1. The pulse width of the /PC.IREQ signal in pulse mode is dependent on the clock period of the master clock input (TPMCKIN). The pulse
width of the /PC.IREQ signal is equal to 192 x TPMCKIN.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
39
EEPROM Register
Address: SELECT 01h
Name: Interrupt Enable Register
Type: Read/Write
Table 13. Interrupt Enable Register: Address 01h
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
Bit 3
EN_PC_INT0
EN_PC_INT1
EN_PC_INT2
EN_PC_INT3
Enables Local Processor interrupt when PCMCIA host has
written CCR0, the Con•guration Option Register. This
interrupt stays present until this bit is set to 0. This bit is
active when set to 1. On Power-On Reset, this bit is set to
0. Also see Registers 06h, 2Ch.
Enables Local Processor interrupt when PCMCIA host has
written CCR1, the Card Status Register. This interrupt
stays present until this bit is set to 0. This bit is active when
set to 1. On Power-On Reset, this bit is set to 0. Also see
Registers 06h, 2Ch.
Enables Local Processor interrupt when PCMCIA host has
written CCR2, the Pin Replacement Register. This
interrupt stays present until this bit is set to 0. This bit is
active when set to 1. On Power-On Reset, this bit is set to
0. Also see Registers 06h, 2Ch.
Enables Local Processor interrupt when PCMCIA host has
written CCR3, the Socket and Copy Register. This
interrupt stays present until this bit is set to 0. This bit is
active when set to 1. On Power-On Reset, this bit is set to
0. Also see Registers 06h, 2Ch.
Bit 4
Bit 5
EN_PC_INT4
Enables Local Processor interrupt when ATA_IREQ is
asserted. This interrupt stays present until this bit is set to
0. This bit is active when set to 1. On Power-On Reset, this
bit is set to 0. Also see Registers 06h, 2Ch.
EN_EXTP_WP
Enables external write protect pin as an input when set to
1. When set to 0, this bit is DASP on the local AT bus side.
On Power-On Reset, this bit is set to 0.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
40
Table 13. Interrupt Enable Register: Address 01h (Continued)
Bit Placement Bit Name
Bit 6 CCR0_OVERIDE
Description
ATA_DASP is used as a DASP pin. Also see Register 02h.
Card Con•guration Register 0 is normally written after
Power-On Reset by the PCMCIA host. If Interrupts are
allowed by the local processor or EEPROM, then the
PCMCIA READY/BSY signal is configured as an
interrupt signal only when the Card Configuration Register
is written. If the local processor does not require the
PCMCIA host to write to CCR0, bit CCR0_OVERIDE can
be set to force the internal logic to select the PCMCIA
READY/BSY as the Interrupt pin, if interrupts are enabled.
This bit is active when set to 1. On Power-On Reset, set
this bit to 0, no override selected. PCMCIA host must
select interrupts and write to the Card Con•guration
Register 0.
Bit 7
EN_INPACK
Enable PCMCIA Input acknowledge when set to 1. On
Power-On Reset, this bit is set to 0.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
41
EEPROM Register
Address: SELECT 02h
Name: Interface Configuration Register 1
Type: Read/Write
Table 14. Interface Configuration Register 1: Address 02h
Bit Placement Bit Name
Description
Bit 0
PDIAG_SET
When set to 1, this bit activates PDIAG on the PCMCIA
bus side. On Power-On Reset, this bit is set to 0.
Bit 1
EN_PDIAG
When set to 1, this bit drives the PCMCIA pin on the
PCMCIA side. On Power-On Reset, this bit is set to 0
(Table 15). Also see Registers 04h, 07h.
Bit 2
Bit 3
PDASP_SET
EN_DASP
When set to 1, this bit sets the DASP pin on the PCMCIA
side. On Power-On Reset, this bit is set to 0.
When set to 1, this bit drives the DASP pin on the
PCMCIA side. On Power-On Reset, this bit is set to 0
(Table 16).
Bit 4
Bit 5
EN_OR_CS01
EN_SPKR
When set to 1, this bit is active and ATA_HCS0 has the
same level as ATA_HCS1. On Power-On Reset, this bit is
set to 0 (Table 17). Also see Register 03h (Table 19).
When set to 1, this bit is active and connects
EXTP_AUDIO (inverted) to the PC_BVD2//SPKR//
DASP/DREQ pin. On Power-On Reset, this bit is set to 0
(Table 18).
Bit 6
Bit 7
EN_DASP_INT
EN_DASP_EXT
When set to 1, DASP is generated internally. On Power-On
Reset, this bit is set to 0.
When set to 1, DASP is generated externally from the
AT_DASP pin on the local AT bus side. On Power-On
Reset, this bit is set to 0. Also see Register 01h (Table 13).
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
42
Table 15. PCMCIA PDIAG Pin Functions
PCMCI Register 7
Bit5,PCM
ATA_PDI PDIAG CIA
Register2 Register2 Register 4 Register4
Bit 1 Bit 0 Bit 7 Bit 6
EN_PDI PDIAG_S EN_PDIAG EN_PDIAG AG
A
OUT
I/O
PDIAG
Input
AG
ET
_EXT
_INT
Pin I/O
Comments
0
X
X
X
X
Float - Z PDIAG-
OUT
Input mode
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
X
Float - Z PDIAG-
OUT
1 (Output) 1
Input mode
X
Output 1
(totem)
Output 0
(totem)
X
0 (Output) 0
0 (Output) 0
0 (Input)
Output
generated
from ATA-
PDIAG.
Output
floated by
ATA-PDIAG
when set to
1.
ATA_PDIA
G is sourced
from
PCMCIA
side.
1
0
0
0
0
0
1
0
0
0
1
1
1 (Input)
Float - Z PDIAG-
OUT
0 (Output) 0 (Input)
0
1
Float - Z
1 (Input)
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
43
Table 16. PCMCIA DASP Pin Functions
PCMCIA Register7
Register2 Register2
Bit 3 Bit 2
Register2
Bit 7
Register2
Bit 6
DASP
ATA_DASP OUT
PCMCIA
DASP
EN_DASP DASP_SET EN_DASP_EXT EN_DASP_INT Pin I/O
I/O
Input
Comment
0
0
1
X
1
1
X
0
0
X
1
1
X
X
X
Float - Z
Float- Z
1 (Output)
DASP-OUT Input mode
DASP-OUT Input mode
1
0
0
Output 1
(totem)
Output 0
(totem)
1
1
0
0
0
1
1
0
X
0 (Output)
0 (Output)
0 (Input)
Output
generated
from ATA-
DASP.
1
0
0
0
0
0
1
0
0
0
1
1
1 (Input)
0 (Output)
Float - Z
Float- Z
0 (Input)
1 (Input)
DASP-OUT Output
floated
when ATA-
DASP is set
to 1.
0
1
ATA_DASP
is sourced
from
PCMCIA
side.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
44
Table 17. Host Chip Select Designations
Register 2
Bit 4
EN_OR_CS01
ATA_HCS0
Internal HCS1 (External)
ATA_HCS0
0
0
1
1
1
0
1
0
0
1
X
X
0
0
1
0
1
1
1
X
Table 18. Audio Pin Configurations
Register 2
Bit 5
Register 7
Bit 0
Register 2
Bit 3
PC_SPKR/
EN_SPKR
EXTP_AUDIO
ATA_MODE EN_DASP
DASP//DREQ
0
1
1
1
0
0
X
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
x
Float - Z
1
0
AT_DREQ Input
AT_DREQ Input
DASP mode
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
45
EEPROM Register
Address: SELECT 03h
Name: Interface Configuration Register 2
Type: Read/Write
Table 19. Interface Configuration Register 2: Address 03h
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
Bit 3
EN_MEM_MODE
Enables PCMCIA memory access mode. This bit controls
window0. It is active when set to 1. On Power-On Reset,
this bit is set to 0.
EN_INDP_MODE
EN_ATT_MODE
EN_INVERT_HCS0
Enables PCMCIA independent I/O access mode. This bit
controls window0. It is active when set to 1. On Power-On
Reset, this bit is set to 0.
Enables PCMCIA attribute memory access. This bit is
active when set to 1. On Power-On Reset, this bit is set to
0. Also see Registers 08h and 09h (Table 28 and Table 29).
Inverts the polarity of HCS0 output. HCS0 is active High
when this bit is set. HCS0 is active Low when this bit is
cleared. This bit is active when set to 1. On Power-On
Reset, this bit is set to 0, active Low. Also see Register 02h
(Table 14).
Bit 4
EN_INVERT_HCS1
Inverts the polarity of HCS1 output. HCS1 is active High
when this bit is set. HCS1 is active Low when this bit is
cleared. This bit is active when set to 1. On Power-On
Reset, this bit is set to 0, active Low. Also see Register 02h
(Table 14).
Bit 5
Bit 6
EN_INVERT_ATRST
EN_IO_MODE
Inverts the polarity of the ATA_HRESET output.
Enables PCMCIA/ATA/IDE access to 1Fx, 3Fx, 17x, 1Fx
task Registers. This bit controls window0. This bit is active
when set to 1. On Power-On-Reset, this bit is set to 0.
Bit 7
Reserved
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
46
EEPROM Register
Address: SELECT 04h
Name: Interface Configuration Register 3
Type: Read/Write
Table 20. Interface Configuration Register 3: Address 04h
Bit Placement Bit Name
Description
Enables IDE/PCMCIA access to primary task file
addresses 1F<0-7>. This bit is active when set to 1. On
Power-On Reset, this bit is set to 0.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
SEL_PRIMARY_1x
SEL_PRINARY_3x
SEL_SECOND_1x
SEL_SECOND_3x
STR_RST
Enables IDE/PCMCIA access to primary task file
addresses 3F<6-7>. Active when set to 1. On Power-On
Reset, this bit is set to 0 (Table 21).
Enables IDE/PCMCIA access to secondary task file
addresses 17<0-7>. Active when set to 1. On Power-On
Reset, this bit is set to 0.
Enables IDE/PCMCIA access to secondary task file
addresses 37<0-7>. Active when set to 1. On Power-On
Reset, this bit is set to 0.
Switching this bit from Low to High to Low again forces
the ZX6017 to check the level on PC_ATA/HOE pin and
latch the mode. This bit is active when set to 1. On Power-
On Reset, this bit is set to 0.
Bit 5
Bit 6
Bit 7
EN_DIS_RST
Disable PCMCIA reset. This bit is active when set to 1.
Resets from the PCMCIA bus are not allowed. On Power-
On Reset, this bit is set to 0 (Table 22).
EN_PDIAG_INT
EN_PDIAG_EXT
When this bit is set to 1, PDIAG is generated internally. On
Power-On Reset, this bit is set to 0. Also see Registers 02h
and 07h (Table 14 and Table 26).
When this bit is set to 1, PDIAG is generated externally
through the AT_PDIAG pin on the local AT side. On
Power-On Reset, this bit is set to 0. Also see Registers 02h
and 07h (Table 14 and Table 26).
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
47
Table 21. ATA Register Selection Designations
Register 4
Bit 3
Register 4
Bit 2
Register 4
Bit 1
Register 4
Bit 0
Register 3 Address
Bit 6 Range
SEL_SECO SEL_SECO SEL_PRIMA SEL_PRIMA EN_IO_M Respons
ND_3x
ND_1x
RY_3x
RY_1x
ODE
e
Note
X
0
0
X
0
0
X
0
0
X
0
1
0
1
1
XX
XX
Disabled
Disabled
1F0-1F7 Primary
HDD
0
0
1
0
1
1
1
0
0
1
0
0
1
1
1
1F0-1F7, Primary
3F6, 3F7 HDD
170-177 Secondary
HDD
170- 177, Two drive
376, 377 system on
local
1
1
1
1
170- 177, AT bus
376, 377, side
1F0-1F7
3F6, 3F7
Table 22. Reset Conditions
Register 4
Bit 5
Register 7
Bit 0
EN_DIS_RST PC_HRESET ATA_MODE ATA_HRESET Notes:
1
X
X
1
PCMCIA Mode, Reset
Disabled
0
0
0
1
0
0
1
0
PCMCIA Mode, No Reset
PCMCIA Mode, Asserted
Reset
0
0
1
0
1
1
1
0
ATA Mode, No Reset.
ATA Mode, Asserted Reset.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
48
EEPROM Register
Address: SELECT 05h
Name: BCMCIA CCR Base Address Register
Type: Read/Write
Table 23. PCMCIA CCR Base Address Register: Address 05h
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
EN_CRR_A4
EN_CRR_A5
EN_CRR_A6
EN_CRR_A7
EN_CRR_A8
EN_CRR_A9
EN_CRR_A10
DIS_CRR_MODE
Enables address bit 4 to be compared as High on PCMCIA
when the PCMCIA Con•guration Register’s base address
is accessed. On Power-On Reset, this bit is set to 0.
Enables address bit 5 to be compared as High on PCMCIA
when the PCMCIA Con•guration Register’s base address
is accessed. On Power-On Reset, this bit is set to 0.
Enables address bit 6 to be compared as High on PCMCIA
when the PCMCIA Con•guration Register’s base address
is accessed. On Power-On Reset, this bit is set to 0.
Enables address bit 7 to be compared as High on PCMCIA
when the PCMCIA Con•guration Register’s base address
is accessed. On Power-On Reset, this bit is set to 0.
Enables address bit 8 to be compared as High on PCMCIA
when the PCMCIA Con•guration Register’s base address
is accessed. On Power-On Reset, this bit is set to 0.
Enables address bit 9 to be compared as High on PCMCIA
when the PCMCIA Con•guration Register’s base address
is accessed. On Power-On Reset, this bit is set to 0.
Enables address bit 10 to be compared as High on
PCMCIA when the PCMCIA Con•guration Register’s base
address is accessed. On Power-On Reset, this bit is set to 0.
Disables PCMCIA host and allows access to the PCMCIA
Con•guration Register’s base address. This bit is active
when set to 1. On Power-On Reset, this bit is set to 0.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
49
Table 24. CCR Location Examples, Register 5
CCR
Base
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EN
1
0
0
0
A10
X
0
0
0
A9
X
0
0
1
A8
X
0
0
0
A7
X
0
0
0
A6
X
0
0
0
A5
X
0
0
0
A4
X
0
1
0
Address
None
0000hx
0010hx
0200hx
0400hx
0
1
0
0
0
0
0
0
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
50
EEPROM Register
Address: SELECT 06h
Name: PCMCIA Interrupt Status Register
Type: Read
Table 25. PCMCIA Interrupt Status Register: Address 06h
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
Bit 3
PC_INT0
PC_INT1
PC_INT2
PC_INT3
PCMCIA host write to CCR0, the Configuration Option
Register has occurred. This bit is active when set to 1. Also
see Register 01h (Table 13).
PCMCIA host write to CCR1, the Card Configuration and
Status Register has occurred. This bit is active when set to
1. Also see Register 01h (Table 13).
PCMCIA host write to CCR2, the Pin Replacement
Register has occurred. This bit is active when set to 1. Also
see Register 01h (Table 13).
PCMCIA host write to CCR3, the Socket and Copy
Register has occurred. This bit is active when set to 1. Also
see Register 01h (Table 13).
Bit 4
Bit 5
Bit 6
Bit 7
PC_INT4
PC_INT5
REV_BA
Reserved
External ATA_IREQ interrupt has occurred. This bit is
active when set to 1. Also see Register 01h (Table 13).
PCMCIA host write to CCR4, an I/O Event Indication
Register has occurred. This bit is active when set to 1.
Set this bit to 1 after writing the revision number (see
device top mark) to the revision control Register.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
51
EEPROM Register
Address: SELECT 07h
Name: PCMCIA Exception Status Register
Type: Read
Table 26. PCMCIA Exception Status Register: Address 07h
Bit Placement Bit Name
Description
Bit 0
ATA/IDE_MODE
When bit 7 of this register is set to 1, ATA mode has been
selected by sampling the /PC_ATA//HOE signal on Power-
On-Reset, or the override bits in Register 0 have set the
ZX6017 to run in ATA/IDE mode. When set to 0, this bit
indicates that the ZX6017 operates in PCMCIA mode
(Table 27).
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
PCRST
Reserved
Reserved
Reserved
PDIAG
DASP
PCMCIA reset status. Active when set to 1.
PDIAG is present. This bit is active when set to 1.
DASP is present. Drive Active/Slave Present. This bit is
active when set
Bit 7
ATA_SAMPLED
When set to 1, this bit indicates that bit 0 of this register is
valid to read.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
52
Table 27. ATA Sample Mode Bit
Register 7
Bit 7
Register 7
Bit 0
ATA_SAMPLED ATA_MODE
Comments
0
1
1
X
0
Not ready
PCMCIA Addressing Mode
ATA/IDE Addressing Mode
1
EEPROM Register
Address: SELECT 08h
Name: Attribute Memory Address Register
Type: Write
Table 28. Attribute Memory Address Register: Address 08h
Bit Placement Bit Name Description
Bits 7-0
Attribute Memory Address After each access to the attribute RAM data register, the
address is automatically incremented. Also see Register
03h.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
53
EEPROM Register
Address: SELECT 09h
Name: Attribute Memory Data Register
Type: Write/Read
Table 29. Attribute Memory Data Register: Address 09h
Bit Placement Bit Name
Description
Bits 7-0
Attribute Memory Data
The data read and written from this register is associated
with the attribute memory location pointed to by the
attribute RAM data address register. After each data write
or read into this location, the address is automatically
incremented by one. Also see Register 03h (Table 19).
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
54
EEPROM Register
Address: SELECT 10h
Name: Window 1 Control Register
Type: Write/Read
Table 30. Window 1 Control Register: Address 10h
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
DIS_PAC1
When this bit is set to 1, the Port 1 Address Control and
decoder are disabled.
EN_PAC1_MEM
EN_PAC1_16
When this bit is set to 1, Memory Mode decoder is
enabled. When cleared, I/O mode is enabled.
When this bit is set, data swapping is provided internal to
the chip during data reads from the low byte of the ATA
bus to the PCMCIA bus high byte, and from the high byte
of the PCMCIA bus to the low byte of the ATA bus during
data writes. When cleared, it is high byte to high byte and
low byte to low byte.
Bit 3
Bit 4
Bit 5
READ_PROTECT
Allows two cards at the same address to be read. When this
bit is set, it prevents the PCMCIA bus from going active.
EN_PAC1_ADDR_COMP When this bit is set, use address compare logic; when it is
cleared, acknowledge all PCMCIA chip selects.
EN_PAC1_HCS
When this bit is set, HCS1 is used as an external chip
select. When this bit is cleared, HCS0 is used as an
external chip select. Also see Registers 02h and 03h
(Table 14 and Table 19).
Bits 7-6
Number of wait states (in Master Clock periods) inserted
on the PCMCIA bus.
00 = 0xTpmclkin (no wait states)
01 = 3x Tpmclkin
10 = 5x Tpmclkin
11 = 7x Tpmclkin
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
55
EEPROM Register
Address: SELECT 11h
Name: Window 1 Start Address LSB
Type: Write/Read
Table 31. Window 1 Start Address LSB: Address 11h
Bit Placement Bit Name
Description
Bits 7-0
LSB starting address for Port 1.
EEPROM Register
Address: SELECT 12h
Name: Window 1 Start/Range Address MSB
Type: Write/Read
Table 32. Window 1 Start/Range Address MSB: Address 12h
Bit Placement Bit Name
Description
Bits 2-0
Bits 8, 9, and 10 of the starting address range of Port 1.
Bit 3
EN_WRITE_PROTECT
When this bit is set, the RWPROT bit in the pin
replacement register is used to inhibit writing to the
external peripherals. When these bits are cleared, PROT is
ignored.
Bits 6-4
Bit 7
Bits 8, 9, and 10 of the starting address range of Port 1.
EN_DMA_ACK
When this bit is set, ATA_DMA_ACKNOWLEDGE is set
when the address space is accessed, and Speaker Out on
the PCMCIA interface is used as DREQ.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
56
EEPROM Register
Address: SELECT 13h
Name: Window 1 Range Address LSB
Type: Write/Read
Table 33. Window 1 Range Address LSB: Address 13h
Bit Placement Bit Name
Description
Bits 7-0
LSB range Address for Port 1
EEPROM Register
Address: SELECT 14h
Name: Window 2 Control Register
Type: Write/Read
Table 34. Window 2 Control Register: Address 14h
Bit Placement Bit Name
Description
Bit 0
DIS_PAC2
When this bit is set to 1, it disables Port 2 address control
and decoder.
Bit 1
EN_PAC2_MEM
When this bit is set to 1, Memory Mode decoder is
enabled. When it is cleared, the I/O Mode decoder is
enabled.
Bit 2
Bit 3
EN_PAC2_16
When this bit is set, data swapping is provided internal to
the chip during data reads from the low byte of the ATA
bus to the PCMCIA bus high byte, and from the high byte
of the PCMCIA bus to the low byte of the ATA bus during
data writes. When this bit is cleared, it is high byte to high
byte and low byte to low byte.
READ_PROTECT
Allows two cards at the same address to be read from.
When this bit is set, it prevents the PCMCIA bus from
becoming active.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
57
Table 34. Window 2 Control Register: Address 14h (Continued)
Bit Placement Bit Name Description
Bit 4
EN_PAC2_ADDR_COMP When this bit is set, use address compare logic, when it is
cleared, acknowledge all PCMCIA chip selects.
Bit 5
EN_PAC2_HCS
When this bit is set, HCS1 is used as an external chip
select; when it is cleared, HCS0 is used as an external chip
select. Also see Registers 02h and 03h.
Bits 7-6
Number of wait states (in Master Clock period) inserted on
the
EEPROM Register
Address: SELECT 15h
Name: Window 2 Start Address LSB
Type: Write/Read
Table 35. Window 2 Start Address LSB: Address 15h
Bit Placement Bit Name
Description
Bits 7-0
LSB starting address for Port 2.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
58
EEPROM Register
Address: SELECT 16h
Name: Window 2 Start/Range Address MSB
Type: Write/Read
Table 36. Window 2 Start/Range Address MSB: Address 16h
Bit Placement Bit Name
Description
Bits 2-0
Bits 8, 9, and 10 of the starting address range of Port 2.
Bit 3
EN_WRITE_PROTECT
When this bit is set, the RWPROT bit in the pin
replacement register is used to inhibit writing to the
external peripherals. When it is cleared, PROT is ignored.
Bits 8, 9, and 10 of the starting address range of Port 2.
Bits 6-4
Bit 7
EN_DMA_ACK
When this bit is set, ATA_DMA_ACKNOWLEDGE is set
when the address space is accessed, and Speaker Out on
the PCMCIA interface is used as DREQ.
EEPROM Register
Address: SELECT 17h
Name: Window 2 Range Address LSB
Type: Write/Read
Table 37. Window 2 Range Address LSB: Address 17h
Bit Placement Bit Name
Description
Bits 7-0
LSB range address for Port 2.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
59
EEPROM Register
Address: SELECT 18h
Name: Window 3 Control Register
Type: Write/Read
Table 38. Window 3 Control Register: Address 18h
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
DIS_PAC3
When set to 1, this bit disables Port 3 address control and
decoder.
EN_PAC3_MEM
EN_PAC3_16+
When this bit is set to 1, Memory mode decoder is enabled.
When it is cleared, I/O mode decoder is enabled.
When this bit is set, data swapping is provided internal to
the chip during data reads from the low byte of the ATA
bus to the PCMCIA bus high byte, and from the high byte
of the PCMCIA bus to the low byte of the ATA bus during
data writes. When this bit is cleared, it is high byte to high
byte and low byte to low byte.
Bit 3
READ_PROTECT
This bit allows two cards to be read from the same address.
When this bit is set, it prevents the PCMCIA bus from
becoming active.
Bit 4
Bit 5
EN_PAC3_ADDR_COMP When this bit is set, use address compare logic; when it is
cleared, acknowledge all PCMCIA chip selects.
EN_PAC3_HCS
When this bit is set, HCS1 is used as an external chip
select; when it is cleared, HCS0 is used as an external chip
select.
Bits 7-6
Number of wait states (in Master Clock periods) inserted
on the PCMCIA bus.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
60
EEPROM Register
Address: SELECT 19h
Name: Window 3 Start Address LSB
Type: Write/Read
Table 39. Window 3 Start Address LSB: Address 19h
Bit Placement Bit Name
Description
Bits 7-0
LSB starting Address for Port 3.
EEPROM Register
Address: SELECT 1Ah
Name: Window 3 Start/Range Address MSB
Type: Write/Read
Table 40. Window 3 Start/Range Address MSB: Address 1Ah
Bit Placement Bit Name
Description
Bits 2-0
Bits 8, 9, and 10 of the starting address range of Port 3.
Bit 3
EN_WRITE_PROTECT
When this bit is set, the RWPROT bit in the pin
replacement register is used to inhibit writing to the
external peripherals. When this bit is cleared, PROT is
ignored.
Bits 6-4
Bit 7
Bits 8, 9, and 10 of the starting address range of Port 3.
EN_DMA_ACK
When this bit is set, ATA_DMA_Acknowledge is set when
the address space is accessed, and Speaker Out on the
PCMCIA interface is used as DREQ.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
61
EEPROM Register
Address: SELECT 1Bh
Name: Window 3 Range Address LSB
Type: Write/Read
Table 41. Window 3 Range Address LSB: Address 1Bh
Bit Placement Bit Name
Description
Bits 7-0
LSB range address for Port 3.
EEPROM Register
Address: SELECT 1Eh
Name: EEPROM Valid Flag Byte Register
Type: Read
Table 42. EEPROM Valid flag Byte Register: Address 1Eh
Bit Placement Bit Name
Bits 7-0 Flag Byte
Description
Read-Only Register used by the internal EEPROM
Sequencer to determine if the contents of the EEPROM are
valid. The valid Flag value is 1Ch.
EEPROM Register
Address: SELECT 20h
Name: EEPROM Address/Status CCR5 Back Door
Type: Write/Read
Table 43. EEPROM Address/Status CCR5 Back Door: Address 20h
Bit Placement Bit Name
Description
Bits 7-0
Address/Status Bits
EEPROM address/status data.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
62
EEPROM Register
Address: SELECT 21h
Name: EEPROM Data CCR6 Back Door
Type: Write/Read
Table 44. EEPROM Data CCR6 Back Door: Address 21h
Bit Placement Bit Name
Bits 7-0 Data Bits
Description
EEPROM data.
EEPROM Register
Address: SELECT 22h
Name: EEPROM Command CCR7 Back Door
Type: Write/Read
Table 45. EEPROM Command CCR7 Back Door: Address 22h
Bit Placement Bit Name
Description
Bits 7-0
Command Bits
Command value.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
63
EEPROM Register
Address: SELECT 23h
Name: Revision Control Register
Type: Read/Write
Table 46. Revision Control Register: Address 23h
Bit Placement Bit Name Description
Bit 3-0
REV_MINOR
The lower four bits determine the minor revision number.
This nibble must be written with the value read back from
the lower nibble in Read-Only Register 24h to enable the
minor revision functions.
Bit 7-4
REV_MAJOR
The upper four bits determine the major revision number.
This nibble must be written with the value read back from
the upper nibble in Read-Only Register 24h to enable the
major revision functions.
EEPROM Register
Address: SELECT 24h
Name: Revision Number Register
Type: Read
Table 47. Revision Number Register: Address 24h
Bit Placement Bit Name
Description
Bit 3-0
Bit 7-4
REV_NUM_MINOR
REV_NUM_MAJOR
This is the Read-Only minor revision number of the chip.
This is the Read-Only major revision number of the chip.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
64
EEPROM Register
Address: SELECT 26h
Name: Bus Control 1 Register
Type: Read/Write
Reset: 00h
Table 48. Bus Control 1 Register: Address 26h
Bit Placement Bit Name
Description
Bit 0
DISABLE_CLK
When this bit is set to 1, it turns off the PC_MCLK_IN
pad. When it is cleared, it enables the PC_MCLK_IN pad.
This bit is automatically cleared when in MASTER mode
and at any access to the EEPROM command Register 7F4h
as seen through the PCMCIA interface.
Bit 1
EN_IOIS_IN
8-Bit_CNTRL
When this bit is set to 1, it enables the IOIS16 signal to be
generated internally (see Register 27, IOIS16 Address
Control Register, Table 49). When it is cleared, the source
for IOIS16 will be the ATA_IOIS16 input.
Bit 3-2
PCMCIA 8- to 16-bit control enable (see Table 51).
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
65
Table 48. Bus Control 1 Register: Address 26h (Continued)
Bit Placement Bit Name
Description
Bit 4
EN_RW_LONG
Set this bit to 1 to enable the read/write long function when
using the 8-bit to 16-bit mode or internal IOCS16
generation in ATA/IDE pass-through mode.
PCMICA 8-Bit to 16-Bit Access After 512 bytes are
transferred, each PC_IOR/IOW strobe to the data register
will generate a ATA_IOR/IOW strobe on the ATA/IDE
bus. 8-bit to 16-bit accesses of the data register will be
continued after any write access to a task file register other
than the data register.
ATA/IDE PASSTHROUGH mode. When set in ATA/IDE
PASSTHROUGH mode after 256 word accesses of the
data register, the //IOCS16 signal on the host interface de-
asserts until the next data transfer phase. The internal
IOCS16 function must also be enabled. (EN_IOIS_IN=1)
and the IOIS16 ADDR register set to 01 pointing to the
ATA/IDE task file data Register 1F0, 170. Clearing this bit
disables the read/write long function.
Bit 6-5
Bit 7
IOIS16_CTRL
BVD_CTRL
IOIS16 source select (see Table 49)
When set to 1, this bit enables the PC_BVD1/STSCHG/
PDIAG and PC_BVD2/SPKR/DASP/DREQ functions.
When cleared, it sets both PC_BVD1/STSCHG/PDIAG
and PC_BVD2/SPKR/DASP /DREQ pins High when in
PCMCIA ATA/IDE memory mode. At Power-On Reset,
set to 0.
Note:
Registers 26h and 27h are only available on the Z16017 device.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
66
EEPROM Register
Address: SELECT 27h
Name: IOIS16 Address Control Register
Type: Read/Write
Reset: 00h
The contents of this register determine which on-Host address IOIS16 is
generated, but only when bit 1 of Register 26h is set to 1.
Table 49. IOIS16 Address Control Register: Address 27h
Register
Content
Bit <7-0>
Host Address
PC_HA <3-0>
PC_WP/IOIS16/IOIS16 Comments
10000000 (80h)
1110 (Eh)
0
Must use this address to generate
IOIS16.1
01000000 (40h)
00100000 (20h)
00010000 (10h)
00001000 (08h)
00000100 (04h)
00000010 (02h)
00000001 (01h)
NOTES:
1100 (Ch)
1010 (Ah)
1000 (8h)
0110 (6h)
0100 (4h)
0010 (2h)
0000 (0h)
0
0
0
0
0
0
0
1. For IOIS16 to be generated on any even address, the register must contain 1 in all positions.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
67
Table 50. 16-Bit_Control
Bit 6
Bit 5
Description
0
0
0
1
IOIS16 is being generated internally.
1
IOIS8 is the source for the IOIS16 in PCMCIA I/O Mode.1
1
IOIS16 is always High in PCMCIA I/O Mode
Note:
IOIS8 is bit 5 in CCR1 Card Configuration and Status Register.
NOTES:
1.
Table 51. 8-Bit _CTRL
Bit 3
Bit 2
Description
0
0
1
0
1
PCMCIA_8 to ATA_16 Mode is disabled.
0
1
IOIS8 controls PCMCIA_8 to ATA_16 Mode.1
1
Forces the ZX6017 into PCMCIA_8 to ATA_16 Mode.
NOTES:
1. IOIS8 is bit 5 in CCR1 Card Configuration and Status Register.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
68
EEPROM Register
Address: SELECT 28h
Name: ATA/IDE Dual Drive Control
Type: Read/Write
Bit Placement Bit Name
Description
Bit 0
M_S_enable
This bit enables the Master/Slave mode control. When
this bit is set to 1, the Master/Slave function is enabled.
When it is set to 0, this function is disabled.
When programmed, this bit determines when to drive the
ATA/IDE bus. When set to 1, the ZX6017 drives the
ATA bus when the host writes a 1 into Bit 4 of the
“Drive/Head” task file register. Both primary and
secondary addresses are compared. If this bit is set to 0,
then the ZX6017 drives the bus if the host writes a 0 into
Bit 4 of the “Drive/Head” task fie register.1
Unused
Bit 1
Drive_select
Bit 7-2
Reserved
NOTES:
1. Read Back Values: Z86017 00010000b = 10h
Z16017 00100000b = 20h
EEPROM Register
Address: SELECT 2Ah
Name: Power Management Timer Count Value
Type: Read/Write
Table 52. Power Management Timer Count Value: Address 2Ah
Bit Placement Bit Name
Description
Power management timer count value. The timer reset
Bit 7-0
TIMER_VAL
during all PCMCIA activity. When the timer expires, it
powers down all noncritical signals. TIMER intervals
(sec.) = PC_MCLK (sec.) * 2(27) * timer_val. For
example: PC_MCLK (20 MHz, 50 ns) * 2(27) * 1 = 6.67
sec. Also see Register 2Ch (Table 56).
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
69
EEPROM Register
Address: SELECT 2Bh
Name: Power Management Control Register
Type: Read/Write
Table 53. Power Management control Register: Address 2Bh
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
EN_8BIT_MODE
When set to 1, this bit enables the 8-bit mode on the local
interface. When cleared, it enables the 16-bit interface.
EN_MODEM_ALT
EN_CLK
When set to 1, this bit enables the alternate modem
functions/pins. When cleared, it disables modem functions.
When this bit is set to 1, all internal clocks are disabled
after loading from the serial EEPROM. When this bit is
cleared, all clocks are enabled.
Bit 3
Bit 4
EN_PADS1
EN_TIMER
When this bit is set to 1, the PCMCIA external pads are
powered-down, unless PCMCIA(*) PC_HCE1 and
PC_HCE2 are active. When this bit is cleared, all external
pads are enabled.
When this bit is set to 1, the power management timer is
enabled. The timer value is contained in Register 2A.
When this bit is cleared, the power management timer is
held reset and disabled.
Bit 5
Bit 6
EN_PM_RDY
EN_EXT_PD
When this bit is set to 1, the ZX6017 sets BUSY on the
PCMCIA interface when the host sets the power down bit
in CCR1.
When this bit is set to 1, the power management timer
activates the external power down signal EXTP_PWND.
When this bit is cleared, the external signal is not be
activated. See also Register 0Bh (Table 67).
Bit 7
EN_EXPD_POL
When this bit is set to 1, the external power down signal
EXTP_PWND is active Low. When this bit is cleared,
EXTP_PWND is active High.
NOTES:
1. When the En_Pads bit is set, access to the CCR Registers is disabled.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
70
EEPROM Register
Address: SELECT 2Ch
Name: Interface Configuration Register 4
Type: Read/Write
Table 54. Interface Configuration Register 4: Address 2Ch
Bit Placement Bit Name Description
Bit 2-0
TSTCLK
These power management clock select bits can be used to
provide delay times in a number of different scales.
Table 55 describes the different delay scale settings. Also
see Register 2Ah (Table 53).
Bit 3
EN_POLL_BSY
This bit allows the ZX6017 to poll the Busy status bit in
the local controller task file. When enabled in PCMCIA
ATA I/O mode, the Busy status bit in the local controllers
task file latches into the pin replacement register. In
PCMCIA ATA Memory mode, the Busy status bit is placed
on the Ready/Busy signal. Set this bit to 1 to enable auto
polling. When this bit is cleared, auto polling is disabled.
On Power-On Reset, it is set to 0.
Bit 4
Bit 5
EN_GLOB_INT
EN_PC_INT5
This is a Global Interrupt Enable for the M-PINT pin.
When set to 1, this bit enables the local µP interrupts.
When cleared, it disables the local µP interrupt. On Power-
On Reset, it is set to 0.
This bit enables the local Processor interrupt when the
PCMCIA host has written the I/O event indication Register
CCR4. This interrupt source stays present until this bit is
set to 0. When set to 1, this bit is active. On Power-On
Reset, it is set to 0.
Bit 6
EN_BVD_INPUTS
When set to 1, this bit enables the two BVD inputs to be
reflected either in Pin Replacement Register or on the
corresponding pins of the ZX6017. On Power-On Reset, it
is set to 0. See also Register 0Ch (Table 66).
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Product Specification
71
Table 54. Interface Configuration Register 4: Address 2Ch (Continued)
Bit Placement Bit Name
Bit 7 EN_PULSE
Description
When set, this bit enables auto busy status when the host
sets reset. The busy status remains present until the internal
time-out or when using a µP and the µP clears the busy
status. When cleared, this bit disables auto busy on host
resets. The pulse time for busy is 2(15)/PC_MCLK (MHz)
= SEL.
Table 55. Power Management Clock Select
Timer/Count
Input Clock PC_MCLK
Bit 2 Bit 1 Bit 0 6.7 sec./count
@ 20 MHz
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
6.4 µsec./count
Disable counter
12.8 µsec./count
100 nsec./count
6.4 µsec./count
6.4 µsec./count
@ 20 MHz
@ 20 MHz
@ 20 MHz
@ 20 MHz
@ 20 MHz
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
72
EEPROM Register
Address: SELECT 2Dh
Name: Configuration Index Compare Register 1
Type: Read/Write
Table 56. Configuration Index Compare Register 1: Address 2Dh
Bit Placement Bit Name
Description
These bits are the configuration index for I/O secondary
Bit 2-0
IO_SEL_SEC
select.
Bit 3
EN_ IO_SEL_SEC
IO_SEL_PRI
When set to 1, this bit enables the configuration index I/O
secondary select; when cleared, it is disabled.
Bit 6-4
Bit 7
These bits are the configuration index for I/O primary
select.
EN_IO_SEL_PRI
When set to 1, this bit enables the configuration index I/O
primary select; when cleared, it is disabled.
EEPROM Register
Address: :SELECT 2Eh
Name: Configuration Index Compare Register 2
Type: Read/Write
Table 57. Configuration Index Compare Register 2: Address 2Eh
Bit
Placement
Bit
Name
Description
Bit 2-0
Bit 3
MEM_INDX
These bits are the configuration index for memory select.
EN_MEM_INDX
When set to 1, this bit enables configuration index memory
select; when cleared, it is disabled.
Bit 6-4
Bit 7
IO_INDP_INDX
These bits are the configuration index for I/O independent
select.
EN_IO_INDP_INDX
When set to 1, this bit enables configuration index
independent select; when cleared, it is disabled.
PS012002-1201
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Z86017/Z16017 PCMCIA Interface Solution
Product Specification
73
EN_IO_MODE bit 6 in Register 03h and Primary/Secondary enables in
Register 04h bits 3, 2, 1, and 0 are globally enabled based on the values
written into Register 2D and the Host writing into the configuration index
bits in CCR0.
EN_MEM_MODE bit 0 and the EN_INDP_MODE bit 1 in Register 03h
are globally enabled based on the values written into Register 2Eh and the
Host writing into the configuration index bits in CCR0.
Programming Internal Registers
PS012002-1201
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Product Specification
74
EEPROM Register
Address: SELECT 2Fh
Name: Bus Control
Type: Read/Write
Table 58. Bus Control Register: Address 2Fh
Bit Placement Bit Name
Description
Bit 0
EN_BHE_POL
When this bit is cleared, it enables the polarity of the
ATA_BHE output to be active High. When it is set, it
enables the polarity to be active Low. At Power-On Reset,
this bit defaults to clear. Also see Register 00h (Table 11).
Bit 1
EN_16_DUECE
When this bit is set, it enables word-to-byte access when in
memory mode. This mode allows a 16-bit host to access 8-
bit peripherals. When cleared, this bit disables word-to-
byte access mode. When set, this bit enables the ZX6017 to
generate two peripheral write or read strobes on the local
peripheral side when the host writes or reads 16 bits of
data. This mode allows a 16-bit host to read/write to 8-bit
peripheral device registers with one 16-bit access. When
this mode is enabled, and the ZX6017 is in memory mode,
the host gains access to the peripheral’s 8-bit registers by
selecting an even address usingPC_HCE1. The ZX6017
asserts the PC_WAIT pin, which allows the write or read
strobe to the peripheral device to be controlled through the
“DUECE_WIDTH” and “DUECE_ACCESS_DLY” bits in
the Bus control Register 2Fh and the externals peripherals
IOCHRDY signal if present (Figure 10). Figure 11 depicts
the PCMCIA to local peripheral data path information.
Bit 2
EN_DIV_ADDR
When set, this bit indicates that PCMCIA host address
lines A3, A2 and A1 are mapped to the local interface
address lines A2, A1 and A0. When cleared, PCMCIA
address lines A2, A1 and A0 are mapped to local interface
A2, A1 and A0.
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Product Specification
75
Table 58. Bus Control Register: Address 2Fh (Continued)
Bit Placement Bit Name
Description
Bit 3
EN_MAP_IO_MEM
When this bit is set, all memory accesses are mapped to
ATA_HIOR and ATA_HIOW. When it is cleared, all
memory accesses are mapped to ATA_MRD and
ATA_MWR.
Bit 5-4
Bit 7-6
DUECE_WIDTH
These bits set the ATA_HIOR/HIOW strobe width and are
clocked by PC_MCLK_IN /2. At Power-On Reset, they
default to 00.
DUECE_ACCESS_DLY
These bits set the ATA_HIOR/HIOW access delay and are
clocked by PC_MCLK_IN /2. At Power-On Reset, they
default to 00.
The ATA_HIOR/HIOW strobe width is three cycles minimum
(PC_MCLK_IN /2), plus IOCHRDY time (if any), plus width count
programmed in bits 5, 4 (Table 59).
Table 59. Strobe Width and Access Delay1
Bits
Bits
7
6
5
4
Delay
Width
7
6
5
4
Delay
Width
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
2
3
0
1
2
3
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
2
2
3
3
3
3
0
1
2
3
0
1
2
3
NOTES:
1. Each count equals PC_MCLK_IN /2.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
76
WORD-TO-BYTE OPERATION
Figure 10 illustrates Word-to-Byte timing and Figure 11 depicts the
Word-to-Byte Mode data path.
PC_HA<10:0>
PC_HCE1
PC_HWE
or PC_HOE
PC_WAIT
ATA_HA<2:0>
ATA_HCS<1:0>
Valid Even Address
Adr+1
ATA_HIOR
ATA_HIOW
ATA_IOCHRDY
Internal Clock
(PC_MCLK_IN /2)
Count 0
Count 0
1
2
Count 0
2
1
2
Count 0
Internal Strobe
Delay (HIOR/HIOW)
1
Count 0
Internal Access
Delay (HIOR/HIOW)
HIOR/HIOW strobe delay equals
IOCHRDY time plus strobe width
period programmed in the Bus
Control register 2Fh bits <5:4>
HIOR/HIOW strobe access
equals access delay period
programmed in the Bus Control
register 2Fh bits <7:6>
Figure 10. Word-to-Byte Timing
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
77
PCMCIA Host Writes
PCMCIA Host Reads
Data
PC_DATA<15-8>
PC_DATA<15-8>
PC_DATA<7-0>
Reciever
Data
MUX
ATA_DATA<7-0>
Data
Latch
PC_DATA<7-0>
ATA_DATA<7-0>
Figure 11. Word-to-Byte Mode Data Path
•
•
PCMCIA Host Write
PC_DATA<7–0> (Even Byte) written to ATA_DATA<7–0>
PC_DATA<15–8> (Odd Byte) written to ATA_DATA<7–0>
PCMCIA Host Read
The PCMCIA selects an even address, then the ZX6017 pulls WAIT
and reads the even register from the peripheral device, saves it in a
latch, increments the local peripherals address bus, then reads the odd
data byte and clears the PCMCIA WAIT pin.
ATA_DATA<7–0> (Even Byte) put onto PC_DATA<7–0>
ATA_DATA<7–0> (Odd Byte) put onto PC_DATA<15–8>
Table 60 describes the PCMCIA Host read and write address examples.
Programming Internal Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
78
Table 60. PCMICA Host Read and Write Address Examples1,2
ATA/IDE Memory General-
PCMCIA
Mode Purpose
Maps
Host Address 0
Host Address 2
Word Access Only
Peripheral Address 2, then
Host Address 0
Host Address 2
Peripheral Address 0, then 1
Peripheral Address 2, then 3
3
Host Address 4
Peripheral Address 4, then
5
Host Address 4
Peripheral Address 4, then 5, and so
on.
NOTES:
1. If the peripheral asserts the ATA_IOCS16, then this feature is aborted.
2. The host accesses must be on even addresses.
PS012002-1201
Programming Internal Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
79
Configuration Registers
INTRODUCTION
Support for the PCMCIA Configuration Registers is provided by the
ZX6017. Table 62 lists register decodes.
Three additional registers have been added to the ZX6017 to provide an
EEPROM link to support remote programming for attribute memory.
Table 62. PCMCIA Address xx0h to xx8h, Configuration Register Decode
WE OE REG CE1 CE2 Address
Action
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
xx0hx
xx0hx
xx2hx
xx2hx
xx4hx
xx4hx
xx6hx
xx6hx
xx8hx
xx8hx
Read Configuration Option Register
Write Configuration Option Register
Read Card Configuration and Status
Write Card Configuration and Status
Read Pin Replacement Register
Write Pin Replacement register
Read Socket and Copy Register
Write Socket and Copy Register
Read I/O Event Indication Status(*)
Write I/O Event Indication Status(*)
* The I/O Event Indication Status Register is only available on BA revisions of the ZX6017. (See device top mark
for revision level.)
Configuration Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
80
Table 63. ZiLOG EEPROM Programming Extensions1
WE OE REG CE1 CE2 Address
Action
0
1
0
1
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
7F0h
7F0h
7F2h
7F2h
7F4h
7F6h
Write EEPROM Address
Read EEPROM Status
Write EEPROM Data
Read EEPROM Data
EEPROM Command
Revision Register
* The I/O Event Indication Status Register is only available on BA revisions of the ZX6017. (See device top mark
for revision level.)
CONFIGURATION REGISTERS
EEPROM Register
Address: SELECT 0Ah
Name: PCMCIA Configuration Option Register CCR0
Type: Write/Read
Table 64. PCMCIA Configuration Option Register CCR0: Address 0Ah
Bit Placement Bit Name
Description
Bits 5–0
Bit 6
Configuration Index
Card configuration chosen by the system.
Level Request
SRESET
Level mode interrupts are selected when this bit is
set to 1. Pulse mode interrupts are selected when this
bit is set to 0.
Bit 7
Setting this bit to 1 places the card in the reset state.
PS012002-1201
Configuration Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
81
EEPROM Register
Address: SELECT 0Bh
Name: PCMCIA Card Status Register CCR1
Type: Write/Read
Table 65. PCMCIA Card Status Register CCR1: Address 0Bh
Bit Placement Bit Name
Description
Bit 0
Bit 1
Reserved
Interrupt
Must be 0.
This bit represents the state of the Interrupt request
signal.
Bit 2
Power Down
The card enters the power down state when this bit is
set to 1. Also see Register 2Bh (.
Bit 3
Bit 4
Bit 5
Audio
Set this bit to 1 for audio information.
Must be 0.
Reserved
IOIS8
System can only provide I/O cycles with an 8-bit D7-
D0 data path.
Bit 6
Bit 7
SIGCHG
Changed
This bit is set and reset by the host to allow a state
change from the status register. Also see Register
1Fh (Table 68).
Configuration Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
82
EEPROM Register
Address: SELECT 0Ch
Name: PCMCIA Pin Replacement Register CCR2
Type: Write/Read
Table 66. PCMCIA Pin Replacement Register CCR2: Address 0Ch
Bit Placement Bit Name
Description
Bit 0
Bit 1
RWPROT
Write Protect switch.
RRDY//BSY
When read, this bit represents the internal state of the
RRDY/BSY signal. When written, this bit acts as a
mark for writing the corresponding bit CRDY/BSY.
Bit 2
Bit 3
RBVD2
RBVD1
When read, this bit represents the internal state of the
Battery Voltage detection circuits on cards which
contain a battery. This signal represents the values on
PCMCIA pin BVD2. Also see Register 2Ch
(Table 54).
When read, this bit represents the internal state of the
Battery Voltage detection circuits on cards which
contain a battery. This signal represents the values on
PCMCIA pin BVD1. Also see Register 2Ch
(Table 54).
Bit 41
Bit 51
CWPROT
This bit is set to 1 when RWPROT changes state.
CRDY//BSY
This bit is set to 1 when the bit RRDY//BSY changes
state.
Bit 61
CBVD2
CBVD1
This bit is set to 1 when the corresponding bit
RBVD2 changes state.
Bit 71
This bit is set to 1 when the corresponding bit
RBVD1 changes state.
NOTES:
1. When this register is read, these four bits are reset.
PS012002-1201
Configuration Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
83
EEPROM Register
Address: SELECT 0Dh
Name: PCMCIA Socket and Copy Register CCR3
Type: Write/Read
Table 67. PCMCIA socket and Copy Register CCR3: Address 0Dh
Bit Placement Bit Name
Description
Bits 3–0
Socket Number
This field indicates to the card that it is located in the
nth socket. The first socket is numbered 0. This
permits cards designed to share a common set of I/O
ports to do so while remaining uniquely identifiable.
Bits 5–4
Copy Number
Reserved
Cards which indicate in their CIS that they support
more than one copy of identically configured cards,
should have a copy number (0 to MAX twin cards,
MAX = n – 1) written back to the socket and copy
register.
Bit 7
Configuration Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
84
EEPROM Register
Address: SELECT 1Fh
Name: PCMCIA I/O Event Indication CCR4
Type: Read/Write
Table 68. PCMCIA I/O Event Indication CCR4: Address 1Fh
Bit Placement Bit Name
Description
Bit 7
Bit 6
Bit 5
RSVDEVT3
RSVDEVT2
PIEvt
Input pin EXTP_STSCHG/RES2 sets this bit. When
this bit is set and the PIEnab bit is set to 1, the
changed bit in the Card configuration and status
register is also set to 1.
Input pin ATA_DATA8/RES1 sets this bit. When this
bit is set and the PIEnab bit is set to 1, the changed
bit in the Card configuration and status register is
also set to 1.
The card latches this bit to a 1on receipt of a
validated incoming packet over an RF channel. The
source of this signal is ATA_DATA9/PACK_IN.
When this bit is set to 1 and the PIEnab bit is set to 1,
the changed bit in the Card configuration and status
register is also set to 1. And, if the SIGCHG bit in the
card configuration status register has also been set by
the host, the STSCHG pin (pin 63) goes Low. The
host writing a 1 to this bit clears it to 0. Writing a 0 to
this bit has no effect.
Bit 4
RIEvt
This bit is latched to a 1 by the card after the receipt
of a 1 on the ATA/PDIAG/ATA_BHE/RING-IN
signal. When this bit is set to 1 and the RIEnab bit is
set to 1, the changed bit in the Card configuration
and status register is also set to 1. And, if the
SIGCHG bit in the card configuration status register
has also been set by the host, then the STSCHG pin
(pin 63) goes Low. The host writing a 1 to this bit
clears it to 0. Writing a 0 to this bit has no effect.
PS012002-1201
Configuration Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
85
Table 68. PCMCIA I/O Event Indication CCR4: Address 1Fh (Continued)
Bit Placement Bit Name
Description
Bit 3
Bit 2
Bit 1
Bit 0
RSVDENAB3
Setting this bit enables the Changed bit in the card
configuration and status register to be set when the
RSVDEVT3 bit is set. When this bit is cleared, this
feature is disabled.
RSVDENAB2
PIENAB
Setting this bit enables the Changed bit in the card
configuration and status register to be set when the
RSVDEVT2 bit is set. When this bit is cleared, this
feature is disabled.
Setting this bit enables the changed bit in the Card
configuration and status register to be set when the
PIEvt bit is set. When this bit is cleared, this feature
is disabled.
RIENAB
Setting this bit enables the changed bit in the Card
configuration and status register to be set when the
RIEvt bit is set. When this bit is cleared, this feature
is disabled.
Configuration Registers
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
86
PS012002-1201
Configuration Registers
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
87
Appendix A: Multifunction Pins
OVERVIEW OF MULTIFUNCTION PINS
ENABLE_RDY_BSY(REG_00 [4])
+READY/–BUSY
S
I1
I0
PC_RDY/BSY/IREQ/HINT
Mx2x1
LEVEL IRQ
I0
Mx2x1
PULSE_IREQ
I1
S
CCR0 [6]
EN_CTR_IRQ,REG_00 [5]
Figure 12. Z16017BA PC_RDY/BSY/IREQ/HINT Pin
Note:
Width of the PULSE_IREQ is: T = 192 x Tpc_mclk_in
Appendix A: Multifunction Pins
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
88
MEM_ACCESS
ATA_PDASP/EXTP_WP
EN EXTP WP, REG01 [5]
PC_WP//IOIS16//IOIS16
I0
I1
ATA_IOCS16
Mx2x1
S
IO_ACCES
EN_WP1, REG12 [3]
EN_WP1
EN_WP2
EN_WP3
EN_WP1, REG16 [3]
EN_WP1, REG1A [3]
Figure 13. Z86017BA PC_WP//IOIS16//IOIS16 Pin
PS012002-1201
Appendix A: Multifunction Pins
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
89
MEM_ACCESS
ATA_PDASP/EXTP_WP
EN EXTP WP, REG01 [5]
PC_WP//IOIS16//IOIS16
I0
I1
ATA_IOCS16
Mx2x1
S
IO_ACCES
EN_WP1, REG12 [3]
EN_WP1
EN_WP2
EN_WP3
EN_WP1, REG16 [3]
EN_WP1, REG1A [3]
Figure 14. Z16017BA PC_WP//IOIS16//IOIS16 Pin
Appendix A: Multifunction Pins
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
90
EN_DASP,REG2 [3]
EN_DASP_EXT,REG2 [7]
ATA_PDASP/EXTP_WP
EN_DASP_INT,REG2 [6]
PDASP_SET,REG2 [2]
PC/BVD2//SPKR//DASP/DREQ
I1
I0
EN_BVD,REG2C [6]
AUDIO_EN,CCR1 [3]
Mx2x1
EXTP_AUDIO
Mx4x1
I0
S
I1
I2
PCMCIA_MODE
ATA_DREQ/BVD1
IORD
S1
S0
I3
CE1
CE2
EN_SPKR,REG02 [5]
EN_DMA_ACK1,REG12 [7]
EN_DMA_ACK2,REG16 [7]
EN_DMA_ACK3,REG1A [7]
PC_INPACK/DREQ
I1
I0
Mx2x1
S
EN_PDIAG_EXT,REG04 [7]
ATA_PDIAG
AT_PDIAG
ATA_MODE
ATA_MODE
INT_PDIAG,REG02 [2]
EN_INT_PDIAG,REG04 [6]
EN_PDIAG,REG02 [1]
PC_BVD1//STSCHG//PDIAG
I0
I1
Mx2x1
S
EXTP_STSCHG
S
I1
I0
PCMCIA_MODE
Mx2x1
PC_REG//DACK
ATA_DACK/BVD2
MAP1_DMACK
MAP2_DMACK
MAP3_DMACK
PCMCIA_MODE
MAPn_DMACK = EN_DMA_ACKn & MAPn_ACC
Figure 15. Z86017BA (Overview of Internal Structure)
PS012002-1201
Appendix A: Multifunction Pins
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
91
EN_DASP,REG2 [3]
EN_DASP_EXT,REG2 [7]
ATA_PDASP/EXTP_W
EN_DASP_INT,REG2 [6]
PDASP_SET,REG2 [2]
I1
I0
PC/BVD2//SPKR//DASP/DREQ
I0
EN_BVD,REG2C [6]
AUDIO_EN,CCR1 [3]
Mx2x1
S
EXTP_AUDIO
Mx4x1
I1
I2
PCMCIA_MODE
ATA_DREQ/BVD1
IORD
CE1
S1
S0
I3
CE2
EN_SPKR,REG02 [5]
EN_DMA_ACK1,REG12 [7]
EN_DMA_ACK2,REG16 [7]
EN_DMA_ACK3,REG1A [7]
PC_INPACK/DREQ
I1
I0
BVD_CTRL,REG26 [7]
Mx2x1
S
EN_PDIAG_EXT,REG04 [7]
ATA_PDIAG
AT_PDIAG
ATA_MODE
ATA_MODE
INT_PDIAG,REG02 [0]
EN_INT_PDIAG,REG04 [6]
EN_PDIAG,REG02 [1]
PC_BVD1//STSCHG//PDIAG
I0
Mx2x1
EXTP_STSCHG
I1
S
S
I1
I0
PCMCIA_MODE
Mx2x1
PC_REG//DACK
ATA_DACK/BVD2
MAP1_DMACK
MAP2_DMACK
MAP3_DMACK
PCMCIA_MODE
MAPn DMACK = EN DMA ACKn & MAPn ACC
Figure 16. Z16017BA (Overview of Internal Structure)
Appendix A: Multifunction Pins
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
92
PS012002-1201
Appendix A: Multifunction Pins
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
93
Appendix B: Electrical Characteristics
and Timing
Table 69. Absolute Maximum Ratings
Parameter
Symbol Unit Min. Value Max. Value
Supply Voltage
VDD
VI
V
V
V
C
C
–0.5
–0.5
–0.5
–40
7.0
Input Voltage
VDD + 0.5
+ 0.5 VDD
+125
Output Voltage
VO
Storage Temperature
Temperature Under Bias
TSTG
TBIAS
–25
+85
Appendix B: Electrical Characteristics and Timing
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
94
Table 70. DC Electrical Characteristics
VCC = 3.3V ± 10%
TA = 0°C to +70°C
Typical
Maximum at 25°C Units Conditions
Sym. Parameter
Minimum
VIH
VIL
Input High Voltage
Input Low Voltage
0.7 VCC
–0.3
VCC
V
V
V
V
0.1 VCC
VOH Output High Voltage
VOH Output High Voltage
1.8
IOH = 4 mA
VCC – 100
mV
IOH = 100 µA
VOL Output Low Voltage
0.4
V
IOL = 4 mA
VRH Reset Input High Voltage
0.8 VCC
–0.3
VCC
0.1 VCC
2
V
VRl
IIL
Reset Input Low Voltage
Input Leakage
V
–2
µA
Test at 0V,
VCC
IOL
Output Leakage
–2
2
µA
Test at 0V,
VCC
IIR
Reset Input Current
Supply Current1
–80
4
µA
mA
µA
V
VRL = 0V
ICC
3
@ 20 MHz
ICC1 Standby Current2
300
VCC
0.8
250
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
–0.3
2.4
V
VOH Output High Voltage
VOH Output High Voltage
V
IOH = –6 mA
IOH = 100 µA
VCC –100
mV
V
VOL Output Low Voltage
0.4
V
IOL = 6 mA
PS012002-1201
Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
95
Table 70. DC Electrical Characteristics (Continued)
VCC = 3.3V ± 10%
TA = 0°C to +70°C
Typical
Maximum at 25°C Units Conditions
Sym. Parameter
Minimum
VRH Reset Input High Voltage
3.8
–0.3
–2
VCC
0.8
2
V
VRl
IIL
Reset Input Low Voltage
Input Leakage
V
µA
Test at 0V,
VCC
IOL
Output Leakage
–2
2
µA
Test at 0V,
VCC
IIR
Reset Input Current
Supply Current1
–80
5
µA
mA
µA
VRL = 0V
ICC
4
@ 20 MHz
ICC1 Standby Current2
350
300
1. All inputs driven to 0V, VCC and outputs floating.
2. EN_Pads Bit Set, PC_MCLK=0, EE_SK=0
Appendix B: Electrical Characteristics and Timing
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
96
INTERNAL ATTRIBUTE MEMORY TIMING
Table 71. Internal Attribute Memory Timing
(Speed Version: 300 ns)
No.
Symbol
Parameter
Minimum Maximum Units
1
TcR
Read Cycle Time
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
2
TaA
Address Access Time
300
300
150
100
100
3
TaCE
TaOE
TdisCE
TdisOE
TenCE
TenOE
TvA
Card Enable Time
4
Output Enable Access Time
Output Disable Time from CE
Output Disable Time from OE
Output Enable Time from CE
Output Enable Time from OE
Data Valid from Address Change
Address Setup Time
5
6
7
5
8
5
9
0
10
11
12
13
14
15
16
TsuA
30
20
0
ThA
Address Hold Time
TsuCE
ThCE
TvWToe
TwWT
TvWT
Card Enable Setup Time
Card Enable Hold Time
Wait Valid from OE
20
35
12
Wait Pulse Width
Data Setup for Wait Released
0
PS012002-1201
Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
97
1
PC_HA <10:0>
PC_REG
2
9
11
PC_HCE1
3
10
7
5
PC_HOE
PC_HWE
12
13
4
8
6
PC_DATA <15:0>
Note:
PC_REG is active Low for Attribute Memory reads only.
Figure 17. PCMCIA Read Memory Timing, No Wait States
Appendix B: Electrical Characteristics and Timing
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
98
1
PC_HA <10:0>
2
9
PC_REG
11
PC_HCE1
or
3
PC_HCE2
7
5
10
PC_HOE
PC_HWE
4
13
12
8
6
PC_DATA <15:0>
14
16
PC_WAIT
Note:
15
PC_REG is active Low for Attribute Memory reads only.
Figure 18. PCMCIA Read Memory Timing, Wait State Enabled
PS012002-1201
Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
99
Table 72. PCMCIA Memory Write Timing
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
No.
17
18
19
20
TcW
Write Cycle Time
200
120
20
150
80
100
60
ns
ns
ns
ns
TwWE
TsuA
Write Pulse Width
Address Setup Time
20
10
TsuAwe Address Setup Time for
WE
140
100
70
21
TsuCwe Card Enable Setup Time 140
for WE
100
70
ns
22
23
24
25
TsuDwe Data Setup Time for WE 60
50
20
20
40
15
15
ns
ns
ns
ns
ThD
Data Hold Time
30
30
TrecWE Write Recover Time
TdisOwe Output Disable Time from
WE
90
90
75
75
50
50
26
27
28
29
TdisOE Output Disable Time from
OE
ns
ns
ns
ns
TenWE Output Enable Time from
WE
5
5
5
TsuCwe Output Enable Setup from 10
WE
10
10
10
10
ThCwe
Card Enable Hold from
WE
10
30
31
TsuCE
ThCE
Card Enable Setup Time
Card Enable Hold Time
0
0
0
ns
ns
20
20
15
Appendix B: Electrical Characteristics and Timing
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
100
Table 72. PCMCIA Memory Write Timing (Continued)
No.
Symbol Parameter
Min. Max. Min. Max. Min. Max. Units
32
33
34
TvWTwe Wait Valid from WE
35
12
35
12
35
12
ns
µs
ns
TwWT
TvWT
Wait Pulse Width
WE High from Wait
Released
0
0
0
PS012002-1201
Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
101
17
PC_HA <10:0>
PC_REG
20
19
24
21
PC_HCE1
or
PC_HCE2
PC_HWE
18
PC_HOE
29
28
26
22
23
Data In
PC_DATA <15:0>
PC_DATA <15:0>
25
27
Data Out
Note: PC_REG is active Low for Attribute Memory reads only.
Figure 19. PCMCIA Write Memory Timing, No Wait States
Appendix B: Electrical Characteristics and Timing
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Z86017/Z16017 PCMCIA Interface Solution
Product Specification
102
17
PC_HA <10:0>
PC_REG
20
24
21
PC_HCE1
or
PC_HCE2
30
31
19
PC_HWE
18
PC_HOE
29
28
22
23
PC_DATA <15:0>
26
PC_WAIT
Note:
33
PC_REG is active Low for Attribute Memory reads only.
Figure 20. PCMCIA Write Memory Timing, Wait State Enabled
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Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
103
Table 73. I/O Read Timing Specification
No.
Symbol
Parameter
Minimum Maximum Units
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TdIORD
ThIORD
twIORD
TsuAiord
ThAiord
TsuCEiord
ThCEiord
Data Delay After IORD
Data Hold Following IORD
IORD Width Time
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
165
70
20
5
Address Setup Before IORD
Address Hold Following IORD
CE Setup Before IORD
CE Hold Following IORD
20
5
TsuRGiord REG Setup Before IORD
ThRGiord
TdIPKiord
TdIPKiord
TdIOISad
TdIOISadr
TdWiord
TdWTr
REG Hold Following IORD
INPACK Delay to IORD
INPACK Delay from IORD
IOIS16 Delay from Address
IOIS16 Delay Rise from Address
Wait Delay from IORD
0
0
45
45
35
35
35
35
12
Data Delay from Wait Rising
Wait Width Time
TwWT
Appendix B: Electrical Characteristics and Timing
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Z86017/Z16017 PCMCIA Interface Solution
Product Specification
104
PC_HA <11:0>
3595
PC_REG
42
43
3576
PC_HCEx
40
41
3556
PC_IORD
38
PC_INPACK
44
45
PC_IOIS16
46
47
PC_WAIT
48
49
36
50
PC_DATA <15:0> (In)
Data
Figure 21. I/O Read Timing
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Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
105
Table 74. I/O Write Timing Specification
No.
Symbol
Parameter
Minimum Maximum Units
51
52
53
54
55
56
57
58
59
60
61
62
63
TsuIOWR
ThIOWR
TwIOWR
TsuAiowr
ThAiowr
Data Setup before IOWR
Data Hold after IOWR
IOWR Width Time
60
30
165
70
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Address Setup to IOWR
Address Hold after IOWR
TsuCEiowr CE Setup before IOWR
ThCEiowr CE Hold after IOWR
TsuRGiowr REG Setup before IOWR
20
5
ThRGiowr
TdIOISadr
REG Hold after IOWR
0
IOIS16 Delay Falling from Address
35
35
35
12
TIdIOISadr IOIS16 delay Rising from Address
TdWTiowr Wait Delay Falling from IOWR
TwWT
Wait Width Timing
Appendix B: Electrical Characteristics and Timing
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Product Specification
106
PC_HA <11:0>
55
PC_REG
58
59
57
PC_HCEx
56
53
PC_IOWR
54
61
PC_IOIS16
63
PC_WAIT
60
51
62
52
PC_DATA <15:0>
Data Out
Figure 22. I/O Write Timing
Table 75. Skew Timing Between PCMCIA And ATA/IDE or
Peripheral Bus
No.
Symbol
Parameter
Minimum
Maximum
Units
64
65
66
67
68
TskADR
TskI/Of
Address Skew
I/O Fall Skew
I/O Rise Skew
Mem Fall Skew
Mem Rise Skew
0
0
0
0
0
25
25
25
25
25
ns
ns
ns
ns
ns
TskI/Or
TskMEMf
TskMEMr
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Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
107
PC_HA <10:0>
ATA_HA <2:0>
64
PC_DATA <15:0>
64
ATA_DATA <15:0>
PC_HIOW, /PC_HIOR
PC_HCE1, PC_HCE2
65
66
ATA_HIOW, /ATA_HIOR
ATA_HCS0, ATA_HCS1
PC_WE, /OE
67
68
ATA_HIOW, ATA_HIOR
ATA_MRD, ATA_MWR
Figure 23. Skew Timing Between PCMCIA and ATA/IDE or
Peripheral Bus
Appendix B: Electrical Characteristics and Timing
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Product Specification
108
017 DEVICE SLEW DELAY
50
40
35
30
ns
25
20
10
0
15
25
50
Output Load (pF)
100
Figure 24. 017 Slew Delay Derating Curve (Typical)
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Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
109
Table 76. Serial Interface Timing
No.
Symbol
Parameter
Minimum
Maximum
Units
69
70
71
72
73
74
75
76
77
TpMCKin
TsuCS
Master Clock In Period
CS Setup to CLK time
CS Hold after CLK
Data Hold Time
50
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ThCS
ThDout
TsuDout
ThDin
10
25
0
Data Setup Time
Data Hold Time
TsuDin
TpCKw
TpCKs
Data Setup Time
25
200
200
Clock Period, Master
Clock Period, Slave
Appendix B: Electrical Characteristics and Timing
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
110
PC_MCLK_IN
69
76
EE_CS
EE_SK
Read
Sync Bit
1
1 0
SB CMD
Address
EE_DO
EE_DI
Master Mode Read EEPROM Timing
Data
Data
Write
Address
Sync Bit
1
0 1
SB CMD
EE_DO
EE_DI
Master Mode Write EEPROM Timing
Ready
Busy
EE_CS
EE_SK
70
71
73
72
EE_DO
EE_IN
75
74
Figure 25. FMaster Mode Read EEPROM Timing
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Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
111
EE_CS
77
EE_SK
EE_DI
8-Bit Address
Command
D7
D2D1
D3D2D1D0
D6D5D4D3
D0D7 D6D5D4
X
1 0 X
X X X
1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Tri-State
Tri-State
EE_DO
Slave Read Command
EE_CS
EE_SK
EE_DI
D7
D6D5D4 D3 D2D1D0D7 D6 D5 D4 D3 D2 D1D0D7
D6D5D4 D3 D2D1D0
Data
X
0 1 X
X X X
1
8-Bit Address
Command
EE_DO
Tri-State
Tri-State
Slave Write Command
EE_CS
70
71
EE_SK
EE_DI
75
74
73
72
Tri-State
Tri-State
EE_DO
Slave Timing
Figure 26. Slave Interface Timing (Read)
Appendix B: Electrical Characteristics and Timing
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Z86017/Z16017 PCMCIA Interface Solution
Product Specification
112
PS012002-1201
Appendix B: Electrical Characteristics and Timing
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
113
Appendix C: Timing Examples
PC_HRESET//HRESET
/POR
/ATA_HRESET
40 µs/@ 20 MHz
65 µs/@ 20 MHz
EE_CE
65 µs/@ 20 MHz
PCMCIA Mode Bit 5 Register 03H = 1
40 µs/@
20 MHz
5 EE accesses
in Master mode
65 µs/@ 20 MHz
65 µs/@ 20 MHz
65 µs/@ 20 MHz + EE
accesses in Master Mode
Vcc
/ATA_HRESET
Z86017BA
Vcc
PC_HRESET//HRESET
Figure 27. Z16017BA Reset Timing PCMCIA Mode
Appendix C: Timing Examples
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Product Specification
114
Figure 28. PCMCIA ATA/IDE 16-Bit I/O Write
(Register 24 = 01, Internal IOIS 16 is selected)
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Appendix C: Timing Examples
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
115
Figure 29. PCMCIA ATA / IDE 8-Bit Long Read
(Reading 512-byte data plus 6-byte ECC)
Appendix C: Timing Examples
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
116
PS012002-1201
Appendix C: Timing Examples
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
117
Appendix D: Packaging and Ordering
Information
20 MHZ PCMCIA ADAPTER CHIPS
Z86017
Z86M17
Z16017
Z16M17
100-Pin VQFP
Z8601720ASC
100-pin VQFP
Z86M1720ASC
100-Pin VQFP
Z1601720ASC
100-Pin VQFP
Z16M1720ASC
For fast results, contact your local ZiLOG sales office for assistance in
ordering the part desired.
Package
A = VQFP
Temperature
S = 0° to +70° C
Speed
20 = 20 MHz
Environmental
C = Plastic Standard
Appendix D: Packaging and Ordering Information
PS012002-1201
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
118
Z 16017 20 A S C
is a Z16017, 20 MHz, VQFP, 0 °C to +70 °C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
Figure 30. Example Package Name
PS012002-1201
Appendix D: Packaging and Order-
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
119
Package Dimensions
Figure 31. 100-Lead VQFP Package Diagram
Appendix D: Packaging and Ordering Information
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Product Specification
120
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Appendix D: Packaging and Order-
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
121
Appendix E: PCMCIA Interface Devel-
opment Kit
GENERAL DESCRIPTION
The Z8601700ZCO Development Kit allows easy evaluation of the
functions and capabilities of the Z86017 PCMCIA Interface Adapter. The
board provides a ZIF socket for easy insertion and removal of the
Z86017, as well as a full pin-out header for access to all signals. The
board also provides breadboard space to assist in development.
Power to the Z86017 can either be supplied through a common point for
current measurements applied through the interface, or supplied through a
separate power connector. Programming the Z86017 is accomplished
through the SPI port of a microcontroller or through the on-board
EEPROM. The main clock source is supplied through the interface or
through the on-board clock.
Z86017 SPECIFICATIONS
Power Requirements:
3.0V < VCC < +5.5V
Dimensions
Length: 7.6 in. (19.3 cm)
Width: 4.5 in. (11.4 cm)
Appendix E: PCMCIA Interface Development Kit
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Z86017/Z16017 PCMCIA Interface Solution
Product Specification
122
KIT CONTENTS
Evaluation Board
•
•
•
•
•
•
•
•
•
•
Z86017 PCMCIA Interface Adapter Device
100-Pin VQFP ZIF Socket
256 X 8-Byte EEPROM
20 MHz Oscillator
Headers for full Z86017 pin-out
Headers for access for PCMCIA signals
Headers for connection to AT-Bus (on both Host and ATA side)
Headers for connection to PCMCIA Extender Card
Header for intelligent peripheral programming of EEPROM
Power Connector
ZPCMCIA0ZDP PCMCIA Extender Card
Cables
•
•
•
Two 6-inch, 34-pin IDC to 34-pin IDC Cables
Power Cable with 1.0A Fuse
Power Cable with Banana Plugs
Software
•
Example Initialization Code
PS012002-1201
Appendix E: PCMCIA Interface De-
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
123
Documentation
•
•
•
Z8601700ZCO Evaluation Kit User’s Manual
Z86017/Z16017 Reference Manual
Product Registration Card
Appendix E: PCMCIA Interface Development Kit
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Product Specification
124
PS012002-1201
Appendix E: PCMCIA Interface De-
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