Z53C80SCSI [ZILOG]
SMALL COMPUTER SYSTEM INTERFACE (SCSI); 小型计算机系统接口（ SCSI ）
| 型号： | Z53C80SCSI |
| 厂家： | 
ZILOG, INC. |
| 描述： | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| 文件： | 总40页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z
ILOG
Z53C80 SCSI
PRODUCT SPECIFICATION
Z53C80
SMALL COMPUTER
SYSTEM INTERFACE (SCSI)
FEATURES
■ Pin Compatible with the Industry Standard 5380
■ Asynchronous Interface (Supports 3 MB/s)
■ 44-Pin PLCC or 48-Pin DIP Package Styles
■ DMA or Programmed I/O Data Transfers
■ Arbitration Support
■ DirectSCSIBusInterfacewithOn-Board48mADrivers
■ Supports Target and Initiator Roles
■ Meets SCSI Protocol as Defined in ANSI X3.131-1986
Standard
■ Supports Normal or Block Mode DMA
■ Memory or I/O Mapped CPU Interface
■ Added “Glitch Eater” Enhancement to Minimize Bus
Reflection
GENERAL DESCRIPTION
The Z53C80 SCSI (Small Computer System Interface)
controller is designed to implement the SCSI protocol as
defined by the ANSI X3.131-1986 standard, and it is fully
compatible with the industry standard 5380. The device is
capable of operating both as a Target and as an Initiator.
Specialhigh-currentopen-drainoutputsenableittodirectly
interface to the SCSI bus. The Z53C80 has the necessary
interface hook-ups which allow the system CPU to
communicate with it as with any other peripheral device.
The CPU can read from, or write to, the SCSI registers
which are addressed as standard or memory-mapped
I/Os.
The added enhancement known as the “Glitch Eater” is
used to minimize effects of bus reflection on improperly
terminated SCSI bus applications. The high frequency
reflections that can occur on the SCSI bus are filtered out,
reducingthesensitivityoftheinputs,specifically/REQand
/ACKtobussignalreflections.Figure1showsaworstcase
input waveform (labeled A), along with the filtered input
(labeled B) and the output of a Schmitt trigger used to
provide the hysteresis required on SCSI inputs (labeled
C). This enhancement is a requirement for the device to
function properly in a Apple Macintosh® environment.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
The Z53C80 increases the system performance by
minimizing the CPU intervention in DMA operations which
the SCSI controls. The CPU is interrupted by the SCSI
when it detects a bus condition that requires attention. It
also supports arbitration and reselection. The Z53C80 has
theproperhandshakesignalstosupportnormalandblock
modeDMAoperationswithmostDMAcontrollersavailable.
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
® Apple Macintosh is a registered trademark of Apple Computer, Inc.
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GENERAL DESCRIPTION (Continued)
5.50
5.00
C
4.50
C
4.00
3.50
3.00
A
B
A&B
B
2.50
A
A
2.00
1.50
1.00
.50
A
B
A
B
0
C
-.50
0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
180.0
Figure 1. Worst Case Unfiltered Input (A), Filtered Input (B),
Output of Schmitt-Trigger Used to Provide Hysteresis (C).
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Z53C80 SCSI
/DB7-/DB0,
/DBP
/ACK
/ATN /BSY /MSG
I//O
C//D /REQ /RST /SEL
48 mA SCSI Transceivers
/IOR
/IOW
/CS
Interface
Control
Logic
Data
Input
Register
Data
Output
Register
CPU BUS
Interface
/RESET
A2-A0
DMA
Logic
Interrupt
Logic
Control
Registers
D7-D0
Figure 2a. SCSI Block Diagram
D7-D0
A2-A0
/IOR
/DB7-/DB0, /DBP
/ACK
/ATN
/BSY
/MSG
/IOW
/CS
Z53C80
SCSI
/RESET
I//O
/DACK
/EOP
C//D
/REQ
/RST
DRQ
READY
/SEL
VCC
IRQ
GND
Figure 2b. SCSI Pin Functions
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GENERAL DESCRIPTION (Continued)
/DB7
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
/DB6
/DB5
GND
/DB4
/DB3
/DB2
N/C
/RST
GND
/BSY
2
3
6
5
4
3
2
1
44 43 42 41 40
/RESET
IRQ
7
39
4
/DB2
/DB1
/DB0
GND
38
37
36
35
34
33
32
31
30
29
/SEL
/ATN
5
8
DRQ
6
9
N/C
7
/EOP
/DACK
GND
10
11
12
13
14
15
16
17
/RESET
IRQ
8
/DBP
/REQ
/ACK
I//O
/DB1
/DB0
GND
/DBP
/REQ
/ACK
I//O
Z53C80
SCSI
9
READY
DRQ
/EOP
/DACK
GND
READY
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A0
A1
Z53C80
SCSI
GND
C//D
A2
/CS
/MSG
18 19 20 21 22 23 24 25 26 27 28
GND
C//D
/MSG
N/C
A1
A2
N/C
/CS
D0
Figure 4. 44-Pin PLCC Pin Assignments
/IOW
/IOR
D7
D1
D2
D3
D6
D4
D5
VCC
Figure 3. 48-Pin DIP Pin Assignments
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Z53C80 SCSI
PIN DESCRIPTION
Microprocessor Bus
/IOR /I/O Read (Input, active Low). This signal is used to
read an internal register selected by /CS and A2-A0. The
Input Data Register can also be selected by this signal
when /DACK is active during DMA transfers.
A2-A0 Address Lines (Input). Address lines are used to
access all internal registers with /CS, /IOR, and /IOW.
/CS /Chip Select (Input, active Low). /CS, in conjunction
with /RD or /WR, enables the internal register selected by
A2-A0, to be read from or write to. /CS and /DACK must
never be active simultaneously.
/IOW /I/O Write (Input, active Low). This signal is used to
writetoaninternalregisterselectedby/CSandA2-A0.The
Output Data Register can also be selected by this signal
when used with /DACK during DMA transfers.
/DACK /DMA Acknowledge (Input, active Low). /DACK, in
conjunction with /IOR and /IOW, is used to enable reading
or writing the SCSI I/O Data Registers when in the DMA
Mode. WhentheDRQhasacknowledgedthatthebytehas
beensuccessfullytransferredtoorfromtheDMAcontroller,
this signal is asserted. /DACK and /CS must never be
active simultaneously.
IRQInterrupt Request(Output, active High). IRQ alerts the
microprocessorofanerrorconditionoraneventcompletion.
Most of the interrupts are individually maskable.
READY Ready (Output, active High). This signal can be
used to control the data transfer handshaking of block
mode DMA transfers. READY is asserted to indicate that
the chip is ready to transfer data and remains false after a
transfer until the chip is ready for another DMA transfer.
READY is always asserted when the DMA Mode Bit is a
zero.
DRQ DMA Request (Output, active High). This signal is
asserted when the chip is ready to transfer a data byte to
and from the DMA controller. The DMA Request will be
asserted only if the DMA Mode bit (Register 2, Bit 1) is set.
The transfer is complete upon reception of /DACK.
/RESET /Reset (Input, active Low). /RESET clears all
registers and has no effect upon the SCSI /RST signal.
Therefore it does not reset the SCSI bus.
D7-D0 Data Lines (Bi-directional; Tri-State, active High).
The Data Bus lines carry data and commands to and from
SCSI. D7 is the most significant bit of this bus.
/EOP /End of Process (Input, active Low). To terminate a
DMA transfer, this signal is asserted. The current byte will
be transferred but no additional bytes will be requested if
asserted during a DMA cycle. /EOP can be used to
generate an interrupt when it is received from a DMA
Controller.
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SCSI BUS
The following signals are all Bi-directional, active Low,
open-drain, with 48 mA sink capacity. All pins interface
directly with the SCSI Bus.
/MSG /Message (Bi-directional, Open-Drain, Active Low).
The Target drives /MSG active during the Message Phase
and is received by the Initiator.
/ACK /Acknowledge (Bi-directional, Open-Drain, Active
Low). /ACK is driven by the Initiator and indicates an
acknowledgmentforaSCSIdatatransfer./ACKisreceived
as a response to the /REQ Signal in the Target role.
/REQ /Request (Bi-directional, Open-Drain, Active Low).
Received by the Initiator and driven by a Target, /REQ
indicates a request for an SCSI data-transfer handshake.
/RST SCSI Bus RESET (Bi-directional, Open-Drain, Active
Low). The /RST signal shows a SCSI Bus RESET condition
has occurred.
/ATN /Attention (Bi-directional, Open-Drain, Active Low).
/ATN is driven by the Initiator and indicates an attention
condition./ATNisreceivedandisrespondedtobyentering
the Message Out Phase in the Target role.
/DB7-/DB0,/DBP /Data Bits, /Parity Bits (Bi-directional,
Open-Drain, Active Low). These eight data bits (/DB7-/
DB0), plusaparitybit(/DBP)formtheSCSIDataBus. /DB7
has the highest priority during the Arbitration phase and is
the most significant bit (MSB). Data parity is odd and is
always generated and optionally checked, which is not
valid during Arbitration.
/BSY /Busy(Bi-directional, Open-Drain, Active Low). /BSY
indicatesthattheSCSIBusisbeingoccupied./BSYcanbe
driven by both the Target and the Initiator device.
/C//D /Control//Data (Bi-directional, Open-Drain, Active
Low). /C//D indicates Control or Data information is on the
SCSI Bus. This signal is driven by a Target and is received
by the Initiator.
/SEL /Select (Bi-directional, Open-Drain, Active Low).
/SEL is used by a Target to select an Initiator, or by an
Initiator to reselect a Target.
/I//O/Input//Output(Bi-directional,Open-Drain,ActiveLow).
/I//O is driven by a Target and controls the direction of data
transfer on the SCSI Bus. When asserted, this signal
indicates input to the Initiator. When not asserted, this
signal indicates output from the Initiator. This signal is also
used to recognize the difference between the Selection
and Reselection Phases.
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Z53C80 SCSI
FUNCTIONAL DESCRIPTION
Address: 0
(Read Only)
General. The Small Computer System interface (SCSI)
devicehasasetofeightregistersthatarecontrolledbythe
CPU. By reading and writing the appropriate registers, the
CPU may initiate any SCSI Bus activity or may sample and
assert any signal on the SCSI Bus. This allows the user to
implementalloranyoftheSCSIprotocolinsoftware.These
registers are read (written) by activating /CS with an
addressonA2-A0andthenissuinga/RD(/WR)pulse. This
section describes the operation of the internal registers
(Table 1).
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Table 1. Register Summary
Address
A2 A1 A0 R/W Register Name
0
0
0
0
0
0
0
0
1
R
W
Current SCSI Data
Output Data
Figure 5. Current SCSI Data Register
R/W Initiator Command
0
0
1
1
1
0
0
1
0
R/W Mode
R/W Target Command
OutputDataRegister.Address0(WriteOnly).TheOutput
Data Register (Figure 6) is a write-only register that is used
to send data to the SCSI Bus. This is accomplished by
either using a normal CPU write, or under DMA control, by
using /WR and /DACK. This register also asserts the
proper ID bits on the SCSI Bus during the Arbitration and
Selection phases.
R
Current SCSI Bus Status
1
1
1
0
0
0
0
1
1
W
R
W
Select Enable
Bus and Status
Start DMA Send
1
1
1
1
1
1
1
1
0
0
1
1
R
W
R
Input Data
Start DMA Target Receive
Reset Parity/Interrupt
Start DMA Initiator Receive
Address: 0
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
W
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Data Registers. The data registers are used to transfer
SCSIcommands,data,status,andmessagebytesbetween
the microprocessor Data Bus and the SCSI Bus. The SCSI
does not interpret any information that passes through the
dataregisters.Thedataregistersconsistofthetransparent
CurrentSCSIDataRegister, theOutputDataRegister, and
the Input Data Register.
Current SCSI Data Register. Address 0 (Read Only). The
Current SCSI Data Register (Figure 5) is a read-only
registerwhichallowsthemicroprocessortoreadtheactive
SCSI Data Bus. This is accomplished by activating /CS
with an address on A2-A0 and issuing a /RD pulse. If parity
checking is enabled, the SCSI Bus parity is checked at the
beginning of the read cycle. This register is used during a
programmed I/O data read or during Arbitration to check
for higher priority arbitrating devices. Parity is not
guaranteed valid during Arbitration.
Figure 6. Output Data Register
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FUNCTIONAL DESCRIPTION (Continued)
(Read Only)
Input Data Register. Address 6 (Read Only). The input
Data Register (Figure 7) is a read-only register that is used
to read latched data from the SCSI Bus. Data is latched
either during a DMA Target receive operation when /ACK
goes active or during a DMA Initiator receive when /REQ
goes active. The DMA Mode bit (Mode Register bit 1) must
be set before data can be latched in the Input Data
Register. This register is read under DMA control using
/RD and /DACK. Parity is optionally checked when the
Input Data Register is loaded.
Address: 1
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
Lost Arbitration
Address: 6
(Read Only)
Arbitration in Progress
Assert /RST
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 8. Initiator Command Register
(Register Read)
Address: 1
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
"0"
Figure 7. Input Data Register
Initiator Command Register. Address 1 (Read/Write).
The Initiator Command Register (Figures 8 and 9) are read
and write registers which assert certain SCSI Bus signals,
monitors those signals, and monitors the progress of bus
arbitration. Many of these bits are significant only when
being used as an Initiator; however, most can be used
during Target role operation.
Test Mode
Assert /RST
Figure 9. Initiator Command Register
(Register Write)
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Z53C80 SCSI
The following paragraphs describe the operation of all bits
in the Initiator Command Register.
Bit 6. Test Mode (Write Bit). Bit 6 is written during a test
environment to place all output drivers, in the high
impedance state.
Bit 0. Assert Data Bus. The Assert Data Bus bit, when set,
allows the contents of the Output Data Register to be
enabled as chip outputs on the signals /DB7-/DB0. Parity
is also generated and asserted on /DBP.
Bit 6. AIP (Arbitration in Process - Read Bit). Bit 6 is used
to determine if Arbitration is in progress. For this bit to be
active, the Arbitrate bit (Mode Register, bit 0) must have
been set previously. It indicates that a Bus-Free condition
has been detected and that the chip has asserted /BSY
and put the contents of the Output Data Register onto the
SCSI Bus. AIP will remain active until the Arbitrate bit is
reset.
When connected as an Initiator, the outputs are only
enabled if the Target Mode bit (Mode Register, bit 6) is
False, the received signal I//O is False, and the phase
signals C//D, I//O, and /MSG match the contents of the
Assert C//O, Assert I//O and Assert /MSG in the Target
Command Register.
Bit 7. Assert/RST. Whenever a one is written to bit 7 of the
Initiator Command Register, the /RST signal is asserted on
theSCSIBus.The/RSTsignalwillremainasserteduntilthis
bit is reset or until an external /RESET occurs. After this bit
is set (1), IRQ goes active and all internal logic and control
registers are reset (except for the interrupt latch and the
Assert/RST bit). Writing a zero to bit 7 of the Initiator
Command Register deasserts the /RST signal. The status
of this bit is monitored by reading the Initiator Command
Register.
This bit should also be set during DMA send operations.
Bit 1. Assert/ATN/. Bit 1 may be asserted on the SCSI Bus
by setting this bit to a 1 if the Target Mode bit (Mode
Register, bit 6) is False, /ATN is normally asserted by the
initiator to request a Message Out bus phase. Note that
since Assert/SEL and Assert/ATN are in the same register,
aselectwith/ATNmaybeimplementedwithoneCPUwrite
/ATN may be deasserted by resetting this bit to zero. A
read on this register simply reflects the status of this bit.
Mode Register. Address 2 (Read/Write). The Mode
Register controls the operation of the chip. This register
determines whether the SCSI operates as an Initiator or a
Target, whether DMA transfers are being used, whether
parityischecked,andwhetherinterruptsaregeneratedon
various external conditions. This register is read to check
the value of these internal control bits (Figure 10).
Bit 2. Assert/SEL. Writing a 1 into this bit position asserts
/SEL onto the SCSI Bus. /SEL is normally asserted after
Arbitration has been successfully completed /SEL may be
disabled by resetting bit 2 to a 0. A read of this register
reflects the status of this bit.
Bit 3. Assert/BSY. Writing a 1 into this bit position asserts
/BSY onto the SCSI Bus. Conversely, a 0 resets the /BSY
signal. Asserting /BSY indicates a successful selection or
reselection. Resetting this bit creates a Bus-Disconnect
condition. Reading this register reflects bit status.
Address: 2
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Arbitrate
DMA Mode
Bit 4. Assert/ACK. Bit 4 is used by the bus initiator to assert
/ACK on the SCSI Bus. In order to assert /ACK, the Target
Mode bit (Mode Register, bit 6) must be False. Writing a
zero to this bit deasserts /ACK. Reading this register
reflects bit status.
Monitor /BSY
Enable /EOP Interrupt
Enable Parity Interrupt
Enable Parity Checking
Target Mode
Bit 5. “0” (Write Bit). Bit 5 should be written with a 0 for
proper operation.
"0"
Bit 5. LA (Lost Arbitration - Read Bit). Bit 5, when active,
indicates that the SCSI detected a Bus-Free condition,
arbitrated for use of the bus by asserting /BSY and its ID on
the Data Bus, and lost Arbitration due to /SEL being
asserted by another bus device. This bit is active only
when the Arbitrate bit (Mode Register, bit 0) is active.
Figure 10. Mode Register
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FUNCTIONAL DESCRIPTION (Continued)
Bit 0. Arbitrate. The Arbitrate bit is set (1) to start the
Arbitrationprocess.Priortosettingthisbit,theOutputData
Register should contain the proper SCSI device ID value.
OnlyonedatabitshouldbeactiveforSCSIBusArbitration.
The SCSI waits for a Bus-Free condition before entering
the Arbitration phase. The results of the Arbitration phase
is determined by reading the status bits LA and AIP
(Initiator Command Register, bits 5 and 6, respectively).
Bit 6. Targetmode. The Targetmode bit allows the SCSI to
operate as either a SCSI Bus Initiator, bit reset (0), or as a
SCSI Bus Target device, bit set (1). If the signals /ATN and
/ACK are to be asserted on the SCSI Bus, the Targetmode
bit must be reset (0). If the signals C//D, I//O, /MSG, and
/REQ are to be asserted on the SCSI Bus, the Targetmode
bit must be set (1).
Bit 7. 0. Bit 7 should be written with a zero for proper
operation.
Bit 1. DMA Mode. The DMA Mode bit is normally used to
enable a DMA transfer and must be set (1) prior to writing
Start DMA Send Register, Start DMA Target Receive
Register, and Start DMA Initiator Receiver Register. These
three registers are used to start DMA transfers. The Target
Mode bit (Mode Register, bit 6) must be consistent with
writes to Start DMA Target Receive and Start DMA Initiator
Receive Registers [i.e., set (1) for a write to start DMA
TargetReceiveRegisterandset(0)forawritetoStartDMA
Initiator Receive Register]. The control bit Assert Data Bus
(Initiator Command Register, bit 0) must be True (1) for all
DMA send operations. In the DMA mode, /REQ and /ACK
are automatically controlled.
TargetCommandRegister.Address3(Read/Write).When
connected as a target device, the Target Command
Register(Figure11)allowstheCPUtocontroltheSCSIBus
InformationTransferphaseand/ortoassert/REQbywriting
this register. The Targetmode bit (Mode Register, bit 6)
must be True (1) for bus assertion to occur. The SCSI Bus
phases are described in Table 2.
Table 2. SCSI Information Transfer Phase
Bus Phase
ASSERT ASSERT ASSERT
I//O
C//D
/MS
The DMA Mode bit is not reset upon the receipt of an /EOP
signal. Any DMA transfer is stopped by writing a zero into
this bit location; however, care must be taken not to cause
/CS and /DACK to be active simultaneously.
Data Out
Unspecified
Command
0
0
0
0
0
1
0
1
0
Message Out
Data In
Unspecified
0
1
1
1
0
0
1
0
1
Bit 2. Monitor Busy. The Monitor Busy bit, when True (1),
causes an interrupt to be generated for an unexpected
loss of /BSY. When the interrupt is generated due to loss of
/BSY, the lower six bits of the Initiator Command Register
are reset (0) and all signals are removed from the SCSI
Bus.
Status
Message In
1
1
1
1
0
1
When connected as an Initiator with DMA Mode True, if the
phase lines I//O, C//D, and /MSG do not match the phase
bits in the Target Command Register, a phase mismatch
interrupt is generated when /REQ goes active. To send
data as an Initiator, the Assert I//O, Assert C//D, and Assert
/MSGbitsmustmatchthecorrespondingbitsintheCurrent
SCSI Bus Status Register. The Assert /REQ bit (bit 3) has
no meaning when operating as an Initiator.
Bit 3. Enable/EOP interrupt. The enable /EOP interrupt,
when set (1), causes an interrupt to occur when the /EOP
(EndofProcess)signalisreceivedfromtheDMAcontroller
logic.
Bit 4. Enable Parity Interrupt. The Enable Parity Interrupt
bit, when set (1), will cause an interrupt (IRQ) to occur if a
parity error is detected. A parity interrupt will only be
generated if the Enable Parity Checking bit (bit 5) is also
enabled (1).
Bits 4, 5, and 6 are not used.
Bit 5. Enable Parity Checking. The Enable Parity Checking
bit determines whether parity errors are ignored or saved
in the parity error latch. If this bit is reset (0), parity is
ignored. Conversely, if this bit is set (1), parity errors are
saved.
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Z53C80 SCSI
Address: 4
(Read Only)
Bit 7. Last Byte Sent (Read Only). The End Of DMA
Transfer bit (Bus and Status Register, bit 7) only indicates
when the last byte was received from the DMA controller.
The Last Byte Sent bit can be used to flag that the last byte
of the DMA send operation has been transferred on the
SCSI Data Bus.
D7 D6 D5 D4 D3 D2 D1 D0
/DBP
/SEL
I//O
Address: 3
(Read/Write)
C//D
D7 D6 D5 D4 D3 D2 D1 D0
/MSG
/REQ
/BSY
/RST
Assert I//O
Assert C//D
Assert /MSG
Assert /REQ
"X"
Figure 12. Current SCSI Bus Status Register
Last Byte Sent
Address: 4
(Write Only)
Figure 11. Target Command Register
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Current SCSI Bus Status Register. Address 4 (Read
Only). The Current SCSI Bus Register is a read-only
register which is used to monitor seven SCSI Bus control
signals, plus the Data Bus parity bit. For example, an
Initiator device can use this register to determine the
current bus phase and to poll /REQ for pending data
transfers. This register may also be used to determine why
a particular interrupt occurred. Figure 12 describes the
Current SCSI Bus Status Register.
Select Enable Register. Address 4 (Write Only). The
Select Enable Register (Figure 13) is a write-only register
which is used as a mask to monitor a signal ID during a
selection attempt. The simultaneous occurrence of the
correct ID bit, /BSY FALSE, and /SEL TRUE will cause an
interrupt.Thisinterruptcanbedisabledbyresettingallbits
in this register. If the Enable Parity Checking bit (Mode
Register, bit 5) is active (1), parity is checked during
selection.
Figure 13. Select Enable Register
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FUNCTIONAL DESCRIPTION (Continued)
Bit 4. Interrupt Request Active. Bit 4 is set if an enabled
interruptconditionoccurs.Itreflectsthecurrentstateofthe
IRQoutputandcanbeclearedbyreadingtheResetParity/
Interrupt Register.
Bus and Status Register. Address 5 (Read Only). The
Bus and Status Register (Figure 14) is a read-only register
which can be used to monitor the remaining SCSI control
signals not found in the Current SCSI Bus Status Registers
(/ATN and /ACK), as well as six other status bits. The
following describes each bit of the Bus Status Register
individually.
Bit 5. Parity Error. Bit 5 is set if a parity error occurs during
adatareceiveoradeviceselection.TheParityErrorbitcan
only be set (1) if the Enable Parity Check bit (Mode
Register, bit 5) is active (1). This bit may be cleared by
reading the Reset Parity/Interrupt Register.
Bit 0. /ACK. Bit 0 reflects the condition of the SCSI Bus
control signal /ACK. This signal is normally monitored by
the Target device.
Bit 6. DMA Request. The DMA Request bit allows the CPU
to sample the output pin DRQ. DRQ can be cleared by
asserting /DACK or by resetting the DMA MODE bit (bit 1)
in the Mode Register. The DRQ signal does not reset when
a phase-mismatch interrupt occurs.
Bit 1. /ATN. Bit 1 reflects the condition of the SCSI Bus
control signal /ATN. This signal is normally monitored by
the Target device.
Address: 5
(Read Only)
Bit 7. End Of DMA Transfer. The End Of DMA Transfer bit
is set if /EOP, /DACK, and either /RD or /WR are
simultaneously active for at least 100 ns. Since the /EOP
signal can occur during the last byte sent to the Output
Data Register, the /REQ and /ACK signals should be
monitoredtoensurethatthelastbytehasbeentransferred.
This bit is reset when the DMA MODE bit is reset (0) in the
Mode Register.
D7 D6 D5 D4 D3 D2 D1 D0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
DMA Registers. Three write-only registers are used to
initiate all DMA activity. They are: Start DMA Send, Start
DMA Target Receive, and Start DMA Initiator Receive.
Performing a write operation into one of these registers
starts the desired type of DM transfer. Data presented to
the SCSI on signals D7-D0 during the register write is
meaningless and has no effect on the operation. Prior to
writing these registers, the DMA Mode bit (bit 1), and the
Target mode bit (bit 6) in the Mode Register must be
appropriately set. The individual registers are briefly
described as follows:
Figure 14. Bus and Status Register
Bit2. BusyError.TheBusyErrorbitisactiveifanunexpected
loss of the /BSY signal has occurred. This latch is set
whenever the Monitor Busy bit (Mode Register, bit 2) is
True and /BSY is False. An unexpected loss of /BSY
disables any SCSI outputs and resets the DMA Mode bit
(Mode Register, bit 1).
Start DMA Send. Address 5 (Write Only). This register is
written to initiate a DMA send, from the DMA to the SCSI
Bus, for either Initiator or Target role operations. The DMA
Mode bit (Mode Register, bit 1) is set prior to writing this
register.
Bit 3. Phase Match. The SCSI signals /MSG, C//D, and
I//O, represent the current information transfer phase. The
Phase Match bit indicates whether the current SCSI Bus
phasematchesthelowerthreebitsoftheTargetCommand
Register. PhaseMatchiscontinuouslyupdatedandisonly
significant when operating as a Bus Initiator. A phase
match is required for data transfers to occur on the SCSI
Bus.
Start DMA Target Receive. Address 6 (Write Only). This
register is written to initiate a DMA receive - from the SCSI
Bus to the DMA, for Target operation only. The DMA Mode
bit (bit 1) and the Targetmode bit (bit 6) in the Mode
Register must both be set (1) prior to writing this register.
12
PS97SCC0200
Z
ILOG
Z53C80 SCSI
Start DMA Initiator Receive. Address 7 (Write Only). This
register is written to initiate a DMA receive from the SCSI
BustotheDMA, forInitiatoroperationonly. TheDMAMode
bit (bit 6) must be False (0) in the Mode Register prior to
writing this register.
Assuming the Z53C80 has been properly initialized, an
interrupt will be generated if the chip is selected or
reselected, ifan/EOPsignaloccurs, ifaparityerroroccurs
during a data transfer, if a bus phase mismatch occurs, or
if a SCSI Bus disconnection occurs.
Reset Parity/Interrupt. Address 7 (Read Only). Reading
this register resets the Parity Error bit (bit 5), the Interrupt
Request bit (bit 4), and the Busy Error bit (bit 2) in the Bus
and Status Register.
Selection Reselection. The Z53C80 generates a select
interrupt if SEL is active (0), its device ID is True and /BSY
is False for at least a bus-settle delay. If I//O is active, this
is considered a reselect interrupt. The correct ID bit is
determined by a match in the Select Enable Register. Only
a single bit match is required to generate an interrupt. This
interruptmaybedisabledbywritingzerosintoallbitsofthe
Select Enable Register.
On-Chip SCSI Hardware Support. The SCSI is easy to
use because of its simple architecture. The chip allows
direct control and monitoring of the SCSI Bus by providing
a latch for each signal. However, portions of the protocol
define timings which are much too quick for traditional
microprocessors to control. Therefore, hardware support
has been provided for DMA transfers, bus arbitration,
phase change monitoring, bus disconnection, bus reset,
parity generation, parity checking, and device selection/
reselection.
If parity is supported, parity should be good during the
selection phase. Therefore, if the Enable Parity bit (Mode
Register, bit 5) is active, the Parity Error bit is checked to
ensure that a proper selection has occurred. The Enable
Parity Interrupt bit need not be set for this interrupt to be
generated.
Arbitration is accomplished using a Bus-Free filter to
continuously monitor /BSY. If /BSY remains inactive for at
least 400 ns, the SCSI is considered free and Arbitration
may begin. Arbitration will begin if the bus is free, /SEL is
inactive, and the Arbitrate bit (Mode Register, bit 0) is
active. Once arbitration has begun (/BSY asserted), an
arbitration delay of 2.2 µs must elapse before the Data Bus
can be examined to determine if Arbitration is enabled.
This delay is implemented in the controlling software
driver.
The proposed SCSI specification also requires that no
more than two device IDs be active during the selection
process. To ensure this, the Current SCSI Data Register is
read.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
15 and 16, respectively.
D0
0
D7
0
0
0
1
X
0
X
The Z53C80 is a clockwise device. Delays such as bus-
free delay, bus-set delay, and bus-settle delay are
implemented using gate delays. These delays may differ
between devices because of inherent process variations,
but are well within the proposed ANSI X3.131 - 1986
specification.
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Interrupts. TheZ53C80providesaninterruptoutput(IRQ)
to indicate a task completion or an abnormal bus
occurrence. The use of interrupts is optional and may be
disabled by resetting the appropriate bits in the Mode
Register or the Select Enable Register.
Whenaninterruptoccurs, theBusandStatusRegisterand
the Current SCSI Bus Status Register (Figures 12 and 14)
must be read to determine which condition created the
interrupt. IRQ can be reset simply by reading the Reset
Parity/Interrupt Register or by an external chip reset
/RESET active for 100 ns.
Figure 15. Bus and Status Register
13
PS97SCC0200
Z53C80 SCSI
Z
ILOG
FUNCTIONAL DESCRIPTION (Continued)
D7
D0
D7
D0
0
1
1
X
X
X
0
X
0
0
0
X
X
X
0
X
/DBP
/SEL
I//O
/DBP
/SEL
I//O
C//D
C//D
/MSG
/REQ
/BSY
/RST
/MSQ
/REQ
/BSY
/RST
Figure 16. Current SCSI Bus Status Register
Figure 18. Current SCSI Bus Status Register
End of Process (EOP) Interrupt. An End Of Process
signal (EOP) which occurs during a DMA transfer (DMA
Mode True) will set the End of DMA Status bit (Bus and
Status Register bit 7) and will optionally generate an
interrupt if Enable EOP Interrupt bit (Mode Register, bit 3)
isTrue. The/EOPpulsewillnotberecognized(EndofDMA
bit set) unless /EOP, /DACK, and either /RD or /WR are
concurrently active for at least 50 ns. DMA transfers can
still occur if /EOP was not asserted at the correct time. This
interrupt is disabled by resetting the Enable EOP Interrupt
bit.
The End of DMA bit is used to determine when a block
transfer is complete. Receive operations are complete
when there is no data left in the chip and no additional
handshakes occurring. The only exception to this is
receiving data as an Initiator and the Target opts to send
additional data for the same phase. In this /REQ goes
active and the new data is present in the Input Data
Register. Since a phase-mismatch interrupt will not occur,
/REQ and /ACK need to be sampled to determine that the
Target is attempting to send more data.
For send operations, the End of DMA bit is set when the
DMAfinishesitstransfers,buttheSCSItransfermaystillbe
in progress. If connected as a Target, /REQ and /ACK
should be sampled until both are False. If connected as an
Initiator, a phase change interrupt is used to signal the
completion of the previous phase. It is possible for the
Target to request additional data for the same phase. In
this case, a phase change will not occur and both /REQ
and/ACKaresampledtodeterminewhenthelastbytewas
transferred.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register for this interrupt are
shown in Figures 17 and 18.
D7
D0
1
0
0
1
0
0
0
X
/ACK
/ATN
SCSI Bus Reset. The SCSI generates an interrupt when
the /RST signal transitions to True. The device releases all
bus signals within a bus-clear delay of this transition. This
interrupt also occurs after setting the Assert /RST bit
(Initiator Command Register, bit 7). This interrupt cannot
be disabled. (Note: /RST is not latched in bit 7 of the
Current SCSI Bus Status Register and is not active when
this port is read. For this case, the Bus Reset interrupt is
determined by default.)
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
19 and 20, respectively.
Figure 17. Bus and Status Register
14
PS97SCC0200
Z
ILOG
Z53C80 SCSI
D7
D0
D7
D0
0
X
0
1
X
0
X
X
0
X
1
1
1
0
X
X
/ACK
/ACK
/ATN
/ATN
Busy Error
Busy Error
Phase Match
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Figure 19. Bus and Status Register
Figure 21. Bus and Status Register
D7
X
D0
D7
D0
X
X
X
X
X
X
X
0
1
1
X
X
X
0
X
/DBP
/SEL
I//O
/DBP
/SEL
I//O
C//D
C//D
/MSG
/REQ
/BSY
/RST
/MSQ
/REQ
/BSY
/RST
Figure 20. Current SCSI Bus Status Register
Figure 22. Current SCSI Bus Status Register
ParityError.Aninterruptisgeneratedforareceivedparity
errorittheEnableParityCheck(bit5)andtheEnableParity
Interrupt (bit 4) bits are set (1) in the Mode Register. Parity
ischeckedduringareadoftheCurrentSCSIDataRegister
and during a DMA receive operation. A parity error can be
detected without generating an interrupt by disabling the
Enable Parity Interrupt bit and checking the Parity Error
flag (Bus and Status Register, bit 5).
Bus Phase Mismatch. The SCSI phase lines have the
signalsI//O, C//D, and/MSG. Thesesignalsarecompared
with the corresponding bits in the Target Command
Register: Assert I//O (bit 0), Assert C//D (bit 1), and Assert
/MSG (bit 2). The comparison occurs continually and is
reflectedinthePhaseMatchbit(bit3)oftheBusandStatus
Register. If the DMA Mode bit (Mode Register, bit 1) is
activeandaphasemismatchoccurswhen/REQtransitions
from False to True, an interrupt (IRQ) is generated.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
21 and 22, respectively.
15
PS97SCC0200
Z53C80 SCSI
Z
ILOG
FUNCTIONAL DESCRIPTION (Continued)
A phase mismatch prevents the recognition of /REQ and
removes the chip from the bus during an Initiator send
operation (/DB7-/DB0 and /DBP will not be driven even
throughtheAssertDataBusbit(InitiatorCommandRegister,
bit 0). This may be disabled by resetting the DMA Mode bit
(Note: It is possible for this interrupt to occur when
connected as a Target if another device is driving the
phase lines to a different state).
Loss of BSY. If the Monitor Busy bit (bit 2) in the Mode
Register is active, an interrupt is generated if the BSY
signal goes FALSE for at least a bus-settle delay. This
interrupt is disabled by resetting the Monitor Busy bit.
Register values are displayed in Figures 25 and 26.
D7
0
D0
0
0
0
1
X
1
0
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
23 and 24, respectively.
/ACK
/ATN
Busy Error
D7
D0
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
0
0
0
1
0
0
X
0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Figure 25. Bus and Status Register
D0
D7
0
0
0
X
X
X
0
0
/DBP
/SEL
I//O
Figure 23. Bus and Status Register
D7
D0
C//D
0
1
X
X
X
X
0
X
/MSQ
/REQ
/BSY
/RST
/DBP
/SEL
I//O
C//D
Figure 26. Current SCSI Bus Status Register
/MSQ
/REQ
/BSY
/RST
Figure 24. Current SCSI Bus Status Register
16
PS97SCC0200
Z
ILOG
Z53C80 SCSI
Reset Conditions. Three possible reset situations exist
with the Z53C80, as follows:
request (DRQ) whenever it is ready for a byte transfer.
External DMA logic uses this DRQ signal to generate
/DACKanda/RDora/WRpulsetotheZ53C80.DRQgoes
inactivewhen/DACKisassertedand/DACKgoesinactive
some time after the minimum read or write pulse width.
This process is repeated for every byte. For this mode,
/DACK should not be allowed to cycle unless a transfer is
taking place.
Hardware Chip Reset. When the signal RST is active for
at least 100 ns, the Z53C80 device is re-initialized and all
internal logic and control registers are cleared. This is a
chip reset only and does not create a SCSI Bus-Reset
condition.
SCSI Bus Reset (/RST) Received. When a SCSI /RST
signalisreceived, anIRQinterruptisgeneratedandachip
reset is performed. All internal logic and registers are
cleared, except for the IRQ interrupt latch and the Assert
/RST bit (bit 7) in the Initiator Command Register. (Note:
The /RST signal may be sampled by reading the Current
SCSI Bus Status Register, however, this signal is not
latched and may not be present when this port is read.)
Block Mode Transfers. The Block Mode DMA transfers
allow an external DMA controller, such as the Intel 8237,
toperformsuccessiveDMAtransferswithoutabandoning
the data bus to the microprocessor. Keeping an active
/DACKpreventsthe(Intel-type)CPUsfromgainingcontrol
of the system bus. The Block Mode handshaking method
does not increase the transfer rate. Preventing the CPU
from multiplexing the system bus does not have any
speed advantages. Therefore, this is not recommended
for initiator use.
SCSI Bus Reset (/RST) Issued. If the CPU sets the Assert
/RST bit+ 7) in the Initiator Command Register, the /RST
signal goes active on the SCSI Bus and an internal reset is
performed. Again, all internal logic and registers are
cleared except for the IRQ interrupt latch and the Assert
/RST bit (bit 7) in the Initiator Command Register. The /RST
signal will continue to be active until the Assert /RST bit is
reset or until a hardware reset occurs.
In the Block Mode, the SCSI chip asserts the DRQ signal
to initiate the transfer. The DMA controller responds to the
DRQsignalbyassertingthe/DACKandremainsasserted
throughout the transfer. The 53C80 asserts the READY
signal after the /IOR or /IOW signals deassert, effectively
replacingtheDRQsignal. TheREADYsignalforIntel-type
DMA controllers extends the memory read and write
signals. Therefore, D7-D0isavailabletobereadorwritten
on the system bus until the SCSI chip is ready for the next
transfer. This transfer method prevents the CPU from
executing any action, such as a refresh cycle on the
system bus. In the non-block DMA mode, the system bus
isunoccupieduntilthe53C80assertsDRQ.Thisindicates
that the chip is ready for the next byte transfer. The
advantage of this mode is that it allows the CPU to use the
systembuswhilethe53C80istransferringdataacrossthe
SCSI bus.
Data Transfers. Data is transferred between SCSI Bus
devices in one of four modes: 1) Programmed I/O, 2)
Normal DMA, 3) Block Mode DMA, or 4) Pseudo DMA. The
following sections describe these modes in detail (Note:
for all data transfer operations /DACK and /CS should
never be active simultaneously.)
Programmed I/O Transfers. Programmed I/O is the most
primitive form of data transfer. The /REQ and /ACK
handshakesignalsareindividuallymonitoredandasserted
by reading and writing the appropriate register bits. This
type of transfer is normally used when transferring small
blocks of data such as command blocks or message and
status bytes. An Initiator send operation would begin by
settingtheC//D,I//O,and/MSGbitsintheTargetCommand
Register to the correct state so that a phase match exists.
Inadditiontothephasematchcondition, itisnecessaryfor
the Assert Data Bus bit (Initiator Command Register, bit 0)
to be True and the received I/O signal to be False for the
Z53C80 to send data. For each transfer, the data is loaded
into the Output Data Register. The CPU then waits for the
/REQ bit (Current SCSI Bus Status Register, bit 5) to
become active. Once /REQ goes active, the Phase Match
bit (Initiator Command Register, bit 4) is set. The /REQ bit
is sampled until it becomes FALSE and the CPU resets the
Assert /ACK bit to complete the transfer.
Caution must be taken when executing this mode due to
theoperationofREADY.Forexample,ifaphasemismatch
interrupt occurs, the READY signal will stay inactive and
IRQ will be active. Then, the DMA controller cannot give
the system bus back to the CPU for the 53C80 interrupt to
be serviced since READY remains inactive. READY must
be asserted to continue the bus cycle. Therefore, /EOP
should be used in Block Mode so that the CPU can regain
control of the bus after the last byte has been transferred.
To make READY active again, reset the DMA Mode Bit.
Block Mode transfers are stopped in the same fashion as
in the Block Mode. This is executed by resetting the DMA
Mode Bit or using the /EOP signal. (See the previous
section, Normal DMA Mode, for more information on
stopping a DMA transfer.)
Normal DMA Mode. DMA transfers are normally used for
large block transfers. The SCSI chip outputs a DMA
17
PS97SCC0200
Z53C80 SCSI
Z
ILOG
FUNCTIONAL DESCRIPTION (Continued)
Pseudo DMA Mode. To avoid monitoring and asserting
the request/acknowledgment handshake signals for
programmedI/Otransfers,thesystemmaybedesignedto
implementapseudoDMAmode.Thismodeisimplemented
by programming the Z53C80 to operate in the DMA mode,
but using the CPU to emulate the DMA handshake. DRQ
may be detected by polling the DMA Request bit (bit 6) in
the Bus and Status Register, by sampling the signal
through an external port, or by using it to generate a CPU
interrupt. Once DRQ is detected, the CPU can perform a
readorwritedatatransfer.ThisCPUread/writeisexternally
decoded to generate the appropriate /DACK and /RD or
/WR signals.
Bus Phase Mismatch Interrupt. A bus phase mismatch
interrupt is used to halt the transfer if operating as an
Initiator. Using this method frees the host from maintaining
a data length counter and frees the DMA logic from
providing the /EOP signal. If performing an Initiator send
operation, the Z53C80 requires /DACK to cycle before
/ACK goes inactive. Since phase changes cannot occur if
/ACK is active, either /DACK must be cycled after the last
byte is sent or the DMA Mode bit must be reset in order to
receive the phase mismatch interrupt.
Resetting the DMA MODE Bit. A DMA operation may be
halted at any time simply by resetting the DMA Mode bit.
It is recommended that the DMA Mode bit be reset after
receiving an /EOP or bus phase-mismatch interrupt. The
DMA Mode bit must then be set before writing any of the
start DMA registers for subsequent bus phases.
Often, external decoding logic is necessary to generate
the /CS signal. This same logic may be used to generate
/DACK at no extra cost and provide an increased
performance in programmed I/O transfers.
If resetting the DMA Mode bit is used instead of /EOP for
Target role operation, then care must be taken to reset this
bit at the proper time. If receiving data as a Target device,
the DMA Mode bit must be reset once the last DRQ is
received and before /DACK is asserted to prevent an
additional /REQ from occurring. Resetting this bit causes
DRQ to go inactive. However, the last byte received
remains in the Input Data Register and may be obtained
either by performing a normal CPU read or by cycling
/DACK and /RD. In most cases, /EOP is easier to use when
operating as a Target device.
Halting a DMA Operation. The EOP signal is not the only
way to halt a DMA transfer. A bus phase mismatch or a
reset of the DMA MODE bit (Mode Register, bit 1) can also
terminate a DMA cycle for the current bus phase.
Using the /EOP Signal. If /EOP is used, it should be
asserted for at least 50 ns while /DACK and /RD or /WR are
simultaneously active. Note, however, that if /RD or /WR is
not active, an interrupt is generated, but the DMA activity
continues. The /EOP signal does not reset the DMA MODE
bit. Since the /EOP signal can occur during the last byte
sent to the Output Data Register, the /REQ and /ACK
signals are monitored to ensure that the last byte has
transferred.
18
PS97SCC0200
Z
ILOG
Z53C80 SCSI
READ REGISTERS
Address: 3
(Read Only)
Address: 0
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Assert I//O
Assert C//D
Assert /MSG
Assert /REQ
"0"
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Last Byte Sent
Figure 30. Target Command Register
Figure 27. Current SCSI Data Register
Address: 4
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Address: 1
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DBP
/SEL
I//O
Assert Data Bus
Assert /ATN
C//D
Assert /SEL
/MSG
/REQ
/BSY
/RST
Assert /BSY
Assert /ACK
Lost Arbitration
Arbitration in Progress
Assert /RST
Figure 31. Current SCSI Bus Status Register
Figure 28. Initiator Command Register
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Address: 5
Address: 2
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/ACK
/ATN
Arbitrate
Busy Error
DMA Mode
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Monitor /BSY
Enable /EOP Interrupt
Enable Parity Interrupt
Enable Parity Checking
Target Mode
"0"
Figure 32. Bus and Status Register
Figure 29. Mode Register
19
PS97SCC0200
Z53C80 SCSI
Z
ILOG
READ REGISTERS (Continued)
Address: 6
(Read Only)
Address: 7
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
"X"
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
X = Don't Care
Figure 34. Reset Parity/Interrupt
Figure 33. Input Data Register
WRITE REGISTERS
Address: 0
Write Only)
Address: 1
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
"0"
Test Mode
Assert /RST
Figure 36. Initiator Command Register
Figure 35. Output Data Register
20
PS97SCC0200
Z
ILOG
Z53C80 SCSI
Address: 2
(Write Only)
Address: 5
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Arbitrate
"X"
DMA Mode
Monitor /BSY
Enable /EOP Interrupt
Enable Parity Interrupt
Enable Parity Checking
Target Mode
Figure 40. Start DMA Send
Address: 6
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
"0"
"X"
Figure 37. Mode Register
Figure 41. Start DMA Target Receive
Address: 3
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Address: 7
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert I//O
Assert C//D
Assert /MSG
Assert /REQ
"X"
"X"
Figure 42. Start DMA Initiator Receive
Last Byte Sent
Figure 38. Target Command Register
Address: 4
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 39. Select Enable Register
21
PS97SCC0200
Z53C80 SCSI
Z
ILOG
ABSOLUTE MAXIMUM RATINGS
StressesgreaterthanthoselistedunderAbsoluteMaximum
Ratingsmaycausepermanentdamagetothisdevice.This
is a stress rating only; operation of the device at any
conditionabovethoseindicatedintheoperationalsections
ofthesespecificationsisnotimplied. Exposuretoabsolute
maximum rating conditions for extended periods may
affect device reliability.
Voltages on all pins
with respect to GND................................. –0.3V to +7.0V
Operating Ambient Temperature ................................... †
Storage Temperature ............................–65°C to +150°C
Note:
† See Ordering Information
STANDARD TEST CONDITIONS
+5V
The DC characteristics and capacitance section below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND.
Positive current flows into the referenced pin. Standard
conditions are as follows:
2.2 kΩ
From Output
Under Test
■ +4.75V ≤ VCC ≤ +5.25V
■ GND = 0V
■ TA as specified in Ordering Information
75 pF
I
= 2 mA
OL
Figure 44. Open-Drain Test Load
Threshold
Voltage
From Output
Under Test
V
= 1.4 V
T
75 pF
I
= 250 µA
OH
Figure 43. Standard Test Dynamic Load Circuit
22
PS97SCC0200
Z
ILOG
Z53C80 SCSI
DC CHARACTERISTICS
Symbol
Parameter
Condition
Min
Max
Units
VDD
VIH
VIL
Supply Voltage
4.75
2.0
VSS –0.5
5.25
VDD +0.5
0.8
V
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
SCSI Bus Pins
IIH1
VIH = 5.25V
VIL = 0V
50
µA
IIH2
IIL1
IIL2
High-Level Input Current
All Other Pins
Low-Level Input Current
SCSI Bus Pins (Except /RST)
Low-Level Input Current
All Other Pins
VIH = 5.25V
10
µA
µA
VIL = VSS
–50
VIL = VSS
–10
VDD
µA
VOH1
VOL1
High-Level Output Voltage
Low-Level Output Voltage
SCSI Bus Pins
Low-Level Output Voltage
All Other Pins
IOH = –4 mA
2.4
VSS
VSS
0
V
IOL = 48 mA
IOL = 8 mA
0.5
V
VOL2
0.4
15
70
V
mA
°C
IDD
TA
Supply Current
Operating Free-Air Temperature
23
PS97SCC0200
Z53C80 SCSI
Z
ILOG
AC CHARACTERISTICS
CPU Write Cycle Timing Diagram
A2-A0
/SCSICS
/RD
1
2
3
4
5
6
D7-D0
Figure 45. CPU Write Cycle
AC CHARACTERISTICS
CPU Write Cycle Table
No
Description
Min
Max
Units
1
2
3
Address Setup to Write Enable [1]
10
10
40
ns
ns
ns
Address Hold from End Write Enable [1]
Write Enable Width*
4
5
6
Chip Select Hold from End of /IOW
Data Setup to end of Write Enable [1]
Data Hold Time form End of /IOW
0
20
20
ns
ns
ns
Note:
[1] Write Enable is the occurrence of /WR and /CS.
24
PS97SCC0200
Z
ILOG
Z53C80 SCSI
AC CHARACTERISTICS
CPU Read Cycle Timing Diagram
A2-A0
/SCSICS
/RD
1
2
3
4
5
D7-D0
Figure 46. CPU Read Cycle
AC CHARACTERISTICS
CPU Read Cycle Table
No
Description
Min
Max
Units
1
2
Address Setup to Read Enable [1]
10
10
ns
ns
Address Hold from End Read Enable [1]
3
4
5
Chip Select Hold from End of /RD
0
ns
ns
ns
Data Access Time from Read Enable [1]
Data Hold Time from End of Read Enable [1]
70
10
Note:
[1] Read Enable is the occurrence of /RD and /CS.
25
PS97SCC0200
Z53C80 SCSI
Z
ILOG
AC CHARACTERISTICS
DMA Write (Non-Block Mode) Initiator Send Cycle Timing Diagram
DRQ
1
2
/DACK
3
4
/WR
D7-D0
/EOP
5
6
7
/REQ
9
10
8
/ACK
12
11
13
/DB7-/DB0,
/DBP
Figure 47. DMA Write (Non-Block Mode) Initiator Send Cycle
26
PS97SCC0200
Z
ILOG
Z53C80 SCSI
AC CHARACTERISTICS
DMA Write Initiator Send Cycle Table
No
Description
Min
Max
Units
1
2
3
DRQ Low from /DACK Low
/DACK High to DRQ High
Write Enable Width [1]
60
ns
ns
ns
30
50
4
5
6
/DACK Hold from End of /WR
0
50
25
ns
ns
ns
Data Setup to End of Write Enable [1]
Data Hold Time from End of /WR
7
8
9
Width of /EOP Pulse [2]
/REQ Low to /ACK Low
/REQ High to DRQ High
50
ns
ns
ns
90
70
10
11
12
13
/DACK High to /ACK High
/WR High to Valid SCSI Data
Data Hold from Write Enable [1]
Data Setup to /ACK Low
90
50
ns
ns
ns
ns
15
55
Notes:
[1] Write Enable is the occurrence of /WR and /DACK.
[2] /EOP, /WR, and /DACK must be concurrently Low for at least T7 for
proper recognition of the /EOP pulse.
27
PS97SCC0200
Z53C80 SCSI
Z
ILOG
AC CHARACTERISTICS
DMA Read (Non-Block Mode) Initiator Receive Timing Diagram
DRQ
1
2
/DACK
3
/IOR
4
5
BYTE N
D7-D0
6
/EOP
7
/REQ
9
8
10
/ACK
11
12
/DB7-/DB0,
/DBP
BYTE N
Figure 48. DMA Read (Non-Block Mode) Initiator Receive
28
PS97SCC0200
Z
ILOG
Z53C80 SCSI
AC CHARACTERISTICS
DMA Read (Non-Block Mode) Initiator Receive Table
Name
Description
Min
Max
Units
1
2
DRQ False from /DACK True
/DACK False to DRQ True
60
ns
ns
30
0
3
4
/DACK Hold Time from End of /IOR
ns
ns
Data Access Time from Read Enable [1]
70
70
5
6
7
Data Hold Time from End of /IOR
Width of /EOP Pulse [2]
/REQ True to DRQ True
10
50
ns
ns
ns
8
9
10
11
12
/REQ True to /ACK True
90
80
90
ns
ns
ns
ns
ns
/REQ False to /ACK False (/DACK False)
/DACK False to /ACK False (/REQ False)
DATA Setup Time to /REQ
20
50
DATA Hold Time from /REQ True
Notes:
[1] Read enable is the occurrence of both /IOR and /DACK.
[2] /EOP, /IOR and /DACK must be concurrently true for at least T6 for
proper recognition of the /EOP pulse.
29
PS97SCC0200
Z53C80 SCSI
Z
ILOG
AC CHARACTERISTICS
DMA Write (Non-Block Mode) Target Send Cycle Timing Diagram
DRQ
1
2
/DACK
3
4
6
/WR
D7-D0
/EOP
5
7
9
8
/REQ
11
10
/ACK
12
13
/DB7-/DB0,
/DBP
Figure 49. DMA Write (Non-Block Mode) Target Send Cycle
30
PS97SCC0200
Z
ILOG
Z53C80 SCSI
AC CHARACTERISTICS
DMA Write Target Send Cycle Table
No
Description
Min
Max
Units
1
2
3
DRQ Low from /DACK Low
/DACK High to DRQ High
Write Enable Width [1]
60
ns
ns
ns
30
50
4
5
6
/DACK Hold from /WR High
0
50
25
ns
ns
ns
Data Setup to End of Write Enable [1]
Data Hold Time from End of /WR
7
8
9
Width of /EOP Pulse [2]
/ACK Low to /REQ High
/REQ from End of /DACK (/ACK High)
50
ns
ns
ns
80
90
10
11
12
13
/ACK Low to DRQ High (Target)
/ACK High to /REQ Low (/DACK High)
Data Hold from Write Enable
70
100
ns
ns
ns
ns
15
55
Data Setup to /REQ Low (Target)
Notes:
[1] Write Enable is the occurrence of /IOW and /DACK
[2] /EOP, /WR, and /DACK must be concurrently Low for at least T7 for
proper recognition of the /EOP pulse.
31
PS97SCC0200
Z53C80 SCSI
Z
ILOG
AC CHARACTERISTICS
DMA Read (Non-Block Mode) Target Receive Timing Diagram
DRQ
1
2
/DACK
3
/IOR
5
4
BYTE N
D7-D0
6
/EOP
7
8
/REQ
9
10
/ACK
11
12
/DB7-/DB0,
/DBP
BYTE N
Figure 50. DMA Read (Non-Block Mode) Target Receive
32
PS97SCC0200
Z
ILOG
Z53C80 SCSI
AC CHARACTERISTICS
DMA Read (Non-Block Mode) Target Receive Table
Name
Description
Min
Max
Units
1
2
3
DRQ False from /DACK True
/DACK False to DRQ True
/DACK Hold Time from End of /IOR
60
ns
ns
ns
30
0
4
5
6
Data Access Time from Read Enable [1]
Data Hold Time from End of /IOR
Width of /EOP Pulse [2]
70
ns
ns
10
50
7
8
9
/ACK True to DRQ True
/DACK False to /REQ True (/ACK False)
/ACK True to /REQ False
70
90
80
10
11
12
/ACK False to /REQ True (/DACK False)
DATA Setup Time to /ACK
DATA Hold Time from /ACK True
100
20
30
Notes:
[1] Read enable is the occurrence of both /IOR and /DACK.
[2] /EOP, /IOR and /DACK must be concurrently true for a least T6 for
proper recognition of the /EOP pulse.
33
PS97SCC0200
Z53C80 SCSI
Z
ILOG
AC CHARACTERISTICS
DMA Write (Block Mode) Target Send Timing Diagram
DRQ
1
/DACK
3
2
/IOW
5
4
D7-D0
/EOP
BYTE N
6
8
/REQ
/ACK
7
9
11
12
10
READY
14
13
BYTE N-1
BYTE N
DB7-DB0
Figure 51. DMA Write (Block Mode) Target Send
34
PS97SCC0200
Z
ILOG
Z53C80 SCSI
AC CHARACTERISTICS
DMA Write (Block Mode) Target Send Table
Name
Description
Min
Max
Units
1
2
3
DRQ False from /DACK True
Write Enable Width [1]
Write Recovery Time
60
ns
ns
ns
50
120
4
5
6
7
Data Setup to End of Write Enable [1]
Data Hold Time from End of /IOW
Width of /EOP Pulse [2]
50
25
50
ns
ns
ns
ns
/ACK True to /REQ False
80
8
9
10
/REQ from End of /IOW (/ACK False)
/REQ from End of ACK (/IOW False)
/ACK True to READY True
90
100
70
ns
ns
ns
11
12
13
14
READY True to /IOW False
/IOW False to READY False
DATA Hold from /ACK True
Data Setup to /REQ True
70
ns
ns
ns
ns
70
40
55
Notes:
[1] Read enable is the occurrence of both /IOR and /DACK.
[2] /EOP, /IOW, and /DACK must be concurrently true for at least T6 for
proper recognition of the /EOP pulse.
35
PS97SCC0200
Z53C80 SCSI
Z
ILOG
AC CHARACTERISTICS
DMA Read (Block Mode) Target Receive Timing Diagram
DRQ
1
/DACK
2
/IOR
3
4
BYTE N
D7-D0
/EOP
5
6
/REQ
/ACK
8
7
11
9
10
READY
12
13
/DB7-/DB0,
/DBP
BYTE N
Figure 52. DMA Read (Block Mode) Target Receive
36
PS97SCC0200
Z
ILOG
Z53C80 SCSI
AC CHARACTERISTICS
DMA Read (Block Mode) Target Receive Table
Name
Description
Min
Max
Units
1
2
3
DRQ False from /DACK True
/IOR Recovery Time
60
ns
ns
ns
120
Data Access Time from Read Enable [1]
70
4
5
6
Data Hold Time from End of /IOR
Width of /EOP Pulse [2]
/IOR False to /REQ True (/ACK False)
10
50
ns
ns
90
7
8
9
/ACK True to /REQ False
/ACK False to /REQ True (/IOR False)
/ACK True to READY True
80
100
70
ns
ns
ns
10
11
12
13
READY True to Valid Data
/IOR False to READY False
DATA Setup time to /ACK
DATA Hold Time from /ACK
50
70
ns
ns
20
30
Notes:
[1] Read enable is the occurrence of both /IOR and /DACK.
[2] /EOP, /IOR, and /DACK must be concurrently true for at least T5 for
proper recognition of the /EOP pulse.
AC CHARACTERISTICS
Reset Timing Diagram
1
/RESET
Figure 53. Reset
AC CHARACTERISTICS
Reset Table
No
Description
Min
100
Max
Units
ns
1
Minimum Width of /RESET
37
PS97SCC0200
Z53C80 SCSI
Z
ILOG
AC CHARACTERISTICS
Arbitration Timing Diagram
/SEL
/BSY
1
2
D7-D0
ARB
BYTE N
Figure 54. Arbitration
AC CHARACTERISTICS
Arbitration Table
Name
Description
Min
Max
Units
1
2
Bus Clear from SEL True
ARBITRATE Start from BSY False
600
2200
ns
ns
1200
38
PS97SCC0200
Z
ILOG
Z53C80 SCSI
PACKAGE INFORMATION
44-Pin PLCC Package Diagram
48-Pin DIP Package Diagram
39
PS97SCC0200
Z53C80 SCSI
Z
ILOG
ORDERING INFORMATION
Z53C80
48-Pin DIP
Z53C8003PSC
44-Pin PLCC
Z53C8003VSC
Package
P = Plastic DIP
V = Plastic Lead Chip Carrier
Environmental
C = Plastic Standard
Temperature
S = 0°C to +70°C
Speed
3 = 3 MB per second
Example:
Z 53C80 03 V S
C
is a Z53C80, 3 MB/s, PLCC, 0°C to +70°C, Plastic Standard Flow.
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
©1997byZilog, Inc. Allrightsreserved. Nopartofthisdocument
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
byZilog,Inc.arecoveredbywarrantyandpatentindemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makesnowarranty, express, statutory, impliedor
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog’s products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
40
PS97SCC0200
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