Z80S18833ASCRXXXX [ZILOG]
Microcontroller, 8-Bit, MROM, Z80 CPU, 33MHz, CMOS, PQFP16, QFP-160;
| 型号： | Z80S18833ASCRXXXX |
| 厂家： | 
ZILOG, INC. |
| 描述： | Microcontroller, 8-Bit, MROM, Z80 CPU, 33MHz, CMOS, PQFP16, QFP-160 微控制器 外围集成电路 |
| 文件： | 总251页 (文件大小：1913K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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©1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applica-
tions, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC.
DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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ꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢎꢃ
ꢀꢉꢄ +06ꢃꢀ/
ꢀꢆꢄ +06ꢃꢀ/
ꢀꢏꢄ +06ꢃꢀ/
ꢀꢍꢄ 4'6+ꢀ+
ꢀꢇꢄ ꢊꢌ%
ꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢎꢊ
ꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢎꢉ
ꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢎꢏ
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ꢀ% ꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢊꢍ
ꢀ
ꢀ4
ꢀ6
ꢀꢁꢄ +ꢋ1ꢀ%
ꢀꢂꢃꢄ (
ꢀꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢉꢃ
ꢀ% ꢀ% ꢀꢓꢀꢎꢃꢀ/* ꢀ ꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢉꢎ
ꢀ/
ꢀꢂꢂꢄ 6
ꢀꢂꢎꢄ /
ꢀꢂꢊꢄ /
ꢀꢂꢉꢄ /
ꢀꢂꢆꢄ /
ꢀꢂꢏꢄ 2
ꢀꢂꢍꢄ 2
ꢀꢂꢇꢄ 4
ꢌ1
ꢀ
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ꢀꢃꢀ1
ꢀ6
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ꢀ6
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ꢄꢀ. ꢀ% ꢀ(
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ꢑ ꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢇꢏ
ꢀ% ꢀ ꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄꢀꢄ ꢀꢁꢇ
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Four Counter/Timer channels (Z80-CTC)
Two 16-bit Programmable Reload Timers (PRTs)
4-KB ROM with security protection
1-KB RAM with security protection
Enhanced Memory Management Unit (MMU) addresses up to 8 MB
Two Direct Memory Access channels (DMAs)
Two Enhanced UART channels (ASCIs)
Clocked Serial I/O interface (CSI/O)
Watch-Dog Timer (WDT)
Chip select and wait state generators
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ZiLOG Debug Interface (ZDI)
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The Z80S188 is a general-purpose integrated microprocessor. It includes the
Z8S180 processor, four 8-bit I/O ports, two multiprotocol serial channels, four
Counter Timer channels, an enhanced MMU that addresses up to 8 MB of
memory, two DMA channels, a Watch-Dog Timer, two enhanced UARTs, two
Programmable Reload Timers, a CSI/O channel, 4 KB of on-chip RAM, and 1 KB
of on-chip ROM. It is packaged in a 160-pin QFP.
32 Bits of General-Purpose I/O. These four 8-bit ports, designated A through D,
are functionally identical to two Z80 PIO devices. Several programmable modes
of operation are featured, including input and output handshaking, or data direc-
tion, and interrupt control at the bit/pin level.
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CTC device. Each channel provides counter or timer functionality, an 8-bit down-
counter with /16 or /256 timer-prescaler, a clock or trigger input, a 0 count/
timeout output, and interrupt capability.
Two 16-Bit Timers. These timers are 16-bit down-counters with auto-reload and
interrupt capability. One channel has waveform generation capability.
Memory Management Unit (MMU). This module has been enhanced from the
MMU found on other 8X18X processors. The MMU now translates addresses
from the 64-KB logical memory address space used by software, to an 8 megabyte
physical memory address space, with a granularity of 1KB.
Two DMA Channels. These channels operate in an 8-Mbyte linear memory
address space and a 64-KB I/O space, and can transfer blocks up to 64 KB long.
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erals.
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generators, modem control, and status.
CSI/O. Clocked serial I/O can be used for serial interfacing to memory, periph-
erals, and other processors.
Chip Select and Wait logic. This feature contains two memory chip select signals
and one I/O chip select signal for external memory and I/O. A programmed
number of wait states can be inserted for each of these three programmable
address ranges.
Watch-Dog Timer. The WDT helps detect code runaway and helps minimize the
negative effects thereof. A range of timeout values is available. The WDTOUTpin
is driven Low if the Watch-Dog Timer counts down to 0 and can be connected to
RESET or NMI, or used in some other way.
4-KB of On-Chip ROM. Optional mask-programmed security features allow
restricted access via nine entry points in low memory, and no access or visibility
from the external bus.
1-KB of On-chip RAM. Optional mask-programmed security feature restricts
access to instructions in on-chip ROM.
ZiLOG Debug Interface. The ZDI module allows in-system debugging using the
ZiLOG Developer Studio (ZDS) running on a PC, and requires a 6-pin header on
the application board and a low-cost interface module.
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This section describes, using text, tables, and figures, how the various parts of the
Z80S188 operate. This description is presented from the processor “outward” to
the peripherals. In the latter parts of this section, refer to the corresponding part of
section 4, which describes the Z80S188’s I/O registers. Cross-reference links are
included in both sections to aid such reference.
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Like the original ZiLOG Z80, the Z80S188 is an 8-bit microprocessor that can
also perform various 16-bit operations. In both data sizes, the processor includes
an accumulator. A is the accumulator for 8-bit operations, and the HL register pair
is the accumulator for 16-bit operations.
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In addition to A, there are six more 8-bit registers named B, C, D, E, H, and L,
which can also be operated on as 16-bit register pairs BC, DE, and HL. The Flag
register F completes the basic register bank.
Two of these basic register banks are included in all Z80 and Z180 processors.
high-speed exchange between these banks can be used by a program internally, or
one bank can be allocated to the mainline program and the other to interrupt
service routines.
Finally, two Index registers IX and IY enable base and displacement addressing in
memory. IX and IY are not included in the register banks on the Z80 and Z180;
therefore, there is only one copy of each.
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Add a Memory Management Unit (MMU) that expands the addressing capability
to 20 bits or 1 Megabyte to the 16-bit, 64-KB memory addressing capability of the
Z80, Z180 processors other than the Z80S188. With the MMU, the 65K logical
addressing space can be divided into one to three areas of programmable size and
location in the 1 Megabyte physical memory space.
On the Z80S188, this MMU has been extended to 23 bits, or 8 MB.
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A separate I/O space includes on-chip and off-chip peripheral devices. On the
Z80, I/O space included 8-bit addresses and 256 bytes. As with memory space, all
Z180 processors feature an expanded I/O space with 16-bit addresses and 64 KB.
The Z80S188 includes an extensive set of on-chip peripherals in I/O space, which
can be augmented by external peripherals.
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In addition to the data-oriented registers described above, the Z80S188 processor
includes several other control registers. Unlike the registers in I/O space that are
described in section 4, these control registers have no addresses, but are used
implicitly in certain processor operations.
2TQITCOꢁ%QWPVGTꢁꢈ2%ꢉꢅꢁThis 16-bit register tracks program execution by the
processor, which automatically increments PC while fetching instructions. PC is
stored on the stack when a CALLor RSTinstruction is executed, and when an
interrupt or Trap occurs. PC is loaded with a new value when a JUMP, CALL, RST,
or RET instruction is executed, and when an INTERRUPT, TRAP, or RESET
instruction occurs. The PC then resets to 0000H.
5VCEMꢁ2QKPVGTꢁꢈ52ꢉꢅꢁThis 16-bit register is decremented by 2, and a 16-bit value is
stored in memory at this updated address, when a PUSH, CALL, or RST instruction
is executed, and when an interrupt or Trap occurs. A 16-bit value is fetched from
memory at the address in SP, and SP is then incriminated by 2, when a POP, RET,
RETI, or RETN instruction is executed. SP can be stored in memory, loaded from
memory or another register, or loaded with a constant/immediate value. Its value
can be added to or subtracted from another register, and it can be incremented or
decremented. Finally, the 16-bit value in memory, at which SP currently points,
can be exchanged with the contents of a 16-bit register. The SP resets to 0000H.
(NCIUꢁꢈ(ꢉꢅꢁThe processor includes two sets of six Flag bits each, named Z (ZERO),
CF (CARRY), S (SIGN), P/V (PARITY or OVERFLOW), HC (HALF-CARRY) and N
(ADD/SUBTRACT). It automatically updates certain flags as part of executing
certain instructions. Subsequent instructions can then use the flags, either as an
operand (ADC, SBC, DAA), or to determine whether to perform a JUMP, CALL, or
RET. The flags can be saved on the stack with a PUSH instruction, or restored from
the stack with a POP. The two sets of Flag registers are paired with the two A accu-
mulators; the current pair is toggled by the EX AF,AF/ instruction.
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1
&
+PVGTTWRVꢁ*KIJꢁ#FFTGUUꢁꢈ+ꢉꢅꢁThe contents of this register are used as the 8 high-
order address bits, when the processor fetches the address of an interrupt service
routine from memory, because of an interrupt from the INT1 or INT2 pin, or from
an on-chip peripheral. Thus, the I register points at a table of interrupt service
routine addresses, that starts at a 256-boundary in the 64-KB logical address
space. The I register resets to 00, and can be read or written by the dedicated
instructions LD A,I and LD I,A.
4ꢁ%QWPVGTꢁꢈ4ꢉꢅꢁOn the original Z80 this register contained the dynamic RAM
refresh address, but on Z8018x family processors it contains a count of executed
Op Code fetch cycles. R resets to 00, and can be read or written by the dedicated
instructions LD A,R and LD R,A.
+NNGICNꢁ+PUVTWEVKQPꢁ6TCRU
Like most processors, the defined instruction set for the 8018x family does not
fully cover all possible sequences of binary values. The Op Code maps in the
section“Op Code Map”, on page 193, include numerous blank cells. These cells
represent Op Code sequences for which no operation is defined, and are
commonly called illegal instructions.
When a Z80S188 or other 8018x processor fetches one of these sequences, it
performs a TRAP operation as follows:
1. The TRAP bit in the Interrupt/Trap Control register is set to 1.
2. The UFO bit is cleared to 0 in the Interrupt/Trap Control register if the
condition is detected while fetching the second byte of the instruction. If it
detected the condition while fetching the third byte of the instruction, the UFO
is set to 1.
3. The SP is decremented by 2 and stores the 16-bit logical address from PC, in
memory at the new SP value. This address points to the last byte of the illegal
Op Code sequence.
4. The PC clears and resumes execution at logical address 0000H.
6TCRꢁ*CPFNKPIꢅꢁThe code at logical address 0000Hstarts by storing the value of
SP in memory, and then setting SP to an area of memory dedicated to its stack.
This step is optional.
In all cases, the trap handling routine stores as many registers among AF, BC, DE,
HL, IX, and IY as it uses in subsequent instructions, by pushing them onto the
stack. A general-purpose routine stores all of these registers, and those in the alter-
nate set as well, plus I and the state of the Interrupt Enable flag.
Next, the code must distinguish among four cases that can bring execution to loca-
tion 0000: RESET, TRAP, an RST 0 instruction, or a program error like a JUMP to
a null pointer. The code can detect a TRAP by reading the Interrupt/Trap Control
register (ITC) and checking bit 7(TRAP). If the value of bit 7is 1, a TRAP
occurred.
Next, the trap-handling code clears the TRAP bit by setting it to 0. The code then
fetches the PC value stored on the stack, and examines bit 6of the ITC (UFO). If
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UFO is 0, the PC value is decremented by 1 so that it points to the start of the
instruction. If UFO is 1, the value is decremented by 2.
What the trap handling routine does next depends on the application and the stage
of its development.
'ZVGPFKPIꢁVJGꢁ+PUVTWEVKQPꢁ5GVꢅꢁCore software can use illegal instructions as
extensions to the Z8018x instruction set. To accomplish this, the core software
fetches and examines the illegal instruction, to determine if it is this type of exten-
sion. If so, software performs the extended operation that the instruction indicates,
advances the stacked PC value over the instruction, restores the registers and
performs a RET to the next instruction.
'TTQTꢁ/GUUCIGꢁXUꢅꢁ4GUVCTVꢅꢁExcept for these extended instructions, software can
either signal an illegal instruction and wait for someone to examine the situation
and restart, or attempt to restart the application immediately. The former course is
more common in the debugging/development stages of an application. The latter
may be more appropriate in the production/deployment stage. In the latter case,
software may log the event for future readout, to a storage medium or just in
memory.
5'%74+6;ꢁ('#674'5ꢁ#0&ꢁ41/ꢁ126+105
Two types of standard Z80S188s may be made available. On a romless part, on-
chip RAM is accessible to code in any memory. On-chip ROM is disabled and can
be emulated by a memory connected to the EV/ROMCS pin. On a monitor part,
on-chip RAM is accessible to code in any memory, and on-chip ROM contains a
standard debug monitor.
Customers submitting a custom ROM code for on-chip ROM can select among
several ROM options that enhance the security of their products and applications.
These options are described in the following sections.
Both standard parts have ROM and RAM Protection disabled and ZDI enabled.
41/ꢋ41/NGUU
41/ꢁ2TQVGEV
This option can selected as enable internal ROM by any customer submitting a
ROM code.
At the initial Op Code fetch of each instruction, the Z80S188 determines whether
the instruction is in on-chip ROM. If this ROM option is selected, the transition
from executing in other memory, to executing in on-chip ROM can occur only if
the first on-chip ROM address is 0000,0008,0010,0018,0020,0028,
0030,0038, or 0066H. If entry to on-chip ROM is attempted at any other
address, an exception occurs, the PC is stacked, and the ROMEE bit in the Inter-
rupt/Trap Control register is set. Execution proceeds from location 0000in a
manner similar to an illegal instruction trap.
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ꢊ When this option is selected, interrupt service routines cannot start in on-
chip ROM.
4#/ꢁ2TQVGEV
If this ROM option is selected:
1. On-chip RAM can only be read and written by instructions in on-chip ROM,
including: not by a DMA channel, nor by an off-chip master in BUSACK state
nor EV state. No exception occurs if code located elsewhere attempts to access
on-chip RAM, but no reading or writing occurs. During production device
testing, the functionality of on-chip RAM must be verified by a routine in the
user’s ROM code. Details of how the tester calls this routine will be specified
at a later date.
2. On-chip ROM can only be read by instructions in on-chip ROM, unless a
special pad is contacted by a wafer-level tester probe.
3. Data is blocked from appearing on the D7-0 pins for cycles in in-chip ROM or
on-chip RAM.
4. Execution in on-chip RAM is not allowed. If an Op Code fetch is attempted in
on-chip RAM, an exception occurs, the PC is stacked, and the RAMEE bit in
the Interrupt/Trap Control register is set. Execution proceeds from location
0000in a manner similar to an illegal instruction trap.
<&+ꢁ'PCDNG
For secure applications, disable this option. The ZiLOG Debug Interface (ZDI) is
a built-in interface that can be used with ZiLOG’s Developers’ Studio and poten-
tially with third-party products, for low-cost emulation facilities. See section
“ZiLOG Debug Interface”, on page 227, for a description of how to include a
connector on any application board to enable debugging via the ZDI.
+06'447265
ZiLOG Z80 and Z180 processors have a rich legacy of sophisticated interrupt
capabilities. Because it includes both Z80- and Z80180-compatible peripherals,
the Z80S188 includes aspects of both families’ interrupt characteristics.
+PVGTTWRVꢁ4GUQWTEGUꢁKPꢁVJGꢁ<ꢂꢃ5ꢄꢂꢂ
+'(ꢄꢁCPFꢁ+'(ꢆꢅꢁThese bits are internal to the processor and can only be affected
and manipulated by certain specific events:
A Reset clears both IEF1 and IEF2.
An EI instruction sets both IEF1 and IEF2.
A DI instruction clears both IEF1 and IEF2.
An NMI sequence copies IEF1 to IEF2, then clears IEF1.
A maskable interrupt clears both IEF1 and IEF2.
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An LD A,I or LD A,R instruction copies IEF2 to the P/V Flag.
An RETN instruction copies IEF2 to IEF1.
When IEF1 is 1, RESET and BUSREQ are both High, and no falling edge has
occurred on NMI, the Z80S188 checks for maskable interrupt requests from
external pins and on-chip peripherals, as it completes each instruction, or each
instruction iteration for HALT, the block I/O instructions, block move instructions,
and block scan instructions.
6JGꢁ+ꢁ4GIKUVGTꢅꢁThe Z80S188 uses the contents of this register as A15-8 of the
logical address for fetching interrupt service routine addresses from memory, in
response to interrupt requests on INT0, INT1, and INT2, and from internal periph-
erals.
“Interrupt Registers”, on page 115, describes the other registers associated with
interrupts:
6JGꢁ+.ꢁ4GIKUVGTꢅꢁThe Z80S188 uses the three Most Significant (MS) bits of this
register as A7-5 of the logical address for fetching interrupt service routine
addresses from memory, in response to interrupt requests on INT1 and INT2, and
from the ASCIs, PRTs, DMAs, and CSI/O.
6JGꢁ+PVGTTWRVꢋ6TCRꢁ%QPVTQNꢁ4GIKUVGTꢁꢈ+6%ꢉꢅꢁThe three Least Significant (LS) bits
of the ITC are individual ENABLE bits for the INT2, INT1, and INT0 pins. They
reset to 001respectively, so that requests on INT0 can be enabled by an EI
instruction after Reset, as is the case on the Z80. Other bits in this register identify
whether a TRAP or security exception has occurred.
0QPꢀ/CUMCDNGꢁ+PVGTTWRVꢁꢈ0/+ꢉ
The Z80S188 latches falling edges on the NMI pin. A falling edge clears the DME
bit in the DMA Status register (DSTAT), thereby disabling the on-chip DMA
channels. Only a Low on RESET or on BUSREQ take precedence over NMI.
Unless Reset or BUSREQ is Low, the Z80S188 checks for a falling edge on NMI
as it completes each instruction (each instruction iteration of HALT, the block I/O
instructions, block move instructions, and block scan instructions), and performs
an NMI sequence if a falling edge has occurred.
An NMI sequence includes four steps:
1. The Z80S188 copies the state of the IEF1 bit to IEF2.
2. The IEF1 is cleared to prevent maskable interrupts.
3. The SP decrements by 2, and stores the logical address in the PC in memory at
the new address in SP. Typically, this new address is the address of the
instruction the processor would have executed next, if no interrupt had
occurred. If the processor was stopped by HALT or SLP, it is the address of
the next instruction. For an incomplete block transfer, block scan, or block I/O
instruction, it is the address of the instruction.
4. The value 0066Hloads into PC, and execution resumes from that logical
address.
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0/+ꢁ*CPFNKPIꢅꢁNMI routines fall into two categories, based on whether or not the
external hardware that drives NMI can produce another falling edge on the pin,
before the routine completes its execution and returns to the interrupted process.
Debug monitors, that may display the state of the interrupt process, inherently fall
into the repeated edge category.
5KPINGꢁ'FIGꢁ)WCTCPVGGFꢅꢁꢁAn NMI routine in this category is much like any
other interrupt service routine. The initial option is provided of storing the
contents of the SP in memory and loading the SP with the address of a memory
area that is dedicated for its stack. In any case, it store as many of the registers as
it uses during its execution.
4GRGCVGFꢁ'FIGꢁ2QUUKDNGꢅꢁAn NMI routine in this category starts with PUSH AF,
then loads A from a dedicated location in memory that indicates whether the inter-
rupted process was, in fact, the NMI routine. If this location indicates that it was,
the routine immediately performs a POP AF and then an RETN instruction to return
to its former execution.
If the in NMI location is clear, software sets it to 1. At this point, if the NMI
routine takes either of the following actions:
Performs a DI instruction in a save the registers routine that it shares with other
means of entry, or
Displays the I register or the interrupt-enable state of the interrupted process, and
enables a user/programmer to change these (a debug monitor),
then an LD A,I instruction and another PUSH AF instruction is performed. This
action stores the I register at the address in SP plus one, and the interrupt enabled
state (IEF2) in the P/V flag and bit 2of the address in SP. If the NMI routine uses
a common save the registers subroutine that it shares with other entry points, the
save subroutine can perform a DI instruction to prevent its being interrupted by
maskable interrupts.
The NMI routine can now store SP in a dedicated location in memory, and load SP
with the address of its dedicated stack area.
In any case, the NMI routine perform a PUSH instruction to as many other regis-
ters as it uses. A debug monitor typically performs PUSH instructions to all regis-
ters in both banks, so that they display.
4GꢀGPCDNKPIꢁVJGꢁ&/#ꢁEJCPPGNUꢅꢁFairly early in an NMI service routine in an
application using the DMA channels, software reads the DSTAT register and re-
enables any DMA operation that was in progress, as described in section “NMI
and DME”, on page 62.
'ZKVKPIꢁVJGꢁ0/+ꢁTQWVKPGꢅꢁUpon completion of its processing, an NMI routine
restores the registers. If the routine used its own stack area, it then restores the SP
value of the interrupt process. If the routine set an in NMI memory location on the
way in, this location is cleared.
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NMI routines that did not save the I register and IEF2 state at the start finish with
an POP AF and a RETN instruction, which copies the state of IEF2 back into IEF1,
restoring the interrupt enable state of the interrupted process.
NMI routines that saved I and IEF2 at the start, finish with a POP AF instruction for
the saved I register and IEF2 bit, a LD I,A, followed by a JP V to a POP AF, EI, RET
sequence. If the JP does not occur, it is followed with POP AF, DI instructions if
one was not performed at the front end, and RET.
+06ꢃ
The on-chip PIOs, SIO, and CTC logically OR their interrupt requests with
external requests on the INT0 pin. The Z80S188 drives INT0 Low in an open-drain
fashion whenever any of these peripherals requests an interrupt.
+06ꢃꢁ/QFGUꢅꢁThe Z80S188 can handle interrupts requested by the on-chip PIOs,
SIO, CTC, or an external device on the INT0 pin, in either of two ways called
mode 1 or 2. The processor itself has another mode called mode 0, but this mode
cannot be used with the PIOs, SIO, or CTC. For completeness, this section
describes all three modes.
The special instructions IM 0, IM 1, and IM 2 select among these three modes.
RESET selects mode 0.
ZiLOG daisy-chainable peripherals, including the on-chip PIOs, SIO, CTC, are
designed for use in mode 2, although they can also be used in mode 1.
+PVGTTWRVꢁ#EMPQYNGFIGꢁ&CKU[ꢁ%JCKPKPIꢅꢁZ80 peripherals, including the on-chip
PIOs, SIO, CTC, use daisy chain signalling to decide amongst themselves, during
an INT0 interrupt acknowledge cycle, which of them responds to the cycle by
driving an 8-bit value onto the D7-0 data bus. Some other ZiLOG peripherals,
including the SCC and USC serial controller families, can also be used in such
daisy chains.
Such a daisy chain is illustrated in Figure 3. It implements a relatively fixed prior-
itization of interrupts among the devices in the chain. The highest-priority device
among those requesting on INT0 always has its IEI pin High. Its IEO pin is
connected to the IEI pin of the next-lower-priority INT0 device, and so on through
all of the INT0 devices. The IEO output of the lowest-priority INT0 device is not
used.
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CTC are always consecutive in the daisy chain, although their relative priority can
be programmed using bits 3-0 of the Interrupt Priority Register, which is illus-
trated on page 118.
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If any external peripherals have higher priority than the on-chip PIOs, SIO, and
CTC, the IEO pin of the lowest-priority among such device(s) is connected or
routed to the Z80S188’s IEI pin. If any external peripherals have lower priority
than the on-chip PIOs, SIO, and CTC, the Z80S188’s IEO pin is connected or
routed to the IEI pin of the highest-priority among such devices.
+06ꢃꢁ2TQEGUUQTꢁ4GURQPUGꢅꢁThe Z80S188 performs an INT0 interrupt sequence
at the end of an instruction (each instruction iteration for HALT, the block I/O
instructions, block move instructions, and block scan instructions), if all of the
following are true:
INT0 is Low,
Bit 0of the Interrupt/Trap Control register is 1to enable INT0,
The IEF1 bit is 1, to enable interrupts in general,
RESET and BUSREQ are both High, and
A negative edge on NMI has not been detected.
When all of these conditions occur simultaneously, the Z80S188 responds as
follows:
1. The IEF1 and IEF2 flags clear to prevent further interrupts.
2. M1 goes Low. This signal makes all ZiLOG daisy-chainable peripherals,
including the on-chip PIOs, SIO, and CTC, halt whether or not they are
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requesting an interrupt. This action allows the interrupt acknowledge daisy
chain to settle and select which Z80 peripheral responds to the cycle.
3. Several clock cycles pass to allow the daisy chain to settle.
4. IORQ goes Low. Simultaneous Lows on M1 and IORQ indicate an INT0
interrupt acknowledge cycle. In response to this condition, the highest-priority
ZiLOG peripheral that requests an interrupt places an 8-bit value on the D7-0
data bus.
5. WAIT is sampled, and the Z80S188 waits until WAIT is High.
6. The cycle is terminated when M1 becomes High, then IORQ becomes High.
While all INT0 acknowledge cycles follow this general pattern, they differ as to
what, if anything, the processor does with the data on D7-0, and what it does after
the acknowledge cycle. These actions depend on the most recently executed IM
instruction, if any, as described in the next three sections.
+06ꢃꢁ/QFGꢁꢃꢅꢁIf no IM instruction was executed since Reset, or if the most
recently executed IM instruction was IM 0, the Z80S188 completes an INT0
sequence as illustrated in Figure 4:
7. The Z80S188 samples D7-0 and interprets the value as an instruction Op Code.
In this mode, the vector registers of all ZiLOG daisy-chainable peripherals
must be programmed to provide one of the Reset Op Codes C7, CF, D7, DF, E7,
EF, F7, or FFH
0
ꢊ The Z80S188 does not automatically stack the contents of the program
counter during an INT0 Mode 0 interrupt sequence. The only other Op Code that a
peripheral can return, assuming the interrupted process is to be restarted is a
CALL instruction DCH. Intel 808x-family interrupt controllers can return a 3-byte
CALL instruction, but ZiLOG peripherals cannot.
8. If the Op Code is CALL, the processor fetches two more bytes to complete the
instruction.
9. Given that the Op Code is CALL or RST, the processor decrements SP by 2, and
stores the contents of PC in memory at the new address in SP. Typically, this is
the address of the instruction the processor would have executed next, if no
interrupt had occurred. If the processor was stopped by HALT or SLP, this
address is the address of the next instruction. For an incomplete block transfer,
block scan, or block I/O instruction, the address is the address of the
instruction.
10. If the Op Code was RST, the processor resumes execution at logical address
0000, 0008, ..., or 0038H. If the Op Code was CALL, it resumes at
the logical address fetched in step 8.
In mode 0, each peripheral connected to INT0 must have a register, the contents of
which is returned on D7-0 when it detects M1 and IORQ Low, an interrupt is
requested, and the IEI pin is High. Software programs each such register with one
of the RST Op Codes C7, CF, D7, ..., FFH.
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ꢊ The PIO and CTC included in the Z80S188 can only return vectors having
bit 0equal to 0. Since all of the RST Op Codes have bit 0equal to 1, if interrupts
are needed from the PIO or CTC, mode 0cannot be used.
If a peripheral has a feature whereby it can replace the low-order bits of this value
with a code reflecting its status, this feature must be turned off for mode 0opera-
tion.
If the number of devices that can interrupt on INT0 is reasonable, each device can
have its own RST instruction, which improves interrupt response time by elimi-
nating the need for the interrupt service routine to poll multiple devices.
If multiple devices are required to share a RST instruction, the interrupt service
routine polls these devices in the same priority order that they are arranged on the
IEI–IEO daisy chain. This action is necessary because a ZiLOG peripheral sets the
IUS bit when it detects M1 and IORQ Low, and it is requesting an interrupt, and the
IEI pin is High. To insure proper operation of the daisy chain in the future, the
polling process must lead to servicing the device that performed this process, and
then clearing the IUS bit either explicitly, or for a Z80 peripheral, by concluding
the ISR with a RETI instruction.
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+06ꢃꢁ/QFGꢁꢄꢅꢁThe following steps occur after step 6 of the section“INT0
Processor Response”, on page 19. If the most recently executed IM instruction
was IM 1, the Z80S188 completes an INT0 sequence as illustrated in Figure 5:
1. The data on D7–0is ignored. Actually, the device proceeds as in mode 0, but
captured FFHwhich is RST 38.
2. SP is decremented by 2, and stores the contents of PC in memory at the new
logical address in SP. Typically, this address is the address of the instruction
the processor would have executed next, if no interrupt had occurred. If the
processor was stopped by HALT or SLP, this address is the address of the next
instruction. For an incomplete block transfer, block scan, or block I/O
instruction, this address is the address of the instruction.
3. 0038H loads into PC, and resumes instruction execution from that logical
address.
In mode 1, the interrupt service routine is required to poll all of the devices
connected to INT0, to detect which one generated the interrupt. If any ZiLOG
peripherals, including the on-chip PIOs, SIO, or CTC, can request an interrupt,
this polling must be done in the same priority order that the devices are arranged
on the IEI–IEO daisy chain. This poll is required because a ZiLOG peripheral sets
the IUS bit when it detects M1 and IORQ Low, an interrupt is requested, and the IEI
pin is High, regardless of the processor’s IM status.
To insure proper operation of the daisy chain in the future, the polling process
must lead to servicing the device that set the IUS bit, and clearing that bit either
explicitly, or for a Z80 peripheral by concluding the ISR, with a RETI instruction.
Probably the best way to insure this is by actually polling the IUS bits, for devices
that allow them to be read.
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+06ꢃꢁ/QFGꢁꢆꢅꢁThe following steps occur after step 6 of the section “INT0
Processor Response”, on page 19. If the most recently executed IM instruction
was IM 2, the Z80S188 completes an INT0 sequence as illustrated in Figure 6:
1. The IEF1 and IEF2 flags clear to prevent further interrupts.
2. M1 goes Low. This signal makes all ZiLOG daisy-chainable peripherals,
including the on-chip PIOs, SIO, and CTC, halt whether or not they are
requesting an interrupt. This action allows the interrupt acknowledge daisy
chain to settle and select which Z80 peripheral responds to the cycle.
3. Several clock cycles pass to allow the daisy chain to settle.
4. IORQ goes Low. Simultaneous Lows on M1 and IORQ indicate an INT0
interrupt acknowledge cycle. In response to this condition, the highest-priority
ZiLOG peripheral that requests an interrupt places an 8-bit value on the D7-0
data bus.
5. WAIT is sampled, and the Z80S188 waits until WAIT is High.
6. The cycle is terminated when M1 becomes High, then IORQ becomes High.
7. The IEF1 and IEF2 flags clear to prevent further interrupts.
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8. M1 goes Low. This signal makes all ZiLOG daisy-chainable peripherals,
including the on-chip PIOs, SIO, and CTC, halt whether or not they are
requesting an interrupt. This action allows the interrupt acknowledge daisy
chain to settle and select which Z80 peripheral responds to the cycle.
9. Several clock cycles pass to allow the daisy chain to settle.
10. IORQ goes Low. Simultaneous Lows on M1 and IORQ indicate an INT0
interrupt acknowledge cycle. In response to this condition, the highest-priority
ZiLOG peripheral that requests an interrupt places an 8-bit value on the D7-0
data bus.
11. WAIT is sampled, and the Z80S188 waits until WAIT is High.
12. The cycle is terminated when M1 becomes High, then IORQ becomes High.
13. The data is captured from D7–0. D0 of this byte must be Low/0 for correct
operation.
14. SP decrements by 2, and stores the contents of PC in memory at the new logical
address in SP. Typically, this address is the address of the instruction the
processor would have executed next, if no interrupt had occurred. If the
processor was stopped by HALT or SLP, this address is the address of the next
instruction. For an incomplete block transfer, block scan, or block I/O
instruction, this address is the address of the instruction.
15. The contents of the I register are placed on A15–8, and the value captured in
step 7on A7–0, and fetches the LS byte of an interrupt service routine address
from memory at that address.
16. A0 goes High/1, and fetches the MS byte of the interrupt service routine
address from memory at that address.
17. Execution resumes at the logical address fetched in steps 9-10.
In mode 2, each peripheral connected to INT0 requires an Interrupt Vector
Register, the contents of which is returned when M1 and IORQ Low are detected,
an interrupt is requested, and the IEI pin is High. Software can program any of
these registers with any even binary value.
If a peripheral has a feature whereby it can replace the low-order bits of this value
with a code reflecting its status, this feature can be enabled in mode 2, in which
case the peripheral occupies more than one slot in the interrupt vector table. Such
status affects vector or vector includes status features can improve interrupt
response time, by reducing the amount of status-polling that the interrupt service
routine must do, to identify the exact cause of the interrupt.
+PVGTTWRVꢁ*CPFNKPIꢅꢁAny interrupt service routine has the initial option of saving
the contents of SP in memory, and loading SP with the address of a memory area
that is dedicated to its stack. Most interrupt service routines do not function in this
manner.
If the application includes a mechanism for allowing nested interrupts, the ISR can
begin as specified by that mechanism, leading to an IE instruction that allows the
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ISR to be interrupted by other interrupts. Most Z80S188 applications do not func-
tion in this manner.
The ISR reads status registers from each of the devices that can request the inter-
rupt, to identify the exact causes of the interrupt. The ISR then processes this
device(s) according to their design, and the application design.
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Many ISRs read data from the interrupting devices, or write data to them. In addi-
tion or alternatively, the ISRs may write commands to, or registers in the device,
to modify its mode, status, or operation in the future.
When all of the work of the ISR is complete, if nested interrupts are allowed, the
ISR terminates as specified by the nesting mechanism. If not, an ISR concludes
with an EI instruction followed by RET or RETI.
Interrupt service routines for Z80 peripherals, including the on-chip PIOs, SIO, or
CTC, terminate with a RETI instruction. As described in the next section, Z80
peripherals monitor the bus for these instructions, and clears the internal Interrupt
Under Service (IUS) status if one is detected. The IEI status indicates the ISRs are
the highest-priority device currently under service.
ISRs for non-Z80 peripherals must clear the device’s IUS bit explicitly. These
devices terminate with RET rather than RETI for two reasons:
If nested interrupts are allowed, and the interrupted process was an ISR for a Z80
peripheral, RETI clears that device’s IUS bit, inappropriately.
RET is both shorter and faster than RETI, and features the same function as for a
non-Z80 peripheral.
4'6+ꢁ+PUVTWEVKQPU
An interrupt service routine for a Z80 peripheral, including the on-chip PIOs, SIO,
and CTC, terminates with an RETI instruction. To the processor, RETI features the
same functionality as RET, but Z80 peripherals monitor the D7–0 lines, M1, and
RD, and detect when the processor is fetching an RETI.
If a Z80 peripheral detects an RETI, has its INTERRUPT UNDER SERVICE (IUS)
bit set, and its IEI pin is High, the interrupt service routine for this peripheral is
terminating. The peripheral clears the IUS bit. This action allows subsequent inter-
rupts from this device, or from lower-priority device on the daisy chain.
The original Z80 processor took four clock cycles to fetch an Op Code, and some
Z80 peripherals built this timing into their logic for detecting RETI instructions. If
the Z80S188 is fetching instructions from a zero-wait-state memory, it fetches
Op Codes using three-clock cycles, which can interfere with RETI detection by
external Z80 peripherals.
The Operating Mode Control Register, described on page 114, includes several
bits that affect the Z80S188’s compatibility with external Z80 peripherals.
$KVꢁꢑꢁꢈ/ꢄ'ꢉꢅꢁIf this bit is 1, as it is after a Reset, the Z80S188 drives M1 Low
when it fetches instruction Op Codes, as well as during INT0 and NMI acknowl-
edge cycles. Use this setting if the only Z80 peripherals in the system are the on-
chip PIOs, SIOs, and CTCs, and/or if all instructions are fetched from memory
with one or more wait states.
0
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1. The on-chip PIOs, SIO, and CTC can detect RETI instructions that are fetched
using three-clock bus cycles.
2. Older members of the Z8018x family refetched an RETI instruction in this mode,
which corrupt the daisy chain by clearing two IUS bits. The Z80S188, like other
recent members of the Z8018x family, does not function in this manner.
If software writes a 0to M1E, the Z80S188 does not drive M1 Low while fetching
instruction Op Codes. If an RETI instruction is detected, the device refetches the
RETI instruction, driving M1 Low and using at least four clocks per bus cycle. Use
this setting if there are external Z80 peripherals and zero-wait-state instruction
memory in the system. Figure 7 illustrates operation of RETI when M1E is 0.
$KVꢁꢐꢁꢈ/ꢄ6'ꢉꢅꢁIf software writes a 0to this bit, the Z80S188 drives M1 Low as it
fetches the next Op Code, regardless of the state of M1E. This capability is needed
after enabling interrupts on a PIO (external or onchip) with M1E 0, because the
PIO does not actually enable the interrupt request until it detects M1 Low.
M1TE resets to 1, always reads as 1, and is cleared to 1after the next Op Code is
fetched.
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The Z80S188 performs an INT1 or INT2 interrupt sequence at the end of an
instruction (each instruction iteration for HALT, the block I/O instructions, block
move instructions, and block scan instructions), if all of the following are true:
INT1 or INT2 is Low,
Bit 2or 1of the Interrupt/Trap Control register (ITC) is 1to enable this pin (if
both pins are enabled and Low, INT1 takes precedence over INT2)
The IEF1 bit is 1, to enable interrupts in general
INT0 is High or bit 0of the ITC is 0,
RESET and BUSREQ are both High, and
A negative edge on NMI has not been detected
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When all of these conditions occur simultaneously, the Z80S188 responds as
follows:
1. The IEF1 and IEF2 pins are cleared to prevent further interrupts.
2. SP decrements by 2, and stores the contents of PC in memory at the new
address in SP. Typically, this address is the address of the instruction the
processor would have executed next, if no interrupt had occurred. If the
processor was stopped by HALT or SLP, this address is the address of the next
instruction. For an incomplete block transfer, block scan, or block I/O
instruction, this address is the address of the instruction.
3. A logical memory address is formed using the contents of the I register as
A15–8, the three LS bits of the IL register as A7–5, and 0as A4–0 for INT1 or
2in A4–0 for INT2.
4. A 16-bit logical address is fetched from memory at that logical address, loaded
into PC, and resumes instruction execution from there.
+06ꢄꢀꢆꢁ*CPFNKPIꢅꢁAll of the considerations noted in the “Interrupt Handling”, on
page 24 for INT0, also apply to ISRs for INT1 and INT2. If there is more than one
device that can drive INT1 or INT2 Low, the interrupt service routine for that pin
must poll all the devices connected to that pin, to determine which of them caused
the interrupt.
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The Z80S188 performs an interrupt sequence for one of these devices, at the end
of an instruction (each instruction iteration for HALT, the block I/O instructions,
block move instructions, and block scan instructions), if all of the following are
true:
An interrupting condition in the device has occurred
That condition is interrupt-enabled in the device’s registers
The IEF1 bit is 1, to enable interrupts in general
No higher-priority internal device is requesting an interrupt (see Table 3 for the
relative priorities of the devices)
Neither INT1 nor INT2 is enabled and Low
INT0 is High or bit 0of the ITC is 0
RESET and BUSREQ are both High
A negative edge on NMI has not been detected
When all of these conditions occur simultaneously, the Z80S188 responds as
follows:
1. The IEF1 and IEF2 flags are cleared to prevent further interrupts.
2. SP decrements by 2, and stores the contents of PC in memory at the new
address in SP. This address is the address of the instruction the processor would
have executed next, if no interrupt had occurred. If the processor was stopped
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by HALT or SLP, this address is the address of the next instruction. For an
incomplete block transfer, block scan, or block I/O instruction, this address is
the address of the instruction.
3. A logical memory address is formed using the contents of the I register as
A15–8, the three LS bits of the IL register as A7–5, and the value
corresponding to the interrupting device (see Table 3) as A4–0.
4. A 16-bit logical address is fetched from memory at that logical address, loaded
into PC, and resumes instruction execution from there.
1Pꢀ%JKRꢁ+PVGTTWRVꢁ*CPFNKPIꢅꢁThe only difference between handling an ASCI,
PRT, DMA, CSI/O, or ZDI interrupt, and the considerations noted in “Interrupt
Handling”, on page 24 for INT0, are that the ISR for an on-chip device never
needs to differentiate among several devices connected to an INT pin.
6
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The Z80S188 includes a 64-KB logical memory space in which software operates,
and an 8-MB physical memory address space in which on-chip and external
memory reside. The Memory Management Unit (MMU) translates 16-bit logical
addresses to 23-bit physical addresses dynamically, as part of each memory
access.
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On the Z80S188, memory is divided into five categories:
4-KB of on-chip ROM, or an external EPROM connected to ROMCS
1-KB of on-chip RAM
External memory connected to MEMCS0,
External memory connected to MEMCS1
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External memory using off-chip decoding
Table 29 describes the On-chip Memory Control Register (OCMCR), which
controls whether on-chip RAM, and either on-chip ROM on a masked part, or the
ROMCS output on an unmasked part, are enabled.
If on-chip ROM (or the ROMCS output) is enabled, physical addresses 000000-
000FFFHbecome Low. If on-chip RAM is enabled, it occupies addresses
00FC00-0FFFFH or 7FFC00-7FFFFFH, depending on bit 6 of the OCMCR.
Reset enables on-chip RAM, and on-chip ROM or the ROMCS output at
00FC00-00FFFFH.
Tables 42 through 45 describe the Memory Chip Select High and Low Registers
for the MEMCS0 and MEMCS1 pins. If the Size/Enable field of a pin’s Low
Register are 0000H, the pin remains High, and any memory connected to this pin
is disabled. For MEMCS0, this field resets to 1001Hand the comparison bits
reset to all 0s, so that MEMCS0 is Low for addresses 001000-007FFFH.For
MEMCS1, the Size/Enable field resets to 0001H, so that MEMCS1 is Low for
addresses 008000-00FB00Hand 010000-7FFFFFH.
For each pin, software can select any number of high-order address lines, from
A22 through A13, to be compared for equality against a programmed value. Each
pin can become Low for any block of contiguous addresses between 8 KB and 4
MB in length, starting at a multiple of that length. Alternatively, software can
select the entire 8-MB address range for a pin.
If the ranges for MEMCS0 and MEMCS1 overlap, MEMCS0 takes precedence in
the region of overlap.
When programming any of these registers, software must not disable or change
the mapping of the addresses where the affected code sequence is located.
#FFTGUUKPIꢁ/QFGU
This term traditionally means how an instruction can specify a memory address.
For the Z80S188 these include:
4GNCVKXGꢁ#FFTGUUKPIꢅꢁJR and DJNZ instructions include a signed 8-bit displace-
ment that specifies a range of addresses -126 to +129 from the Op Code, to which
program control can be transferred.
&KTGEVꢁ#FFTGUUKPIꢅꢁIn this mode, instructions include a 16-bit logical address.
4GIKUVGTꢁ+PFKTGEVꢁ#FFTGUUKPIꢅꢁThe address is taken from one of the register pairs
BC, DE or HL.
+PFGZGFꢁ#FFTGUUKPIꢅꢁIn this mode, instructions include an 8-bit signed displace-
ment from the address in an index register IX or IY.
Other contexts in which memory is accessed include instruction fetching, inter-
rupts, DMA operations, cycles generated by external masters while BUSACK is
Low, and possibly DRAM Refresh cycles.
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The MMU translates the 16-bit addresses used by software, called logical
addresses, into 20- or 23-bit physical addresses, as part of all memory accesses
performed by the processor. It has no effect on accesses performed by the DMA
channels, which include 23-bit address registers. It also has no effect on addresses
in I/O space, which always have A22-16 all 0.
The MMU resets to a state in which it has no effect on addresses in processor
cycles, passing A15-0 through without change and keeping A22-16 all 0. If an
application requires 64 KB of memory or less, the MMU is not necessary.
Even when the MMU has been programmed to do active address transaction, it
passes A11-0 (or A9-0 depending on its operating mode) from the logical to the
physical address without change. In other words, it manages memory in 4-KB (or
1-KB) byte blocks.
The Z80S188’s MMU can operate in either of two modes: Classic and Extended.
Reset selects Classic mode, in which the MMU registers at I/O addresses 0038-
003AHhave the same functionality as on the Z80180 and other 8018x family
members (introduced before the Z80S188). This mode is limited to a 1-MB
address space, and manages memory in 4-KB blocks.
By executing three specific I/O operations in succession:
1. IN from 003BH
2. IN from 003DH
3. OUT to 003CH
software selects the EXTENDED mode of MMU operation.
Extended mode expands the physical memory address space to 8 MB, and reduces
the unit of memory management to 1-KB blocks. The I/O registers at 0038-003H
operate differently, and are augmented by additional registers at 003B-003H
0
ꢊ
1. The Out operation (step 3, previously) does not actually write the register
at 00CH.
2. Changing from Classic to Extended mode does not change the memory
mapping in effect. Instead, the contents of registers 0038-003AHare
rearranged to reflect the new mode.
3. Software selects Extended mode as part of device initialization, before
interrupts are enabled. When interrupts are enabled, the software guaran-
tees that the three I/O instructions are consecutive by performing them
between DI and EI instructions.
4. Software can change back from Extended to Classic mode by using the
sequence IN from 003BH, IN from 003DH, IN from 003CH.
“MMU Registers”, on page 118, describes the registers associated with the MMU.
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%NCUUKEꢁ/QFGꢁ1RGTCVKQPꢅꢁIn Classic mode, the MMU compares bits 15-12of
each logical address to two 4-bit fields in its Common Base Address Register
(CBAR), in an unsigned manner.
If bits 15-12of a logical address are less than the value in bits 3-0 of the CBAR,
the MMU considers the address to be in Common Area 0. For these addresses, the
MMU passes bits 15-12to the A15-12 pins unchanged, and drives A22-16 all
0s.
If bits 15-12of a logical address are greater than or equal to the value in bits 3-
0 of the CBAR, but are less than the value in bits 7-4of the CBAR, the MMU
considers the address to be in the Bank Area. For these addresses, the MMU adds
the value in its 8-bit Bank Base Register (BBR) to bits 15-12of the logical ad-
dress, and outputs the 8-bit sum on A19-12 with A22-20 all 0s.
If bits 15-12of a logical address are greater than or equal to the value in bits 7-
4 of the CBAR, it considers the address to be in Common Area 1. For these ad-
dresses, the MMU adds the value in its 8-bit Common Base Register (CBR) to bits
15-12of the logical address, and outputs the 8-bit sum on A19-12 with A22-20
all 0s.
0
ꢊ In Classic mode, software must not program the value in bits 7-4of the
CBAR to be less than the value in bits 3-0of the CBAR.
'ZVGPFGFꢁ/QFGꢁ1RGTCVKQPꢅꢁIn Extended mode, the MMU compares bits 15-10
of each logical address to bits 7-2of its Bank Area Register (BAR) and Common
Area Register (CAR), in an unsigned manner.
If bits 15-10of a logical address are less than the value in bits 7-2 of the BAR,
the MMU considers the address to be in Common Area 0. For these addresses, the
MMU passes bits 15-10to the A15-10 pins unchanged, and drives A22-16 all
0s.
If bits 15-10of a logical address are greater than or equal to the value in bits 7-
2of the BAR, but are less than the value in bits 7-2of the CAR, the MMU con-
siders the address to be in the Bank Area. For these addresses, the MMU adds the
13-bit value in its Bank Base Registers High and Low (BBRH and BBRL) to bits
15-10of the logical address, and outputs the 13-bit sum on A22-10.
If bits 15-10of a logical address are greater than or equal to the value in bits 7-
2 of the CAR, it considers the address to be in Common Area 1. For these address-
es, the MMU adds the 13-bit value in its Common Base Registers High and Low
(CBRH and CBRL) to bits 15-10of the logical address, and outputs the 13-bit
sum on A22-10.
0
ꢊ In Classic mode, the value in bits 7-2 of the CAR must not be
programmed to be less than the value in bits 7-2of the BAR.
//7ꢁ%QPHKIWTCVKQPUꢅꢁIn the general case, the MMU divides the 64-KB logical
memory space into three parts, with Common Area 0 always located at the start of
the physical address space, and the Bank Area and Common Area 1 relocatable to
other parts of the physical address space, by the values in the Bank Base Register
and Common Base Register, respectively.
ꢊꢎ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
/
ꢀꢐ41/ꢀ
ꢀ4#/ꢑ
1
&
Certain combinations of values in the CBAR in Classic mode [or BAR and CAR
in Extended mode] result in the logical address space being divided into fewer
active areas:
If the CBAR [or BAR and CAR] contains all 0s, all logical addresses fall into
Common Area 1, and are relocated to a contiguous 64-KB area starting at the
address in the CBR times 4096 [or the value in CBRH6-0 and CBRL7-2, times
1024].
If CBAR3-0 are 0but CBAR7-4 are non-0[or bits 7-2of the BAR are 0but bits
7-2of the CAR are non-0], the Bank Area and Common Area 1 are active.
Logical addresses less than (CBAR7-4)*4096, or (CAR7-2)*1024are relo-
cated by the Bank Base Register, while other addresses are related by the
Common Base Register.
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢊꢊ
1
&
/
ꢀꢐ41/ꢀ
ꢀ4#/ꢑ
If BAR7-2 and CAR7-2 are equal and not 0, Common Area 0 and Common Area
1 are active. Logical addresses less than (CBAR3-0)*4096, or (BAR7-
2)*1024are not relocated, and map to the start of physical memory. Other
addresses are relocated by the Command Base register.
6JGꢁ//7ꢁ#HVGTꢁ4GUGVꢅꢁSince the MMU resets to Classic mode and the CBAR
resets to 11110000, logical addresses 0000-EFFFHare in the Bank Area and
F000-FFFFHare in Common Area 1. But since the BBR and CBR both reset to
0, the MMU passes all logical addresses through without change, with A22-16 all
0s.
1Pꢀ%JKRꢁ41/ꢁQTꢁ41/%5ꢁ&GXKEG
Bit 5in the On-Chip Memory Control Register (page 115) controls whether phys-
ical addresses 00000-00FFFHaccess external memory, vs. on-chip ROM on a
masked part, or memory connected to the ROMCS pin on an unmasked part. If
this bit is 1, as it is after a Reset, on-chip ROM or ROMCS is enabled.
1Pꢀ%JKRꢁ4#/
Bits 7-6in the On-Chip Memory Control register (page 115) control processor
access to on-chip RAM.
If bit 7is 0, on-chip RAM is disabled.
If bits 7-6are 10, as they are after a reset, on-chip RAM does not decode A22-16
of physical addresses, and responds to all physical addresses having A15-11 all 1,
which we might call addresses xxF800Hthrough xxFFFFH.
If bits 6-5are 11, on-chip RAM responds to physical addresses with A22-11 all
1: addresses 7FF800-7FFFFFH.
'ZVGTPCNꢁ/GOQT[ꢁ7UKPIꢁ/'/%5ꢃꢀꢄ
Tables 42-45 on pages 123-126 describe the registers for the Memory Chip Select
and Wait block. For each pin there is a high and a low register.
5K\Gꢋ'PCDNGꢁ(KGNFꢅꢁBits 5-2of each Low Register are the Size/Enable field. Table
4 describes the possible values of this field.
In all cases, if the address ranges for MEMCS0 and MEMCS1 overlap, MEMCS0
is Low and MEMCS1 is High for addresses in the region of overlap.
ꢊꢉ
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25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
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ꢀꢐ41/ꢀ
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&
6
ꢁꢎꢅ 5 ꢋ'
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.QYꢀYJGPꢀ#ꢎꢎꢌꢂꢉꢀꢒꢀJKIJꢀTGIꢀꢔꢀDKVꢀꢍꢀQHꢀNQYꢀTGIꢀꢐꢂꢏ-ꢀRCTVKVKQPꢑ
.QYꢀYJGPꢀ#ꢎꢎꢌꢂꢊꢀꢒꢀJKIJꢀTGIꢀꢔꢀDKVUꢀꢍꢌꢏꢀQHꢀNQYꢀTGIꢀꢐꢇ-ꢀRCTVKVKQPꢑ
4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
9CKVꢁ5VCVGUꢁ(KGNFꢅꢁBits 1-0of each low register control how many Wait states
the Z80S188 generates for memory accesses in which that pin goes Low, as
described in Table 5. These bits reset to 11(three Wait states).
0
ꢊ OR instructions are performed on these wait states with the number
selected by the Central Wait State Generator described on page 36, and wait states
generated by the external WAIT pin. That is, the cycle completes only after all
three sources have permitted completion.
6
ꢁꢏꢅ /'/%5ꢃꢀꢄꢁ9 ꢁ5
.QYꢁ4GIꢁ$KVUꢁꢄꢀꢃ 9CKVꢁ5VCVGU /KPꢁ%NQEMUꢋ%[ENG
ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
ꢃ
ꢂ
ꢎ
ꢊ
ꢊ
ꢉ
ꢆ
ꢏ
'ZVGTPCNꢁ/GOQT[ꢁYKVJꢁ'ZVGTPCNꢁ&GEQFKPI
If there are more than two types of external memory (three, counting a ROMCS
device on an unmasked part), external address decoding logic is necessary to
decode separate selection for two or more of the categories. There are three
methods of designing this logic:
(WTVJGTꢁ&GEQFKPIꢁQHꢁ/'/%5ꢃꢀꢄꢅꢁThis method uses the Low state of MEMCS0
or MEMCS1 to qualify decoding of the highest address lines not used in generating
the MEMCS output. RD and WR can be used directly as Low-active Output
Enables and Write Enable controls on the memory. This method is the simplest,
but is a few nanoseconds slower than the following methods.
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢊꢆ
1
&
/
ꢀꢐ41/ꢀ
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(WNNꢁ&GEQFKPIꢁ3WCNKHKGFꢁD[ꢁ/'/43ꢅꢁThis method uses the Low state of
MEMRQ to qualify decoding of as many address lines as necessary, from A22 on
down. RD and WR can be used directly as Low-active Output Enable and Write
Enable controls on the memory.
(WNNꢁ&GEQFKPIꢍꢁ5VTQDGUꢁ3WCNKHKGFꢁD[ꢁ/'/43ꢅꢁUsing this method, logic
decodes chip selection from the address lines only, but performs AND instructions
(positive-logic OR function) on the Low state of MEMRQ with Lows on RD and
WR. This action produces Output Enable and Write Enable controls for the
memory.
Depending on the memory device timing, either of these choices may yield the
highest performance, or the greatest timing margin. With either of these two
methods, software ensures that any memory connected to MEMCS0-1 is never
selected for the same read cycle as the externally-decoded memory.
%GPVTCNꢁ9CKVꢁ5VCVGꢁ)GPGTCVQT
The Z80S188 includes a register that controls automatic insertion of wait states
into all memory and I/O accesses. The output of this generator performs logical
OR instructions (Low-active OR, positive-logic AND) with wait contributions
from other on-chip wait state logic and the external WAIT pin. The result is that for
a given address, the number of wait states taken is the largest number among these
facilities and any external wait-state generator.
The DMA/Wait Control register (DCNTL) is described on page 142, and is
present on all 8018x family members. The DCNTL is located in the DMA register
address range, but its wait states apply to accesses by the processor as well as
those generated by the DMA channels.
Bits 7-6 of DCNTL select the number of waits states for all memory accesses, as
described below:
&%06.ꢑꢀꢐ
9CKVꢁ5VCVGU
/KPꢁ2*+ꢁ%NQEMUꢋ%[ENGꢁHQTꢁ/GOQT[
ꢃꢃ
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ꢂꢂ
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ꢂ
ꢎ
ꢊ
ꢊ
ꢉ
ꢆ
ꢏ
&4#/ꢁ4GHTGUJ
ZiLOG’s Z80 and Z8018x families have traditionally included dynamic RAM
refresh logic. This logic is identical on all Z8018x devices including the Z80S188.
The Refresh Control Register (RCR), described on page 114, controls the DRAM
refresh feature. When bit 7 is 1, as it is after a reset, the part generates DRAM
refresh cycles. Z80S188 applications, which do not include dynamic memory,
write an all-0 byte to the RCR as part of initialization. This action disables DRAM
refreshing, and saves the bus bandwidth that would otherwise be taken by refresh
cycles.
ꢊꢏ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
+
ꢋ1
1
&
If bits 7-6 are 11, as they are after a reset, refresh cycles are three clocks long,
while if they are 10, refresh cycles are two clocks long. Figure 8 illustrates the
timing of a 3-clock refresh cycle; a two-clock cycle eliminates the middle clock
cycle (the one labelled T ).
RW
If bit 7 is 1, bits 1–0 of the RCR control how often refresh cycles occur, as
described in Table 6.
6
6
6
(
ꢂꢅ ꢌꢀ%
ꢁ4
ꢁ%
0
ꢊ * If three refresh cycles are specified, T
is inserted. Otherwise, T
is
RW
RW
not inserted.
ꢁꢐꢅ 4
4%4ꢄꢀꢃ 4GHTGUJꢁ%[ENGꢁ(TGSWGPE[
6
ꢁ%
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ꢉꢃꢀ2*+ꢀENQEMU
ꢇꢃꢀ2*+ꢀENQEMU
+0276ꢋ176276
The Z80S188 includes an I/O space that is distinct from memory space. This I/O
space is accessed by means of IN and OUT instructions rather than LD, PUSH,
POP, and other instructions that access memory space. The MMU passes addresses
in I/O space through without change; such addresses always have A22-16 all 0.
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
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ꢊꢍ
1
&
+
ꢋ1
+ꢋ1ꢁ+PUVTWEVKQPU
The original Z80 featured a 256-byte I/O space. The following instructions are
specific to this 256-byte I/O space, and must only be used to access I/O devices
that do not decode A15-8.
On the Z80S188, bit 7 of the Interrupt Priority Register (INTPR) controls whether
the SIO, PIO, CTC, WDT, Chip Select and Wait registers, and the Interrupt Priority
register itself, decode A15-8 all 0, or ignore these lines. If this AllPageIO bit is 1,
the following instructions can be used for these registers.
In no case can these instructions be used for the other registers on the port. The
80180 registers are:
OUT (port),A
IND
INDR
INI
INIR
OTDR
OTIR
OUTD
OUTI
The following instructions ensure that A15-8 are all 0, and can be used to access
any of the Z80S188’s on-chip I/O registers, as well as external devices that decode
A15-8 as all 0:
IN0 r,(port)
OUT0 (port),r
OTDM
OTDMR
OTIM OTIMR
The following instructions drive A15-0 from the BC register pair, and can be used
to access the full 64-KB I/O space:
IN r,(C)
OUT (C),r
The following instruction can be used to access the entire 64-KB register space,
but only by first loading the MS 8 bits of the address into A. This step is not neces-
sary for devices that do not decode A15-8, including the SIO, PIO, CTC, WDT,
CHIP SELECT and WAIT registers when the AllPageIO bit is 1.
IN
A,(port)
4GNQECVKPIꢁVJGꢁꢂꢃꢄꢂꢃꢁTGIKUVGTU
The “Registers Summary”, on page 109 describes how the Z80S188’s I/O regis-
ters are divided into 80180 registers and Z80S188-specific registers. The latter
registers are always located in the range 00D0-00FCH. After a reset, the 80180
registers are located in the range 0000-003HF, but bits 7-6 of the I/O Control
ꢊꢇ
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25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
+
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1
&
register (page 115) allow software to relocate the 80180 registers to higher
addresses:
+1%4ꢁꢑꢀꢐ ꢄꢂꢃꢁ4GIKUVGTꢁ#FFTGUUGU
ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
ꢃꢃꢃꢃꢌꢃꢃꢊ(
ꢃꢃꢉꢃꢌꢃꢃꢍ(
ꢃꢃꢇꢃꢌꢃꢃ$(
4GUGTXGF
This facility was included to ease porting of Z80 applications to the Z8018x
family, but use it with care, as certain tools may assume that the 80180 registers
are located in the 0000-003FHrange. These tools must be reconfigured to allow
for relocated 80180 registers.
+ꢋ1ꢁ%JKRꢁ5GNGEV
The Z80S188 includes one I/O CHIP SELECt pin (IOCS), controlled by the I/O
Chip Select high and low registers (IOCSH, IOCSL), which are described on
page 127.
Bit 4 of the low register controls whether or not the decode logic matches A15-8
equal to the high register.
Bits 3-2 of the low register are a Size field, and control how the logic matches Bits
7-5 of the low register against A7-5, as described in Table 7.
6
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#ꢍꢌꢆꢀꢒꢀDKVUꢀꢍꢌꢆꢀQHꢀNQYꢀTGIKUVGT
For I/O cycles that drive IOCS Low, bits 1-0 of the low register select how many
wait states the I/O Chip select logic add to such cycles. These bits can be consid-
ered to add 0-3 Wait states to a base cycle of 4 clocks, or to add 1-4 Wait states to
a basic 3-clock cycle. In either case:
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢊꢁ
1
&
+
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ꢃꢃ
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%GPVTCNꢁ+ꢋ1ꢁ9CKVU
As noted in a previous section, bits 5-4 of the DMA/Wait Control Register can be
used to insert wait states into I/O cycles with the Z80S188-specific registers at
addresses 00D0-00FCH, and into I/O cycles with external devices. These bits
add 0-3 Wait states to a base cycle of 4 clocks, or add 1-4 Wait states to a basic 3-
clock cycle:
&%06.ꢏꢀꢎ
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ꢃꢃ
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ꢆ
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+143ꢁCPFꢁ4&ꢁ6KOKPI
Bit 5 in the Operating Mode Control Register (OMCR, described on page 114)
controls the timing of the IORQ signal for accesses to non-180 I/O registers, and
the timing of the RD signal when software reads from an non-180 I/O register.
If this bit is 1, as it is after a reset, the Z80S188 drives IORQ (and RD if applicable)
Low from the falling edge of PHI in the T1 clock cycle, which is compatible with
the Hitachi 64180. If this bit is 0, the Z80S188 drives IORQ (and RD if applicable)
Low one-half clock cycle later, from the rising edge of PHI at the start of T2,
which is compatible with the ZiLOG Z80. Both cases are illustrated in Figure .
6ꢂ
6ꢎ
6Y
6ꢊ
2*+
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4& ꢐ1/%4ꢆꢒꢂꢑ
4& ꢐ1/%4ꢆꢒꢃꢑ
94
(
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ꢁ6
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25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
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1
&
%.1%-+0)
The Z80S188 can be clocked in either of two ways:
1. By an external TTL- or CMOS-level clock on the EXTAL pin
2. By a crystal connected to its XTAL and EXTAL pins
For an external clock, the signal must be free of overshoot or ringing, must make
continuous, monotonic, and rapid transitions in both directions, and must meet the
minimum High and Low times specified in “AC Characteristics”.
/WNVKRN[ꢁD[ꢁꢆꢁ1RVKQP
Regardless of whether EXTAL is connected to a crystal or an external clock signal,
bit 7 of the Clock Multiplier register (CMR, described on page 112) controls
whether or not the Z80S188 multiplies the frequency of EXTAL by two.
If CMR bit 7 is 1, the part multiplies the frequency by two. If this bit is 0, as it is
after a reset, the part does not perform the multiplication.
This feature can be used with crystals (or external clocks) up to 16.67 MHz. This
feature may allow use of a lower-cost crystal, and eliminates the need for an LC
tank circuit, described in “Circuits”, on page 41.
&KXKFGꢁD[ꢁꢆꢁ1RVKQP
Bit 7 of the CPU Control Register (CCR, described on page 113) controls whether
the Z80S188 uses the signal from the clock multiplier directly as PHI, or whether
it divides the signal by two to obtain PHI.
If CCR bit 7 is 0, as it is after a reset, the part divides the signal from the clock
multiplier by 2. This mode insulates the part against an asymmetric waveform.
Software can write a 1 to CCR bit 7 as part of device initialization, to use the
selected signal directly.
If an external clock is connected to EXTAL, and neither the *2 nor /2 option is
used, the waveform on EXTAL must meet the minimum High and Low times spec-
ified in “AC Characteristics”, on page 203.
%KTEWKVU
When using a crystal connected to XTAL and EXTAL, locate it as close as possible
to the pins, and minimize the trace lengths among the crystal, pins, and the two
capacitors illustrated in Figure 10, which illustrates the connection of a funda-
mental mode crystal up to and including 20 MHz. C1 and C2 are 20-30 pF, a
typical value for which is 22 pF.
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For frequencies above 20 MHz, use a third-overtone crystal and include a C-L
tank circuit to filter the fundamental frequency, as illustrated in Figure 11. Again,
it is essential to minimize trace lengths by locating all of the components as close
as possible to the XTAL and EXTAL pins.
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For fundamental mode crystals up to 20 MHz:
Fundamental, parallel type (AT cut recommended)
Load capacitance: C = C1 = C2 = 20-30 pF (22 pF typical)
L
Equivalent Resistance R < 60 ohms
S
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Bit 6 in the Clock Multiplier Register, described on page 112, controls the drive
(gain) of the oscillator. When this bit is 0, as it is after a reset, the Z80S188 drives
a crystal connected to XTAL and EXTAL in an energetic manner, to guarantee that
oscillation always starts. This drive is suitable for traditional crystals packaged in
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turized applications like PCMCIA.
To reduce the drive/gain of the oscillator, software writes a 1to bit 6 of the Clock
Control Register as part of initialization. This action reduces the drive to about
25% of Normal mode, and also reduces the maximum oscillator frequency from
33 to 20 MHz.
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How Reset affects each of the registers in I/O space is described in the section,
“I/O Registers”, on page 109. Among processor registers, the following registers
and state bits are cleared to 0: PC, SP, I, IEF1, IEF2, R, and F. The following are not
changed by Reset: A, B, C, D, E, H, L, IX, and IY.
The Z80S188 resets itself at power-up. When power is applied internally, the
Z80S188 detects the power rising. After the oscillator starts, the Power On Reset
16
circuitry holds the Z80S188 in reset for 2 clock cycles, driving RESET low to
provide a reset to external peripherals.
Another possible source of reset is the Watch-Dog Timer (WDT). See section
“Watch-Dog Timer”, on page 63, for more about the WDT.
219'4ꢁ/#0#)'/'06
As on other members of the 8018x family, the Z80S188’s main power saving
modes are controlled by the Standby and Idle/Quick bits in the CPU Control
Register (page 113), the IOSTOP bit in the I/O Control Register (page 115), and
the execution of SLP and HALT instructions. Section “Low-Power Modes”, next,
describes the low-power modes.
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The IOSTOP bit in the I/O Control Register (page 115) controls operation of the
ASCIs, PRTs and CSI/O. When this bit is 0, these peripherals operate normally.
When this bit is 1, they are disabled, reducing power use.
The Standby and Idle/Quick bits in the CPU Control Register (page 113) control
the actions of the Z80S188 when it executes an SLP instruction. If the application
uses the XTAL/EXTAL oscillator and Standby is 1, a SLP instruction stops the
oscillator, leading to the lowest power consumption of any mode. This action
requires time to restart the oscillator in response to Reset, an interrupt request, or a
bus request.
When Standby is 1, the Idle/Quick bit controls how many PHI clocks the
Z80S188 waits after re-enabling the oscillator, before restarting operation, with 0
17
selecting 2 (128K) clocks, and 1selecting 64 clocks.
When Standby is 0, the oscillator runs for the duration of the SLP instruction, but
clocking is blocked to most of the Z80S188. In this case, the Idle/Quick bit
controls whether the oscillator output is driven onto the PHI pin, with a 1in Idle/
Quick disabling clocking on PHI.
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When Standby is 1, the BREXT bit, bit 5 in the CPU Control Register (page 113),
controls whether the Z80S188 restarts the oscillator in response to a Low on the
BUSREQ pin, with a 1enabling these responses.
The interaction of these various bits and states is detailed in Table 8 below,
including the conditions that cause the Z80S188 to leave each low-power mode
and resume normal operation.
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In SLEEP, SYSTEM STOP, IDLE, or either STANDBY mode, if the Z80S188
leaves the mode because of an NMI or an enabled interrupt with the IEF1 flag 1, it
resumes operation by performing the interrupt, with the return address being the
instruction after the SLP. If the device exits the low-power mode because of an
individually-enabled interrupt request, but the IEF1 bit is 0, the Z80S188 resumes
by executing the instruction after the SLP.
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The Z80S188 includes the equivalent of two Z80 PIO devices, which provide four
ports called Port A through Port D. Each port includes 8 data pins named PA7-0,
PB7-0, PC7-0, or PD7-0, an input Strobe ASTB, BSTB, CSTB, or DSTB, and an
output Ready signal ARDY, BRDY, CRDY, or DRDY.
Two consecutive addresses in I/O space are associated with each port. As for the
other Z80 peripherals on the Z80S188, bit 7 of the Interrupt Priority Register
controls whether A15-8 are decoded as all 0for these addresses, as for the
80180 peripherals, or whether A15-8 are ignored so that Z80-compatible I/O
instructions can be used to access the PIOs. The following table shows only bits
7-0of each PIO address.
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An OUT instruction to the lower (Data) address for each port sets output data,
while an IN instruction from the lower (Data) address reads input data. The
Z80S188 decodes the less significant bits of data written to the higher (Control)
address for each port, thus categorizing such output into the following words:
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Two other kinds of output words can contain any data, and are implicitly the target
of an OUT instruction to the Control address following certain other Words.
After a Mode Control Word where bits 7-6 are 11is written to the Control
address, the next OUT to the Control address is implicitly an I/O Register Control
Word, in which 1s identify input pins and 0s identify outputs.
After an Interrupt Control Word where bit 4 is 1is written to the Control address,
the next OUT to the Control address is implicitly a Mask Control Word, in which
0s identify pins that can cause an interrupt.
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Software can set each port into one of four modes, by writing a Mode Control
Word to the port’s Control address. Each mode is numbered according to the
binary value of bits 7-6 of the Mode Control Word, and is also named.
1WVRWVꢁOQFGꢋOQFGꢁꢃꢅꢁIn this mode, all 8 port pins are outputs. The XRDY pin
goes High when software or a DMA channel writes data to the port’s Data
register. A Low pulse on the XSTB pin indicates when external logic has acquired
the data. A rising edge on XSTB makes the Z80S188 drive the XRDY line back
Low, and can be programmed to cause an interrupt request from the port.
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ꢊ Because PIO ports do not provide a status register, the only alternative to
enabling interrupts for a port operating in mode 0, 1, or 2, is to connect the port’s
XRDY line to a port pin of another port, that is operating in BIT CONTROL
mode.
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sequence of transfers by doing a dummy read from the port’s Data address, which
drives XRDY High as a data request to external logic. That logic drives XSTB Low
to signify that it has provided data on the port pins. The Low level of XSTB opens
the Data register latches, and the rising edge latches the data, makes the Z80S188
drive XRDY Low, and can be programmed to cause an interrupt request from the
port. When this interrupt occurs, or when software detects XRDY Low in another
port, it can read the captured data from the port’s Data address, which again drives
XRDY High.
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because it uses the BRDY and BSTB pins in conjunction with port A, or uses the
DRDY and DSTB pins in conjunction with port C. When this mode is selected for
port A or C, the only mode that can be used on port B or D (respectively) is BIT
CONTROL mode, mode 3.
To simplify the language, this mode is described for port A. ARDYand ASTB are
used for output handshaking, as in mode 0, while BRDY and BSTB are used for
input handshaking, as in mode 1.
If interrupts are enabled for port A, its interrupt vector is returned when ASTB
goes High for an output handshake. If interrupts are enabled for port B, its inter-
rupt vector is returned when BSTB goes High for an input handshake, or if a mode
3 interrupt condition is programmed for port B, and it occurs on the PB7-0 lines.
This ambiguity can be avoided by programming port B’s Mask Control Word with
all ones, to disable mode 3 interrupts.
Bidirectionality is achieved by having the Z80S188 drive output data onto the
PA7-0 (or PC7-0) pins in this mode, only when external logic drives ASTB (or
CSTB) Low. Obviously, external logic must not drive any of the PA7-0 (or PC7-0)
pins at the same time that it drives ASTB (or CSTB) Low.
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inputs and outputs. After writing 11 to bits 7-6 in a Mode Control Word, software
next writes an I/O Register Control Word to the port’s Data address, containing a 1
for each port pin that is an input, and a 0 for each port pin that the Z80S188 drives
as an output. When this value is written, the Z80S188 immediately begins driving
pins corresponding to 0, and releases drive on pins corresponding to 1.
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In this mode, the port’s READY and STROBE pins are not used in conjunction
with this port. Instead, the port can interrupt based on conditions on its port pins,
as controlled by bits 7-5 of an Interrupt Control Word and a subsequent Mask
Control Word. After writing a 1to bit 4 of an Interrupt Control Word, software
next writes a Mask Control Word to the port’s Control address, containing a 0for
each port that is active for mode 3 interrupt, and a 1for each pin that is ignored.
Pins with a corresponding 1(input) in the I/O Register Control word, and a 0in
the Mask Control Word, are active with respect to mode 3 interrupts.
If bit 5 in a port’s Interrupt Control Word is written as 1, the pins are active High,
while if bit 5 is 0they are active Low.
If bit 6 of the Interrupt Control Word is written as 1, all of the active pins in the
port must be in the active state simultaneously to cause a mode 3 interrupt. If bit 6
is 0, any of the pins that are in an active state can cause an interrupt.
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The PIO, SIO, and CTC modules perform logical OR instructions on their inter-
rupt requests with those from any external peripherals that may be connected to
the INT0 pin. These external peripherals drive INT0 Low in an open-collector or
open-drain fashion. The Z80S188 drives INT0 Low in an open-drain fashion,
when any of the PIOs, SIO, or CTC request an interrupt.
Each PIO port can request an interrupt, and includes state bits called Interrupt
Pending (IP) and Interrupt Under Service (IUS) and its own 8-bit interrupt vector.
The PIOs cannot be used in interrupt mode 0. They can be used in interrupt mode
1, but since the functionality of this mode is so limited, all following descriptions
of PIO interrupt operation assume that software has performed an IM 2 instruction
to place the processor in interrupt mode 2.
+PVGTTWRVꢁ2TKQTKV[ꢁ&CKU[ꢁ%JCKPKPIꢅꢁBecause more than one port, channel, or
interrupt type can request an interrupt at the same time, a mechanism is needed to
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select the order in which their requests are serviced. Z80 peripherals and certain
other ZiLOG devices use a daisy chain to control the relative priority of interrupt
requests among multiple devices and interrupt types within devices.
As described in “Interrupt Acknowledge Daisy Chaining”, on page 18, each PIO
port includes an Interrupt Enable In (IEI) pin, from which it receives permission to
interrupt from higher-priority devices, and an Interrupt Enable Out (IEO) pin, on
which it grants permission to interrupt, to lower-priority devices.
The daisy-chain order and priority within each Z80-device-equivalent module is
fixed. For the PIOs, port A has the highest priority, followed by ports B, C, and D.
The PIOs, SIO, and CTC in the Z80S188 are always consecutive on the daisy
chain, but the relative priority among PIO AB, PIO CD, SIO, and CTC is
programmable in the Interrupt Priority register, with the sole restriction that PIO
AB always has higher priority than PIO CD.
Please see “Interrupt Acknowledge Daisy Chaining”, on page 18 for more infor-
mation about interrupt daisy-chaining.
2+1ꢁ5QHVYCTGꢁ5GSWGPEGU
The following sections present typical software sequences for both polled and
interrupt-driven operation in each of the four operating modes. These procedures
can be applied to any channel with the following restrictions:
BIDIRECTIONAL mode 2 can only be used on channels A and C.
If channel A or C is used in mode 2, then channel B or D respectively can only be
used in BIT CONTROL mode 3.
2QNNGFꢁ1RGTCVKQPꢁKPꢁ1WVRWVꢁ/QFGꢁꢄꢅꢁ
1. Connect the XRDY output to a pin of a port that is in Bit Control Mode 3, or
to some other general purpose input such as DCD0 or CTS0, for which bit 6 or
5 (respectively) of ASCI0’s Extension Control register is 1.
2. Program the register(s) associated with that pin to ensure that it is an input. For
a PIO port, write a CFH to that port’s Control address to select mode 3,
followed by an I/O Register Control Word that includes a 1 for the pin in
question.
3. Write a 03Hto its Control address, if this port may have been used in another
mode since Reset, to ensure that interrupts from the port are disabled.
4. Write a 0HFto this port’s Control address, to select Output Mode 0.
5. Write the first (or next) data byte to be sent via the port to the port’s Data
address when it is available. This action sets the XRDY pin High.
6. Read, periodically, the register containing the bit corresponding to the input
pin that is connected to the XRDY pin, and test the bit. When a Low appears on
the pin, indicating that the destination device has responded with a rising edge
on the XSTB pin, return to step 5.
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1. Disable interrupts (DI), if necessary.
2. Execute as many of the following instructions as have not already been
implemented since Reset:
IM
2
LD A,inttab/256
LD I,A
;inttab=start of interrupt table
LD HL,outisr
LD (inttab+ourvec),HL
;outisr = start of ISR
;ourvec = our vector
0
00.
ꢊ The value of inttabis a multiple of 256; that is, bits 7-0 of its value is
3. Write the even value called ourvecin the previous step, to the port’s Control
address. Bit 0of this value must be 0.
4. Write 0FHto this port’s Control address, to select Output Mode 0.
5. Write 87Hto this port’s Control address, to enable interrupts.
6. Clear an output byte count in memory.
7. Enable interrupts (EI)
8. As each output data byte becomes available:
a. Disable interrupts (DI).
b. Check the output byte count in memory. If it is 0, write the character to the
port’s Data address, otherwise store it where the interrupt service routine
can find it.
c. Increment the output byte count in memory.
d. Enable interrupts (EI).
9. When control comes to outisr:
a. Save as many registers as the ISRmight use (worst case), using PUSH,
EX AF, AF’, or EXXinstructions.
b. Decrement the output byte count. If it is still 1, fetch the next character and
output it to the port’s Data address.
c. Conclude the interrupt service routine by restoring the saved register
values, then executing EIfollowed by RETI. The port decodes the RETI
instruction and re-enables interrupts from itself and from lower-priority
devices.
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1. Connect the XRDY output to a pin of a port that is in Bit Control Mode 3, or to
some other general purpose input such as DCD0 or CTS0, for which bit 6 or 5
(respectively) of ASCI0’s Extension Control Register is 1.
2. Program the register(s) associated with that pin to ensure that it is an input. For
a PIO port, write a CFH to that port’s Control address to select mode 3,
followed by an I/O Register Control Word that includes a 1 for the pin in
question.
3. Write a 03Hto its Control address, to ensure that interrupts from the port are
disabled, if this port may have been used in another mode since Reset.
4. Write a 4FHto this port’s Control address, to select Input Mode 1.
5. Read the port’s Data address, to make the XRDYpin High.
6. Read the register containing the bit corresponding to the input pin that is
connected to the XRDYpin periodically, and test the bit.
7. Read the port’s Data address and process the byte when it shows a Low on the
pin, indicating that the external device has responded with a data byte and a
rising edge on the XSTB pin.
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1. If necessary, disable interrupts (502Z90502)
2. Execute as many of the following instructions that have not been implemented
since Reset:
IM
2
LD A,inttab/256
LD I,A
; inttab = start of interrupt table
LD HL,inisr
LD (inttab+ourvec),HL
; inisr = start of ISR
; ourvec = our vector
0
ꢊ The value of inttabmust be a multiple of 256, that is, bits 7-0 of its
value must be 00.
3. Write the even value called ourvecin the previous step, to the port’s Control
address. Bit 0 of this value must be 0.
4. Write 4FHto this port’s Control address, to select Input Mode 1.
5. Write 87Hto this port’s Control address, to enable interrupts.
6. Read the port’s Data address, to make the XRDY pin High.
7. Re-enable interrupts (EI).
8. Save as many registers as the ISRmight use (worst case), using PUSH, EX
AF,AF’, or EXXinstructions, when control comes to inisr.
9. Read the port’s Data address and process the character.
10. Conclude the interrupt service routine by restoring the saved register values,
then executing EIfollowed by a RETIinstruction. The port decodes the RETI
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1
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instruction and re-enables interrupts from itself and from lower-priority
devices.
2QNNGFꢁ1RGTCVKQPꢁKPꢁ$KFKTGEVKQPCNꢁ/QFGꢁꢆꢅꢁThis mode can only be used on ports
A and C.
1. Connect both the ARDY and BRDY pins, or CRDY and DRDY pins, to pins of a
port that is in Bit Control Mode 3, or to some other general purpose inputs such
as DCD0 and CTS0, with bits 6 and 5 of ASCI0’s Extension Control Register
containing the value 11. (Since port B or D must be in Bit Control Mode 3 in
order to use Bidirectional Mode 2 on port A or C respectively, two port B or D
pins are natural choices.)
2. Program the register(s) associated with these two pins to ensure that they are
inputs. For a PIO port, write a CFHto that port’s Control address to select mode
3, followed by an I/O Register Control Word that includes 1s for the pins in
question.
3. If the port may have been used in another mode since Reset, write 03Hto the
Control addresses of both port A and B (or C and D), to ensure that interrupts
are disabled.
4. Write CFH to the port B (or D) Control address, if necessary, to select Bit
Control Mode 3, followed by an I/O Control Word to the port B (or D) Control
address, containing a 1for each input pin and a 0for each output.
5. Write 8FHto the Port A (or C) Control address, to select Bidirectional Mode 2.
6. Read the Port A (or C) Data address, to make the BRDY (or DRDY) pin High.
7. Clear an Output Started flag in memory.
8. Write the first output byte available to the Port A (or C) Data address, to make
the ARDY (or CRDY) pin High. Also, set the Output Started flag at this time.
9. Read the register(s) containing the bits corresponding to the ARDY and BRDY
(or CRDY and DRDY) lines periodically.
10. Write the Output Started flag to the Port A Data address if it is set and ARDY
is Low, indicating that the external device has acknowledged the last output,
and another output byte is available.
11. Read BRDY from the Port A Data address, and process it if BRDY is Low,
indicating that external logic has provided an input character.
+PVGTTWRVꢀ&TKXGPꢁ1RGTCVKQPꢁKPꢁ$KFKTGEVKQPCNꢁ/QFGꢁꢆꢅꢁThis mode can only be
used on ports A and C.
1. If necessary, disable interrupts (DI).
2. Execute as many of the following instructions that have not been implemented
since Reset:
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IM
2
LD A,inttab/256
LD I,A
; inttab = start of interrupt table
LD HL,outisr
LD (inttab+outvec),HL
LD HL,inisr
; outisr = start of output ISR
; outvec = output vector
; inisr = start of input ISR
; invec = input vector
LD (inttab+invec),HL
0
ꢊ The value of inttabmust be a multiple of 256,that is, bits 7-0 of its
value must be 00.
3. Write the even value called outvecin the previous step, to the port A (or C)
Control address, and the even value called invecto the port B (or D) Control
address. Bit 0 of both values must be 0.
4. Write CFH to the port B (or D) Control address, if necessary, to select Bit
Control Mode 3, followed by an I/O Control Word to the port B (or D) Control
address, containing a 1for each input pin and a 0for each output.
5. Write 8FHto the Port A (or C) Control address, to select Bidirectional Mode 2.
6. Write 97Hto the Port B (or D) Control address, to enable input interrupts and
indicate that a mask word follows, then write FFHto the Port B (or D) Control
address, to disable all port B pins from causing an interrupt.
7. Write 87Hto the Port A (or C) Control address, to enable output interrupts.
8. Read the Port A (or C) Data address, to make the BRDY (or DRDY) pin High.
9. Clear an Output Data Count in memory to 0.
10. Enable interrupts (EI).
11. When each output byte becomes available:
a. Disable interrupts (DI)
b. Check the output data count in memory. If it is 0, write the character to the
Port A (or C) Data address, to make the ARDY (or CRDY) pin High.
Otherwise, store the character in memory where the interrupt service
routine can find it.
c. Increment the output data count.
d. Enable interrupts (EI)
12. If control comes to outisr:
a. Save as many registers that the interrupt service routine may use (worst
case), using PUSH, EX AF,AF’, or EXX instructions.
b. Decrement the output data count in memory. If it is still non-zero, retrieve
the next output character and output it to the Port A (or C) Data address.
c. Restore the saved registers, then execute an EI and RETI. The port
decodes the RETI instruction and re-enables interrupts from itself and
from lower-priority devices.
13. If control comes to inisr:
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a. Save as many registers as the interrupt service routine may use (worst
case), using PUSH, EX AF,AF’, or EXXinstructions.
b. Read the Port A (or C) Data address to obtain the byte from the external
device, and process it.
c. Restore the saved registers, then execute an EI and RETI. The port
decodes the RETI instruction and re-enables interrupts from itself and
from lower-priority devices.
1VJGTꢁ$KFKTGEVKQPCNꢁ1RGTCVKPIꢁ/QFGUꢅꢁSoftware can be written for other Bidi-
rectional possibilities than those described above. For example, output can be
handled in an interrupt-driven fashion while input can be handled by polling, or
operate in the opposite direction. Also, when using input interrupts, port B or D
input pins can be left unmasked to cause interrupts, which use the same vector as
input interrupts.
2QNNGFꢁ1RGTCVKQPꢁKPꢁ$KVꢁ%QPVTQNꢁ/QFGꢁꢌꢅꢁ
1. Write 03Hto this port’s Control address, if this port may have been used in
another mode since Reset, to ensure that interrupts from the port are disabled.
2. Write CFHto the port’s Control address, to select Bit Control Mode 3.
3. Write an I/O Control Word to the port’s Control address, containing a 1for
each input pin and a 0for each output pin.
4. Read the port’s Data address whenever the state of inputs is needed. For output
bits this action returns the data last written to the Data address.
5. Write the new states to the port’s data address whenever the state of outputs
needs to change. Data written to input bits is ignored.
+PVGTTWRVꢀ&TKXGPꢁ1RGTCVKQPꢁKPꢁ$KVꢁ%QPVTQNꢁ/QFGꢁꢌꢅꢁ
1. If necessary, disable interrupts (DI)
2. Execute as many of the following instructions as have not already been
implemented since Reset:
IM
2
LD A,inttab/256
LD I,A
; inttab = start of interrupt table
LD HL,ourisr
LD (inttab+ourvec),HL
; ourisr = start of ISR
; ourvec = our vector
0
ꢊ The value of inttabmust be a multiple of 256, that is, bits 7-0 of its
value must be 00.
3. Write the even value called ourvecin the previous step, to the port’s Control
address. Bit 0 of this value must be 0.
4. Write CFHto the port’s Control address, to select Bit Control Mode 3.
5. Write an I/O Control Word to the port’s Control address, containing a 1for
each input pin and a 0for each output pin. If all pins are outputs, the port does
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not interrupt. See the preceding section,“Polled Operation in Bit Control Mode
3”.
6. Write a value of form 1ah10111to the port’s Control address. This enables
interrupts from the port and indicates that a mask value follows. The h bit is 1
if a High on the selected port pin(s) is the active state, or 0if a Low on the
pin(s) is the active state. The a bit matters only if the following mask word
contains 0s for more than one input pin. In this case a 0in the a bit makes the
port request an interrupt when any of the selected pins are in the selected active
state, and a 1in a makes the port request an interrupt when all of the selected
pins are in the active state. The former is called an OR function and the latter
an AND function.
7. Write a mask value to the port’s Control address. The port ignores bits in this
value corresponding to output pins. For input pins, a 0enables the pin to cause
an interrupt as described above, while a 1prevents the pin from causing an
interrupt. If no input pins are enabled by a corresponding 0, the port does not
interrupt: See the preceding section “Polled Operation in Bit Control Mode 3”.
8. Enable interrupts (EI).
9. Whenever the state of inputs is needed, read the port’s Data address. For output
bits this action returns the data last written to the Data address.
10. Write the new states to the port’s data address whenever the state of outputs
needs to change. Data written to input pins is ignored.
11. Monitor the input pin(s) selected by 0s in step 6 for the condition specified by
the h and a bits. When this logical state goes from false to true, the port
requests an interrupt.
12. When control comes to ourisr:
a. Software saves as many registers as it might use (worst-case), using
PUSH, EX AF,AF’, or EXXinstructions.
b. Software may need to read the port’s Data address, or other registers, to
gather more data about current conditions.
c. The interrupt service routine’s (ISR’s) response to the interrupt is
application-dependent. No action is necessary to clear the interrupt. The a
and hbits, or the mask, may be changed for the next interrupt.
d. The ISR concludes by restoring the saved registers, followed by EIand
RETIinstructions. The port decodes the RETIinstruction and re-enables
interrupts from itself and from lower-priority devices.
2+1UꢁCPFꢁ4GUGV
Reset configures the PIO ports as follows:
1. Each port is placed in Input Mode 1. This disables output drive on all port pins.
2. XRDYoutputs are forced Low.
3. Interrupts are disabled.
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4. Output registers for modes 0, 2, and 3 are cleared to 0s, which correspond to
Lows.
5. Mode 3 mask registers are cleared to 0s to disable interrupts for all pins.
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The Z80S188 includes two DMA channels called DMA0 and DMA1. Both chan-
nels can transfer data between memory and a peripheral in I/O space. In addition,
DMA0 can perform memory to memory block transfers, and transfers between
memory and memory-mapped I/O devices.
Both DMA channels are of the flowthrough type, in which each byte transferred
requires two bus cycles, one to read the source and the second to write the desti-
nation. Because of this technique, neither memory nor peripherals differentiate
the bus cycles performed by the DMA channels, because they are identical to bus
cycles from the processor.
DMA transfer can occur as fast as 6 clocks/byte. At 33 MHz, the speed is up to 5.5
MB/second. Destination/output devices typically require edge-sensitive request
mode, in which case the maximum rate is 9 clocks/byte, or 3.67 MB/second at 33
MHz.“DMA Registers”, on page 132, describes the registers associated with the
DMA channels.
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DMA0 has two 23-bit address registers and a 16-bit byte count, while DMA1 has
one 23-bit memory address registers and a 16-bit I/O address register and byte
count. For DMA0 the address registers are called the Source and Destination
Address Registers (SAR and DAR). DMA1’s registers and called the Memory and
I/O Address Registers (MAR and IAR).
Each address register is divided into three Z80S188 I/O registers, called L(LOW),
H(High), and B. When the DMA channel is operating, A7-0is driven from the L
register and A15-8from the H register. For memory addresses (always for MAR)
the channel drives A22-16 from the LS 7 bits of the B register. For I/O addresses
(always for IAR) the channel uses the LS three bits of the B register to select the
source of the DMA Request signal that controls data transfer.
Each byte count register is divided into two Z80S188 I/O registers, called L(Low)
and H(High).
After programming a channel’s address and byte count registers, software starts
the channel by setting its Enable bit in the DSTAT register (DE0 or DE1). As a
DMA channel transfers each byte, the byte counter register decrements. When a
channel has decremented the byte count to 0, it becomes inactive by clearing the
Enable bit.
Software can select whether a channel increments or decrements a memory
address as it transfers each byte. DMA0 also has an option to keep a memory
address fixed. To select this fixed address option for the source or destination,
DMA0 must be a memory-mapped I/O device that provides a DMA Request
signal on the DREQ0pin.
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An external peripheral, that needs a DMA channel to transfer data for it, must
provide a DMA request signal to the DREQ0pin for DMA0, and/or to the DREQ1
pin for DMA1. A DMA request can be connected directly to one of these pins if
only one external peripheral is serviced by that DMA channel, or via external
selection logic if more than one external device is to use the DMA channel.
Bits corresponding to address bits 18-16 of the register containing the I/O address
of a peripheral, select between the external DREQpin and internal peripherals as
the source of each DMA channel’s request. For a memory-mapped peripheral, that
is, a source or destination of a DMA0 memory-to-memory operation that’s
programmed to use a fixed address, the DREQ0pin is always used as the
REQUEST signal.
The DMA request signal indicates when an input or source peripheral has a byte
to be transferred to memory, or when an output or destination peripheral needs a
byte from memory.
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DMA requests can be programmed to be Low-level sensitive or falling-edge
sensitive. For an output/destination peripheral, the timing requirements on the
DMA Request signal dictate falling-edge mode. An input/source peripheral can
use either an edge- or level-sensitive DMA Request.
Figure 16 illustrates the timing of a level-sensitive DMA Request. DMA opera-
tion is triggered when the Z80S188 samples the DMA request line Low. In the
figure below, the Z80S188 samples the Request line again, at the rising PHI edge
that begins the second-last clock cycle of the machine cycle that writes the byte to
the destination. If the Request line is Low at that time, as it is in the rightmost
down-arrow below, DMA operation continues for another byte. If the Request is
sampled High, as at the leftmost down-arrow below, the current DMA channel
relinquishes use of the bus (to the processor, the other DMA channel, or an
external master) after completing the write cycle.
CPU Machine Cycle DMA Read Cycle
T1 T2 T3 T1 T2 T3 T1
DMA Write Cycle (I/O)
DMA Write Cycle
DMA Read Cycle
T1
T2
T2
TW
TW
T3
TW
T3
TW
..
..
.*.*
**
**
Request
*.*. Request is sampled at
(
ꢄꢐꢅ 2
ꢋ&/#ꢁ1
ꢁ
ꢁ.
ꢀ5
ꢁ4
ꢆꢇ
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25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
&/#ꢀ%
1
&
Figure 17 illustrates the timing of an edge-sensitive request. At the first down-
arrow, the DMA channel writes a byte to the destination. A new falling edge has
not occurred by the second-last rising PHI edge of the cycle, so the bus is relin-
quished to the processor. At the same sampling point in the processor cycle, a new
falling edge has occurred on the Request line. The DMA reads and then writes a
byte. At the same point in its write cycle, a new falling edge has not occurred, and
bus control is returned to the processor, and the DMA channel does not operate
again until the Request line has gone High and then Low again, some time past the
right edge of the figure below.
CPU Machine
Cycle
CPU Machine
Cycle
DMA Read
Cycle
DMA Write
Cycle
DMA Write Cycle
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
2
3
W
3
1
2
3
1
2
3
1
2
W
3
1
φ
..
.*.*
.*.*
..
**
**
Request
..
**Request is sampled at
(
ꢄꢑꢅ 2
ꢋ&/#ꢁ1
ꢁ
ꢁ' ꢀ5 ꢁ4
/GOQT[ꢀVQꢀ/GOQT[ꢁ/QFGU
In a DMA0 memory-to-memory operation, in which both the source and destina-
tion are programmed for address incrementing or decrementing, there is no
peripheral to supply a request signal to control the transfer. In this case, software
can select between two modes of operation by programming MMOD, bit 1 of the
DMA Mode register.
If MMOD is 0, the processor and DMA channel alternate bus cycles until the
DMA has completed the block transfer and decremented its byte count to 0. This
mode is called CYCLE STEAL mode.
If MMOD is 1, the DMA channel does continuous cycles until it completes the
block transfer, and the processor can do nothing during this time. This mode is
called BURST mode.
&/#ꢁ+PVGTTWRVU
Software can enable interrupts from each DMA channel, which then requests an
interrupt when it has decremented its byte count to 0. When the processor
acknowledges such an interrupt, the interrupt service routine address is fetched
from memory at (I : IL : 8) for DMA0 or (I : IL : 10) for DMA1.
If the interrupt service routine does not have another block of data for the DMA
channel to transfer, it prevents further interrupts by clearing the interrupt enable
bit (DSTAT bit 2 for DMA0, bit 3 for DMA1) before it re-enables interrupts with an
EI instruction. If the ISR programs the DMA channel for another transfer, inter-
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
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ꢆꢁ
1
&
&/#ꢀ%
rupts can be re-enabled with an EI instruction, after the DMA is restarted by
writing DCNTL.
5GVVKPIꢁ7RꢁCꢁ&/#ꢁ6TCPUHGT
9TKVGꢁVJGꢁ#FFTGUUꢁ4GIKUVGTUꢅꢁFor DMA0, this transfer includes SAR0L, SAR0H,
SAR0B, DAR0L, DAR0H, and DAR0B. If the source is in I/O space, write SAR0B
with a code to select the source of the DMA Request for DMA0, as described in
Table 11:
6
ꢁꢄꢄꢅ 5#4ꢃ$ꢁ
ꢁ
ꢁ ꢁ5
ꢁ ꢁ+ꢋ1ꢁ5
5#4ꢃ$ꢁ$KVUꢁꢆꢀꢃ
&/#ꢁ4GSWGUVꢁ5QWTEG
ꢃꢃꢃ
ꢃꢃꢂ
ꢃꢂꢃ
ꢃꢂꢂ
ꢂꢃꢃ
ꢂꢃꢂ
ꢂꢂꢃ
ꢂꢂꢂ
&4'3ꢃꢀRKP
#5%+ꢃꢀ4&4(
#5%+ꢂꢀ4&4(
4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
5+1ꢀ#ꢀ4Z
5+1ꢀ$ꢀ4Z
2+1ꢀ#ꢀ+P
2+1ꢀ$ꢀ+P
If the DMA destination is in I/O space, write DAR0B with a code to select the
source of the DMA Request for DMA0, as described in Table 12:
6
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ꢁ ꢁ+ꢋ1ꢁ5
ꢃ$ꢁ$KVUꢁꢆꢀꢃ
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ꢃꢃꢃ
ꢃꢃꢂ
ꢃꢂꢃ
ꢃꢂꢂ
ꢂꢃꢃ
ꢂꢃꢂ
ꢂꢂꢃ
ꢂꢂꢂ
&4'3ꢃꢀRKP
#5%+ꢃꢀ6&4'
#5%+ꢂꢀ6&4'
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5+1ꢀ#ꢀ6Z
5+1ꢀ$ꢀ6Z
2+1ꢀ#ꢀ1WV
2+1ꢀ$ꢀ1WV
For DMA1, software must write MAR1L, MAR1H, MAR1B, IAR1L, IAR1H, and
IAR1B. Write IAR1B with a code to select (with the DIM1 bit in the DCNTL
register) the source of the DMA Request for DMA1, as described in Table 13:
ꢏꢃ
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1
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6
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ꢃꢃꢃ
ꢃꢃꢂ
:
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4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
5+1ꢀ#ꢀ6Z
ꢃꢀꢐOGO→+ꢋ1ꢑ
ꢂꢀꢐ+ꢋ1→OGOꢑ
ꢃꢀꢐOGO→+ꢋ1ꢑ
ꢂꢀꢐ+ꢋ1→OGOꢑ
:
ꢃꢂꢃ
ꢃꢂꢂ
ꢂꢃꢃ
ꢃꢀꢐOGO→+ꢋ1ꢑ
ꢂꢀꢐ+ꢋ1→OGOꢑ
ꢃꢀꢐOGO→+ꢋ1ꢑ
ꢂꢀꢐ+ꢋ1→OGOꢑ
ꢃꢀꢐOGO→+ꢋ1ꢑ
ꢂꢀꢐ+ꢋ1→OGOꢑ
ꢃꢀꢐOGO→+ꢋ1ꢑ
ꢂꢀꢐ+ꢋ1→OGOꢑ
5+1ꢀ#ꢀ4Z
ꢂꢃꢂ
ꢂꢂꢃ
ꢂꢂꢂ
5+1ꢀ$ꢀ6Z
5+1ꢀ$ꢀ4Z
2+1ꢀ#ꢀ1WV
2+1ꢀ#ꢀ+P
2+1ꢀ$ꢀ1WV
2+1ꢀ$ꢀ+P
9TKVGꢁVJGꢁ$[VGꢁ%QWPVꢁ4GIKUVGTUꢅꢁWrite the less-significant byte to BCR0L or
BCR1L, and the MS byte to BCR0H or BCR1H. An all-0 value makes the DMA
transfer 65,536 bytes.
(QTꢁ&/#ꢃꢍꢁYTKVGꢁVJGꢁ&/1&'ꢁ4GIKUVGTꢅꢁBits 3-2 select the operating mode for
the source, as described in Table 14. Bits 5-4 select the operating mode for the
destination, as described in Table 15. For memory-to-memory block transfers, bit
1 (MMOD) selects between Cycle Steal and Burst mode, as described in
“Memory-to-Memory Modes”, on page 59.
6
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ꢃꢃ
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(KZGFꢀ+ꢋ1ꢀ#FFTGUU
6
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&GETGOGPVꢀ/GOQT[ꢀ#FFTGUU
(KZGFꢀ/GOQT[ꢀ#FFTGUUꢀꢐTGSWGUVꢀQPꢀ&4'3ꢃꢀRKPꢑ
(KZGFꢀ+ꢋ1ꢀ#FFTGUU
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ꢏꢂ
1
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9TKVGꢁVJGꢁ&%06.ꢁ4GIKUVGTꢅꢁTypically, software reads this register, modifies the
bits for the current DMA channel, and writes back the result. Bits 7-4 select the
number of waits to insert for Memory and I/O accesses, as described in “Central
Wait State Generator”, on page 36. For DMA0, bit 2 selects edge- vs. level-sensi-
tivity on the DMA Request, as described in an earlier section. For DMA1, bit 3
selects between edge- and level-sensitivity, and bits 1-0 select the operating mode,
as described in Table 16:
6
ꢁꢄꢐꢅ &/#ꢄꢁ1
ꢁ/
&%06.ꢁꢄꢀꢃ /QFG
ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
+PETGOGPVꢀ/GOQT[ꢀ#FFTGUUꢀ→ꢀ(KZGFꢀ+ꢋ1ꢀ#FFTGUU
&GETGOGPVꢀ/GOQT[ꢀ#FFTGUUꢀ→ꢀ(KZGFꢀ+ꢋ1ꢀ#FFTGUU
(KZGFꢀ+ꢋ1ꢀ#FFTGUUꢀ→ꢀ+PETGOGPVꢀ/GOQT[ꢀ#FFTGUU
(KZGFꢀ+ꢋ1ꢀ#FFTGUUꢀ→ꢀ&GETGOGPVꢀ/GOQT[ꢀ#FFTGUU
9TKVGꢁVJGꢁ&56#6ꢁ4GIKUVGTꢁVQꢁ'PCDNGꢁVJGꢁ&/#ꢁ%JCPPGNꢅꢁSoftware reads this
register, modifies the bits noted below, and writes back the result. For DMA0,
write 110to bits 6-4, keep bit 3 unchanged, and write a 1to bit 2 if DMA0 inter-
rupts when it has decremented the byte count to 0, or a 0to bit 2 if DMA0 does
not interrupt.
For DMA1, write a 1to bit 7, 01to bits 5-4, write a 1to bit 3 if the user requires
DMA1 to interrupt when it has decremented the byte count to 0, or a 0to bit 3 if
not, and keep bit 2 unchanged.
0/+ꢁCPFꢁ&/'
When software writes to DSTATto start either DMA channel as described above,
this action also sets the DMA Master Enable (DME) bit that can be read as bit 0 in
DSTAT. A 1in this bit enables operation by either or both DMA channels.
To guarantee that a Non-Maskable Interrupt (NMI) is handled promptly, the
Z80S188 clears DME to suspend DMA operation, when NMILow is detected.
As soon as possible, the NMIservice routine reads DSTAT. For each DMA
channel, if the DEbit (DSTAT7 or 6) is 1, and the associated device (if any) has
not overrun or underrun, the service routine clears that channel’s DWE bit
(DSTAT5 or 4) to 0. If either DWE bit is 0, the result is written back to DSTAT.
This action sets DME again and re-enables DMA operation.
&/#ꢁ%JCPPGNꢁ%QORNGVKQP
While a DMA channel is operating, software can stop it by reading the DSTAT
register, clearing bits 6 and 4 for DMA0, or 7 and 5 for DMA1, and writing the
result back to DSTAT.
Otherwise, if software enabled the channel to interrupt, when the channel decre-
ments the byte count to 0, an interrupt is requested.
ꢏꢎ
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9
ꢌ& ꢀ6
1
&
If software does not enable the DMA channel to interrupt, it polls the Enable bit in
DSTAT (bit 6 for DMA0, bit 7 for DMA1) to determine when the DMA channel
finishes transferring the current block of data. In some applications, software can
use status or an interrupt from the associated peripheral device, to determine
completion of the block transfer.
*CPFNKPIꢁ&/#ꢁ+PVGTTWRVU
When the conditions noted in “On-Chip Interrupt Handling”, on page 29 are met
with respect to a DMA interrupt request, the processor fetches the interrupt
service routine address from memory at (I:IL:8) for DMA0 or
(I:IL:10) for DMA1. The service routine, as a minimum:
1. Reads the DSTAT register to determine that the DE bit for the DMA channel
corresponding to the service routine entry point, has gone from 1to 0. If a
common routine is used for both DMAs, the service routine determines which
DE bit has been cleared, or both.
2. Reprograms the channel’s registers if there is more for a completed DMA
channel to process, and restart it, as described above.
3. Clears the DIE bit for the channel, in the DSTAT register, to prevent another
interrupt for the same DMA completion, if there is no more data to process.
4. The ISR ends with an EI and a RET instruction, to return to the interrupted
process.
9#6%*ꢀ&1)ꢁ6+/'4
The Watchdog Timer (WDT) can be used to protect against unreliable software,
power line faults that put the processor into unusual states, and other processes
harmful to the device.
When the WDT is enabled, software must reload it periodically to prevent it from
driving the WDTOUT output Low. WDTOUT can be connected to RESET, to
NMI, or to external logic. The time period, within which software must reload the
16 18 20
WDT to prevent a Low on WDTOUT, is programmable among 2 , 2 , 2 , or
22
2
system clocks.
The registers in the WDT are described in “Watch-Dog Timer Registers”, on page
143. Several provisions of the WDT are intended to enhance its integrity against
runaway execution. The WDT can be reloaded by writing the specific value 4EH
to the WDT Command register. This register can only be disabled by writing a 0
to bit 7 of the WDT Master register, then writing the value B1Hto the WDT
Command register.
%1706'4ꢋ6+/'4ꢁ%*#00'.5ꢁꢈ%6%5ꢉ
The Z80S188 includes the equivalent of one Z80 CTC device: four Counter/Timer
Channels numbered 0 through 3. Each channel includes a readable 8-bit down
counter, a prescaler that can divide the channel’s input clock by 16 or 256, a
Clock/Trigger input (CLK/TRG0-3), and a Zero Count/Timeout output (ZC/TO0-3).
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
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ꢏꢊ
1
&
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ꢋ6
ꢀ%
ꢀꢐ%6% ꢑ
Each channel can operate in a Counter mode, in which the CLK/TRG pin provides
its down-count clock, or in TIMER mode, in which the down-count clock is the
Z80S188’s master PHI clock divided by 16 or 256, and in which the CLK/TRG pin
can optionally provide a trigger to start down-counting.
In both modes, when down-counting reaches 0, the channel produces a pulse on
its ZC/TO output, and reloads the down counter from its Time Constant register.
%6%ꢁ#FFTGUUGUꢁCPFꢁ4GIKUVGTU
Each CTC channel has one 8-bit address in I/O space. Like the other Z80 periph-
erals in the Z80S188, CTC I/O decoding can include A15-8all 0as for 80180
register decoding, or can ignore A15-8, depending on the AllPageIO bit in the
Interrupt Priority register. The latter choice allows use of Z80 I/O instructions for
legacy-code compatibility.
6
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ꢃ
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“Counter/Timer (CTC) Registers”, on page 144, describes the use of the CTC
addresses.
Reading a CTC channel’s address always yields the contents of its down counter.
Except when a channel is expecting a Time Constant as described below, writing
an even value (having a 0in bit 0) to channel 0’s address sets bits 7-3 of the inter-
rupt vector value for all four channels, while writing an odd value (having a 1in
bit 0) to any channel loads its Channel Control register. If bit 2 written to a
Channel Control register is 1, the next write to that channel’s address loads the
channel’s Time Constant register.
%JCPPGNꢁ%QPVTQNꢁ4GIKUVGTꢅꢁBit 7 of this register must be 1to enable an interrupt
from the channel when its down counter reaches 0, or 0if an interrupt is not
required.
A 1in bit 6 selects Counter mode, in which the down-counter is decremented by
the selected edge on the CLK/TRG input, while a 0in bit 6 selects Timer mode, in
which the down-counter is decremented by the PHI clock divided by 16 or 256,
and in which the selected edge on CLK/TRG can optionally enable the channel to
start down-counting.
In Timer mode only, a 1in bit 5 conditions the prescaler to divide PHI by 256,
while a 0in bit 5 divides PHI by 16. In Counter mode, bit 5 has no significance.
In Counter mode, a 1in bit 4 selects rising edges on CLK/TRG to decrement the
down-counter, while a 0selects falling edges. In Timer mode with a 1in bit 3, a 1
ꢏꢉ
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1
&
in bit 4 selects a rising edge on CLK/TRG to start down-counting, while a 0selects
a falling edge on CLK/TRG. In Timer mode with a 0in bit 3, bit 4 has no
significance.
In Timer mode, a 1in bit 3 conditions the channel to wait for the edge selected by
bit 4, following the rising edge of machine cycle T2 after the one loading the Time
Constant. A 0in bit 3 starts the prescaler counting at the rising edge of T2. In
Counter mode, bit 3 is insignificant.
A 1written to bit 2 conditions a channel to load the next byte written to the
channel’s address into the Time Constant register. Writing a 0to bit 2 keeps the
channel decoding bit 0 to select between the Channel Control register and the
Interrupt Vector register. If a channel is already operating, and software writes 10
to bits 2-1, the subsequently-written Time Constant cannot take effect until the
next time the channel counts down to 0.
A 1written to bit 1 stops the channel, if it was running, and resets it. If software
writes 11to bits 2-1, the channel is re-enabled for operation when software writes
the new Time Constant. Writing 0to bit 1 of a running channel, allows the
channel to continue running.
Bit 0 must be 1to identify a byte for the Channel Control register. Writing a byte
to channel 0, with a 0in bit 0, writes bits 7-3 of the value into the Interrupt Vector
register that applies to all four channels.
6KOGꢁ%QPUVCPVꢁ4GIKUVGTꢅꢁAfter software writes a 1to bit 2 of a Channel Control
register, the next byte written to that channel’s address is loaded into the channel’s
Time Constant register. If the channel is not already running, the value is also
loaded into the down-counter, and the channel is enabled to count down from that
value. (In Timer mode with a 1in bit 3 of the CCR, actual down-counting is
delayed until the channel senses the selected edge on CLK/TRG.)
A 0time constant forces a channel count down from 256.
+PVGTTWRVꢁ8GEVQTꢁ4GIKUVGTꢅꢁIf software writes a value with a 0in bit 0 to channel
0’s address, bits 7-3 of the value are captured in this register. Subsequently, when
any CTC channel interrupts the processor (assuming the processor is in INT0
interrupt mode 2), the CTC returns these bits as bits 7-3 of the Interrupt Vector,
with the number of the interrupting channel as bits 2-1 and a 0in bit 0.
4GCFKPIꢁVJGꢁ&QYPꢁ%QWPVGTꢅꢁReading any channel’s address yields the current
contents of its down-counter. The software can remembers the status of each
channel.
%6%ꢁ+PVGTTWRVU
The CTC, PIO, and SIO modules perform logical OR instructions on interrupt
requests using those from any external peripherals that may be connected to the
INT0 pin. These external peripherals drive INT0 Low in an open-collector or open-
drain fashion. The Z80S188 drives INT0 Low in an open-drain fashion when any
of the CTC or SIO channels or PIO ports are requesting an interrupt.
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
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ꢀꢐ%6% ꢑ
Each CTC channel can request an interrupt, and includes state bits called Interrupt
Pending (IP) and Interrupt Under Service (IUS). The 4 CTC channels share a 5-bit
base interrupt vector. A CTC channel that is the highest priority requesting device
during an interrupt acknowledge cycle returns the channel number in bit 2-1 of the
interrupt vector.
+PVGTTWRVꢁ2TKQTKV[ꢁ&CKU[ꢁ%JCKPKPIꢅꢁSince more than one port, channel, or inter-
rupt type can request an interrupt at the same time, a mechanism is needed to
select the order in which their requests are serviced. Z80 peripherals and certain
other ZiLOG devices use a daisy chain to control the relative priority of interrupt
requests among multiple devices and interrupt types within devices.
As described in “Interrupt Acknowledge Daisy Chaining”, on page 18, each CTC
channel includes an Interrupt Enable In (IEI) pin, from which permission is
received to interrupt from higher-priority devices, and an Interrupt Enable Out
(IEO) pin, on which permission is received to interrupt to lower-priority devices.
The daisy-chain order and priority within each Z80-device-equivalent module is
fixed. For the CTC, channel 0 has the highest priority and channel 3 the lowest.
The CTC, PIOs, and SIO in the Z80S188 are always consecutive on the daisy
chain, but the relative priority among them is programmable in the Interrupt
Priority register.
See “Interrupt Acknowledge Daisy Chaining”, on page 18 for more information
about interrupt daisy-chaining.
%6%ꢁ5QHVYCTGꢁ5GSWGPEGU
The following sections describe polled and interrupt-driven operations in both
Counter and Timer modes. These operations apply equally to any of the four chan-
nels.
2QNNGFꢁ1RGTCVKQPꢁKPꢁ%QWPVGTꢁ/QFGꢅꢁ
1. Write a 47Hto the channel’s address if falling edges on the channel’s CLK/
TRGn pin decrement the counter, or 57Hif rising edges decrement the counter.
2. Write the value from which the counter counts down, to the channel’s address.
A 0 value forces the channel count down from 256. This value is loaded into
the counter and the channel’s TIME CONSTANT register. Unless software
reloads a new TIME CONSTANT value in step 5, this is also the value from
which the counter restarts, after it has counted down to 0.
3. Enable the channel to count down by 1 whenever the selected edge occurs on
its CLK/TRGn pin. Software can read the channel’s address at any time, to
determine the counter value.
4. When a channel’s counter contains 01, and the selected edge occurs on its
CLK/TRGn pin, instead of going to 00, the counter is reloaded with the value
currently in the channel’s Time Constant register. This event is accompanied
by a High pulse on the channel’s ZC/TON pin. Unless software is monitoring
the counter very closely, so that it is guaranteed to read every value of the
counter, the most reliable method for software to detect this event is to
ꢏꢏ
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1
&
compare successive values that have read from the channel’s address. When a
value is larger than its predecessor, the counter has counted down to 0 and
reloaded. (Software cannot detect reloads if the Time Constant value is 01.)
5. To load a new value into the Time Constant register while the channel is
running, software first writes a 45H or 55H to the channel’s address
(depending on the same edge selection as in step 1), and then writes the new
Time Constant value to the channel’s address.
+PVGTTWRVꢀ&TKXGPꢁ1RGTCVKQPꢁKPꢁ%QWPVGTꢁ/QFGꢅꢁ
1. Disable interrupts (DI), if necessary.
2. Execute as many of the following instructions that have not been implemented
since Reset:
IM
2
LD A,inttab/256
LD I,A
; inttab = start of interrupt table
LD HL,ctcNisr
LD (inttab+ctcNvec),HL
; ctcNisr = start of ISR
; ctcNvec = our vector
0
ꢊ The value of inttabmust be a multiple of 256, that is, bits 7-0 of its
value must be 00.
3. Bit 0 of the value called ctcNvecin the previous step must be 0, and
bits 2-1 must be equal to this channel’s number. Unless this step has been done
previously, write this value to channel 0’s address (D0H).
4. Write a C7Hto this channel’s address if falling edges on the channel’s CLK/
TRGn pin decrements the counter, or D7H if rising edges decrement the
counter.
5. Write the value from which the counter counts down, to the channel’s address.
A 0value makes the channel count down from 256. This value is loaded into
the counter and the channel’s Time Constant register. Unless software reloads
a new Time Constant value in step 6, this is also the value from which the
counter restarts, after it has counted down to 0.
6. The channel is enabled to count down from the value written in the previous
step, whenever the selected edge occurs on its CLK/TRGn pin. If the counter
restarts from a different value when it reaches 0, software immediately writes
a C5Hor D5Hto the channel’s address (depending on the same edge selection
as in step 4), and then writes the new Time Constant value to the channel’s
address.
7. Software reads the counter’s value from the channel’s address at any time.
8. When a channel’s counter contains 01, and the selected edge occurs on its
CLK/TRGn pin, instead of containing the value 00, the counter reloads with
the value currently in the channel’s Time Constant register. This event is
accompanied by a High pulse on the channel’s ZC/TOn pin, and the channel
requests an interrupt.
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9. When the processor acknowledges the interrupt, the CTC automatically
supplies the channel’s number in bits 2-1 of the interrupt vector, so that control
comes to ctcNisr. At that time:
a. Software saves as many registers as it may use (worst-case), using PUSH,
EX AF,AF’, or EXXinstructions.
b. If the counter must be reloaded with a different value the next time it
reaches 0, the interrupt service routine (ISR) writes a C5Hor D5Hto the
channel’s address (depending on the same edge selection as in step 4), and
then writes the new Time Constant value to the channel’s address.
c. Other actions by the ISR are application-dependent.
d. The ISRconcludes by restoring the saved registers, followed by EIand
RETI instructions. The channel decodes the RETI instruction and re-
enables interrupts from itself and from lower-priority devices.
2QNNGFꢁ1RGTCVKQPꢁKPꢁ6KOGTꢁ/QFGꢅꢁ
1. Write a value of form 00pet111Bto the channel’s address. A 0in the pbit
conditions the channel to decrement its counter once every 16 PHI clocks,
while a 1in bit p (20H) conditions the channel to decrement the counter once
every 256 PHI clocks. A 0in the t bit conditions the timer to start as soon as
the following time constant is written, while a 1in bit t forces the timer to wait
for the time constant, then the edge selected by the e bit, on its CLK/TRGn pin.
If t is 1and eis 0(08H), the channel waits for a falling edge on CLK/TRGn
before starting the timer. If tand eare both 1(18H), the channel waits for a
rising edge on CLK/TRGn before starting the timer.
2. Write the value from which the timer counts down, to the channel’s address.
This value is loaded into the counter and the channel’s Time Constant register.
Unless software reloads a new Time Constant value, this is also the value from
which the timer restarts, after it has counted down to 0.
3. Software can read the channel’s address at any time, to determine the counter
value.
4. When a channel’s counter is decremented to 00, it is reloaded with the value
currently in the channel’s Time Constant register. This event is accompanied
by a High pulse on the channel’s ZC/TOn pin. Unless software is monitoring
the counter very closely, so that every value of the counter is read, the most
reliable way for software to detect this event is to compare successive values
that were read from the channel’s address. When a value is larger than its
predecessor, the counter has counted down to 0 and then reloaded. (Software
cannot detect reloads if the Time Constant value is 01.)
5. To load a new value into the Time Constant register while the channel is
running, software waits for any programmed CLK/TRG wait to finish, as
evidenced by the counter value being decremented from its initial value. The
software writes 00pet101Bto the channel’s address, and then writes the new
Time Constant value to the channel’s address.
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1. Disable interrupts (DI), if necessary.
2. Execute as many of the following instructions that have not been imlemented
since Reset:
IM
2
LD A,inttab/256
LD I,A
; inttab = start of interrupt table
LD HL,ctcNisr
LD (inttab+ctcNvec),HL
; ctcNisr = start of ISR
; ctcNvec = our vector
0
ꢊ The value of inttabmust be a multiple of 256, that is, bits 7-0 of its
value must be 00.
3. Write the value of bit 0 to channel 0’s address (D0H) unless this step has been
implemented previously. Bit 0 of the value called ctcNvec in the previous step
must be 0, and bits 2-1 must be equal to this channel’s number.
4. Write a value of form 10pet111Bto the channel’s address. A 0in the p bit
conditions the channel to decrement its counter once every 16 PHI clocks,
while a 1in p(20H) conditions the channel to decrement the counter once
every 256 PHI clocks. A 0in the t bit conditions the timer to start as soon as
the following time constant is written. A 1in tmakes the timer wait for the
time constant, followed by the edge selected by the e bit, on its CLK/TRGn pin.
If tis 1and eis 0(08H), the channel waits for a falling edge on CLK/TRGn
before starting the timer. If tand eare both 1(18H), the channel waits for a
rising edge on CLK/TRGn before starting the timer.
5. Write the value from which the timer counts down, to the channel’s address.
This value is loaded into the counter and the channel’s Time Constant register.
Unless software reloads a new Time Constant value, this value is also the value
from which the timer restarts, after it has counted down to 0.
6. If the counter restarts from a different value when it reaches 0, software waits
for any programmed CLK/TRG wait to finish, as evidenced by the counter
value being decremented from its initial value. Software writes 10pe0101B
to the channel’s address, and then writes the new Time Constant value to the
channel’s address.
7. Software can read the channel’s address at any time, to determine the counter
value.
8. When a channel’s counter is decremented to 00, the counter is reloaded with
the value currently in the channel’s Time Constant register. This event is
accompanied by a High pulse on the channel’s ZC/TOn pin, and the channel
requests an interrupt.
9. When the processor acknowledges the interrupt, the CTC automatically
supplies the channel’s number in bits 2-1 of the interrupt vector, so that control
comes to ctcNisr. At that time:
a. Software saves as many registers as it might use (worst-case), using
PUSH, EX AF,AF’, or EXXinstructions.
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b. If the timer restarts from a different value the next time it reaches 0, the
interrupt service routine (ISR) writes 10pe0101B to the channel’s
address, and then writes the new Time Constant value to the channel’s
address.
c. Other actions by the ISR are application-dependent.
d. The ISRconcludes by restoring the saved registers, followed by EIand
RETI instructions. The channel decodes the RETI instruction and re-
enables interrupts from itself and from lower-priority devices.
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Each PRT is a 16-bit down-counter that can be read dynamically, with a reload
value that can be dynamically programmed. Each PRT can optionally interrupt the
processor when it counts down to 0and reloads.
The PRTs on most other 8018x family members count down at the fixed
frequency of PHI/20, but the Z80S188 includes a flexible prescaler that can count
down each PRT at any power-of-two divisor between PHI and PHI/16384. The
prescalers reset to an 80180-compatible countdown rate of PHI/20.
Software can program PRT1 to do waveform generation on its TOUT output,
under control of the TOC 1-0 bits in the Timer Control Register. This capability is
enhanced by the flexible prescaler.
“Programmable Reload Timer (PRT) Registers”, on page 147, shows the PRT
registers. Reset clears both Timer Downcount Enable bits (TDE1, TDE0) in the
Timer Control register to 0, which inhibits the PRTs from operating.
5VCTVKPIꢁCꢁ246
Before starting a PRT, software writes the Timer Prescale register to select the
downcounter frequency, which can be PHI/20 as on the 80180, or any power-of-
two divisor between PHI and PHI/16384.
Next, software programs the PRT’s initial down-count value to its Timer Data
registers (TMDR0L and TMDR0H, or TMDR1L and TMDR1H), and write its
second (and possibly constant) down-count value to its Timer ReloaD registers
(RLDR0L and RLDR0H, or RLDR1L and RLDR1H).
Then software reads the Timer Control register (TCR), set the appropriate Timer
Downcount Enable bit (TDE0or TDE1), set or clear the corresponding Timer
Interrupt Enable bit (TIE0or TIE1) depending on whether an interrupt is desired
when the count is decremented to 0, and write the result value back to the TCR.
The read-modify-write procedure, described above, ensures that starting one PRT
does not affect the operation of the other. Applications that only use one PRT can
write only the desired value to the TCR.
5VQRRKPIꢁCꢁ246
Software can stop a running PRT at any time, by reading the TCR, clearing its
TDE bit, and writing the result value back to the TDR. The software may do this
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1
&
because the PRT’s counting is no longer necessary, or before rewriting its RLDR
value as described below.
246ꢁ1RGTCVKQP
While a PRT is running, the down-counter is decremented at the frequency
selected in the Timer Prescale Register, which resets to PHI/20. When the count
down reaches 0, the PRT automatically reloads its TMDR from its RLDR, and
sets its TIF bit in the TCR. If the TIE bit in the TCR is 1, an interrupt is requested.
Software can clear a TIF bit after reading it as 1in the TCR, by thereafter reading
either half of that PRT’s TMDR. However, a TMDR read, without first reading a
TIF bit as 1in the TCR, does not clear the PRT’s TIF.
Software can read the down-counter, from TMDR0L and TMDR0H or TMDR1L
and TMDR1H, at any time without worrying about the timer counting between
the two 8-bit IN0instructions, as long as it reads the L register first. Reading the L
register captures the 8 MS bits of the down-counter in a separate 8-bit latch, from
which the value is read when software reads the H register.
9TKVKPIꢁCPꢁ4.&4ꢅꢁSoftware can write a new reload value, to RLDR0L and
RLDR0H or RLDR1L and RLDR1H, while the PRT is running, but there is no
hardware safeguard against the down-counter decrementing to 0 between the two
8-bit OUT0instructions necessary to write the new reload value, and consequently
loading an incorrect value.
If software writes a new reload value in response to a PRT interrupt or to detecting
a TIF bit 1in the TCR, and count values are always large enough to prevent this
type of problem, software can automatically write the RLDR. Otherwise, software
performs the following tasks:
1. Reads the Timer Control Register (TCR)
2. Clears the TDE bit,
3. Writes the result back to the TCR,
4. Writes the RLDR (L and H, in either order)
5. Writes the value from step 1 (with the TDE bit 1) back to the TCR.
*CPFNKPIꢁ246ꢁKPVGTTWRVU
When the conditions noted in “On-Chip Interrupt Handling”, on page 29 are met
with respect to an interrupt request from a PRT, the processor reads the address of
the interrupt service routine from memory at address (I:IL:4) for PRT0, or
(I:IL:6) for PRT1. The PRT ISR performs the following actions:
1. Saves as many registers of the interrupted process as it may use, by means of
PUSH, EX AF,AF’, and/or EXXinstructions.
2. Reads the TCR, verify that its TIF bit is 1, and then reads the PRT’s TMDRL
register to clear its TIF bit. This process prevents another interrupt during the
same 0count.
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3. Changes the RLDR value for the down count sequence after the one that is
currently in progress, as described above.
A PRT interrupt involves time-periodic functions in service to the overall
application.
4. Restores the saved registers when the PRT ISRis complete, then returns to
the interrupt process using EI and RET instructions.
If both PRTs are active and both are started and stopped, sometimes at interrupt
level and sometimes at mainline level, mainline code that reads, modifies, and
writes the TCR protects against conflicts with an ISR for the other PRT,
surrounding the read-modify-write (or steps 1-5 in “Writing an RLDR”, on page
71) with DI and EI instructions.
246UꢁCPFꢁ4GUGV
Both prescalers reset to PHI/20, both TMDRs and both RLDRs reset to FFFFH,
and the TCR resets to all 0s, which inhibits PRT operation until a TDE bit is set.
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The Z80S188 includes the equivalent of one Z80-SIO device: two multiprotocol,
full-duplex serial channels called A and B. Each channel can handle Asynchro-
nous, Classic Synchronous, or HDLC/SDLC communications, providing a variety
of options in each mode.
Each channel provides pins for Tx and Rx Data, Tx and Rx Clock inputs, Request
to Send and Data Terminal Ready outputs, Clear to Send and Data Carrier Detect
inputs, a Sync input or output, and a Wait/Ready output.
5+1ꢁ#FFTGUUGU
Each channel has a Data address and a Control address in I/O space.
As for the other Z80 peripherals on the Z80S188, bit 7 of the Interrupt Priority
register controls whether A15-8are decoded as all 0 for these addresses, as for
the 80180 peripherals, or whether A15-8are ignored so that Z80-compatible I/O
instructions can be used to access the SIO channels. The following table describes
only bits 7-0 of each SIO address.
6
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Writing to a channel’s Data address provides a byte of data to be transmitted,
while reading from a channel’s Data address fetches a byte of received data.
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Read or write the Data address only when status information read from the
Control address indicates that received data is available for reading, or that the
Transmitter is ready for a data byte.
Alternatively, if a transmitter or receiver is programmed to operate with DMA
channel 0 or 1, internal signalling controls when the DMA channel reads or writes
the Data address.
The Control address for an SIO channel uses indirect addressing to access several
write-only and read-only registers, as described in the following table
6
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Indirect addressing works as follows. After Reset, reading the Control address for
an SIO channel returns the contents of Read Register 0, and writing to the Control
address writes Write Register 0.
Write Register 0 includes three fields. Bits 7-6 allow software to issue one of three
separate commands affecting frame/message structure, with 00signifying No
Operation. Bits 5-3 allow software to issue one of seven other commands, with
000signifying No Operation. Bits 2-0 are an indirect register number that allows
a software to select a different Write or Read register for its next access to the
Control register, with 000keeping the next access referring to Read or Write
register 0.
Writing an all-0byte to WR0 affects nothing. At the other extreme, one write to
WR0 can issue two separate commands and select another register for the next
access to the Control address.
When software writes a non-0 value to bits 2-0 of WR0, and then reads or writes
the register selected by that value, the SIO channel clears bits 2-0 of WR0 back to
000immediately thereafter, so that the next access to the CONTROL address
again accesses Write register 0 or Read register 0.
Accesses to the Data register have no effect on this alternating access mechanism
in the Control register.
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Rather than describing registers as bit 7 of WR0 through bit 0 of WR7, then RR0-
RR2, this section describes registers, and fields within them, in a top-down order
that makes the SIO easier to learn. This order is also the order in which software
writes the Write Registers during channel initialization.
“Serial I/O (SIO) Registers”, on page 152, presents the SIO registers and fields in
Classic numerical order.
94ꢎꢅꢁThis register sets the basic modes of the overall channel.
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WR4bits 3-2 are the most basic mode selection in an SIO channel. If these bits are
00, the channel operates in a Synchronous mode. Otherwise, the channel operates
in an Asynchronous mode, and the field indicates the (minimum) number of STOP
bits that the transmitter sends between characters.
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If WR4bits 3-2 are 00, then WR4bits 5-4 select the Synchronous protocol:
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If WR4 bits 3-2 are 00to select a Synchronous mode, WR4 bits 7-6 must be 00to
select a 1X clock. If WR4 bits 3-2 are non-0 to select Async operation, WR4 bits
7-6 may be any of the following values:
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The combination of Asynchronous format on TxD and RxD, and a 1X clock, is
sometimes called Isochronous mode. In this mode, data on RxD must be Synchro-
nized with the clock on RXC as in Synchronous modes, so it is not appropriate to
call this an Asynchronous mode on the bit level. However, characters can still
occur irregularly/asynchronously, because start and stop bits frame each character.
WR4 bits 1-0 control whether the transmitter generates and sends, and the
receiver expects and checks, an additional parity bit in each character, after the
number of bits specified in WR3 (for Rx) or WR5 (for Tx):
94ꢎꢁ$KVUꢁꢏꢀꢎ
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Even parity means that the total number of one bits in each character, including
the parity bit, is even. On the receive side, if parity is used with less than 8 bits/
character, the parity bit is included in data that software or a DMA channel reads
from the channel’s Data address.
0
ꢊ Parity can be used in either Asynchronous or Synchronous modes, but it is
more common in Asynchronous applications.
94ꢏꢅꢁMost of the bits in WR5 control the Transmitter.
A 1in WR5 bit 4 enables the transmitter to send data, when software or a DMA
channel writes data to the channel’s Data address. A 0in WR5 bit 4 disables the
Transmitter.
WR5 bits 6-5 control how many data bits the Transmitter sends in each character:
94ꢏꢁ$KVUꢁꢐꢀꢏ
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This number does not include any start, parity, or stop bits.
If this field is less than 11(to select less than 8 bits per character), the Transmitter
sends the less significant bits of each character that software or a DMA channel
writes to the channel’s Data address.
If WR5 bits 6-5 are 00(to select 5 or less bits per character), each byte written to
the channel’s Data address must have one of the formats described in the
following table. The Transmitter sends the 1–5 least significant bits of each char-
acter, based on the contents of the more significant bits of each byte:
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Writing a 1to WR5 bit 4 immediately forces the TXD pin Low to send a break
condition, even if the transmitter is currently sending a character. Writing a 0to
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&
5
ꢀ+ꢋ1ꢀ%
ꢀꢐ5+1 ꢑ
WR5bit 4 releases this forcing condition, typically letting the pin return to High/1/
Mark.
WR5 bit 0 controls whether the transmitter includes transmitted characters in its
CRC calculation. In Classic Synchronous applications in which not all Tx charac-
ters are included in the CRC, software sets this bit to 1for a character to be
included, or 0for a character to be excluded, just before writing each character to
the Data address.
WR5 bit 2 selects the CRC polynomial for both transmitting and receiving. It
must be 0 for HDLC/SDLC mode. For Classic Synchronous mode it can be either:
94ꢏꢁ$KVꢁꢆ
%4%ꢁRQN[PQOKCN
X16+X12+X5+1 (CCITT)
X16+X15+X2+1 (CRC-16)
0
1
WR5bits 7 and 1 control the DTRand RTS pins respectively. In both cases, a 1
makes the pin Low and a 0makes it High. The only exception to complete soft-
ware control is that in Async mode, if software changes the RTS bit from 1to 0
while data is still being sent, the pin does not become High until all data previ-
ously written to the channel’s Data address has been sent.
94ꢌꢅꢁThe bits in WR3 control the receiver.
A 1in WR3 bit 0 enables the receiver, a 0disables the receiver. Set this bit only
after all other receive parameters have been set and the receiver is completely
initialized.
WR3bits 7-6 control the number of data bits the receiver captures in each char-
acter, not including any start, parity, or stop bits:
94ꢌꢁ$KVUꢁꢑꢀꢐ
4GEGKXGꢁ&CVCꢁ$KVUꢁRGTꢁ%JCTCEVGT
ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
ꢆ
ꢏ
ꢍ
ꢇ
WR3bit 5controls whether the CTS and DCD pins auto-enable the Transmitter and
Receiver, respectively. If bit 5 is 0, the pins can be read in Read Register 0, but
have no effect on the hardware.
In Synchronous modes, writing a 1to WR3 bit 4 sets the Sync/Hunt bit in Read
Register 0, forcing the receiver into Hunt mode, in which it searches for a Sync
character or Flag.
WR3 bit 3controls whether the receiver includes received characters in its CRC
checking. In HDLC/SDLC mode, software sets this bit to 1during initialization,
because all characters in every frame are covered by the CRC. In other Synchro-
ꢍꢏ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
5
ꢀ+ꢋ1ꢀ%
ꢀꢐ5+1 ꢑ
1
&
nous modes, software must set this bit to the appropriate state for each received
character, before the next character is transferred from the receive shift register to
the receive FIFO, or within 8-bit times of when each character goes into the FIFO.
This procedure is possible because, in Synchronous modes other than HDLC/
SDLC, the receiver includes an extra 8 bits of shift register between the receive
shift register (from which each character is transferred to the Rx FIFO) and the
receive CRC checker. This action allows 8-bit times for software to read each
character, decide if it must included in the CRC, and set or clear WR3 bit 3
accordingly.
In HDLC/SDLC mode, WR3bit 2 controls whether the receiver checks an address
at the start of each frame. If bit 2 is 1, the receiver ignores any frame in which the
first 8 bits do not match either the contents of WR6 or the global address FFH. If
this bit is 0, the receiver receives all frames.
In Synchronous modes other than HDLC/SDLC, WR3bit 1 controls whether the
receiver places Sync characters in the Rx FIFO (if this bit is 0) or strips them from
the data stream (if this bit is 1).
0
ꢊ Because this option does not affect whether received Sync characters are
included in CRC checking, software must clear this bit when it receives the first
(non-Sync) character of each message, and thereafter check for embedded Syncs
and clear WR3bit 3 for such characters.
94ꢄꢅꢁThis register controls a channel’s interrupts and WAIT/READY pin.
WR1 bits 7-5 control the WAIT/READY pin. A 1in bit 7 enables the pin. Bit 6
selects between the Ready function (1) and the Wait function (0). Bit 5 selects
whether the pin is based on the transmitter (ꢃ) or receiver (1). Treating all three
bits as a field:
94ꢄꢁ$KVUꢁꢑꢀꢏ
(WPEVKQPꢁQHꢁ9CKVꢋ4GCF[ꢁ2KP
ꢃꢃZ
ꢃꢂZ
ꢂꢃꢃ
ꢂꢃꢂ
ꢂꢂꢃ
0QVꢀFTKXGP
*KIJ
.QYꢀꢒꢀ6ZꢀPQVꢀHWNNꢘꢀ*KIJꢀꢒꢀ6ZꢀHWNN
.QYꢀꢒꢀ4ZꢀFCVCꢀCXCKNCDNGꢘꢀ*KIJꢀꢒꢀ4ZꢀGORV[
.QYꢀꢒꢀYTKVGꢀVQꢀ&CVCꢀCFFTGUUꢅꢀ6ZꢀHWNNꢘꢀ
0QVꢀ&TKXGPꢀꢒꢀPQꢀYTKVGꢀQTꢀPQVꢀHWNN
ꢂꢂꢂ
NQYꢀꢒꢀTGCFꢀHTQOꢀ&CVCꢀCFFTGUUꢅꢀ4ZꢀGORV[ꢘꢀ
0QVꢀ&TKXGPꢀꢒꢀPQꢀTGCFꢀQTꢀPQVꢀGORV[
0
ꢊ This field does not have to be programmed with any particular value in
order to use a receiver or transmitter with a DMA channel.
WR1 bit 2 in Channel B controls whether the SIO modifies the interrupt vector
that it returns during an interrupt acknowledge cycle, to identify the highest-
priority cause of the interrupt. If this bit is 0, the SIO always returns the interrupt
vector as software wrote it to Write Register 2 in channel B. If this bit is 1, the
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢍꢍ
1
&
5
ꢀ+ꢋ1ꢀ%
ꢀꢐ5+1 ꢑ
SIO modifies bits 3-1 of the vector it returns, to identify the highest-priority cause
of the interrupt (higher values have higher priority):
8GEVQTꢁ$KVUꢁꢌꢀꢄ
*KIJGUVꢀ2TKQTKV[ꢁ+PVGTTWRV
ꢃꢃꢃ
ꢃꢃꢂ
ꢃꢂꢃ
ꢃꢂꢂ
ꢂꢃꢃ
ꢂꢃꢂ
ꢂꢂꢃ
ꢂꢂꢂ
%JCPPGNꢀ$ꢀ6Zꢀ$WHHGTꢀ'ORV[
%JCPPGNꢀ$ꢀ'ZVGTPCNꢋ5VCVWUꢀ%JCPIG
%JCPPGNꢀ$ꢀ4Zꢀ%JCTCEVGTꢀ#XCKNCDNG
%JCPPGNꢀ$ꢀ5RGEKCNꢀ4GEGKXGꢀ%QPFKVKQP
%JCPPGNꢀ#ꢀ6Zꢀ$WHHGTꢀ'ORV[
%JCPPGNꢀ#ꢀ'ZVGTPCNꢋ5VCVWUꢀ%JCPIG
%JCPPGNꢀ#ꢀ4Zꢀ%JCTCEVGTꢀ#XCKNCDNG
%JCPPGNꢀ#ꢀ5RGEKCNꢀ4GEGKXGꢀ%QPFKVKQP
0
ꢊ WR1bit 2in channel A has no function.
WR1bits 4-3 control receive interrupts:
94ꢄꢁ$KVUꢁꢎꢀꢌ
4GEGKXGꢁKPVGTTWRVꢁOQFG
ꢃꢃ
ꢃꢂ
ꢂꢃ
&KUCDNGFꢀꢐPGXGTꢑ
1PꢀHKTUVꢀEJCTCEVGT
#NNꢀEJCTCEVGTUꢘꢀRCTKV[ꢀGTTQTꢀKUꢀCꢀ5RGEKCNꢀ4GEGKXGꢀ%QPFKꢌ
VKQP
ꢂꢂ
#NNꢀEJCTCEVGTUꢘꢀRCTKV[ꢀGTTQTꢀKUꢀPQVꢀCꢀ5RGEKCNꢀ4GEGKXGꢀ
%QPFKVKQP
If parity checking is enabled in WR4, WR bit 2 is 1, and this field is 10, an inter-
rupt for a received character with a parity error is written to the Special Receive
Condition ISR, while interrupts for parity-correct characters are written to the Rx
Character Available ISR.
A 1in WR1 bit 1 enables an interrupt whenever the Transmitter buffer is empty.
A 1in WR1 bit 0 enables External/Status Change interrupts. “Handling External/
Status Interrupts”, on page 94, describes how to handle such interrupts.
%QOOCPFUꢁKPꢁ94ꢃꢅꢁIn addition to the indirect register address in bits 2-0, WR0
contains two command fields. Commands are values written to these fields, that
are not themselves latched like most other register bits, but rather serve to change
the state of the SIO channel at the end of the write operation.
ꢍꢇ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
5
ꢀ+ꢋ1ꢀ%
ꢀꢐ5+1 ꢑ
1
&
WR0 bits 5-3 can contain the following commands:
94ꢃꢁ$KVUꢁꢏꢀꢌ
%QOOCPFꢁ0COGꢁCPFꢁ&GUETKRVKQP
ꢃꢃꢃ
0WNNꢁEQFGꢅꢀ7UGꢀVJKUꢀXCNWGꢀYJGPꢀYTKVKPIꢀ94ꢃꢀVQꢀUGVꢀCPꢀKPFKꢌ
TGEVꢀCFFTGUUꢀCPFꢋQTꢀKUUWGꢀCꢀEQOOCPFꢀKPꢀDKVUꢀꢍꢌꢏꢄ
ꢃꢃꢂ
ꢃꢂꢃ
5GPFꢁ#DQTVꢅꢀ+Pꢀ*&.%ꢀOQFGꢅꢀVJKUꢀEQOOCPFꢀOCMGUꢀVJGꢀ
VTCPUOKVVGTꢀUGPFꢀCPꢀ#DQTVꢀUGSWGPEGꢅꢀEQPUKUVKPIꢀQHꢀꢇꢀVQꢀꢂꢊꢀ
ꢂUꢄ
4GUGVꢁ'ZVGTPCNꢋ5VCVWUꢁ+PVGTTWRVUꢅꢀ#HVGTꢀCPꢀ'ZVGTPCNꢋ5VCVWUꢀ
KPVGTTWRVꢅꢀVJGꢀUVCVWUꢀDKVUꢀKPꢀ44ꢃꢀCTGꢀNCVEJGFꢄꢀ6JKUꢀEQOOCPFꢀ
WPNCVEJGUꢀVJGOꢀCPFꢀTGꢌGPCDNGUꢀUWEJꢀKPVGTTWRVUꢄꢀ.CVEJKPIꢀ
VJGꢀUVCVWUꢀDKVUꢀECRVWTGUꢀUJQTVꢀRWNUGUꢅꢀUQꢀVJCVꢀUQHVYCTGꢀJCUꢀ
CꢀEJCPEGꢀVQꢀFGVGEVꢀJQYꢀVJGUGꢀDKVUꢀJCXGꢀEJCPIGFꢄ
ꢃꢂꢂ
%JCPPGNꢁ4GUGVꢅꢀ6JKUꢀEQOOCPFꢀTGUGVUꢀVJGꢀEJCPPGNꢀUVCVGꢀNKMGꢀ
Cꢀ.QYꢀQPꢀ4'5'6ꢄꢀ9TKVKPIꢀVJKUꢀEQOOCPFꢀVQꢀEJCPPGNꢀ#ꢀCNUQꢀ
TGUGVUꢀVJGꢀKPVGTTWRVꢀRTKQTKVK\CVKQPꢀNQIKEꢄꢀ#NNQYꢀHQWTꢀGZVTCꢀ
2*+ꢀENQEMUꢀCHVGTꢀKUUWKPIꢀVJKUꢀEQOOCPFꢅꢀDGHQTGꢀYTKVKPIꢀVQꢀ
VJGꢀEJCPPGNꢀCICKPꢄ
ꢂꢃꢃ
ꢂꢃꢂ
'PCDNGꢁ+PVGTTWRVꢁQPꢁ0GZVꢁ4Zꢁ%JCTCEVGTꢅꢀ+Hꢀ94ꢊꢀDKVUꢀCTGꢀꢃꢂꢀ
VQꢀUGNGEVꢀ+PVGTTWRVꢀ1Pꢀ(KTUVꢀ%JCTCEVGTꢀOQFGꢀHQTꢀVJGꢀTGEGKXGTꢅꢀ
VJKUꢀEQOOCPFꢀTGꢌGPCDNGUꢀCPꢀKPVGTTWRVꢀHQTꢀVJGꢀPGZVꢀEJCTꢌ
CEVGTꢀTGEGKXGFꢄ
4GUGVꢁ6TCPUOKVVGTꢁ+PVGTTWRVꢁ2GPFKPIꢅꢀ+HꢀVTCPUOKVVGTꢀKPVGTꢌ
TWRVUꢀCTGꢀGPCDNGFꢀD[ꢀ94ꢂꢀDKVꢀꢂꢅꢀKPVGTTWRVUꢀQEEWTꢀYJGPꢀVJGꢀ
6ZꢀDWHHGTꢀTGIKUVGTꢀDGEQOGUꢀGORV[ꢄꢀ5QHVYCTGꢀECPꢀKUUWGꢀVJKUꢀ
EQOOCPFꢀVQꢀRTGXGPVꢀHWTVJGTꢀ6ZꢀKPVGTTWRVUꢅꢀWPVKNꢀUQHVYCTGꢀ
YTKVGUꢀCꢀPGYꢀ6ZꢀEJCTCEVGTꢀVQꢀVJGꢀEJCPPGN Uꢀ&CVCꢀCFFTGUUꢅꢀQTꢀ
WPVKNꢀVJGꢀ%4%ꢀJCUꢀDGGPꢀUGPVꢄ
ꢂꢂꢃ
ꢂꢂꢂ
'TTQTꢁ4GUGVꢅꢀ6JGꢀ2CTKV[ꢀCPFꢀ1XGTTWPꢀDKVUꢀKPꢀ44ꢂꢀCTGꢀEWOWꢌ
NCVKXGꢋNCVEJGFꢄꢀ6JKUꢀEQOOCPFꢀTGUGVꢀVJGUGꢀDKVUꢄ
4GVWTPꢁ(TQOꢁ+PVGTTWRVꢅꢀ9TKVKPIꢀVJKUꢀEQOOCPFꢀVQꢀEJCPPGNꢀ#ꢀ
JCUꢀVJGꢀUCOGꢀGHHGEVꢀCUꢀGZGEWVKPIꢀCPꢀ4'6+ꢀKPUVTWEVKQPꢈꢀKVꢀ
ENGCTUꢀVJGꢀ+PVGTTWRVꢀ7PFGTꢀ5GTXKEGꢀꢐ+75ꢑꢀUVCVWUꢀQHꢀVJGꢀ
JKIJGUVꢀRTKQTKV[ꢀ5+1ꢀOQFWNGꢀVJCVꢀJCFꢀ+75ꢀUGVꢀꢐKHꢀCP[ꢑꢄꢀ6JKUꢀ
GPCDNGUꢀNQYGTꢌRTKQTKV[ꢀKPVGTTWRVUꢀVJCVꢀJCFꢀDGGPꢀKPJKDKVGFꢀ
D[ꢀVJGꢀ+75ꢀEQPFKVKQPꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢍꢁ
1
&
5
ꢀ+ꢋ1ꢀ%
ꢀꢐ5+1 ꢑ
WR0 bits 7-6 may contain the following commands:
94ꢃꢁ$KVUꢁꢑꢀꢐ
%QOOCPFꢁ0COGꢁCPFꢁ&GUETKRVKQP
ꢃꢃ
0WNNꢁEQFGꢅꢀ7UGꢀVJKUꢀXCNWGꢀYJGPꢀYTKVKPIꢀVQꢀ94ꢃꢀVQꢀUGVꢀCPꢀ
KPFKTGEVꢀCFFTGUUꢀCPFꢋQTꢀKUUWGꢀCꢀEQOOCPFꢀKPꢀDKVUꢀꢆꢌꢊꢄ
ꢃꢂ
4GUGVꢁ4Zꢁ%4%ꢁ%JGEMGTꢅꢀ6JKUꢀEQOOCPFꢀKUꢀPGGFGFꢀQPN[ꢀKPꢀ
%NCUUKEꢀ5[PEJTQPQWUꢀOQFGꢅꢀDGECWUGꢀKPꢀ*&.%ꢋ5&.%ꢀOQFGꢀ
%4%ꢀEJGEMKPIꢀKUꢀHWNN[ꢀCWVQOCVKEꢄꢀ+Pꢀ%NCUUKEꢀ5[PEJTQPQWUꢀ
OQFGꢅꢀUQHVYCTGꢀKUUWGUꢀVJKUꢀEQOOCPFꢀDGHQTGꢀVJGꢀHKTUVꢀ
HTCOGꢅꢀCPFꢀCHVGTꢀKVꢀJCUꢀEJGEMGFꢀVJGꢀ%4%ꢀEQTTGEVPGUUꢀQHꢀCꢀ
HTCOGꢄ
ꢂꢃ
ꢂꢂ
4GUGVꢁ6Zꢁ%4%ꢁ)GPGTCVQTꢅꢀ+Pꢀ*&.%ꢋ5&.%ꢀOQFGꢅꢀVJKUꢀ
EQOOCPFꢀKUꢀPGGFGFꢀQPN[ꢀFWTKPIꢀFGXKEGꢀKPKVKCNK\CVKQPꢄꢀ+Pꢀ
%NCUUKEꢀ5[PEJTQPQWUꢀOQFGꢅꢀUQHVYCTGꢀKUUWGUꢀVJKUꢀEQOOCPFꢀ
DGHQTGꢀYTKVKPIꢀVJGꢀHKTUVꢀEJCTCEVGTꢀQHꢀCꢀPGYꢀHTCOGꢀVQꢀVJGꢀ
EJCPPGN UꢀFCVCꢀCFFTGUUꢄ
4GUGVꢁ6Zꢁ7PFGTTWPꢋ'1/ꢁ.CVEJꢅꢀ+UUWKPIꢀVJKUꢀEQOOCPFꢀ
ENGCTUꢀCPꢀKPVGTPCNꢀUVCVGꢀKPꢀVJGꢀVTCPUOKVVGTꢀECNNGFꢀVJGꢀ
7PFGTTWPꢋ'1/ꢀDKVꢅꢀYJKEJꢀKUꢀWUGFꢀQPN[ꢀKPꢀ5[PEJTQPQWUꢀ
OQFGUꢄꢀ6JKUꢀDKVꢀKUꢀUGVꢀD[ꢀ4'5'6ꢀCPFꢀYJGPꢀVJGꢀVTCPUOKVVGTꢀ
UGPFUꢀVJGꢀGPFꢀQHꢀCꢀ5[PEJTQPQWUꢀHTCOGꢋOGUUCIGꢄꢀ+Vꢀ
EQPVTQNUꢀYJCVꢀVJGꢀVTCPUOKVVGTꢀFQGUꢀYJGPꢀKVꢀTWPUꢀQWVꢀQHꢀ
FCVCꢅꢀCꢀ6TCPUOKVꢀ7PFGTTWPꢀEQPFKVKQPꢄꢀ
+Pꢀ%NCUUKEꢀ5[PEJTQPQWUꢀOQFGꢅꢀKHꢀVJGꢀDKVꢀKUꢀꢂꢀVJGꢀ6ZꢀUGPFUꢀCꢀ
5[PEꢀEJCTCEVGTꢅꢀYJKNGꢀKHꢀVJGꢀDKVꢀKUꢀꢃꢀKVꢀUGPFUꢀVJGꢀCEEWOWꢌ
NCVGFꢀ%4%ꢀHQNNQYKPIꢀD[ꢀQPGꢀQTꢀOQTGꢀ5[PEꢀEJCTCEVGTꢐUꢑꢄꢀ+Pꢀ
*&.%ꢋ5&.%ꢀOQFGꢅꢀKHꢀVJGꢀDKVꢀKUꢀꢂꢀVJGꢀ6ZꢀUGPFUꢀQPGꢀQTꢀOQTGꢀ
(NCIꢐUꢑꢀYJGPꢀCPꢀWPFGTTWPꢀQEEWTUꢄꢀ+HꢀVJGꢀDKVꢀKUꢀꢃꢅꢀKVꢀUGPFUꢀVJGꢀ
CEEWOWNCVGFꢀ%4%ꢀHQNNQYGFꢀD[ꢀQPGꢀQTꢀOQTGꢀ(NCIꢐUꢑꢄ
*KUVQTKECNN[ꢅꢀ5+1ꢀFQEWOGPVCVKQPꢀJCUꢀWTIGFꢀ*&.%ꢋ5&.%ꢀ
UQHVYCTGꢀVQꢀKUUWGꢀVJKUꢀEQOOCPFꢀCPFꢀENGCTꢀVJGꢀDKVꢅꢀCUꢀUQQPꢀ
CUꢀRQUUKDNGꢀCHVGTꢀKVꢀRTGUGPVUꢀVJGꢀHKTUVꢀEJCTCEVGTꢀQHꢀVJGꢀHTCOGꢀ
VQꢀVJGꢀ6TCPUOKVVGTꢄꢀ+PꢀVJKUꢀECUGꢅꢀVJGꢀVTCPUOKVVGTꢀCNYC[Uꢀ
UGPFUꢀCꢀ%4%ꢄꢀ+HꢀUQHVYCTGꢀFGVGEVUꢀVJCVꢀVJGꢀWPFGTTWPꢀ
QEEWTTGFꢀCVꢀCPꢀKPCRRTQRTKCVGꢀRQKPVꢅꢀUQHVYCTGꢀECPꢀQXGTTKFGꢀ
VJGꢀUGPFKPIꢀQHꢀVJGꢀ%4%ꢀD[ꢀKUUWKPIꢀCꢀ5GPFꢀ#DQTVꢀEQOOCPFꢄꢀ
6JKUꢀUGSWGPEGꢀKUꢀV[RKECNꢀYJGPꢀCPꢀWPFGTTWPꢀQEEWTUꢀYKVJKPꢀCꢀ
HTCOGꢄ
+PVGTTWRVꢁ8GEVQTꢁKPꢁ%JCPPGNꢁ$ꢁ94ꢆꢅꢁData written to this register are returned
during an interrupt acknowledge cycle for any interrupt from either channel. If
channel B’s WR1 bit 2 is 0, all eight bits are returned as written. If this bit is 1, bits
7-4 and 0are returned as written, and bits 3-1reflect the highest priority channel
and interrupt type being requested, as described above for WR1 bit 2.
94ꢐꢅꢁThe contents of this register depends on the channel mode:
Async: not used
ꢇꢃ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
5
ꢀ+ꢋ1ꢀ%
ꢀꢐ5+1 ꢑ
1
&
Monosync or External Sync: Tx Sync character
Bisync: First 8 bits of common Tx/Rx Sync pattern
HDLC/SDLC: Address match character if WR2 bit 2 is 1
94ꢑꢅꢁThe contents of this register depends on the channel mode:
Async or External Sync: not used
Monosync: Rx Sync character
Bisync: Last 8 bits of common Tx/Rx Sync pattern
HDLC/SDLC: must be 01111110(Flag pattern)
5+1ꢁ4GCFꢁTGIKUVGTU
44ꢃꢅꢁThis register includes the most basic channel status.
RR0 bit 0 is 1if there is at least one received character available to be read from
the channel’s data address.
In channel A, RR0 bit 1 is 1if there are any interrupt condition(s) in either
channel.
RR0 bit 2 is 1if there is permission to write a transmit character to the channel’s
data address.
0
ꢊ
1. Bits 7-3 of RR0 are latched as a group by the channel, whenever any of
bits 7 or 5-3 change, or when bit 6 is 1. This latching prevents transient
conditions from being lost before software can detect them. To clear this
latching and read the real-time status of these bits, write a Reset
External Status Interruptscommand to WR0, as described
above.
2. In the following descriptions, the phrase the last time status was latched
or unlatched is defined as the more recent of the following states
a. The first time any of bits 7 or 5-3 changed, or bit 6 was set, since
Reset or since the last Reset
External/Status
Interruptscommand was written to WR0
b. When the last Reset
External/Status Interrupts
command was written to WR0
RR0 bit 3 describes the state of the channel’s DCD pin (0= High, 1= Low) the
last time status was latched or unlatched.
RR0 bit 4 describes the state of the SYNC pin the last time status was latched or
unlatched. Behind the latch, this pin is an input or output according to the mode:
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RR0 bit 5 describes the state of the channel’s CTS pin (0=High, 1=Low) the last
time status was latched or unlatched.
RR0 bit 6 displays the Transmit Underrun status the last time status was latched or
unlatched. Behind the latch, Transmit Underrun status is set by Reset, and when
an Underrun occurs in a Synchronous mode, that is, when software or a DMA
channel has not written a character to the channel’s Data address by the time one
is needed, inside a frame or message. Transmit Underrun status is cleared only by
writing the Reset Transmit Underrun command to WR0, as described above.
0
ꢊ In Synchronous modes the transmitter behaves differently when an
Underrun occurs, depending on whether software has cleared the Transmit
Underrun status. If so, it sends the CRC before sending the Sync or Flag. If not, it
sends a Sync or Flag.
RR0 bit 7 displays the Break detection status in Async mode, or Abort detection
status in HDLC/SDLC mode, the last time status was latched or unlatched. Behind
the latch, Break detection is set by an all-0character with a Framing Error, and
cleared when the channel’s RXD pin returns to 1. Break detection can also be set
when Abort detection is set by seven consecutive 1s inside a frame, and is cleared
when a 0is received.
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44ꢄꢅꢁThis register contains Special Receive Condition status and the HDLC/
SDLC Residue value.
In HDLC/SDLC mode, a 1in RR1 bit 7 indicates that a closing Flag has been
received. It can be cleared by writing an ERROR RESET command to WR0, and is
automatically cleared when the first character of the next frame is received.
A 1in RR1 bit 6 indicates a Framing Error in Async mode or a CRC error in other
modes. Framing Error accompanies the character in which the error was detected.
As CRC error, this bit is meaningful only when bit 7 is 1. In either meaning, the
bit is not latched and is updated after a character is read and the next character has
been received.
A 1in RR1 bit 5 indicates a Receive Overrun condition. Overrun occurs if the
Receive FIFO contains 3 characters and another character has been assembled in
the receive shift register. This error bit accompanies the character that overwrote
the previous character, which was lost. But even if the character is read, this bit is
latched, and maintains the value of 1until software writes an Error Reset
command to WR0. If receive data interrupts are enabled and Status Affects Vector
operation is enabled because WR1 bit 2 is 1, the channel returns the Special
Receive Condition vector for a character with an Overrun error.
RR1 bit 4 indicates a Parity Error. It is 1if parity checking is enabled because
WR4 bit 0 is 1, and the character parity did not match the type selected by WR4
bit 1. This bit is latched, and stays 1until software writes an Error Reset
command to WR0.
For HDLC/SDLC reception, when RR1 bit 7 is 1, RR1 bits 3-1 indicate the
number of data bits in the last few characters presented by the receiver for the
frame. Figures 18 through illustrate the relationship between values of this field
and the contents of these characters, for 8 through 5 bits/character respectively.
In Async modes, RR1 bit 0 is set when all transmit data written to the channel’s
data address has been sent. It is always 1in Synchronous modes.
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44ꢆꢅꢁThis register can be read only from channel B, and returns the interrupt
vector that an interrupt acknowledge cycle returns at the same moment. If channel
B’s WR1 bit 2 is 1to select Status Affects Vector operation, bits 7-4 and 0 are
returned as software write them to WR2, while bits 3-1 contain a code for the
highest-priority condition for which an interrupt is currently pending, or 011if no
interrupts are currently pending. Table 20 describes the codes. If WR1 bit 2 is 0,
reading RR2 returns exactly what the software last wrote to WR2.
6
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The SIO, CTC, and PIO modules logically OR their interrupt requests with those
from any external peripherals that are connected to the INT0 pin. Three external
peripherals must drive INT0 Low in an open-collector or open-drain fashion. The
Z80S188 drives INT0 Low in an open-drain fashion, when any of the SIO or CTC
channels or PIO ports are requesting an interrupt.
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Each SIO channel includes three modules that can request an interrupt: the
Receiver, Transmitter, and External/Status conditions. Each of these 6 interrupt
types include state bits called Interrupt Pending (IP)and Interrupt
Under Service (IUS). All six types share the same base interrupt vector,
but if bit 2 of WR1 is 1, the SIO returns a code identifying the highest priority
SIO type requesting an interrupt in bits 3-1 of the interrupt vector.
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interrupt type can request an interrupt at the same time, a mechanism is needed to
select the order in which their requests are serviced. Z80 peripherals and certain
other ZiLOG devices use a daisy chain to control the relative priority of interrupt
requests among multiple devices and interrupt types within devices.
As described in “Interrupt Acknowledge Daisy Chaining”, on page 18, each SIO
interrupt type has an Interrupt Enable In (IEI) pin, from which it receives
permission to interrupt from higher-priority devices, and an Interrupt Enable Out
(IEO)pin, on which it grants permission to interrupt, to lower-priority devices.
The daisy-chain order and priority within each Z80-device-equivalent module is
fixed. For the SIO, Channel A’s Receiver has the highest priority, followed by
Transmitter A, External/Status A, Receiver B, Transmitter B, and External/Status
B.
The SIO, CTC, and PIOs in the Z80S188 are always consecutive on the daisy
chain, but the relative priority among them is programmable in the Interrupt
Priority register.
Please see “Interrupt Acknowledge Daisy Chaining”, on page 18 for more infor-
mation about interrupt daisy-chaining.
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1. Write a Channel Resetcommand, 08H, to WR0
2. Write the desired interrupt vector to channel B’s WR2, if the application
enables any interrupts from either SIO channel, and previous initialization has
not yet been implemented.
3. Write binary cc00ssppto WR4:
a. ccare typically 01for /16 clocking, but can be 00for 1X isochronous,
10for /32, or 11for /64 clocking. In isochronous operation, data on RxD
need not be synchronous to the clock on RxC, as in Sync modes.
b. sscan be 01to send 1 Stop bit, 10for 1.5, or 11to send 2 Stop bits.
c. ppare typically 00, but can be 10for odd parity generation and checking,
or 11for even parity.
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4. Write binary nne00001to WR3:
a. nnis typically 11to assemble 8 data bits per character, but can be 10for
7, 01for 6, and 00for 5 bits/character. This number does not include the
parity bit if the previous step enabled parity.
b. eis typically 0, but can be 1if the signal on the DCD pin auto-enables the
receiver, and the signal on CTS autoenables the transmitter.
5. Write binary dnn010r0to WR5:
a. dcontrols the DTR pin, 0for High, 1for Low.
b. nnis typically 11to send 8 bits/character, but can be 10for 7, 01for 6,
and 00for 5 bits/character. This number does not include the parity bit if
parity is enabled in WR4.
c. rcontrols the RTS pin, 0for High, 1for Low.
6. Write binary wwwiisteto WR1:
a. wwware typically 000; otherwise they select the function of the WAIT/
RDY pin as described on page 77.
b. ii are typically 00 for polled reception or 11 for interrupt-driven
reception. 01selects a receive interrupt on the first received character. 10
selects interrupt-driven reception in which a character with a parity error
is handled via the Special Receive condition ISR.
c. sis typically 1to select status affects vector operation, in which the SIO
returns one of 8 consecutive vectors depending on the highest priority
interrupting condition. If sis 0, the SIO returns the vector in WR2 for any
interrupt on either channel.
d. A 1in tenables transmit interrupts
e. A 1in eenables external/status interrupts
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1. Write a Channel Resetcommand, 08H, to WR0.
2. Write the desired interrupt vector to channel B’s WR2 if the application
enables any interrupts from either SIO channel, and previous initialization has
not yet been implemented.
3. Write binary 00mm00ppto WR4:
a. mmare 00to select an 8-bit Sync pattern (monosync), 01to select a 16-
bit Sync pattern (Bisync), or 11to select external Sync detection.
b. ppare typically 00, but can be 10for odd parity generation and checking,
or 11for even parity.
4. Write binary dnn00cr0to WR5:
a. dcontrols the DTR pin, 0for High, 1for Low.
b. nnis typically 11to send 8 bits/character, but can be 10for 7, 01for 6,
and 00for 5 bits/character. This number does not include the parity bit if
parity is enabled in WR4.
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c. cis 0to use the CRC/CCITT polynomial, 1for CRC-16.
d. rcontrols the RTS pin, 0for High, 1for Low.
5. Write binary nne10010to WR3:
a. nnis typically 11to assemble 8 data bits per character, but can be 10for
7, 01for 6, and 00for 5 bits/character. This number does not include the
parity bit if parity is enabled in WR4.
b. eis typically 0, but can be 1if the DCD pin auto-enables the receiver, and
the signal on CTS autoenables the transmitter.
6. Write the Sync character to WR6 for monosync operation. For Bisync, write
the first Sync character to WR6 and the second Sync character to WR7.
7. Write binary wwwiisteto WR1:
a. wwware typically 000; otherwise they select the function of the WAIT/
RDY pin as described on page 77.
b. ii are typically 00 for polled reception or 11 for interrupt-driven
reception. 01selects a receive interrupt on the first received character. 10
selects interrupt-driven operation in which a character with a parity error
is handled via the Special Receive condition ISR.
c. sis typically 1to select status affects vector operation, in which the SIO
returns one of 8 consecutive vectors depending on the highest priority
interrupting condition. If sis 0, the SIO returns the vector in WR2 for any
interrupt on either channel.
d. A 1in tenables transmit interrupts.
e. A 1in eenables external/status interrupts.
8. Write the same value as in step 4 to WR5, but with bit 3 (08H) set to enable
the transmitter. Write the value from step 5 to WR3, but with bit 0 set to enable
the receiver.
9. Write a Reset Rx CRC Checker command to WR0.
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1. Write a Channel Resetcommand, 08H, to WR0
2. Write the desired interrupt vector to channel B’s WR2 if the application
enables any interrupts from either SIO channel, and previous initialization has
not yet been implemented.
3. Write binary 001000ppto WR4. ppare typically 00, but can be 10for odd
parity generation and checking, or 11for even parity.
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4. Write binary dnn000r1to WR5:
a. dcontrols the DTR pin, 0for High, 1for Low.
b. nnis typically 11to send 8 bits/character, but can be 10for 7, 01for 6,
and 00for 5 bits/character. This number does not include the parity bit if
parity is enabled in WR4.
c. rcontrols the RTS pin, 0for High, 1for Low.
5. Write binary nne10a00to WR3:
a. nnis typically 11to assemble 8 data bits per character, but can be 10for
7, 01for 6, and 00for 5 bits/character. This number does not include the
parity bit if parity is enabled in WR4.
b. eis typically 0, but can be 1if the DCD pin auto-enables the receiver, and
CTS autoenables the transmitter.
c. ais 1if the channel matches the first character of each received frame
against the character in WR6, and ignores non-matching frames.
6. Write the match character to WR6.
7. Write 7EH(the Flag pattern) to WR7.
8. Write binary wwwiisteto WR1:
a. wwware typically 000; otherwise, they select the function of the WAIT/
RDY pin as described on page 77.
b. ii are typically 00 for polled reception or 11 for interrupt-driven
reception. 01selects a receive interrupt on the first received character. 10
selects interrupt-driven operation in which a character with a parity error
is handled via the Special Receive condition ISR.
c. sis typically 1to select status affects vector operation, in which the SIO
returns one of 8 consecutive vectors depending on the highest priority
interrupting condition. If sis 0, the SIO returns the vector in WR2 for any
interrupt on either channel.
d. A 1in tenables transmit interrupts
e. A 1in eenables external/status interrupts
9. Write the same value as in step 4 to WR5, except with bit 3 (08H) set to enable
the transmitter. Write the value from step 5 to WR3, except with bit 0 set to
enable the receiver.
10. Write a Reset Tx CRC Generator command (80H) to WR0.
2QNNGFꢁ6TCPUOKUUKQP
1. If there is data to send, software reads RR0 from the channel’s Control address
periodically, and proceeds to the next step if bit 2, Tx Empty, is 1.
2. In HDLC/SDLC mode, if frames have a required format and the next character
is not the first one of a frame, read RR0 and check the Tx Underrun/EOM bit.
If it is 1, an underrun condition has occurred inside of a frame. Write a Send
Abort command to WR0, and return to step 1.
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3. In CLASSIC SYNC mode only, if the next character is the first included in the
CRC for the message, write a Reset Tx CRC Generator command to
WR0.
4. In CLASSIC SYNC mode only, determine if the next character is included in
the CRC. Write WR5 (if necessary) with bit 0 set to 1for inclusion or 0to
exclude.
5. Fetch the next character from memory and write it to the channel’s data
address.
6. In HDLC mode only, if the character just written is the first one of a new frame,
write a Reset Tx Underrun/EOMcommand to WR0.
7. In CLASSIC SYNC mode only, if messages have a required format and the
character just written was the last one of a message, or if messages can be of
any length and serve only to convey a byte stream with its own internal
structure, and the character just written was the first one of a message, write a
Reset Tx Underrun/EOM command to WR0 and set an internal flag
indicating that this operation was performed.
8. Return to step 1.
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1. Read RR0 from the channel’s Control address periodically. Proceed to the next
step if either bit 0 or bit 7, Rx Available or Break/Abort, is 1.
2. In Async or HDLC/SDLC modes only, if RR0 bit 7, Break/Abort, is 1, write a
ResetExternal/Statuscommand to WR0 to unlatch the status in RR0,
then read RR0 periodically until RR0 bit 7 returns to 0, which indicates that
the Breakor Abortsequence is over. At that time, write another Reset
External/Statuscommand to WR0 to unlatch the RR0 status again.
In HDLC/SDLC mode, an Abort sequence while a frame is in progress
indicates that software discards that frame, then returns to step 1 to wait for the
first character of the next frame.
In Async mode on a full duplex link, a Break traditionally indicates that the
station receiving it stops sending. If a Break follows a character that
contained a Framing Error, the Break indicates that sender started the Break
while that character was being sent. When a BREAK is over, bit 0 of RR0, Rx
Available, is set, and software reads the extraneous all-0character from the
Data address, then discards it, and returns to step 1.
3. For Rx Available without Break/Abort, software reads the status
associated with the character from RR1, then saves it, and reads the character
from the channel’s Data address.
4. If parity checking is enabled, handling of a character with a parity error is
application- and protocol-dependent, except that software must write an
ErrorResetcommand to WR0 to clear the parity error bit.
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5. If the RR1 status shows an overrun condition, handling of preceding data is
application- and protocol-dependent. One character was lost before the
character flagged with the overrun status; others may have been lost
subsequently. Software must write an Error Reset command to WR0 to
clear the overrun bit. In HDLC/SDLC and CLASSIC SYNC modes, software
typically discards/ignores the frame/message in progress, then writes a value
to WR3 that includes a 1in bit 4, which forces the receiver into HUNT mode,
then returns to step 1.
6. In ASYNC mode, software checks the Framing Error bit in RR1, but the
handling of a character with a framing error is application-dependent.
7. Except for certain kinds of error characters in certain protocols, software stores
the received character in memory, advances the buffer address, and if the
current buffer is filled, advances the pointer to the next buffer.
8. In CLASSIC SYNC mode, if the Strip Sync bit was set in WR3, software
rewrites WR3 to clear this bit.
9. In CLASSIC SYNC mode with CRC checking, software examines the
character to determine if it is included in CRC checking, and if necessary, write
to WR3 so that bit 3 is 1 to include or 0 to exclude the character. (Sync
characters within a message are excluded.)
10. In Classic Sync mode, software must examine whether each character is a
message-terminator. When a message-terminator is detected, if CRC checking
is used and the Rx character length is less than 8 bits, software rewrites WR3
for 8 bits/character, at least for the duration of the CRC.
a. For CRC checking, software waits for four more Rx Available flags (RR0
bit 0). The first two flags are associated with the CRC characters
themselves; the third is typically a Pad or Sync character. These three
characters can be read and discarded. When the fourth Rx Available flag
is set, software reads RR1 and checks bit 6 to determine the CRC
correctness of the message.
b. Software writes a Reset Rx CRC Checker command to WR0. Depending
on the protocol, software reads the next character and examines it for a
Sync character or the start of a new frame. Software may then discard the
character, exclude it from the Rx CRC, and write to WR3 to force the
receiver back into Hunt mode for a new Sync sequence.
11. In HLDC/SDLC mode, software checks bit 7 of RR1 (EOF) to detect when the
last character of the CRC was read. When RR1 bit 7 is 1, the accompanying
bit 6 indicates CRC correctness, and the accompanying bits 3-1 indicate the
frame length.
12. Unless indicated otherwise in a step above, after processing each character, the
software returns to step 1.
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The following steps assume the processor is in Interrupt mode 2 and that bit 2 of
WR1 is 1to select Status Affects Vector mode. Otherwise, when an interrupt
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occurs, software must read RR0 and possibly RR1 of each SIO channel, to deter-
mine the cause of each interrupt.
1. When the SIO returns an interrupt vector, resulting in execution of an SIO Tx
Interrupt Service Routine (ISR), the SIO saves as many registers that it may
use (worst case), using PUSHor EX AF,AF’and EXXinstructions.
2. Next, the Tx ISR retrieves the transmit context. If this interrupt follows CRC
transmission in a Synchronous mode, and another frame or message is not to
follow immediately, proceed to step 4.
3. Otherwise, the ISR proceeds as in steps 2-7 of “Polled Transmission”, on page
89. If the transmit context was not the end of a frame or message in a
Synchronous mode, or if there is more data to send in Async mode, proceed to
step 5.
4. Write a Reset Transmitter Interrupt Pending command to WR0. If a CRC is
sent in Synchronous modes, the next Tx interrupt cannot occur until after the
CRC has been sent. Otherwise software must write the next Tx character to the
channel’s Data address at mainline level, before another Tx interrupt can
occur.
5. The ISR concludes by restoring the saved registers and executing EI and
RETIinstructions. The transmitter detects the RETIand re-enables interrupts
from itself and lower-priority devices.
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The following steps assume the processor is in Interrupt mode 2 and that bit 2 of
WR1 is 1to select Status Affects Vector mode. Otherwise, when an interrupt
occurs, software must read RR0 and possibly RR1 of each SIO channel, to deter-
mine the cause of each interrupt.
1. When the SIO returns an interrupt vector, resulting in execution of an SIO Rx
Interrupt Service Routine (ISR), it saves as many registers that it may use
(worst case), using PUSH or EX AF,AF’ and EXX instructions.
2. The next received character is read and stored in memory. The buffer pointer
advances, and if the current buffer is full, the pointer advances to the next
buffer.
3. In CLASSIC SYNC mode, proceed as in steps 8-10 of “Polled Reception”, on
page 90.
4. Because all exceptional receive conditions, including EOM in HDLC mode,
result in External/Status interrupts or Special Receive interrupts rather than
normal Rx interrupts, the ISR concludes by restoring the saved registers and
executing EIand RETIinstructions. The receiver detects the RETIand re-
enables interrupts from itself and lower-priority devices.
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This section assumes that in Synchronous modes, each frame or message to be
sent occupies a single contiguous buffer in memory. Otherwise, software
processing is more complex.
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characters in a DMA buffer are included in the CRC. Otherwise the message is
sent using polling or interrupt-driven techniques.
1. Ensure that WR1 bit 1 is 0to disable Tx interrupts.
2. In CLASSIC SYNC mode only, write a Reset Tx CRC Generator command to
WR0, and ensure that WR5 bit 0 is 1to include all characters in the CRC (see
note above).
3. Two of the four SIO transmitters and receivers can be handled by the
Z80S188’s DMA channels at one time. If these assignments are not fixed or
were not set up during device initialization:
a. Write 100to DAR0Bbits 2-0, and 11 to DMODEbits 5-4, to handle SIO
channel A Tx using DMA0.
b. Write 101to DAR0B bits 2-0, and 11 to DMODE bits 5-4, to handle SIO
channel B Tx using DMA0.
c. Write 100 to IAR1B bits 2-0, and 0 to DCNTL bit 1, to handle SIO
channel A Tx using DMA1.
d. Write 101 to IAR1B bits 2-0, and 0 to DCNTL bit 1, to handle SIO
channel B Tx using DMA1.
4. Load DAR0L,H or IAR1L,H with 00D8H for channel A or 00DAH for
channel B. Program the other DMA registers as described in “Setting Up a
DMA Transfer”, on page 60. When the DMA channel is enabled and the SIO
Tx requests data, the DMA begins providing data to the SIO Tx.
5. In Sync modes, if the Tx is auto-enabled, wait to be sure that the transfer had
begun.
6. In Sync modes, write a Reset Tx Underrun/EOM command to WR0.
7. When the DMA channel interrupts or when software polls bit 7 or 6 of the
DSTAT register as 0, all the data has been transferred to the SIO transmitter.
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In general, CLASSIC SYNC reception cannot be handled by DMA because some
received characters (such as embedded Syncs) must be excluded from CRC
checking, and each received character must be checked for message termination.
Only very straightforward CLASSIC SYNC reception, in which message lengths
are fixed and all characters in every message are included in CRC checking, can
be handled by DMA.
1. Ensure that WR1 bits 4-3 are 00to disable Rx interrupts. WR1 bit 0 can be 1
to enable External/Status interrupts, or 0if software polls RR0 and RR1.
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2. Two of the four SIO transmitters and receivers can be handled by the
Z80S188’s DMA channels at one time. If these assignments are not fixed or
were not set up during device initialization:
a. Write 100to SAR0Bbits 2-0, and 11to DMODEbits 3-2, to handle SIO
channel A Rx using DMA0.
b. Write 101to SAR0Bbits 2-0, and 11to DMODEbits 3-2, to handle SIO
channel B Rx using DMA0.
c. Write 100 to IAR1B bits 2-0, and 1 to DCNTL bit 1, to handle SIO
channel A Rx using DMA1.
d. Write 101 to IAR1B bits 2-0, and 1 to DCNTL bit 1, to handle SIO
channel B Rx using DMA1.
3. In Classic Sync mode only, write a Reset Rx CRC Generatorcommand
to WR0, ensure that WR3 bit 3 is 1to include all characters in the CRC and set
WR3 bit 1 to strip initial Syncs.
4. Load SAR0L,Hor IAR1L,Hwith 00DHfor channel A or 00DAHfor channel
B. In Classic Sync mode, load the BCR with the fixed message length plus 3,
to allow for the CRC and the subsequent Pad or Sync character. Program the
other DMA registers as described in “Setting Up a DMA Transfer”, on page
60. When the DMA channel is enabled and the SIO Rx receives a character,
the DMA begins storing SIO Rx data.
5. If External/Status interrupts are not enabled, software must periodically poll
RR0 and RR1 to watch for conditions like BREAK, ABORT, DCD change, and
EOF.
6. When the DMA channel interrupts or when software detects bit 7 or 6 of the
DSTAT register as 0, the DMA has filled the buffer with received data. If more
Rx data is expected, software returns to step 3 or 4 to set up a new DMA buffer.
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The following steps assume the processor is in interrupt mode 2 and that bit 2 of
WR1 is 1 to select status affects vector mode. Otherwise, when an interrupt
occurs, software reads RR0 and possibly RR1 of each SIO channel, to determine
the cause of each interrupt.
1. When the SIO returns an interrupt vector resulting in execution of an SIO
External/Status Interrupt Service Routine (ISR), the SIO saves as many
registers that it may use, using PUSH or EX AF,AF’ and EXX instructions.
2. Software then retrieves the SIO context, including the last value read from
RR0.
3. Next, software reads RR0, save this value, and then performs an XOR
instruction on the current RR0 value and the previous value. Differences (1s)
among bits 7–3 of this result identify the reason(s) for the interrupt. A 1-to-0
transition of bit 6 does not produce an interrupt.
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4. Before or after handling these events, software writes a Reset External/Status
Interrupts command to WR0. This action unlatches bits 7–3 of RR0, and
allows future External/Status interrupts.
5. The ISRconcludes by restoring the saved register values, followed by EIand
RETIinstructions. The External/Status logic detects the RETIand re-enables
interrupts from itself and from lower-priority devices.
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The ASCIs are asynchronous full-duplex UARTs with the following features:
7- or 8-Bit data
Odd, even, or no parity
1 or 2 Tx stop bits
Checking for parity, framing, and overrun errors
Break generation and detection
A choice of two baud rate generators
Rx and Tx interrupts
Input or output clocking on CKA0-1
DCD and CTS on ASCI0
Operation with the on-chip DMA channels, and
A multiprocessor mode with an extra bit designating address vs. data characters.
The registers associated with the ASCIs are described in section “Async Serial
Communications Interface (ASCI) Registers”, on page 166. Control registers A
and B (CNTLA0, CNTLA1, CNTLB0, and CNTLB1) and the Extension Control
registers (ASEXT0, ASEXT1) are typically written once each, to configure an
ASCI. The Status registers (STAT0 and STAT1) indicate the current state of each
ASCI’s Receiver and Transmitter. Under control of this status, software can write
bytes to be transmitted to the Transmit Data Registers (TDR0 and TDR1), and can
read received bytes from the Receiver Data Registers (RDR0 and RDR1).
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Each ASCI uses the same basic clock for both transmitting and receiving. If bits
2–0 of an ASCI’s CNTLB register are 111, as they are after a Reset, the basic
clock is taken from the CKA0 or CKA1 pin, and neither Baud Rate Generator is
used.
To use the old BRG, which is compatible with the original ZiLOG Z80180, soft-
ware must:
1. Clear bit 3 (BRG mode) of the Extension Control register to 0, to select the
old BRG.
2. Write bit 5 (PS) and bits 2–0 (SS) in the CNTLB register to select what value
the old BRG divides the PHI clock by, to obtain the basic clock for this ASCI,
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as indicated in Table 21. This basic clock is then driven onto the CKA0 or
CKA1 pin.
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To use the new BRG, which is compatible with the ZiLOG SCC family, software
must:
1. Set bit 3 (BRG mode) of the Extension Control register to 1, to select the new
BRG.
2. Write a 16-bit binary value to the Time Constant Low and High registers. This
value is the factor by which PHI is divided to produce the basic clock, divided
by two, minus two. The new BRG derives the basic clock as:
basic clock = PHI / 2 (TC+2)
This basic clock is then driven onto the CKA0 or CKA1 pin.
%NQEMꢁ/QFGꢅꢁIf bit 4 (X1clock) in an ASCI’s Extension Control Register is 1, the
basic clock on CKA0 or CKA1 is used directly as a 1X isochronous bit clock,
which must be synchronized to the data on RXA0 or RXA1. This mode can be used
in either of two ways:
With CKA0 or CKA1 as an input, bearing a clock from the remote transmitter, that
is synchronous to the data on this ASCI’s RXA pin.
With CKA0 or CKA1 as an output, bearing the clock to the remote transmitter,
which uses it to output data on this ASCIs RXA pin.
If bit 4 (X1clock) in an ASCI’s Extension Control Register is 0, and the DRbit
(bit 3) in the CNTLB register is 0, the ASCI divides its basic clock by 16 to obtain
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the serial bit rate. If X1clock is 0and DRis 1, the ASCI divides its basic clock by
64.
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Figure 22 shows a single asynchronous character on the TXA or RXA pin. When a
Transmitter is disabled, or when it has completed sending any and all characters
that software or a DMA channel has provided, it maintains a High level on the
TXD pin. This state is also called 1 or Mark.
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When software or a DMA channel provides a character to an idle ASCI trans-
mitter, it
1. Drives TXA lot to start a start bit, on the next falling edge of the basic clock,
and maintains TXA Low for 1, 16, or 64 basic clocks depending on the X1
clock and DR bits.
2. Switches TXA to the state of the least significant bit (bit 0) of the character, and
holds that for 1, 16, or 64 clocks, and so on through the most significant bit (bit
6 or 7) of the character, and for a parity or MP bit if one of these is enabled.
3. Switches TXA to High (1, Mark) again for the first Stop bit, and maintains it
High for at least 1, 16, or 64 clocks, plus another 1, 16, or 64 clocks if bit 0 of
its CNTLA register is 1to select send two Stop bits.
The Tx character is now complete. If software or a DMA channel has provided
another character to send, the transmitter starts another start bit as described
above. Otherwise, it keeps TXA High until a character is provided.
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The Receiver has a more complex task. When it is first enabled, or after a char-
acter has been received:
1. The receiver samples the RXA pin on the rising edge of each basic clock is
sampled. If RXA is High it remains in the same state of waiting for a start bit.
If it samples RXA Low, and the X1 clock bit is 0, the receiver counts off half
a bit time, 8 basic clocks if DRis 0, or 32 basic clocks if DRis 1. The receiver
samples RXAagain.
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2. If RXA is now High, the receiver rejects the transient Low state on RXA as not
representing a Start bit, and returns to step 1. If the X1 clock bit is 1, the
receiver skips this step.
3. The receiver then counts off the number of basic clocks in a bit, 1, 16, or 64
depending on the X1 clock and DR bits, and samples RXA for the least
significant data bit (bit 0). This operation continues for each More Significant
Data bit (through bit 6 or 7), and optionally for a Parity or MP bit if these are
enabled.
4. Finally, the receiver counts off 1, 16, or 64 more basic clocks and samples the
first Stop bit. When X1clock is 0, if the receiver’s basic clock is close to the
clock that the transmitter used to send the character, (near the middle of the
first Stop bit), and if there is no noise or other error on the line, the receiver
samples the Stop bit as High/1/Mark.
If X1clock is 0, and the receiver’s and transmitter’s clocks were sufficiently
different, or if there is noise or contention on the line, the receiver samples a
Low/0/Space. This latter situation is called a framing error; when it occurs, the
receiver sets an error bit that accompanies the character through the receiver
FIFO, and sets the FE bit in the STAT register when the character becomes the
oldest in the FIFO.
The received character is now complete, and the receiver returns to sample the line
for a new Start bit, as described above.
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The Sampling Rate can be 1, 16, or 64 depending on the X1 bit in the ASEXT
register and the DR bit in the CNTLA register:
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The following notations apply to the equations below, where:
bits/second is the serial rate
f
is the system clock frequency
PHI
PS is the value written to bit 5 of CNTLB (0 or 1)
^ indicates exponentiation (2 to the power)
SS2-0is the binary value of bits 2–0 of CNTLB (0 thru 6)
DRis bit 3 of CNTLB (0 or 1)
TC is the 16-bit value in the ASTCL and ASTCH registers
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If the SS2–0 bits in the CNTLA register are 111, the CKA pin is a clock input,
which is divided by the sampling rate by the receiver and transmitter:
bits/second = fCKAin / Sampling Rate
If the SS2–0 bits are not 111, and the BRG Mode bit in the ASEXT register is 0,
the old baud rate generator divides PHI as follows for serial clocking.
bits/second=fPHI/((10+20*PS)*2^SS2-0*Sampling Rate)
where PS selects between a prescaler of 10 and 30, and 2^SS2–0is a power of
two between 1 and 64. The CKA pin outputs the clock before the final division by
the Sampling Rate:
H
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If the SS2–0 bits are not 111, and the BRG mode bit is 1, the new baud rate
generator divides PHI for serial clocking as on the ZiLOG SCC family:
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Where TC is the 16-bit value programmed into the TC high and low registers. The
CKA pin outputs the clock before the final division by the Sampling Rate:
fCKAout = fPHI/(2*(TC+2))
To find the TC value for a particular serial bit rate:
TC = (fPHI/(2 * bits/second * Sampling Rate)) - 2
1RVKQPU
ꢑꢁQTꢁꢂꢁ&CVCꢁ$KVUꢅꢁIf bit 2 of the CNTLA register is 0, the transmitter sends, and
the receiver accumulates, 7 data bits per character. If CNTLA2 is 1, the trans-
mitter sends, and the receiver accumulates, 8 data bits per character.
2CTKV[ꢅꢁIf bit 1 of the CNTLA register is 1, the transmitter accumulates and sends
a Parity bit after the data bits, and the receiver samples and checks such a bit. If
CNTLA1 is 1, a 1in bit 4 of the CNTLB register selects odd parity and a 0
selects even parity. Odd parity defines a correct character that contains an odd
number of 1bits, through and including the Parity bit, while even parity defines a
correct character that contains an even number of 1bits.
If the receiver samples the Parity bit in the incorrect state for a character, an error
bit is set that accompanies the character through the receiver FIFO, and sets the
PE bit in the STAT register when the character becomes the oldest one in the
FIFO.
6TCPUOKVꢁ5VQRꢁ$KVUꢅꢁIf bit 0 of CNTLA is 0, the transmitter sends a minimum of
one Stop bit between characters. If CNTLA is 1, it sends at least two Stop bits
between characters. Selecting two stop bits has been known to work around
timing mismatches between a transmitter and a receiver.
0
ꢊ The ASCI receivers on the Z80S188 check only one Stop bit, regardless of
bit 0 of CNTLA. This is also true of ASCI receivers on other current 8018x family
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members, as well as other UARTs, but on the original 80180, the ASCIs actually
checked two Stop bits if CNTLA0 was 1.
5VCVWU
$TGCMꢁ%QPFKVKQPUꢅꢁBreak conditions date back to the early days of Async
communications using Teletypewriters, which were functionally half-duplex in
that text could only flow in one direction at a time. If the operator of a receiving
TTY) had a problem, or something to say, and wanted to interrupt the data from
the other machine, there was a Break key that could be pressed. This drove the line
to 0/Space state for several character times, which served to turn a light on at the
other machine and stopped its paper tape reader if it was in use.
A Break is still defined as at least two character times of consecutive 0s on the
line. A receiver detects this as one or more all-0 character(s) with Framing
error(s).
Software can make a Z80S188 ASCI send a Break by writing a 1to bit 0 of the
Extension Control register. Software can ensure that any characters previously
written to the Transmit Data register are sent (by monitoring bit 0 of the Extension
Control register), before it writes a 1to the Tx Break bit. The duration of a trans-
mitted Break is completely under software control—the Break is terminated by
writing a 0to ASEXT bit 0.
While receiving an all-0 character with a Framing error is definitive evidence of a
Break, bit 1 of the Extension Control register provides more specific break detec-
tion. When the receiver detects an all-0 character with a framing error, a Break
status bit is set that accompanies the character through the receiver FIFO, and sets
bit 1 in the ASEXT register when the character becomes the oldest in the FIFO.
When this procedure occurs, the receiver does not assemble any further characters
until the RXA line returns to High/1/Mark, signalling the end of the Break condi-
tion.
4Zꢁ1XGTTWPꢅꢁThe ASCIs in the Z80S188 have 4-character Rx FIFOs between their
RX SHIFT registers and the Receive data registers that software or a DMA channel
can read. If the receiver finishes receiving a character when there are already 4
characters in the FIFO, an overrun status bit is set that accompanies the preceding
character through the FIFO, and the OVRN bit (bit 6 in the STAT register) is set
when that character becomes the oldest in the FIFO.
The receiver discards the character that triggers the overrun condition, and subse-
quent characters, until the last good character has come to the top of the FIFO so
that OVRN is set. Software then writes a 0to the EFR bit to clear it.
4GEGKXGꢁ5VCVWUꢅꢁThere are 4 receive status bits in the STAT register and one in the
Extension Control register. RDRF, bit 7 of the STAT register, is set to 1whenever
there is at least one received character in the Rx FIFO. This bit is cleared when
software or a DMA channel has read all characters out of the Rx FIFO, by Reset,
in I/O STOP mode, and on ASCI0, when the DCD0pin is autoenabled and is High.
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FE, PE, and OVRNin the STAT register are set to 1when a character with a
framing error or parity error, or the last character before an Rx Overrun, comes to
the top of the receive FIFO. Similarly, bit 1 in the Extension Control register is set
to 1when a break character comes to the top of the FIFO.
Any of these bits stay 1even if the character associated with the condition is read
out of the receive FIFO, that is, they latch an error or exception condition. All four
of these bits are cleared by reading CNTLA, clearing bit 3 (Error Flag Reset,
EFR) to 0, and writing the result back to CNTLA. This action also allows the
receiver to put subsequent characters into the receive FIFO after an Overrun, and
if the receiver is being handled by a DMA channel, allows the channel to service
the receiver once again.
/QFGOꢁ%QPVTQNꢋ5VCVWUꢅꢁASCI modem control or status signals on the Z80S188
are DCD0and CTS0. The state of the DCD0pin can be read as bit 2 of the STAT0
register, and that of CTS0in bit 5 of CNTLB0. Both bits read as 1if the pin is
High/Inactive.
Bit 6 in Extension Control register 0controls whether DCD0automatically
enables and disables the receiver, while bit 5 controls whether CTS0automati-
cally enables and disables the transmitter. In each case, if one of these ASEXT bits
is 0, as it is after a Reset, then a Low on the pin allows the module to operate. A
High disables the module. If an ASEXT bit is 1, software can still read the state of
the corresponding pin, but this state does not affect the hardware.
When ASEXT0 bit 6is 0, a High on DCD0forces the status bits RDRF, PE, FE,
OVRN, and RxBreakto 0. If DCD0goes Low thereafter, the next read of the
STAT register still indicates a 1in bit 2 (DCD0). Subsequent reads of STAT indi-
cates current status.
When ASEXT0 bit 5 is 0, a High on CTS0clears the TDRE bit in STAT. This
prevents software or a DMA channel from putting further Tx data into TDR, but
as many as three characters (one from the Tx shift register, two from the 2-stage
Tx FIFO) can still come out on TDA0after CTS0goes High.
&/#ꢁ1RGTCVKQP
On the Z80S188, data can be transferred to or from either ASCI by either DMA
channel. Setting up for such operation is covered in the following ASCI and DMA
topics:
“Starting a Transmitter”(below)
“Starting a Receiver”, on page 102
“Handling ASCI Interrupts”, on page 103
“Setting Up a DMA Transfer”, on page 60.
A DMA channel used with an ASCI transmitter must be programmed to use the
appropriate TDRE flag as its DMA request, and must be set up for edge-sensitive
DMA request.
A DMA channel used with an ASCI receiver must be programmed to use the
appropriate RDRF flag as its DMA request, and can be used in either edge- or
level-sensitive mode. In this application, software must set both RIEin the STAT
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register, and bit 7 of the Extension Control register to v, to enable ASCI receive
interrupts in case of errors, but not for each received character.
0
ꢊ The signal that an ASCI receiver provides as a Request to a DMA
channel, is not simply RDRF but rather RDRF and not PE and not FE and not
OVRN and not RxBreak. DMA operation is suspended if one of these errors or
exceptional conditions occurs, so that software can determine the point in the
receive data stream at which the error or condition occurred.
2TQITCOOKPIꢁ6GEJPKSWGU
5VCTVKPIꢁCꢁ6TCPUOKVVGTꢅꢁSoftware can enable a transmitter at the same time as its
associated receiver, or separately, as follows:
1. Write the CNTLB register to set up the clocking and basic options.
2. Write the Extension Control register, if necessary, to select the X1 and BRG
modes and, on ASCI0, the mode of the CTS0pin.
3. Set bit 0 (TIE) in the STAT register to 1if Transmit Interrupts are desired,
otherwise, clear it to 0.
4. Write the CNTLA register with a 1in bit 5 to enable the transmitter, as well as
other desired mode settings.
The TDRE flag is set immediately. If Transmit Interrupts were enabled in step 3,
an interrupt occurs immediately.
0
ꢊ If a DMA channel provides data to the transmitter, it can be set up when-
ever transmit data is available, including selecting TDREas its DMA Request.
Edge-sensitivity is required on the DMA request for transmit/output devices. If
TDREis set before the DMA channel is started, device software must set up the
DMA to not include the first Tx character. It then writes the first character to the
TDR, to prime the ASCI-DMA handshake.
5VCTVKPIꢁCꢁ4GEGKXGTꢅꢁSoftware can enable a receiver at the same time as its asso-
ciated transmitter, or separately, as follows:
1. Write the CNTLB register to set up the clocking and basic options.
2. Write the Extension Control register, if necessary, to select the X1 and BRG
modes and, on ASCI0, the mode of the DCD0 pin. If the receiver is to be
handled by a DMA channel, set bit 7 of the Extension Control register to block
the RDRFflag from requesting a receive interrupt.
3. Set bit 3 (RIE) in the STAT register to 1if receive interrupts are desired, else
clear it to 0.
4. Set up the receiver, if the receiver is to be handled by a DMA channel,
including selecting RDRFas the DMA Request signal.
5. Write the CNTLA register with a 1in bit 6 to enable the receiver, as well as
other desired mode settings.
6. RDRFis set when there is data in the Rx FIFO, and if RDRFinterrupts are
enabled, an interrupt occurs at that time.
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2QNNGFꢁ6TCPUOKUUKQPꢅꢁWhen a transmitter is started without interrupts enabled,
software must:
1. Read the STAT register (preferably more often than once per character time)
until bit 1 (TDRE) set to 1is detected.
2. Write the next character to be transmitted to the TDR. If there is more data to
send, return to step 1.
2QNNGFꢁ4GEGRVKQPꢅꢁOnce it has started a receiver without interrupt enabled, soft-
ware must:
1. Read the STAT register, at least once per character time, until bit 7 (RDRF) set
to 1is detected.
2. Read a received character from the RDR.
3. Process that character, then return to step 1.
*CPFNKPIꢁ#5%+ꢁ+PVGTTWRVUꢅꢁAs noted above, software can output to an ASCI in
interrupt-driven mode by setting bit 0 (TIE) in the STAT register, and/or can input
from an ASCI in interrupt-driven mode by setting bit 3 (RIE) in STAT. If any of
following are true, an ASCI requests an interrupt from the processor.
TIEand TDREare both 1,
RIEis 1and any of OVRN, PE, FE, or RxBreak(ASEXT bit 1) are 1,
RIEis 1, bit 7 of the Extension Control register is 0, and RDRFis 1, or
For ASCI0, RIEis 1, bit 6 in the Extension Control register is 0, and the DCD0
pin is High.
When the conditions listed in “On-Chip Interrupt Handling”, on page 29 are met
with respect to an ASCI’s interrupt request, the processor fetches the address of
the Interrupt Service Routine (ISR) from (I : IL : 14) for ASCI0, or from
(I : IL : 16) for ASCI1.
An ASCI ISR that handles both kinds of interrupts must:
1. Save as many registers as it may use, by means of PUSH, EX AF,AF’, and/or
EXX instructions.
2. Read the STAT register for this ASCI.
3. If TIEand TDREin STAT are both 1:
a. If Another Transmit character is available, write it to the TDR
b. If Not, clear the TIE bit until another Tx character is available.
4. If RIEin STAT is 1and any of OVRN, PE, FE, or RxBreak(ASEXT bit 1)
are 1:
a. If bit 7 of the Extension Control register is 1, indicating that a DMA
channel is handling receive data, read the DSTAT register, clear the DE
and DWE bits for that DMA channel, and write the result back to DSTAT.
b. Read the CNTLA register, clear bit 3 (EFR) and write the result back to
CNTLA,
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c. Read the associated character from the RDR,
d. For PEor FEconditions, applications can choose to discard the character,
replace it with a standard error character, or simply handle it like other
characters,
e. For OVRN (without any other error), most applications process this last
good character, as in step 5. An application may then post an overrun
occurred here notification in the received data stream, or otherwise deal
with the situation.
f. For Break, most applications discard the all-0 character. An application
may post a break occurred here notification in the received data stream.
The receiver does not assemble more all-0 characters, but waits for RDA
to go High before searching for a new Start bit.
5. Read the next received character from the RDR, if no errors were found in step
4, but RIEis 1, bit 7 of the Extension Control register is 0, and RDRFis 1.
Process that character, of which the simplest case is storing it at the next
memory location in a buffer.
6. If for ASCI0, RIEis 1, bit 6 in the Extension Control register is 0, and bit 2
of STAT is 1, carrier has been lost, and the ASCI receiver is inactive until it
returns. In this case, software may either clear RIEto 0, or set bit 6 in the
Extension Control register, to prevent further interrupts because DCD0 is
High.
7. Software can now read STAT again, and return to step 3 if either RIEand
RDRFare both 1, or TIEand TDREare both 1. (This routine saves interrupt
overhead.)
8. If the ISR disabled the receive DMA channel in step 4a, the ISR restarts the
channel.
9. Finally, the ISR restores the saved registers, and return to the interrupted
process by means of EI and RET instructions.
/WNVKRTQEGUUQTꢁ/QFG
In this mode, the transmitter sends, and the receiver expects, an extra bit between
the data and stop bits, that differentiates address from data characters. Other
manufacturers’ devices have a similar mode called 9-bit mode. To enable this
mode for both the transmitter and receiver, software sets bit 6 of the CNTLB
register to 1as part of initializing the ASCI.
0
ꢊ MULTIPROCESSOR mode cannot be used with parity generation and
checking.
In Multiprocessor mode, data is grouped into frames or messages, each preceded
by an address character, which differs from data characters in that the extra bit is
1.
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To send a frame in MULTIPROCESSOR mode, software must:
1. Wait, if necessary, for the TDREbit (bit 1 of the STAT register) to become 1,
indicating that software can write a new Tx character to the TDR. The next two
steps can be done in an ASCI Interrupt Service Routine.
2. Read the CNTLB register, set bits 7–6 to 11, and write the result back to
CNTLB. This routine sets up the transmitter to send the first character of the
frame with the extra bit 1.
3. Write the address value for the intended destination device to the TDR.
4. For each data character in the frame, again wait, if necessary for the TDREbit
(bit 1 of the STAT register) to be 1. The following two steps can be
implemented in an ASCI ISR.
5. Read CNTLB, clear bit 7, and write the result back. This routine causes the
transmitter to send the next character with the extra bit 0.
6. Write the next data character to the TDR. If there are more characters in the
frame, return to step 4.
Assuming that bit 6 of CNTLB was set to 1during ASCI initialization, to receive
a frame in Multiprocessor mode software must:
1. Read CNTLA, set bit 7, and write the result back to CNTLA. This routine
causes the receiver to ignore data characters, that have a 0in their extra bit.
2. Wait for the RDRFbit in the STAT register to be 1. The following steps can be
done in an ASCI interrupt service routine.
3. Read CNTLA and check that bit 3 is 1, verifying that the next available
character is indeed an address character. If not, read the RDR, discard the data
character, and return to step 2.
4. Read the RDR and check if the value obtained indicates a frame destined for
this processor. (Some schemes use a unique address for each node, plus
broadcast and/or group addresses.) If not, discard the character and return to
step 2. The hardware ignores the data characters in the frame.
5. Store the address character in memory (this action is optional). The required
actions may vary depending on the address.
6. Read CNTLA, clear bit 7, and write the result back to CNTLA. This routine
causes the receiver assemble the following data characters.
7. Wait for the RDRFbit in the STAT register to be 1for each data character in
the frame. The following steps can be done in an ASCI interrupt service routine.
8. Read the data character from the RDR and store it in memory. If frames are not
fixed-length, software determines the frame length from its content. If the
frame is not complete, return to step 7.
9. Check for checking or validation information in the frame. Most protocols
specify that a receiver ignores a frame that does not pass checking/validation.
10. Process the frame based on its content. This routine is application-dependent.
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The CSI/O allows synchronous communication with serial memories, peripherals,
and other processors that include compatible interfaces. It is a half-duplex inter-
face that can send or receive 8-bit bytes, but not both simultaneously.
The CSI/O includes separate receive and transmit data pins, RXSand TXS, plus a
clock pin CKSthat can be either an input or an output. In either direction, CKSis
gated so that it switches only during active data characters on RXSand TXS.
The bit rate can be as much as PHI/20 for an internally generated clock, and even
faster with an externally-generated clock.
The CSI/O Control (CNTR) and Data (TRDR) registers are described in section
“Clocked Serial I/O (CSI/O) Registers”, on page 176.
%NQEMꢁ5GNGEVKQP
After Reset, bits 2–0 of the CNTR are 111, which conditions the CKSpin to be an
input. If this Z80S188 is to provide the clock to the other station(s), write bits 2–0
with one of the other values described in Table 22, to select by what factor the
CSI/O divides PHI to produce the clock it drives onto CKS.
6
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0
ꢊ Wait at least 1 bit time after the transmitter clears its TEbit, or the
receiver clears its REbit, before changing the baud rate.
1RGTCVKQP
The clock signal on CKSand the data signals on TXSand RXShave the same
basic relationship, regardless of whether this Z80S188 is driving or receiving the
clock on CKS, and regardless of whether it is sending on TXSor receiving on
RXS. Figure 23 illustrates this relationship, along with the operation of the flags in
the CNTR.
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CKS is High between bytes. The CSI/O operates as follows in the four possible
cases of clock and data sourcing:
1WVRWVꢁ%NQEMꢍꢁ1WVRWVꢁ&CVCꢅꢁAfter software writes a byte to be transmitted to the
TRDRand sets the TEbit in the CNTR, the CSI/O drives CKSLow, and shortly
thereafter drives the LS bit of the byte onto TXS. Thereafter it toggles CKSat the
selected clock rate, driving each next-more-significant bit shortly after each
falling edge on TXS, until it has driven the MS bit onto TXS. Thereafter the CSI/O
clears the TEbit and sets the EFbit in the CNTR. Driving CKSHigh thereafter,
completes the operation for this byte.
+PRWVꢁ%NQEMꢍꢁ1WVRWVꢁ&CVCꢅꢁSoftware must write the byte to be transmitted to the
TRDR, and then set the TEbit in the CNTR, before the external clock source drives
CKSLow for the first bit of the byte. The CSI/O waits for falling edges on CKS,
and after each such edge it drives a bit of the character onto TXS, starting with the
LS bit. After driving the MS bit onto TxS, the CSI/O clears the TEbit and sets the
EFbit in the CNTR.
1WVRWVꢁ%NQEMꢍꢁ+PRWVꢁ&CVCꢅꢁAfter software sets the REbit in the TRDR, the CSI/O
drives CKSLow, and thereafter toggles CKSat the selected clock rate, for a total
of 8 falling and 8 rising edges. The CSI/O samples one bit of the byte starting with
the LS bit at each rising edge on CKS. sampled into the TRDR, starting with the
LS bit. After sampling the MS bit, the CSI/O clears the REbit and sets the EFbit
in the CNTR.
+PRWVꢁ%NQEMꢍꢁ+PRWVꢁ&CVCꢅꢁSoftware must set the REbit in the CNTR, before the
external clock source drives CKSLow for the first bit of the byte. After each rising
edge on CKS, one bit of the byte is sampled starting with the LS bit. After
sampling the MS bit, the CSI/O clears the REbit and sets the EFbit in the CNTR.
6TCPUOKVVKPIꢁCꢁ$[VGꢅꢁBoth the TE and RE flags in the CNTR must be 0 before
software can send a(nother) byte. At that point, software must:
1. Write the (next) byte to be transmitted into the TRDR,
2. Write a 1to the TEbit (bit 4) in the CNTR, with the desired clock control value
in bits 2–0. If no interrupt is desired when the byte has been sent, write a 0in
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bit 6 (EIE) of this register. Otherwise, write a 1and set a Transmit flag for the
interrupt service routine.
3. If the transmit flag is cleared:
a. Read the TRDR.
b. Process the byte.
4GEGKXKPIꢁCꢁ$[VGꢅꢁBoth the TE and RE flags in the CNTR must be 0before soft-
ware can condition the CSI/O to receive a(nother) byte. At this point software
must:
1. Write a 1to the REbit (bit 5) in the CNTR, with the desired clock control value
in bits 2–0. For polled operation write a 0in bit 6 (EIE) of this value, else write
a 1and clear the Transmit flag for the Interrupt Service Routine.
2. For polled operation, read the CNTR, periodically or in a tight loop, until REis
0and EFis 1. For interrupt-driven operation, the following step is processed
in the interrupt service routine, as described in the next topic.
3. For polled operation, read the TRDRto acquire the byte and clear the EF flag.
If the sending station contains more data, return to step 1.
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when Z80S188 is sourcing CKS, because the remote station’s hardware may hang
in mid-byte. For operation with an external clock, software could perform this
action after a time-out period has expired, indicating that the remote station has
nothing more to send or cannot accept further data.
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If software sets bit 6 (EIE) of the CNTR at the start of an transmit or receive oper-
ation, then when the CSI/O completes the operation and sets the EFbit, the CSI/O
requests an interrupt from the processor. If the conditions listed in “On-Chip Inter-
rupt Handling”, on page 29 are met with respect to this request, the processor
responds by fetching the address of the CSI/O interrupt service routine (ISR) from
memory at address (I : IL : 12). This ISR must:
1. Save as many registers as it may use, by means of PUSH, EX AF,AF’, and/
or EXXinstructions.
2. Read the CNTR. If the EFbit is 0, the ISR may log this unknown interrupt
before restoring the registers and returning to the interrupted process with EI
and RETinstructions.
3. If the XMIT flag is cleared:
a. Read the TRDR to acquire the byte and clear the EFflag.
b. Process the byte.
c. If further reception is necessary, write a 1to REas in step 1 of “Receiving
a Byte” above.
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d. If there is data to be sent, write the first byte to the TRDR (this action clears
the EF flag) and then set TE in the CNTR, as in steps 1-2 of the
“Transmitting a Byte” section. Also, set the XMIT flag for the next
interrupt.
4. If the XMIT flag is set:
a. Write the next byte to the TRDR(this clears the EFflag).
b. Set TEin the CNTR, as in steps 1-2 of “Transmitting a Byte” above.
5. If there is data to be received, perform a dummy read of TRDRto clear the EF
flag, then write a 1to REas in step 1 of the section, “Receiving a Byte”. Also,
clear the XMIT flag.
6. If there is no other actions to be taken, perform a dummy read of TRDRto clear
the EFflag.
7. Restore the saved registers and return to the interrupted process using EI and
RET instructions.
+ꢋ1 4')+56'45
The registers that are integral to the processor and the programming model are
described in section “Processor Description”, on page 11. This chapter describes
the registers in I/O space that control the operation of the overall device and its
on-chip peripherals.
4')+56'45ꢁ57//#4;
I/O registers on the Z80S188 are divided into two classes, the 80180 registers, and
other on-chip registers.
The 80180 registers:
Are located at addresses between 0000Hand 003FG.
Can be relocated to 0040–007FHor 0080–00BFHif desired.
Must be accessed using IN0, OUT0, OTDM(R), and OTIM(R) instructions.
Require three clocks per I/O instruction.
Other on-chip registers:
If bit 7 of the Interrupt Priority Register is 1, are located at I/O addresses between
xxD0and xxFFH, and can be accessed using IN, OUT, IND(R), INI(R),
OUTD, OUTI, OTDR, and OTIRinstructions.
If bit 7 of the Interrupt Priority Register is 0, are located at I/O addresses between
00D0and 00FFH, and can be accessed using IN0, OUT0, OTDM(R), and
OTIM(R)instructions.
Require 4 clocks per I/O instruction.
The following table includes all on-chip registers in both classes. I/O addresses
not described are not used.
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See section “Interrupts”, on page 15, for more about these registers.
6
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QEEWTUꢄꢀ9TKVKPIꢀCꢀꢃꢀVQꢀVJKUꢀDKVꢀENGCTUꢀKVꢘꢀ
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4ꢋ9
4ꢋ9
4ꢋ9
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25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
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//7ꢀ4
6
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4ꢋ9
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ꢃꢃꢂꢂ 2+1ꢀ#$ꢅꢀ2+1ꢀ%&ꢅꢀ%6%ꢅꢀ5+1ꢀꢐNQYGUVꢑ
ꢃꢂꢃꢃ 5+1ꢅꢀ2+1ꢀ#$ꢅꢀ2+1ꢀ%&ꢅꢀ%6%ꢀꢐNQYGUVꢑ
ꢃꢂꢃꢂ %6%ꢅꢀ2+1ꢀ#$ꢅꢀ5+1ꢅꢀ2+1ꢀ%&ꢀꢐNQYGUVꢑ
ꢂꢃꢃꢃ 5+1ꢅꢀ2+1ꢀ#$ꢅꢀ%6%ꢅꢀ2+1ꢀ%&ꢀꢐNQYGUVꢑ
ꢂꢃꢃꢂ 2+1ꢀ#$ꢅꢀ%6%ꢅꢀ2+1ꢀ%&ꢅꢀ5+1ꢀꢐNQYGUVꢑ
ꢂꢃꢂꢃ 2+1ꢀ#$ꢅꢀ5+1ꢅꢀ2+1ꢀ%&ꢅꢀ%6%ꢀꢐNQYGUVꢑ
ꢂꢃꢂꢂ 2+1ꢀ#$ꢅꢀ%6%ꢅꢀ5+1ꢅꢀ2+1ꢀ%&ꢀꢐNQYGUVꢑ
ꢂꢂꢃꢃ 2+1ꢀ#$ꢅꢀ5+1ꢅꢀ%6%ꢅꢀ2+1ꢀ%&ꢀꢐNQYGUVꢑ
ꢂꢂꢃꢂ
//7ꢁ4')+56'45
See section “Memory Management Unit (MMU)”, on page 31, for more about
these registers.
6
ꢁꢌꢌꢅ %
ꢁ$
ꢁ4
ꢁꢈꢃꢃꢌꢂ*ꢁ ꢁ%
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4ꢋ9
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4ꢋ9
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0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
ꢂꢂꢇ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
//7ꢀ4
+ꢋ1 4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ %QOOQPꢀꢂꢀ 4ꢋ9
#TGCꢀ$CUG
+HꢀVJGꢀEQORCTKUQPꢀQHꢀDKVUꢀꢂꢆꢌꢂꢎꢀQHꢀCꢀ
NQIKECNꢀCFFTGUUꢀKPFKECVGUꢀVJCVꢀVJGꢀ
CFFTGUUꢀKUꢀKPꢀ%QOOQPꢀ#TGCꢀꢂꢅꢀVJKUꢀ
XCNWGꢀꢐUJKHVGFꢀNGHVꢀꢂꢎꢀDKVUꢅꢀVKOGUꢀꢉꢃꢁꢏꢑꢀ
KUꢀCFFGFꢀVQꢀVJGꢀNQIKECNꢀCFFTGUUꢀVQꢀ
HQTOꢀVJGꢀRJ[UKECNꢀCFFTGUUꢄ
6
ꢁꢌꢎꢅ $
ꢁ$
ꢁ4
ꢁꢈꢃꢃꢌ*ꢓꢁ ꢁ%
ꢁ/
ꢉꢁ$$4
$KV
ꢍ
ꢃ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
ꢃ
ꢃ
$KVꢋ(KGNF
4ꢋ9
$CUGꢀQHꢀ$CPMꢀ#TGC
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
$CPMꢀ#TGCꢀ
$CUG
4ꢋ9
+HꢀVJGꢀEQORCTKUQPꢀQHꢀDKVUꢀꢂꢆꢌꢂꢎꢀQHꢀCꢀ
NQIKECNꢀCFFTGUUꢀKPFKECVGUꢀVJCVꢀVJGꢀ
CFFTGUUꢀKUꢀKPꢀVJGꢀ$CPMꢀ#TGCꢅꢀVJKUꢀ
XCNWGꢀꢐUJKHVGFꢀNGHVꢀꢂꢎꢀDKVUꢅꢀVKOGUꢀꢉꢃꢁꢏꢑꢀ
KUꢀCFFGFꢀVQꢀVJGꢀNQIKECNꢀCFFTGUUꢀVQꢀ
HQTOꢀVJGꢀRJ[UKECNꢀCFFTGUUꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢂꢁ
+ꢋ1 4
//7ꢀ4
6
ꢁꢌꢏꢅ %
ꢋ$
ꢁ#
ꢁ4
ꢁꢈꢃꢃꢌ#*ꢁ ꢁ%
ꢁ/
ꢉꢁ%$#4
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
$CPMꢋ%QOOQPꢀꢂꢀ$QWPFCT[
4ꢋ9
%QOOQPꢀꢃꢋ$CPMꢀ$QWPFCT[
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢃ
ꢃ
ꢃ
ꢃ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢉ
ꢊꢌꢃ
0
$CPMꢋ
%QOOQPꢀꢂꢀ
$QWPFCT[
4ꢋ9
+HꢀDKVUꢀꢂꢆꢌꢂꢎꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀCTGꢀ
ITGCVGTꢀVJCPꢀQTꢀGSWCNꢀVQꢀVJKUꢀXCNWGꢅꢀ
VJGꢀCFFTGUUꢀKUꢀKPꢀ%QOOQPꢀ#TGCꢀꢂꢄ
%QOOQPꢀꢃꢋ 4ꢋ9
$CPMꢀ
$QWPFCT[
+HꢀDKVUꢀꢂꢆꢌꢂꢎꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀCTGꢀ
NGUUꢀVJCPꢀVJKUꢀXCNWGꢅꢀVJGꢀCFFTGUUꢀKUꢀKPꢀ
%QOOQPꢀ#TGCꢀꢃꢄ
ꢊꢁ+Pꢀ%NCUUKEꢀOQFGꢅꢀKHꢀDKVUꢀꢊꢌꢃꢀQHꢀVJKUꢀTGIꢀꢓꢀDKVUꢀꢂꢆꢌꢂꢎꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀꢓꢀDKVUꢀꢍꢌ
ꢉꢀQHꢀVJKUꢀTGIꢅꢀVJGꢀCFFTGUUꢀKUꢀKPꢀVJGꢀ$CPMꢀ#TGCꢄꢀ&QꢀPQVꢀRTQITCOꢀVJKUꢀTGIKUVGTꢀUQꢀVJCVꢀDKVUꢀ
ꢊꢌꢃꢀ ꢀDKVUꢀꢍꢌꢉꢄꢀ#NNꢀEQORCTKUQPUꢀCTGꢀWPUKIPGFꢄ
6
ꢁꢌꢐꢅ %
ꢁ$
ꢁ4
ꢁ. ꢁꢈꢃꢃꢌꢂ*ꢁ ꢁ'
ꢁ/
ꢉꢁ%$4.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%QOOQPꢀ#TGCꢀꢂꢀ$CUGꢀCFFTGUUꢅꢀDKVUꢀꢂꢆꢌꢂꢃ
4ꢋ9
4GUGTXGF
:
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢎ
%QOOQPꢀ
#TGCꢀꢂꢀ$CUGꢀ
#FFTGUUꢀꢂꢆꢌ
ꢂꢃ
4ꢋ9
+Pꢀ'ZVGPFGFꢀOQFGꢅꢀKHꢀVJGꢀEQORCTKUQPꢀ
QHꢀDKVUꢀꢂꢆꢌꢂꢃꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀKPFKꢌ
ECVGUꢀVJCVꢀVJGꢀCFFTGUUꢀKUꢀKPꢀ%QOOQPꢀ
#TGCꢀꢂꢅꢀVJKUꢀXCNWGꢀKUꢀCFFGFꢀVQꢀDKVUꢀꢂꢆꢌ
ꢂꢃꢀQHꢀVJGꢀNQIKECNꢀCFFTGUUꢀVQꢀHQTOꢀDKVUꢀ
ꢂꢆꢌꢂꢃꢀQHꢀVJGꢀRJ[UKECNꢀCFFTGUUꢄ
ꢂꢎꢃ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
//7ꢀ4
+ꢋ1 4
6
ꢁꢌꢑꢅ %
ꢁ$
ꢁ4
ꢁ* ꢁꢈꢃꢃꢌꢓ*ꢁ ꢁ'
ꢁ/
ꢉꢁ%$4*
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
ꢃ
$KVꢋ(KGNF 4GUGTXGF
%QOOQPꢀ#TGCꢀꢂꢀ$CUGꢀCFFTGUUꢅꢀDKVUꢀꢎꢎꢌꢂꢏ
4ꢋ9
4ꢋ9
4GUGV
0
:
:
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢎ
%QOOQPꢀ
#TGCꢀꢂꢀ$CUGꢀ
#FFTGUUꢀꢎꢎꢌ
ꢂꢏ
4ꢋ9
+Pꢀ'ZVGPFGFꢀOQFGꢅꢀKHꢀVJGꢀEQORCTKUQPꢀ
QHꢀDKVUꢀꢂꢆꢌꢂꢃꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀKPFKꢌ
ECVGUꢀVJCVꢀVJGꢀCFFTGUUꢀKUꢀKPꢀ%QOOQPꢀ
#TGCꢀꢂꢅꢀVJKUꢀXCNWGꢅꢀRNWUꢀVJGꢀECTT[ꢀHTQOꢀ
VJGꢀCFFKVKQPꢀQHꢀDKVUꢀꢂꢆꢌꢂꢃꢅꢀKUꢀWUGFꢀCUꢀ
DKVUꢀꢎꢎꢌꢂꢏꢀQHꢀVJGꢀRJ[UKECNꢀCFFTGUUꢄ
6
ꢁꢌꢂꢅ $
ꢁ#
ꢁ4
ꢁꢈꢃꢃꢌ#*ꢁ ꢁ'
ꢁ/
ꢉꢁ$#4
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%QOOQPꢀꢃꢋ$CPMꢀ#TGCꢀ$QWPFCT[ꢅꢀDKVUꢀꢂꢆꢌꢂꢃ
4ꢋ9
4GUGTXGF
:
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢎ
%QOOQPꢀꢃꢋ 4ꢋ9
+Pꢀ'ZVGPFGFꢀOQFGꢅꢀKHꢀDKVUꢀꢂꢆꢌꢂꢃꢀQHꢀCꢀ
NQIKECNꢀCFFTGUUꢀCTGꢀNGUUꢀVJCPꢀVJKUꢀ
XCNWGꢅꢀVJGꢀCFFTGUUꢀKUꢀKPꢀ%QOOQPꢀ
#TGCꢀꢃꢄ
$CPMꢀ#TGCꢀ
$QWPFCT[ꢀ
ꢂꢆꢌꢂꢃ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢎꢂ
+ꢋ1 4
//7ꢀ4
6
ꢁꢌꢓꢅ %
ꢁ#
ꢁ4
ꢁꢈꢃꢃꢌ$*ꢁ ꢁ'
ꢁ/
ꢉꢁ%#4
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
$CPMꢋ%QOOQPꢀꢂꢀ#TGCꢀ$QWPFCT[ꢅꢀDKVUꢀꢂꢆꢌꢂꢃ
4ꢋ9
4GUGTXGF
:
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢎ
%QOOQPꢀꢃꢋ 4ꢋ9
+Pꢀ'ZVGPFGFꢀOQFGꢅꢀKHꢀDKVUꢀꢂꢆꢌꢂꢃꢀQHꢀCꢀ
NQIKECNꢀCFFTGUUꢀCTGꢀITGCVGTꢀVJCPꢀQTꢀ
GSWCNꢀVQꢀVJKUꢀXCNWGꢅꢀVJGꢀCFFTGUUꢀKUꢀKPꢀ
%QOOQPꢀ#TGCꢀꢂꢄ
$CPMꢀ#TGCꢀ
$QWPFCT[ꢀ
ꢂꢆꢌꢂꢃ
0
ꢊꢁ+Pꢀ'ZVGPFGFꢀOQFGꢅꢀKHꢀDKVUꢀꢍꢌꢎꢀQHꢀVJGꢀ$#4ꢀꢓꢀDKVUꢀꢂꢆꢌꢂꢎꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀꢓꢀDKVUꢀ
ꢍꢌꢎꢀQHꢀVJKUꢀTGIꢅꢀVJGꢀCFFTGUUꢀKUꢀKPꢀVJGꢀ$CPMꢀ#TGCꢄꢀ&QꢀPQVꢀRTQITCOꢀVJGUGꢀTGIKUVGTUꢀUQꢀVJCVꢀ
DKVUꢀꢍꢌꢎꢀQHꢀVJGꢀ$#4ꢀ ꢀDKVUꢀꢍꢌꢎꢀQHꢀVJKUꢀTGIKUVGTꢄꢀ#NNꢀEQORCTKUQPUꢀCTGꢀWPUKIPGFꢄ
6
ꢁꢎꢃꢅ $
ꢁ$
ꢁ4
ꢁ. ꢁꢈꢃꢃꢌ%*ꢁ ꢁ'
ꢁ/
ꢉꢁ$$4.
$KV
ꢍ
ꢃ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
$CPMꢀ#TGCꢀ$CUGꢀCFFTGUUꢅꢀDKVUꢀꢂꢆꢌꢂꢃ
4ꢋ9
4GUGTXGF
:
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢎ
$CPMꢀ#TGCꢀ
$CUGꢀ
#FFTGUUꢀꢂꢆꢌ
ꢂꢃ
4ꢋ9
+Pꢀ'ZVGPFGFꢀOQFGꢅꢀKHꢀVJGꢀEQORCTKUQPꢀ
QHꢀDKVUꢀꢂꢆꢌꢂꢃꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀKPFKꢌ
ECVGUꢀVJCVꢀVJGꢀCFFTGUUꢀKUꢀKPꢀVJGꢀ$CPMꢀ
#TGCꢅꢀVJKUꢀXCNWGꢀKUꢀCFFGFꢀVQꢀDKVUꢀꢂꢆꢌꢂꢃꢀ
QHꢀVJGꢀNQIKECNꢀCFFTGUUꢀVQꢀHQTOꢀDKVUꢀꢂꢆꢌ
ꢂꢃꢀQHꢀVJGꢀRJ[UKECNꢀCFFTGUUꢄ
ꢂꢎꢎ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
%
ꢀ5
ꢀ
ꢀ9 ꢀ4
+ꢋ1 4
6
ꢁꢎꢄꢅ $
ꢁ$
ꢁ4
ꢁ* ꢁꢈꢃꢃꢌ&*ꢁ ꢁ'
ꢁ/
ꢉꢁ$$4*
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
ꢃ
$KVꢋ(KGNF 4GUGTXGF
$CPMꢀ#TGCꢀ$CUGꢀCFFTGUUꢅꢀDKVUꢀꢎꢎꢌꢂꢏ
4ꢋ9
4ꢋ9
4GUGV
0
:
:
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢎ $CPMꢀ#TGCꢀ
4ꢋ9
+Pꢀ'ZVGPFGFꢀOQFGꢅꢀKHꢀVJGꢀEQORCTKUQPꢀ
QHꢀDKVUꢀꢂꢆꢌꢂꢃꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀKPFKꢌ
ECVGUꢀVJCVꢀVJGꢀCFFTGUUꢀKUꢀKPꢀ%QOOQPꢀ
#TGCꢀꢂꢅꢀVJKUꢀXCNWGꢅꢀRNWUꢀVJGꢀECTT[ꢀHTQOꢀ
VJGꢀCFFKVKQPꢀQHꢀDKVUꢀꢂꢆꢌꢂꢃꢅꢀKUꢀWUGFꢀCUꢀ
DKVUꢀꢎꢎꢌꢂꢏꢀQHꢀVJGꢀRJ[UKECNꢀCFFTGUUꢄ
$CUGꢀ
#FFTGUUꢀꢎꢎꢌ
ꢂꢏ
%*+2ꢁ5'.'%6ꢁ#0&ꢁ9#+6ꢁ4')+56'45
See pages 34 and 39 for more detail about these registers.
6
ꢁꢎꢆꢅ
ꢁ% ꢁ5
ꢁꢃꢁ. ꢁ4
ꢁꢈ (ꢐꢁ ꢁꢃꢃ(*ꢐꢉꢁ/%5ꢃ.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
5K\Gꢋ'PCDNG
4ꢋ9
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%#ꢂꢉꢌꢂꢊ
4ꢋ9
9CKVꢀ5VCVGU
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢂ
ꢃ
ꢃ
ꢂ
ꢂ
ꢂ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢎꢊ
+ꢋ1 4
%
ꢀ5
ꢀ
ꢀ9 ꢀ4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢏ
%QORCTKUQPꢀ 4ꢋ9
#FFTGUU
ꢂꢉꢌꢂꢊ
6JGꢀ5K\Gꢋ'PCDNGꢀHKGNFꢀEQPVTQNUꢀYJGVJGTꢀ
VJGUGꢀDKVUꢀCTGꢀEQORCTGFꢀHQTꢀGSWCNKV[ꢀVQꢀ
#ꢂꢉꢌꢂꢊꢄ
ꢆꢌꢎ
5K\Gꢋ'PCDNG
4ꢋ9 ꢃꢃꢃꢃ MEMCS0 is disabled (remains High).
ꢃꢃꢃꢂ MEMCS0 Low for all of memory
ꢃꢃꢂꢃ MEMCS0 Low when A22==CA22
ꢃꢃꢂꢂ MEMCS0 Low when A22-21==CA22-21
ꢃꢂꢃꢃ MEMCS0 Low when A22-20==CA22-20
ꢃꢂꢃꢂ MEMCS0 Low when A22-19==CA22-19
ꢃꢂꢂꢃ MEMCS0 Low when A22-18==CA22-18
ꢃꢂꢂꢂ MEMCS0 Low when A22-17==CA22-17
ꢂꢃꢃꢃ MEMCS0 Low when A22-16==CA22-16
ꢂꢃꢃꢂ MEMCS0 Low when A22-15==CA22-15
ꢂꢃꢂꢃ MEMCS0 Low when A22-14==CA22-14
ꢂꢃꢂꢂ MEMCS0 Low when A22-13==CA22-13
ꢂꢂZZ Reserved; do not program these values
ꢂꢌꢃ
9CKVꢀ5VCVGU 4ꢋ9 ꢃꢃ 0QꢀYCKVꢀUVCVGUꢀCFFGFꢀKPꢀ/'/%5ꢃꢀTCPIG
#VꢀNGCUVꢀꢂꢀYCKVꢀUVCVGꢀKPꢀ/'/%5ꢃꢀTCPIG
ꢃꢂ #VꢀNGCUVꢀꢎꢀYCKVꢀUVCVGUꢀKPꢀ/'/%5ꢃꢀTCPIG
#VꢀNGCUVꢀꢊꢀYCKVꢀUVCVGUꢀKPꢀ/'/%5ꢃꢀTCPIG
ꢂꢃ
ꢂꢂ
ꢂꢎꢉ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
%
ꢀ5
ꢀ
ꢀ9 ꢀ4
+ꢋ1 4
6
ꢁꢎꢌꢅ /
ꢁ% ꢁ5
ꢁꢃꢁ* ꢁ4
ꢁꢈ (ꢑꢁ ꢁꢃꢃ(ꢑ*ꢉꢁ/%5ꢃ*
$KV
ꢍ
ꢃ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%QORCTKUQPꢀ#FFTGUUꢀꢎꢎꢌꢂꢆ
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
4ꢋ9 6JGꢀ5K\Gꢋ'PCDNGꢀHKGNFꢀKPꢀ/%5ꢃ.ꢀ
ꢍꢌꢃ
%QORCTꢌ
KUQPꢀ
#FFTGUUꢀꢎꢎꢌ
ꢂꢆ
EQPVTQNUꢀJQYꢀOCP[ꢀQHꢀVJGUGꢀDKVUꢀCTGꢀ
EQORCTGFꢀHQTꢀGSWCNKV[ꢀVQꢀ#ꢎꢎꢌꢂꢆꢄ
6
ꢁꢎꢎꢅ /
ꢁ% ꢁ5
ꢁꢄꢁ. ꢁ4
ꢁꢈ (ꢂꢁ ꢁꢃꢃ(ꢂ*ꢉꢁ/%5ꢄ.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%#ꢂꢉꢌꢂꢊ
4ꢋ9
5K\Gꢋ'PCDNG
4ꢋ9
9CKVꢀ5VCVGU
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢂ
ꢂ
ꢂ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
4ꢋ9 6JGꢀ5K\Gꢋ'PCDNGꢀHKGNFꢀEQPVTQNUꢀ
ꢍꢌꢏ
%QORCTꢌ
KUQPꢀ
YJGVJGTꢀVJGUGꢀDKVUꢀCTGꢀEQORCTGFꢀHQTꢀ
GSWCNKV[ꢀVQꢀ#ꢂꢉꢌꢂꢊꢄ
#FFTGUUꢀꢂꢉꢌ
ꢂꢊ
ꢆꢌꢎ
5K\Gꢋ'PCDNG
4ꢋ9 ꢃꢃꢃꢃ MEMCS1 is disabled (remains High)
ꢃꢃꢃꢂ MEMCS1 Low for all memory (see note)
ꢃꢃꢂꢃ MEMCS1 Low when A22==CA22
ꢃꢃꢂꢂ MEMCS1 Low when A22-21==CA22-21
ꢃꢂꢃꢃ MEMCS1 Low when A22-20==CA22-20
ꢃꢂꢃꢂ MEMCS1 Low when A22-19==CA22-19
ꢃꢂꢂꢃ MEMCS1 Low when A22-18==CA22-18
ꢃꢂꢂꢂ MEMCS1 Low when A22-17==CA22-17
ꢂꢃꢃꢃ MEMCS1 Low when A22-16==CA22-16
ꢂꢃꢃꢂ MEMCS1 Low when A22-15==CA22-15
ꢂꢃꢂꢃ MEMCS1 Low when A22-14==CA22-14
ꢂꢃꢂꢂ MEMCS1 Low when A22-13==CA22-13
ꢂꢂZZ Reserved; do not program these values
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢎꢆ
+ꢋ1 4
%
ꢀ5
ꢀ
ꢀ9 ꢀ4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢂꢌꢃ
9CKVꢀ5VCVGU 4ꢋ9
ꢃꢃ 0QꢀYCKVꢀUVCVGUꢀCFFGFꢀKPꢀ/'/%5ꢂꢀ
TCPIG
ꢃꢂ #VꢀNGCUVꢀꢂꢀYCKVꢀUVCVGꢀKPꢀ/'/%5ꢂꢀTCPIG
#VꢀNGCUVꢀꢎꢀYCKVꢀUVCVGUꢀKPꢀ/'/%5ꢂꢀ
ꢂꢃ TCPIG
#VꢀNGCUVꢀꢊꢀYCKVꢀUVCVGUꢀKPꢀ/'/%5ꢂꢀ
ꢂꢂ TCPIG
0
ꢊꢁ+HꢀVJGꢀTCPIGUꢀHQTꢀ/'/%5ꢃꢀCPFꢀ/'/%5ꢂꢀQXGTNCRꢅꢀ/'/%5ꢃꢀIQGUꢀ.QYꢀCPFꢀ
/'/%5ꢂꢀTGOCKPUꢀ*KIJꢀHQTꢀCFFTGUUGUꢀKPꢀVJGꢀQXGTNCRRGFꢀTGIKQPꢄ
6
ꢁꢎꢏꢅ /
ꢁ% ꢁ5
ꢁꢄꢁ* ꢁ4
ꢁꢈ (ꢓꢁ ꢁꢃꢃ(ꢓ*ꢉꢁ/%5ꢄ*
$KV
ꢍ
ꢃ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%QORCTKUQPꢀ#FFTGUUꢀꢎꢎꢌꢂꢆ
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
4ꢋ9 6JGꢀ5K\Gꢋ'PCDNGꢀHKGNFꢀKPꢀ/%5ꢂ.ꢀ
ꢍꢌꢃ
%QORCTꢌ
KUQPꢀ
#FFTGUUꢀꢎꢎꢌ
ꢂꢆ
EQPVTQNUꢀJQYꢀOCP[ꢀQHꢀVJGUGꢀDKVUꢀCTGꢀ
EQORCTGFꢀHQTꢀGSWCNKV[ꢀVQꢀ#ꢎꢎꢌꢂꢆꢄ
ꢂꢎꢏ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
%
ꢀ5
ꢀ
ꢀ9 ꢀ4
+ꢋ1 4
6
ꢁꢎꢐꢅ +ꢋ1ꢁ% ꢁ5
ꢁ. ꢁ4
ꢁꢈ (#ꢁ ꢁꢃꢃ(#*ꢉꢁ+1%5.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
%#ꢍꢌꢆ
%QOR
*K
5K\G
4ꢋ9
9CKVꢀ5VCVGU
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢂ
ꢂ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢆ
%QORCTKUQPꢀ 4ꢋ9
6JGꢀ5K\GꢀHKGNFꢀEQPVTQNUꢀJQYꢀOCP[ꢀQHꢀ
VJGUGꢀDKVUꢀCTGꢀEQORCTGFꢀHQTꢀGSWCNKV[ꢀ
VQꢀ#ꢍꢌꢆꢄ
#FFTGUUꢀꢍꢌꢆ
%QOR*K
5K\G
ꢉ
4ꢋ9
4ꢋ9
ꢃ
ꢂ
+1%5ꢀFGEQFKPIꢀKIPQTGUꢀ#ꢂꢆꢌꢇ
+1%5ꢀ.QYꢀTGSWKTGUꢀ#ꢂꢆꢌꢇꢒꢒ%#ꢂꢆꢌꢇ
ꢊꢌꢎ
ꢃꢃ +1%5ꢀFQGUꢀPQVꢀFGEQFGꢀ#ꢍꢌꢆꢀꢐUGGꢀPQVGꢑ
ꢃꢂ +1%5ꢀ.QYꢀTGSWKTGUꢀ#ꢍꢒꢒ%#ꢍ
ꢂꢃ +1%5ꢀ.QYꢀTGSWKTGUꢀ#ꢍꢌꢏꢒꢒ%#ꢍꢌꢏ
ꢂꢂ +1%5ꢀ.QYꢀTGSWKTGUꢀ#ꢍꢌꢆꢒꢒ%#ꢍꢌꢆ
ꢂꢌꢃ
9CKVꢀ5VCVGU
4ꢋ9
ꢃꢃ /KPꢀꢉꢀENQEMUꢋE[ENGꢀKPꢀ+1%5ꢀTCPIG
ꢃꢂ /KPꢀꢆꢀENQEMUꢋE[ENGꢀKPꢀ+1%5ꢀTCPIG
ꢂꢃ /KPꢀꢏꢀENQEMUꢋE[ENGꢀKPꢀ+1%5ꢀTCPIG
ꢂꢂ /KPꢀꢍꢀENQEMUꢋE[ENGꢀKPꢀ+1%5ꢀTCPIG
0
ꢊꢁ+1%5ꢀCNYC[UꢀTGOCKPUꢀ*KIJꢀHQTꢀQPꢌEJKRꢀ+ꢋ1ꢀCFFTGUUGUꢄ
6
ꢁꢎꢑꢅ +ꢋ1ꢁ% ꢁ5
ꢁ* ꢁ4
ꢁꢈ ($ꢁ ꢁꢃꢃ($*ꢉꢁ+1%5*
$KV
ꢍ
ꢏ
ꢃ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%QORCTKUQPꢀ#FFTGUUꢀꢂꢆꢌꢇ
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
%QORCTꢌ
KUQPꢀ
#FFTGUUꢀꢂꢆꢌ
ꢇ
4ꢋ9
6JGꢀ%QOR*KꢀDKVꢀKPꢀ+1%5.ꢀEQPVTQNUꢀ
YJGVJGTꢀVJGUGꢀDKVUꢀCTGꢀEQORCTGFꢀHQTꢀ
GSWCNKV[ꢀVQꢀ#ꢂꢆꢌꢇꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢎꢍ
+ꢋ1 4
+ꢋ1ꢀ2
ꢀꢐ2+1ꢑꢀ4
+ꢋ1ꢁ2146ꢁꢈ2+1ꢉꢁ4')+56'45
See section “Parallel I/O (PIOs)”, on page 45, for more about these registers.
6
ꢁꢎꢂꢅ 2 ꢁ#ꢁ& ꢁꢈ &%ꢁ ꢁꢃꢃ&%*ꢉꢁ2#&
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
2QTVꢀ#ꢀ&CVC
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
2QTVꢀ#ꢀ&CVC 4ꢋ9
9TKVKPIꢀVQꢀVJKUꢀCFFTGUUꢀUGVUꢀQWVRWVꢀ
FCVCꢀHQTꢀVJGꢀ2#ꢍꢌꢃꢀRKPUꢅꢀCPFꢀKPꢀOQFGꢀ
ꢃꢀQTꢀꢎꢀOCMGUꢀ#4&;ꢀ*KIJꢄꢀ4GCFKPIꢀ
HTQOꢀVJKUꢀCFFTGUUꢀTGVWTPUꢀKPRWVꢀFCVCꢀ
HTQOꢀVJGꢀ2#ꢍꢌꢃꢀRKPUꢅꢀCPFꢀKPꢀOQFGꢀꢂꢀ
QTꢀꢎꢀOCMGUꢀ#4&;ꢀQTꢀ$4&;ꢀꢐTGURGEꢌ
VKXGN[ꢑꢀ*KIJꢄ
6
ꢁꢎꢓꢅ 2
ꢁ#ꢁ%
ꢁꢈ &&ꢁ ꢁꢃꢃ&&*ꢉꢁ2#%
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
2QTVꢀ#ꢀ%QPVTQN
91
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
$KVꢋ
2QUKVKQP (KGNF
ꢍꢌꢃ 2QTVꢀ#
%QPVTQN
4ꢋ9
8CNWG
&GUETKRVKQP
91
6JGꢀRQTVꢀFGEQFGUꢀVJGꢀ.5ꢀDKVUꢀQHꢀFCVCꢀ
YTKVVGPꢀVQꢀVJKUꢀCFFTGUUꢅꢀVQꢀUGNGEVꢀ
COQPIꢀVJGꢀHQNNQYKPIꢀEQPVTQNꢀYQTFUꢈ
+PVGTTWRVꢁ8GEVQTꢁ9QTFꢅꢀ6JGꢀRQTVꢀ
XXXXXXXꢃ TGVWTPUꢀVJKUꢀXCNWGꢀCUꢀCPꢀKPVGTTWRVꢀ
XGEVQTꢄ
+PVGTTWRVꢁ&KUCDNGꢁ9QTFꢅꢀ$KVꢀꢍꢀGPCDNGUꢀ
GZZZꢃꢃꢂꢂ ꢐꢂꢑꢀQTꢀFKUCDNGUꢀꢐꢃꢑꢀRQTVꢀKPVGTTWRVUꢄ
+PVGTTWRVꢁ%QPVTQNꢁ9QTFꢅꢀ$KVꢀꢍꢀGPCDNGUꢀ
ꢐꢂꢑꢀQTꢀFKUCDNGUꢀꢐꢃꢑꢀRQTVꢀKPVGTTWRVUꢄꢀ
GCJOꢃꢂꢂꢂ ꢐ%QPVKPWGFꢑ
ꢂꢎꢇ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
+ꢋ1ꢀ2
ꢀꢐ2+1ꢑꢀ4
+ꢋ1 4
$KV
$KVꢋ
2QUKVKQP (KGNF
4ꢋ9
8CNWG
&GUETKRVKQP
ꢍꢌꢃ
2QTVꢀ#
91
+PꢀOQFGꢀꢊꢀQPN[ꢅꢀDKVꢀꢆꢀEQPVTQNUꢀ
YJGVJGTꢀRKPUꢀUGNGEVGFꢀD[ꢀꢂUꢀKPꢀVJGꢀ
OCUMꢀKPVGTTWRVꢀYJGPꢀ*KIJꢀꢐꢂꢑꢀQTꢀ.QYꢀ
ꢐꢃꢑꢅꢀDKVꢀꢏꢀEQPVTQNUꢀYJGVJGTꢀKPVGTTWRVꢀ
QEEWTUꢀYJGPꢀCNNꢀꢐꢂꢑꢀQTꢀCP[ꢀꢐꢃꢑꢀQHꢀVJGUGꢀ
RKPUꢀKUꢀKPꢀVJGꢀCEVKXGꢀUVCVGꢅꢀCPFꢀCꢀꢂꢀKPꢀ
DKVꢀꢉꢀKPFKECVGUꢀVJCVꢀVJGꢀPGZVꢀXCNWGꢀ
YTKVVGPꢀVQꢀVJKUꢀCFFTGUUꢀKUꢀCPꢀKPVGTTWRVꢀ
OCUMꢄ
ꢐEQPVꢄꢑ %QPVTQN
/QFGꢁ%QPVTQNꢁ9QTFꢅꢀ$KVUꢀꢍꢌꢏꢀUGNGEVꢀ
OOZZꢂꢂꢂꢂ VJGꢀRQTV UꢀQRGTCVKPIꢀOQFGꢈ
ꢃꢃꢀ1WVRWV
ꢃꢂꢀ+PRWV
ꢂꢃꢀ$KFKTGEVKQPCN
ꢂꢂꢀ$KVꢀ%QPVTQNꢄꢀ5GVVKPIꢀVJKUꢀXCNWGꢀCNUQꢀ
OCMGUꢀVJGꢀRQTVꢀECRVWTGꢀVJGꢀPGZVꢀ
XCNWGꢀYTKVVGPꢀVQꢀVJKUꢀCFFTGUUꢅꢀCUꢀCPꢀ+ꢋ
1ꢀ4GIKUVGTꢀ%QPVTQNꢀ9QTFꢅꢀKPꢀYJKEJꢀꢂUꢀ
KFGPVKH[ꢀKPRWVUꢀCPFꢀꢃUꢀKFGPVKH[ꢀ
QWVRWVUꢄ
6
ꢁꢏꢃꢅ 2
ꢁ$ꢁ&
ꢁꢈ &'ꢁ ꢁꢃꢃ&'*ꢉꢁ2$&
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
2QTVꢀ$ꢀ&CVC
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
2QTVꢀ$ꢀ&CVC
4ꢋ9
9TKVKPIꢀVQꢀVJKUꢀCFFTGUUꢀUGVUꢀQWVRWVꢀ
FCVCꢀHQTꢀVJGꢀ2$ꢍꢌꢃꢀRKPUꢅꢀCPFꢀKPꢀOQFGꢀ
ꢃꢀOCMGUꢀ$4&;ꢀ*KIJꢄꢀ4GCFKPIꢀHTQOꢀ
VJKUꢀCFFTGUUꢀTGVWTPUꢀKPRWVꢀFCVCꢀHTQOꢀ
VJGꢀ2$ꢍꢌꢃꢀRKPUꢅꢀCPFꢀKPꢀOQFGꢀꢂꢀOCMGUꢀ
$4&;ꢀ*KIJꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢎꢁ
+ꢋ1 4
+ꢋ1ꢀ2
ꢀꢐ2+1ꢑꢀ4
6
ꢁꢏꢄꢅ 2
ꢁ$ꢁ%
ꢁꢈ &(ꢁ ꢁꢃꢃ&(*ꢉꢁ2$%
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
2QTVꢀ$ꢀ%QPVTQN
91
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
$KVꢋ
2QUKVKQP (KGNF
4ꢋ9
8CNWG
&GUETKRVKQP
ꢍꢌꢃ
2QTVꢀ$
%QPVTQN
91
6JGꢀRQTVꢀFGEQFGUꢀVJGꢀ.5ꢀDKVUꢀQHꢀFCVCꢀ
YTKVVGPꢀVQꢀVJKUꢀCFFTGUUꢅꢀVQꢀUGNGEVꢀ
COQPIꢀVJGꢀHQNNQYKPIꢀEQPVTQNꢀYQTFUꢈ
+PVGTTWRVꢁ8GEVQTꢁ9QTFꢅꢀ6JGꢀRQTVꢀ
XXXXXXXꢃ TGVWTPUꢀVJKUꢀXCNWGꢀCUꢀCPꢀKPVGTTWRVꢀ
XGEVQTꢄ
+PVGTTWRVꢁ&KUCDNGꢁ9QTFꢅꢀ$KVꢀꢍꢀGPCDNGUꢀ
GZZZꢃꢃꢂꢂ ꢐꢂꢑꢀQTꢀFKUCDNGUꢀꢐꢃꢑꢀRQTVꢀKPVGTTWRVUꢄ
+PVGTTWRVꢁ%QPVTQNꢁ9QTFꢅꢀ$KVꢀꢍꢀGPCDNGUꢀ
ꢐꢂꢑꢀQTꢀFKUCDNGUꢀꢐꢃꢑꢀRQTVꢀKPVGTTWRVUꢄꢀ+Pꢀ
GCJOꢃꢂꢂꢂ OQFGꢀꢊꢀQPN[ꢅꢀDKVꢀꢆꢀEQPVTQNUꢀYJGVJGTꢀ
RKPUꢀUGNGEVGFꢀD[ꢀꢂUꢀKPꢀVJGꢀOCUMꢀ
KPVGTTWRVꢀYJGPꢀ*KIJꢀꢐꢂꢑꢀQTꢀ.QYꢀꢐꢃꢑꢅꢀ
DKVꢀꢏꢀEQPVTQNUꢀYJGVJGTꢀKPVGTTWRVꢀ
QEEWTUꢀYJGPꢀCNNꢀꢐꢂꢑꢀQTꢀCP[ꢀꢐꢃꢑꢀQHꢀVJGUGꢀ
RKPUꢀKUꢀKPꢀVJGꢀCEVKXGꢀUVCVGꢅꢀCPFꢀCꢀꢂꢀKPꢀ
DKVꢀꢉꢀKPFKECVGUꢀVJCVꢀVJGꢀPGZVꢀXCNWGꢀ
YTKVVGPꢀVQꢀVJKUꢀCFFTGUUꢀKUꢀCPꢀKPVGTTWRVꢀ
OCUMꢄ
/QFGꢁ%QPVTQNꢁ9QTFꢅꢀ$KVUꢀꢍꢌꢏꢀUGNGEVꢀ
VJGꢀRQTV UꢀQRGTCVKPIꢀOQFGꢈ
ꢃꢃꢀ1WVRWV
OOZZꢂꢂꢂꢂ ꢃꢂꢀ+PRWV
ꢂꢃꢀ&QꢀPQVꢀRTQITCO
ꢂꢂꢀ$KVꢀ%QPVTQNꢄꢀ
5GVVKPIꢀVJKUꢀXCNWGꢀCNUQꢀOCMGUꢀVJGꢀ
RQTVꢀECRVWTGꢀVJGꢀPGZVꢀXCNWGꢀYTKVVGPꢀVQꢀ
VJKUꢀCFFTGUUꢅꢀCUꢀCPꢀ+ꢋ1ꢀ4GIKUVGTꢀ
%QPVTQNꢀ9QTFꢅꢀKPꢀYJKEJꢀꢂUꢀKFGPVKH[ꢀ
KPRWVUꢀCPFꢀꢃUꢀKFGPVKH[ꢀQWVRWVUꢄ
ꢂꢊꢃ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
+ꢋ1ꢀ2
ꢀꢐ2+1ꢑꢀ4
+ꢋ1 4
6
ꢁꢏꢆꢅ 2
ꢁ%ꢁ&
ꢁꢈ &ꢎꢁ ꢁꢃꢃ&ꢎ*ꢉꢁ2%&
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
2QTVꢀ%ꢀ&CVC
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
0
ꢊ This address operates as described for Port A Data above, except that it is
associated with the PC7-0 and CRDY pins, and for mode 2 the DRDY pin.
6
ꢁꢏꢌꢅ 2 ꢁ%ꢁ% ꢁꢈ &ꢏꢁ ꢁꢃꢃ&ꢏ*ꢉꢁ2%%
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
2QTVꢀ%ꢀ%QPVTQN
91
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVGꢀ91ꢀꢒꢀ9TKVGꢀ1PN[
0
ꢊ This address operates as described for Port A Control above, except that it
is associated with the PC7-0 and CRDY pins, and for mode 2 the DRDY pin.
6
ꢁꢏꢎꢅ 2 ꢁ&ꢁ& ꢁꢈ &ꢐꢁ ꢁꢃꢃ&ꢐ*ꢉꢁ2&&
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
2QTVꢀ&ꢀ&CVC
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
0
ꢊ This address operates as described for Port B Data above, except that it is
associated with the PD7-0 pins, and in mode 0 or 1 the DRDY pin.
6
ꢁꢏꢏꢅ 2 ꢁ&ꢁ% ꢁꢈ &ꢑꢁ ꢁꢃꢃ&ꢑ*ꢉꢁ2&%
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
2QTVꢀ&ꢀ%QPVTQN
91
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVGꢀ91ꢀꢒꢀ9TKVGꢀ1PN[
0
ꢊ This address operates as described for Port B Control above, except that it
is associated with the PD7–0pins, and in mode 0 or 1 the DRDYpin
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢊꢂ
+ꢋ1 4
&/#ꢀ4
&/#ꢁ4')+56'45
See section “DMA Channels”, on page 57, for more about these registers.
6
ꢁꢏꢐꢅ &/#ꢃꢁ5
ꢁ#
ꢁ4
ꢁ. ꢁꢈꢃꢃꢆꢃ*ꢉꢁ5#4ꢃ.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀD[VGꢀQHꢀ&/#ꢃꢀ5QWTEGꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
&/#ꢃꢀ
5QWTEGꢀ
#FFTGUUꢀ.5ꢀ
D[VG
4ꢋ9
.5ꢀD[VGꢀQHꢀVJGꢀ5QWTEGꢀ#FFTGUUꢀHQTꢀ
&/#ꢀEJCPPGNꢀꢃꢄ
6
ꢁꢏꢑꢅ &/#ꢃꢁ5
ꢁ#
ꢁ4
ꢁ* ꢁꢈꢃꢃꢆꢄ*ꢉꢁ5#4ꢃ*
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
/KFFNGꢀD[VGꢀQHꢀ&/#ꢃꢀ5QWTEGꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
&/#ꢃꢀ
5QWTEGꢀ
4ꢋ9
$KVUꢀꢂꢆꢌꢇꢀQHꢀVJGꢀ5QWTEGꢀ#FFTGUUꢀHQTꢀ
&/#ꢀEJCPPGNꢀꢃꢄ
#FFTGUUꢀ
OKFFNGꢀD[VG
ꢂꢊꢎ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
&/#ꢀ4
+ꢋ1 4
6
ꢁꢏꢂꢅ &/#ꢃꢁ5
ꢁ#
ꢁ4
ꢁ$ꢁꢈꢃꢃꢆꢆ*ꢉꢁ5#4ꢃ$
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF 4GUGTX
GF
&/#ꢃꢀ5QWTEGꢀ#FFTGUUꢀꢎꢎꢌꢂꢏꢅꢀ14
0QVꢀWUGF &/#ꢀ4GSWGUVꢀ5GNGEV
4ꢋ9
4GUGV
0
0ꢋ#
:
4ꢋ9
:
:
:
:
:
:
:
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢏꢌꢃ
&/#ꢃꢀ
4ꢋ9
+HꢀVJGꢀ5QWTEGꢀ/QFGꢀHKGNFꢀKPꢀVJGꢀ
5QWTEGꢀ
#FFTGUUꢀꢎꢎꢌ
ꢂꢏꢅꢀ14ꢀ
&/#ꢀ
&/1&'ꢀTGIKUVGTꢀKUꢀꢃꢃꢌꢂꢃꢅꢀVJKUꢀHKGNFꢀ
EQPVCKPUꢀ#ꢎꢎꢌꢂꢏꢀQHꢀVJGꢀ5QWTEGꢀ
OGOQT[ꢀCFFTGUU
4GSWGUVꢀ
5GNGEV
+HꢀVJGꢀ5QWTEGꢀ/QFGꢀHKGNFꢀKPꢀVJGꢀ
&/1&'ꢀTGIKUVGTꢀKUꢀꢂꢂꢅꢀKPFKECVKPIꢀCPꢀ+ꢋ
1ꢀUQWTEGꢅꢀDKVUꢀꢎꢌꢃꢀUGNGEVꢀYJKEJꢀ
UQWTEGꢀFGXKEGꢀJCPFUJCMGꢀNKPGꢀ
EQPVTQNUꢀFCVCꢀVTCPUHGTꢅꢀCUꢀHQNNQYUꢈ
&4'3ꢃꢀRKP
ꢃꢃꢃ #5%+ꢃꢀ4&4(
ꢃꢃꢂ #5%+ꢂꢀ4&4(
ꢃꢂꢃ 4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
ꢃꢂꢂ 5+1ꢀ#ꢀ4Z
ꢂꢃꢃ 5+1ꢀ$ꢀ4Z
ꢂꢃꢂ 2+1ꢀ#ꢀ+P
ꢂꢂꢃ 2+1ꢀ$ꢀ+P
ꢂꢂꢂ
6
ꢁꢏꢓꢅ &/#ꢃꢁ&
ꢁ#
ꢁ4
ꢁ. ꢁꢈꢃꢃꢆꢌ*ꢉꢁꢃ.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀD[VGꢀQHꢀ&/#ꢃꢀ&GUVKPCVKQPꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
&/#ꢃꢀ
4ꢋ9
.5ꢀD[VGꢀQHꢀVJGꢀ&GUVKPCVKQPꢀ#FFTGUUꢀ
HQTꢀ&/#ꢀEJCPPGNꢀꢃꢄ
&GUVKPCVKQPꢀ
#FFTGUUꢀ.5ꢀ
D[VG
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢊꢊ
+ꢋ1 4
&/#ꢀ4
6
ꢁꢐꢃꢅ &/#ꢃꢁ&
ꢁ#
ꢁ4
ꢁ* ꢁꢈꢃꢃꢆꢎ*ꢉꢁꢃ*
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
/KFFNGꢀD[VGꢀQHꢀ&/#ꢃꢀ&GUVKPCVKQPꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
&/#ꢃꢀ
&GUVKPCVKQPꢀ
#FFTGUUꢀ
4ꢋ9
$KVUꢀꢂꢆꢌꢇꢀQHꢀVJGꢀ&GUVKPCVKQPꢀ#FFTGUUꢀ
HQTꢀ&/#ꢀEJCPPGNꢀꢃꢄ
OKFFNGꢀD[VG
6
ꢁꢐꢄꢅ &/#ꢃꢁ&
ꢁ#
ꢁ4
ꢁ$ꢁꢈꢃꢃꢆꢏ*ꢉꢁꢃ$
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF 4GUGTXGF
&/#ꢂꢀ&GUVKPCVKQPꢀ#FFTGUUꢀꢎꢎꢌꢂꢏꢅꢀ14
0QVꢀWUGF &/#ꢀ4GSWGUVꢀ5GNGEV
4ꢋ9
4GUGV
0
0ꢋ#
:
4ꢋ9
:
:
:
:
:
:
:
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢏꢌꢃ
&/#ꢃꢀ
4ꢋ9
+HꢀVJGꢀ&GUVKPCVKQPꢀ/QFGꢀHKGNFꢀKPꢀVJGꢀ
&/1&'ꢀTGIKUVGTꢀKUꢀꢃꢃꢌꢂꢃꢅꢀVJKUꢀHKGNFꢀ
EQPVCKPUꢀ#ꢎꢎꢌꢂꢏꢀQHꢀVJGꢀ&GUVKPCVKQPꢀ
OGOQT[ꢀCFFTGUU
&GUVKPCVKQPꢀ
#FFTGUUꢀꢎꢎꢌ
ꢂꢏꢅꢀ14
&/#ꢀ
4GSWGUVꢀ
5GNGEV
+HꢀVJGꢀ&GUVKPCVKQPꢀ/QFGꢀHKGNFꢀKPꢀVJGꢀ
&/1&'ꢀTGIKUVGTꢀKUꢀꢂꢂꢅꢀKPFKECVKPIꢀCPꢀ+ꢋ
1ꢀFGUVKPCVKQPꢅꢀDKVUꢀꢎꢌꢃꢀUGNGEVꢀYJKEJꢀ
FGUVKPCVKQPꢀFGXKEGꢀJCPFUJCMGꢀNKPGꢀ
EQPVTQNUꢀFCVCꢀVTCPUHGTꢅꢀCUꢀHQNNQYUꢈ
&4'3ꢃꢀRKP
ꢃꢃꢃ #5%+ꢃꢀ6&4'
ꢃꢃꢂ #5%+ꢂꢀ6&4'
ꢃꢂꢃ 4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
ꢃꢂꢂ 5+1ꢀ#ꢀ6Z
ꢂꢃꢃ 5+1ꢀ$ꢀ6Z
ꢂꢃꢂ 2+1ꢀ#ꢀ1WV
ꢂꢂꢃ 2+1ꢀ$ꢀ1WV
ꢂꢂꢂ
ꢂꢊꢉ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
&/#ꢀ4
+ꢋ1 4
6
ꢁꢐꢆꢅ &/#ꢃꢁ$
ꢁ%
ꢁ4
ꢁ. ꢁꢈꢃꢃꢆꢐ*ꢉꢁ$%4ꢃ.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀD[VGꢀQHꢀ&/#ꢃꢀ$[VGꢀ%QWPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
&/#ꢃꢀ$[VGꢀ 4ꢋ9
%QWPVꢀ.5ꢀ
D[VG
.5ꢀD[VGꢀQHꢀVJGꢀ$[VGꢀ%QWPVꢀHQTꢀ&/#ꢀ
EJCPPGNꢀꢃꢄ
6
ꢁꢐꢌꢅ &/#ꢃꢁ$
ꢁ%
ꢁ4
ꢁ* ꢁꢈꢃꢃꢆꢑ*ꢉꢁ$%4ꢃ*
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
/5ꢀD[VGꢀQHꢀ&/#ꢃꢀ$[VGꢀ%QWPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
&/#ꢃꢀ$[VGꢀ 4ꢋ9
%QWPVꢀ/5ꢀ
D[VG
/5ꢀD[VGꢀQHꢀVJGꢀ$[VGꢀ%QWPVꢀHQTꢀ&/#ꢀ
EJCPPGNꢀꢃꢄ
6
ꢁꢐꢎꢅ &/#ꢄꢁ/
ꢁ#
ꢁ4
ꢁ. ꢁꢈꢃꢃꢆꢂ*ꢉꢁ/#4ꢄ.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
&/#ꢂꢀ/GOQT[ꢀ#FFTGUUꢀDKVUꢀꢍꢌꢃ
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
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ꢆꢌꢉ
&/#ꢃꢀ&GUVꢀ 4ꢋ9
/QFG
6JKUꢀHKGNFꢀEQPVTQNUꢀQRGTCVKQPꢀQHꢀVJGꢀ
FGUVKPCVKQPꢀUKFGꢀQHꢀ&/#ꢀEJCPPGNꢀꢃꢈ
/GOQT[ꢀYTKVGꢅꢀCFFTGUUꢀKPETGOGPV
ꢃꢃ /GOQT[ꢀYTKVGꢅꢀCFFTGUUꢀFGETGOGPV
ꢃꢂ /GOQT[ꢀꢐQTꢀOGOQT[ꢀOCRRGFꢀ+ꢋ1ꢑꢀ
ꢂꢃ YTKVGꢅꢀHKZGFꢀCFFTGUU
+ꢋ1ꢀYTKVGꢅꢀHKZGFꢀCFFTGUU
ꢂꢂ
ꢊꢌꢎ
&/#ꢃꢀ
5QWTEGꢀ
/QFG
4ꢋ9
4ꢋ9
6JKUꢀHKGNFꢀEQPVTQNUꢀQRGTCVKQPꢀQHꢀVJGꢀ
UQWTEGꢀUKFGꢀQHꢀ&/#ꢀEJCPPGNꢀꢃꢈ
ꢃꢃ /GOQT[ꢀTGCFꢅꢀCFFTGUUꢀKPETGOGPV
ꢃꢂ /GOQT[ꢀTGCFꢅꢀCFFTGUUꢀFGETGOGPV
ꢂꢃ /GOQT[ꢀꢐQTꢀOGOQT[ꢀOCRRGFꢀ+ꢋ1ꢑꢀ
TGCFꢅꢀHKZGFꢀCFFTGUU
ꢂꢂ +ꢋ1ꢀTGCFꢅꢀHKZGFꢀCFFTGUU
ꢂ
//1&
9JGPꢀVJGꢀ5QWTEGꢀCPFꢀ&GUVꢀ/QFGꢀ
HKGNFUꢀCDQXGꢀCTGꢀDQVJꢀꢃZꢅꢀKPFKECVKPIꢀ
OGOQT[ꢀVQꢀOGOQT[ꢀQRGTCVKQPꢅꢀPQꢀ
FGXKEGꢀTGSWGUVꢀꢐHQTꢀGZCORNGꢅꢀ&4'3ꢃꢑꢀ
EQPVTQNUꢀFCVCꢀVTCPUHGTꢀQPꢀ&/#ꢀ
EJCPPGNꢀꢃꢄꢀ+PꢀVJKUꢀECUGꢅꢀVJKUꢀDKVꢀUGNGEVUꢀ
DGVYGGPꢀVYQꢀOQFGUꢈ
ꢃ
ꢂ
%[ENGꢁ5VGCNꢁOQFGꢊꢀVJGꢀ&/#ꢐUꢑꢀCPFꢀ
RTQEGUUQTꢀCNVGTPCVGꢀDWUꢀE[ENGUꢄ
$WTUVꢁOQFGꢊꢀ&/#ꢃꢀWUGUꢀVJGꢀDWUꢀ
EQPVKPWQWUN[ꢀVQꢀEQORNGVGꢀVJGꢀDNQEMꢀ
VTCPUHGTꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢉꢂ
+ꢋ1 4
&/#ꢀ4
6
ꢁꢑꢎꢅ &/#ꢋ9 ꢁ%
ꢁ4
ꢁꢈꢃꢃꢌꢆ*ꢉꢁ&%06.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF /GOQT[ꢀ9CKVU
+ꢋ1ꢀ9CKVU
4GSWGUVꢀ5GPUGꢀ &/#ꢂꢀ/QFG
ꢂꢌꢃ
4ꢋ9
4GUGV
0
4ꢋ9
4ꢋ9
4ꢋ9
4ꢋ9
ꢂ
ꢂ
ꢂ
ꢂ
ꢃ
ꢃ
ꢃ
ꢃ
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢏ
ꢆꢌꢉ
ꢊꢌꢎ
/GOQT[ꢀ
9CKVU
4ꢋ9
4ꢋ9
4ꢋ9
6JKUꢀHKGNFꢀEQPVTQNUꢀJQYꢀOCP[ꢀYCKVꢀ
UVCVGUꢀCTGꢀKPLGEVGFꢀKPVQꢀ&/#ꢀCPFꢀ
RTQEGUUQTꢀOGOQT[ꢀE[ENGUꢈ
ꢃꢃ 0QPG
ꢃꢂ 1PG
ꢂꢃ 6YQ
ꢂꢂ 6JTGG
+ꢋ1ꢀ9CKVU
6JKUꢀHKGNFꢀEQPVTQNUꢀJQYꢀOCP[ꢀYCKVꢀ
UVCVGUꢀCTGꢀKPLGEVGFꢀKPVQꢀ&/#ꢀCPFꢀ
RTQEGUUQTꢀ+ꢋ1ꢀE[ENGUꢈ
ꢃꢃ 0QPG
ꢃꢂ 1PG
ꢂꢃ 6YQ
ꢂꢂ 6JTGG
4GSWGUVꢀ
5GPUGꢀꢂꢌꢃ
'CEJꢀQHꢀVJGUGꢀDKVUꢀEQPVTQNUꢀJQYꢀVJGꢀ
EQTTGURQPFKPIꢀ&/#ꢀEJCPPGNꢀ
UCORNGUꢀKVUꢀ4GSWGUVꢀUKIPCNꢀꢐGZEGRVꢀ
YJGPꢀ&/#ꢀꢃ Uꢀ5QWTEGꢀCPFꢀ&GUVꢀ
/QFGꢀHKGNFUꢀCTGꢀDQVJꢀꢃZꢑ
ꢃ
ꢂ
.GXGNꢁUGPUGꢊꢀVJGꢀ&/#ꢀUCORNGUꢀKVUꢀ
4GSWGUVꢀCICKPꢀFWTKPIꢀVJGꢀꢎPFꢀE[ENGꢀ
HQTꢀGCEJꢀD[VG
'FIGꢁUGPUGꢊꢁCPQVJGTꢀHCNNKPIꢀGFIGꢀKUꢀ
PGGFGFꢀQPꢀVJGꢀ4GSWGUVꢀNKPGꢀDGHQTGꢀ
VJGꢀ&/#ꢀEJCPPGNꢀVTCPUHGTUꢀCPQVJGTꢀ
D[VG
5GGꢀUGEVKQPꢀ 'FIGꢌꢀXUꢄꢀ.GXGNꢌ5GPUKꢌ
VKXGꢀ4GSWGUVU ꢅꢀQPꢀRCIGꢀꢆꢇꢅꢀHQTꢀ
VKOKPIꢀQHꢀDQVJꢀECUGUꢄ
ꢂꢌꢃ
&/#ꢂꢀ
/QFG
4ꢋ9
6JKUꢀHKGNFꢀEQPVTQNUꢀVJGꢀFKTGEVKQPꢀQHꢀ
DQVJꢀVTCPUHGTꢀCPFꢀCFFTGUUꢀUVGRRKPIꢀ
QPꢀ&/#ꢀEJCPPGNꢀꢂꢈ
ꢃꢃ +PETGOGPVKPIꢀ/GOQT[ꢀCFFTUꢀVQꢀ+ꢋ1
ꢃꢂ &GETGOGPVKPIꢀ/GOQT[ꢀCFFTUꢀVQꢀ+ꢋ1
ꢂꢃ +ꢋ1ꢀVQꢀKPETGOGPVKPIꢀ/GOQT[ꢀCFFTU
ꢂꢂ +ꢋ1ꢀVQꢀFGETGOGPVKPIꢀ/GOQT[ꢀCFFTU
ꢂꢉꢎ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
9
ꢌ& ꢀ6
ꢀ4
+ꢋ1 4
9#6%*ꢀ&1)ꢁ6+/'4ꢁ4')+56'45
See section “Watch-Dog Timer”, on page 63, for more about these registers.
6
ꢁꢑꢏꢅ 9
ꢀ& ꢁ6
ꢁ/
ꢁ4
ꢁꢈ (ꢃꢁ ꢁꢃꢃ(ꢃ*ꢉꢁ9&6/4
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢂ
ꢎ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF 'PCDNG 2GTKQFꢀ5GNGEV
4GUGTXGF
4ꢋ9
4GUGV
0
4ꢋ9
ꢂ
4ꢋ9
:
ꢃ
ꢃ
ꢃ
ꢂ
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍ
9&6ꢀ'PCDNG 4ꢋ9
ꢃ
9TKVKPIꢀ$ꢂ*ꢀVQꢀVJGꢀ9&6ꢀ%QOOCPFꢀ
TGIKUVGTꢀFKUCDNGUꢀVJGꢀ9&6
ꢂ
6JGꢀ9&6ꢀECPPQVꢀDGꢀFKUCDNGFꢄ
ꢏꢌꢆ
2GTKQFꢀ
5GNGEV
4ꢋ9
6JGꢀHKGNFꢀUGNGEVUꢀJQYꢀNQPIꢀUQHVYCTGꢀ
ECPꢀNGCXGꢀVJGꢀ9CVEJꢌ&QIꢀ6KOGTꢀWPCVꢌ
VGPFGFꢅꢀDGHQTGꢀKVꢀFTKXGUꢀ9&6176ꢀ
.QYꢈ
ꢎ
ꢎ
ꢎ
ꢎ
ꢀꢐꢀꢏꢆꢅꢆꢊꢏꢑꢀ2*+ꢀENQEMU
ꢀꢐꢀꢎꢏꢎꢅꢂꢉꢉꢑꢀ2*+ꢀENQEMU
ꢀꢐꢂꢅꢃꢉꢇꢅꢆꢍꢏꢑꢀ2*+ꢀENQEMU
ꢀꢐꢉꢅꢂꢁꢉꢅꢊꢃꢉꢑꢀ2*+ꢀENQEMU
ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
6
ꢁꢑꢐꢅ 9
ꢀ& ꢁ6
ꢁ%
ꢁ4
ꢁꢈ (ꢄꢁ ꢁꢃꢃ(ꢄ*ꢉꢁ9&6%4
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
9&6ꢀ%QOOCPF
9
4GUGV
PꢋC
PꢋC
PꢋC
PꢋC
PꢋC
PꢋC
PꢋC
PꢋC
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
9&6ꢀ
%QOOCPF
9
5QHVYCTGꢀECPꢀYTKVGꢀVJGꢀHQNNQYKPIꢀ
XCNWGUꢀVQꢀVJKUꢀTGIKUVGTꢅꢀVQꢀCHHGEVꢀVJGꢀ
UVCVWUꢀQHꢀVJGꢀ9&6ꢀCPFꢀ<ꢇꢃ5ꢂꢇꢇꢈ
4GNQCFUꢋ4GUVCTVUꢀ9&6
ꢉ'* &KUCDNGUꢀ9&6ꢀKHꢀ9&6/4ꢀDKVꢀꢍꢀKUꢀꢃ
$ꢂ*
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢉꢊ
+ꢋ1 4
%
ꢋ6
ꢀꢐ%6%ꢑꢀ4
%1706'4ꢋ6+/'4ꢁꢈ%6%ꢉꢁ4')+56'45
See section “Counter/Timer Channels (CTCs)”, on page 63, for more about these
registers.
6
ꢁꢑꢑꢅ %6%ꢃꢁꢈ &ꢃꢁ ꢁꢃꢃ&ꢃ*ꢉꢁ%6%ꢃ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4GCFꢈꢀXCNWGꢀQHꢀ%6%ꢃꢀFQYPꢌEQWPVGT
9TKVGꢈꢀ+PVGTTWRVꢀ8GEVQTꢀQTꢀ%JCPPGNꢀ%QPVTQNꢀQTꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
ꢂꢉꢉ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
%
ꢋ6
ꢀꢐ%6%ꢑꢀ4
+ꢋ1 4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9
8CNWG
&GUETKRVKQP
ꢍꢌꢃ %6%ꢃ
4ꢋ9
4GCFKPIꢀVJKUꢀCFFTGUUꢀTGVWTPUꢀVJGꢀ
XCNWGꢀQHꢀEJCPPGNꢀꢃ UꢀFQYPꢌEQWPVGTꢄ
9TKVKPIꢀCPꢀGXGPꢀXCNWGꢀUGVUꢀDKVUꢀꢍꢌꢊꢀQHꢀ
XXXXXZZꢃ VJGꢀKPVGTTWRVꢀXGEVQTꢀHQTꢀCNNꢀHQWTꢀEJCPꢌ
PGNUꢄ
9TKVKPIꢀCPꢀQFFꢀXCNWGꢀNQCFUꢀCꢀ
GERWVHTꢂ %JCPPGNꢀ%QPVTQNꢀYQTFꢅꢀKPꢀYJKEJꢈ
$KVꢁꢑꢀGPCDNGUꢀꢐꢂꢑꢀQTꢀFKUCDNGUꢀꢐꢃꢑꢀKPVGTꢌ
TWRVUꢀHTQOꢀVJKUꢀEJCPPGNꢄ
$KVꢁꢐꢀUGNGEVUꢀ%QWPVGTꢀꢐꢂꢑꢀQTꢀ6KOGTꢀꢐꢃꢑꢀ
OQFGꢄ
+Pꢀ6KOGTꢀOQFGꢅꢀDKVꢁꢏꢀUGNGEVUꢀYJGVJGTꢀ
VJGꢀRTGUECNGTꢀFKXKFGUꢀ2*+ꢀD[ꢀꢎꢆꢏꢀꢐꢂꢑꢀ
QTꢀꢂꢏꢀꢐꢃꢑꢄ
$KVꢁꢎꢀUGNGEVUꢀTKUKPIꢀꢐꢂꢑꢀQTꢀHCNNKPIꢀꢐꢃꢑꢀ
GFIGUꢀQPꢀ%.-ꢋ64)ꢃꢀVQꢀFGETGOGPVꢀ
VJGꢀFQYPꢌEQWPVGTꢀKPꢀ%QWPVGTꢀOQFGꢅꢀ
QTꢀVQꢀVTKIIGTꢀFQYPꢌEQWPVKPIꢀKPꢀ6KOGTꢀ
OQFGꢀYKVJꢀDKVꢀꢊꢀUGVꢄꢀ
+Pꢀ6KOGTꢀOQFGꢅꢀDKVꢁꢌꢀEQPVTQNUꢀ
YJGVJGTꢀVJGꢀEJCPPGNꢀUVCTVUꢀFQYPꢌ
EQWPVKPIꢀKOOGFKCVGN[ꢀCHVGTꢀUQHVYCTGꢀ
NQCFUꢀVJGꢀ6KOGꢀ%QPUVCPVꢀꢐꢃꢑꢅꢀQTꢀYCKVUꢀ
HQTꢀVJGꢀGFIGꢀUGNGEVGFꢀD[ꢀDKVꢀꢉꢅꢀQPꢀ
%.-ꢋ64)ꢃꢅꢀDGHQTGꢀEQWPVKPIꢀFQYPꢀ
ꢐꢂꢑꢄ
9TKVKPIꢀCꢀꢂꢀVQꢀDKVꢁꢆꢀKPFKECVGUꢀVJCVꢀVJGꢀ
EJCPPGNꢀNQCFUꢀVJGꢀPGZVꢀD[VGꢀYTKVVGPꢀ
VQꢀVJKUꢀCFFTGUUꢅꢀKPVQꢀKVUꢀ6KOGꢀ
%QPUVCPVꢀTGIKUVGTꢄꢀ+HꢀVJGꢀEJCPPGNꢀKUꢀ
UVQRRGFꢅꢀQTꢀDKVꢀꢂꢀKUꢀꢂꢅꢀVJGꢀXCNWGꢀKUꢀ
CNUQꢀNQCFGFꢀKPVQꢀKVUꢀFQYPꢌEQWPVGTꢄ
9TKVKPIꢀCꢀꢂꢀVQꢀDKVꢁꢄꢀUVQRUꢀVJGꢀEJCPPGNꢀ
KHꢀKVꢀJCUꢀDGGPꢀTWPPKPIꢅꢀCPFꢀTGUGVUꢀKVꢀKPꢀ
CP[ꢀECUGꢄꢀ+HꢀDKVUꢀꢎꢌꢂꢀCTGꢀꢂꢂꢅꢀVJGꢀ
EJCPPGNꢀKUꢀTGꢌGPCDNGFꢀCHVGTꢀUQHVYCTGꢀ
YTKVGUꢀVJGꢀPGYꢀ6KOGꢀ%QPUVCPVꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢉꢆ
+ꢋ1 4
%
ꢋ6
ꢀꢐ%6%ꢑꢀ4
6
ꢁꢑꢂꢅ %6%ꢄꢁꢈ &ꢄꢁ ꢁꢃꢃ&ꢄ*ꢉꢁ%6%ꢄ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4GCFꢈꢀXCNWGꢀQHꢀ%6%ꢂꢀFQYPꢌEQWPVGT
9TKVGꢈꢀ%JCPPGNꢀ%QPVTQNꢀQTꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
ꢊ This address operates as described for CTC0 above, except:
1. Software cannot write an interrupt vector to this address, and
2. The pin associated with CTC1 is CLK/TRG1
6
ꢁꢑꢓꢅ %6%ꢆꢁꢈ &ꢆꢁ ꢁꢃꢃ&ꢆ*ꢉꢁ%6%ꢆ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4GCFꢈꢀXCNWGꢀQHꢀ%6%ꢎꢀFQYPꢌEQWPVGT
9TKVGꢈꢀ%JCPPGNꢀ%QPVTQNꢀQTꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
0
ꢊ This address operates as described for CTC0 above, except:
1. Software cannot write an interrupt vector to this address, and
2. The pin associated with CTC2 is CLK/TRG2
6
ꢁꢂꢃꢅ %6%ꢌꢁꢈ &ꢌꢁ ꢁꢃꢃ&ꢌ*ꢉꢁ%6%ꢌ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4GCFꢈꢀXCNWGꢀQHꢀ%6%ꢊꢀFQYPꢌEQWPVGT
9TKVGꢈꢀ%JCPPGNꢀ%QPVTQNꢀQTꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
0
ꢊ This address operates as described for CTC0 above, except:
1. Software cannot write an interrupt vector to this address, and
2. The pin associated with CTC3 is CLK/TRG3
ꢂꢉꢏ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
2
ꢀ4
ꢀ6
ꢀꢐ246ꢑꢀ4
+ꢋ1 4
241)4#//#$.'ꢁ4'.1#&ꢁ6+/'4ꢁꢈ246ꢉꢁ4')+56'45
See section “Programmable Reload Timers (PRTs)”, on page 70, for more about
these registers.
6
ꢁꢂꢄꢅ 246ꢃꢁ6
ꢁ&
ꢁ4
ꢁ. ꢁꢈꢃꢃꢃ%*ꢉꢁ6/&4ꢃ.
$KV
ꢍ
ꢏ
ꢆ
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ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
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246ꢃꢀ
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6
ꢁꢂꢆꢅ 246ꢃꢁ6
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246ꢃꢀ
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2
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4ꢋ9
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4
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4
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4ꢋ9
4ꢋ9
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4ꢋ9
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$KV
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2TGUECNGꢀ
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ꢃꢃꢃꢃ 2*+ꢋꢎ
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ꢃꢂꢃꢃ 2*+ꢋꢊꢎ
ꢃꢂꢃꢂ 2*+ꢋꢏꢉ
ꢃꢂꢃꢃ 2*+ꢋꢂꢎꢇ
ꢃꢂꢂꢂ 2*+ꢋꢎꢆꢏ
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ꢂꢂꢂꢂ
6
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246ꢂꢀ
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25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
2
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6
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ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
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4ꢋ9 8CNWG &GUETKRVKQP
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246ꢂꢀ
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6
ꢁꢂꢓꢅ 246ꢄꢁ4
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0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
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4ꢋ9
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246ꢂꢀ
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6
ꢁꢓꢃꢅ 246ꢄꢁ4
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0
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4ꢋ9 8CNWG &GUETKRVKQP
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6JGꢀ/5ꢀꢇꢀDKVUꢀQHꢀVJGꢀXCNWGꢀVJCVꢀKUꢀ
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YJGPꢀKVꢀKUꢀFGETGOGPVGFꢀVQꢀꢃꢄ
246ꢂꢀ
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8CNWG
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢆꢂ
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5
ꢀ+ꢋ1ꢀꢐ5+1ꢑꢀ4
5'4+#.ꢁ+ꢋ1ꢁꢈ5+1ꢉꢁ4')+56'45
See section “Serial I/O Channels (SIOs)”, on page 72, for more about these regis-
ters.
6
ꢁꢓꢄꢅ 5+1ꢁ#ꢁ&
ꢁꢈ &ꢂꢁ ꢁꢃꢃ&ꢂ*ꢉꢁ5+1#&
$KV
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4ꢋ9
9TKVGꢈꢀ6ZꢀEJCTCEVGTꢅꢀ4GCFꢈꢀ4ZꢀEJCTCEVGT
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
&CVC
4ꢋ9
#ꢀEJCTCEVGTꢀVQꢀDGꢀVTCPUOKVVGFꢀECPꢀDGꢀ
YTKVVGPꢀVQꢀVJKUꢀCFFTGUUꢅꢀQPN[ꢀYJGPꢀDKVꢀ
ꢎꢀQHꢀ44ꢃꢀKUꢀꢂꢄꢀ+HꢀDKVUꢀꢏꢌꢆꢀQHꢀ94ꢆꢀ
URGEKH[ꢀNGUUꢀVJCPꢀꢇꢀDKVUꢋEJCTCEVGTꢅꢀ
QPN[ꢀVJGꢀ.5ꢀDKVUꢀQHꢀVJGꢀXCNWGꢀYTKVVGPꢀ
KUꢀUGPVꢄ
6JKUꢀCFFTGUUꢀKUꢀTGCFꢀQPN[ꢀYJGPꢀDKVꢀꢃꢀ
QHꢀ44ꢃꢀKUꢀꢂꢅꢀKPꢀYJKEJꢀECUGꢀKVꢀTGVWTPUꢀ
VJGꢀQNFGUVꢀCXCKNCDNGꢀTGEGKXGFꢀEJCTꢌ
CEVGTꢄ
6
ꢁꢓꢆꢅ 5+1ꢁ#ꢁ%
ꢁꢈ &ꢓꢁ ꢁꢃꢃ&ꢓ*ꢉꢁ5+1#%
$KV
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9TKVGꢈꢀ94ꢃꢅꢂꢅꢊꢌꢍꢀRGTꢀ94ꢃꢀDKVUꢀꢎꢌꢃꢅꢀ
4GCFꢈꢀ44ꢃꢌꢂꢀRGTꢀ94ꢃꢀDKVUꢀꢎꢌꢃ
4ꢋ9
4ꢋ9
4GUGV
:
:
:
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:
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0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
ꢂꢆꢎ
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25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
5
ꢀ+ꢋ1ꢀꢐ5+1ꢑꢀ4
+ꢋ1 4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
4ꢋ9
ꢍꢌꢃ 94ꢀQTꢀ44
9TKVKPIꢀVQꢀVJKUꢀCFFTGUUꢀNQCFUꢀVJGꢀ
9TKVGꢀ4GIKUVGTꢀUGNGEVGFꢀD[ꢀDKVUꢀꢎꢌꢃꢀQHꢀ
94ꢃꢅꢀYJKNGꢀTGCFKPIꢀHTQOꢀVJKUꢀ
CFFTGUUꢀTGVWTPUꢀVJGꢀEQPVGPVUꢀQHꢀVJGꢀ
4GCFꢀ4GIKUVGTꢀUGNGEVGFꢀD[ꢀDKVUꢀꢎꢌꢃꢀQHꢀ
94ꢃꢄꢀ$KVUꢀꢎꢌꢃꢀQHꢀ94ꢃꢀCTGꢀENGCTGFꢀVQꢀ
ꢃꢃꢃꢀD[ꢀTGUGVꢀCPFꢀCHVGTꢀCP[ꢀCEEGUUꢀVQꢀ
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ꢀ+ꢋ1ꢀꢐ5+1ꢑꢀ4
+ꢋ1 4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍ
*&.%ꢋ5&.%ꢀ
'PFꢀQHꢀ
(TCOG
4
6JKUꢀDKVꢀKUꢀUGVꢀQPN[ꢀKPꢀ*&.%ꢋ5&.%ꢀ
OQFGꢅꢀYJGPꢀCꢀENQUKPIꢀ(NCIꢀKUꢀ
FGVGEVGFꢄꢀ+VꢀKUꢀENGCTGFꢀKHꢀUQHVYCTGꢀ
YTKVGUꢀCPꢀ'TTQTꢀ4GUGVꢀEQOOCPFꢀVQꢀ
94ꢃꢅꢀCPFꢀCNUQꢀYJGPꢀVJGꢀHKTUVꢀEJCTꢌ
CEVGTꢀQHꢀVJGꢀPGZVꢀHTCOGꢀCTTKXGUꢄ
ꢏ
%4%ꢋ
(TCOKPIꢀ
'TTQT
4
+Pꢀ#U[PEꢀQTꢀKUQEJTQPQWUꢀOQFGꢅꢀVJKUꢀ
DKVꢀKUꢀꢂꢀKHꢀCꢀEJCTCEVGTꢀKUꢀCXCKNCDNGꢀVQꢀDGꢀ
TGCFꢀHTQOꢀVJGꢀEJCPPGN UꢀFCVCꢀ
CFFTGUUꢅꢀKPꢀYJKEJꢀVJGꢀTGEGKXGTꢀ
UCORNGFꢀVJGꢀ5VQRꢀDKVꢀCUꢀꢃꢋURCEGꢋ.QYꢄꢀ
+Pꢀ*&.%ꢋ5&.%ꢀOQFGꢅꢀCꢀꢂꢀKPꢀVJKUꢀDKVꢀ
KPFKECVGUꢀCꢀ%4%ꢀGTTQTꢀYJGPꢀCEEQORCꢌ
PKGFꢀD[ꢀCꢀꢂꢀKPꢀDKVꢀꢍꢄ
+Pꢀ%NCUUKEꢀ5[PEꢀOQFGUꢅꢀYJGPꢀUQHVꢌ
YCTGꢀTGCFUꢀCꢀOGUUCIGꢌVGTOKPCVKPIꢀ
EJCTCEVGTꢀHTQOꢀVJGꢀEJCPPGN UꢀFCVCꢀ
CFFTGUUꢅꢀKHꢀVJGꢀ4ZꢀEJCTCEVGTꢀNGPIVJꢀKPꢀ
94ꢊꢀKUꢀNGUUꢀVJCPꢀꢇꢀDKVUꢅꢀ94ꢊꢀKUꢀ
YTKVVGPꢀVQꢀEJCPIGꢀKVꢀVQꢀꢇꢀDKVUꢋEJCTꢌ
CEVGTꢄꢀ6JGPꢀUQHVYCTGꢀYCKVUꢀHQTꢀꢉꢀOQTGꢀ
4Zꢀ#XCKNCDNGꢀHNCIUꢅꢀVJGꢀHKTUVꢀVYQꢀEJCTꢌ
CEVGTUꢀQHꢀYJKEJꢀCTGꢀVJGꢀ%4%ꢄ
ꢏꢀꢐEQPVꢄꢑ
+Pꢀ%NCUUKEꢀ5[PEꢀOQFGUꢅꢀVJKUꢀDKVꢀXCNKFN[ꢀ
TGHNGEVUꢀ%4%ꢀEQTTGEVPGUUꢀYJGPꢀ44ꢃꢀ
DKVꢀꢃꢀKUꢀꢂꢀHQTꢀVJGꢀꢎPFꢀEJCTCEVGTꢀCHVGTꢀ
VJGꢀNCUVꢀ%4%ꢀEJCTCEVGTꢄꢀ4GICTFNGUUꢀQHꢀ
VJGꢀOQFGꢅꢀVJKUꢀDKVꢀECPꢀDGꢀENGCTGFꢀD[ꢀ
YTKVKPIꢀCPꢀ'TTQTꢀ4GUGVꢀEQOOCPFꢀVQꢀ
94ꢃꢅꢀDWVꢀVJGꢀDKVꢀKUꢀPQVꢀNCVEJGFꢀCPFꢀKUꢀ
WRFCVGFꢀHQTꢀGCEJꢀTGEGKXGFꢀEJCTCEVGT
ꢆ
4Zꢀ1XGTTWP
4
+PꢀCP[ꢀOQFGꢅꢀVJGꢀTGEGKXGTꢀUGVUꢀVJKUꢀDKVꢀ
KHꢀUQHVYCTGꢀQTꢀCꢀ&/#ꢀEJCPPGNꢀJCUꢀPQVꢀ
TGCFꢀTGEGKXGFꢀEJCTCEVGTUꢀHTQOꢀVJGꢀ
EJCPPGN UꢀFCVCꢀCFFTGUUꢀKPꢀCꢀVKOGN[ꢀ
OCPPGTꢅꢀUQꢀVJCVꢀCPQVJGTꢀEJCTCEVGTꢀ
CTTKXGUꢀYJGPꢀVJGꢀꢊꢌEJCTCEVGTꢀ4Zꢀ(+(1ꢀ
KUꢀHWNNꢄꢀ6JKUꢀDKVꢀKUꢀUGVꢀYJGPꢀVJGꢀEJCTꢌ
CEVGTꢀVJCVꢀQXGTYTQVGꢀKVUꢀRTGFGEGUUQTꢀ
EQOGUꢀVQꢀVJGꢀVQRꢀQHꢀVJGꢀ4Zꢀ(+(1ꢅꢀCPFꢀ
TGOCKPUꢀUGVꢀWPVKNꢀKVꢀKUꢀENGCTGFꢀD[ꢀCPꢀ
'TTQTꢀ4GUGVꢀEQOOCPFꢀYTKVVGPꢀVQꢀ
94ꢃꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢏꢊ
+ꢋ1 4
5
ꢀ+ꢋ1ꢀꢐ5+1ꢑꢀ4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢉ
2CTKV[ꢀ'TTQT
4
+HꢀDKVꢀꢃꢀQHꢀ94ꢉꢀKUꢀꢂꢅꢀVJGꢀTGEGKXGTꢀUGVUꢀ
VJKUꢀDKVꢀYJGPꢀCꢀEJCTCEVGTꢀYKVJꢀRCTKV[ꢀ
FKHHGTGPVꢀHTQOꢀVJGꢀUGPUGꢀFGHKPGFꢀD[ꢀ
94ꢉꢀDKVꢀꢂꢅꢀEQOGUꢀVQꢀVJGꢀVQRꢀQHꢀVJGꢀ4Zꢀ
(+(1ꢄꢀ9JGPꢀUGVꢅꢀVJKUꢀDKVꢀTGOCKPUꢀꢂꢀ
WPVKNꢀKVꢀKUꢀENGCTGFꢀD[ꢀCPꢀ'TTQTꢀ4GUGVꢀ
EQOOCPFꢀYTKVVGPꢀVQꢀ94ꢃꢄ
ꢊꢌꢂ
*&.%ꢋ5&.%ꢀ
4Zꢀ4GUKFWG
4
+Pꢀ*&.%ꢋ5&.%ꢀOQFGꢅꢀYJGPꢀDKVꢀꢍꢀQHꢀ
VJKUꢀTGIKUVGTꢀKUꢀꢂꢅꢀVJGUGꢀDKVUꢀKPFKECVGꢀ
VJGꢀPWODGTꢀCPFꢀRNCEGOGPVꢀQHꢀVJGꢀ
HKPCNꢀFCVCꢀDKVUꢀCPFꢀ%4%ꢅꢀKPꢀVJGꢀNCUVꢀꢊꢀ
QTꢀꢉꢀEJCTCEVGTUꢀQHꢀVJGꢀHTCOGꢄꢀ6JGꢀ
OGCPKPIꢀQHꢀVJKUꢀXCNWGꢀFGRGPFUꢀQPꢀ
VJGꢀPWODGTꢀQHꢀDKVUꢀRGTꢀEJCTCEVGTꢅꢀCPFꢀ
KUꢀKNNWUVTCVGFꢀKPꢀ(KIWTGUꢀꢂꢇꢀVJTQWIJꢀꢎꢂꢄ
ꢃ
#NNꢀ5GPV
4
+Pꢀ#U[PEꢀCPFꢀKUQEJTQPQWUꢀOQFGUꢅꢀ
VJKUꢀDKVꢀKUꢀꢂꢀYJGPꢀCNNꢀEJCTCEVGTUꢀ
YTKVVGPꢀVQꢀVJGꢀEJCPPGN UꢀFCVCꢀCFFTGUUꢀ
JCXGꢀDGGPꢀUGPVꢄ
ꢂꢏꢉ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
5
ꢀ+ꢋ1ꢀꢐ5+1ꢑꢀ4
+ꢋ1 4
6
ꢁꢄꢃꢆꢅ 5+1ꢁ$ꢁ&
ꢁꢈ &#ꢁ ꢁꢃꢃ&#*ꢉꢁ5+1$&
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
9TKVGꢈꢀ6ZꢀEJCTCEVGTꢅꢀ4GCFꢈꢀ4ZꢀEJCTCEVGT
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
0
ꢊ This address operates as described for SIO A Data above, except that it
deals with transmit data to be sent on the TxDB pin, and received data from the
RxDB pin.
6
ꢁꢄꢃꢌꢅ 5+1ꢁ$ꢁ%
ꢁꢈ &$ꢁ ꢁꢃꢃ&$*ꢉꢁ5+1$%
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
9TKVGꢈꢀ94ꢃꢌꢍꢀRGTꢀ94ꢃꢀDKVUꢀꢎꢌꢃꢅꢀ4GCFꢈꢀ44ꢃꢌꢎꢀRGTꢀ94ꢃꢀDKVUꢀꢎꢌꢃ
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
0
ꢊ This address operates as described for SIO A Control above, providing
access to the same Write and Read Registers for SIO channel B, except:
1. The Return From Interruptcommand cannot be issued in channel
B WR0.
2. The Status Affects Vector bit (WR1 bit 2) is only effective in channel B
WR1.
3. The Interrupt Pending bit (RR0 bit 1) is always 0in channel B RR0.
4. The following two registers are only accessible in channel B:
6
ꢁꢄꢃꢎꢅ 5+1ꢁ$ꢁ94ꢆꢁꢈ9
ꢁ
ꢁ
&$ꢁ ꢁꢃꢃ&$*ꢁ
ꢁ
94ꢃꢁꢆꢀꢃꢒꢃꢄꢃꢉ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
+PVGTTWRVꢀ8GEVQT
9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢏꢆ
+ꢋ1 4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
+PVGTTWRVꢀ
8GEVQT
9
6JGUGꢀDKVUꢀCTGꢀTGVWTPGFꢀCUꢀVJGꢀXGEVQTꢀ
FWTKPIꢀKPVGTTWRVꢀCEMPQYNGFIGꢀE[ENGUꢀ
KPꢀYJKEJꢀGKVJGTꢀ5+1ꢀEJCPPGNꢀKUꢀVJGꢀ
JKIJGUVꢀRTKQTKV[ꢀTGSWGUVKPIꢀFGXKEGꢄꢀ+Hꢀ
DKVꢀꢎꢀQHꢀEJCPPGNꢀ$ꢀ94ꢂꢀKUꢀꢂꢅꢀDKVUꢀꢊꢌꢂꢀ
EQPVCKPꢀCꢀEQFGꢀKFGPVKH[KPIꢀVJGꢀJKIJGUVꢀ
RTKQTKV[ꢀ5+1ꢀKPVGTTWRVꢀRGPFKPIꢅꢀCUꢀ
FGUETKDGFꢀHQTꢀ44ꢎꢄꢀ$KVꢀꢃꢀOWUVꢀDGꢀꢃꢀHQTꢀ
OQFGꢀꢎꢀKPVGTTWRVUꢄ
6
ꢁꢄꢃꢏꢅ 5+1ꢁ$ꢁ44ꢆꢁꢈ4
ꢁ
ꢁ
&$ꢁ ꢁꢃꢃ&$*ꢁ
ꢁ94ꢃꢁꢆꢀꢃꢒꢃꢄꢃꢉ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
+PVGTTWRVꢀ8GEVQT
4
8GEVQTꢀQTꢀ6[RGꢀ%QFG
4
+8ꢀꢃ
4
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢉ
+PVGTTWRVꢀ
8GEVQT
4
6JGUGꢀDKVUꢀCTGꢀKFGPVKECNꢀVQꢀDKVUꢀꢍꢌꢉꢀQHꢀ
VJGꢀNCVGUVꢀXCNWGꢀYTKVVGPꢀVQꢀ94ꢎꢄ
ꢊꢌꢂ
8GEVQTꢀQTꢀ
6[RGꢀ%QFG
4
+HꢀDKVꢀꢎꢀKPꢀEJCPPGNꢀ$ꢀ94ꢂꢀKUꢀꢃꢅꢀVJGUGꢀ
DKVUꢀCTGꢀKFGPVKECNꢀVQꢀDKVUꢀꢊꢌꢂꢀQHꢀVJGꢀ
NCVGUVꢀXCNWGꢀYTKVVGPꢀVQꢀ94ꢎꢄꢀ+HꢀDKVꢀꢎꢀKUꢀ
ꢂꢅꢀVJGUGꢀDKVUꢀKFGPVKH[ꢀVJGꢀJKIJGUVꢀ
RTKQTKV[ꢀKPVGTTWRVꢀRGPFKPIꢀKPꢀVJGꢀ5+1ꢀ
EJCPPGNUꢅꢀQTꢀꢃꢃꢂꢀKHꢀPQꢀKPVGTTWRVꢀKUꢀ
RGPFKPIꢈ
ꢃꢃꢃ %JCPPGNꢀ$ꢀ6TCPUOKVꢀꢐNQYGUVꢀRTKQTKV[ꢑ
ꢃꢃꢂ %JCPPGNꢀ$ꢀ'ZVGTPCNꢋ5VCVWU
ꢃꢂꢃ %JCPPGNꢀ$ꢀ4Zꢀ%JCTCEVGTꢀ#XCKNCDNG
ꢃꢂꢂ %JCPPGNꢀ$ꢀ5RGEKCNꢀ4GEGKXGꢀ%QPFKVKQP
%JCPPGNꢀ#ꢀ6TCPUOKV
ꢂꢃꢃ %JCPPGNꢀ#ꢀ'ZVGTPCNꢋ5VCVWU
ꢂꢃꢂ %JCPPGNꢀ#ꢀ4Zꢀ%JCTCEVGTꢀ#XCKNCDNG
ꢂꢂꢃ %JCPPGNꢀ#ꢀ5RGEKCNꢀ4GEGKXGꢀ%QPFKVKQP
ꢂꢂꢂ
ꢃ
8GEVQT
4
6JKUꢀDKVꢀKUꢀKFGPVKECNꢀVQꢀDKVꢀꢃꢀQHꢀVJGꢀ
NCVGUVꢀXCNWGꢀYTKVVGPꢀVQꢀ94ꢎꢄ
#5;0%ꢁ5'4+#.ꢁ%1//70+%#6+105ꢁ+06'4(#%'ꢁꢈ#5%+ꢉꢁ4')+56'45
See Async Serial Communications Interface (ASCI), which starts on page 95, for
more detail about these registers.
ꢂꢏꢏ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢋ1 4
6
ꢁꢄꢃꢐꢅ #5%+ꢃꢁ%
ꢁ4
ꢁ#ꢁꢈꢃꢃꢃꢃ*ꢉꢁ%06.#ꢃ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
/2'
4'
6'
465ꢃ /2$4ꢋ /1&ꢎ /1&ꢂ /1&ꢃ
'(4
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢂ
4ꢋ9
:
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4GUGV
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍ
/WNVKꢌ
2TQEGUUQTꢀ
/QFGꢀ
4ꢋ9
+HꢀVJKUꢀDKVꢀCPFꢀVJGꢀ/2ꢀDKVꢀKPꢀ%06.$ꢀCTGꢀ
DQVJꢀꢂꢅꢀQPN[ꢀTGEGKXGFꢀEJCTCEVGTUꢀ
JCXKPIꢀCꢀꢂꢀKPꢀCPꢀCFFKVKQPCNꢀDKVꢀ
'PCDNG
DGVYGGPꢀVJGꢀNCUVꢀFCVCꢀDKVꢀCPFꢀVJGꢀUVQRꢀ
DKVꢅꢀKUꢀRNCEGFꢀKPꢀVJGꢀ4Zꢀ(+(1ꢄꢀ+HꢀGKVJGTꢀ
VJGꢀ/2ꢀDKVꢀQTꢀVJKUꢀDKVꢀKUꢀꢃꢅꢀCNNꢀTGEGKXGFꢀ
EJCTCEVGTUꢀCTGꢀRNCEGFꢀKPꢀVJGꢀ4Zꢀ(+(1ꢄ
ꢏ
ꢆ
4GEGKXGꢀ
'PCDNG
4ꢋ9
4ꢋ9
4ꢋ9
#ꢀꢂꢀKPꢀVJKUꢀDKVꢀGPCDNGUꢀVJGꢀTGEGKXGTꢄꢀ
9TKVKPIꢀCꢀꢃꢀUWOOCTKN[ꢀUVQRUꢀTGEGRꢌ
VKQPꢄ
6TCPUOKVꢀ
'PCDNG
#ꢀꢂꢀKPꢀVJKUꢀDKVꢀGPCDNGUꢀVJGꢀVTCPUOKVVGTꢄꢀ
9TKVKPIꢀCꢀꢃꢀUWOOCTKN[ꢀUVQRUꢀVTCPUꢌ
OKUUKQPꢄ
ꢉ
ꢊ
465ꢃ
VJKUꢀDKVꢀEQPVTQNUꢀVJGꢀ465ꢃꢀQWVRWVꢄ
/2ꢀ$KVꢀ4EXꢋ 4ꢋ9
'TTQTꢀ(NCIꢀ
4GUGV
4GCFKPIꢀVJKUꢀDKVꢀTGVWTPUꢀVJGꢀXCNWGꢀQHꢀ
VJGꢀ OWNVKRTQEGUUQT ꢀDKVꢄꢀ4GCFꢀVJKUꢀ
TGIKUVGTꢀDGHQTGꢀTGCFKPIꢀVJGꢀ4&4ꢄꢀ
9TKVKPIꢀCꢀꢃꢀVQꢀVJKUꢀDKVꢀENGCTUꢀVJGꢀ
1840ꢅꢀ('ꢅꢀ2'ꢅꢀCPFꢀ$TGCMꢀ&GVGEVꢀDKVUꢄꢀ
9TKVKPIꢀCꢀꢂꢀJCUꢀPQꢀGHHGEVꢄ
ꢎ
ꢂ
ꢃ
/1&ꢎ
/1&ꢂ
/1&ꢃ
4ꢋ9
4ꢋ9
4ꢋ9
ꢃ
ꢂ
ꢍꢀDKVꢀFCVCꢀꢐ6ZꢀCPFꢀ4Zꢑ
ꢇꢀDKVꢀFCVC
ꢃ
ꢂ
0QꢀRCTKV[ꢀꢐ6ZꢀCPFꢀ4Zꢑ
2CTKV[ꢀIGPGTCVGFꢀꢐ6ZꢑꢅꢀEJGEMGFꢀꢐ4Zꢑ
ꢃ
ꢂ
ꢂꢀ5VQRꢀDKVꢀ6TCPUOKVVGF
ꢎꢀ5VQRꢀDKVUꢀ6TCPUOKVVGF
6
ꢁꢄꢃꢑꢅ #5%+ꢄꢁ%
ꢁ4
ꢁ#ꢁꢈꢃꢃꢃꢄ*ꢉꢁ%06.#ꢄ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
/2'
4'
6'
4GUGTX /2$4ꢋ /1&ꢎ /1&ꢂ /1&ꢃ
GF
4ꢋ9
ꢂ
'(4
4ꢋ9
:
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4GUGV
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢏꢍ
+ꢋ1 4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
All bits in this register are as described in the previous table.
6
ꢁꢄꢃꢂꢅ #5%+ꢃꢁ%
ꢁ4
ꢁ$ꢁꢈꢃꢃꢃꢆ*ꢉꢁ%06.$ꢃ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
&4
4ꢋ9
ꢃ
ꢎ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF /2$6
/2 %65ꢋ25 2'1
5RGGFꢀ5GNGEV
4ꢋ9
4GUGV
0
4ꢋ9
:
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢂ
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍ
/WNVKꢌ
2TQEGUUQTꢀ
$KVꢀ6Z
4ꢋ9
+HꢀVJGꢀ/2ꢀDKVꢀꢐPGZVꢑꢀKUꢀꢂꢅꢀVJKUꢀDKVꢀ
FGHKPGUꢀVJGꢀXCNWGꢀVQꢀUGPFꢀKPꢀVJGꢀ/2ꢀ
DKVꢀYKVJꢀVJGꢀPGZVꢀEJCTCEVGTꢀYTKVVGPꢀVQꢀ
VJGꢀ6TCPUOKVꢀ&CVCꢀ4GIKUVGTꢄ
ꢏ
/WNVKꢌꢀ
2TQEGUUQTꢀ
/QFG
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ#5%+ꢀUGPFUꢅꢀCPFꢀ
GZRGEVUꢀVQꢀTGEGKXGꢅꢀCPꢀGZVTCꢀDKVꢀCHVGTꢀ
VJGꢀNCUVꢀFCVCꢀDKVꢄꢀ6JKUꢀDKVꢀKUꢀꢂꢀVQꢀKFGPꢌ
VKH[ꢀCFFTGUUꢀEJCTCEVGTUꢀVJCVꢀDGIKPꢀ
HTCOGUꢅꢀQTꢀꢃꢀVQꢀKFGPVKH[ꢀHQNNQYKPIꢀ
FCVCꢀEJCTCEVGTUꢄ
ꢆ
%65ꢋ25
4ꢋ9
4GCFKPIꢀVJKUꢀRKPꢀTGVWTPUꢀVJGꢀUVCVGꢀQHꢀ
VJGꢀ%65ꢀRKPꢀꢐꢃꢒNQYꢅꢀꢂꢒJKIJꢑꢄꢀ(QTꢀ
YTKVKPIꢅꢀVJKUꢀDKVꢀKUꢀ25ꢄꢀ+HꢀDKVUꢀꢎꢌꢃꢀKPꢀVJKUꢀ
TGIKUVGTꢀCTGꢀPQVꢀꢂꢂꢂꢀCPFꢀVJGꢀ$4)ꢀ
/QFGꢀDKVꢀKPꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀ
TGIKUVGTꢀKUꢀꢃꢅꢀ25ꢀFGVGTOKPGUꢀYJGVJGTꢀ
VJGꢀ2*+ꢀENQEMꢀKUꢀ 2TGUECNGF ꢀD[ꢀꢂꢃꢀ
ꢐHQTꢀꢃꢑꢀQTꢀꢊꢃꢀꢐHQTꢀꢂꢑꢀCUꢀVJGꢀHKTUVꢀUVCIGꢀKPꢀ
#5%+ꢀENQEMKPIꢄ
ꢉ
2CTKV[ꢀ'XGPꢋ 4ꢋ9
1FF
+Hꢀ/1&ꢂꢀꢐ%06.#ꢀDKVꢀꢂꢑꢀKUꢀꢂꢅꢀVJKUꢀDKVUꢀ
UGNGEVUꢀYJGVJGTꢀRCTKV[ꢀKUꢀIGPGTCVGFꢀ
CPFꢀEJGEMGFꢀCUꢀGXGPꢀꢐHQTꢀꢃꢑꢀQTꢀQFFꢀ
ꢐHQTꢀꢂꢑꢄ
ꢂꢏꢇ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢋ1 4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢊ
&4
4ꢋ9
ꢃ
6JGꢀ#5%+ꢀFKXKFGUꢀVJGꢀKVUꢀDCUKEꢀENQEMꢀ
D[ꢀꢂꢏꢀVQꢀQDVCKPꢀKVUꢀDKVꢀTCVGꢄ
ꢂ
6JGꢀ#5%+ꢀFKXKFGUꢀVJGꢀKVUꢀDCUKEꢀENQEMꢀ
D[ꢀꢏꢉꢀVQꢀQDVCKPꢀKVUꢀDKVꢀTCVG
ꢎꢌꢃ
5RGGFꢀ
5GNGEV
4ꢋ9
ꢂꢂꢂ &QꢀPQVꢀRTQITCOꢀVJKUꢀXCNWGꢄ
ꢐQVJGTꢑ +HꢀVJGꢀ$4)ꢃꢀ/QFGꢀDKVꢀKUꢀꢂꢅꢀVJGꢀQWVRWVꢀ
QHꢀVJGꢀPGYꢀ$4)ꢀKUꢀVJGꢀDCUKEꢀENQEMꢀQHꢀ
VJGꢀ#5%+ꢄꢀ+Hꢀ$4)ꢃꢀ/QFGꢀKUꢀꢃꢅꢀVJGUGꢀ
DKVUꢀFGVGTOKPGꢀYJCVꢀVJGꢀQWVRWVꢀQHꢀVJGꢀ
2TGUECNGTꢀKUꢀFKXKFGFꢀD[ꢅꢀVQꢀQDVCKPꢀ
DCUKEꢀENQEMꢀHQTꢀVJGꢀ#5%+ꢈ
7UGFꢀCUꢀKU
ꢃꢃꢃ ꢋꢎ
ꢃꢃꢂ ꢋꢉ
ꢃꢂꢃ ꢋꢇ
ꢃꢂꢂ ꢋꢂꢏ
ꢂꢃꢃ ꢋꢊꢎ
ꢂꢃꢂ ꢋꢏꢉ
ꢂꢂꢃ +PꢀCP[ꢀECUGꢅꢀVJGꢀDCUKEꢀENQEMꢀKUꢀFKXKFGFꢀ
D[ꢀꢂꢏꢀQTꢀꢏꢉꢀVQꢀQDVCKPꢀVJGꢀ#5%+ꢀDKVꢀ
TCVGꢄ
6
ꢁꢄꢃꢓꢅ #5%+ꢄꢁ%
ꢁ4
ꢁ$ꢁꢈꢃꢃꢃꢌ*ꢉꢁ%06.$ꢄ
$KV
ꢍ
ꢏ
/2
4ꢋ9
ꢃ
ꢆ
ꢉ
ꢊ
&4
4ꢋ9
ꢃ
ꢎ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF /2$6
25
2'1
4ꢋ9
ꢃ
5RGGFꢀ5GNGEV
4ꢋ9
4GUGV
0
4ꢋ9
:
4ꢋ9
ꢃ
4ꢋ9
ꢂ
ꢂ
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
All bits in this register are as described in the preceding table, except that bit 5 has
no function in write operations on the Z80S188 ASCI1.
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢏꢁ
+ꢋ1 4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
6
ꢁꢄꢄꢃꢅ #5%+ꢃꢁ5
ꢁ4
ꢁꢈꢃꢃꢃꢎ*ꢉꢁ56#6ꢃ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
('
4
ꢊ
4+'
4ꢋ9
ꢃ
ꢎ
ꢂ
ꢃ
6+'
4ꢋ9
ꢃ
$KVꢋ(KGNF
4ꢋ9
4&4( 1840
2'
4
&%&ꢃ 6&4'
4
ꢃ
4
ꢃ
4
4
ꢃ
4GUGV
ꢃ
ꢃ
RKP
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍ
4&4(
4
6JGꢀ<ꢇꢃ5ꢂꢇꢇ UGVUꢀVJKUꢀDKVꢀYJGPꢀCꢀ
EJCTCEVGTꢀKUꢀTGEGKXGFꢄꢀ4GCFKPIꢀVJGꢀ
NCUVꢀTGEGKXGFꢀD[VGꢀHTQOꢀVJGꢀ4Zꢀ(+(1ꢀ
ENGCTUꢀVJKUꢀDKVꢄꢀ5GGꢀ0QVGꢀDGNQYꢄ
ꢏ
1840
4
6JKUꢀDKVꢀKUꢀUGVꢀYJGPꢀVJGꢀNCUVꢀEJCTCEVGTꢀ
TGEGKXGFꢀDGHQTGꢀCPꢀ1XGTTWPꢀEQPFKVKQPꢀ
EQOGUꢀVQꢀVJGꢀVQRꢀQHꢀVJGꢀ4Zꢀ(+(1ꢄꢀ+VꢀKUꢀ
ENGCTGFꢀYJGPꢀUQHVYCTGꢀYTKVGUꢀCꢀꢃꢀVQꢀ
VJGꢀ'(4ꢀDKVꢀKPꢀ%06.ꢃꢄꢀ5GGꢀ0QVGꢀ
DGNQYꢄ
ꢆ
ꢉ
2'
('
4
4
6JKUꢀDKVꢀKUꢀUGVꢀKHꢀRCTKV[ꢀKUꢀGPCDNGFꢅꢀCPFꢀ
CꢀEJCTCEVGTꢀYKVJꢀCꢀ2CTKV[ꢀ'TTQTꢀEQOGUꢀ
VQꢀVJGꢀVQRꢀQHꢀVJGꢀ4Zꢀ(+(1ꢄꢀ+VꢀKUꢀENGCTGFꢀ
YJGPꢀUQHVYCTGꢀYTKVGUꢀCꢀꢃꢀVQꢀVJGꢀ'(4ꢀ
DKVꢀKPꢀ%06.ꢃꢄꢀ5GGꢀ0QVGꢀDGNQYꢄ
6JKUꢀDKVꢀKUꢀUGVꢀKHꢀCꢀEJCTCEVGTꢀYKVJꢀCꢀ
(TCOKPIꢀ'TTQTꢀꢐQPGꢀKPꢀYJKEJꢀVJGꢀ5VQRꢀ
DKVꢀYCUꢀUCORNGFꢀCUꢀꢃꢑꢀEQOGUꢀVQꢀVJGꢀ
VQRꢀQHꢀVJGꢀ4Zꢀ(+(1ꢄꢀ+VꢀKUꢀENGCTGFꢀYJGPꢀ
UQHVYCTGꢀYTKVGUꢀCꢀꢃꢀVQꢀVJGꢀ'(4ꢀDKVꢀKPꢀ
%06.ꢃꢄꢀ5GGꢀ0QVGꢀDGNQYꢄ
ꢊ
ꢎ
4+'
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ#5%+ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀCP[ꢀQHꢀVJGꢀHNCIUꢀ
1840ꢅꢀ2'ꢅꢀ('ꢅꢀQTꢀ$TGCMꢀ&GVGEVꢀKUꢀUGVꢅꢀ
QTꢀKHꢀDKVꢀꢍꢀQHꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀ
TGIKUVGTꢀKUꢀꢃꢀCPFꢀ4&4(ꢀKUꢀUGVꢅꢀQTꢀKHꢀDKVꢀ
ꢏꢀQHꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀTGIKUVGTꢀKUꢀ
ꢃꢀCPFꢀ&%&ꢃꢀKUꢀ.QYꢄ
&%&ꢃ
4
6JKUꢀDKVꢀKUꢀꢂꢀYJGPGXGTꢀVJGꢀ&%&ꢃꢀRKPꢀ
KUꢀ*KIJꢄꢀ9JGPꢀ&%&ꢃꢀIQGUꢀ.QYꢅꢀVJGꢀ
PGZVꢀTGCFꢀQHꢀVJKUꢀTGIKUVGTꢀTGVWTPUꢀCꢀꢂꢅꢀ
DWVꢀVJGꢀPGZVꢀTGCFꢀTGVWTPUꢀCꢀꢃꢀKHꢀ&%&ꢃꢀ
KUꢀUVKNNꢀ.QYꢄꢀ4GUGVꢀUGVUꢀVJKUꢀDKVꢀ
CEEQTFKPIꢀVQꢀVJGꢀUVCVGꢀQHꢀVJGꢀRKPꢄ
ꢂꢍꢃ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢋ1 4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢂ
6&4'
4
6JKUꢀDKVꢀKUꢀENGCTGFꢀYJGPꢀUQHVYCTGꢀ
YTKVGUꢀCꢀEJCTCEVGTꢀVQꢀVJGꢀ6&4ꢄꢀ+VꢀKUꢀUGVꢀ
YJGPꢀVJGꢀEJCTCEVGTꢀNGCXGUꢀVJGꢀ6&4ꢀ
HQTꢀVTCPUOKUUKQPꢅꢀD[ꢀTGUGVꢅꢀCPFꢀKPꢀ+ꢋ1ꢀ
5612ꢀOQFGꢄꢀ+VꢀKUꢀENGCTGFꢀKHꢀDKVꢀꢆꢀQHꢀVJGꢀ
'ZVGPUKQPꢀ%QPVTQNꢀTGIKUVGTꢀKUꢀꢃꢀCPFꢀ
%65ꢃꢀKUꢀ*KIJꢄ
ꢃ
6+'
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ#5%+ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀ6&4'ꢀKUꢀꢂꢄ
0
ꢊꢁ6JGꢀ4&4(ꢅꢀ1840ꢅꢀ2'ꢅꢀCPFꢀ('ꢀDKVUꢀCTGꢀENGCTGFꢀD[ꢀ4GUGVꢅꢀFWTKPIꢀ+ꢋ1ꢀ5VQRꢀOQFGꢅꢀ
CPFꢀHQTꢀ#5%+ꢃꢅꢀKHꢀVJGꢀ&%&ꢀ&KUCDNGꢀDKVꢀKPꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀTGIKUVGTꢀKUꢀꢃꢀCPFꢀ&%&ꢃꢀ
KUꢀ*KIJꢄ
6
ꢁꢄꢄꢄꢅ #5%+ꢄꢁ5
ꢁ4
ꢁꢈꢃꢃꢃꢏ*ꢉꢁ56#6ꢄ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4&4( 1840
2'
('
4+'
4GUGTX 6&4'
GF
6+'
4ꢋ9
4
ꢃ
4
ꢃ
4
ꢃ
4
ꢃ
4ꢋ9
ꢃ
4
4
ꢃ
4ꢋ9
ꢃ
4GUGV
RKP
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
This register is as described in the previous Table, except that bit 2 has no function
on the Z80S188 ASCI1.
6
ꢁꢄꢄꢆꢅ #5%+ꢃꢁ6 ꢁ&
ꢁ4
ꢁꢈꢃꢃꢃꢐ*ꢉꢁ6&4ꢃ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%JCTCEVGTꢀVQꢀ6Z
9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
6ZꢀEJCTCEVGT 4ꢋ9
5QHVYCTGꢀECPꢀYTKVGꢀCꢀEJCTCEVGTꢀVQꢀDGꢀ
VTCPUOKVVGFꢀVQꢀVJKUꢀTGIKUVGTꢅꢀYJGPGXGTꢀ
VJGꢀ6&4'ꢀHNCIꢀKPꢀ56#6ꢃꢀKUꢀꢂꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢍꢂ
+ꢋ1 4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
6
ꢁꢄꢄꢌꢅ #5%+ꢄꢁ6 ꢁ&
ꢁ4
ꢁꢈꢃꢃꢃꢑ*ꢉꢁ6&4ꢄ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%JCTCEVGTꢀVQꢀ6Z
9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
6ZꢀEJCTCEVGT 4ꢋ9
5QHVYCTGꢀECPꢀYTKVGꢀCꢀEJCTCEVGTꢀVQꢀDGꢀ
VTCPUOKVVGFꢀVQꢀVJKUꢀTGIKUVGTꢅꢀYJGPGXGTꢀ
VJGꢀ6&4'ꢀHNCIꢀKPꢀ56#6ꢂꢀKUꢀꢂꢄ
6
ꢁꢄꢄꢎꢅ #5%+ꢃꢁ4 ꢁ&
ꢁ4
ꢁꢈꢃꢃꢃꢂ*ꢉꢁ4&4ꢃ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
4GEGKXGFꢀ%JCTCEVGT
4
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
4ZꢀEJCTꢌ
CEVGT
4ꢋ9
9JGPGXGTꢀVJGꢀ4&4(ꢀHNCIꢀKPꢀ56#6ꢃꢀKUꢀ
ꢂꢅꢀUQHVYCTGꢀECPꢀTGCFꢀCꢀTGEGKXGFꢀEJCTꢌ
CEVGTꢀHTQOꢀVJKUꢀTGIKUVGTꢄ
6
ꢁꢄꢄꢏꢅ #5%+ꢄꢁ4 ꢁ&
ꢁ4
ꢁꢈꢃꢃꢃꢓ*ꢉꢁ4&4ꢄ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
4GEGKXGFꢀ%JCTCEVGT
4
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
4ZꢀEJCTꢌ
CEVGT
4ꢋ9
9JGPGXGTꢀVJGꢀ4&4(ꢀHNCIꢀKPꢀ56#6ꢂꢀKUꢀ
ꢂꢅꢀUQHVYCTGꢀECPꢀTGCFꢀCꢀTGEGKXGFꢀEJCTꢌ
CEVGTꢀHTQOꢀVJKUꢀTGIKUVGTꢄ
ꢂꢍꢎ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢋ1 4
6
ꢁꢄꢄꢐꢅ #5%+ꢃꢁ'
ꢁ%
ꢁ4
ꢁꢈꢃꢃꢄꢆ*ꢉꢁ#5':6ꢃ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4&+& &%&ꢃꢀ %65ꢃꢀ
:ꢂꢀ
$4)ꢀ 5VCTVꢀ+'
4Z
6Z
&KUCDNG &KUCDNG %NQEM /QFG
$TGCM $TGCMꢋ
6Z'PF
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4
ꢃ
4ꢋ9
ꢃ
4GUGV
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍ
4Zꢀ&CVCꢀ
+PVGTTWRVꢀ
&KUCDNG
4ꢋ9
+Hꢀ4+'ꢀꢐ56#6ꢀDKVꢀꢊꢑꢀCPFꢀVJKUꢀDKVꢀCTGꢀ
DQVJꢀꢂꢅꢀVJGꢀ#5%+ꢀTGSWGUVUꢀTGEGKXGꢀ
KPVGTTWRVUꢀQPN[ꢀYJGPꢀ1840ꢅꢀ2'ꢅꢀQTꢀ
('ꢀKUꢀUGVꢄꢀ+Hꢀ4+'ꢀKUꢀꢂꢀCPFꢀVJKUꢀDKVꢀKUꢀꢃꢅꢀ
KPVGTTWRVUꢀCTGꢀCNUQꢀTGSWGUVGFꢀYJGPꢀ
4&4(ꢀKUꢀUGVꢀꢐHQTꢀGCEJꢀTGEGKXGFꢀEJCTꢌ
CEVGTꢑꢄꢀ+Hꢀ4+'ꢀKUꢀꢃꢀVJKUꢀDKVꢀJCUꢀPQꢀGHHGEVꢄ
ꢏ
ꢆ
ꢉ
&%&ꢃꢀ
&KUCDNG
4ꢋ9
4ꢋ9
4ꢋ9
ꢃ
ꢂ
&%&ꢃꢀCWVQꢌGPCDNGUꢀVJGꢀTGEGKXGT
&%&ꢃꢀJCUꢀPQꢀGHHGEVꢀQPꢀVJGꢀTGEGKXGT
%65ꢃꢀ
&KUCDNG
ꢃ
ꢂ
%65ꢃꢀCWVQꢌGPCDNGUꢀVJGꢀVTCPUOKVVGT
%65ꢃꢀJCUꢀPQꢀGHHGEVꢀQPꢀVJGꢀVTCPUOKVVGT
:ꢂꢀ%NQEM
$4)ꢀ/QFG
5VCTVꢀ+'
ꢃ
6JGꢀENQEMꢀQPꢀVJGꢀ%-#ꢃꢀRKPꢀKUꢀFKXKFGFꢀ
D[ꢀꢂꢏꢀQTꢀꢏꢉꢀVQꢀQDVCKPꢀVJGꢀ#5%+ꢀDKVꢀ
ENQEMꢄ
6JGꢀENQEMꢀQPꢀVJGꢀ%-#ꢃꢀRKPꢀKUꢀWUGFꢀCUꢀ
VJGꢀ#5%+ꢀDKVꢀENQEMꢄ
ꢂ
ꢊ
ꢎ
4ꢋ9
4ꢋ9
ꢃ
ꢂ
6JGꢀ55ꢀDKVUꢀFGVGTOKPGꢀVJGꢀHCEVQTꢀD[ꢀ
YJKEJꢀVJGꢀ2TGUECNGTꢀQWVRWVꢀKUꢀFKXKFGFꢅꢀ
VQꢀQDVCKPꢀVJGꢀ#5%+ UꢀDCUKEꢀENQEMꢄ
6JGꢀ#5%+ UꢀDCUKEꢀENQEMꢀEQOGUꢀHTQOꢀ
VJGꢀPGYꢀ$4)ꢄ
+HꢀVJKUꢀDKVꢀCPFꢀ4+'ꢀCTGꢀDQVJꢀꢂꢅꢀVJGꢀ#5%+ꢀ
TGSWGUVUꢀCPꢀKPVGTTWRVꢀYJGPꢀKVꢀFGVGEVUꢀ
VJGꢀUVCTVꢀQHꢀCꢀUVCTVꢀDKVꢅꢀHQTꢀCWVQꢌ
DCWFKPIꢄꢀ9TKVKPIꢀCꢀꢃꢀVQꢀVJKUꢀDKVꢀCHVGTꢀ
UWEJꢀCPꢀKPVGTTWRVꢀQEEWTUꢅꢀENGCTUꢀVJGꢀ
5VCTV+'ꢀKPVGTTWRVꢀTGSWGUVꢄꢀ
ꢂ
4Z$TGCM
4
6JKUꢀDKVꢀKUꢀꢂꢀKHꢀVJGꢀTGEGKXGTꢀJCUꢀ
FGVGEVGFꢀCꢀ$TGCMꢀEQPFKVKQPꢅꢀVJCVꢀKUꢅꢀKHꢀ
CNNꢀDKVUꢀKPꢀCꢀEJCTCEVGTꢅꢀKPENWFKPIꢀVJGꢀ
UVQRꢀDKVꢅꢀCTGꢀꢃꢄꢀ6JGꢀCNNꢌꢃꢀEJCTCEVGTꢀKUꢀ
RNCEGFꢀKPꢀVJGꢀ4Zꢀ(+(1ꢀKHꢀVJGTGꢀKUꢀ
URCEGꢅꢀDWVꢀVJGꢀTGEGKXGTꢀFQGUꢀPQVꢀ
CUUGODNGꢀCP[ꢀOQTGꢀEJCTCEVGTUꢀWPVKNꢀ
VJGꢀ4Z#ꢀRKPꢀTGVWTPUꢀVQꢀ*KIJꢄ
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢍꢊ
+ꢋ1 4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
4ꢋ9
ꢃ
6Z$TGCMꢋ
6Z'PF
9TKVKPIꢀCꢀꢂꢀVQꢀVJKUꢀDKVꢀOCMGUꢀVJGꢀ
VTCPUOKVVGTꢀFTKXGꢀ6:#ꢀ.QYꢀVQꢀUGPFꢀCꢀ
$TGCMꢀEQPFKVKQPꢅꢀWPVKNꢀUQHVYCTGꢀYTKVGUꢀ
CꢀꢃꢀVQꢀVJKUꢀDKVꢄꢀ6JKUꢀDKVꢀTGCFUꢀCUꢀꢃꢀ
YJKNGꢀCꢀEJCTCEVGTꢀKUꢀDGKPIꢀVTCPUꢌ
OKVVGFꢅꢀDWVꢀIQGUꢀVQꢀꢂꢀYJGPꢀVJGꢀ
PWODGTꢀQHꢀUVQRꢀDKVUꢀUGNGEVGFꢀD[ꢀ
/1&ꢃꢀKPꢀ%06.#ꢀJCXGꢀDGGPꢀUGPVꢄ
6
ꢁꢄꢄꢑꢅ #5%+ꢄꢁ'
ꢁ%
ꢁ4
ꢁꢈꢃꢃꢄꢌ*ꢉꢁ#5':6ꢄ
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4&+&
4GUGTXGF
:ꢂꢀ
%NQEM /QFG
$4)ꢀ 5VCTVꢀ+'
4Z
6Z
$TGCM $TGCMꢋ
6Z'PF
4ꢋ9
4ꢋ9
ꢃ
0ꢋ#
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4
ꢃ
4ꢋ9
ꢃ
4GUGV
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
This register is as described in the previous table, except that bits 6–5have no
function for Z80S188 ASCI1.
6
ꢁꢄꢄꢂꢅ #5%+ꢃꢁ6 ꢁ%
ꢁ. ꢁꢈꢃꢃꢄ#*ꢉꢁ#56%ꢃ.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
.5ꢀD[VGꢀQHꢀ
6KOGꢀ
4ꢋ9
6JGꢀ.5ꢀꢇꢀDKVUꢀQHꢀVJGꢀ#5%+ꢃꢀ$CWFꢀ4CVGꢀ
)GPGTCVQT Uꢀ6KOGꢀ%QPUVCPVꢄ
%QPUVCPV
ꢂꢍꢉ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢋ1 4
6
ꢁꢄꢄꢓꢅ #5%+ꢃꢁ6 ꢁ%
ꢁ* ꢁꢈꢃꢃꢄ$*ꢉꢁ#56%ꢃ*
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
/5ꢀ$[VGꢀQHꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
/5ꢀ$[VGꢀQHꢀ 4ꢋ9
6KOGꢀ
6JGꢀ/5ꢀꢇꢀDKVUꢀQHꢀVJGꢀ#5%+ꢃꢀ$CWFꢀ4CVGꢀ
)GPGTCVQT Uꢀ6KOGꢀ%QPUVCPVꢄ
%QPUVCPV
6
ꢁꢄꢆꢃꢅ #5%+ꢄꢁ6 ꢁ%
ꢁ. ꢁꢈꢃꢃꢄ%*ꢉꢁ#56%ꢄ.
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
.5ꢀ$[VGꢀQHꢀ
6KOGꢀ
4ꢋ9
6JGꢀ.5ꢀꢇꢀDKVUꢀQHꢀVJGꢀ#5%+ꢂꢀ$CWFꢀ4CVGꢀ
)GPGTCVQT Uꢀ6KOGꢀ%QPUVCPVꢄ
%QPUVCPV
6
ꢁꢄꢆꢄꢅ #5%+ꢄꢁ6 ꢁ%
ꢁ* ꢁꢈꢃꢃꢄ&*ꢉꢁ#56%ꢄ*
$KV
ꢍ
ꢏ
ꢆ
ꢉ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
/5ꢀ$[VGꢀQHꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍꢌꢃ
/5ꢀ$[VGꢀQHꢀ 4ꢋ9
6KOGꢀ
6JGꢀ/5ꢀꢇꢀDKVUꢀQHꢀVJGꢀ#5%+ꢂꢀ$CWFꢀ4CVGꢀ
)GPGTCVQT Uꢀ6KOGꢀ%QPUVCPVꢄ
%QPUVCPV
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢂꢍꢆ
+ꢋ1 4
%
ꢀ5
ꢀ+ꢋ1ꢀꢐ%5+ꢋ1ꢑꢀ4
%.1%-'&ꢁ5'4+#.ꢁ+ꢋ1ꢁꢈ%5+ꢋ1ꢉꢁ4')+56'45
See the section “Clocked Serial Input/Output Module (CSI/O)”, on page 106, for
more about these registers.
6
ꢁꢄꢆꢆꢅ ꢁ%5+ꢋ1ꢁ%
ꢁ4
ꢁꢈꢃꢃꢃ#*ꢉꢁ%064
$KV
ꢍ
ꢏ
'+'
4ꢋ9
ꢃ
ꢆ
ꢉ
6'
4ꢋ9
ꢃ
ꢊ
ꢎ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
'(
4
4'
5RGGFꢀ5GNGEVꢀꢐ55ꢑ
4ꢋ9
4ꢋ9
ꢃ
0ꢋ#
:
4GUGV
ꢃ
ꢂ
ꢂ
ꢂ
0
ꢊꢁ4ꢀꢒꢀ4GCFꢀ9ꢀꢒꢀ9TKVGꢀ:ꢀꢒꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢍ
'PFꢀ(NCIꢀ
ꢐ'(ꢑ
4
6JGꢀ%5+ꢋ1ꢀUGVUꢀVJKUꢀDKVꢀVQꢀꢂꢀYJGPꢀKVꢀ
EQORNGVGUꢀUGPFKPIꢀQTꢀTGEGKXKPIꢀCꢀ
D[VGꢄꢀ+VꢀENGCTUꢀVJKUꢀDKVꢀYJGPꢀUQHVYCTGꢀ
TGCFUꢀQTꢀYTKVGUꢀVJGꢀ64&4ꢅꢀQPꢀ4GUGVꢀ
CPFꢀFWTKPIꢀ+ꢋ1ꢀ5VQRꢀOQFGꢄ
ꢏ
ꢆ
'PFꢀ+PVGTꢌ
TWRVꢀ'PCDNGꢀ
ꢐ'+'ꢑ
4ꢋ9
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ%5+ꢋ1ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀKVꢀEQORNGVGUꢀUGPFKPIꢀ
QTꢀTGEGKXKPIꢀCꢀD[VGꢀCPFꢀUGVUꢀ'(ꢄ
4GEGKXGꢀ
'PCDNGꢀꢐ4'ꢑ
9TKVGꢀCꢀꢂꢀVQꢀVJKUꢀDKVꢀVQꢀUVCTVꢀCꢀ%5+ꢋ1ꢀ
TGEGKXGꢀQRGTCVKQPꢄꢀ+HꢀVJGꢀ55ꢀDKVUꢀCTGꢀ
ꢂꢂꢂꢅꢀVJGꢀ%5+ꢋ1ꢀYCKVUꢀHQTꢀꢇꢀENQEMꢀ
RWNUGUꢀQPꢀ%-5ꢅꢀQVJGTYKUGꢀKVꢀQWVRWVUꢀꢇꢀ
ENQEMꢀRWNUGUꢀQPꢀ%-5ꢄꢀ+PꢀGKVJGTꢀECUGꢅꢀKVꢀ
ENQEMUꢀFCVCꢀQPꢀ4:5ꢀKPVQꢀVJGꢀ64&4ꢀ
CHVGTꢀGCEJꢀHCNNKPIꢀGFIGꢀQPꢀ%-5ꢄꢀ#HVGTꢀ
ECRVWTKPIꢀVJGꢀꢇVJꢀDKVꢅꢀKVꢀENGCTUꢀVJKUꢀDKVꢀ
CPFꢀUGVUꢀ'(ꢄ
ꢉ
6TCPUOKVꢀ
'PCDNGꢀꢐ6'ꢑ
4ꢋ9
9TKVGꢀCꢀꢂꢀVQꢀVJKUꢀDKVꢀVQꢀUVCTVꢀ%5+ꢋ1ꢀ
VTCPUOKUUKQPꢄꢀ+HꢀVJGꢀ55ꢀDKVUꢀCTGꢀꢂꢂꢂꢅꢀ
VJGꢀ%5+ꢋ1ꢀYCKVUꢀHQTꢀꢇꢀENQEMꢀRWNUGUꢀQPꢀ
%-5ꢅꢀQVJGTYKUGꢀKVꢀQWVRWVUꢀꢇꢀENQEMꢀ
RWNUGUꢀQPꢀ%-5ꢄꢀ+PꢀGKVJGTꢀECUGꢅꢀKVꢀ
ENQEMUꢀFCVCꢀQPVQꢀ6:5ꢀCHVGTꢀGCEJꢀ
HCNNKPIꢀGFIGꢀQPꢀ%-5ꢄꢀ#HVGTꢀUGPFKPIꢀꢇꢀ
DKVUꢅꢀVJGꢀ%5+ꢋ1ꢀENGCTUꢀVJKUꢀDKVꢀCPFꢀUGVUꢀ
'(ꢄ
ꢂꢍꢏ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
%
ꢀ5
ꢀ+ꢋ1ꢀꢐ%5+ꢋ1ꢑꢀ4
+
5
$KV
2QUKVKQP $KVꢋ(KGNF
4ꢋ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
5RGGFꢀ
5GNGEVꢀꢐ55ꢑ
4ꢋ9
+HꢀVJGUGꢀDKVUꢀCTGꢀꢂꢂꢂꢅꢀCUꢀVJG[ꢀCTGꢀCHVGTꢀ
Cꢀ4GUGVꢅꢀVJGꢀ%5+ꢋ1ꢀVCMGUꢀGZVGTPCNꢀ
ENQEMKPIꢀHTQOꢀVJGꢀ%-5ꢀRKPꢄꢀ1VJGTꢌ
YKUGꢅꢀKVꢀFTKXGUꢀCꢀENQEMꢀQPVQꢀ%-5ꢅꢀVJCVꢀ
KVꢀFGTKXGUꢀHTQOꢀ2*+ꢀCUꢀHQNNQYUꢈ
ꢃꢃꢃ 2*+ꢋꢎꢃ
ꢃꢃꢂ 2*+ꢋꢉꢃ
ꢃꢂꢃ 2*+ꢋꢇꢃ
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6
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ꢍꢌꢃ
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CNNQYKPIꢀVJGꢀ%5+ꢋ1ꢀVQꢀUGPFꢀKVꢄꢀ5QHVꢌ
YCTGꢀTGCFUꢀCꢀTGEGKXGFꢀD[VGꢀHTQOꢀVJKUꢀ
TGIKUVGTꢅꢀCHVGTꢀVJGꢀ%5+ꢋ1ꢀUGVUꢀVJGꢀ'(ꢀ
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The Z80S188 includes the 8S180 processor, which is descended from the ZiLOG
Z80. Its 8-bit data bus and 23-bit address space fit well into a wide variety of mid-
range embedded processing applications, providing significantly more computing
power than a microcontroller, at a fraction of the system cost of a larger micropro-
cessor.
For details of these instructions see the Z80S188 User Manual, or the Z8S180 or
Z80185 User Manuals until the Z80S188 UM is available.
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The following Figure shows the Flags register. Bits in this register are set and
cleared by certain instructions as described in the Z80S188 User Manual. Some of
the Flags can be tested by conditional JR, JP, CALL, and RET instructions, and
ꢂꢇꢃ
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%
ꢀ%
+
5
some are used by subsequent instructions such as ADC, SBC, and DAA. The
Flags can also have PUSH and POP instructions applied to them with the accumu-
lator A.
6
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ꢁ4
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5
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%(
%10&+6+10ꢁ%1&'5
Table 135 shows the codes used in the “Flags Affected” columns of the later
Instruction Summary Table, to indicate how each Flag is affected by each type of
instruction.
6
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8
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The following table shows the condition codes that can be used in conditional JP,
CALL, and RETinstructions in assembly language. A subset of these codes can
also be used in JRinstructions, which are shorter and faster than JP’s.
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;
;
;
;
0
0
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0
0
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2ꢋ8ꢀꢒꢀꢂ
2ꢋ8ꢀꢒꢀꢃ
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0
+
5
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The following table describes other notation used in the subsequent Instruction
Summary table.
6
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5[ODQN
ꢐCCꢑ
&GHKPKVKQP
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D[ꢀCꢀTGIKUVGTꢀRCKT
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EE
EE
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F
GG
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+'(ꢂꢅꢎ
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TWRVU ꢀUGEVKQPꢀHQTꢀOQTGꢀFGVCKNꢄ
OP
#ꢀꢂꢏꢌDKVꢀKOOGFKCVGꢀFCVCꢀXCNWGꢀQTꢀFKTGEVꢀCFFTGUU
P
#ꢀꢇꢌDKVꢀKOOGFKCVGꢀXCNWGꢀQTꢀRQTVꢀPWODGTꢅꢀꢃ ꢎꢆꢆ*ꢀQTꢀꢃ ((*
QRꢂ QRꢎ
#ꢀTCPIGꢀQHꢀ1Rꢀ%QFGꢀXCNWGUꢅꢀVJCVꢀKPENWFGUꢀUQOGꢀQHꢀVJGꢀ
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2%
RR
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2TQITCOꢀ%QWPVGT
#ꢀꢂꢏꢌDKVꢀTGIKUVGTꢀ$%ꢅꢀ&'ꢅꢀ*.ꢅꢀ52ꢅꢀ+:ꢅꢀ+;ꢅꢀQTꢀ#(
#PꢀꢇꢌDKVꢀTGIKUVGTꢀ#ꢅꢀ$ꢅꢀ%ꢅꢀ&ꢅꢀ'ꢅꢀ*ꢅꢀQTꢀ.ꢄ
#ꢀꢂꢏꢌDKVꢀTGIKUVGTꢀ*.ꢅꢀ+:ꢅꢀQTꢀ+;ꢄ
U
52
UU
CPꢀꢇꢌDKVꢀTGIKUVGTꢀQTꢀOGOQT[ꢀNQECVKQP
5VCEMꢀ2QKPVGT
#ꢀꢂꢏꢌDKVꢀTGIKUVGTꢀ$%ꢅꢀ&'ꢅꢀ*.ꢅꢀQTꢀ52ꢄ
6JGꢀOQTGꢌꢀCPFꢀNGUUꢌUKIPKHKECPVꢀꢇꢀDKVUꢀQHꢀCꢀTGIKUVGTꢀRCKT
UU ꢅꢀUU
VV
#ꢀꢂꢏꢌDKVꢀTGIKUVGTꢀNKMGꢀUUꢅꢀGZEGRVꢀVJCVꢀVJGꢀXCNWGꢀVJCVꢀFGUKIꢌ
PCVGUꢀ*.ꢀKPꢀVJGꢀUUꢀGPEQFKPIꢅꢀJGTGꢀOGCPUꢀ UCOGꢀCUꢀVJGꢀ
FGUVKPCVKQPꢀTGIKUVGTꢀ*.ꢅꢀ+:ꢅꢀQTꢀ+; ꢄ
0
ꢊ The – between Op Codes (op1–op2), in the Op Codes column of the
following Instruction Summary table, indicates all the binary values between the
lower and upper limits inclusive, that can be formed by incrementing the set of
bits that differ between the lower and upper value.
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0
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Stresses greater than those listed below may cause permanent damage to the
device. These are stress ratings only; proper operation of the device at any condi-
tion above those indicated in the operational sections of these specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
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Unless otherwise noted, the DC and AC characteristics in this document are
measured under standard test conditions that include the load circuit described in
Figure 24. This circuit closely mimics the loading presented by active devices
such as memories and peripheral devices.
All voltages are referenced to the Vss pins (ground, 0V). Positive current flows
into the referenced pin.
All AC parameters assume a load capacitance of 100 pF. See “Characteristic
Curves” on page 226 for the effect of lesser or greater total capacitance on the
timing. AC timing measurements are referenced to the high and low voltage
thresholds given in the DC specifications, as indicated in Figures 25 through 40.
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25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢎꢎꢆ
5
ꢁ&
ꢁ%
%
ꢀ%
%*#4#%6'4+56+%ꢁ%748'5
20
16
12
8
G
I
F
G
ꢀ
I
P
K
N
N
C
(
G
I
F
G
ꢀ
I
P
K
U
K
4
4
0
-4
-8
25
50
75
100
ꢎꢂꢅ %
125
ꢁ.
150
175
200
225
250
275 pF
(
ꢁ% ꢁ ꢅꢁ5
ꢁ6
5;56'/ꢁ&'5+)0ꢁ%105+&'4#6+105
'44#6#
The following errata apply to revision AB of the Z80S188, which is identified by a
0in the Device Revision register, I/O address 003DH.
5EJOKVVꢁ6TKIIGTU
The RESET, NMI, ZCL and ZDA pins are specified to include Schmitt triggers,
but these were not included on Rev AB. The 50 mS max rise and fall time speci-
fied for RESET thus becomes much shorter, 50 nS or less. Since RESET is an
open-drain output, perhaps the best work around is to simply connect a pullup
resistor, and not drive RESET externally.
0Qꢁ46%ꢁ#NCTO
The Alarm function of the Real Time Clock is not operative.
294596%*ꢁ0GICVKXGꢁ.QIKE
The PWRSWTCH pin is specified as positive logic, but in Rev AB is implemented
as negative logic (1 is Low, 0 is High).
1WVRWVꢁ%QPVTQNꢁ4GIKUVGTꢁ4GUGV
The OCR is specified to reset to 0xx0 0000, but instead resets to 0xx1 1000.
0Qꢁ4GUGVꢁ(TQOꢁ12/1&ꢄ
A rising edge on OPMOD1 does not trigger a Power On Reset sequence.
ꢎꢎꢏ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
< .1)ꢀ&
ꢀ+
#
ꢁ0
ꢋ&
ꢁ6
2+15ꢁ2QTVꢁ+PKVKCNK\CVKQP
246ꢁ4CEGꢁ%QPFKVKQP
The Programmable I/O Sequencer enables Port C outputs when it is enabled. Soft-
ware needs to define the state of Port C outputs before enabling the PIOS, by writ-
ing to the Port C Data Register.
If software writes to the PRT Reload registers while the PRT is operating, and a
write coincides with a window near the end of the PRT’s countdown cycle, the
down counter may end up reloaded with the wrong value.
ꢏꢃꢋꢐꢃꢁ*\ꢁ46%ꢁ%NQEMꢁ6CMGPꢁ(TQOꢁ9TQPIꢁ2KP
The RTC specs read that if bit 4 of the RTC Control/Status Register is 1, the RTC
takes a 50- or 60-Hz clock from the PC0 pin. Rev AB makes the frequency adjust-
ment when this bit is 1, but takes the clock from LFEXTAL, as when the bit is 0.
4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁ5VCVGꢁ+PFGVGTOKPCVGꢁ#HVGTꢁ4GUGV
The Register Write Enable state that is readable as bit 0 of the Watch-Dog Timer
Master register is specified to reset to 1. However, its value is indeterminate after
power up and unchanged by other Resets. Reset-initialization software writes a
0BH to the Watch-Dog Timer Command Register to set this bit, before writing
any of the System Configuration, Power Control, Port Data Direction, or Real
Time Clock registers.
%5+ꢋ1ꢁ%NQEMꢁ2KPꢁ&KTGEVKQPꢁ4GXGTUGF
The tri-state control signal for the CKS pin is inverted. Thus when
the CSI/O module thinks the pin should be an input, the pad is driving
out, and vice-versa. This renders the CSI/O unusable in any mode.
#22.+%#6+10ꢁ016'5ꢋ&'8'.12/'06ꢁ611.5
<+.1)ꢁ&'$7)ꢁ+06'4(#%'
The Z80S188 includes this serial interface to allow ZiLOG and third-party devel-
opment systems and emulators to control and monitor the processor and other on-
chip resources, during application development and debugging. This two-wire
interface is intended to be a standard feature of ZiLOG processors developed in
the future, eliminating the need for expensive and cumbersome pods and clip-on
emulation equipment.
In order to use the ZiLOG Developer Studio (ZDS) or equivalent equipment with
an application or target board, include a standard right angle, 0.1 in spaced, 0.025
in square post, 6-pin header on the board (Berg P/N 75867-131 or equivalent).
Connect the ZCL and ZDA pins of the Z80S188 to pins 4 and 6 of this header as
illustrated in Figure 49, which is a top view of the board.
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢎꢎꢍ
1
+
< .1)ꢀ&
ꢀ+
VDD
Z80S188
1
3
5
4
6
ZCL
ZDA
10K
GND
90
91
ZDA
ZCL
(
ꢎꢓꢅ <&+ꢁ%
ꢁ
ꢁ6
ꢁ$
14&'4+0) +0(14/#6+10
<ꢂꢃ5ꢄꢂꢂꢁꢈꢌꢌꢁ/*\ꢉ
5VCPFCTFꢁ6GORGTCVWTG
ꢂꢏꢃꢀ2KPꢀ3(2
<ꢇꢃ5ꢂꢇꢇꢊꢊ#5%4ZZZZ
'ZVGPFGFꢁ6GORGTCVWTG
ꢂꢏꢃꢀ2KPꢀ3(2
<ꢇꢃ5ꢂꢇꢇꢊꢊ#'%4ZZZZ
<ꢂꢃ.ꢄꢂꢂꢁꢈꢆꢃꢁ/*\ꢉ
5VCPFCTFꢁ6GORGTCVWTG
ꢂꢏꢃꢀ2KPꢀ3(2
<ꢇꢃ.ꢂꢇꢇꢎꢃ#5%4ZZZZ
'ZVGPFGFꢁ6GORGTCVWTG
ꢂꢏꢃꢀ2KPꢀ3(2
<ꢇꢃ.ꢂꢇꢇꢎꢃ#'%4ZZZZ
For fast results, contact your local ZiLOG sale offices for assistance in ordering
the part(s) desired.
ꢎꢎꢇ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
2
ꢀ0
ꢀ&
1
+
2#46ꢁ07/$'4ꢁ&'5%4+26+10
ZiLOG part numbers consist of a number of components.
ꢊꢁ
'
Part number Z80S188 33 A S C, a Z80S188, 33 MHz, Quad Flat Pack, 0° to 70°
C, Plastic Standard Flow, is made up of the codes described in the following table.
<
<K.1)ꢀ2TGHKZ
2TQFWEVꢀ0WODGT
5RGGF
<ꢇꢃ5ꢂꢇꢇ
ꢊꢊ
#
2CEMCIG
5
6GORGTCVWTG
'PXKTQPOGPVCNꢀ(NQY
%
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢎꢎꢁ
1
+
2
ꢀ0
ꢀ&
<+.1)ꢁ<ꢂꢃ5ꢄꢂꢂꢁ%1&'ꢁ57$/+55+10ꢁ(14/
To submit a ROM Code:
1. Complete ROM code submission form.
2. E-mail this form and the hex file (in Intel Hex format) as separate attachments
to: codes@ZiLOG.com
%QORCP[ꢀ0COGꢈ
&KUV[ꢋ5WDEQPꢈ
&CVGꢈꢀAAAAAAAA
<K.1)ꢀ2ꢋ0ꢈꢀAAAAAAAAAAAAAAAAAAAAAAAA
%JGEMUWOꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAA ꢀꢃꢃ
2CEMCIGꢀ%QFGꢀ.GIGPFꢈꢀ
AAAAAAAAAAAA
4'8ꢈꢀꢐ+PRWVꢀD[ꢀ
<K.1)
ꢐ+PRWVꢀD[ꢀ<K.1)
%QORCP[ꢀ2ꢋ0ꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAꢀ(KNGꢀ2ꢀ+PRWVꢈꢀAAAAAAAAAAAAAAA
'ZRGEVGFꢀ#PPWCNꢀ8QNWOGꢀKPꢀ7PKVUꢈꢀAAAAAA
#RRNKECVKQPꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
5RGEKCNꢀ+PUVTWEVKQPUꢈꢀꢐ1RVKQPCNꢑAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
<K.1)ꢀ5CNGUꢀ1HHKEGꢀꢐQTꢀ[QWTꢀEKV[ꢀCPFꢀEQWPVT[ꢑꢈꢀAAAAAAAAAAAAAAAAAAAAAꢀAAAAAAAAAAA
5GPFꢀ41/ꢀXGTKHKECVKQPꢀVQꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
2JQPGꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
'ꢌOCKNꢀCFFTGUUꢈꢀAAAAAAAAAAAAAAA (CZꢈꢀAAAAAAAAAAA
6QꢀUWDOKVꢀCꢀVQROCTMꢈ
ꢂꢄ %JGEMꢀDQZꢀHQTꢀFGHCWNVꢀQTꢀEWUVQOꢀHQTꢀVJGꢀRTGHGTTGFꢀRCEMCIGꢄ
ꢎꢄ 1PꢀFGHCWNVꢅꢀꢁꢁꢁꢁꢀKPFKECVGUꢀ41/ꢀPWODGTꢀCUUKIPGFꢀVQꢀRCTVꢀD[ꢀ<K.1)ꢄ
ꢊꢄ +HꢀEWUVQOꢀVQROCTMꢀKUꢀUGNGEVGFꢅꢀGPVGTꢀEJCTCEVGTUꢀKPꢀVJGꢀURCEGꢀRTQXKFGFꢄ
<K.1)ꢀCFFUꢀVJGꢀFCVGꢀEQFGꢀꢐFGUETKDGFꢀDGNQYꢀCUꢀ::;;ꢀ$$ꢑꢀCUꢀDQVVQOꢀNKPG
CPFꢀCNKIPꢀCUꢀFGUETKDGFꢀQPꢀFGHCWNVꢀVQROCTMꢄ
ꢉꢄ +HꢀCNNꢀVJGꢀNKPGUꢀQPꢀCꢀEWUVQOꢀVQROCTMꢀCTGꢀPQVꢀWUGFꢅꢀNGCXGꢀVJGꢀVQRꢀNKPGꢀDNCPMꢄ
ꢆꢄ (QTꢀ ꢀꢐ6TCFGOCTMꢑꢀU[ODQNꢅꢀRNCEGꢀNQYGTECUGꢀtmꢄ
ꢏꢄ (QTꢀlꢀꢐ%QR[TKIJVꢑꢀU[ODQNꢅꢀRNCEGꢀNQYGTECUGꢀcꢀHQNNQYGFꢀD[ꢀCꢀURCEGꢄ
ꢍꢄ (QTꢀEWUVQOꢀNQIQꢅꢀCVVCEJꢀCꢀ$/2ꢅꢀ,2')ꢀQTꢀ)+(ꢀHKNGꢀVQꢀVJKUꢀHQTOꢄ
ꢇꢄ 6QꢀWUGꢀ<K.1)ꢀKPꢀCꢀEWUVQOꢀVQROCTMꢅꢀV[RGꢀpZiLOGꢄꢀ6JGꢀpꢀKUꢀCꢀRNCEGOCTM
HQTꢀVJGꢀ<K.1)ꢀPCOGꢄ
6JGꢁ<ꢁNQIQꢁKUꢁWUGFꢁYJGPꢁCRRNKECDNGꢄ
3(2ꢀꢂꢏꢃꢀ2KP
&GHCWNV
%WUVQO
ꢂꢂꢀEJCTꢀOCZ
ꢎꢊꢃ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
2
ꢀ2
&
&+5%.#+/'4
©1999 by ZiLOG, Inc. All rights reserved. Information in this publication
concerning the devices, applications, or technology described is intended to
suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCU-
RACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME
LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECH-
NOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express
written approval of ZiLOG, use of information, devices, or technology as critical
components of life support systems is not authorized. No licenses are conveyed,
implicitly or otherwise, by this document under any intellectual property rights.
24'%*#4#%6'4+<#6+10ꢁ241&7%6
The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or non-
conformance with some aspects of the document may be found, either by ZiLOG
or its customers in the course of further application and characterization work. In
addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up
yield issues.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX 408 558-8300
Internet: HTTP://WWW.ZILOG.COM
&1%7/'06ꢁ+0(14/#6+10
%*#0)'ꢁ.1)
4GX
&CVG
2WTRQUG
$[
ꢃꢃ
ꢃꢁꢁꢁ
1TKIKPCNꢀKUUWG
IICODNG
25ꢃꢃꢂꢆꢃꢃꢌ</2ꢃꢁꢁꢁ
<ꢇꢃ5ꢂꢇꢇꢀꢌꢀ24'.+/+0#4;
ꢎꢊꢂ
24'.+/+0#4;
+
Capacitance . . . . . . . . . . . . . . . . . . . . . . 214
CCF instruction . . . . . . . . . . . . . . . . . . . 185
Channels
Counter/Timer (CTC). . . . . . . . . . . . . 63
DMA. . . . . . . . . . . . . . . . . . . . . . . . . 57
Characteristics
Curves. . . . . . . . . . . . . . . . . . . . . . . 227
Electrical . . . . . . . . . . . . . . . . . . . . . 200
Chip Select Decoding for IOCS pin . . . . . . 39
Circuits
Fundamental mode crystal . . . . . . . . . 42
Third-overtone crystal . . . . . . . . . . . . 42
Clock, CSI/O selection . . . . . . . . . . . . . . 106
Clocking
#
AC characteristics
Extended temperature range . . . . . . 209
Normal temperature range . . . . . . . . 203
ADC instruction . . . . . . . . . . . . . . . . . . 184
ADD instruction . . . . . . . . . . . . . . . . . . 184
Addressing modes . . . . . . . . . . . . . . . . . 30
alarm, RTC . . . . . . . . . . . . . . . . . . . . . 227
AND instruction . . . . . . . . . . . . . . . . . . 185
application notes/development tools . . . . 228
Arithmetic instructions. . . . . . . . . . . . . . 178
ASCI
ASCI interrupts . . . . . . . . . . . . . . . . 103
Basic clocking. . . . . . . . . . . . . . . . . . 95
Baud rate generator (BRG). . . . . . . . . 95
Clock mode. . . . . . . . . . . . . . . . . . . . 96
Clocking summary. . . . . . . . . . . . . . . 98
DMA operation . . . . . . . . . . . . . . . . 101
Multiprocessor mode . . . . . . . . . . . . 104
Operation . . . . . . . . . . . . . . . . . . . . . 86
Options. . . . . . . . . . . . . . . . . . . . . . . 99
Polled reception. . . . . . . . . . . . . . . . 103
Polled transmission . . . . . . . . . . . . . 103
Programming techniques . . . . . . . . . 102
Reception . . . . . . . . . . . . . . . . . . . . . 97
Status . . . . . . . . . . . . . . . . . . . . . . . 100
Timing diagram. . . . . . . . . . . . . . . . 223
Transmission. . . . . . . . . . . . . . . . . . . 97
Circuits . . . . . . . . . . . . . . . . . . . . . . . 41
Crystal specifications . . . . . . . . . . . . . 42
Divide by 2 option 41
Multiply by 2 option. . . . . . . . . . . . . . 41
Reduced oscillator drive option . . . . . . 42
Reset conditions. . . . . . . . . . . . . . . . . 43
Sample rate . . . . . . . . . . . . . . . . . . . . 98
Summary . . . . . . . . . . . . . . . . . . . . . . 98
Condition codes . . . . . . . . . . . . . . . . . . . 181
Configuration, MMU . . . . . . . . . . . . . . . . 32
Control timing diagram. . . . . . . . . . . . . . . 37
Counter/Timer Channel
Addresses and registers. . . . . . . . . . . . 64
Channel Control register . . . . . . . . . . . 64
Down Counter . . . . . . . . . . . . . . . . . . 65
Interrupt priority daisy chaining . . . . . 66
Interrupt Vector register . . . . . . . . . . . 65
Interrupts . . . . . . . . . . . . . . . . . . . . . . 65
Software sequences . . . . . . . . . . . . . . 66
Time Constant register . . . . . . . . . . . . 65
CP instruction . . . . . . . . . . . . . . . . . . . . 185
CPD instruction . . . . . . . . . . . . . . . . . . . 185
CPDR instruction . . . . . . . . . . . . . . . . . . 185
CPI instruction . . . . . . . . . . . . . . . . . . . . 185
CPIR instruction. . . . . . . . . . . . . . . . . . . 185
CPL instruction . . . . . . . . . . . . . . . . . . . 186
Crystal
$
Basic
Device registers. . . . . . . . . . . . . . . . 111
Timing diagram. . . . . . . . . . . . . . . . 215
Baud rate generator (BRG). . . . . . . . . . . . 95
BIT
Instruction. . . . . . . . . . . . . . . . . . . . 185
Manipulation instructions. . . . . . . . . 179
Block transfer instructions . . . . . . . . . . . 179
Bus exchange timing diagram. . . . . . . . . 219
Byte
Reception . . . . . . . . . . . . . . . . . . . . 108
Transmission. . . . . . . . . . . . . . . . . . 107
Circuits . . . . . . . . . . . . . . . . . . . . . . . 41
Specifications. . . . . . . . . . . . . . . . . . . 42
CSI/O
%
Byte reception . . . . . . . . . . . . . . . . . 108
Byte transmission. . . . . . . . . . . . . . . 107
Cancelling transmission or reception 108
CALL instruction . . . . . . . . . . . . . . . . . 185
Cancel CSI/O transmission or reception . 108
PS001500-ZMP0999
Z80S188
233
+
24'.+/+0#4;
%ꢁꢈ%
ꢉ
'
CSI/O (Continued)
EI instruction . . . . . . . . . . . . . . . . . . . . . 186
Electrical characteristics
Clock selection . . . . . . . . . . . . . . . . 106
Interrupts . . . . . . . . . . . . . . . . . . . . 108
Operation . . . . . . . . . . . . . . . . . . . . 106
Timing diagram. . . . . . . . . . . . . . . . 223
CTC, Timing diagram . . . . . . . . . . . . . . 226
Absolute maximum ratings . . . . . . . . 200
AC characteristics . . . . . . . . . . . . . . 203
Capacitance . . . . . . . . . . . . . . . . . . . 214
Characteristic curves. . . . . . . . . . . . . 227
DC characteristics . . . . . . . . . . . . . . 201
Standard test conditions . . . . . . . . . . 200
Test load circuit . . . . . . . . . . . . . . . . 201
Errata . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Exchange instructions. . . . . . . . . . . . . . . 178
External status interrupts. . . . . . . . . . . . . . 94
EXX instruction . . . . . . . . . . . . . . . . . . . 186
&
DAA instruction . . . . . . . . . . . . . . . . . . 186
Daisy chain signalling . . . . . . . . . . . . . . . 19
DAR0 registers . . . . . . . . . . . . . . . . . . . . 60
DC characteristics
Extended temperature range . . . . . . . 202
Normal temperature range . . . . . . . . 201
DEC instruction. . . . . . . . . . . . . . . . . . . 186
Description
General. . . . . . . . . . . . . . . . . . . . . . . . 1
Part number . . . . . . . . . . . . . . . . . . 230
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Destination
And source registers (DAR, SAR) . . . 57
Mode DMA0. . . . . . . . . . . . . . . . . . . 61
DI instruction . . . . . . . . . . . . . . . . . . . . 186
Diagram, pin . . . . . . . . . . . . . . . . . . . . . . . 4
Disclaimer . . . . . . . . . . . . . . . . . . . . . . 232
DJNZ instruction. . . . . . . . . . . . . . . . . . 186
DMA
Async operation . . . . . . . . . . . . . . . .101
Basics. . . . . . . . . . . . . . . . . . . . . . . . 57
Channel completion. . . . . . . . . . . . . . 62
Channels. . . . . . . . . . . . . . . . . . . . . . 57
Edge- vs. level-senstive requests. . . . . 58
Edge-sense request timing . . . . . . . . . 59
Edge-sensitive request . . . . . . . . . . . 101
Handling interrupts . . . . . . . . . . . . . . 63
Interrupts . . . . . . . . . . . . . . . . . . . . . 59
Level-sense request timing. . . . . . . . . 58
Memory-to-memory modes . . . . . . . . 59
Reception . . . . . . . . . . . . . . . . . . . . . .93
Request timing diagram . . . . . . . . . . .221
Requests . . . . . . . . . . . . . . . . . . . . . . 58
Setting up a transfer. . . . . . . . . . . . . . 60
Termination timing diagram. . . . . . . 221
Transmission. . . . . . . . . . . . . . . . . . . 93
DSTAT register. . . . . . . . . . . . . . . . . . . . 57
(
Features of the Z80S188 . . . . . . . . . . . . . . . 1
Flag settings definitions . . . . . . . . . . . . . 181
Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
)
*
General description. . . . . . . . . . . . . . . . . . . 1
Halt 180
And I/O Stop mode. . . . . . . . . . . . . . . 44
Instruction . . . . . . . . . . . . . . . . . . . . 186
Mode. . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing diagram . . . . . . . . . . . . . . . . 222
+
I register . . . . . . . . . . . . . . . . . . . . . . . . . 16
I/O
Memory address registers (IAR, MAR) 57
Chip select high 127
Read timing diagram 218
Stop mode 44
Idle mode. . . . . . . . . . . . . . . . . . . . . . . . . 45
IL register . . . . . . . . . . . . . . . . . . . . . . . . . s 16
Illegal instruction traps . . . . . . . . . . . . . . . 13
IM instruction . . . . . . . . . . . . . . . . . . . . 186
IN A instruction . . . . . . . . . . . . . . . . . . . 186
IN instruction. . . . . . . . . . . . . . . . . . . . . 186
IN0 instruction . . . . . . . . . . . . . . . . . . . . 186
INC instruction. . . . . . . . . . . . . . . . . . . . 186
IND instruction . . . . . . . . . . . . . . . . . . . 187
234
Z80S188
PS001500-ZMP0999
24'.+/+0#4;
+
Interrupt (Continued)
+ꢁꢈ%
ꢉ
Timing diagram . . . . . . . . . . . . . . . . 220
Trap control register 17
Interrupt-driven
Reception . . . . . . . . . . . . . . . . . . . . . 92
Transmission . . . . . . . . . . . . . . . . . . . 91
IORQ and RD . . . . . . . . . . . . . . . . . . . . . 40
ITC register . . . . . . . . . . . . . . . . . . . . . . . 17
INDR instruction . . . . . . . . . . . . . . . . . . 187
INI instruction. . . . . . . . . . . . . . . . . . . . 187
INIR instruction . . . . . . . . . . . . . . . . . . 187
Input/Output
Central I/O waits . . . . . . . . . . . . . . . . 40
Chip select . . . . . . . . . . . . . . . . . . . . 39
I/O cycle timing diagram . . . . . . . . . . 41
I/O instructions . . . . . . . . . . . . . . . . . 38
IORQ and RD timing. . . . . . . . . . . . . 40
Relocating the 80180 registers . . . . . . 38
Space . . . . . . . . . . . . . . . . . . . . . . . . 37
Input/output
,
.
JP instruction . . . . . . . . . . . . . . . . . . . . . 187
JR instruction. . . . . . . . . . . . . . . . . . . . . 187
Instructions . . . . . . . . . . . . . . . . . . . 180
Instruction
LD instruction . . . . . . . . . . . . . . . . . . . . 187
LDD instruction . . . . . . . . . . . . . . . . . . . 188
LDI instruction. . . . . . . . . . . . . . . . . . . . 188
LDIR instruction . . . . . . . . . . . . . . . . . . 189
Load instructions . . . . . . . . . . . . . . . . . . 178
Logic, negative. . . . . . . . . . . . . . . . . . . . 227
Logical instructions . . . . . . . . . . . . . . . . 178
Low power modes . . . . . . . . . . . . . . . . . . 43
Classes . . . . . . . . . . . . . . . . . . . . . . 178
Input/Output . . . . . . . . . . . . . . . . . . . 38
Notation . . . . . . . . . . . . . . . . . . . . . 183
RET . . . . . . . . . . . . . . . . . . . . . . . . . 26
RET . . . . . . . . . . . . . . . . . . . . . . . . . . .I 26
RETI Bit 6 (M1TE) . . . . . . . . . . . . . . 27
RETI Bit 7 (M1E) . . . . . . . . . . . . . . . 26
Set . . . . . . . . . . . . . . . . . . . . . . . . . 177
Summary . . . . . . . . . . . . . . . . . . . . 184
INT0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mode 0 timing diagram . . . . . . . . . . . 22
Mode 1 timing diagram . . . . . . . . . . . 23
Mode 2 timing diagram . . . . . . . . . . . 26
modes. . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupt
/
Mark state . . . . . . . . . . . . . . . . . . . . . . . . 97
Maskable interrupt requests. . . . . . . . . . . . 16
Maximum ratings . . . . . . . . . . . . . . . . . . 200
Memcs0-1, size/enable values . . . . . . . . . . 35
Memory (ROM and RAM)
Addressing modes . . . . . . . . . . . . . . . 30
Clocking . . . . . . . . . . . . . . . . . . . . . . 41
DRAM refresh . . . . . . . . . . . . . . . . . . 36
Acknowledge timing diagram. . . . . . 221
ASCI . . . . . . . . . . . . . . . . . . . . . . . 103
ASCI, PRT, DMA,CSI/O, and ZDI. . . 28
CSI/O . . . . . . . . . . . . . . . . . . . . . . . 108
CTC . . . . . . . . . . . . . . . . . . . . . . . . . 65
DMA . . . . . . . . . . . . . . . . . . . . . . . . 59
External/Status . . . . . . . . . . . . . . . . . 94
Maskable requests . . . . . . . . . . . . . . . 16
Non-maskable . . . . . . . . . . . . . . . 17, 62
Offsets and priorities . . . . . . . . . . . . . 29
PIO. . . . . . . . . . . . . . . . . . . . . . . . . . 49
Priority . . . . . . . . . . . . . . . . . . . . . . 118
PRT . . . . . . . . . . . . . . . . . . . . . . . . . 71
External memory
with exernal decoding. . . . . . . . . . 35
External, using MEMSC0-1 . . . . . . . . 34
Input/output space . . . . . . . . . . . . . . . 37
Memory Management Unit (MMU). . . 31
On-chip RAM . . . . . . . . . . . . . . . . . . 34
On-chip ROM . . . . . . . . . . . . . . . . . . 34
Structure . . . . . . . . . . . . . . . . . . . . . . 29
Wait state generator . . . . . . . . . . . . . . 36
Memory and I/O address registers
(MAR, IAR . . . . . . . . . . . . . . . . . . . . . ) 57
Relative priority of PIOs, SIO,
Memory Management Unit (MMU). . . . . . 31
Memory read timing diagram . . . . . . . . . 216
Memory write timing diagram. . . . . . . . . 217
Memory-to-memory modes. . . . . . . . . . . . 59
and CTC . . . . . . . . . . . . . . . . . . . 20
Resources in the Z80S188 . . . . . . . . . 16
SIO. . . . . . . . . . . . . . . . . . . . . . . . . . 85
PS001500-ZMP0999
Z80S188
235
+
24'.+/+0#4;
OTDR instruction. . . . . . . . . . . . . . . . . . 189
OTIM instruction . . . . . . . . . . . . . . . . . . 189
OTIMR instruction. . . . . . . . . . . . . . . . . 189
OTIR instruction . . . . . . . . . . . . . . . . . . 190
OUT instruction . . . . . . . . . . . . . . . . . . . 190
OUT0 instruction . . . . . . . . . . . . . . . . . . 190
OUTD instruction. . . . . . . . . . . . . . . . . . 190
OUTI instruction . . . . . . . . . . . . . . . . . . 190
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . 1
/ꢁꢈ%
ꢉ
MLT instruction . . . . . . . . . . . . . . . . . . 189
Mode
0 output timing diagram. . . . . . . . . . . 47
1 input timing diagram. . . . . . . . . . . . 48
2 bidirectional timing diagram . . . . . . 48
3 bit control timing . . . . . . . . . . . . . . 49
Async clock . . . . . . . . . . . . . . . . . . . 96
Async multiprocessor . . . . . . . . . . . 104
Destination DMA0 . . . . . . . . . . . . . . 61
Halt . . . . . . . . . . . . . . . . . . . . . . . . . 44
Halt and I/O . . . . . . . . . . . . . . . . . . . 44
I/O Stop . . . . . . . . . . . . . . . . . . . . . . 44
Idle . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low power . . . . . . . . . . . . . . . . . . . . 43
Memory-to-memory . . . . . . . . . . . . . 59
Nine-bit . . . . . . . . . . . . . . . . . . . . . 104
Normal . . . . . . . . . . . . . . . . . . . . . . . 44
Operating DMA1. . . . . . . . . . . . . . . . 62
Sleep . . . . . . . . . . . . . . . . . . . . . . . . 44
Source, DMA0 . . . . . . . . . . . . . . . . . 61
Standby . . . . . . . . . . . . . . . . . . . . . . 45
Standby with quick recovery . . . . . . . 45
System Stop . . . . . . . . . . . . . . . . . . . 44
2
Part number description . . . . . . . . . . . . . 230
Pin description . . . . . . . . . . . . . . . . . . . . . . 4
PIO
Addresses . . . . . . . . . . . . . . . . . . . . . 46
DMA channels . . . . . . . . . . . . . . . . . . 57
Interrupt control word. . . . . . . . . . . . . 46
Interrupts . . . . . . . . . . . . . . . . . . . . . . 49
Mode 0 (output) timing diagram . . . . 224
Mode 1 (input) timing diagram . . . . . 224
Mode 2 (bidirectional) timing diagram 225
Mode 3 (bit control) timing diagram 225
Mode control word . . . . . . . . . . . . . . . 46
Operation modes . . . . . . . . . . . . . . . . 46
Output control words . . . . . . . . . . . . . 46
Registers . . . . . . . . . . . . . . . . . . . . . . 45
Reset . . . . . . . . . . . . . . . . . . . . . . . . . 56
Software sequences . . . . . . . . . . . . . . 50
PIOS port 1 initialization . . . . . . . . . . . . 228
Polled reception . . . . . . . . . . . . . . . . . . . . 90
POP instruction . . . . . . . . . . . . . . . . . . . 190
Power management . . . . . . . . . . . . . . . . . 43
Precharacterization . . . . . . . . . . . . . . . . . 232
Processor control instructions . . . . . . . . . 180
Processor description
0
1
NEG instruction . . . . . . . . . . . . . . . . . . 189
Nine-bit mode . . . . . . . . . . . . . . . . . . . . 104
Non-maskable interrupt . . . . . . . . . . . . . . 62
Non-maskable interrupt (NMI) . . . . . . . . . 17
NOP instruction. . . . . . . . . . . . . . . . . . . 189
Normal low power mode . . . . . . . . . . . . . 44
Op code map
Control registers. . . . . . . . . . . . . . . . . 12
Flags . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O space . . . . . . . . . . . . . . . . . . . . . . 12
Interrupt high address register (I). . . . . 13
Memory Management Unit (MMU). . . 12
Program Counter (PC) . . . . . . . . . . . . 13
Program registers . . . . . . . . . . . . . . . . 12
Rcounter register (R) . . . . . . . . . . . . . 13
Stack Pointer (SP) . . . . . . . . . . . . . . . 13
Processor flags . . . . . . . . . . . . . . . . . . . . 180
Program control instuctions. . . . . . . . . . . 179
Programming techniques. . . . . . . . . . . . . 102
1st op code . . . . . . . . . . . . . . . . . . . 193
2nd op code after OCBH . . . . . . . . . .194
2nd op code after ODDH . . . . . . . . . .195
2nd op code after OEDH . . . . . . . . . .196
2nd op code after OFDH . . . . . . . . . .197
4th byte after ODDH, OCBH, and D. .198
4th byte after OFDH, OCBH, and D . .199
OR instruction. . . . . . . . . . . . . . . . . . . . 189
Ordering information. . . . . . . . . . . . . . . 229
Oscillator drive . . . . . . . . . . . . . . . . . . . . 42
OTDM instruction . . . . . . . . . . . . . . . . .189
OTDMR instruction. . . . . . . . . . . . . . . . 189
236
Z80S188
PS001500-ZMP0999
24'.+/+0#4;
+
Register (Continued)
2ꢁꢈ%106+07'&ꢉ
PRT
Processor control . . . . . . . . . . . . . . . . 12
R counter (R) . . . . . . . . . . . . . . . . . . . 13
Refresh control. . . . . . . . . . . . . . . . . . 36
Relocating the 80180 . . . . . . . . . . . . . 38
SAR0, DAR0. . . . . . . . . . . . . . . . . . . 60
SIO Read. . . . . . . . . . . . . . . . . . . . . . 81
SIO Write . . . . . . . . . . . . . . . . . . . . . 73
Source and destination (SAR, DAR) . . 57
Summary . . . . . . . . . . . . . . . . . . . . . 109
Time Constant . . . . . . . . . . . . . . . . . . 65
Handling interrupts . . . . . . . . . . . . . . 71
Operation . . . . . . . . . . . . . . . . . . . . . 71
Reset . . . . . . . . . . . . . . . . . . . . . . . . 72
Starting. . . . . . . . . . . . . . . . . . . . . . . 70
Stopping . . . . . . . . . . . . . . . . . . . . . . 70
Timing diagram. . . . . . . . . . . . . . . . 223
PRT race condition. . . . . . . . . . . . . . . . . . . 228
PUSH instruction. . . . . . . . . . . . . . . . . . 190
3
4
Register, ASCI
ASCI 0 Rx data . . . . . . . . . . . . . . . . 172
ASCI0 control . . . . . . . . . . . . . . . . . 167
ASCI0 control B. . . . . . . . . . . . . . . . 168
ASCI0 extension control. . . . . . . . . . 173
ASCI0 status . . . . . . . . . . . . . . . . . . 170
ASCI0 time constant high . . . . . . . . . 175
ASCI0 time constant low . . . . . . . . . 174
ASCI0 time constatn high . . . . . . . . . 175
ASCI0 Tx data . . . . . . . . . . . . . . . . . 171
ASCI1 control A . . . . . . . . . . . . . . . 168
ASCI1 control B. . . . . . . . . . . . . . . . 169
ASCI1 extension control. . . . . . . . . . 174
ASCI1 Rx data. . . . . . . . . . . . . . . . . 172
ASCI1 status . . . . . . . . . . . . . . . . . . 171
ASCI1 time constant low . . . . . . . . . 175
ASCI1 Tx data . . . . . . . . . . . . . . . . . 172
Register, basic device
Clock multiplier . . . . . . . . . . . . . . . . 112
CPU control. . . . . . . . . . . . . . . . . . . 113
Free-running counte . . . . . . . . . . . . . 111
I/O control . . . . . . . . . . . . . . . . . . . . 115
On-chip memory control. . . . . . . . . . 115
Operating mode control . . . . . . . . . . 114
Refresh control . . . . . . . . . . . . . . . . 114
Register, chip select and wait
Quick recovery (standby) mode . . . . . . . . 45
RAM Protect option. . . . . . . . . . . . . . . . . 15
Receiver, Async 102
Reception
Async . . . . . . . . . . . . . . . . . . . . . . . . 97
DMA . . . . . . . . . . . . . . . . . . . . . . . . 93
Interrupt-driven . . . . . . . . . . . . . . . . . 92
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Control register . . . . . . . . . . . . . . . . . 36
DRAM . . . . . . . . . . . . . . . . . . . . . . . 36
Timing diagram (2-clock cycle . . . . . 221
Register . . . . . . . . . . . . . . . . . . . . . . . . 111
Addresses . . . . . . . . . . . . . . . . . . . . 110
Bank Area (BAR) . . . . . . . . . . . . . . . 32
Bank Base (BBR) . . . . . . . . . . . . . . . 32
Bank Base High and Low . . . . . . . . . 32
Channel Control . . . . . . . . . . . . . . . . 64
Clock Multiplier (CMR). . . . . . . . . . . 41
Common Area (CAR. . . . . . . . . . . . . .) 32
Common Base (CBR) . . . . . . . . . . . . 32
Common base area (CBAR) . . . . . . . . 32
Common Base High and Low . . . . . . 32
DSTAT. . . . . . . . . . . . . . . . . . . . . . . 57
Chip select and wait . . . . . . . . . . . . . 127
I/O chip select low . . . . . . . . . . . . . . 127
Memory chip select 0 high . . . . . . . . 125
Memory chip select 0 low . . . . . . . . . 123
Memory chip select 1 high . . . . . . . . 126
Memory chip select 1 low . . . . . . . . . 125
Register, CSI/O
I
. . . . . . . . . . . . . . . . . . . . . . . . . . 16
IL . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input/Output Chip Select High
and Low. . . . . . . . . . . . . . . . . . . . . 39
Interrupt High address (I . . . . . . . . . . .) 13
Interrupt Vector. . . . . . . . . . . . . . . . . 65
Interrupt/trap control . . . . . . . . . . . . . 17
ITC. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory and I/O address (MAR, IAR) 57
On-chip memory control . . . . . . . . . . 34
PIO. . . . . . . . . . . . . . . . . . . . . . . . . . 45
CSI/O control. . . . . . . . . . . . . . . . . . 176
CSI/O data. . . . . . . . . . . . . . . . . . . . 177
PS001500-ZMP0999
Z80S188
237
+
24'.+/+0#4;
Register, PRT
R (Continued)
Register, CTC
PRT0 reload high . . . . . . . . . . . . . . . 148
PRT0 reload low . . . . . . . . . . . . . . . 147
PRT0 timer data low. . . . . . . . . . . . . 147
PRT1 reload high . . . . . . . . . . . . . . . 151
PRT1 reload low . . . . . . . . . . . . . . . 151
PRT1 timer data high . . . . . . . . . . . . 150
PTRT0 timer data high . . . . . . . . . . . 147
Timer control . . . . . . . . . . . . . . . . . . 148
Timer prescale . . . . . . . . . . . . . . . . . 150
CTC0 . . . . . . . . . . . . . . . . . . . . . . . 144
CTC2 . . . . . . . . . . . . . . . . . . . . . . . 146
CTC3 . . . . . . . . . . . . . . . . . . . . . . . 146
Register, DMA
DMA mode. . . . . . . . . . . . . . . . . . . 141
DMA status. . . . . . . . . . . . . . . . . . . 140
DMA/wait control . . . . . . . . . . . . . . 142
DMA0 byte count high . . . . . . . . . . 135
DMA0 byte count low . . . . . . . . . . . 135
DMA0 destination address B . . . . . . 134
DMA0 destination address high . . . . 134
DMA0 destination address low. . . . . 133
DMA0 source address B . . . . . . . . . 133
DMA0 source address high . . . . . . . 132
DMA0 source address low . . . . . . . . 132
DMA1 byte count high . . . . . . . . . . 139
DMA1 byte count low . . . . . . . . . . . 139
DMA1 I/O address B . . . . . . . . . . . . 137
DMA1 I/O address high. . . . . . . . . . 137
DMA1 I/O address low . . . . . . . . . . 136
DMA1 memoory address B . . . . . . . 136
DMA1 memory address high . . . . . . 136
DMA1 memory address low. . . . . . . 135
Register, interrupt . . . . . . . . . . . . . . . . . 118
Interrupt vector low . . . . . . . . . . . . . 116
Trap control . . . . . . . . . . . . . . . . . . 117
Register, MMU
Register, SIO
RR0. . . . . . . . . . . . . . . . . . . . . . . . . 160
RR1. . . . . . . . . . . . . . . . . . . . . . . . . 163
SIO A control. . . . . . . . . . . . . . . . . . 152
SIO A data. . . . . . . . . . . . . . . . . . . . 152
SIO B control. . . . . . . . . . . . . . . . . . 165
SIO B data . . . . . . . . . . . . . . . . . . . . 165
SIO B rr2. . . . . . . . . . . . . . . . . . . . . 166
SIO B wr2 . . . . . . . . . . . . . . . . . . . . 165
WR0 . . . . . . . . . . . . . . . . . . . . . . . . 154
WR1 . . . . . . . . . . . . . . . . . . . . . . . . 155
WR3 . . . . . . . . . . . . . . . . . . . . . . . . 156
WR4 . . . . . . . . . . . . . . . . . . . . . . . . 157
WR5 . . . . . . . . . . . . . . . . . . . . . . . . 158
WR6 . . . . . . . . . . . . . . . . . . . . . . . . 159
WR7 . . . . . . . . . . . . . . . . . . . . . . . . 160
Register, WDT
Master . . . . . . . . . . . . . . . . . . . . . . . 143
Watch-Dog Timer command . . . . . . . 143
Requests
Bank area . . . . . . . . . . . . . . . . . . . . 121
Bank base . . . . . . . . . . . . . . . . . . . . 119
Bank base high, extended mode . . . . 123
Bank base low, extended mode. . . . . 122
Common area, extended mode . . . . . 122
Common base . . . . . . . . . . . . . . . . . 118
Common base high . . . . . . . . . . . . . 121
Common base low . . . . . . . . . . . . . .120
Common/bank area . . . . . . . . . . . . . 120
Register, PIO
DMA. . . . . . . . . . . . . . . . . . . . . . . . . 58
Edge vs. level sensitive . . . . . . . . . . . . 58
RES instruction . . . . . . . . . . . . . . . . . . . 190
Reset
Conditions . . . . . . . . . . . . . . . . . . . . . 43
Watch-Dog timer . . . . . . . . . . . . . . . . 43
None from OPMOD1 . . . . . . . . . . . . 227
Output control register . . . . . . . . . . . 227
RET instruction
INT0 mode 2 timing . . . . . . . . . . . . . . 26
Instruction summary. . . . . . . . . . . . . 190
RETI instruction
Bit 6 (M1TE) . . . . . . . . . . . . . . . . . . . 27
Bit 7 (M1E) . . . . . . . . . . . . . . . . . . . . 26
Timing with M1E=0 . . . . . . . . . . . . . . 27
RETN instruction . . . . . . . . . . . . . . . . . . 190
RL instruction . . . . . . . . . . . . . . . . . . . . 191
Port A control . . . . . . . . . . . . . . . . . 128
Port A data . . . . . . . . . . . . . . . . . . . 128
Port B control . . . . . . . . . . . . . . . . . 130
Port B data . . . . . . . . . . . . . . . . . . . 129
Port C control . . . . . . . . . . . . . . . . . 131
Port C data . . . . . . . . . . . . . . . . . . . 131
Port D control . . . . . . . . . . . . . . . . . 131
Port D data . . . . . . . . . . . . . . . . . . . 131
238
Z80S188
PS001500-ZMP0999
24'.+/+0#4;
+
R (Continued)
6
RLA instruction. . . . . . . . . . . . . . . . . . . 191
RLC instruction. . . . . . . . . . . . . . . . . . . 191
RLCA instruction . . . . . . . . . . . . . . . . . 191
RLD instruction. . . . . . . . . . . . . . . . . . . 191
ROM Protect option. . . . . . . . . . . . . . . . . 15
ROMCS device . . . . . . . . . . . . . . . . . . . . 34
ROMless option . . . . . . . . . . . . . . . . . . . 15
Rotate and shift instructions . . . . . . . . . . 179
RR instruction . . . . . . . . . . . . . . . . . . . . 191
RRA instruction . . . . . . . . . . . . . . . . . . 191
RRC instruction. . . . . . . . . . . . . . . . . . . 191
RRCA instruction . . . . . . . . . . . . . . . . . 191
RRD instruction . . . . . . . . . . . . . . . . . . 191
RST instruction . . . . . . . . . . . . . . . . . . . 191
Test load circuit . . . . . . . . . . . . . . . . . . . 201
Timing diagrams
ASCI. . . . . . . . . . . . . . . . . . . . . . . . 223
Basic . . . . . . . . . . . . . . . . . . . . . . . 215
Bus exchange. . . . . . . . . . . . . . . . . . 219
Control timing diagram. . . . . . . . . . . . 37
CSI/O . . . . . . . . . . . . . . . . . . . . . . . 223
CTC . . . . . . . . . . . . . . . . . . . . . . . . 226
DMA request . . . . . . . . . . . . . . . . . . 221
CSI/O . . . . . . . . . . . . . . . . . . . . . . . 223
CTC . . . . . . . . . . . . . . . . . . . . . . . . 226
DMA Request . . . . . . . . . . . . . . . . . 221
DMA termination. . . . . . . . . . . . . . . 221
DMA Transmission . . . . . . . . . . . . . . 93
Edge-sense request . . . . . . . . . . . . . . . 59
Halt . . . . . . . . . . . . . . . . . . . . . . . . . 222
I/O cycle . . . . . . . . . . . . . . . . . . . . . . 41
I/O read timing. . . . . . . . . . . . . . . . . 218
I/O write timing. . . . . . . . . . . . . . . . . . 219
INT0 mode 0 . . . . . . . . . . . . . . . . . . . 22
INT0 mode 1 . . . . . . . . . . . . . . . . . . . 23
INT0 mode 2 . . . . . . . . . . . . . . . . . . . 26
Interrupt. . . . . . . . . . . . . . . . . . . . . . 220
Interrupt acknowledge timing . . . . . . 221
Level-sense request . . . . . . . . . . . . . . 58
Memory read timing . . . . . . . . . . . . . 216
Memory write timing . . . . . . . . . . . . 217
Mode 0 outpu . . . . . . . . . . . . . . . . . . . t 47
Mode 1 input . . . . . . . . . . . . . . . . . . . 48
Mode 2 bidirectional. . . . . . . . . . . . . . 48
Mode 3 bit contol . . . . . . . . . . . . . . . . 49
PIO mode 0 (output). . . . . . . . . . . . . 224
PIO mode 1 (input). . . . . . . . . . . . . . 224
PIO mode 2 (bidirectional) . . . . . . . . 225
PIO mode 3 (bit control) . . . . . . . . . . 225
PRT. . . . . . . . . . . . . . . . . . . . . . . . . 223
Refresh cycle . . . . . . . . . . . . . . . . . . . 37
Refresh timing (2-clock cycle) . . . . . 221
RETI instruction with M1E=0. . . . . . . 27
SIO . . . . . . . . . . . . . . . . . . . . . . . . . 226
Sleep . . . . . . . . . . . . . . . . . . . . . . . . 222
Watch-Dog timer . . . . . . . . . . . . . . . 223
Transmission
5
SAR0 registers . . . . . . . . . . . . . . . . . . . . 60
SBC instruction. . . . . . . . . . . . . . . . . . . 192
SCF instruction . . . . . . . . . . . . . . . . . . . 192
Security features . . . . . . . . . . . . . . . . . . . 15
SET instruction . . . . . . . . . . . . . . . . . . . 192
Setting up a DMA transfer . . . . . . . . . . . . 60
Signalling, Daisy chain . . . . . . . . . . . . . . 19
SIO
Addresses . . . . . . . . . . . . . . . . . . . . . 72
Interrupts . . . . . . . . . . . . . . . . . . . . . 85
Read registers . . . . . . . . . . . . . . . . . . 81
Registers per channel. . . . . . . . . . . . . 73
Timing diagram. . . . . . . . . . . . . . . . 226
Write registers. . . . . . . . . . . . . . . . . . 73
SLA instruction . . . . . . . . . . . . . . . . . . . 192
Sleep
Mode . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing diagram. . . . . . . . . . . . . . . . 222
Source
And destination registers (SAR, DAR) 57
Mode, DMA0 . . . . . . . . . . . . . . . . . . 61
SRA instruction. . . . . . . . . . . . . . . . . . . 192
SRL instruction . . . . . . . . . . . . . . . . . . . 192
Stack pointer (SP) . . . . . . . . . . . . . . . . . . 13
Standard test conditions . . . . . . . . . . . . . 200
Standby mode . . . . . . . . . . . . . . . . . . . . . 45
Status, Async . . . . . . . . . . . . . . . . . . . . 100
Stopping a PRT . . . . . . . . . . . . . . . . . . . . 70
SUB instruction. . . . . . . . . . . . . . . . . . . 192
Sync operation . . . . . . . . . . . . . . . . . . . . 87
System Stop mode . . . . . . . . . . . . . . . . . 44
Async . . . . . . . . . . . . . . . . . . . . . . . . 97
DMA. . . . . . . . . . . . . . . . . . . . . . . . . 93
Interrupt-driven . . . . . . . . . . . . . . . . . 91
PS001500-ZMP0999
Z80S188
239
+
24'.+/+0#4;
6ꢁꢈ%
ꢉ
Transmitter, Async . . . . . . . . . . . . . . . . 102
Traps, illegal instruction. . . . . . . . . . . . . . 13
Triggers, Schmitt. . . . . . . . . . . . . . . . . . 227
TST instruction . . . . . . . . . . . . . . . . . . . 192
TSTIO instruction . . . . . . . . . . . . . . . . . 192
9
Wait state generator. . . . . . . . . . . . . . . . . 36
Waits, Central I/O . . . . . . . . . . . . . . . . . . 40
Watch-Dog
Time. . . . . . . . . . . . . . . . . . . . . . . . . 63
Timing diagram. . . . . . . . . . . . . . . . 223
:
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XOR instruction . . . . . . . . . . . . . . . . . . 192
ZDI
Connector on target board . . . . . . . . 229
Enable . . . . . . . . . . . . . . . . . . . . . . . 16
ZiLOG
Debug Interface (ZDI) . . . . . . . . . . . 228
Developer Studio (ZDS) . . . . . . . . . 228
240
Z80S188
PS001500-ZMP0999
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