Z85230_技术文档

SCC™/ESCC™ USER’S MANUAL

TABLE OF CONTENTS

Chapter 1. General Description

1.1 Introduction .................................................................................................................................... 1-1

1.2 SCC’s Capabilities ......................................................................................................................... 1-2

1.3 Block Diagram ............................................................................................................................... 1-4

1.4 Pin Descriptions ............................................................................................................................. 1-5

1.4.1

1.4.2

1.4.3

Pins Common to both Z85X30 and Z80X30 .................................................................... 1-7

Pin Descriptions, (Z85X30 Only) ...................................................................................... 1-8

Pin Descriptions, (Z80X30 Only) ...................................................................................... 1-9

Chapter 2. Interfacing the SCC/ESCC

2.1 Introduction .................................................................................................................................... 2-1

2.2 Z80X30 Interface Timing ................................................................................................................ 2-1

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

Z80X30 Read Cycle Timing ............................................................................................. 2-2

Z80X30 Write Cycle Timing .............................................................................................. 2-3

Z80X30 Interrupt Acknowledge Cycle Timing .................................................................. 2-4

Z80X30 Register Access .................................................................................................. 2-5

Z80C30 Register Enhancement ....................................................................................... 2-8

Z80230 Register Enhancements ...................................................................................... 2-8

Z80X30 Reset .................................................................................................................. 2-9

2.3 Z85X30 Interface Timing ............................................................................................................. 2-10

2.3.1

2.3.2

2.3.3

2.3.4

2.3.5

2.3.6

2.3.7

Z85X30 Read Cycle Timing ........................................................................................... 2-10

Z85X30 Write Cycle Timing ............................................................................................ 2-11

Z85X30 Interrupt Acknowledge Cycle Timing ................................................................ 2-11

Z85X30 Register Access ................................................................................................ 2-12

Z85C30 Register Enhancement ..................................................................................... 2-14

Z85C30/Z85230 Register Enhancements ...................................................................... 2-14

Z85X30 Reset ................................................................................................................ 2-15

2.4 Interface Programming ................................................................................................................ 2-15

2.4.1

2.4.2

2.4.3

2.4.4

2.4.5

2.4.6

2.4.7

2.4.8

2.4.9

I/O Programming Introduction ........................................................................................ 2-15

Polling ............................................................................................................................ 2-16

Interrupts ........................................................................................................................ 2-16

Interrupt Control ............................................................................................................. 2-17

Daisy-Chain Resolution .................................................................................................. 2-19

Interrupt Acknowledge ................................................................................................... 2-21

The Receiver Interrupt ................................................................................................... 2-21

Transmit Interrupts and Transmit Buffer Empty Bit ........................................................ 2-25

External/Status Interrupts ............................................................................................... 2-31

2.5 Block/DMA Transfer ..................................................................................................................... 2-33

2.5.1

2.5.2

Block Transfers .............................................................................................................. 2-33

DMA Requests ............................................................................................................... 2-36

2.6 Test Functions ............................................................................................................................. 2-41

2.6.1

2.6.2

Local Loopback .............................................................................................................. 2-41

Auto Echo ....................................................................................................................... 2-41

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Chapter 3. SCC/ESCC Ancillary Support Circuitry

3.1 Introduction .................................................................................................................................... 3-1

3.2 Baud Rate Generator ..................................................................................................................... 3-1

3.3 Data Encoding/Decoding ............................................................................................................... 3-4

3.4 DPLL Digital Phase-Locked Loop .................................................................................................. 3-7

3.4.1

3.4.2

3.4.3

3.4.4

DPLL Operation in the NRZI Mode .................................................................................. 3-8

DPLL Operation in the FM Modes .................................................................................... 3-9

DPLL Operation in the Manchester Mode ...................................................................... 3-10

Transmit Clock Counter (ESCC only) ............................................................................. 3-10

3.5

3.6

Clock Selection ........................................................................................................................... 3-11

Crystal Oscillator ......................................................................................................................... 3-14

Chapter 4. Data Communication Modes

4.1 Introduction .................................................................................................................................... 4-1

4.1.1

4.1.2

Transmit Data Path Description ....................................................................................... 4-1

Receive Data Path Description ....................................................................................... 4-2

4.2 Asynchronous Mode ...................................................................................................................... 4-3

4.2.1

4.2.2

4.2.3

Asynchronous Transmit ................................................................................................... 4-4

Asynchronous Receive .................................................................................................... 4-6

Asynchronous Initialization ............................................................................................... 4-7

4.3 Byte-Oriented Synchronous Mode ................................................................................................. 4-8

4.3.1

4.3.2

4.3.3

Byte-Oriented Synchronous Transmit .............................................................................. 4-8

Byte-Oriented Synchronous Receive ............................................................................. 4-10

Transmitter/Receiver Synchronization ........................................................................... 4-17

4.4 Bit-Oriented Synchronous (SDLC/HDLC) Mode .......................................................................... 4-18

4.4.1

4.4.2

4.4.3

4.4.4

SDLC Transmit ............................................................................................................... 4-19

SDLC Receive ................................................................................................................ 4-22

SDLC Frame Status FIFO .............................................................................................. 4-27

SDLC Loop Mode ........................................................................................................... 4-30

Chapter 5. Register Descriptions

5.1 Introduction .................................................................................................................................... 5-1

5.2 Write Registers .............................................................................................................................. 5-2

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

Write Register 0 (Command Register) ............................................................................. 5-2

Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) .......... 5-4

Write Register 2 (Interrupt Vector) ................................................................................... 5-7

Write Register 3 (Receive Parameters and Control) ........................................................ 5-7

Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) .................. 5-8

Write Register 5 (Transmit Parameters and Controls) ..................................................... 5-9

Write Register 6 (Sync Characters or SDLC Address Field) .......................................... 5-10

Write Register 7 (Sync Character or SDLC Flag) ........................................................... 5-11

Write Register 7 Prime (ESCC only) .............................................................................. 5-12

5.2.10 Write Register 7 Prime (85C30 only) .............................................................................. 5-13

5.2.11 Write Register 8 (Transmit Buffer) .................................................................................. 5-13

5.2.12 Write Register 9 (Master Interrupt Control) .................................................................... 5-14

5.2.13 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) ........................... 5-15

5.2.14 Write Register 11 (Clock Mode Control) ......................................................................... 5-17

5.2.15 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) ....................... 5-18

5.2.16 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) ....................... 5-19

5.2.17 Write Register 14 (Miscellaneous Control Bits) .............................................................. 5-19

5.2.18 Write Register 15 (External/Status Interrupt Control) ..................................................... 5-20

5.3 Read Registers ............................................................................................................................ 5-21

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

Read Register 0 (Transmit/Receive Buffer Status and External Status) ........................ 5-21

Read Register 1 ............................................................................................................. 5-23

Read Register 2 ............................................................................................................. 5-24

Read Register 3 ............................................................................................................. 5-25

Read Register 4 (ESCC and 85C30 Only) ..................................................................... 5-25

Read Register 5 (ESCC and 85C30 Only) ..................................................................... 5-25

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5.3.7

5.3.8

5.3.9

Read Register 6 (Not on NMOS) ................................................................................... 5-25

Read Register 7 (Not on NMOS) ................................................................................... 5-25

Read Register 8 ............................................................................................................. 5-26

5.3.10 Read Register 9 (ESCC and 85C30 Only) ..................................................................... 5-26

5.3.11 Read Register 10 ........................................................................................................... 5-26

5.3.12 Read Register 11 (ESCC and 85C30 Only) ................................................................... 5-27

5.3.13 Read Register 12 ........................................................................................................... 5-27

5.3.14 Read Register 13 ........................................................................................................... 5-27

5.3.15 Read Register 14 (ESCC and 85C30 Only) ................................................................... 5-27

5.3.16 Read Register 15 ........................................................................................................... 5-27

Chapter 6. Application Notes

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family ......................................................................... 6-1

The Z180™ Interfaced with the SCC at MHZ........................................................................................ 6-34

The Zilog Datacom Family with the 80186 CPU .................................................................................. 6-59

SCC in Binary Synchronous Communications...................................................................................... 6-79

™

Serial Communication Controller (SCC ): SDLC Mode of Operation .................................................. 6-93

Using SCC with Z8000 in SDLC Protocol6-105

Boost Your System Performance Using The Zilog ESCC ................................................................ 6-117

™

Technical Considerations When Implementing LocalTalk Link Access Protocol ................................ 6-131

On-Chip Oscillator Design................................................................................................................... 6-151

Chapter 7. Questions and Answers

Zilog SCC Z8030/Z8530 Questions and Answers................................................................................... 7-1

™

Zilog ESCC Controller Questions and Answers................................................................................. 7-11

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LIST OF FIGURES

Chapter 1

Figure 1-1.

Figure 1-2.

Figure 1-3.

Figure 1-4.

Figure 1-5.

Figure 1-6.

Figure 1-7.

SCC Block Diagram .............................................................................................................................. 1-4

Z85X30 Pin Functions .......................................................................................................................... 1-5

Z80X30 Pin Functions .......................................................................................................................... 1-6

Z85X30 DIP Pin Assignments .............................................................................................................. 1-6

Z85X30 PLCC Pin Assignments ........................................................................................................... 1-6

Z80X30 DIP Pin Assignments .............................................................................................................. 1-7

Z80X30 PLCC Pin Assignments ........................................................................................................... 1-7

Chapter 2

Figure 2-1.

Figure 2-2.

Figure 2-3.

Figure 2-4.

Figure 2-5.

Z80X30 Read Cycle ............................................................................................................................. 2-2

Z80X30 Write Cycle .............................................................................................................................. 2-3

Z80X30 Interrupt Acknowledge Cycle .................................................................................................. 2-4

Write Register 7 Prime (WR7') ............................................................................................................. 2-8

Z85X30 Read Cycle Timing ................................................................................................................ 2-10

Figure 2-6.

Figure 2-7.

Z85X30 Write Cycle Timing ................................................................................................................ 2-11

Z85X30 Interrupt Acknowledge Cycle Timing .................................................................................... 2-11

Figure 2-8a. Write Register 7 Prime (WR7') for the 85230 ..................................................................................... 2-14

Figure 2-8b. Write Register 7 Prime for the 85C30 ................................................................................................. 2-14

Figure 2-9.

ESCC Interrupt Sources ..................................................................................................................... 2-16

Figure 2-10. Peripheral Interrupt Structure ............................................................................................................. 2-17

Figure 2-11. Internal Priority Resolution ................................................................................................................. 2-17

Figure 2-12. RR3 Interrupt Pending Bits ................................................................................................................. 2-18

Figure 2-13. Interrupt Flow Chart (for each interrupt source). ................................................................................ 2-20

Figure 2-14. Write Register 1 Receive Interrupt Mode Control ............................................................................... 2-22

Figure 2-15. Special Conditions Interrupt Service Flow .......................................................................................... 2-24

Figure 2-16. Transmit Interrupt Status When WR7' D5=1 For ESCC ..................................................................... 2-26

Figure 2-17. Transmit Buffer Empty Bit Status For ESCC For Both WR7' and WR7' D5=0 ................................... 2-27

Figure 2-18. Transmit Interrupt Status When WR7' D5=0 For ESCC ..................................................................... 2-27

Figure 2-19. TxIP Latching on the ESCC ................................................................................................................ 2-27

Figure 2-20. Operation of TBE, Tx Underrun/EOM and TxIP on NMOS/CMOS. .................................................... 2-28

Figure 2-21. Operation of TBE, Tx Underrun/EOM and TxIP on ESCC ................................................................. 2-29

Figure 2-22. Flowchart example of processing an end of packet ........................................................................... 2-30

Figure 2-23. RR0 External/Status Interrupt Operation ............................................................................................ 2-31

Figure 2-24. Wait On Transmit Timing .................................................................................................................... 2-34

Figure 2-25. Wait On Transmit Timing .................................................................................................................... 2-34

Figure 2-26. Wait On Receive Timing ..................................................................................................................... 2-35

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Figure 2-27. Wait On Receive Timing ..................................................................................................................... 2-35

Figure 2-28. Transmit Request Assertion ............................................................................................................... 2-36

Figure 2-29. Z80X30 Transmit Request Release ................................................................................................... 2-37

Figure 2-30. Z85X30 Transmit Request Release ................................................................................................... 2-37

Figure 2-31. /DTR//REQ Deassertion Timing ......................................................................................................... 2-38

Figure 2-32. DMA Receive Request Assertion ....................................................................................................... 2-39

Figure 2-33. Z80X30 Receive Request Release .................................................................................................... 2-40

Figure 2-34. Z85X30 Receive Request Release .................................................................................................... 2-40

Figure 2-35. Local Loopback .................................................................................................................................. 2-41

Figure 2-36. Auto Echo ........................................................................................................................................... 2-41

Chapter 3

Figure 3-1.

Figure 3-2.

Figure 3-3.

Figure 3-4.

Baud Rate Generator ........................................................................................................................... 3-1

Baud Rate Generator Start Up ............................................................................................................. 3-2

Data Encoding Methods ....................................................................................................................... 3-4

Manchester Encoding Circuit ................................................................................................................ 3-6

Figure 3-5.

Figure 3-6.

Digital Phase-Locked Loop ................................................................................................................... 3-7

DPLL in NRZI Mode ............................................................................................................................. 3-8

Figure 3-7.

Figure 3-8.

DPLL Operating Example (NRZI Mode) ............................................................................................... 3-9

DPLL Operation in the FM Mode .......................................................................................................... 3-9

Figure 3-9.

DPLL Transmit Clock Counter Output (ESCC only) ........................................................................... 3-11

Figure 3-10. Clock Multiplexer ................................................................................................................................ 3-12

Figure 3-11. Async Clock Setup Using an External Crystal .................................................................................... 3-13

Figure 3-12. Clock Source Selection ...................................................................................................................... 3-13

Figure 3-13. Synchronous Transmission, 1x Clock Rate, FM Data Encoding, using DPLL ................................... 3-14

Chapter 4

Figure 4-1.

Figure 4-2.

Figure 4-3.

Figure 4-4.

Figure 4-5.

Figure 4-6.

Transmit Data Path ............................................................................................................................... 4-1

Receive Data Path ................................................................................................................................ 4-2

Asynchronous Message Format ........................................................................................................... 4-3

Monosync Data Character Format ....................................................................................................... 4-8

Sync Character Programming ............................................................................................................ 4-11

/SYNC as an Input .............................................................................................................................. 4-11

Figure 4-7.

Figure 4-8.

Figure 4-9.

/SYNC as an Output ........................................................................................................................... 4-12

Changing Character Length ............................................................................................................... 4-13

Receive CRC Data Path ..................................................................................................................... 4-14

Figure 4-10. Transmitter to Receiver Synchronization ............................................................................................ 4-17

Figure 4-11. SDLC Message Format ...................................................................................................................... 4-18

Figure 4-12. /SYNC as an Output ........................................................................................................................... 4-23

Figure 4-13. Changing Character Length ............................................................................................................... 4-24

Figure 4-14. Residue Code 101 Interpretation ........................................................................................................ 4-25

Figure 4-15. SDLC Frame Status FIFO (N/A on NMOS) ........................................................................................ 4-28

Figure 4-16. SDLC Byte Counting Detail ................................................................................................................ 4-29

Chapter 5

Figure 5-1.

Figure 5-2.

Figure 5-3.

Figure 5-4.

Figure 5-5.

Write Register 0 in the Z85X30 ............................................................................................................ 5-3

Write Register 0 in the Z80X30 ............................................................................................................ 5-3

Write Register 1 .................................................................................................................................... 5-4

Write Register 2 .................................................................................................................................... 5-7

Write Register 3 .................................................................................................................................... 5-7

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Figure 5-6.

Figure 5-7.

Write Register 4 .................................................................................................................................... 5-8

Write Register 5 .................................................................................................................................... 5-9

Figure 5-8.

Figure 5-9.

Write Register 6 .................................................................................................................................. 5-11

Write Register 7 .................................................................................................................................. 5-11

Figure 5-10. Write Register 7 Prime ....................................................................................................................... 5-12

Figure 5-10a. Write Register 7 Prime (WR7') ........................................................................................................... 5-13

Figure 5-11. Write Register 9 .................................................................................................................................. 5-14

Figure 5-12. Write Register 10 ................................................................................................................................ 5-15

Figure 5-13. NRZ (NRZI), FM1 (FM0) Timing ......................................................................................................... 5-16

Figure 5-14. Write Register 11 ................................................................................................................................ 5-17

Figure 5-15. Write Register 12 ................................................................................................................................ 5-18

Figure 5-16. Write Register 13 ................................................................................................................................ 5-19

Figure 5-17. Write Register 14 ................................................................................................................................ 5-19

Figure 5-18. Write Register 15 ................................................................................................................................ 5-20

Figure 5-19. Read Register 0 .................................................................................................................................. 5-21

Figure 5-20. Read Register 1 .................................................................................................................................. 5-23

Figure 5-21. Read Register 2 .................................................................................................................................. 5-25

Figure 5-22. Read Register 3 .................................................................................................................................. 5-25

Figure 5-23. Read Register 6 (Not on NMOS) ........................................................................................................ 5-25

Figure 5-24. Read Register 7 (Not on NMOS) ........................................................................................................ 5-26

Figure 5-25. Read Register 10 ................................................................................................................................ 5-26

Figure 5-26. Read Register 12 ................................................................................................................................ 5-27

Figure 5-27. Read Register 13 ................................................................................................................................ 5-27

Figure 5-28. Read Register 15 ................................................................................................................................ 5-27

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LIST OF TABLES

Chapter 2

Table 2-1. Z80X30 Register Map (Shift Left Mode) ................................................................................................... 2-6

Table 2-2. Z80X30 Register Map (Shift Right Mode) ................................................................................................. 2-7

Table 2-3. Z80230 SDLC/HDLC Enhancement Options ........................................................................................... 2-8

Table 2-4. Z80X30 Register Reset Values ................................................................................................................ 2-9

Table 2-5. Z85X30 Register Map ............................................................................................................................. 2-13

Table 2-6. Z85C30/Z85230 Register Enhancement Options ................................................................................... 2-14

Table 2-7. Z85X30 Register Reset Value ................................................................................................................ 2-15

Table 2-8. Interrupt Source Priority .......................................................................................................................... 2-16

Table 2-9. Interrupt Vector Modification ................................................................................................................... 2-19

Chapter 3

Table 3-1. Baud Rates for 2.4576 MHz Clock and 16x Clock Factor ........................................................................ 3-3

Chapter 4

Table 4-1. Write Register Bits Ignored in Asynchronous Mode ................................................................................. 4-4

Table 4-2. Transmit Bits per Character ...................................................................................................................... 4-5

Table 4-3. Initialization Sequence Asynchronous Mode ............................................................................................ 4-7

Table 4-4. Registers Used in Character-Oriented Modes .......................................................................................... 4-9

Table 4-5. Transmitter Initialization in Character- Oriented Mode ........................................................................... 4-10

Table 4-6. Sync Character Length Selection ........................................................................................................... 4-11

Table 4-7. Enabling and Disabling CRC .................................................................................................................. 4-16

Table 4-8. Initializing the Receiver in Character-Oriented Mode ............................................................................. 4-17

Table 4-9. ESCC Action Taken on Tx Underrun ...................................................................................................... 4-20

Table 4-10. Residue Codes ....................................................................................................................................... 4-24

Table 4-11. Initializing in SDLC Mode ....................................................................................................................... 4-26

Table 4-12. SDLC Loop Mode Initialization ............................................................................................................... 4-32

Chapter 5

Table 5-1. SCC Write Registers ................................................................................................................................ 5-1

Table 5-2. SCC Read Registers ................................................................................................................................ 5-1

Table 5-3. Z85X30 Register Map ............................................................................................................................... 5-5

Table 5-4. Receive Bits per Character ....................................................................................................................... 5-7

Table 5-5. Transmit Bits per Character .................................................................................................................... 5-10

Table 5-6. Interrupt Vector Modification ................................................................................................................... 5-14

Table 5-7. Data Encoding ........................................................................................................................................ 5-15

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Table 5-8. Receive Clock Source ............................................................................................................................ 5-18

Table 5-9. Transmit Clock Source ........................................................................................................................... 5-18

Table 5-10. Transmit External Control Selection ....................................................................................................... 5-18

Table 5-11. I-Field Bit Selection (8 Bits Only) ............................................................................................................ 5-24

Table 5-12. Bits per Character Residue Decoding .................................................................................................... 5-24

Table 5-13. Read Register 7 FIFO Status Decoding ................................................................................................ 5-26

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1

CHAPTER 1

GENERAL DESCRIPTION

1.1 INTRODUCTION

The Zilog SCC Serial Communication Controller is a dual

channel, multiprotocol data communication peripheral de-

signed for use with 8- and 16-bit microprocessors. The

SCC functions as a serial-to-parallel, parallel-to-serial con-

verter/controller. The SCC can be software-configured to

satisfy a wide variety of serial communications applica-

tions. The device contains a variety of new, sophisticated

internal functions including on-chip baud rate generators,

digital phase-lock loops, and crystal oscillators, which dra-

matically reduce the need for external logic.

The SCC/ESCC family consists of the following seven

devices;

®

Z-Bus

Universal-Bus

NMOS

CMOS

ESCC

Z8030

Z8530

Z80C30

Z80230

Z85C30

Z85230

Z85233

EMSCC

As a convention, use the following words to distinguish the

devices throughout this document.

The SCC handles asynchronous formats, synchronous

byte-oriented protocols such as IBM Bisync, and syn-

®

chronous bit-oriented protocols such as HDLC and IBM

SDLC. This versatile device supports virtually any serial

data transfer application (telecommunication, LAN, etc.)

Description applies to all versions.

SCC:

Description applies to NMOS version

(Z8030/Z8530)

NMOS:

The device can generate and check CRC codes in any

synchronous mode and can be programmed to check data

integrity in various modes. The SCC also has facilities for

modem control in both channels. In applications where

these controls are not needed, the modem controls can be

used for general-purpose I/O.

Description applies to CMOS version

(Z80C30/Z85C30)

CMOS:

ESCC:

Description applies to ESCC

(Z80230/Z85230)

Description applies to EMSCC (Z85233)

EMSCC:

Z80X30:

Description applies to Z-Bus version of the

device (Z8030/Z80C30/Z80230)

With access to 14 Write registers and 7 Read registers per

channel (the number of the registers varies depending on

the version), the user can configure the SCC to handle all

synchronous formats regardless of data size, number of

stop bits, or parity requirements.

Description applies to Universal version of

the device (Z8530/Z85C30/Z85230/Z85233)

Z85X3X:

The Z-Bus version has a multiplexed bus interface and is

directly compatible with the Z8000, Z16C00 and 80x86

CPUs. The Universal version has a non-multiplexed bus

interface and easily interfaces with virtually any CPU, in-

cluding the 8080, Z80, 68X00.

Within each operating mode, the SCC also allows for pro-

tocol variations by checking odd or even parity bits, char-

acter insertion or deletion, CRC generation, checking

break and abort generation and detection, and many other

protocol-dependent features.

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SCC™/ESCC™ User’s Manual

General Description

1.2 SCC’S CAPABILITIES

The NMOS version of the SCC is Zilog’s original device.

The design is based on the Z80 SIO architecture. If you are

familiar with the Z80 SIO, the SCC can be treated as an

SIO with support circuitry such as DPLL, BRG, etc. Its fea-

tures include:

■

Receiver FIFO

ESCC:

8 bytes deep

3 bytes deep

NMOS/CMOS:

Transmitter FIFO

ESCC:

■

Two independent full-duplex channels

4 bytes deep

1 byte deep

Synchronous/Isosynchronous data rates:

NMOS/CMOS:

–

Up to 1/4 of the PCLK using external clock source.

Up to 5 Mbits/sec at 20 MHz PCLK (ESCC)

Up to 4 Mbits/sec at 16 MHz PCLK (CMOS)

Up to 2 MBits/sec at 8 MHz PCLK (NMOS)

NRZ, NRZI or FM encoding/decoding. Manchester code

decoding (encoding with external logic).

■

Baud Rate Generator in each channel

Digital Phase Locked Loop (DPLL) for clock recovery

Crystal oscillator

–

Up to 1/8 of the PCLK (up to 1/16 on NMOS) using

FM encoding with DPLL

Up to 1/16 of the PCLK (up to 1/32 on NMOS)

using NRZI encoding with DPLL

The CMOS version of the SCC is 100% plug in compatible

to the NMOS versions of the device, while providing the

following additional features:

■

Asynchronous Capabilities

–

5, 6, 7 or 8 bits/character (capable of handling 4

bits/character or less.)

■

Status FIFO

–

1, 1.5, or 2 stop bits

Odd or even parity

Software interrupt acknowledge feature

Enhanced timing specifications

Faster system clock speed

Times 1, 16, 32 or 64 clock modes

Break generation and detection

Parity, overrun and framing error detection

™

■

Byte oriented synchronous capabilities:

Designed in Zilog’s Superintegration core format

–

Internal or external character synchronization

When the DPLL clock source is external, it can be up to

2x the PCLK, where NMOS allows up to PCLK (32.3

MHz max with 16/20 MHz version).

One or two sync characters (6 or 8 bits/sync

character) in separate registers

–

Automatic Cyclic Redundancy Check (CRC)

generation/detection

SDLC/HDLC capabilities:

–

Abort sequence generation and checking

Automatic zero insertion and detection

Automatic ﬂag insertion between messages

Address ﬁeld recognition

I-ﬁeld residue handling

CRC generation/detection

SDLC loop mode with EOP recognition/loop entry

and exit

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General Description

The Z85C30 CMOS SCC has added new features, while

maintaining 100% hardware/software compatibility. It has

the following new features:

ESCC (Enhanced SCC) is pin and software compati-

ble to the CMOS version, with the following additional

enhancements.

1

■

New programmable WR7' (write register 7 prime) to

enable new features.

■

Deeper transmit FIFO (4 bytes)

Deeper receive FIFO (8 bytes)

■

Improvements to support SDLC mode of synchronous

communication:

Programmable FIFO interrupt and DMA request level

–

Improved functionality to ease sending back-to

back frames

Seven enhancements to improve SDLC link layer

supports:

–

Automatic SDLC opening Flag transmission*

–

Automatic transmission of the opening ﬂag

Automatic reset of Tx Underrun/EOM latch

Deactivation of /RTS pin after closing ﬂag

Automatic CRC generator preset

Automatic Tx Underrun/EOM Latch reset in SDLC

mode*

–

Automatic /RTS deactivation*

TxD pin forced “H” in SDLC NRZI mode after

closing ﬂag*

Complete CRC reception

TxD pin automatically forced high with NRZI

encoding when using mark idle

–

Complete CRC reception*

Improved response to Abort sequence in status

FIFO

–

Status FIFO handles better frames with an

ABORT

–

Automatic Tx CRC generator preset/reset

Extended read for write registers*

Receive FIFO automatically unlocked for special

receive interrupts when using the SDLC status

FIFO

Write data setup timing improvement

■

Improved AC timing:

■

Delayed bus latching for easier microprocessor

interface

–

Three to 3.5 PCLK access recovery time.

Programmable /DTR//REQ timing*

New programmable features added with Write Register

7' (WR seven prime)

Elimination of write data to falling edge of /WR

setup time requirement

■

Write registers 3, 4, 5 and 10 are now readable

Read register 0 latched during access

–

Reduced /INT timing

Other features include:

–

Extended read function to read back the written

value to the write registers*

DPLL counter output available as jitter-free transmitter

clock source

–

Latching RR0 during read

■

Enhanced /DTR, /RTS deactivation timing

RR0, bit D7 and RR10, bit D6 now has reset

defaultvalue.

Some of the features listed above are available by de-

fault, and some of them (features with “*”) are disabled on

default.

1-3

UM010901-0601

SCC™/ESCC™ User’s Manual

General Description

1.3 BLOCK DIAGRAM

Figure 1-1 has the block diagram of the SCC. Note that the

depth of the FIFO differs depending on the version. The

10X19 SDLC Frame Status FIFO is not available on the

NMOS version of the SCC.

Detailed internal signal path will be discussed in Chapter 4.

Transmit Log

Transmit FIFO

NMOS/CMOS: 1 b

ESCC: 4 Bytes

Transmit MU

TxDA

Data Encoding & CR

Generation

Channel A

Exploded Vie

/TRxCA

/RTxCA

Receive and Transmit Clock Mul

Digital

Phase-Locke

Loop

Crystal

Oscillato

Amplifie

Baud Rate

Generato

/CTSA

/DCDA

Modem/Control Lo

Receive Log

/SYNCA

/RTSA

/DTRA//REQ

Rec. Status*Rec. Data*

FIFO FIFO

Receive MU

RxDA

CRC Checker

Data Decode &

Sync Charact

Detection

SDLC Frame Status F

10 x 19

** See No

*

NMOS/CMOS: 3 bytes each

ESCC: 8 bytes

** Not Available on NMOS

Interna

Contro

Logic

Channel A

Register

Channel A

Databu

Contro

CPU & DMA

Bus Interfac

/INT

/INTAC

Channel B

Interrup

Control

Logic

Channel B

Register

Interru

Contro

IEI

IEO

Figure 1-1. SCC Block Diagram

UM010901-0601

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SCC™/ESCC™ User’s Manual

General Description

1.4 PIN DESCRIPTIONS

The SCC pins are divided into seven functional groups:

Address/Data, Bus Timing and Reset, Device Control, In-

terrupt, Serial Data (both channels), Peripheral Control

(both channels), and Clocks (both channels). Figures 1-2

and 1-3 show the pins in each functional group for both

Z80X30 and Z85X30. Notice the pin functions unique to

each bus interface version in the Address/Data group, Bus

Timing and Reset group, and Control groups.

The timing and control groups designate the type of trans-

action to occur and when it will occur. The interrupt group

provides inputs and outputs to conform to the Z-Bus

specifications for handling and prioritizing interrupts. The

remaining groups are divided into channel A and channel

B groups for serial data (transmit or receive), peripheral

control (such as DMA or modem), and the input and output

lines for the receive and transmit clocks.

1

®

The Address/Data group consists of the bidirectional lines

used to transfer data between the CPU and the SCC (Ad-

dresses in the Z80X30 are latched by /AS). The direction

of these lines depends on whether the operation is a Read

or Write.

The signal functionality and pin assignments (Figures 1-4

to 1-7) stay constant within the same bus interface group

(i.e., Z80X30, Z85X30), except for some timing and/or DC

specification differences. For details, please reference the

individual product specifications.

TxDA

Serial

D7

D6

D5

Data

RxDA

/TRxCA

Channel

Clocks

/RTxCA

D4

Data Bus

/SYNCA

/W//REQA

/DTR//REQA

/RTSA

D3

D2

D1

D0

Channel

Controls

for Modem,

DMA and

Other

/CTSA

/RD

Bus Timing

and Reset

/DCDA

/WR

A//B

/CE

Z85X30

TxDB

RxDB

Serial

Data

Control

/TRxCB

/RTxCB

/SYNCB

/W//REQB

/DTR//REQB

/RTSB

Channel

Clocks

D//C

/INT

/INTACK

IEI

Interrupt

Channel

Controls

for Modem,

DMA and

Other

IEO

/CTSB

/DCDB

Figure 1-2. Z85X30 Pin Functions

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General Description

1.4 PIN DESCRIPTIONS (Continued)

TxDA

RxDA

AD7

Serial

Data

AD6

AD5

AD4

AD3

AD2

AD1

AD0

/AS

/TRxCA

/RTxCA

Channel

Clocks

Address

Data Bus

/SYNCA

/W//REQA

/DTR//REQA

/RTSA

Channel A

Channel

Controls

for Modem,

DMAand

Other

/CTSA

Bus Timing

and Reset

/DCDA

/DS

Z80X30

TxDB

R//W

CS1

Serial

Data

Control

RxDB

/TRxCB

/RTxCB

Channel

Clocks

/CS0

/INT

/SYNCB

/W//REQB

/DTR//REQB

/RTSB

/INTACK

IEI

Interrupt

Channel B

Channel

Controls

for Modem,

DMAand

Other

IEO

/CTSB

/DCDB

Figure 1-3. Z80X30 Pin Functions

1

2

3

4

5

6

7

8

9

10

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

D1

D3

D0

D2

D5

D4

D7

D6

/INT

/RD

IEO

/WR

IEI

A//B

/INTACK

VCC

/CE

D//C

/W//REQA

/SYNCA

/RTxCA

RxDA

GND

Z85X30

/W//REQB

/SYNCB

/RTxCB

RxDB

/TRxCB

TxDB

/DTR//REQB

RTSB

/CTSB

/DCDB

11

12

13

14

15

16

17

18

19

20

/TRxCA

TxDA

/DTR//REQA

/RTSA

/CTSA

/DCDA

PCLK

Figure 1-5. Z85X30 PLCC Pin Assignments

Figure 1-4. Z85X30 DIP Pin Assignments

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SCC™/ESCC™ User’s Manual

General Description

AD1

AD3

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

AD0

AD2

AD4

AD6

/DS

2

1

AD5

3

AD7

4

/INT

5

IEO

6

/AS

IEI

7

R//W

/INTACK

VCC

8

/CS0

CS1

9

/W//REQA

/SYNCA

/RTxCA

RxDA

10

11

12

13

14

15

16

17

18

19

20

GND

Z80X30

/W//REQB

/SYNCB

/RTxCB

RxDB

/TRxCA

TxDA

/TRxCB

TxDB

/DTR//REQA

/RTSA

/CTSA

/DCDA

PCLK

/DTR//REQB

RTSB

/CTSB

/DCDB

Figure 1-7. Z80X30 PLCC Pin Assignments

Figure 1-6. Z80X30 DIP Pin Assignments

outputs, and, they strictly follow the inverse state of WR5,

bit D1.

1.4.1 Pins Common to both Z85X30 and

Z80X30

/CTSA, /CTSB. Clear To Send (inputs, active Low). These

pins function as transmitter enables if they are pro-

grammed for Auto Enable (WR3, D5=1). A Low on the in-

puts enables the respective transmitters. If not pro-

grammed as Auto Enable, they may be used as general-

purpose inputs. Both inputs are Schmitt-trigger buffered to

accommodate slow rise-time inputs. The SCC detects

pulses on these inputs and can interrupt the CPU on both

logic level transitions.

ESCC and 85C30:

In SDLC mode, the /RTS pins can be programmed to

be deasserted when the closing flag of the message

clears the TxD pin, if WR7' D2 is set.

/SYNCA, /SYNCB. Synchronization (inputs or outputs, ac-

tive Low). These pins can act either as inputs, outputs, or

part of the crystal oscillator circuit. In the Asynchronous

Receive mode (crystal oscillator option not selected),

these pins are inputs similar to CTS and DCD. In this

mode, transitions on these lines affect the state of the Syn-

chronous/Hunt status bits in Read Register 0 but have no

other function.

/DCDA, /DCDB. Data Carrier Detect (inputs, active Low).

These pins function as receiver enables if they are pro-

grammed for Auto Enable (WR3, D5=1); otherwise, they

are used as general-purpose input pins. Both pins are

Schmitt-trigger buffered to accommodate slow rise time

signals. The SCC detects pulses on these pins and can in-

terrupt the CPU on both logic level transitions.

In External Synchronization mode, with the crystal oscilla-

tor not selected, these lines also act as inputs. In this

mode, /SYNC is driven Low to receive clock cycles after

the last bit in the synchronous character is received. Char-

acter assembly begins on the rising edge of the receive

clock immediately preceding the activation of SYNC.

/RTSA, /RTSB. Request To Send (outputs, active Low).

The /RTS pins can be used as general-purpose outputs or

with the Auto Enable feature. When used with Auto Enable

ON (WR3, D5=1) in asynchronous mode, the /RTS pin

goes High after the transmitter is empty. When Auto En-

able is OFF, the /RTS pins are used as general-purpose

In the Internal Synchronization mode (Monosync and Bi-

sync) with the crystal oscillator not selected, these pins

act as outputs and are active only during the part of the

1-7

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General Description

1.4 PIN DESCRIPTIONS (Continued)

receive clock cycle in which the synchronous condition is

not latched. These outputs are active each time a synchro-

nization pattern is recognized (regardless of character

boundaries). In SDLC mode, the pins act as outputs and

are valid on receipt of a flag. The /SYNC pins switch from

input to output when monosync, bisync, or SDLC is pro-

grammed in WR4 and sync modes are enabled.

parallels the Digital Phase-Locked Loop), the crystal oscil-

lator, the baud rate generator, or the transmit clock in the

output mode.

PCLK. Clock (input). This is the master SCC clock used to

synchronize internal signals. PCLK is a TTL level signal.

PCLK is not required to have any phase relationship with

the master system clock.

/DTR//REQA, /DTR//REQB. Data Terminal Ready/Re-

quest (outputs, active Low). These pins are programmable

(WR14, D2) to serve either as general-purpose outputs or

as DMA Request lines. When programmed for DTR func-

tion (WR14 D2=0), these outputs follow the state pro-

grammed into the DTR bit of Write Register 5 (WR5 D7).

When programmed for Ready mode, these pins serve as

DMA Requests for the transmitter.

IEI. Interrupt Enable In (input, active High). IEI is used with

IEO to form an interrupt daisy chain when there is more

than one interrupt driven device. A high IEI indicates that

no other higher priority device has an interrupt under ser-

vice or is requesting an interrupt.

IEO. Interrupt Enable Out (output, active High). IEO is High

only if IEI is High and the CPU is not servicing the SCC in-

terrupt or the SCC is not requesting an interrupt (Interrupt

Acknowledge cycle only). IEO is connected to the next

lower priority device’s IEI input and thus inhibits interrupts

from lower priority devices.

ESCC and 85C30:

When used as DMA request lines (WR14, D2=1), the

timing for the deactivation request can be pro-

grammed in the added register, Write Register 7'

(WR7') bit D4. If this bit is set, the /DTR//REQ pin is de-

activated with the same timing as the /W/REQ pin. If

WR7' D4 is reset, the deactivation timing of /DTR//REQ

pin is four clock cycles, the same as in the Z85C30.

/INT. Interrupt (output, open drain, active Low). This signal

is activated when the SCC requests an interrupt. Note that

/INT is an open-drain output.

/INTACK. Interrupt Acknowledge (input, active Low). This

is a strobe which indicates that an interrupt acknowledge

cycle is in progress. During this cycle, the SCC interrupt

daisy chain is resolved. The device is capable of returning

an interrupt vector that may be encoded with the type of in-

terrupt pending. During the acknowledge cycle, if IEI is

high, the SCC places the interrupt vector on the databus

when /RD goes active. /INTACK is latched by the rising

edge of PCLK.

/W//REQA, /W//REQB. Wait/Request (outputs, open-drain

when programmed for Wait function, driven High or Low

when programmed for Ready function). These dual-pur-

pose outputs may be programmed as Request lines for a

DMA controller or as Wait lines to synchronize the CPU to

the SCC data rate. The reset state is Wait.

RxDA, RxDB. Receive Data (inputs, active High). These

input signals receive serial data at standard TTL levels.

1.4.2 Pin Descriptions, (Z85X30 Only)

/RTxCA, /RTxCB. Receive/Transmit Clocks (inputs, active

Low). These pins can be programmed to several modes of

operation. In each channel, /RTxC may supply the receive

clock, the transmit clock, the clock for the baud rate gener-

ator, or the clock for the Digital Phase-Locked Loop. These

pins can also be programmed for use with the respective

SYNC pins as a crystal oscillator. The receive clock may

be 1, 16, 32, or 64 times the data rate in asynchronous

modes.

D7-D0. Data bus (bidirectional, tri-state). These lines carry

data and commands to and from the Z85X30.

/CE. Chip Enable (input, active Low). This signal selects

the Z85X30 for a read or write operation.

/RD. Read (input, active Low). This signal indicates a read

operation and when the Z85X30 is selected, enables the

Z85X30’s bus drivers. During the Interrupt Acknowledge cy-

cle, /RD gates the interrupt vector onto the bus if the Z85X30

is the highest priority device requesting an interrupt.

TxDA, TxDB. Transmit Data (outputs, active High). These

output signals transmit serial data at standard TTL levels.

/TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or out-

puts, active Low). These pins can be programmed in sev-

eral different modes of operation. /TRxC may supply the

receive clock or the transmit clock in the input mode or

supply the output of the Transmit Clock Counter (which

/WR. Write (input, active Low). When the Z85X30 is select-

ed, this signal indicates a write operation. This indicates

that the CPU wants to write command bytes or data to the

Z85X30 write registers.

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General Description

A//B. Channel A/Channel B (input). This signal selects the

channel in which the read or write operation occurs. High

selects channel A and Low selects channel B.

/CS0. Chip Select 0 (input, active Low). This signal is

latched concurrently with the addresses on AD7-AD0 and

must be active for the intended bus transaction to occur.

1

D//C. Data/Control Select (input). This signal defines the

type of information transferred to or from the Z85X30.

High means data is being transferred and Low indicates

a command.

CS1. Chip Select 1 (input, active High). This second select

signal must also be active before the intended bus trans-

action can occur. CS1 must remain active throughout the

transaction.

/DS. Data Strobe (input, active Low). This signal provides

timing for the transfer of data into and out of the Z80X30.

If /AS and /DS are both Low, this is interpreted as a reset.

1.4.3 Pin Descriptions, (Z80X30 Only)

AD7-AD0. Address/Data Bus (bidirectional, active High,

tri-state). These multiplexed lines carry register addresses

to the Z80X30 as well as data or control information to and

from the Z80X30.

/AS. Address Strobe (input, active Low). Address on AD7-

AD0 are latched by the rising edge of this signal.

R//W. Read//Write (input, read active High). This signal

specifies whether the operation to be performed is a read

or a write.

document may be copied or reproduced in any form or by

any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change

without notice. Devices sold by Zilog, Inc. are covered by

warranty and patent indemnification provisions appearing

in Zilog, Inc. Terms and Conditions of Sale only.

Zilog, Inc. shall not be responsible for any errors that may

appear in this document. Zilog, Inc. makes no commitment

to update or keep current the information contained in this

document.

Zilog’s products are not authorized for use as critical

components in life support devices or systems unless a

specific written agreement pertaining to such intended use

is executed between the customer and Zilog prior to use.

Life support devices or systems are those which are

intended for surgical implantation into the body, or which

sustains life whose failure to perform, when properly used

in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in

significant injury to the user.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS,

STATUTORY, IMPLIED OR BY DESCRIPTION,

REGARDING THE INFORMATION SET FORTH HEREIN

OR REGARDING THE FREEDOM OF THE DESCRIBED

DEVICES

FROM

INTELLECTUAL

PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY

OF MERCHANTABILITY OR FITNESS FOR ANY

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Campbell, CA 95008-6600

Telephone (408) 370-8000

FAX 408 370-8056

Internet: http://www.zilog.com

1-9

UM010901-0601

USER’S MANUAL

2

CHAPTER 2

INTERFACING THE SCC/ESCC

2.1 INTRODUCTION

This chapter covers the system interface requirements

with the SCC. Timing requirements for both devices are

described in a general sense here, and the user should re-

fer to the SCC Product Specification for detailed AC/DC

parametric requirements.

the ability to read WR3, WR4, WR5, WR7', and WR10.

Both the ESCC and the 85C30 have the ability to deassert

the /DTR//REG pin quickly to ease DMA interface design.

Additionally, the Z85230 features a relaxed requirement for

a valid data bus when the /WR pin goes Low. The effects

of the deeper data FIFOs should be considered when writ-

ing the interrupt service routines. The user should read the

sections which follow for details on these features.

The ESCC and the 85C30 have an additional register,

Write Register Seven Prime (WR7'). Its features include

2.2 Z80X30 INTERFACE TIMING

®

The Z-Bus compatible SCC is suited for system applica-

Because of this, /AS must be kept cycling for the inter-

rupt section to function properly.

tions with multiplexed address/data buses similar to the

®

Z8 , Z8000 , and Z280 .

The Z80X30 generates internal control signals in response

to a register access. Since /AS and /DS have no phase re-

lationship with PCLK, the circuit generating these internal

control signals provides time for metastable conditions to

disappear. This results in a recovery time related to PCLK.

Two control signals, /AS and /DS, are used by the Z80X30

to time bus transactions. In addition, four other control sig-

nals (/CS0, CS1, R//W, and /INTACK) are used to control

the type of bus transaction that occurs. A bus transaction

is initiated by /AS; the rising edge latches the register ad-

dress on the Address/Data bus and the state of /INTACK

and /CS0.

This recovery time applies only to transactions involving

the Z80X30, and any intervening transactions are ignored.

This recovery time is four PCLK cycles, measured from the

falling edge of /DS of one access to the SCC, to the falling

edge of /DS for a subsequent access.

In addition to timing bus transactions, /AS is used by the

interrupt section to set the Interrupt Pending (IP) bits.

2-1

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Interfacing the SCC/ESCC

2.2 Z80X30 INTERFACE TIMING (Continued)

2.2.1 Z80X30 Read Cycle Timing

The read cycle timing for the Z80X30 is shown in Figure 2-1.

The register address on AD7-AD0, as well as the state of

/CS0 and /INTACK, are latched by the rising edge of /AS.

R//W must be High before /DS falls to indicate a read

cycle. The Z80X30 data bus drivers are enabled while CS1

is High and /DS is Low.

/AS

/CS0

/INTACK

AD7 - AD0

Address

Data Valid

R//W

CS1

/DS

Figure 2-1. Z80X30 Read Cycle

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Interfacing the SCC/ESCC

2.2.2 Z80X30 Write Cycle Timing

The write cycle timing for the Z80X30 is shown in

a write cycle. The leading edge of the coincidence of CS1

High and /DS Low latches the write data on AD7-AD0, as

well as the state of R//W.

Figure 2-2. The register address on AD7-AD0, as well as

the state of /CS0 and /INTACK, are latched by the rising

edge of /AS. R//W must be Low when /DS falls to indicate

2

/AS

/CS0

/INTACK

AD7 - AD0

Address

Data Valid

R//W

CS1

/DS

Figure 2-2. Z80X30 Write Cycle

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Interfacing the SCC/ESCC

2.2 Z80X30 INTERFACE TIMING (Continued)

2.2.3 Z80X30 Interrupt Acknowledge Cycle Timing

The interrupt acknowledge cycle timing for the Z80X30 is

shown in Figure 2-3. The address on AD7-AD0 and the

state of /CS0 and /INTACK are latched by the rising edge

of /AS. However, if /INTACK is Low, the address, /CS0,

CS1 and R//W are ignored for the duration of the interrupt

acknowledge cycle.

/AS

/CS0

AD7 - AD0

Vector

/DS

/INTACK

IEI

IEO

/INT

Figure 2-3. Z80X30 Interrupt Acknowledge Cycle

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Interfacing the SCC/ESCC

The Z80X30 samples the state of /INTACK on the rising

edge of /AS, and AC parameters #7 and #8 specify the set-

up and hold-time requirements. Between the rising edge of

/AS and the falling edge of /DS, the internal and external

daisy chains settle (AC parameter #29). A system with no

external daisy chain should provide the time specified in

spec #29 to settle the interrupt daisy-chain priority internal

to the SCC. Systems using an external daisy chain should

refer to Note 5 referenced in the Z80X30 Read/Write & In-

terrupt Acknowledge Timing for the time required to settle

the daisy chain.

Shift Right/Shift Left bit in the Channel B WR0 controls

which bits are decoded to form the register address. It is

placed in this register to simplify programming when the

current state of the Shift Right/Shift Left bit is not known.

2

A hardware reset forces Shift Left mode where the address

is decoded from AD5-AD1. In Shift Right mode, the ad-

dress is decoded from AD4-AD0. The Shift Right/Shift Left

bit is written via a command to make the software writing

to WR0 independent of the state of the Shift Right/Shift

Left bit.

While in the Shift Left mode, the register address is

placed on AD4-AD1 and the Channel Select bit, A/B, is

decoded from AD5. The register map for this case is

shown in Table 2-1. In Shift Right mode, the register ad-

dress is again placed on AD4-AD1 but the channel select

A/B is decoded from AD0. The register map for this case

is shown in Table 2-2.

Note: /INTACK is sampled on the rising edge of /AS. If it

does not meet the setup time to the first rising edge of /AS

of the interrupt acknowledge cycle, it is latched on the next

rising edge of /AS. Therefore, if /INTACK is asynchronous

to /AS, it may be necessary to add a PCLK cycle to the cal-

culation for /INTACK to /RD delay time.

If there is an interrupt pending in the SCC, and IEI is High

when /DS falls, the acknowledge cycle was intended for

the SCC. This being the case, the Z80X30 sets the Inter-

rupt-Under-Service (IUS) latch for the highest priority

pending interrupt, as well as placing an interrupt vector on

AD7-AD0. The placing of a vector on the bus can be dis-

abled by setting WR9, D1=1. The /INT pin also goes inac-

tive in response to the falling edge of /DS. Note that there

should be only one /DS per acknowledge cycle. Another

important fact is that the IP bits in the Z80X30 are updated

by /AS, which may delay interrupt requests if the processor

does not supply /AS strobes during the time between ac-

cesses of the Z80X30.

Because the Z80X30 does not contain 16 read registers,

the decoding of the read registers is not complete; this is

indicated in Table 2-1 and Table 2-2 by parentheses

around the register name. These addresses may also be

used to access the read registers. Also, note that the

Z80X30 contains only one WR2 and WR9; these registers

may be written from either channel.

Shift Left Mode is used when Channel A and B are to be

programmed differently. This allows the software to se-

quence through the registers of one channel at a time. The

Shift Right Mode is used when the channels are pro-

grammed the same. By incrementing the address, the user

can program the same data value into both the Channel A

and Channel B register.

2.2.4 Z80X30 Register Access

The registers in the Z80X30 are addressed via the address

on AD7-AD0 and are latched by the rising edge of /AS. The

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2.2 Z80X30 INTERFACE TIMING (Continued)

Table 2-1. Z80X30 Register Map (Shift Left Mode)

80C30/230*

WR15 D2 = 0

80230

WR15 D2=1

WR7' D6=1

80C30/230

WR15 D2=1

AD5

AD4

AD3

AD2

AD1

WRITE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

WR0B

WR1B

WR2

WR3B

WR4B

WR5B

WR6B

WR7B

WR8B

WR9

WR10B

WR11B

WR12B

WR13B

WR14B

WR15B

WR0A

WR1A

WR2

WR3A

WR4A

WR5A

WR6A

WR7A

WR8A

WR9

RR0B

RR1B

RR2B

RR3B

RR0B

RR1B

RR2B

RR3B

(RR0B)

(RR1B)

RR6B

RR7B

RR8B

(RR13B)

RR10B

(RR15B)

RR12B

RR13B

RR14B

RR15B

RR0A

RR1A

RR2A

RR3A

(RR0A)

(RR1A)

RR6A

RR7A

RR8A

(RR13A)

RR10A

(RR15A)

RR12A

RR13A

RR14A

RR15A

RR0B

RR1B

RR2B

RR3B

(WR4B)

(WR5B)

RR6B

RR7B

RR8B

(WR3B)

RR10B

(WR10B)

RR12B

RR13B

(WR7’B)

RR15B

RR0A

RR1A

RR2A

RR3A

(WR4A)

(WR5A)

RR6A

RR7A

RR8A

(WR3A)

RR10A

(WR10A)

RR12A

RR13A

(WR7’A)

RR15A

(RR0B)

(RR1B)

(RR2B)

(RR3B)

RR8B

(RR13B)

RR10B

(RR15B)

RR12B

RR13B

RR14B

RR15B

RR0A

RR1A

RR2A

RR3A

(RR0A)

(RR1A)

(RR2A)

(RR3A)

RR8A

(RR13A)

RR10A

(RR15A)

RR12A

RR13A

RR14A

RR15A

WR10A

WR11A

WR12A

WR13A

WR14A

WR15A

Notes:

The register names in ( ) are the values read out from that register location.

WR15, bit D2 enables status FIFO function (not available on NMOS).

WR7' bit D6 enables extend read function (only on ESCC).

* Includes 80C30/230 when WR15 D2=0.

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Table 2-2. Z80X30 Register Map (Shift Right Mode)

80230

80C30/230*

WR15 D2 = 0

80C30/230

WR15 D2=1

WR7' D6=1

2

AD4

AD3

AD2

AD1

AD0

WRITE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

WR0B

WR0A

WR1B

WR1A

WR2

RR0B

RR0A

RR1B

RR1A

RR2B

WR2

RR2A

WR3B

WR3A

WR4B

WR4A

WR5B

WR5A

WR6B

WR6A

WR7B

WR7A

WR8B

WR8A

WR9

RR3B

RR3A

(RR0B)

(RR0A)

(RR1B)

(RR1A)

(RR2B)

(RR2A)

(RR3B)

(RR3A)

RR8B

(RR0B)

(RR0A)

(RR1B)

(RR1A)

RR6B

RR6A

RR7B

RR7A

RR8B

(WR4B)

(WR4A)

(WR5B)

(WR5A)

RR6B

RR6A

RR7B

RR7A

RR8B

RR8A

(RR13B)

(RR13A)

RR10B

RR10A

(RR15B)

(RR15A)

RR12B

RR12A

RR13B

RR13A

RR14B

RR14A

RR15B

RR15A

(RR13B)

(RR13A)

RR10B

RR10A

(RR15B)

(RR15A)

RR12B

RR12A

RR13B

RR13A

RR14B

RR14A

RR15B

RR15A

(WR3B)

(WR3A)

RR10B

RR10A

(WR10B)

(WR10A)

RR12B

RR12A

RR13B

RR13A

(WR7’B)

(WR7’A)

RR15B

RR15A

WR9

WR10B

WR10A

WR11B

WR11A

WR12B

WR12A

WR13B

WR13A

WR14B

WR14A

WR15B

WR15A

Notes:

The register names in ( ) are the values read out from that register location.

WR15 bit D2 enables status FIFO function (not available on NMOS).

WR7' bit D6 enables extend read function (only on ESCC).

* Includes 80C30/230 when WR15 D2=0.

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2.2 Z80X30 INTERFACE TIMING (Continued)

WR7' bit D6=1, enables the extended read register capa-

bility. This allows the user to read the contents of WR3,

WR4, WR5, WR7' and WR10 by reading RR9, RR4, RR5,

RR14 and RR11, respectively. When WR7' D6=0, these

write registers are write only.

2.2.5 Z80C30 Register Enhancement

The Z80C30 has an enhancement to the NMOS Z8030

register set, which is the addition of a 10x19 SDLC Frame

Status FIFO. When WR15 bit D2=1, the SDLC Frame Sta-

tus FIFO is enabled, and it changes the functionality of

RR6 and RR7. See Section 4.4.3 for more details on this

feature.

Table 2-3 shows what functions are enabled for the various

combinations of register bit enables. See Table 2-1 (Shift

Left) and Table 2-2 (Shift Right) for the register address map

with the SDLC FIFO enabled only and the map with both the

extended read and SDLC FIFO features enabled.

2.2.6 Z80230 Register Enhancements

In addition to the Z80C30 enhancements, the 80230 has

several enhancements to the SCC register set. These in-

clude the addition of Write Register 7 Prime (WR7'), and

the ability to read registers that are read only in the 8030.

Table 2-3. Z80230 SDLC/HDLC

Enhancement Options

WR15

WR7'

Write Register 7' is addressed by setting WR15 bit, D0=1

and then addressing WR7. Figure 2-4 shows the register

bit location of the six features enabled through this

register. All writes to address seven are to WR7' when

WR15, D0=1. Refer to Chapter 5 for detailed information

on WR7'.

Bit D2 Bit D0 Bit D6 Functions Enabled

0

1

0

1

WR7' enabled only

WR7' with extended read

enabled

10x19 SDLC FIFO

enhancement

1

0

X

WR7'

enabled only

D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

10x19 SDLC FIFO and WR7'

with extended read enabled

Auto Tx Flag

Auto EOM Reset

Auto RTS Turnoff

Rx FIFO Half Full

DTR/REQ Timing M

Tx FIFO Empty

External Read Enab

0

Figure 2-4. Write Register 7 Prime (WR7')

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The Z80X30 has three software resets that are encoded

into two command bits in WR9. There are two channel re-

sets, which only affect one channel in the device and

some bits of the write registers. The command forces the

same result as the hardware reset, the Z80X30 stretches

the reset signal an additional four to five PCLK cycles be-

yond the ordinary valid access recovery time. The bits in

WR9 may be written at the same time as the reset com-

mand because these bits are affected only by a hardware

reset. The reset values of the various registers are shown

in Table 2-4.

2.2.7 Z80X30 Reset

The Z80X30 may be reset by either a hardware or software

reset. Hardware reset occurs when /AS and /DS are both

Low at the same time, which is normally an illegal condi-

tion. As long as both /AS and /DS are Low, the Z80X30

recognizes the reset condition. However, once this condi-

tion is removed, the reset condition is asserted internally

for an additional four to five PCLK cycles. During this time,

any attempt to access is ignored.

2

Table 2-4. Z80X30 Register Reset Values

Hardware RESET

Channel RESET

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

WR0

WR1

WR2

WR3

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

WR4

WR5

WR6

WR7

WR7'*

X

0

X

0

X

0

X

1

X

0

X

0

X

0

X

0

1

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

1

X

0

X

0

X

0

X

0

1

0

X

0

X

0

X

0

X

0

WR9

1

0

X

1

0

X

0

X

0

X

0

1

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

WR10

WR11

WR12

WR13

WR14

WR15

RR0

X

1

X

1

X

1

X

1

X

0

1

X

0

1

X

0

X

0

X

1

X

1

X

1

X

0

1

X

0

1

X

0

1

X

0

X

0

X

1

X

0

RR1

RR3

RR10

0

X

0

1

0

1

0

X

0

X

0

1

0

1

0

X

0

Notes:

*WR7' is available only on the Z80230.

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2.3 Z85X30 INTERFACE TIMING

Two control signals, /RD and /WR, are used by the

Z85X30 to time bus transactions. In addition, four other

control signals, /CE, D//C, A//B and /INTACK, are used to

control the type of bus transaction that occurs. A bus trans-

action starts when the addresses on D//C and A//B are as-

serted before /RD or /WR fall (AC Spec #6 and #8). The

coincidence of /CE and /RD or /CE and /WR latches the

state of D//C and A//B and starts the internal operation.

The /INTACK signal must have been previously sampled

High by a rising edge of PCLK for a read or write cycle to

occur. In addition to sampling /INTACK, PCLK is used by

the interrupt section to set the IP bits.

This recovery time applies only between transactions in-

volving the Z85X30, and any intervening transactions are

ignored. This recovery time is four PCLK cycles (AC Spec

#49), measured from the falling edge of /RD or /WR in the

case of a read or write of any register.

2.3.1 Z85X30 Read Cycle Timing

The read cycle timing for the Z85X30 is shown in

Figure 2-5. The address on A//B and D//C is latched by the

coincidence of /RD and /CE active. /CE must remain Low

and /INTACK must remain High throughout the cycle. The

Z85X30 bus drivers are enabled while /CE and /RD are

both Low. A read with D//C High does not disturb the state

of the pointers and a read cycle with D//C Low resets the

pointers to zero after the internal operation is complete

The Z85X30 generates internal control signals in response

to a register access. Since /RD and /WR have no phase re-

lationship with PCLK, the circuitry generating these inter-

nal control signals provides time for metastable conditions

to disappear. This results in a recovery time related to

PCLK.

.

A//B, D//C

Address Valid

/INTACK

/CE

/RD

Data Valid

D7-D0

Figure 2-5. Z85X30 Read Cycle Timing

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2.3.2 Z85X30 Write Cycle Timing

The write cycle timing for the Z85X30 is shown in Figure 2-

6. The address on A//B and D//C, as well as the data on

D7-D0, is latched by the coincidence of /WR and /CE ac-

tive. /CE must remain Low and /INTACK must remain High

throughout the cycle. A write cycle with D//C High does not

disturb the state of the pointers and a write cycle with D//C

Low resets the pointers to zero after the internal operation

is complete.

Historically, the NMOS/CMOS version latched the data

bus on the falling edge of /WR. However, many CPUs do

not guarantee that the data bus is valid at the time when

the /WR pin goes low, so the data bus timing was modified

to allow a maximum delay from the falling edge of /WR to

the latching of the data bus. On the Z85230, the AC Timing

parameter #29 TsDW(WR), Write Data to /WR falling min-

imum, has been changed to: /WR falling to Write Data Val-

id maximum. Refer to the AC Timing Characteristic section

of the Z85230 Product Specification for more information

regarding this change.

2

Address Valid

A//B, D//C

/INTACK

/CE

/WR

See Note

D7-D0

Data Valid

Note: Dotted line is ESCC only.

Figure 2-6. Z85X30 Write Cycle Timing

2.3.3 Z85X30 Interrupt Acknowledge Cycle Timing

The interrupt acknowledge cycle timing for the Z85X30 is

shown in Figure 2-7. The state of /INTACK is latched by

the rising edge of PCLK (AC Spec #10). While /INTACK is

Low, the state of A//B, /CE, D//C, and /WR are ignored.

/INTACK

/RD

D7-D0

Vector

Figure 2-7. Z85X30 Interrupt Acknowledge Cycle Timing

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2.3 Z85X30 INTERFACE TIMING (Continued)

Between the time /INTACK is first sampled Low and the

time /RD falls, the internal and external IEI/IEO daisy chain

settles (AC parameter #38 TdIAI(RD) Note 5). A system

with no external daisy chain must provide the time speci-

fied in AC Spec #38 to settle the interrupt daisy chain pri-

ority internal to the SCC. Systems using the external

IEI/IEO daisy chain should refer to Note 5 referenced in the

Z85X30 Read/Write and Interrupt Acknowledge Timing for

the time required to settle the daisy chain.

intended for the Z85X30. In this case, the Z85X30 sets the

appropriate Interrupt-Under-Service latch, and places an

interrupt vector on D7-D0.

If the falling edge of /RD sets an IUS bit in the Z85X30, the

/INT pin goes inactive in response to the falling edge. Note

that there should be only one /RD per acknowledge cycle.

Note 1: The IP bits in the Z85X30 are updated by PCLK.

However, when the register pointer is pointing to RR2 and

RR3, the IP bits are prevented from changing. This pre-

vents data changing during a read, but will delay interrupt

requests if the pointers are left pointing at these registers.

Note: /INTACK is sampled on the rising edge of PCLK. If it

does not meet the setup time to the first rising edge of PCLK

of the interrupt acknowledge cycle, it is latched on the next

rising edge of PCLK. Therefore, if /INTACK is asynchronous

to PCLK, it may be necessary to add a PCLK cycle to the

calculation for /INTACK to /RD delay time.

Note 2: The SCC should only receive one INTACK signal

per acknowledge cycle. Therefore, if the CPU generates

more than one (as is common for the 80X86 family), an ex-

ternal circuit should be used to convert this into a single

pulse or does not use Interrupt Acknowledge.

If there is an interrupt pending in the Z85X30, and IEI is

High when /RD falls, the interrupt acknowledge cycle was

The fact that the pointer bits are reset to 0, unless explicitly

set otherwise, means that WR0 and RR0 may also be ac-

cessed in a single cycle. That is, it is not necessary to write

the pointer bits with 0 before accessing WR0 or RR0.

2.3.4 Z85X30 Register Access

The registers in the Z85X30 are accessed in a two step

process, using a Register Pointer to perform the address-

ing. To access a particular register, the pointer bits are set

by writing to WR0. The pointer bits may be written in either

channel because only one set exists in the Z85X30. After

the pointer bits are set, the next read or write cycle of the

Z85X30 having D//C Low will access the desired register.

At the conclusion of this read or write cycle the pointer bits

are reset to 0s, so that the next control write is to the point-

ers in WR0.

There are three pointer bits in WR0, and these allow ac-

cess to the registers with addresses 7 through 0. Note that

a command may be written to WR0 at the same time that

the pointer bits are written. To access the registers with ad-

dresses 15 through 8, the Point High command must ac-

company the pointer bits. This precludes concurrently is-

suing a command when pointing to these registers.

A read to RR8 (the receive data FIFO) or a write to WR8

(the transmit data FIFO) is either done in this fashion or by

accessing the Z85X30 having D//C pin High. A read or

write with D//C High accesses the data registers directly,

and independently of the state of the pointer bits. This al-

lows single-cycle access to the data registers and does not

disturb the pointer bits.

The register map for the Z85X30 is shown in Table 2-5. If,

for some reason, the state of the pointer bits is unknown

they may be reset to 0 by performing a read cycle with the

D//C pin held Low. Once the pointer bits have been set, the

desired channel is selected by the state of the A//B pin dur-

ing the actual read or write of the desired register.

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Table 2-5. Z85X30 Register Map

85C30/230

WR15 D2 = 0

85C30/230

WR15 D2=1

WR7' D6=1

2

A//B

PNT2

PNT1

PNT0

WRITE

0

1

0

1

0

1

WR0B

WR1B

WR2

RR0B

RR1B

RR2B

RR3B

RR0B

RR1B

RR2B

RR3B

RR0B

RR1B

RR2B

RR3B

WR3B

0

1

0

1

0

1

0

1

WR4B

WR5B

WR6B

WR7B

(RR0B)

(RR1B)

(RR2B)

(RR3B)

(RR0B)

(RR1B)

RR6B

(WR4B)

(WR5B)

RR6B

RR7B

1

0

1

0

1

0

1

WR0A

WR1A

WR2

RR0A

RR1A

RR2A

RR3A

RR0A

RR1A

RR2A

RR3A

RR0A

RR1A

RR2A

RR3A

WR3A

1

0

1

0

1

0

1

WR4A

WR5A

WR6A

WR7A

(RR0A)

(RR1A)

(RR2A)

(RR3A)

(RR0A)

(RR1A)

RR6A

(WR4A)

(WR5A)

RR6A

RR7A

With Point High Command

0

1

0

1

0

1

WR8B

WR9

WR10B

WR11B

RR8B

(RR13B)

RR10B

(RR15B)

(RR13B)

RR10B

(RR15B)

(WR3B)

RR10B

(WR10B)

0

1

0

1

0

1

0

1

WR12B

WR13B

WR14B

WR15B

RR12B

RR13B

RR14B

RR15B

RR12B

RR13B

RR14B

RR15B

RR12B

RR13B

(WR7’B)

RR15B

1

0

1

0

1

0

1

WR8A

WR9

WR10A

WR11A

RR8A

(RR13A)

RR10A

(RR15A)

(RR13A)

RR10A

(RR15A)

(WR3A)

RR10A

(WR10A)

1

0

1

0

1

0

1

WR12A

WR13A

WR14A

WR15A

RR12A

RR13A

RR14A

RR15A

RR12A

RR13A

RR14A

RR15A

RR12A

RR13A

(WR7’A)

RR15A

Notes:

WR15 bit D2 enables status FIFO function. (Not available on NMOS)

WR7' bit D6 enables extend read function. (Only on ESCC and 85C30)

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2.3 Z85X30 INTERFACE TIMING (Continued)

2.3.5 Z85C30 Register Enhancement

WR7' Prime

The Z85C30 has an enhancement to the NMOS Z8530

register set, which is the addition of a 10x19 SDLC Frame

Status FIFO. When WR15 bit D2=1, the SDLC Frame Sta-

tus FIFO is enabled, and it changes the functionality of

RR6 and RR7. See Section 4.4.3 for more details on this

feature.

D7 D6 D5 D4 D3 D2 D1 D0

Auto Tx Flag

Auto EOM Reset

Auto/RTS Deactivation

Force TxD High

2.3.6 Z85C30/Z85230 Register

Enhancements

/DTR//REQ Fast Mode

Complete CRC Reception

Extended Read Enable

Reserved (Program as 0)

In addition to the enhancements mentioned in 2.3.5, the

85C30/85230 provides several enhancements to the SCC

register set. These include the addition of Write Register 7

Prime (WR7'), the ability to read registers that are write-

only in the SCC.

Figure 2-8b. Write Register 7 Prime for the 85C30

Write Register 7' is addressed by setting WR15, D0=1 and

then addressing WR7. Figure 2-8 shows the register bit lo-

cation of the six features enabled through this register for

the 85230, while Figure 2-7 shows the register bit location

for the 85C30. Note that the difference between the two

WR7' registers for the 85230 and the 85C30 is bit D5 and

bit D4. All writes to address seven are to WR7' when

WR15 D0=1. Refer to Chapter 5 for detailed information on

WR7'.

Setting WR7' bit D6=1 enables the extended read register

capability. This allows the user to read the contents of

WR3, WR4, WR5, WR7' and WR10 by reading RR9, RR4,

RR5, RR14 and RR11, respectively. When WR7' D6=0,

these write registers are write-only.

Table 2-6 shows what functions are enabled for the vari-

ous combinations of register bit enables. See Table 2-5 for

the register address map with only the SDLC FIFO en-

abled and with both the extended read and SDLC FIFO

features enabled.

WR7'

D7 D6 D5 D4 D3 D2 D1 D0

Table 2-6. Z85C30/Z85230 Register

Enhancement Options

Auto Tx Flag

WR15

WR7'

Auto EOM Reset

Auto/RTS Deactivation

Bit D2 Bit D0 Bit D6 Functions Enabled

0

1

0

1

WR7' enabled only

WR7' with extended read

enabled

Rx FIFO Half Full

DTR/REQ Timing Mode

Tx FIFO Empty

1

0

X

10x19 SDLC FIFO

Extended Read Enable

Reserved (Must be 0)

enhancement enabled only

10x19 SDLC FIFO and WR7'

with extended read enabled

1

0

1

Figure 2-8a. Write Register 7 Prime (WR7')

for the 85230

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The Z85X30 has three software resets that are encoded

into the command bits in WR9. There are two channel re-

sets which only affect one channel in the device and

some bits of the write registers. The command forces the

same result as the hardware reset, the Z85X30 stretches

the reset signal an additional four to five PCLK cycles be-

yond the ordinary valid access recovery time. The bits in

WR9 may be written at the same time as the reset com-

mand because these bits are affected only by a hardware

reset. The reset values of the various registers are shown

in Table 2-7.

2.3.7 Z85X30 Reset

The Z85X30 may be reset by either a hardware or software

reset. Hardware reset occurs when /WR and /RD are both

Low at the same time, which is normally an illegal condi-

tion. As long as both /WR and /RD are Low, the Z85X30

recognizes the reset condition. However, once this condi-

tion is removed, the reset condition is asserted internally

for an additional four to five PCLK cycles. During this time

any attempt to access is ignored.

2

Table 2-7. Z85X30 Register Reset Value

Hardware RESET

Channel RESET

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

WR0

WR1

WR2

WR3

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

WR4

WR5

WR6

WR7

X

0

X

0

X

0

X

1

0

X

0

X

0

X

0

X

0

X

1

0

X

0

X

WR7'*

WR9

WR10

WR11

0

1

0

1

0

1

0

1

0

X

0

X

0

X

0

X

1

0

X

0

X

0

X

0

X

0

X

0

X

0

X

WR12

WR13

WR14

WR15

X

1

X

1

X

1

X

1

X

0

1

X

0

X

0

X

0

X

1

X

1

X

1

X

0

1

X

0

1

X

0

X

0

X

0

RR0

RR1

RR3

RR10

X

0

1

0

X

0

X

0

X

0

1

0

1

0

X

0

X

0

1

0

X

0

X

0

X

0

1

0

1

0

X

0

Notes:

*WR7' is only available on the 85C30 and the ESCC.

2.4 INTERFACE PROGRAMMING

The following subsections explain and illustrate all areas of

interface programming.

Regardless of the version of the SCC, all communication

modes can use a choice of polling, interrupt and block

transfer. These modes are selected by the user to deter-

mine the proper hardware and software required to supply

data at the rate required.

2.4.1 I/O Programming Introduction

The SCC can work with three basic forms of I/O opera-

tions: polling, interrupts, and block transfer. All three I/O

types involve register manipulation during initialization and

data transfer. However, the interrupt mode also incorpo-

rates Z-Bus interrupt protocol for a fast and efficient data

transfer.

Note to ESCC Users: Those familiar with the NMOS/CMOS

version will find the ESCC I/O operations very similar but

should note the following differences: the addition of soft-

ware acknowledge (which is available in the current version

of the CMOS SCC, but not in NMOS); the /DTR//REQ pin

can be programmed to be deasserted faster; and the pro-

grammability of the data interrupts to the FIFO fill level.

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Interfacing the SCC/ESCC

2.4 INTERFACE PROGRAMMING (Continued)

2.4.2 Polling

2.4.3 Interrupts

This is the simplest mode to implement. The software must

poll the SCC to determine when data is to be input or out-

put from the SCC. In this mode, MIE (WR9, bit 3), and

Wait/DMA Request Enable (WR1, bit 7) are both reset to 0

to disable any interrupt or DMA requests. The software

must then poll RR0 to determine the status of the receive

buffer, transmit buffer and external status.

Each of the SCC’s two channels contain three sources of

interrupts, making a total of six interrupt sources. These

three sources of interrupts are: 1) Receiver, 2) Transmit-

ter, and 3) External/Status conditions. In addition, there

are several conditions that may cause these interrupts.

Figure 2-9 shows the different conditions for each interrupt

source and each is enabled under program control. Chan-

nel A has a higher priority than Channel B with Receive,

Transmit, and External/Status Interrupts prioritized, re-

spectively, within each channel as shown in Table 2-8. The

SCC internally updates the interrupt status on every PCLK

cycle in the Z85X30 and on /AS in the Z80X30.

During a polling sequence, the status of Read Register 0

is examined in each channel. This register indicates

whether or not a receive or transmit data transfer is need-

ed and whether or not any special conditions are present,

e.g., errors.

Table 2-8. Interrupt Source Priority

This method of I/O transfer avoids interrupts and, conse-

quently, all interrupt functions should be disabled. With no

interrupts enabled, this mode of operation must initiate a

read cycle of Read Register 0 to detect an incoming char-

acter before jumping to a data handler routine.

Receive Channel A

Highest

Transmit Channel A

External/Status Channel A

Receive Channel B

Transmit Channel B

External/Status Channel B

Lowest

INT on first Rx Character

or Special Condition

INT on all Rx Character

or Special Condition

Receive Character Available

Receive Overrun

Rx Interrupt on Special

Condition Only

Framing Error

Receiver

Interrupt

Sources

End of Frame (SDLC)

Parity Error (If enabled)

Transmitter

Interrupt

Source

SCC

Interrupt

Transmit Buffer Empty

Zero Count

DCD

SYNC/HUNT

CTS

External/Status

Interrupt

Sources

Tx Underrun/EOM

Break/Abort

Figure 2-9. ESCC Interrupt Sources

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Interfacing the SCC/ESCC

ESCC:

The External/status interrupts have several sources which

may be individually enabled in WR15. The sources are

zero count, /DCD, Sync/Hunt, /CTS, transmitter under-

run/EOM and Break/Abort.

The receive interrupt request is either caused by a re-

ceive character available or a special condition. When

the receive character available interrupt is generated,

it is dependent on WR7' bit D3. If WR7' D3=0, the re-

ceive character available interrupt is generated when

one character is loaded into the FIFO and is ready to

be read. If WR7' D3=1, the receive character available

interrupt is generated when four bytes are available to

be read in the receive data FIFO. The programmed val-

ue of WR7' D5 also affects how DMA requests are gen-

erated. See Section 2.5 for details.

2

2.4.4 Interrupt Control

In addition to the MIE bit that enables or disables all SCC

interrupts, each source of interrupt in the SCC has three

control/status bits associated with it. They are the Interrupt

Enable (IE), Interrupt Pending (IP), and Interrupt-Under-

Service (IUS). Figure 2-10 shows the SCC interrupt

structure.

Note: If the ESCC is used in SDLC mode, it enables the

SDLC Status FIFO to affect how receive interrupts are

generated. If this feature is used, read Section 4.4.3 on the

SDLC Anti-Lock Feature.

Interrupt Vector

The special conditions are Receive FIFO overrun,

CRC/framing error, end of frame, and parity. If parity is in-

cluded as a special condition, it is dependent on WR1 D2.

The special condition status can be read from RR1.

IE

MIE

DLC

IP

IUS

On the NMOS/CMOS versions, set the IP bit whenever the

transmit buffer becomes empty. This means that the trans-

mit buffer was full before the transmit IP can be set.

IEI

/INT /INTACK IEO

from Pullup

Resistor or IEO

line of Higher

To IEI Input of

Lower Priority

Device

ESCC:

From

CPU

Status

The transmit interrupt request has only one source

and is dependent on WR7' D5. If the IP bit WR7' D5=0,

it is set when the transmit buffer becomes completely

empty. If IP bit WR7' D5=1, the transmit interrupt is

generated when the entry location of the FIFO is emp-

ty. Note that in both cases the transmit interrupt is not

set until after the first character is written to the ESCC.

Priority Device

To CPU

Decoder

Figure 2-10. Peripheral Interrupt Structure

Figure 2-11 shows the internal priority resolution method

to allow the highest priority interrupt to be serviced first.

Lower priority devices on the external daisy chain can be

prevented from requesting interrupts via the Disable Lower

Chain bit in WR9 D2.

For more information on Transmit Interrupts, see Section

2.4.8 for details.

Channel A

Receiver

(Highest Priority)

Channel A

External/Status

Conditions

Channel A

Transmitter

from

IEI

IE

IEO

IUS

IEI

IE

IEO

IUS

IEI

IE

IEO

IUS

IP

Channel B

External/Status

Conditions

(Lowest

Channel B

Receiver

Channel B

Transmitter

To

IEO

IEI

IE

IEO

IUS

IEI

IE

IEO

IUS

IEI

IEO

Priority)

IP

IE

IP IUS

Figure 2-11. Internal Priority Resolution

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Interfacing the SCC/ESCC

2.4 INTERFACE PROGRAMMING (Continued)

2.4.4.1 Master Interrupt Enable Bit

2.4.4.4 Interrupt-Under-Service Bit

The Master Interrupt Enable (MIE) bit, WR9 D3, must be

set to enable the SCC to generate interrupts. The MIE bit

should be set after initializing the SCC registers and en-

abling the individual interrupt enables. The SCC requests

an interrupt by asserting the /INT pin Low from its open-

drain state only upon detection that one of the enabled in-

terrupt conditions has been detected.

The Interrupt-Under-Service (IUS) bits are completely hid-

den from the processor. An IUS bit is set during an inter-

rupt acknowledge cycle for the highest priority IP. On the

CMOS or ESCC, the IUS bits can be set by either a hard-

ware acknowledge cycle with the /INTACK pin or through

software if WR9 D5=1 and then reading RR2.

The IUS bits control the operation of internal and external

daisy-chain interrupts. The internal daisy chain links the

six sources of interrupt in a fixed order, chaining the IUS

bit of each source. If an internal IUS bit is set, all lower pri-

ority interrupt requests are masked off; during an interrupt

acknowledge cycle the IP bits are also gated into the daisy

chain. This ensures that the highest priority IP selected

has its IUS bit set. At the end of an interrupt service rou-

tine, the processor must issue a Reset Highest IUS com-

mand in WR0 to re-enable lower priority interrupts. This is

the only way, short of a software or hardware reset, that an

IUS bit may be reset.

2.4.4.2 Interrupt Enable Bit

The Interrupt Enable (IE) bits control interrupt requests

from each interrupt source on the SCC. If the IE bit is set

to 1 for an interrupt source, that source may generate an

interrupt request, providing all of the necessary conditions

are met. If the IE bit is reset, no interrupt request is gener-

ated by that source. The transmit interrupt IE bit is WR1

D1. The receive interrupt IE bits are WR1 D3 and D4. The

external status interrupts are individually enabled in WR15

with the master external status interrupt enable in WR1

D0. Reminder: The MIE bit, WR9 D3, must be set for any

interrupt to occur.

Note: It is not necessary to issue the Reset Highest IUS

command in the interrupt service routine, since the IUS

bits can only be set by an interrupt acknowledge if no hard-

ware acknowledge or software acknowledge cycle (not

with NMOS) is executed. The only exception is when the

SDLC Frame Status FIFO (not with NMOS) is enabled and

“receive interrupt on special condition only” is used. See

section 4.4.3 for more details on this mode.

2.4.4.3 Interrupt Pending Bit

The Interrupt Pending (IP) bit for a given source of interrupt

is set by the presence of an interrupt condition in the SCC.

It is reset directly by the processor, or indirectly by some

action that the processor may take. If the corresponding IE

bit is not set, the IP for that source of interrupt will never be

set. The IP bits in the SCC are read only via RR3 as shown

in Figure 2-12.

2.4.4.5 Disable Lower Chain Bit

The Disable Lower Chain (DLC) bit in WR9 (D2) is used to

disable all peripherals in a lower position on the external

daisy chain. If WR9 D2=1, the IEO pin is driven Low and

prevents lower priority devices from generating an inter-

rupt request. Note that the IUS bit, when set, will have the

same effect, but is not controllable through software.

Read Register 3

D7 D6 D5 D4 D3 D2 D1 D0

Channel B Ext/Stat

Channel B Tx IP

Channel B Rx IP

Channel A Ext/Stat

Channel A Tx IP

Channel A Rx IP

0

*

Always 0 In B Channel

Figure 2-12. RR3 Interrupt Pending Bits

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Interfacing the SCC/ESCC

When the processor requests an interrupt vector, only the

highest priority interrupt source with a pending interrupt

(IP is 1) has its IEI input High, its IE bit set to 1, and its IUS

bit set to 0. This is the interrupt source being acknowl-

edged, and at this point it sets its IUS bit to 1. If its NV bit

is 0, the SCC identifies itself by placing the interrupt vector

from WR2 on the data bus. If the NV bit is 1, the SCC data

bus remains floating, allowing external logic to supply a

vector. If the VIS bit in the SCC is 1, the vector also con-

tains status information, encoded as shown in Table 2-9,

which further describes the nature of the SCC interrupt.

2.4.5 Daisy-Chain Resolution

The six sources of interrupt in the SCC are prioritized in a

fixed order via a daisy chain; provision is made, via the IEI

and IEO pins, for use of an external daisy chain as well. All

Channel A interrupts are higher priority than any

Channel B interrupts, with the receiver, transmitter, and

External/Status interrupts prioritized in that order within

each channel. The SCC requests an interrupt by pulling

the /INT pin Low from its open-drain state. This is con-

trolled by the IP bits and the IEI input, among other things.

A flowchart of the interrupt sequence for the SCC is shown

in Figure 2-13.

2

Table 2-9. Interrupt Vector Modiﬁcation

The internal daisy chain links the six sources of interrupt in

a fixed order, chaining the IUS bits for each source. While

an IUS bit is set, all lower priority interrupt requests are

masked off, thus preventing lower priority interrupts, but

still allowing higher priority interrupts to occur. Also, during

an interrupt acknowledge cycle the IP bits are gated into

the daisy chain. This insures that the highest priority IP is

selected to set IUS. The internal daisy chain may be con-

trolled by the MIE bit in WR9. This bit, when reset, has the

same effect as pulling the IEI pin Low, thus disabling all in-

terrupt requests.

V3

V4

V2

V5

V1

V6

Status High/Status Low = 0

Status High/Status Low = 1

0

1

0

1

0

1

Ch B Transmit Buffer Empty

Ch B External/Status Change

Ch B Receive Character Avail

Ch B Special Receive Condition

1

0

1

0

1

0

1

Ch A Transmit Buffer Empty

Ch A External/Status Change

Ch A Receive Character Avail

Ch A Special Receive Condition

2.4.5.1 External Daisy-Chain Operations

If the VIS bit is 0, the vector held in WR2 is returned without

modification. If the SCC is programmed to include status

information in the vector, this status may be encoded and

placed in either bits 1-3 or in bits 4-6. This operation is

selected by programming the Status High/Status Low bit in

WR9. At the end of the interrupt service routine, the

processor should issue the Reset Highest IUS command

to unlock the daisy chain and allow lower priority interrupt

requests. The IP is reset during the interrupt service

routine, either directly by command or indirectly through

some action taken by the processor. The external daisy

chain may be controlled by the DLC bit in WR9. This bit,

when set, forces IEO Low, disabling all lower priority

devices.

The SCC generates an interrupt request by pulling /INT

Low, but only if such interrupt requests are enabled

(IE is 1, MIE is 1) and all of the following conditions occur:

■ IP is set without a higher priority IUS being set

■ No higher priority IUS is being set

■ No higher priority interrupt is being serviced (IEI is High)

■ No interrupt acknowledge transaction is taking place

IEO is not pulled Low by the SCC at this time, but instead

continues to follow IEI until an interrupt acknowledge

transaction occurs. Some time after /INT has been pulled

Low, the processor initiates an Interrupt Acknowledge

transaction. Between the time the SCC recognizes that an

Interrupt Acknowledge cycle is in progress and the time

during the acknowledge that the processor requests an in-

terrupt vector, the IEI/IEO daisy chain settles. Any periph-

eral in the daisy chain having an Interrupt Pending (IP is 1)

or an Interrupt-Under-Service (IUS is 1) holds its IEO line

Low and all others make IEO follow IEI.

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Interfacing the SCC/ESCC

2.4 INTERFACE PROGRAMMING (Continued)

Start

Interrupt

Condition

Exits?

No

Yes

Specific

Interrupt Enabl

(IEx=1)?

Yes

Interrupt Pendi

Set (IP=1)

Master

Interrupt Enable

(MIE=1)?

No

Yes

Is Peripheral

Enable Pin Ac

(IEI=H)?

Yes

Peripheral Request

Interrupt (INT=L)

CPU Initiates Statu

Decode (INTACK=L

IEI/IEO Daisy Chain

Settles (Wait for DS

Has Higher

Priority Periphera

Disabled Unit?

(IEI=L)

No

Unit Selected for CPU

Service (IUS=1)

Yes

Service

Routine Comple

?

No

CPU Services High

Priority Periphera

Yes

Priority

Service

No

(Option) Check Oth

Internal IP, Bits,

RESET IUS and Ex

Complete?

Yes

Interrupt Still

Pending (IP=1)

?

No

Figure 2-13. Interrupt Flow Chart (for each interrupt source).

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Interfacing the SCC/ESCC

If the No Vector bit is set (WR9 D1=1), the SCC will not

place the vector on the data bus. An interrupt controller

must then vector the code to the interrupt routine. The in-

terrupt routine reads RR2 from Channel B to read the sta-

tus. This is similar to an interrupt without an acknowledge,

except the IUS is set and the vector will not change until

the Reset IUS command in RR0 is issued.

2.4.6 Interrupt Acknowledge

The SCC is flexible with its interrupt method. The interrupt

may be acknowledged with a vector transferred, acknowl-

edged without a vector, or not acknowledged at all.

2

2.4.6.1 Interrupt Without Acknowledge

In this mode, the Interrupt Acknowledge signal does not

have to be generated. This allows a simpler hardware de-

sign that does not have to meet the interrupt acknowledge

timing. Soon after the INT goes active, the interrupt con-

troller jumps to the interrupt routine. In the interrupt routine,

the code must read RR2 from Channel B to read the vector

including status. When the vector is read from Channel B,

it always includes the status regardless of the VIS bit (WR9

bit 0). The status given will decode the highest priority in-

terrupt pending at the time it is read. The vector is not

latched so that the next read could produce a different vec-

tor if another interrupt occurs. The register is disabled from

change during the read operation to prevent an error if a

higher interrupt occurs exactly during the read operation.

2.4.6.3 Software Interrupt Acknowledge (CMOS/ESCC)

An interrupt acknowledge cycle can be done in software

for those applications which use an external interrupt con-

troller or which cannot generate the /INTACK signal with

the required timing. If WR9 D5 is set, reading register two,

RR2, results in an interrupt acknowledge cycle to be exe-

cuted internally. Like a hardware INTACK cycle,

a software acknowledge causes the /INT pin to return

High, the IEO pin to go Low and the IUS latch to be set for

the highest priority interrupt pending.

As when the hardware /INTACK signal is used, a software

acknowledge cycle requires that a Reset Highest IUS

command be issued in the interrupt service routine. If RR2

is read from Channel A, the unmodified vector is returned.

If RR2 is read from Channel B, then the vector is modified

to indicate the source of the interrupt. The Vector Includes

Status (VIS) and No Vector (NV) bits in WR9 are ignored

when bit D5 is set to 1.

Once the status is read, the interrupt routine must decode

the interrupt pending, and clear the condition. Removing

the interrupt condition clears the IP and brings /INT inac-

tive (open-drain), as long as there are no other IP bits set.

For example, writing a character to the transmit buffer

clears the transmit buffer empty IP.

2.4.7 The Receiver Interrupt

When the interrupt IP, decoded from the status, is cleared,

RR2 can be read again. This allows the interrupt routine to

clear all of the IP’s within one interrupt request to the CPU.

The sources of receive interrupts consist of Receive Char-

acter Available and Special Receive Condition. The Spe-

cial Receive Condition can be subdivided into Receive

Overrun, Framing Error (Asynchronous) or End of Frame

(SDLC). In addition, a parity error can be a special receive

condition by programming.

2.4.6.2 Interrupt With Acknowledge

After the SCC brings /INT active, the CPU can respond

with a hardware acknowledge cycle by bringing /INTACK

active. After enough time has elapsed to allow the daisy

chain to settle (see AC Spec #38), the SCC sets the IUS

bit for the highest priority IP. If the No Vector bit is reset

(WR9 D1=0), the SCC then places the interrupt vector on

the data bus during a read. To speed the interrupt re-

sponse time, the SCC can modify 3 bits in the vector to in-

dicate the source of the interrupt. To include the status, the

VIS bit, WR9 D0, is set. The service routine must then

clear the interrupting condition. For example, writing a

character to the transmit buffer clears the transmit buffer

empty IP. After the interrupting condition is cleared, the

routine can read RR3 to determine if any other IP’s are set

and take the appropriate action to clear them. At the end

of the interrupt routine, a Reset IUS command (WR0) is is-

sued to unlock the daisy chain and allow lower-priority in-

terrupt requests. This is the only way, short of a software

or hardware reset, that an IUS bit is reset.

As shown in Figure 2-14, Receive Interrupt mode is

controlled by three bits in WR1. Two of these bits, D4 and

D3, select the interrupt mode; the third bit, D2, is a modifier

for the various modes. On the ESCC, WR7' bit D2 affects

the receiver interrupt operation mode as well. If the

interrupt capability of the receiver in the SCC is not

required, polling may be used. This is selected by disabling

receive interrupts and polling the Receiver Character

Available bit in RR0. When this bit indicates that a received

character has reached the exit location (CPU side) of the

FIFO, the status in RR1 should be checked and then the

data should be read. If status is checked, it must be done

before the data is read, because the act of reading the data

pops both the data and error FIFOs. Another way of polling

SCC is to enable one of the interrupt modes and then reset

the MIE bit in WR9. The processor may then poll the IP bits

in RR3A to determine when receive characters are

available.

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Interfacing the SCC/ESCC

2.4 INTERFACE PROGRAMMING (Continued)

WR1

D4 D3 D2

Parity is special condition

00 Receive Interrupt Disabled

01 Rx INT On First Character or Special Condition

10 Rx INT On All Receive Characters or Special Condition

11 Rx INT On Special Condition Only

Figure 2-14. Write Register 1 Receive Interrupt Mode Control

2.4.7.1 Receive Interrupt on the ESCC

On the ESCC, one other bit, WR7' bit D2, also affects the

interrupt operation.

and no special conditions have been detected. There-

fore, the interrupt service routine can read four bytes

from the data FIFO without having to read RR1 to check

for error conditions.

WR7' D3=0, a receive interrupt is generated when one

byte is available in the FIFO. This mode is selected after

reset and maintains compatibility with the SCC. Systems

with a long interrupt response time can use this mode to

generate an interrupt when one byte is received, but still al-

low up to seven more bytes to be received without an over-

run error. By polling the Receive Character Available bit,

RR0 D0, and reading all available data to empty the FIFO

before exiting the interrupt service routine, the frequency

of interrupts can be minimized.

Case 2: Data Received with Error Conditions. When any

of the four bytes from the exit side in the receive error FIFO

indicate an error has been detected, a Special Receive

condition interrupt is triggered without waiting for the byte

to reach the top of the FIFO. In this case, the interrupt ser-

vice routine must read RR1 first before reading each data

byte to determine which byte has the special receive con-

dition and then take the appropriate action. Since, in this

mode, the status must be checked before the data is read,

the data FIFO is not locked and the Error Reset command

is not necessary.

WR7' D3=1, the ESCC generates an interrupt when there

are four bytes in the Receive FIFO or when a special con-

dition is received. By setting this bit, the ESCC generates

a receive interrupt when four bytes are available to read

from the FIFO. This allows the CPU not to be interrupted

until at least four bytes can be read from the FIFO, thereby

minimizing the frequency of receive interrupts. If four or

more bytes remain in the FIFO when the Reset Highest

IUS command is issued at the end of the service routine,

another receive interrupt is generated.

Note: The above cases assume that the receive IUS bit is

reset to zero in order for an interrupt to be generated.

WR7' D3 should be written zero when using Interrupt on

First Character and Special Condition or Interrupt on Spe-

cial Condition Only. See the description for Interrupt on All

Characters or Special Condition mode for more details on

this feature.

Note: The Receive Character Available Status bit, RR0

D0, indicates if at least one byte is available in the Receive

FIFO, independent of WR7' D3. Therefore, this bit can be

polled at any time for status if there is data in the Receive

FIFO.

When a special receive condition is detected in the top four

bytes, a special receive condition interrupt is generated

immediately. This feature is intended to be used with the

Interrupt On All Receive Characters and Special Condition

mode. This is especially useful in SDLC mode because the

characters are contiguous and the reception of the closing

flag immediately generates a special receive interrupt. The

generation of receive interrupts is described in the follow-

ing two cases:

2.4.7.2 Receive Interrupts Disabled

This mode prevents the receiver from requesting an inter-

rupt. It is used in a polled environment where either the

status bits in RR0 or the modified vector in RR2 (Channel

B) is read. Although the receiver interrupts are disabled,

the interrupt logic can still be used to provide status.

Case 1: Four Bytes Received with No Errors. A receive

character available interrupt is triggered when the four

bytes in receive data FIFO (from the exit side) are full

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When these bits indicate that a received character has

reached the exit location of the FIFO, the status in RR1

should be checked and then the data should be read. If

status is to be checked, it must be done before the data is

read, because the act of reading the data pops both the

data and error FIFOs.

On the ESCC with D3=1, four bytes are accumulated in the

Receive FIFO before an interrupt is generated (IP is set),

and reset when the number of the characters in the FIFO

is less than four.

2

The special receive conditions are identical to those previ-

ously mentioned, and as before, the only difference be-

tween a “receive character available” interrupt and a “spe-

cial receive condition” interrupt is the status encoded in the

vector. In this mode a special receive condition does not

lock the receive data FIFO so that the service routine must

read the status in RR1 before reading the data.

2.4.7.3 Receive Interrupt on First Character or Special

Condition

This mode is designed for use with DMA transfers of the

receive characters. The processor is interrupted when the

SCC receives the first character of a block of data. It reads

the character and then turns control over to a DMA device

to transfer the remaining characters. After this mode is se-

lected, the first character received, or the first character al-

ready stored in the FIFO, sets the receiver IP. This IP is re-

set when this character is removed from the SCC.

At moderate to high data rates where the interrupt over-

head is significant, time can usually be saved by checking

for another character before exiting the service routine.

This technique eliminates the interrupt acknowledge and

the status processing, saving time, but care must be exer-

cised because this receive character must be checked for

special receive conditions before it is removed from

the SCC.

No further receive interrupts occur until the processor is-

sues an Enable Interrupt on Next Receive Character com-

mand in WR0 or until a special receive condition occurs.

The correct sequence of events when using this mode is

to first select the mode and wait for the receive character

available interrupt. When the interrupt occurs, the proces-

sor should read the character and then enable the DMA to

transfer the remaining characters.

2.4.7.5 Receive Interrupt on Special Conditions

This mode is designed for use when a DMA transfers all

receive characters between memory and the SCC. In this

mode, only receive characters with special conditions will

cause the receive IP to be set. All other characters are as-

sumed to be transferred via DMA. No special initialization

sequence is needed in this mode. Usually, the DMA is ini-

tialized and enabled, then this mode is selected in the

SCC. A special receive condition interrupt may occur at

any time after this mode is selected, but the logic guaran-

tees that the interrupt will not occur until after the character

with the special condition has been read from the SCC.

The special condition locks the FIFO so that the status is

valid when read in the interrupt service routine, and it guar-

antees that the DMA will not transfer any characters until

the special condition has been serviced.

ESCC:

WR7' bit D3 should be reset to zero in this mode.

A special receive condition interrupt may occur any time

after the first character is received, but is guaranteed to oc-

cur after the character having the special condition has

been read. The status is not lost in this case, however, be-

cause the FIFO is locked by the special condition. In the in-

terrupt service routine, the processor should read RR1 to

obtain the status, and may read the data again if neces-

sary. The FIFO is unlocked by issuing an Error Reset com-

mand in WR0. If the special condition was End-of-Frame,

the processor should now issue the Enable Interrupt on

Next Receive Character command to prepare for the next

frame. The first character interrupt and special condition

interrupt are distinguished by the status included in the in-

terrupt vector. In all other respects they are identical, in-

cluding sharing the IP and IUS bits.

In the service routine, the processor should read RR1 to

obtain the status and unlock the FIFO by issuing an Error

Reset command. DMA transfer of the receive characters

then resumes. Figure 2-15 shows the special conditions

interrupt service routine.

Note: On the CMOS and ESCC, if the SDLC Frame Status

FIFO is being used, please refer to Section 4.4.3 on the

FIFO anti-lock feature.

2.4.7.4 Interrupt on All Receive Characters or Special

Condition

This mode is designed for an interrupt driven system. In

this mode, the NMOS/CMOS version and the ESCC with

WR7' D3=0 sets the receive IP when a received character

is shifted into the exit location of the FIFO. This occurs

whether or not it has a special receive condition. This in-

cludes characters already in the FIFO when this mode is

selected. In this mode of operation the IP is reset when the

character is removed from the FIFO, so if the processor re-

quires status for any characters, this status must be read

before the data is removed from the FIFO.

Note: Special Receive Condition interrupts are generated

after the character is read from the FIFO, not when the

special condition is first detected. This is done so that

when using receive interrupt on first or Special Condition

or Special Condition Only, data is directly read out of the

data FIFO without checking the status first. If a special

condition interrupted the CPU when first detected, it would

be necessary to read RR1 before each byte in the FIFO to

determine which byte had the special condition. Therefore,

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2.4 INTERFACE PROGRAMMING (Continued)

by not generating the interrupt until after the byte has been

read and then locking the FIFO, only one status read is

necessary. A DMA can be used to do all data transfers

(otherwise, it would be necessary to disable the DMA to

allow the CPU to read the status on each byte).

Consequently, since the special condition locks the FIFO

to preserve the status, it is necessary to issue the Error

Reset command to unlock it. Only the exit location of the

FIFO is locked allowing more data to be received into the

other bytes of the Receive FIFO.

Special

Condition

Is It

Parity

(RR1 Bit 4)?

Yes

Error Handli

1

No

Is It

Overrun

(RR1 Bit 5)?

Error Handli

No

Is It

EOF

(RR1 Bit 7

Is It

CRC Error

(RR1 Bit 6)?

Yes

Error Handli

No

Is It

Framing

(RR1 Bit 6)

No

1

Yes

Good Messag

1

Reads Dat

Characte

Error Handli

1

Reset Highest IU

(WR0 - 38)

Re

Figure 2-15. Special Conditions Interrupt Service Flow

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Interfacing the SCC/ESCC

byte is loaded into the Transmit Shift Register, but before

the last bit of the second CRC byte has cleared the Trans-

mit Shift Register, then data was written while the CRC

was being sent.

2.4.8 Transmit Interrupts and Transmit Buffer

Empty Bit

Transmit interrupts are controlled by Transmit Interrupt

Enable bit (D1) in WR1. If the interrupt capabilities of the

SCC are not required, polling may be used. This is select-

ed by disabling transmit interrupts and polling the Transmit

Buffer Empty bit (TBE) in RR0. When the TBE bit is set, a

character may be written to the SCC without fear of writing

over previous data. Another way of polling the SCC is to

enable transmit interrupts and then reset Master Interrupt

Enable bit (MIE) in WR9. The processor may then poll the

IP bits in RR3A to determine when the transmit buffer is

empty. Transmit interrupts should also be disabled in the

case of DMA transfer of the transmitted data.

2

2.4.8.2 Transmit Interrupt and Transmit Buffer Empty

bit on the ESCC

The ESCC has a 4-byte deep Transmit FIFO, while the

NMOS/CMOS SCC is just 1-byte deep. For this reason,

the generation of transmit interrupts is slightly different

from that of the NMOS/CMOS SCC version. The ESCC

has two modes of transmit interrupt generation, which are

programmed by bit D5 of WR7'. One transmit mode gener-

ates interrupts when the entry location (the location the

CPU writes data) of the Transmit FIFO is empty. This al-

lows the ESCC response to be tailored to system require-

ments for the frequency of interrupts and the interrupt re-

sponse time. On the other hand, the Transmit Buffer

Empty (TBE) bit on the ESCC will respond the same way

in each mode, in which the bit will become set when the

entry location of the Transmit FIFO is empty. The TBE bit

is not directly related to the transmit interrupt status nor the

state of WR7' bit D5.

Because the depth of the transmitter buffer is different be-

tween the NMOS/CMOS version of the SCC and ESCC,

generation of the transmit interrupt is slightly different. The

following subsections describe transmit interrupts.

Note: For all interrupt sources, the Master Interrupt Enable

(MIE) bit, WR9 bit D3, must be set for the device to gener-

ate a transmit interrupt.

When WR7' D5=1 (the default case), the ESCC will gener-

ate a transmit interrupt when the Transmit FIFO becomes

completely empty. The transmit interrupt occurs when the

data in the exit location of the Transmit FIFO loads into the

Transmit Shift Register and the Transmit FIFO becomes

completely empty. This mode minimizes the frequency of

transmit interrupts by writing 4 bytes to the Transmit FIFO

upon each entry to the interrupt will become set when

WR7' D5=1. The TBE bit RR0 bit D2 will become set when-

ever the entry location of the Transmit FIFO becomes

empty. The TBE bit will reset when the entry location be-

comes full. The TBE bit in a sense translates to meaning

“Transmit Buffer Not Full” for the ESCC only, as the TBE

bit will become set whenever the entry location of the

Transmit FIFO becomes empty. This bit may be polled at

any time to determine if a byte can be written to the FIFO.

Figure 2-17 illustrates when the TBE bit will become set.

WR7' bit D5 is set to one by a hardware or channel reset.

2.4.8.1 Transmit Interrupts and Transmit Buffer Empty

Bit on the NMOS/CMOS

The NMOS/CMOS version of the SCC only has a one byte

deep transmit buffer. The status of the transmit buffer can

be determined through TBE bit in RR0, bit D2, which

shows whether the transmit buffer is empty or not. After a

hardware reset (including a hardware reset by software),

or a channel reset, this bit is set to 1.

While transmit interrupts are enabled, the NMOS/CMOS

version sets the Transmit Interrupt Pending (TxIP) bit

whenever the transmit buffer becomes empty. This means

that the transmit buffer must be full before the TxIP can be

set. Thus, when transmit interrupts are first enabled, the

TxIP will not be set until after the first character is written

to the NMOS/CMOS. In synchronous modes, one other

condition can cause the TxIP to be set. This occurs at the

end of a transmission after the CRC is sent. When the last

bit of the CRC has cleared the Transmit Shift Register and

the flag or sync character is loaded into the Transmit Shift

Register, the NMOS/CMOS version sets the TxIP and TBE

bit. Data for a second frame or block transmission may be

written at this time.

When WR7' D5=0, the TxIP bit is set when the entry lo-

cation of the Transmit FIFO becomes empty. In this

mode, only one byte is written to the Transmit FIFO at a

time for each transmit interrupt. The ESCC will generate

transmit interrupts when there are 3 or fewer bytes in the

FIFO, and will continue to do so until the FIFO is filled.

When WR7' D5=0, the transmit interrupt is reset momen-

tarily when data is loaded into the entry location of the

Transmit FIFO. Transmit interrupt is not generated when

the entry location of the Transmit FIFO is filled. The trans-

mit interrupt is generated when the data is pushed down

the FIFO and the entry location becomes empty (approx-

imately one PCLK time). Figure 2-18 illustrates when the

transmit interrupts will become set when WR7' D5=0.

Again, the TBE bit is not dependent on the state of WR7'

The TxIP is reset either by writing data to the transmit buff-

er or by issuing the Reset Tx Int command in WR0. Ordi-

narily, the response to a transmit interrupt is to write more

data to the device; however, the Reset Tx Int command

should be issued in lieu of data at the end of a frame or a

block of data where the CRC is to be sent next.

Note: A transmit interrupt may indicate that the packet has

terminated illegally, with the CRC byte(s) overwritten by

the data. If the transmit interrupt occurs after the first CRC

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Interfacing the SCC/ESCC

2.4 INTERFACE PROGRAMMING (Continued)

bit D5 nor the transmit interrupt status, and will respond

exactly the same way as mentioned above. Figure 2-17 il-

lustrates when the TBE bit will become set.

cleared the Transmit Shift Register and the flag or sync

character is loaded into the Transmit Shift Register, the

ESCC sets the TxIP. Data for the new frame or block to be

transmitted may be written at this time. In this particular

case, the Transmit Buffer Empty bit in RR0 and the TxIP

are set.

Note: When WR7' D5=0. only one byte is written to the

FIFO at a time, when there are three or fewer bytes in

FIFO. Thus, for the ESCC multiple interrupts are generat-

ed to fill the FIFO. To avoid multiple interrupts, one can poll

the TBE bit (RR0 D2) after writing each byte.

An enhancement to the ESCC from the NMOS/CMOS ver-

sion is that the CRC has priority over the data, where on

the NMOS/CMOS version data has priority over the CRS.

This means that on the ESCC the CRC bytes are guaran-

teed to be sent, even if the data for the next packet has

written before the second transmit interrupt, but after the

EOM/Underrun condition exists. This helps to increase the

system throughput because there is not waiting for the

second transmit interrupt. On the NMOS/CMOS version, if

the data is written while the CRC is sent, CRC byte(s) are

replaced with the flag/sync pattern followed by the data.

While transmit interrupts are enabled, the ESCC sets the

TxIP when the transmit buffer reaches the condition pro-

grammed in WR7' bit D5. This means that the transmit

buffer must have been written to before the TxIP is set.

Thus, when transmit interrupts are first enabled, the trans-

mit IP is not set until the programmed interrupting condition

is met.

The TxIP is reset either by writing data to the transmit buff-

er or by issuing the Reset Tx Int Pending command in

WR0. Ordinarily, the response to a transmit interrupt is to

write more data to the ESCC; however, if there is no more

data to be transmitted at that time, it is the end of the

frame. The Reset Tx Int command is used to reset the TxIP

and clear the interrupt. For example, at the end of a frame

or block of data where the CRC is to be sent next, the Re-

set Tx Int Pending command should be issued after the

last byte of data has been written to the ESCC.

Another enhancement of the ESCC is that it latches the

transmit interrupt because the CRC is loaded into the

Transmit Shift Register even if the transmit interrupt, due

to the last data byte, is not yet reset. Therefore, the end of

a synchronous frame is guaranteed to generate two

transmit interrupts even if a Reset Tx Int Pending

command for the data created interrupt is issued after

(Time “A” in Figure 2-16) the CRC interrupt had occurred.

In this case, two reset Tx Int Pending commands are

required. The TxIP is latched if the EOM latch has been

reset before the end of the frame.

In synchronous modes, one other condition can cause the

TxIP to be set. This occurs at the end of a transmission af-

ter the CRC is sent. When the last bit of the CRC has

04

TxFIFO

03

04

03

02

01

Tx Shift Register

02

Transmit Interrupt

TxIP=1

No Transmit Interrupt

TxIP=0

No Transmit Interrupt

TxIP=0

Figure 2-16. Transmit Interrupt Status When WR7' D5=1 For ESCC

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04

03

02

01

2

04

03

02

TxFIFO

04

03

Opening Flag

TBE=0

02

Tx Shift Register

01

TBE=1

Figure 2-17. Transmit Buffer Empty Bit Status For ESCC For Both WR7' and WR7' D5=0

04

03

02

03

02

01

TxFIFO

Opening Flag

Tx Shift Register

01

No Transmit Interrupt

TxIP = 0

Transmit Interrupt

TxIP = 1

Figure 2-18. Transmit Interrupt Status When WR7' D5=0 For ESCC

.

Data

CRC1

CRC2

Flag

TXBE

Time "A"

TXIP Bit

TXIP 1

TXIP 2

Figure 2-19. TxIP Latching on the ESCC

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2.4 INTERFACE PROGRAMMING (Continued)

2.4.8.3 Transmit Interrupt and Tx Underrun/EOM bit in

synchronous modes

data. That means after the reception of the Underrun/EOM

(End Of Message) interrupt, it accepts the data for the next

packet without collapsing the packet. On the ESCC, if data

was written during the time period described above, the

TBE bit (bit D2 of RR0) will not be set even if the second

TxIP is guaranteed to set when the flag/sync pattern was

loaded into the Transmit Shift Register, as mentioned

above (Figures 2-17 and 18). Hence, on the ESCC, there

is no need to wait for the second TxIP bit to set before

writing data for the next packet and reducing the overhead.

As described in the section above, the behavior of the

NMOS/CMOS version and the ESCC is slightly different,

particularly at the end of packet sending. On the

NMOS/CMOS version, the data has higher priority over

CRC data; writing data before this interrupt would

terminate the packet illegally. In this case, the CRC byte(s)

are replaced with a Flag or Sync pattern, followed by the

data written. On the ESCC, the CRC has priority over the

Last Data -1

Last Data

CRC1

CRC2

Flag

Can not write data

TBE (RR0, D2)

Tx Underrun /EOM

Indicating CRC get loaded

Reset Tx Underrun/EOM command

If TxIP Reset Command

NOT Issued

TxIP

TxIP Reset Command

to Clear Interrupt

Indicating 1st byte of next packet

can be written this time

Figure 2-20. Operation of TBE,Tx Underrun/EOM and TxIP on NMOS/CMOS.

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Last Data -1

Last Data

CRC1

CRC2

Flag

2

TBE

Set if Tx FIFO is Empty

When Auto EOM Reset has enabled

Tx Underrun /EOM

Indicating CRC get loaded

Reset Tx Underrun/EOM Latch Command

If TxIP Reset Command

NOT Issued

TxIP

Data can be written to Tx FIFO after this point

TxIP Reset Command

to Clear Tx Interrupt

Figure 2-21. Operation of TBE,Tx Underrun/EOM and TxIP on ESCC

An example flowchart for processing an end of packet is

shown in Figure 2-22. The chart includes the differences in

processing between the ESCC and NMOS/CMOS version.

In this chart, Tx IP and Underrun/EOM INT can be

processed by interrupts or by polling the registers. Note

that this flowchart does not have the procedures for

interrupt handling, such as saving/restoring of registers to

be used in the ISR (Interrupt Service Routine), Reset IUS

command, or return from interrupt sequence.

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2.4 INTERFACE PROGRAMMING (Continued)

START

Write Last Data

No

TxIP=1 ?

(TBE=1)

Yes

Issue

Reset Tx IP command

No

Underrun/EOM

INT?

Yes

Issue Ext/Stat Int cmd

(to clear Ext/stat INT)

ESCC

NMOS/CMOS

ESCC or

NMOS/CMOS

No

TxIP=1 ?

(TBE=1)

Write data for next

packet (max. 4 Bytes)

Yes

Write 1st byte of

Next Packet (1 byte)

End

Figure 2-22. Flowchart example of processing an end of packet

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The External/Status IP is set by the closing of the latches

and remains set as long as they are closed. In order to de-

termine which condition(s) require service when an exter-

nal/status interrupt is received, the processor should keep

an image of RR0 in memory and update this image each

time it executes the external/status service routine.

2.4.9 External/Status Interrupts

Each channel has six external/status interrupt conditions:

BRG Zero Count, Data Carrier Detect, Sync/Hunt, Clear to

Send, Tx Underrun/EOM, and Break/Abort. The master

enable for external/status interrupts is D0 of WR1, and the

individual enable bits are in WR15. Individual enable bits

control whether or not a latch is present in the path from

the source of the interrupt to the corresponding status bit

in RR0. If the individual enable is set to 0, then RR0 re-

flects the current unlatched status, and if the individual en-

able is set to 1, then RR0 reflects the latched status.

2

Thus, a read of RR0 returns the current status for any bits

whose individual enable is 0, and either the current state

or the latched state of the remainder of the bits. To

guarantee the current status, the processor should issue a

Reset External/Status interrupts command in WR0 to open

the latches. The External/Status IP is set by the closing of

the latches and remains set as long as they are closed. If

the master enable for the External/Status interrupts is not

set, the IP is never set, even though the latches may be

present in the signal paths and working as described.

The latches for the external/status interrupts are not inde-

pendent. Rather, they all close at the same time as a result

of a state change in one of the sources of enabled exter-

nal/status interrupts. This is shown schematically in

Figure 2-23.

Change

To IP

Detecto

External/St

Condition

with

Latch

IE = 1

To RR0

External/St

Condition

with

IE = 0

Figure 2-23. RR0 External/Status Interrupt Operation

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2.4 INTERFACE PROGRAMMING (Continued)

Because the latches close on the current status, but give

no indication of change, the processor must maintain a

copy of RR0 in memory. When the SCC generates an Ex-

ternal/Status Interrupt, the processor should read RR0 and

determine which condition changed state and take appro-

priate action. The copy of RR0 in memory is then updated

and the Reset External/Status Interrupt command issued.

Care must be taken in writing the interrupt service routine

for the External/Status interrupts because it is possible for

more than one status condition to change state at the

same time. All of the latch bits in RR0 should be compared

to the copy of RR0 in memory. If none have changed and

the ZC interrupt is enabled, the Zero Count condition

caused the interrupt.

Interrupts may be generated as a result. The Break/Abort bit

is unique in that both transitions are guaranteed to cause

the latches to close, even if another External/Status inter-

rupt is pending at the time these transitions occur. This

guarantees that a break or abort will be caught. This bit is

undetermined after reset.

2.4.9.2 Transmit Underrun/EOM

The Transmit Underrun/EOM bit is used in synchronous

modes to control the transmission of the CRC. This bit is

reset by issuing the Reset Transmit Underrun/EOM com-

mand in WR0. However, this transition does not cause the

latches to close; this occurs only when the bit is set. To in-

form the processor of this fact, the SCC sets this bit when

the CRC is loaded into the Transmit Shift Register. This bit

is also set if the processor issues the Send Abort com-

mand in WR0. This bit is always set in Asynchronous

mode.

On the ESCC, the contents of RR0 are latched while read-

ing this register. The ESCC prevents the contents of RR0

from changing while the read cycle is active. On the

NMOS/CMOS version, it is possible for the status of RR0

to change while a read is in progress, so it is necessary to

read RR0 twice to detect changes that otherwise may be

missed. The contents of RR0 are latched on the falling

edge of /RD and are updated after the rising edge of /RD.

ESCC:

The ESCC has been modified so that in SDLC mode

this interrupt indicates when more data can be written

to the Transmit FIFO. When this interrupt is used in

this way, the Automatic SDLC Flag Transmission fea-

ture must be enabled (WR7' D0=1). On the ESCC, the

Transmit Underrun/EOM interrupt can be used to sig-

nal when data for a subsequent frame can be written

to the Transmit FIFO which more easily supports the

transmission of back to back frames.

The operation of the individual enable bits in WR15 for

each of the six sources of External/Status interrupts is

identical, but subtle differences exist in the operation of

each source of interrupt. The six sources are Break/Abort,

Underrun/EOM, CTS, DCD, Sync/Hunt and Zero Count.

The Break/Abort, Underrun/EOM, and Zero Count condi-

tions are internal to the SCC, while Sync/Hunt may be in-

ternal or external, and CTS and DCD are purely external

signals. In the following discussions, each source is as-

sumed to be enabled so that the latches are present and

the External/Status interrupts are enabled as a whole. Re-

call that the External/Status IP is set while the latches are

closed and that the state of the signal is reflected immedi-

ately in RR0 if the latches are not present.

2.4.9.3 CTS/DCD

The CTS bit reports the state of the /CTS input, and the

DCD bit reports the status of the /DCD input. Both bits

latch on either input transition. In both cases, after the Re-

set External/Status Interrupt command is issued, if the

latches are closed, they remain closed if there is any odd

number of transitions on an input; they open if there is an

even number of transitions on the input.

2.4.9.4 Zero Count

2.4.9.1 Break/Abort

The Zero Count bit is set when the counter in the baud rate

generator reaches a count of 0 and is reset when the

counter is reloaded. The latches are closed only when this

bit is set to 1. The status in RR0 always reflects the current

status. While the Zero count IE bit in WR15 is reset, this bit

is forced to 0.

The Break/Abort status is used in asynchronous and

SDLC modes, but is always 0 in synchronous modes other

than SDLC. In asynchronous modes, this bit is set when a

break sequence (null character plus framing error) is de-

tected in the receive data stream, and remains set as long

as 0s continue to be received. This bit is reset when a 1 is

received. A single null character is left in the Receive FIFO

each time that the break condition is terminated. This char-

acter should be read and discarded.

2.4.9.5 Sync/Hunt

There are a variety of ways in which the Sync/Hunt may be

set and reset, depending on the SCC’s mode of operation.

In the Asynchronous mode this bit reports the state of the

/SYNC pin, latching on both input transitions. The same is

true of External Sync mode. However, if the crystal oscilla-

tor is enabled while in Asynchronous mode, this bit will be

forced to 0 and the latches will not be closed. Selecting the

In SDLC mode, this bit is set by the detection of an abort se-

quence which is seven or more contiguous 1s in the receive

data stream. The bit is reset when a 0 is received. A re-

ceived abort forces the receiver into Hunt, which is also an

external/status condition. Though these two bits change

state at roughly the same time, one or two External/Status

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crystal option in External Sync mode is illegal, but the re-

sult will be the same.

SDLC mode, the receiver automatically synchronizes on

Flag characters. The receiver is in Hunt mode when it is en-

abled, so the Enter Hunt command is never needed.

In Synchronous modes other than SDLC, the Sync/Hunt

reports the Hunt state of the receiver. Hunt mode is en-

tered when the processor issues the Enter Hunt command

in WR3. This forces the receiver to search for a sync char-

acter match in the receive data stream. Because both tran-

sitions of the Hunt bit close the latches, issuing this com-

mand will cause an External/Status interrupt. The SCC

resets this bit when character synchronization has been

achieved, causing the latches to again be closed.

2

2.4.9.6 External/Status Interrupt Handling

If careful attention is paid to details, the interrupt service

routine for External/Status interrupts is straightforward. To

determine which bit or bits changed state, the routine

should first read RR0 and compare it to a copy from mem-

ory. For each changed bit, the appropriate action should

be taken and the copy in memory updated. The service

routine should close with two Reset External/Status inter-

rupt commands to reopen the latches. The copy of RR0 in

memory should always have the Zero Count bit set to 0,

since this is the state of the bit after the Reset Exter-

nal/Status interrupts command at the end of the service

routine. When the processor issues the Reset Transmit

Underrun/EOM latch command in WR0, the Transmit Un-

derrun/EOM bit in the copy of RR0 in memory should be

reset because this transition does not cause an interrupt.

In these synchronous modes, the SCC will not re-enter the

Hunt mode automatically; only the Enter Hunt command will

set this bit. In SDLC mode this bit is also set by the Enter

Hunt command, but the receiver automatically enters the

Hunt mode if an Abort sequence is received. The receiver

leaves Hunt upon receipt of a flag sequence. Both transi-

tions of the Hunt bit will cause the latches to be closed. In

2.5 BLOCK/DMA TRANSFER

The SCC provides a Block Transfer mode to accommo-

date CPU block transfer functions and DMA controllers.

The Block Transfer mode uses the /W//REQ output in con-

junction with the Wait/Request bits in Write Register 1. The

/W//REQ output can be defined by software as a /WAIT

line in the CPU Block Transfer mode or as a /REQ line in

the DMA Block Transfer mode. The /DTR//REQ pin can

also be programmed through WR14 bit D2 to function as a

DMA request for the transmitter.

has two pins which are used to control the block transfer of

data. Both pins in each channel may be programmed to act

as DMA Request signals. The /W//REQ pin in each chan-

nel may be programmed to act as a Wait signal for the

CPU. In either mode, it is advisable to select and enable

the mode in two separate accesses of the appropriate reg-

ister. The first access should select the mode and the sec-

ond access should enable the function. This procedure

prevents glitches on the output pins. Reset forces Wait

mode, with /W//REQ open-drain.

To a DMA controller, the SCC's /REQ outputs indicate that

the SCC is ready to transfer data to or from memory. To

the CPU, the /WAIT output indicates that the SCC is not

ready to transfer data, thereby requesting the CPU to ex-

tend the I/O cycle.

2.5.1.1 Wait On Transmit

The Wait On Transmit function is selected by setting both

D6 and D5 to 0 and then enabling the function by setting

D7 of WR1 to 1. In this mode the /W//REQ pin carries the

/WAIT signal, and is open-drain when inactive and Low

when active. When the processor attempts to write to the

transmit buffer when it is full, the SCC asserts /WAIT until

the byte is written (Figure 2-24).

2.5.1 Block Transfers

The SCC offers several alternatives for the block transfer

of data. The various options are selected by WR1 (bits D7

through D5) and WR14 (bit D2). Each channel in the SCC

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2.5 BLOCK/DMA TRANSFER (Continued)

/DS or /WR

to Tx Buffer

Empty

Tx Buffer Empty

Full

/W//REQ

(=WAIT)

Figure 2-24. Wait On Transmit Timing

This allows the use of a block move instruction to transfer

the transmit data. In the case of the Z80X30, /WAIT will go

active in response to /DS going active, but only if WR8 is

being accessed and a write is attempted. In all other cas-

es, /WAIT remains open-drain. In the case of the Z85X30,

/WAIT goes active in response to /WR going active, but

only if the data buffer is being accessed, either directly or

via the pointers. The /WAIT pin is released in response to

the falling edge of PCLK. Details of the timing are shown

in Figure 2-25.

Care must be taken when using this function, particularly

at slow transmission speed. The /WAIT pin stays active as

long as the transmit buffer stays full, so there is a possibil-

ity that the CPU may be kept waiting for a long period.

/TRxC

PCLK

/WAIT

SYNC Modes

ASYNC Modes

Figure 2-25. Wait On Transmit Timing

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2.5.1.2 Wait On Receive

and Low when active. When the processor attempts to

read data from the Receive FIFO when it is empty, the

SCC asserts /WAIT until a character has reached the exit

location of the FIFO (Figure 2-26).

The Wait On Receive function is selected by setting D6 or

WR1 to 0, D5 of WR1 to 1, and then enabling the function

by setting D7 of WR1 to 1. In this mode, the /W//REQ pin

carries the /WAIT signal, and is open-drain when inactive

2

/DS or /RD

(from Rx FIFO)

Character Available

Rx Character

Available

FIFO Empty

/W//REQ

(=WAIT)

Figure 2-26. Wait On Receive Timing

This allows the use of a block move instruction to trans-

fer the receive data. In the case of the Z80X30, /WAIT

goes active in response to /DS going active, but only if

RR8 is being accessed and a read is attempted. In all

other cases, /WAIT remains open-drain. In the case of

the Z85X30, /WAIT goes active in response to /RD go-

ing active, but only if the receive data FIFO is being ac-

cessed, either directly or via the pointers. The /WAIT pin

is released in response to the falling edge of PCLK. De-

tails of the timing are shown in Figure 2-27.

Care must be taken when this mode is used. The /WAIT

pin stays active as long as the Receive FIFO remains emp-

ty. When the CPU access the SCC, the CPU remains in

the wait state until data gets into the Receive FIFO, freez-

ing the system.

/RTxC

5•••8

1

2

3

4

9

10

11

12

13

PCLK

/WAIT

SYNC Modes

ASYNC Modes

Figure 2-27. Wait On Receive Timing

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2.5 BLOCK/DMA TRANSFER (Continued)

2.5.2.2 DMA Request On Transmit (using /W//REQ)

The Request On Transmit function is selected by setting

D6 of WR1 to 1, D5 of WR1 to 0, and then enabling the

function by setting D7 of WR1 to 1. In this mode, the

/W//REQ pin carries the /REQ signal, which is active Low.

When this mode is selected but not yet enabled, the

/W//REQ is driven High.

2.5.2 DMA Requests

The two DMA request pins /W//REQ and /DTR//REQ can

be programmed for DMA requests. The /W//REQ pin is

used as either a transmit or a receive request, and the

/DTR//REQ pin can be used as a transmit request only. For

full-duplex operation, the /W//REQ is used for receive, and

the /DTR//REQ is used for transmit. These modes are de-

scribed below.

The /REQ pin generates a falling edge for each byte writ-

ten to the transmit buffer when the DMA controller is to

write new data. For the Z80X30, the /REQ pin then goes

inactive on the falling edge of the DS that writes the new

data (see AC spec #26, TdDSf(REQ)) For the Z85X30, the

/REQ pin then goes inactive on the falling edge of the WR

strobe that writes the new data (see AC spec #33, Td-

WRf(REQ)) This is shown in Figure 2-28.

2.5.2.1 DMA Request on ESCC

Transmit DMA request is also affected by WR7' bit D5. As

noted earlier, WR7' D5 affects both the transmit interrupt

and DMA request generation similarly.

Note: WR7' D3 is ignored by the Receive Request

function. This allows a DMA to transfer all bytes out of the

Receive FIFO and still maintain the full advantage of the

FIFO when the DMA has a long latency response

acquiring the data bus.

Note: The /REQ pin follows the state of the transmit buffer

even though the transmitter is disabled. Thus, if the /REQ

is enabled, the DMA writes data to the SCC before the

transmitter is enabled. This will not cause a problem in

Asynchronous mode, but it may cause problems in

Synchronous mode because the SCC sends data in

preference to flags or sync characters. It may also

complicate the CRC initialization, which cannot be done

until after the transmitter is enabled.

Bit D5 of WR7' is set to 1 after reset to maintain maximum

compatibility with SCC designs. This is necessary because

if WR7' D5=0 when the request function is enabled, re-

quests are made in rapid succession to fill the FIFO. Conse-

quently, some designs which require an edge to be detected

for each data transfer may not recover fast enough to detect

the edges. This is handled by programming WR7' D5=1, or

changing the DMA to be level sensitive instead of edge sen-

sitive. Programming WR7' D5=0 has the advantage of the

DMA requesting to keep the FIFO full. Therefore, if the CPU

is busy, a significantly longer latency can be tolerated with-

out the transmitter under-running.

On the ESCC, this complication can be avoided in SDLC

mode by using the Automatic SDLC Opening Flag Trans-

mission feature and the Auto EOM reset feature, which

also resets the transmit CRC (see Section 4.4.1 for de-

tails). Applications using other synchronous modes should

enable the transmitter before enabling the /REQ function.

/TRxC

PCLK

/REQ

(/DTR//REQ)

/REQ

(/W//REQ)

ASYNC Modes

SYNC Modes

Figure 2-28. Transmit Request Assertion

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With only one exception, the /REQ pin directly follows the

state of the transmit buffer (for the ESCC as programmed

by WR7' D5) in this mode. The SCC generates only one

falling edge on /REQ per character requested and the tim-

ing for this is shown in Figure 2-29.

PCLK cycle. The DMA uses this falling edge on /REQ to

write the first character of the next frame to the SCC. In the

case of the Z80X30, /REQ goes High in response to the

falling edge of DS, but only if the appropriate channel

transmit buffer in the SCC is accessed. This is shown in

Figure 2-25. In the case of the Z85X30, /REQ goes High in

response to the falling edge of /WR, but only when the ap-

propriate channel transmit buffer in the SCC is accessed.

This is shown in Figure 2-30.

2

The one exception occurs in synchronous modes at the

end of a CRC transmission. At the end of a CRC transmis-

sion, when the closing flag or sync character is loaded into

the Transmit Shift Register, /REQ is pulsed High for one

/AS

AD7-AD0

/DS

WR8

Transmit Data

PCLK

/REQ

(/DTR//REQ)

/REQ

(/W//REQ)

Figure 2-29. Z80X30 Transmit Request Release

/WR

D7-D0

Transmit Data

PCLK

/REQ

(/DTR//REQ)

/REQ

(/W//REQ)

Figure 2-30. Z85X30 Transmit Request Release

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2.5 BLOCK/DMA TRANSFER (Continued)

2.5.2.3 DMA Request On Transmit (using /DTR//REQ)

A second Request on Transmit function is available on the

/DTR//REQ pin. This mode is selected by setting D2 of

WR14 to 1. /REQ goes Low when the Transmit FIFO is

empty if WR7' D5=1, or when the exit location of the Trans-

mit FIFO is empty if WR7' D5=0. In the Request mode,

/REQ follows the state of the Transmit FIFO even though

the transmitter is disabled. While D2 of WR14 is set to 0,

the /DTR//REQ pin is /DTR and follows the inverted state

of D7 in WR5. This pin is High after a channel or hardware

reset and in the DTR mode.

The /DTR//REQ pin goes inactive High between each

transfer for a minimum of one PCLK cycle (Figure 2-31).

/DS or /WR

D7-D0

/DTR//REQ

/WAIT//REQ

Transmit Data

ESCC WR7' D4 =1

ESCC WR7' D4 =0, or CMOS/NMOS version

Figure 2-31. /DTR//REQ Deassertion Timing

ESCC:

spec #35b TdWRr(REQ) and Z80230 AC spec #27b

TdDSr(REQ). This feature is beneficial to applications

needing the DMA request to be deasserted quickly. It

prevents a full Transmit FIFO from being overwritten

due to the assertion of REQUEST being too long and

being recognized as a request for more data.

The timing of deactivation of this pin is programmable

through WR7' bit D4. The /DTR//REQ waits until the

write operation has been completed before going in-

active. Refer to Z85230 AC spec #35a TdWRr(REQ)

and Z80230 AC spec #27a TdDSr(REQ). This mode is

compatible with the SCC and guarantees that any sub-

sequent access to the ESCC does not violate the valid

access recovery time requirement.

Note: If WR7' D4=1, analysis should be done to verify

that the ESCC is not repeatedly accessed in less than

four PCLKs. However, since many DMAs require four

clock cycles to transfer data, this typically is not a

problem.

If WR7' D4=1, the /DTR//REQ is deactivated with iden-

tical timing as the /W/REQ pin. Refer to Z85230 AC

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In the Request mode, /REQ will follow the state of the

transmit buffer even though the transmitter is disabled.

Thus, if /REQ is enabled before the transmitter is enabled,

the DMA may write data to the SCC before the transmitter

is enabled. This does not cause a problem in Asynchro-

nous mode, but may cause problems in Synchronous

modes because the SCC sends data in preference to flags

or sync characters. It may also complicate the CRC initial-

ization, which cannot be done until after the transmitter is

enabled. On the ESCC, this complication can be avoided

in SDLC mode by using the Automatic SDLC Opening Flag

Transmission feature and Auto EOM reset feature which

also resets the transmit CRC. (See section 4.4.1.2 for de-

tails). Applications using other synchronous modes should

enable the transmitter before enabling the /REQ function.

the /REQ signal, which is active Low. When REQ on Re-

ceive is selected, but not yet enabled (WR1 D7=0), the

/W//REQ pin is driven High. When the enable bit is set,

/REQ goes Low if the Receive FIFO contains a character

at the time, or will remain High until a character enters the

Receive FIFO. Note that the /REQ pin follows the state of

the Receive FIFO even though the receiver is disabled.

Thus, if the receiver is disabled and /REQ is still enabled,

the DMA transfers the previously received data correctly.

In this mode, the /REQ pin directly follows the state of the

Receive FIFO with only one exception. /REQ goes Low

when a character enters the Receive FIFO and remains

Low until this character is removed from the Receive FIFO.

2

The SCC generates only one falling edge on /REQ per

character transfer requested (Figure 2-32). The one ex-

ception occurs in the case of a special receive condition in

the Receive Interrupt on First Character or Special Condi-

tion mode, or the Receive Interrupt on Special Condition

Only mode. In these two interrupt modes, any receive

character with a special receive condition is locked at the

top of the FIFO until an Error Reset command is issued.

This character in the Receive FIFO would ordinarily cause

additional DMA Requests after the first time it is read.

However, the logic in the SCC guarantees only one falling

edge on /REQ by holding /REQ High from the time the

character with the special receive condition is read, and

the FIFO locked, until after the Error Reset command has

been issued.

With only one exception, the /REQ pin directly follows the

state of the Transmit FIFO (for ESCC, as programmed by

WR7' D5) in this mode. The one exception occurs in syn-

chronous modes at the end of a CRC transmission. At the

end of a CRC transmission, when the closing flag or sync

character is loaded into the Transmit Shift Register, /REQ

is pulsed High for one PCLK cycle. The DMA uses this fall-

ing edge on /REQ to write the first character of the next

frame to the SCC.

2.5.2.4 DMA Request On Receive

The Request On Receive function is selected by setting D6

and D5 of WR1 to 1 and then enabling the function by set-

ting D7 of WR1 to 1. In this mode, the /W//REQ pin carries

Character Available

FIFO

Empty

Rx Character

Available

Read Strobe

to FIFO

W/REQ

(=REQ)

Figure 2-32. DMA Receive Request Assertion

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2.5 BLOCK/DMA TRANSFER (Continued)

Once the FIFO is locked, it allows the checking of the Re-

ceive Error FIFO (RR1) to find the cause of the error. Lock-

ing the data FIFO, therefore, stops the error status from

popping out of the Receive Error FIFO. Also, since the

DMA request becomes inactive, the interrupt (Special

Condition) is serviced.

Once the FIFO is unlocked by the Error Reset command,

/REQ again follows the state of the receive buffer.

In the case of the Z80X30, /REQ goes High in response to

the falling edge of /DS, but only if the appropriate receive

buffer in the SCC is accessed (Figure 2-33). In the case of

the Z85X30, /REQ goes High in response to the falling

edge of /RD, but only when the appropriate receive buffer

in the SCC is accessed (Figure 2-34).

/AS

AD7-AD0

/DS

WR8

Receive Data

PCLK

/REQ

Figure 2-33. Z80X30 Receive Request Release

/RD

D7- D0

Receive Data

PCLK

/REQ

Figure 2-34. Z85X30 Receive Request Release

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2.6 TEST FUNCTIONS

The SCC contains two other features useful for diagnostic

purposes, controlled by bits in WR14. They are Local

Loopback and Auto Echo.

2.6.2 Auto Echo

2

Auto Echo is selected when bit D3 of WR14 is set to 1. In

this mode, the TxD pin is connected directly to the RxD pin,

and the receiver input is connected to the RxD pin. In this

mode, the /CTS pin is ignored as a transmitter enable and

the output of the transmitter does not connect to anything.

If both the Local Loopback and Auto Echo bits are set to 1,

the Auto Echo mode is selected, but both the /CTS pin and

/DCD pin are ignored as auto enables. This should not be

considered a normal operating mode (Figure 2-36).

2.6.1 Local Loopback

Local Loopback is selected when WR14 bit D4 is set to 1.

In this mode, the output of the transmitter is internally con-

nected to the input of the receiver. At the same time, the

TxD pin remains connected to the transmitter. In this

mode, the /DCD pin is ignored as a receive enable and the

/CTS pin is ignored as a transmitter enable even if the Auto

Enable mode has been selected. Note that the DPLL input

is connected to the RxD pin, not to the input of the receiver.

This precludes the use of the DPLL in Local Loopback. Lo-

cal Loopback is shown schematically in Figure 2-35.

/DCD

Rx Enable

Receiver

RxD

TxD

/DCD

Rx Enable

Transmitter

NC

RxD

TxD

NC

Receiver

Tx Enable

/CTS

Transmitter

Auto Echo

Tx Enable

/CTS

Figure 2-36. Auto Echo

Local Loop Back

Figure 2-35. Local Loopback

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3

CHAPTER 3

SCC/ESCC ANCILLARY

SUPPORT CIRCUITRY

3.1 INTRODUCTION

The serial channels of the SCC are supported by ancillary

circuitry for generating clocks and performing data encod-

ing and decoding. This chapter presents a description of

these functional blocks.

Note to SCC Users: The ancillary circuitry in the ESCC is

the same as in the SCC with the following noted changes.

The DPLL (Dual Phased-Locked Loop) output, when used

as the transmit clock source, has been changed to be free

of jitter. Consequently, this only affects the use of the DPLL

as the transmit clock source (it is typically used for the re-

ceive clock source), this has no effect on using the DPLL

as the receive clock source.

Note to ESCC/CMOS Users: The maximum input fre-

quency to the DPLL has been specified as two times the

PCLK frequency (Spec #16b TxRX(DPLL)). There are no

changes to the baud rate generators from the NMOS to the

CMOS/ESCC.

3.2 BAUD RATE GENERATOR

The Baud Rate Generator (BRG) is essential for

asynchronous communications. Each channel in the SCC

contains a programmable baud rate generator. Each

generator consists of two 8-bit, time-constant registers

forming a16-bit time constant, a 16-bit down counter, and

a flip-flop on the output so that it outputs a square wave.

On start-up, the flip-flop on the output is set High, so that it

starts in a known state, the value in the time-constant

register is loaded into the counter, and the counter begins

counting down. When a count of zero is reached, the

output of the baud rate generator toggles, the value in the

time-constant register is loaded into the counter, and the

process starts over. The programmed time constant is

read from RR12 and RR13. A block diagram of the baud

rate generator is shown in Figure 3-1.

WR12

WR 13

Zero

Count

(Gives one Transition

Each Time the Counter

Counts to Zero)

16-Bit Counter

(May Provide

Higher Resolution

to Sample Data)

Output

÷2

Baud Rate

Generator

/RTxC Pin

PCLK Pin

Clock

÷Clock

Mode

Desired Baud

(Asynchronous Mode)

(Takes One More

Clock to Load

Time Constant

Value to

Counter

Figure 3-1. Baud Rate Generator

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3.2 BAUD RATE GENERATOR (Continued)

The time-constant can be changed at any time, but the

new value does not take effect until the next load of the

counter (i.e., after zero count is reached).

The clock source for the baud rate generator is selected by

bit D1 of WR14. When this bit is set to 0, the BRG uses the

signal on the /RTxC pin as its clock, independent of wheth-

er the /RTxC pin is a simple input or part of the crystal os-

cillator circuit. When this bit is set to 1, the BRG is clocked

by the PCLK. To avoid metastable problems in the

counter, this bit should be changed only while the baud

rate generator is disabled, since arbitrarily narrow pulses

can be generated at the output of the multiplexer when it

changes status.

No attempt is made to synchronize the loading of a new

time-constant with the clock used to drive the generator.

When the time-constant is to be changed, the generator

should be stopped first by writing WR14 D0=0. After loading

the new time constant, the BRG can be started again. This

ensures the loading of a correct time constant, but loading

does not take place until zero count or a reset occurs.

The BRG is enabled while bit D0 of WR14 is set to 1. It is

disabled while WR14 D0=0 and after a hardware reset (but

not a software reset). To prevent metastable problems

when the baud rate generator is first enabled, the enable

bit is synchronized to the baud rate generator clock. This

introduces an additional delay when the baud rate

generator is first enabled (Figure 3-2). The baud rate

generator is disabled immediately when bit D0 of WR14 is

set to 0, because the delay is only necessary on start-up.

The baud rate generator is enabled and disabled on the fly,

but this delay on start-up must be taken into consideration.

If neither the transmit clock nor the receive clock are pro-

grammed to come from the /TRxC pin, the output of the

baud rate generator may be made available for external

use on the /TRxC pin.

Note: This feature is very useful for diagnostic purposes.

By programming the output of the baud rate generator as

output on the /TRxC pin, the BRG is source and time test-

ed, and the programmed time constant verified.

Figure 3-2. Baud Rate Generator Start Up

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The formulas relating the baud rate to the time-constant

and vice versa are shown below.

Table 3-1. Baud Rates for 2.4576 MHz Clock and 16x

Clock Factor

Time Constant

Baud

3

Rate

Decimal

Hex

Clock Frequency

- 2

Time Constant =

Baud Rate =

38400

19200

9600

4800

2400

1200

600

0

2

6

14

30

62

126

254

510

0000

0002

0006

000E

001E

003E

007E

00FE

01FE

2 x (Clock Mode) x (Baud Rate)

Clock Frequency

2 x (Clock Mode) x (Time Constant+ 2)

In these formulas, the BRG clock frequency (PCLK or

/RTxC) is in Hertz, the desired baud rate in bits/sec, Clock

Mode is 1 in sync modes, 1, 16, 32 or 64 in async mode

and the time constant is dimensionless. The example in

Table 3-1 assumes a 2.4576 MHz clock (from /RTxC) fac-

tor of 16 and shows the time constant for a number of pop-

ular baud rates.

300

150

Other commonly used clock frequencies include 3.6846,

4.6080, 4.91520, 6.144, 7.3728, 9.216, 9.8304, 12.288,

14.7456, 19.6608 (units in MHz).

Initializing the BRG is done in three steps. First, the time-

constant is determined and loaded into WR12 and WR13.

Next, the processor must select the clock source for the

BRG by setting bit D1 of WR14. Finally, the BRG is en-

abled by setting bit D0 of WR14 to 1.

For example:

6

10

2.4576 x 10

TC =

-2 = 510

(2 x 16) x 150

.

Note: The first write to WR14 is not necessary after a hard-

ware reset if the clock source is the /RTxC pin. This is be-

cause a hardware reset automatically selects the /RTxC

pin as the BRG clock source.

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3.3 DATA ENCODING/DECODING

Data encoding is utilized to allow the transmission of clock

and data information over the same medium. This saves

the need to transmit clock and data over separate medium

as would normally be required for synchronous data. The

SCC provides four different data encoding methods,

selected by bits D6 and D5 in WR10. An example of these

four encoding methods is shown in Figure 3-3. Any

encoding method is used in any X1 mode in the SCC,

asynchronous or synchronous. The data encoding

selected is active even though the transmitter or receiver

is idling or disabled.

DATA

NRZ

1

0

1

0

Bit Cell Level:

High = 1

Low = 0

No Change = 1

Change = 0

NRZI

Bit Center Transition:

Transition = 1

No Transition = 0

FM1

(Biphase Mark)

FM0

(Biphase Space)

No Transition = 1

Transition = 0

High → Low = 1

Low → High = 0

MANCHESTER

Figure 3-3. Data Encoding Methods

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NRZ (Non-Return to Zero). In NRZ, encoding a 1 is rep-

resented by a High level and a 0 is represented by a Low

level. In this encoding method, only a minimal amount of

clocking information is available in the data stream in the

form of transitions on bit-cell boundaries. In an arbitrary

data pattern, this may not be sufficient to generate a clock

for the data from the data itself.

FM1 (Bi-phase Mark). In FM1 encoding, also known as bi-

phase mark, a transition is present on every bit cell bound-

ary, and an additional transition may be present in the mid-

dle of the bit cell. In FM1, a 0 is sent as no transition in the

center of the bit cell and a 1 is sent as a transition in the

center of the bit cell. FM1 encoded data contains sufficient

information to recover a clock from the data.

3

NRZI (Non-Return to Zero Inverted). In NRZI, encoding

a 1 is represented by no change in the level and a 0 is rep-

resented by a change in the level. As in NRZ, only a mini-

mal amount of clocking information is available in the data

stream, in the form of transitions on bit cell boundaries. In

an arbitrary data pattern this may not be sufficient to gen-

erate a clock for the data from the data itself. In the case

of SDLC, where the number of consecutive 1s in the data

stream is limited, a minimum number of transitions to gen-

erate a clock are guaranteed.

FM0 (Bi-phase Space). In FM0 encoding, also known as

bi-phase space, a transition is present on every bit cell

boundary and an additional transition may be present in

the middle of the bit cell. In FM0, a 1 is sent as no transition

in the center of the bit cell and a 0 is sent as a transition in

the center of the bit cell. FM0 encoded data contains suffi-

cient information to recover a clock from the data.

Manchester (Bi-phase Level). Manchester (bi-phase lev-

el) encoding always produces a transition at the center of

the bit cell. If the transition is Low to High, the bit is 0. If the

transition is High to Low, the bit is 1. Encoding of Manches-

ter format requires an external circuit consisting of a ‘D’

flip-flop and four gates (Figure 3-4). The SCC is used to

decode Manchester data by using the DPLL in the FM

mode and programming the receiver for NRZ data (See

Section 3.1.3).

ESCC:

TxD Pin Forced High in SDLC feature. When the ESCC

is programmed for SDLC mode with NRZI data encod-

ing and mark idle (WR10 D6=0, D5=1, D3=1), the TxD

pin is automatically forced high when the transmitter

goes to the mark idle state. There are several different

ways for the transmitter to go into the idle state. In

each of the following cases the TxD pin is forced high

when the mark idle condition is reached: data, CRC,

flag and idle; data, flag and idle; data, abort (on under-

run) and idle; data, abort (command) and idle; idle flag

and command to idle mark. The Force High feature is

disabled when the mark idle bit is reset. The TxD pin is

forced High on the falling edge of the TxC cycle after

the falling edge of the last bit of the closing flag. Using

SDLC Loop mode is independent of this feature.

Data Encoding Initialization. The data encoding method is

selected in the initialization procedure before the transmitter

and receiver are enabled, but no other restrictions apply.

Note that in NRZ and NRZI, the receiver samples the data

only on one edge, as shown in Figure 3-3. However, in FM1

and FM0, the receiver samples the data on both edges.

Also, as shown in Figure 3-3, the transmitter defines bit cell

boundaries by one edge in all cases and uses the other

edge in FM1 and FM0 to create the mid-bit transition.

This feature is used in combination with the automatic

SDLC opening flag transmission feature, WR7' D0=1,

to assure that data packets are properly formatted.

Therefore, when these features are used together, it is

not necessary for the CPU to issue any commands

when using the force idle mode in combination with

NRZI data encoding. If WR7' D0 is reset, like the SCC,

it is necessary to reset the mark idle bit (WR10 D2) to

enable flag transmission before an SDLC packet is

transmitted.

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3.3 DATA ENCODING/DECODING (Continued)

NRZ

3

4

5

Manchester

1

a

b

2

Transmit Clock

Transmit

Clock

NRZ

1

2

3

4

5

Figure 3-4. Manchester Encoding Circuit

3-6

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3.4 DPLL DIGITAL PHASE-LOCKED LOOP

Each channel of the SCC contains a digital phase-locked

loop that can be used to recover clock information from a

data stream with NRZI, FM, NRZ, or Manchester encod-

ing. The DPLL is driven by a clock nominally at 32 (NRZI)

or 16 (FM) times the data rate. The DPLL uses this clock,

along with the data stream, to construct a receive clock for

the data. This clock can then be used as the SCC receive

clock, the transmit clock, or both.

Figure 3-5 shows a block diagram of the digital phase-

locked loop. It consists of a 5-bit counter, an edge detector,

and a pair of output decoders. The clock for the DPLL

comes from the output of a two-input multiplexer, and the

two outputs go to the transmitter and receive clock

multiplexers. The DPLL is controlled by seven commands

encoded in WR14 bits D7, D6 and D5.

3

Receive

Clock

RxD

Edge Detector

Count Modifier

Decode

Transmit

Clock

5-Bit Counter

Figure 3-5. Digital Phase-Locked Loop

The clock source for the DPLL is selected issuing one of

the two commands in WR14, that is:

As in the case of the clock source selection, the mode of

operation is only changed while the DPLL is disabled to

prevent unpredictable results.

WR14 (7-5) = 100 selects the BRG

WR14 (7-5) = 101 selects the /RTxC pin

In the NRZI mode, the DPLL clock must be 32 times the

data rate. In this mode, the transmit and receive clock out-

puts of the DPLL are identical, and the clocks are phased

so that the receiver samples the data in the middle of the

bit cell. In NRZI mode, the DPLL does not require a transi-

tion in every bit cell, so this mode is useful for recovering

the clocking information from NRZ and NRZI data streams.

The first command selects the baud rate generator as the

clock source. The other command selects the /RTxC pin

as the clock source, independent of whether the /RTxC pin

is a simple input or part of the crystal oscillator circuit.

Initialization of the DPLL is done at any time during the ini-

tialization sequence, but should be done after the clock

modes have been selected in WR11, and before the re-

ceiver and transmitter are enabled. When initializing the

DPLL, the clock source should be selected first, followed

by the selection of the operating mode.

In the FM mode, the DPLL clock must be 16 times the data

rate. In this mode, the transmit clock output of the DPLL

lags the receive clock outputs by 90 degrees to make the

transmit and receive bit cell boundaries the same, be-

cause the receiver must sample FM data at one-quarter

and three-quarters bit time.

To avoid metastable problems in the counter, the clock

source selection is made only while DPLL is disabled,

since arbitrarily narrow pulses are generated at the output

of the multiplexer when it changes status.

The DPLL is enabled by issuing the Enter Search Mode

command in WR14; that is WR14 (7-5) = 001. The Enter

Search Mode command unlocks the counter, which is held

while the DPLL is disabled, and enables the edge detector.

If the DPLL is already enabled when this command is is-

sued, the DPLL also enters Search Mode.

The DPLL is programmed to operate in one of two modes,

as selected by commands in WR14.

WR14 (7-5) = 111 selects NRZI mode

WR14 (7-5) = 110 selects FM mode

Note: A channel or hardware reset disables the DPLL, se-

lects the /RTxC pin as the clock source for the DPLL, and

places it in the NRZI mode.

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3.4 DPLL DIGITAL PHASE-LOCKED LOOP (Continued)

If the bit cell boundary (from space to mark) occurs be-

3.4.1 DPLL Operation in the NRZI Mode

tween the middle of count 16 and count 31, the DPLL is

sampling the data too early in the bit cell. In response to

this, the DPLL extends its count by one during the next 0

to 31 counting cycle, which effectively moves the edge of

the clock that samples the receive data closer to the center

of the bit cell.

To operate in NRZI mode, the DPLL must be supplied with

a clock that is 32 times the data rate. The DPLL uses this

clock, along with the receive data, to construct receive and

transmit clock outputs that are phased to properly receive

and transmit data.

To do this, the DPLL divides each bit cell into four regions,

and makes an adjustment to the count cycle of the 5-bit

counter dependent upon the region a transition on the re-

ceive data input occurred (Figure 3-6).

If the transition occurs between count 0 and the middle of

count 15, the output of the DPLL is sampling the data too

late in the bit cell. To correct this, the DPLL shortens its

count by one during the next 0 to 31 counting cycle, which

effectively moves the edge of the clock that samples the

receive data closer to the center of the bit cell.

Ordinarily, a bit-cell boundary occurs between count 15

and count 16, and the DPLL output causes the data to be

sampled in the middle of the bit cell. However, four differ-

ent situations can occur:

If the DPLL does not see any transition during a counting cy-

cle, no adjustment is made in the following counting cycle.

If the bit-cell boundary (from space to mark) occurs any-

where during the second half of count 15 or the first half of

count 16, the DPLL allows the transition without making a

correction to its count cycle.

If an adjustment to the counting cycle is necessary, the

DPLL modifies count 5, either deleting it or doubling it.

Thus, only the Low time of the DPLL output is lengthened

or shortened.

Bit Cell

Count

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Correction

Add One Count

No Change

Subtract One Count

No Change

DPLL Out

Figure 3-6. DPLL in NRZI Mode

While the DPLL is in search mode, the counter remains at

count 16, where the DPLL outputs are both High. The

missing clock latches in the DPLL, which may be accessed

in RR10, are not used in NRZI mode. An example of the

DPLL in operation is shown in Figure 3-7.

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Receive

Data

3

DPLL

Output

Correction

Windows

+1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1

Count

Length

32

31

33

Figure 3-7. DPLL Operating Example (NRZI Mode)

In FM mode, the counter in the DPLL counts from 0 to 31,

but now each cycle corresponds to 2-bit cells. To make

adjustments to remain in phase with the receive data, the

DPLL divides a pair of bit cells into five regions, making the

adjustment to the counter dependent upon which region the

transition on the receive data input occurred (Figure 3-8).

3.4.2 DPLL Operation in the FM Modes

To operate in FM mode, the DPLL must be supplied with a

clock that is 16 times the data rate. The DPLL uses this

clock, along with the receive data, to construct, receive,

and transmit clock outputs that are phased to receive and

transmit data properly.

Bit Cell

Count

Correction

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

+1

Ignored

+1

No Change

RX DPLL Out

TX DPLL Out

Figure 3-8. DPLL Operation in the FM Mode

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3.4 DPLL DIGITAL PHASE-LOCKED LOOP (Continued)

In FM mode, the transmit clock and receive clock outputs

from the DPLL are not in phase. This is necessary to make

the transmit and receive bit cell boundaries coincide, since

the receive clock must sample the data one-fourth and

three-fourths of the way through the bit cell.

While the DPLL is disabled, the transmit clock output of the

DPLL may be toggled by alternately selecting FM and

NRZI mode in the DPLL. The same is true of the receive

clock.

While the DPLL is in the Search mode, the counter re-

mains at count 16 where the receive output is Low and the

transmit output is Low. This fact is used to provide a trans-

mit clock under software control since the DPLL is in the

Search mode while it is disabled.

Ordinarily, a bit cell boundary occurs between count 15 or

count 16, and the DPLL receive output causes the data to

be sampled at one-fourth and three-fourths of the way

through the bit cell.

However, four variations can occur:

As in NRZI mode, if an adjustment to the counting cycle is

necessary, the DPLL modifies count 5, either deleting it or

doubling it. If no adjustment is necessary, the count se-

quence proceeds normally.

If the bit-cell boundary (from space to mark) occurs any-

where during the second half of count 15 or the first half of

count 16, the DPLL allows the transition without making a

correction to its count cycle.

When the DPLL is programmed to enter Search mode,

only clock transitions should exist on the receive data pin.

If this is not the case, the DPLL may attempt to lock on to

the data transitions. If the DPLL does lock on to the data

transitions, then the Missing Clock condition will inevitably

occur because data transitions are not guaranteed every

bit cell.

If the bit-cell boundary (from space to mark) occurs be-

tween the middle of count 16 and the middle of count 19,

the DPLL is sampling the data too early in the bit cell. In

response to this, the DPLL extends its count by one during

the next 0 to 31 counting cycle, which effectively moves

the receive clock edges closer to where they should be.

To lock in the DPLL properly, FM0 encoding requires con-

tinuous 1s received when leaving the Search mode. In

FM1 encoding, continuous 0s are required; with Manches-

ter encoded data this means alternating 1s and 0s. With all

three of these data encoding methods there is always at

least one transition in every bit cell, and in FM mode the

DPLL is designed to expect this transition.

Any transitions occurring between the middle of count 19

in one cycle and the middle of count 12 during the next cy-

cle are ignored by the DPLL. This guarantees that any data

transitions in the bit cells do not cause an adjustment to the

counting cycle.

If no transition occurs between the middle of count 12 and

the middle of count 19, the DPLL is probably not locked

onto the data properly. When the DPLL misses an edge,

the One Clock Missing bit is RR10, it is set to 1 and

latched. It will hold this value until a Reset Missing Clock

command is issued in WR14, or until the DPLL is disabled

or programmed to enter the Search mode. Upon missing

this one edge, the DPLL takes no other action and does

not modify its count during the next counting cycle.

3.4.3 DPLL Operation in the Manchester

Mode

The SCC can be used to decode Manchester data by us-

ing the DPLL in the FM mode and programming the receiv-

er for NRZ data. Manchester encoded data contains a

transition at the center of every bit cell; it is the direction of

this transition that distinguishes a 1 from a 0. Hence, for

Manchester data, the DPLL should be in FM mode (WR14

command D7=1, D6=1, D5=0), but the receiver should be

set up to accept NRZ data (WR10 D6=0, D5=0).

If the DPLL does not see an edge between the middle of

count 12 and the middle of count 19 in two successive 0 to

31 count cycles, a line error condition is assumed. If this

occurs, the Two Clocks Missing bit in RR10 is set to 1 and

latched. At the same time, the DPLL enters the Search

mode. The DPLL makes the decision to enter the Search

mode during count 2, where both the receive clock and

transmit clock outputs are Low. This prevents any glitches

on the clock outputs when the Search mode is entered.

While in the Search mode, no clock outputs are provided

by the DPLL. The Two Clocks Missing bit in RR10 is

latched until a Reset Missing Clock command is issued in

WR14, or until the DPLL is disabled or programmed to en-

ter the Search mode.

3.4.4 Transmit Clock Counter (ESCC only)

The ESCC includes a Transmit Clock Counter which par-

allels the DPLL. This counter provides a jitter-free clock

source to the transmitter by dividing the DPLL clock source

by the appropriate value for the programmed data encod-

ing format as shown in Figure 3-9. Therefore, in FM mode

(FM0 or FM1), the counter output is the input frequency di-

vided by 16. In NRZI mode, the counter frequency is the in-

put divided by 32. The counter output replaces the DPLL

transmit clock output, available as the transmit clock

source. This has no effect on the use of the DPLL as the

receive clock source.

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The output of the transmit clock derived from this counter

is available to the /TRxC pin when the DPLL output is

selected as the transmit clock source. Care must be taken

using ESCC in SDLC Loop mode with the DPLL. The

SDLC Loop mode requires synchronized Tx and Rx

clocks, but the ESCC’s DPLL might be off-sync because of

this Transmit Clock Counter. In SDLC Loop, one should

instead echo the signal of the RxDPLL out to clock the

receiver and transmitter to achieve synchronization. This

can be programmed via bits D1-D0 in WR11.

3

DPLL CLK

DPLL

DPLL Output to Receiver

DPLL Output to Transmitter

Input

DPLL Counter

Input Divided by 16 (FM0 or FM1)

Input Divided by 32 for NRZI

Figure 3-9. DPLL Transmit Clock Counter Output (ESCC only)

3.5 CLOCK SELECTION

The SCC can select several clock sources for internal and

external use. Write Register 11 is the Clock Mode Control

register for both the receive and transmit clocks. It deter-

mines the type of signal on the /SYNC and /RTxC pins and

the direction of the /TRxC pin.

to the multiplexer section, as well as the various signal in-

versions that occur in the paths to the outputs.

Selection of the clocking options may be done anywhere in

the initialization sequence, but the final values must be se-

lected before the receiver, transmitter, baud rate genera-

tor, or DPLL are enabled to prevent problems from arbi-

trarily narrow clock signals out of the multiplexers. The

same is true of the crystal oscillator, in that the output

should be allowed to stabilize before it is used as a clock

source.

The SCC is programmed to select one of several sources

to provide the transmit and receive clocks.

The source of the receive clock is controlled by bits D6 and

D5 of WR11. The receive clock may be programmed to

come from the /RTxC pin, the /TRxC pin, the output of the

baud rate generator, or the receive output of the DPLL.

Also shown are the edges used by the receiver, transmit-

ter, baud rate generator and DPLL to sample or send data

or otherwise change state. For example, the receiver sam-

ples data on the falling edge, but since there is an inver-

sion in the clock path between the /RTxC pin and the re-

ceiver, a rising edge of the /RTxC pin samples the data for

the receiver.

The source of the transmit clock is controlled by bits D4

and D3 of WR11. The transmit clock may be programmed

to come from the /RTxC pin, the /TRxC pin, the output of

the baud rate generator, or the transmit output of the

DPLL.

Ordinarily, the /TRxC pin is an input, but it can become an

output if this pin has not been selected as the source for

the transmitter or the receiver, and bit D2 of WR11 is set

to 1. The selection of the signal provided on the /TRxC out-

put pin is controlled by bits D1 and D0 of WR11. The

/TRxC pin is programmed to provide the output of the crys-

tal oscillator, the output of the baud rate generator, the re-

ceive output of the DPLL or the actual transmit clock. If the

output of the crystal oscillator is selected, but the crystal

oscillator has not been enabled, the /TRxC pin is driven

High. The option of placing the transmit clock signal on the

/TRxC pin when it is an output allows access to the trans-

mit output of the DPLL.

The following shows three examples for selecting different

clocking options. Figure 3-11 shows the clock set up for

asynchronous transmission, 16x clock mode using the on-

chip oscillator with an external crystal. This example uses

the oscillator as the input to the baud rate generator, al-

though it can be used directly as the transmit or receive clock

source. The registers involved are WR11 through WR14 and

the figure shows the programming in these registers.

An example of asynchronous communication where a 1x

clock is obtained from an external MODEM is shown in

Figure 3-12. The data encoding is NRZ. Note that:

1. The BRG is not used under this configuration.

Figure 3-10 shows a simplified schematic diagram of the

circuitry used in the clock multiplexing. It shows the inputs

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3.5 CLOCK SELECTION (Continued)

2. The x1 mode in Asynchronous mode is a combination

of both synchronous and asynchronous transmission.

The data is clocked by a common timing base, but

characters are still framed with Start and Stop bits.

Because the receiver waits for one clock period after

detecting the first High-to-Low transition before

beginning to assemble characters, the data and clock

is synchronized externally. The x1 mode is the only

mode in which a data encoding method other than

NRZ is used.

OSC

RX

/SYNC

Receiver

OSC

/RTxC

TX

/TRxC

Transmitter

Echo

DPLL

BRG

Echo

Baud Rate

Generator Out

Tx DPLL Out

Rx DPLL Out

PCLK

Baud Rate

Generator

Figure 3-10. Clock Multiplexer

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External

Crystal

3

/SYNC Pin

/RTxC Pin

B

R

G

16x

Output

TxC

RxC

/TRxC Pin

SCC

Figure 3-11. Async Clock Setup Using an External Crystal

WR11

D7

WR14

D0

0

D1

0

1

0

1

0

1

/TRxC OUT = BRG Output

/TRxC Pin = Output Pin

Tx Clock = BRG Output

Rx Clock = BRG Output

Using External Crystal

BRG Clock Source = /RTXC

or XTAL OSCILLATOR

NRZ Data

TxC

RxC

SYNC

Modem

RxD Pin

1x

/RTxC Pin

SCC

Figure 3-12. Clock Source Selection

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3.6 CRYSTAL OSCILLATOR (Continued)

Figure 3-13 shows the use of the DPLL to derive a 1x clock

from the data. In this example:

The DPLL clock output = RxC (receiver clock) WR11.

Set FM mode WR14.

The DPLL clock input = BRG output (x16 the data rate)

WR14.

Set FM mode WR10.

External

Crystal

/SYNC Pin

B

R

G

/RTxC Pin

16x Data Rate

D

RxC

P

RxD Pin

L

TxC

RxD

Figure 3-13. Synchronous Transmission, 1x Clock Rate, FM Data Encoding, using DPLL

3.6 CRYSTAL OSCILLATOR

Each channel contains a high gain oscillator amplifier for

Of course, since the oscillator uses the /RTxC and /SYNC

pins, this precludes the use of these pins for other func-

tions. In synchronous modes, no sync pulse is output, and

the External Sync mode cannot be selected. In asynchro-

nous modes, the state of the Sync/Hunt bit in RR0 is no

longer controlled by the /SYNC pin. Instead, the Sync/Hunt

bit is forced to 0.

use with an external crystal circuit. The amplifier is avail-

able between the /RTxC pin (crystal input) and the /SYNC

pin (crystal output) for each channel.

The oscillator amplifier is enabled by writing WR11 D7=1.

While the crystal oscillator is enabled, anything that has

selected the /RTxC pin as its clock source automatically

connects to the output of the crystal oscillator.

The crystal oscillator requires some finite time to stabilize

and must be allowed to stabilize before it is used as a clock

source. This stabilization time is dependent on the external

circuit impedance and 20 ms is a suggested minimum. The

External Crystal should operate in parallel resonance. For

further details on designing with the crystal, refer to Appen-

dix A, “On-Chip Oscillator Design”.

Note: The output of the oscillator amplifier can be pro-

grammed to output on the /TRxC pin, which is particularly

valuable for diagnostic purposes. Because amplifier char-

acteristics can be affected by the impedance of measure-

ment equipment applied directly to the crystal circuit, using

the /TRxC pin allows the oscillation to be tested without af-

fecting the circuit.

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4

CHAPTER 4

DATA COMMUNICATION MODES

4.1 INTRODUCTION

The SCC provides two independent, full-duplex channels

programmable for use in any common asynchronous or

synchronous data communication protocol. The data com-

munication protocols handled by the SCC are:

4.1.1 Transmit Data Path Description

A diagram of the transmit data path is shown in Figure 4-1.

The transmitter has a Transmit Data buffer (a 4-byte deep

FIFO on the ESCC, a one byte deep buffer on the

NMOS/CMOS version) which is addressed through WR8.

It is not necessary to enable the transmit buffer. It is

available in all modes of operation. The Transmit Shift

register is loaded from either WR6, WR7, or the Transmit

Data buffer. In Synchronous modes, WR6 and WR7 are

programmed with the sync characters. In Monosync mode,

an 8-bit or 6-bit sync character is used (WR6), whereas a

16-bit sync character is used in the Bisynchronous mode

(WR6 and WR7). In bit-oriented Synchronous modes, the

SDLC flag character (7E hex) is programmed in WR7 and

is loaded into the Transmit Shift Register at the beginning

and end of each message.

■ Asynchronous mode:

Asynchronous (x16, x32, or x64 clock

Isochronous (x1 clock)

■ Character-Oriented mode:

Monosynchronous

Bisynchronous

External Synchronous

■ Bit-Oriented mode

SDLC/HDLC

SDLC/HDLC Loop

Internal Data Bus

To Other Channel

TX Buffer (1-Byte; NMOS/CMOS)

TX FIFO (4 Byte; ESCC)

WR8

Internal TxD

WR7

WR6

Register SYNC Register

SYNC

Final TX

MUX

TxD

20-Bit TX Shift Register

ASYNC

SYNC

Transmit

MUX & 2-Bit

Delay

Zero

Insert

5-Bit Delay

NRZI

Encode

SDLC

CRC-SDLC

Transmit Clock

CRC-Gen

From Receiver

Figure 4-1. Transmit Data Path

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4.1 INTRODUCTION (Continued)

For asynchronous data, the Transmit Shift register is for-

matted with start and stop bits along with the data; option-

ally with parity information bit. The formatted character is

shifted out to the transmit multiplexer at the selected clock

rate. WR6 & WR7 are not used in Asynchronous mode.

4.1.2 Receive Data Path Description

On the ESCC, the receiver has an 8-byte deep, 8-bit wide

Data FIFO, while the NMOS/CMOS version receiver has a

3-byte deep, 8-bit wide data buffer. In both cases, the Data

buffer is paired with an 8-bit Error FIFO and an 8-bit Shift

Register. The receive data path is shown in Figure 4-2.

This arrangement creates a 8-character buffer, allowing

time for the CPU to service an interrupt or for the DMA to

acquire the bus at the beginning of a block of high-speed

data. It is not necessary to enable the Receive FIFO, since

it is available in all modes of operation. For each data byte

in the Receive FIFO, a byte is loaded into the Error FIFO

to store parity, framing, and other status information. The

Error FIFO is addressed through Read Register 1.

Synchronous data (except SDLC/HDLC) is shifted to the

CRC generator as well as to the transmit multiplexer.

SDLC/HDLC data is shifted to the CRC Generator and out

through the zero insertion logic (which is disabled while the

flags are being sent). A 0 is inserted in all address, control,

information, and frame check fields following five contigu-

ous 1s in the data stream. The result of the CRC generator

for SDLC data is also routed through the zero insertion log-

ic and then to the transmit multiplexer.

CPU I/O

I/O Data buffer

Internal Data Bus

Upper Byte (WR13)

Time Constant

Lower Byte (WR12)

Time Constant

Status FIFO

10 x 19 Frame*

Rec. Data FIFO**

Rec. Error FIFO**

See

Note

See

Note

See

Note

BRG

Input

BRG

Output

16-Bit Down Counter

DIV 2

14-Bit Counter

Rec. Error Logic

Hunt Mode (BISYNC)

DPLL

IN

DPLL

OUT

SYNC Register

& Zero Delete

Receive Shift

Register

DPLL

3-Bit

Internal TXD

CRC Delay

Register (8 bits)

SYNC

CRC

RxD

1-Bit

MUX

NRZI Decode

MUX

CRC

Checker

SDLC-CRC

To Transmit Section

CRC Result

Notes:

* Not with NMOS.

** Rec. Data FIFO and Rec. Error FIFO are 8 Bytes Deep (ESCC), 3 Bytes Deep (NMOS/CMOS).

Figure 4-2. Receive Data Path

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Data Communication Modes

Incoming data is routed through one of several paths de-

pending on the mode and character length. In Asynchro-

nous mode, serial data enters the 3-bit delay if a character

length of seven or eight bits is selected. If a character

length of five or six bits is selected, data enters the receive

shift register directly.

been received and the receiver is synchronized to that flag.

If the seventh bit is a 1, an abort or an EOP (End Of Poll) is

recognized, depending upon the selection of either the nor-

mal SDLC mode or SDLCLoop mode.

4

Note: The insertion and deletion of the zero in the SDLC

data stream is transparent to the user, as it is done after

the data is written to the Transmit FIFO and before data is

read from the Receive FIFO. This feature of the

SDLC/HDLC protocol is to prevent the inadvertent sending

of an ABORT sequence as part of the data stream. It is

also valuable to applications using encoded data to insure

a sufficient number of edges on the line to keep a DPLL

synchronized on a receive data stream.

In Synchronous modes, the data path is determined by the

phase of the receive process currently in operation. A syn-

chronous receive operation begins with a hunt phase in

which a bit pattern that matches the programmed sync

characters (6-,8-, or 16-bit) is searched.

The incoming data then passes through the Sync register

and is compared to a sync character stored in WR6 or

WR7 (depending on which mode it is in). The Monosync

mode matches the sync character programmed in WR7

and the character assembled in the Receive Sync register

to establish synchronization.

The same path is taken by incoming data for both SDLC

and SDLC Loop modes. The reformatted data enters the

3-bit delay and is transferred to the Receive Shift register.

The SDLC receive operation begins in the hunt phase by

attempting to match the assembled character in the Re-

ceive Shift Register with the flag pattern in WR7. When the

flag character is recognized, subsequent data is routed

through the same path, regardless of character length.

Synchronization is achieved differently in the Bisync

mode. Incoming data is shifted to the Receive Shift register

while the next eight bits of the message are assembled in

the Receive Sync register. If these two characters match

the programmed characters in WR6 and WR7, synchroni-

zation is established. Incoming data can then bypass the

Receive Sync register and enter the 3-bit delay directly.

Either the CRC-16 or CRC-SDLC (cyclic redundancy

check or CRC) polynomial can be used for both Monosync

and Bisync modes, but only the CRC-SDLC polynomial is

used for SDLC operation. The data path taken for each

mode is also different. Bisync protocol is a byte-oriented

operation that requires the CPU to decide whether or not a

data character is to be included in CRC calculation. An 8-

bit delay in all Synchronous modes except SDLC is al-

lowed for this process. In SDLC mode, all bytes are includ-

ed in the CRC calculation.

The SDLC mode of operation uses the Receive Sync regis-

ter to monitor the receive data stream and to perform zero

deletion when necessary; i.e., when five continuous 1s are

received, the sixth bit is inspected and deleted from the data

stream if it is 0. The seventh bit is inspected only if the sixth

bit equals one. If the seventh bit is 0, a flag sequence has

4.2 ASYNCHRONOUS MODE

In asynchronous communications, data is transferred in

the format shown in Figure 4-3.

Idle State

of Line

Stop

Bit(s)

Data Field

1

0

LSB

1

1.5

Parity

Bit

Start

Bit

2

Figure 4-3. Asynchronous Message Format

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4.2 ASYNCHRONOUS MODE (Continued)

The transmission of a character begins when the line

makes a transition from the 1 state (or MARK condition) to

the 0 state (or SPACE condition). This transition is the ref-

erence by which the character’s bit cell boundaries are de-

fined. Though the transmitter and receiver have no com-

mon clock signal, they must be at the same data rate so

that the receiver can sample the data in the center of the

bit cell.

of WR6 and WR7, and all of WR10 except D6 and D5. Ig-

nored bits are programmed with 1 or 0 (Table 4-1).

Table 4-1. Write Register Bits Ignored in

Asynchronous Mode

Register D7 D6 D5 D4 D3 D2 D1 D0

WR3

WR4

WR5

WR6

WR7

WR10

x

0

x

The SCC also supports Isochronous mode, which is the

same as Asynchronous except that the clock is the same

rate as the data. This mode is selected by selecting

x1 clock mode in WR4 (D7 & D6=0). Using this mode typ-

ically requires that the transmit clock source be transmitted

along with the data, or that the clock be synchronized with

the data.

x

Note: If WR3 D1 is set (enabling the sync character load inhibit

feature), any character matching the value in WR6 is stripped out

of the incoming data stream and not put into the Receive FIFO.

Therefore, as this feature is typically only desired in synchronous

formats, this bit should reset in Asynchronous mode.

The character can be broken up into four fields:

■ Start bit - signals the beginning of a character frame.

■ Data field - typically 5-8 bits wide.

4.2.1 Asynchronous Transmit

Asynchronous mode is selected by specifying the number

of stop bits per character in bits D3 and D2 of WR4. The

three options available are one, one-and-a-half, and two

stop bits per character. These two bits select only the num-

ber of stop bits for the transmitter, as the receiver always

checks for one stop bit.

■ Parity bit - optional error checking mechanism.

■ Stop bit(s) - Provides a minimum interval between the

end of one character and the beginning of the next.

Generation and checking of parity is optional and is con-

trolled by WR4 D1 & D0. WR4 bit D0 is used to enable par-

ity. If WR4 bit D1 is set, even parity is selected and if D1 is

reset, odd parity is selected. For even parity, the parity bit

is set/reset so that the data byte plus the parity bit contains

an even number of 1s. For odd parity, the parity bit is

set/reset such that the data byte plus the parity bit contains

an odd number of 1s.

The number of bits per transmitted character is controlled

both by bits D6 and D5 in WR5 and the way the data is for-

matted within the transmit buffer (in the case of the ESCC,

Transmit FIFO). The bits in WR5 allow the option of five,

six, seven, or eight bits per character. In all cases the data

must be right-justified, with the unused bits being ignored

except in the case of five bits per character. When the five

bits per character option is selected, the data may be for-

matted before being written to the transmit buffer. This al-

lows transmission of from one to five bits per character.

The formatting is shown in Table 4-2.

The SCC supports Asynchronous mode with a number of

programmable options including the number of bits per

character, the number of stop bits, the clock factor, modem

interface signals, and break detect and generation.

Asynchronous mode is selected by programming the de-

sired number of stop bits in D3 and D2 of WR4. Program-

ming these two bits with other than 00 places both the re-

ceiver and transmitter in Asynchronous mode. In this

mode, the SCC ignores the state of bits D4, D3, and D2 of

WR3, bits D5 and D4 of WR4, bits D2 and D0 of WR5, all

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Table 4-2. Transmit Bits per Character

to send clocking information (transmit clock) along with the

data in order to receive data correctly.

Bit 7

Bit 6

There are two modem control signals associated with the

transmitter provided by the SCC; /RTS and /CTS.

0

1

0

1

0

1

5 or less bits/character

7 bits/character

6 bits/character

4

The /RTS pin is a simple output that carries the inverted

state of the RTS bit (D1) in WR5, unless the Auto Enables

mode bit (D5) is set in WR3. When Auto Enables is set, the

/RTS pin immediately goes Low when the RTS bit is set.

However, when the RTS bit is reset, the /RTS pin remains

Low until the transmitter is completely empty and the last

stop bit has left the TxD pin. Thus, the /RTS pin may be

used to disable external drivers for the transmit data. The

/CTS pin is ordinarily a simple input to the CTS bit in RR0.

However, if Auto Enables mode is selected, this pin be-

comes an enable for the transmitter. That is, if Auto En-

ables is on and the /CTS pin is High, the transmitter is dis-

abled; the transmitter is enabled while the /CTS pin is Low.

8 bits/character

Note: For five or less bits per character selection in WR5, the

following encoding is used in the data sent to the transmitter.

D is the data bit(s) to be sent.

D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

1

0

1

0

D

0

D

0

D

0

D

Sends one data bit

Sends two data bits

Sends three data bits

Sends four data bits

Sends ﬁve data bits

D

An additional bit, carrying parity information, may be auto-

matically appended to every transmitted character by set-

ting bit D0 of WR4 to 1. This bit is sent in addition to the

number of bits specified in WR4 or by bit D1 of WR4. If this

bit is set to 1, the transmitter sends even parity and, if set

to 0, the parity is odd.

The initialization sequence for the transmitter in Asynchro-

nous mode is WR4 first to select the mode, then WR3 and

WR5 to select the various options. At this point the other

registers should be initialized as necessary. When all of

this is complete, the transmitter may be enabled by setting

bit D3 of WR5 to 1. Note that the transmitter and receiver

may be initialized at the same time.

The transmitter may be programmed to send a Break by

setting bit D4 of WR5 to 1. The transmitter will send con-

tiguous 0s from the first transmit clock edge after this com-

mand is issued, until the first transmit clock edge after this

bit is reset. The transmit clock edges referred to here are

those that defined transmitted bit cell boundaries. Care

must be taken when Break is sent. As mentioned above,

the SCC initiates the Break sequence regardless of the

character boundaries. Typically, the break sequence is de-

fined as “null character (all 0 data) with framing error”. The

other party may not be able to recognize it as a break se-

quence if the Send Break bit has been set in the middle of

sending a non-zero character.

4.2.1.1 Asynchronous transmit on the NMOS/CMOS

On the NMOS/CMOS version of the SCC, characters are

loaded from the transmit buffer to the shift register where

they are given a start bit and a parity bit (as programmed),

and are shifted out to the TxD pin. The transmit buffer

empty interrupt and the DMA request (either /W//REQ or

/DTR//REQ pin) are asserted when the transmit buffer is

empty, if these are enabled. At this time, the CPU or the

DMA is able to write one byte of transmit data. The Trans-

mit Buffer Empty (TBE) bit (RR0, bit D2) also follows the

state of the transmit buffer. The All Sent bit, RR1, bit D0,

can be polled to determine when the last bit of transmit

data has cleared the TxD pin. For details about the trans-

mit DMA and transmit interrupts, refer to Section 2.4.8

“Transmit Interrupt and Transmit Buffer Empty bit.”

An additional status bit for use in Asynchronous mode is

available in bit D0 of RR1. This bit, called All Sent, is set

when the transmitter is completely empty and any previous

data or stop bits have reached the TxD pin. The All Sent

bit can be used by the processor as an indication that the

transmitter may be safely disabled, or indication to change

the modem status signal.

4.2.1.2 Asynchronous transmit on the ESCC

On the ESCC, characters are loaded from the Transmit

FIFO to the shift register where they are given a start bit

and a parity bit (as programmed), and are shifted out to the

TxD pin. The ESCC can generate an interrupt or DMA re-

quest depending on the status of the Transmit FIFO. If

WR7' D5 is reset, the transmit buffer empty interrupt and

DMA request (either /W//REQ or /DTR//REQ pin) are as-

serted when the entry location of the Transmit FIFO is

empty (one byte can be written). If WR7' D5 is set, the

transmit interrupt and DMA request is generated when the

Transmit FIFO is completely empty (four bytes can be writ-

ten). The Transmit Buffer Empty (TBE) bit in RR0, bit D2

also is affected by the state of WR7' bit D5. The All Sent

The SCC may be programmed to accept a transmit clock

that is one, sixteen, thirty-two, or sixty-four times the data

rate. This is selected by bits D7 and D6 in WR4, in com-

mon with the clock factor for the receiver.

Note: When using Isosynchronous (X1 clock) mode, one-

and-a-half stop bits are not allowed. Only one or two stop

bits should be selected. If some length other than one stop

bit is desired in the times one mode, only two stop bits may

be used. Also, in this mode, the Transmitter usually needs

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4.2 ASYNCHRONOUS MODE (Continued)

bit, bit D0 of RR1, can be polled to determine when the last

bit of transmit data has cleared the TxD pin.

■ Parity errors—The parity bit of a character disagrees

with the sense programmed in WR4.

The number of transmit interrupts can be minimized by set-

ting bit D5 of WR7' to one and writing four bytes to the

transmitter for each transmit interrupt. This requires that

the system response to interrupt is less than the time it

takes to transmit one byte at the programmed baud rate. If

the system’s interrupt response time is too long to use this

feature, bit D5 of WR7' should be reset to 0. Then, poll the

TBE bit and poll after each data write to test if there is

space in the Transmit FIFO for more data.

■ Overrun errors—When the Receive FIFO overflows.

If interrupts are not used to transfer data, the Parity Error,

Framing Error, and Overrun Error bits in RR1 should be

checked before the data is removed from the receive data

FIFO, because reading data pops up the error information

stored in the Error FIFO.

The SCC may be programmed to accept a receive clock

that is one, sixteen, thirty-two, or sixty-four times the data

rate. This is selected by bits D7 and D6 in WR4. The 1X

mode is used when bit synchronization external to the re-

ceived clock is present (i.e., the clock recovery circuit, or

active receive clock from the sender side). The 1X mode is

the only mode in which a data encoding method other than

NRZ may be used. The clock factor is common to the re-

ceiver and transmitter.

For details about the transmit DMA and transmit interrupts,

refer to Section 2.4.8 “Transmit Interrupt and Transmit

Buffer Empty bit”.

4.2.2 Asynchronous Receive

Asynchronous mode is selected by specifying the number

of stop bits per character in bits D3 and D2 of WR4. This

selection applies only to the transmitter, however, as the

receiver always checks for one stop bit. If after character

assembly the receiver finds this stop bit to be a 0, the

Framing Error bit in the receive error FIFO is set at the

same time that the character is transferred to the receive

data FIFO. This error bit accompanies the data to the exit

location (CPU side) of the Receive FIFO, where it is a spe-

cial receive condition. The Framing Error bit is not latched,

so it must be read in RR1 before the accompanying data

is read.

The break condition is continuous 0s, as opposed to the

usual continuous ones during an idle condition. The SCC

recognizes the Break condition upon seeing a null charac-

ter (all 0s) plus a framing error. Upon recognizing this se-

quence, the Break bit in RR0 is set and remains set until a

1 is received. At this point, the break condition is no longer

present. At the termination of a break, the receive data

FIFO contains a single null character, which should be

read and discarded. The framing error bit will not be set for

this character, but if odd parity has been selected, the Par-

ity Error bit is set.

The number of bits per character is controlled by bits D7

and D6 of WR3. Five, six, seven or eight bits per character

may be selected via these two bits. Data is right justified

with the unused bits set to 1s. An additional bit, carrying

parity information, may be selected by setting bit D0 of

WR4 to 1. Note that this also enables parity for the trans-

mitter. The parity sense is selected by bit D1 of WR4. If this

bit is set to 1, the received character is checked for even

parity, and if set to 0, the received character is checked for

odd parity. The additional bit per character that is parity is

transferred to the receive data FIFO along with the data, if

the data plus parity is eight bits or less. The parity error bit

in the receive error FIFO may be programmed to cause

special receive interrupts by setting bit D2 of WR1 to 1.

Once set, this error bit is latched and remains active until

an Error Reset command has been issued.

Note: Caution should be exercised if the receive data line

contains a switch that is not debounced to generate

breaks. If this is the case, switch bounce may cause multi-

ple breaks to be recognized by the SCC, with additional

characters assembled in the receive data FIFO and the

possibility of a receive overrun condition being latched.

The SCC provides up to three modem control signals as-

sociated with the receiver; /SYNC, /DTR//REQ,

and /DCD.

The /SYNC pin is a general purpose input whose state is

reported in the Sync/Hunt bit in RR0. If the crystal oscillator

is enabled, this pin is not available and the Sync/Hunt bit

is forced to 0. Otherwise, the /SYNC pin may be used to

carry the Ring Indicator signal.

Since errors apply to specific characters, it is necessary

that error information moves alongside the data that it re-

fers to. This is implemented in the SCC with an error FIFO

in parallel with the data FIFO. The three error conditions

that the receiver checks for in Asynchronous mode are:

The /DTR//REQ pin carries the inverted state of the DTR

bit (D7) in WR5 unless this pin has been programmed to

carry a DMA request signal.

The /DCD pin is ordinarily a simple input to the DCD bit in

RR0. However, if the Auto Enables mode is selected by

setting D5 of WR3 to 1, this pin becomes an enable for the

■ Framing errors—When a character’s stop bit is a 0.

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Data Communication Modes

receiver. That is, if Auto Enables is on and the /DCD pin is

High, the receiver is disabled; while the /DCD pin is low,

the receiver is enabled.

4.2.3 Asynchronous Initialization

The initialization sequence for Asynchronous mode is

shown in Table 4-3. All of the SCC’s registers should be re-

initialized after a channel or hardware reset. Also, WR4

should be programmed first after a reset.

4

Received characters are assembled, checked for errors,

and moved to the receive data FIFO (eight bytes on ESCC,

three bytes on NMOS/CMOS). The user can program the

SCC to generate an interrupt to the CPU or to request a

data read from a DMA when data is received.

Table 4-3. Initialization Sequence

Asynchronous Mode

Reg

WR9

WR4

Bit No Description

On the NMOS/CMOS version, it generates the Receive

Character Available interrupt and DMA Request on Re-

ceive (if enabled). The receive interrupt and DMA request

is generated when there is at least one character in the

FIFO. The Rx Character Available (RCA) bit is set if there

is at least one byte available.

6, 7 Hardware or channel Reset

3, 2 Select Async Mode and the number

of stop bits*

0, 1 Select parity*

6, 7 Select clock mode*

7, 6 Select number of receive bits per

character

WR3

WR5

Note:

The ESCC generates the receive character available inter-

rupt and DMA request on Receive (if enabled) and is de-

pendent on WR7' bit D3. If this bit is reset to 0 (this mode

is comparable to the NMOS/CMOS version), the receive

interrupt and DMA request is generated when there is at

least one character in the FIFO. If WR7' bit D3 is set to 1,

the receive interrupt and DMA request are generated

when there are four bytes available in the Receive FIFO.

The RCA bit in RR0 follows the state of WR7' D3. The RCA

bit is set if there is at least one byte available, regardless

of the status of WR7' bit D3.

5

Select Auto Enables Mode*

6, 5 Select number of bits/char for

transmitter

1

Select modem control (RTS)

* Initializes transmitter and receiver simultaneously.

At this point, the other registers should be initialized ac-

cording to the hardware design such as clocking,

I/O mode, etc. When this is completed, the transmitter is

enabled by setting WR5 bit D3 to 1 and the receiver is en-

abled by setting WR3 bit D0 to 1.

This is the initialization sequence for the receiver in Asyn-

chronous mode. First, WR4 selects the mode, then WR3

and WR5 select the various options. At this point, the other

registers should be initialized as necessary. When all of

this is complete, the receiver may be enabled by setting bit

D0 of WR3 to 1.

See Section 2.4.7 “The Receive Interrupt” for more details

on receive interrupts.

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE

The SCC supports three byte-oriented synchronous proto-

cols. They are: monosynchronous, bisynchronous, and ex-

ternal synchronous.

with no gaps between characters. This requires that there

be an agreement as to the location of the character

boundaries so that the characters can be properly

framed. This is normally accomplished by defining spe-

cial synchronization patterns, or Sync characters. The

synchronization pattern serves as a reference; it signals

the receiver that a character boundary occurs immediate-

ly after the last bit of the pattern. For example Monosync

Protocol usually uses 16 Hex as this special character,

and the SDLC protocol uses 0, six 1s, followed by a 0 (7E

Hex; usually referred to as Flag Pattern) to mark the be-

ginning and end of a block of data. Another way of iden-

tifying the character boundaries (i.e., achieving synchro-

nization) is with a logic signal that goes active just as the

first character is about to enter the receiver. This method

is referred to as External Synchronization.

In synchronous communications, the bit cell boundaries

are referenced to a clock signal common to both the trans-

mitter and receiver. Consequently, they operate in a fixed-

phase relationship. This eliminates the need for the receiv-

er to locate the bit cell boundaries with a clock 16, 32, or

64 times the receive data rate, allowing for higher speed

communication links. Some applications may encode (i.e.,

NRZI or FM coding) the clock information on the same line

as the data. Therefore, these applications require that the

receiver use a high speed clock to find the bit cell bound-

aries (decoding is typically done with the PLL—Phase-

Locked Loop; the SCC has on-chip Digital PLL). Data en-

coding eliminates the need to transmit the synchronous

clock on a separate wire from the data.

Figure 4-4 shows the character format for synchronous

transmission. For example, bits 1-8 might be one charac-

ter and bits 9-13 part of another character; or, bit 1 might

be part of a second character, and bits 10-13 part of a third

character. This is accomplished by defining a synchroniza-

tion character, commonly called a Sync Character.

Synchronous data does not use start and stop bits to de-

lineate the boundaries for each character. This eliminates

the overhead associated with every character and increas-

es the line efficiency. Because of the phase relationship of

synchronous data to a clock, data is transferred in blocks

1 Bit Time

Modem Clock

Bit

1

0

2 3 4 5 6 7 8 9 10 11 12 13 . . .

1 1 0 1 0 0 0 1 1 0 1 0 1 0 1

Bit State

Data LSB

Sync Character

Data Character

Figure 4-4. Monosync Data Character Format

The 8-bit sync character is selected by setting bits 4 and 5

4.3.1 Byte-Oriented Synchronous Transmit

of WR4 to zeros and bit 0 of WR10 to zeros. With this op-

tion selected, the transmitter sends the contents of WR6

when it has no data to send.

Once Synchronous mode has been selected, any of three

of the following sync character lengths may be selected:

■ 6-bit

■ 8-bit

■ 16-bit

For a 16-bit sync character, set bit D4 of WR4 to 1 and bit

D5 of WR4 and bit D0 of WR10 to 0. In this mode, the

transmitter sends the concatenation of WR6 and WR7 for

the idle line condition.

Because the receiver requires that sync characters be left-

justified in the registers, while the transmitter requires

them to be right justified, only the receiver works with a 12-

bit sync character. While the receiver is in External Sync

The 6-bit option sync character is selected by setting bits

4 and 5 of WR4 to zeros and bit 0 of WR10 to one. Only

the least significant six bits of WR6 are transmitted.

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mode, the transmitter sync length may be six or eight bits,

as selected by bit D0 of WR10.

the data must be right-justified, with the unused bits being

ignored except in the case of five bits per character. When

the five bits per character option is selected, the data must

be formatted before being written to the transmit buffer to

allow transmission of from one to five bits per character.

This formatting is shown in Table 4-2.

Monosync and Bisync modes require clocking information

to be transmitted along with the data either by a method of

encoding data that contains clocking information, or by a

modem that encodes or decodes clock information in the

modulation process. Refer to the Monosync message for-

mat shown in Figure 4-4.

4

An additional bit, carrying parity information, may be auto-

matically appended to every transmitted character by set-

ting bit D0 of WR4 to 1. This parity bit is sent in addition to

the number of bits specified in WR4 or by the data format.

If this bit is set to 1, the transmitter sends even parity; if set

to 0, the transmitted parity is odd. Parity is not typically

used in synchronous applications because the CRC pro-

vides a more reliable method for detecting errors.

The Bisync mode of operation is similar to the Monosync

mode, except that two sync characters are provided in-

stead of one. Bisync attempts a more structured approach

to synchronization through the use of special characters

as message headers or trailers.

Character-oriented mode is selected by programming bits

D3 and D2 of WR4 with zeros. This selects Synchronous

mode, as opposed to Asynchronous mode, but this selec-

tion is further modified by bits 5 and 7 of WR4 as well as

bits 1 and 0 of WR10. During the sync character-oriented

modes, except in External Sync mode, the state of bits 7

and 6 of WR4 are always forced internally to zeros. In ex-

ternal sync mode, these two bits must be programmed with

zeros (Table 4-4.). The combination, other than 00 in Ex-

ternal Sync mode, puts the SCC in special synchronization

modes.

Either of two CRC polynomials are used in Synchronous

modes, selected by bit D2 in WR5. If this bit is set to 1, the

CRC-16 polynomial is used and, if this bit is set to 0, the

CRC-CCITT polynomial is used. This bit controls the se-

lection for both the transmitter and receiver. The initial

state of the generator and checker is controlled by bit D7

of WR10. When this bit is set to 1, both the generator and

checker have an initial value of all ones; if this bit is set to

0, the initial values are all zeros.

The SCC does not automatically preset the CRC genera-

tor in byte Synchronous modes, so this must be done in

software. This is accomplished by issuing the Reset Tx

CRC Generator command, which is encoded in bits D7

and D6 of WR0. For proper results, this command is is-

sued while the transmitter is enabled and sending sync

characters.

Table 4-4. Registers Used in Character-Oriented

Modes

Reg

Bit No Description

WR4

3 (=0)

2 (=0)

4 (=0)

5 (=0)

4 (=1)

5 (=0)

4 (=1)

5 (=1)

6 (=0)

7 (=0)

select sync mode

If the CRC is to be used, the transmit CRC generator must

be enabled by setting bit D0 of WR5 to 1. This bit may also

be used to exclude certain characters from the CRC calcu-

lation. Sync characters (from sync registers) are automat-

ically excluded from the CRC calculation, and any charac-

ters written as data are excluded from the calculation by

using bit D0 of WR5. Internally, enabling or disabling the

CRC for a particular character happens at the same time

the character is loaded from the transmit data buffer (on

the ESCC, the Transmit FIFO) to the Transmit Shift regis-

ter. Thus, to exclude a character from the CRC calculation

bit, D0 of WR5 is set to 0 before the character is written to

the transmit buffer (on the ESCC, the Transmit FIFO).

select monosync mode

(8-bit sync character)

select bisync mode

(16-bit sync character)

select external sync mode

(external sync signal required)

select 1x clock mode

WR6

WR7

WR10

7-0

1

sync character (low byte)

sync character (high byte)

select sync character length

In character-oriented modes, a special bit pattern is used

to provide character synchronization. The SCC offers sev-

eral options to support Synchronous mode including vari-

ous sync generation and checking, CRC generation and

checking, as well as modem controls and a transmitter to

receiver synchronization function.

ESCC:

Since the ESCC has a four-byte FIFO, if a character is

to be excluded from the CRC calculation, it is recom-

mended that only one byte be written to the ESCC at

that time. If WR7' D5 is reset, the transmit interrupt is

generated when the FIFO is completely empty. This

can be used as a signal to reset WR5 bit D0, and then

the character can be written to the Transmit FIFO. This

guarantees that the internal disable occurs when the

character moves from the buffer to the shift register.

The number of bits per transmitted character is controlled

by D6 and D5 of WR5 plus the way the data is formatted

within the transmit buffer. The bits in WR5 select the option

of five, six, seven, or eight bits per character. In all cases,

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

Once the buffer becomes empty, the Tx CRC Enable

bit is written for the next character.

The initialization sequence for the transmitter in character-

oriented mode is shown in Table 4-5.

Enabling the CRC generator is not sufficient to control the

transmission of the CRC. In the SCC, this function is con-

trolled by the Tx Underrun/EOM bit, which is reset by the

processor and set by the SCC. When the transmitter un-

derruns (both the transmit buffer and Transmit Shift regis-

ter are empty) the state of the Tx Underrun/EOM bit deter-

mines the action taken by the SCC. If the Tx

Underrun/EOM bit is reset when the underrun occurs, the

transmitter sends the accumulated CRC and sets the Tx

Underrun/EOM bit to indicate this. This transition is pro-

grammed to cause an external/status interrupt, or the Tx

Underrun/EOM is available in RR0.

Table 4-5. Transmitter Initialization in Character-

Oriented Mode

Reg Bit No Description

WR4

0,1

selects parity (not typically used

insync modes)

WR5

1

2

RTS

selects CRC generator

selects number of bits per character

CRC preset value

5,6

7

WR10

At this point, the other registers should be initialized as nec-

essary. When all of this is completed, the transmitter is en-

abled by setting bit 3 of WR5 to one. Now that the transmit-

ter is enabled, the CRC generator is initialized by issuing the

Reset Tx CRC Generator command in WR0, bits 6-7.

The Reset Tx Underrun/EOM Latch command is encoded

in bits D7 and D6 of WR0. For correct transmission of the

CRC at the end of a block of data, this command is issued

after the first character is written to the SCC but before the

transmitter underruns. The command is usually issued im-

mediately after the first character is written to the SCC so

that the CRC is sent if an underrun occurs inadvertently

during the block of data.

4.3.2 Byte-Oriented Synchronous Receive

The receiver in the SCC searches for character synchroni-

zation only while it is in Hunt mode. In this mode the receiv-

er is idle except that it is searching the incoming data

stream for a sync character match.

85X30

If WR7' bit D1 is set, the Reset Transmit Underrun/EOM

latch is automatically reset after the first byte is writ-

ten to the transmitter. This eliminates the need for the

CPU to issue this command. This feature can be par-

ticularly useful to applications using a DMA to write

data to the transmitter since there is no longer a need

to interrupt the data transfers to issue this command.

In Hunt mode, the receiver shifts for each bit into the Re-

ceive Shift register. The contents of the Receive Shift reg-

ister are compared with the sync character (stored in an-

other register), repeating the process until a match occurs.

When a match occurs, the receiver begins transferring

bytes to the Receive FIFO.

The receiver is in Hunt mode when it is first enabled, and

it may be placed in Hunt mode by the processor issuing the

Enter Hunt Mode command in WR3. This bit (D4) is a com-

mand, so writing a 0 to it has no effect. The hunt status of

the receiver is reported by the Sync/Hunt bit in RR0.

Sync/Hunt is one of the possible sources of external/status

interrupts, with both transitions causing an interrupt. This

is true even if the Sync/Hunt bit is set as a result of the pro-

cessor issuing the Enter Hunt Mode command.

If the transmitter is disabled during the transmission of a

character, that character is sent completely. This applies

to both data and sync characters. However, if the transmit-

ter is disabled during the transmission of the CRC, the

16-bit transmission is completed, but the remaining bits

will come from the Sync registers rather than the remain-

der of the CRC.

There are two modem control signals associated with the

transmitter provided by the SCC: /RTS and /CTS.

Once the sync character-oriented mode has been select-

ed, any of the four sync character lengths may be selected:

6 bits, 8 bits, 12 bits, or 16 bits.

The /RTS pin is a simple output that carries the inverted

state of the RTS bit (D1) in WR5.

The /CTS pin is ordinarily a simple input to the CTS bit in

RR0. However, if Auto Enables mode is selected, this pin

becomes an enable for the transmitter. That is, if Auto En-

ables is on and the /CTS pin is High, the transmitter is dis-

abled. While the /CTS pin is Low, the transmitter is enabled.

The Table 4-6 shows the write register bit setting for se-

lecting sync character length.

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Table 4-6. Sync Character Length Selection

provide a character synchronization signal on the /SYNC

pin. This mode is selected by setting bits D5 and D4 of

WR4 to 1. In this mode, the Sync/Hunt bit in RR0 reports

the state of the /SYNC pin, but the receiver is still placed in

Hunt mode when the external logic is searching for a sync

character match. Two receive clock cycles after the last bit

of the sync character is received, the receiver is in Hunt

mode and the /SYNC pin is driven Low, then character as-

sembly begins on the rising edge of the receive clock. This

immediately precedes the activation of /SYNC (Figure 4-

6). The receiver leaves Hunt mode when /SYNC is driven

Low.

Sync Length WR4,D5

WR4,D4

WR10,D0

6 bits

8 bits

12 bits

16 bits

0

1

0

1

0

4

The arrangement of the sync character in WR6 and WR7

is shown in Figure 4-5.

For those applications requiring any other sync character

length, the SCC makes provision for an external circuit to

Write Register 6

D7 D6 D5 D4 D3 D2 D1 D0

Sync5 Sync4 Sync3

Sync0

Monosync, 8 Bits

Sync7 Sync6

Sync2 Sync1

Sync1 Sync0 Sync5 Sync4 Sync3 Sync2 Sync1 Sync0 Monosync, 6 Bits

Sync5 Sync4 Sync3

Sync0

Sync7 Sync6

Sync3 Sync2

ADR7 ADR6

Sync2 Sync1

Bisync, 16 Bits

Bisync, 12 Bits

SDLC

Sync1 Sync0

ADR5 ADR4

1

ADR3

x

1

ADR0

x

1

ADR2 ADR1

x

SDLC (Address Range)

Write Register 7

D7 D6 D5 D4 D3 D2 D1 D0

Sync5 Sync4 Sync3 Sync2 Sync1 Sync0 Monosync, 8 Bits

Sync7 Sync6

Sync5 Sync4 Sync3 Sync2 Sync1 Sync0

x

Monosync, 6 Bits

Sync13 Sync12 Sync11 Sync10 Sync9 Sync8 Bisync, 16 Bits

Sync9 Sync8 Sync7 Sync6 Sync5 Sync4 Bisync, 12 Bits

Sync15 Sync14

Sync11 Sync10

1

0

SDLC

0

1

Figure 4-5. Sync Character Programming

/RTxC

RxD

SYNC Last-1

SYNC Last

Data 0

Data 1

Data 2

/SYNC

Figure 4-6. /SYNC as an Input

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

In all cases except External Sync mode, the /SYNC pin is

an output that is driven Low by the SCC to signal that a

sync character has been received. The /SYNC pin is

activated regardless of character boundaries, so any

external circuitry using it should only respond to the /SYNC

pulse that occurs while the receiver is in Hunt mode. The

timing for the /SYNC signal is shown in Figure 4-7.

/RTxC

PCLK

/SYNC

State Changes in One

/RTxC Clock Cycle

Figure 4-7. /SYNC as an Output

To prevent sync characters from entering the receive data

FIFO, set the Sync Character Load Inhibit bit (D1) in WR3

to 1. While this bit is set to 1, characters about to be loaded

into the receive data FIFO are compared with the contents

of WR6. If all eight bits match the character, it is not loaded

into the receive data FIFO. Because the comparison is

across eight bits, this function should only be used with 8-

bit sync characters. It cannot be used with 12- or 16-bit

sync characters. Both leading sync characters are re-

moved in the case of a 6-bit sync character. Care must be

exercised in using this feature because sync characters

which are not transferred to the receive data FIFO will au-

tomatically be excluded from CRC calculation. This works

properly only in the 8-bit case.

An additional bit carrying parity information is selected by

setting bit D0 of WR4 to 1. Note that this also enables par-

ity for the transmitter. The bit D1 of WR4 selects parity

sense. If this bit is set to 1, the received character is

checked for even parity. If WR4 D1 is reset to 0, the re-

ceived character is checked for odd parity. The additional

bit per character is transferred to the FIFO as a part of data

when the data plus parity is less than 8 bits per character.

The Parity Error bit in the receive error FIFO may be pro-

grammed to cause a Special Receive Condition interrupt

by setting bit D2 of WR1 to 1. Once set, this error bit is

latched and remains active until an Error Reset command

has been issued. If interrupts are not used to transfer data,

the Parity Error, CRC Error, and Overrun Error bits in RR1

should be checked before the data is removed from the re-

ceive data FIFO.

The number of bits per character is controlled by bits D7

and D6 of WR3. Five, six, seven, or eight bits per character

may be selected via these two bits. The data is right-justi-

fied in the receive data buffer. The SCC merely takes a

snapshot of the receive data stream at the appropriate

times, so the “unused” bits in the receive buffer are only

the bits following the character in the data stream.

The character length can be changed at any time before

the new number of bits has been assembled by the

receiver, but, care should be exercised as unexpected

results may occur. A representative example would be

switching from five bits to eight bits and back to five bits

(Figure 4-8).

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Receive Data Buffer

4

5 Bits

8 Bits

5 Bits

8

7

6

5

4

3

8

2

7

1

6

Time

13 12 11 10 9

Change from Five to Eight

21 20 19 18 17 16 15 14

29 28 27 26 25 24 23 22

34 33 32 31 30 29 28 27

39 38 37 36 35 34 33 32

Change from Eight to Five

Figure 4-8. Changing Character Length

Either of two CRC polynomials are used in Synchronous

modes, selected by bit D2 in WR5. If this bit is set to 1, the

CRC-16 polynomial is used, if this bit is set to 0, the CRC-

CCITT polynomial is used. This bit controls the polynomial

selection for both the receiver and transmitter.

Some synchronous protocols require that certain charac-

ters be excluded from CRC calculation. This is possible in

the SCC because CRC calculations are enabled and dis-

abled on the fly. To give the processor sufficient time to de-

cide whether or not a particular character should be includ-

ed in the CRC calculation, the SCC contains an 8-bit time

delay between the receive shift register and the CRC

checker. The logic also guarantees that the calculation

only starts or stops on a character boundary by delaying

the enable or disable until the next character is loaded into

the receive data FIFO. Because the nature of the protocol

requires that CRC calculation disable/enable be selected

before the next character gets loaded into the Receive

FIFO, users cannot take advantage of the FIFO.

The initial state of the generator and checker is controlled

by bit D7 of WR10. When this bit is set to 1, both the gen-

erator and checker have initial values of all ones; if this bit

is set to 0, the initial values are all 0. The SCC presets the

checker whenever the receiver is in Hunt mode so a CRC

reset command is not necessary. However, there is a Re-

set CRC Checker command in WR0. This command is en-

coded in bits D7 and D6 of WR0. If the CRC is used, the

CRC checker is enabled by setting bit D0 of WR3 to 1.

To understand how this works refer to Figure 4-9 and the

following explanation. Consider a case where the SCC

receives a sequence of eight bytes, called A, B, C, D, E, F,

G and H, with A received first. Now suppose that A is the

sync character, the CRC is calculated on B, C, E, and F,

and that F is the last byte of this message. This process is

used to control the SCC.

Sync characters can be stripped from the data stream any

time before the first non-sync character is received. If the

sync strip feature is not being used, the CRC is not en-

abled until after the first data character has been trans-

ferred to the receive data FIFO. As previously mentioned,

8-bit sync characters stripped from the data stream are au-

tomatically excluded from CRC calculation.

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

3 Bytes Deep for NMOS/CMOS

8 Bytes Deep for ESCC

Receive Data FIFO

Receive Data

Receive Shift Register

Eight Bit Time Delay

CRC Checker

Figure 4-9. Receive CRC Data Path

Before A is received, the receiver is in Hunt mode and the

CRC is disabled. When A is in the receive shift register, it

is compared with the contents of WR7. Since A is the sync

character, the bit patterns match and receive leaves Hunt

mode, but character A is not transferred to the receive

data FIFO.

the Receive Shift register and the CRC is not being calcu-

lated on D. After these eight-bit times have elapsed, E is in

the 8-bit delay, and F is in the Receive Shift register. Now

F is transferred to the receive data FIFO and the CRC is

enabled. During the next eight-bit times, the processor

reads F and leaves the CRC enabled. The processor de-

tects that this is the last character in the message and pre-

pares to check the result of the CRC computation. Howev-

er, another sixteen bit-times are required before the CRC

has been calculated on all of character F.

After eight-bit times, B is loaded into the receive data

FIFO. The CRC remains disabled even though some-

where during the next eight bit times the processor reads

B and enables the CRC. At the end of this eight-bit time, B

is in the 8-bit delay and C is in the receive shift register.

At the end of eight-bit times, F is in the 8-bit delay and G is

in the Receive Shift register. At this time, it is transferred to

the receive data FIFO. Character G is read and discarded

by the processor. Eight-bit times later, H is also transferred

to the receive data FIFO. The result of a CRC calculation

is latched in to the Receive Error FIFO at the same time as

data is written to the Receive Data FIFO. Thus, the CRC

result through character F accompanies character H in the

FIFO and will be valid in RR1 until character H is read from

the Receive Data FIFO. The CRC checker is disabled and

reset at any time after character H is transferred to the Re-

ceive Data FIFO. Recall, however, that internally the CRC

is not disabled until after this occurs. A better alternative is

to place the receiver in Hunt mode, which automatically

disables and resets the CRC checker. See Table 4-7 for a

condensed description.

Character C is loaded into the receive data FIFO and at the

same time the CRC checker becomes enabled. During the

next eight-bit time, the processor reads C and since the

CRC is enabled within this period, the SCC has calculated

the CRC on B, character C is the 8-bit delay, and D is in

the Receive Shift register. D is then loaded into the receive

data FIFO and at some point during the next eight-bit time

the processor reads D and disables the CRC. At the end

of these eight-bit times, the CRC has been calculated on

C, character D is in the 8-bit delay, and E is in the Receive

Shift register.

Now E is loaded into the receive data FIFO. During the

next eight-bit time, the processor reads E and enables the

CRC. During this time E shifts into the 8-bit delay, F enters

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Modem Controls. Up to two modem control signals asso-

ciated with the receiver are available in Synchronous

modes: /DTR//REQ and /DCD. The /DTR//REQ pin carries

the inverted state of the DTR bit (D7) in WR5 unless this

pin has been programmed to carry a DMA Request on

Transmit signal. The /DCD pin is ordinarily a simple input

to the DCD bit in RR0. However, if the Auto Enables mode

is selected by setting D5 of WR3 to 1, this pin becomes an

enable for the receiver. Therefore, if Auto Enables is ON

and the /DCD pin is High, the receiver is disabled; while

the /DCD pin is Low, the receiver is enabled.

Initialization. The initialization sequence for the receiver

in character-oriented mode is WR4 first, to select the

mode, then WR10 to modify it if necessary; WR6 and WR7

to program the sync characters; WR3 and WR5 to select

the various options. At this point the other registers are ini-

tialized as necessary. When all this is completed, the re-

ceiver is enabled by setting bit D0 of WR3 to a one. A sum-

mary is shown in Table 4-8. A detailed example of using

the SCC in 16-bit sync mode is available in the application

note “SCC in Binary Synchronous Communications.”

4

Note that with Auto Enables mode enabled, when /DCD

goes inactive, the receiver stops immediately and the

character being assembled is lost.

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

Table 4-7. Enabling and Disabling CRC

A

B

C

D

E

F

G

H

(Sync) (Data1) (Data2) (Data3) (CRC1) (CRC2) (Data) (Data)

Note: No CRC Calculation on "D"

Direction of Data

Coming into SCC

Shift

Receive

Delay

CRC

Notes

Stage

1

Register Data FIFO Register

H G F E D C B

H G F E D C

d

A

H G F E D

CPU Read

B

2

3

B

d

e

CPU Enables CR

C

D

H G F E D

CPU Read

B

C

CRC Calc on B

CRC Calc on C

H G F E

CPU Read

D*

CPU Disables CR

E

4

5

H G F

CPU Read

D

d

E

CPU Enables CR

CRC Calc is

Disabled on D

F

G

H

H G

E

F

e

CPU Read

F

CRC Calc on E

H

CPU Reads & Disca

G

CRC Calc on F

G

CRC Calc on F

Result latched in

Error FIFO †

Read RR1 D

H

Read H & Disca

Legend:

* Usually D is a end-of-message character indicator.

† The status is latched on the Error FIFO for each received byte. In the calculation of F,

the CRC error flag in the Error FIFO will be 0 for an error free message.

d = disabled

e = enabled

A B C D E F G H

A = SYNC

B - F = Data with E = CRC1 and F = CRC2

G and H are arbitrary data (Pad Character)

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Table 4-8. Initializing the Receiver in Character-Oriented Mode

Bit Number

Reg

WR4

D7

D6

D5

D4

D3

D2

D1

D0 Description

4

0

x

0

1

Select x1 clock, enable sync mode, & no parity

x=0 for 8-bit sync, x=1 for 16-bit sync

WR3

WR5

r

x

t

0

x

1

0

1

0

r

rx=# of Rx bits/char, No auto enable, enter Hunt,

Enable Rx CRC, No sync character load inhibit

d

d=inverse state of DTR pin, tx=# of Tx bits/char,

use CRC-16, r=inverse state of /RTS pin, CRC enable

sync character, lower byte

WR6

WR7

x

sync character, upper byte

WR10

c

0

i

0

s

c=CRC preset, NRZ data, i=idle line condition

s=size of sync character

WR3

WR5

WR0

r

d

1

x

t

0

x

0

1

0

1

0

r

0

1

0

Enable Receiver

Enable Transmitter

Reset CRC generator

receiver recognizes a sync character, it leaves Hunt mode;

one character time later the transmitter is enabled and

begins sending sync characters. Beyond this point the

receiver and transmitter are again completely independent,

except that the character boundaries are now aligned

(Figure 4-10).

4.3.3 Transmitter/Receiver Synchronization

The SCC contains a transmitter-to-receiver synchronization

function that is used to guarantee that the character

boundaries for the received and transmitted data are the

same. In this mode, the receiver is in Hunt and the

transmitter is idle, sending either all 1s or all 0s. When the

Direction of Message Flow

RxD

TxD

Sync

Receiver Leaves Hunt

Figure 4-10. Transmitter to Receiver Synchronization

There are several restrictions on the use of this feature in

the SCC. First, it only works with 6-bit, 8-bit or 16-bit sync

characters. The data character length for both the receiver

and the transmitter must be six bits with 6-bit sync charac-

ter, and eight bits with an 8-bit or 16-bit sync character. Of

course, the receive and transmit clocks must have the

same rate as well as the proper phase relationship.

A specific sequence of operations must be followed to syn-

chronize the transmitter to the receiver. Both the receiver

and transmitter must have been initialized for operation in

Synchronous mode sometime in the past, although this ini-

tialization need not be redone each time the transmitter is

synchronized to the receiver. The transmitter is disabled

by setting bit D3 of WR5 to 0. At this point the transmitter

will send continuous 1s. If it is required that continuous

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

0s be transmitted, the Send Break bit (D4) in WR5 is set

to 1. The transmitter is now idling but is still placed in the

transmitter to receiver synchronization mode. This is ac-

complished by setting the Loop Mode bit (D1) in WR10

and then enabling the transmitter by setting bit D3 of

WR5 to 1. At this point, the processor should set the Go

Active on Poll bit (D4) in WR10. The final step is to force

the receiver to search for sync characters. If the receiver

is currently disabled, the receiver enters Hunt mode

when it is enabled, by setting bit D0 of WR3 to 1. If the

receiver is already enabled, it is placed in Hunt mode by

setting bit D4 of WR3 to 1. Once the receiver leaves

Hunt mode, the transmitter is activated on the following

character boundary.

4.4 BIT-ORIENTED SYNCHRONOUS (SDLC/HDLC) MODE

Synchronous Data Link Control mode (SDLC) uses syn-

chronization characters similar to Bisync and Monosync

modes (such as flags and pad characters). It is a bit-orient-

ed protocol instead of a byte-oriented protocol. High level

Data Link Control (HDLC) is defined as CCITT, also EIAJ

and other standards; SDLC is one of the implementations

The basic format for SDLC is a frame (Figure 4-11). A

Frame is marked at the beginning and end by a unique flag

pattern. The flags enclose an address, control,

information, and frame check fields. There are many

different implementations of the SDLC protocol and many

do not use all of the fields. The SCC provides many

features to control how each of the fields is received and

transmitted.

®

made by IBM . The SDLC protocol uses the technique of

zero insertion to make all data transparent from SYNC

characters. All references to SDLC in this manual apply to

both SDLC and HDLC.

Frame

Beginning Flag

01111110

8 Bits

Information

Any Number

Of Bits

Ending Flag

01111110

8 Bits

Frame

Check

16 Bits

Address Control

8 Bits 8 Bits

Figure 4-11. SDLC Message Format

Frames of information are enclosed by a unique bit pattern

called a flag. The flag character has a bit pattern of

“01111110” (7E Hex). This sequence of six consecutive

ones is unique because all data between the opening and

closing flags is prohibited from having more than five con-

secutive 1s. The transmitter guarantees this by watching

the transmit data stream and inserting a 0 after five con-

secutive 1s, regardless of character boundaries. In turn,

the receiver searches the receive data stream for five con-

secutive 1s and deletes the next bit if it is a 0. Since the

SDLC mode does not use characters of defined length, but

rather works on a bit-by-bit basis, the 01111110 flag can

be recognized at any time. Inserted and removed 0s are

not included in the CRC calculation. Since the transmis-

sion of the flag character is excluded from the zero inser-

tion logic, its transmission is guaranteed to be seen as a

flag by the receiver. The zero insertion and deletion is

completely transparent to the user.

The two flags that delineate the SDLC frame serve as ref-

erence points when positioning the address and control

fields, and they initiate the transmission error check. The

ending flag indicates to the receiving station that the 16-

bits just received constitute the frame check (CRC; also re-

ferred to as FCS or Frame Check Sequence). The ending

flag can be followed by another frame, another flag, or an

idle. This means that when two frames follow one another,

the intervening flag may simultaneously be the ending flag

of the first frame and the beginning flag of the next frame.

This case is usually referred to as “Back-to-Back Frames”.

The SCC’s SDLC address field is eight bits long and is

used to designate which receiving stations accept a trans-

mitted message. The 8-bit address allows up to 254

(00000001 through 11111110) stations to be addressed

uniquely or a global address (11111111) is used to broad-

cast the message to all stations. Address 0 (00000000) is

usually used as a Test packet address.

Because of the zero insertion/deletion, actual bit length on

the transmission line may be longer than the number of

bits sent.

The control field of a SDLC frame is typically 8 bits, but can

be any length. The control field is transparent to the SCC

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Data Communication Modes

and is treated as normal data by the transmit and receive

logic.

times before writing data because ‘1s’ are transmitted

eight at a time and all eight must leave the Transmit Shift

register before a flag is loaded.

The information field is not restricted in format or content

and can be of any reasonable length (including zero). Its

maximum length is that which is expected to arrive at the

receiver error-free most of the time. Hence, the determina-

tion of maximum length is a function of the communication

channel’s error rate. Usually the upper layer of the protocol

specifies the packet size. Although the data is always writ-

ten/read in a given character size, the Residue Code fea-

ture provides the mechanism to read any number of bits at

the end of the frame that do not make up a full character.

This allows for the data field to be an arbitrary number of

bits long.

4

The ESCC has two improvements over the NMOS/CMOS

version to control the transmission of the flag at the begin-

ning of a frame. Additionally, the ESCC has improved fea-

tures to ease the handling of SDLC mode of operation, in-

cluding a function to deactivate the /RTS signal at the end

of the packet automatically. For these features, refer to the

next subsection, 4.4.1.2, “ESCC Enhancements for

SDLC Transmit.”

The number of bits per transmitted character is controlled

by bits D6 and D5 of WR5 and the way the data is format-

ted within the transmit buffer. The bits in WR5 allow the op-

tion of five, six, seven, or eight bits per character. In all cas-

es, the data must be right justified, with the unused bits

being ignored, except in the case of five bits per character.

When five bits per character are selected, the data may be

formatted before being written to the transmit buffer. This

allows transmission of one to five bits per character

(Table 4-2).

The frame check field is used to detect errors in the received

address, control and information fields. The method used to

test if the received data matches the transmitted data, is

called a Cyclic Redundancy Check (CRC). The SCC has an

option to select between two CRC polynomials, and in SDLC

mode only the CRC-CCITT polynomial is used because the

transmitter in the SCC automatically inverts the CRC before

transmission. To compensate for this, the receiver checks

the CRC result for the bit pattern 0001110100001111. This

is consistent with bit-oriented protocols such as SDLC,

HDLC, and ADCCP and the others.

An additional bit, carrying parity information, is automati-

cally appended to every transmitted character by setting

bit D0 of WR4 to 1. This bit is sent in addition to the number

of bits specified in WR4 or by the data format. The parity

sense is selected by bit D1 of WR4. Parity is not normally

used in SDLC mode as the overhead of parity is unneces-

sary due to the availability of the CRC.

There are two unique bit patterns in SDLC mode besides

the flag sequence. They are the Abort and EOP (End of

Poll) sequence. An Abort is a sequence of seven to thir-

teen consecutive 1s and is used to signal the premature

termination of a frame. The EOP is the bit pattern

11111110, which is used in loop applications as a signal to

a secondary station that it may begin transmission.

The SCC transmits address and control fields as normal

data and does not automatically send any address or con-

trol information. The value programmed into WR6 is used

by the receiver to compare the address of the received

frame (if address search mode is enabled), but WR6 is not

used by the transmitter. Therefore, the address is written

to the transmitter as the first byte of data in the frame.

SDLC mode is selected by setting bit D5 of WR4 to 1 and

bits D4, D3, and D2 of WR4 to 0. In addition, the flag se-

quence is written to WR7. Additional control bits for SDLC

mode are located in WR10 and WR7' (85X30).

The information field can be any number of characters

long. On the NMOS/CMOS version, the transmitter can in-

terrupt the CPU when the transmit buffer is empty. On the

ESCC, the transmitter can interrupt the CPU when the en-

try location of the Transmit FIFO is empty or when the

Transmit FIFO is completely empty. Also, the

NMOS/CMOS version can issue a DMA request when the

transmit buffer is empty, while the ESCC can issue a DMA

request when the entry location of the Transmit FIFO is

empty or when the Transmit FIFO is completely empty.

This allows the ESCC user to optimize the response to the

application requirements. Since the ESCC has a four byte

Transmit FIFO buffer, the Transmit Buffer Empty (TBE) bit

(D2 of RR0) will become set when the entry location of the

Transmit FIFO becomes empty. The TBE bit will reset

when a byte of data is loaded into the entry location of the

Transmit FIFO. For more details on this subject, refer to

4.4.1 SDLC Transmit

In SDLC mode, the transmitter moves characters from the

transmitter buffer (on the ESCC, four-byte transmitter

FIFO) to the Transmit Shift register, through the zero in-

serter and out to the TxD pin. The insertion of zero is com-

pletely transparent to the user. Zero insertion is done to all

transmitted characters except the flag and abort.

A SDLC frame must have the 01111110 (7E Hex) flag se-

quence transmitted before the data. This is done automat-

ically by the SCC by programming WR7 with 7EH as part

of the device initialization, enabling the transmitter, and

then writing data. If the SCC is programmed to idle Mark

(WR10 D3=1), special consideration must be taken to

transmit the opening flag. Ordinarily, it is necessary to re-

set the WR10 D3 to idle flag, wait 8-bit times, and then

write data to the transmitter. It is necessary to wait eight bit

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

Section 2.4.8 “Transmit Interrupts and Transmit Buffer

Empty bit”.

or to the command being issued, a Send Abort causes a

sequence of from eight to thirteen 1s to be transmitted.

The Send Abort command also clears the transmit

data FIFO.

The character length may be changed on the fly, but the

desired length must be selected before the character is

loaded into the Transmit Shift register from the transmit

data FIFO. The easiest way to ensure this is to write to

WR5 to change the character length before writing the

data to the transmit buffer. Note that although the charac-

ter can be any length, most protocols specify the ad-

dress/control field as 8-bit fields. The SCC receiver

checks the address field as 8-bit, if address search mode

is enabled.

When transmitting in SDLC mode, note that all data pass-

es through the zero inserter, which adds an extra five bit

times of delay between the Transmit Shift register and the

TxD Pin.

When the transmitter underruns (both the Transmit

FIFO and Transmit Shift register are empty), the state of

the Tx Underrun/EOM bit determines the action taken by

the SCC.

Only the CRC-CCITT polynomial is used in SDLC mode.

This is selected by setting bit D2 in WR5 to 0. This bit con-

trols the selection for both the transmitter and receiver.

The initial state of the generator and checker is controlled

by bit D7 of WR10. When this bit is set to 1, both the gen-

erator and checker have an initial value of all 1s, and if this

bit is set to 0, the initial values are all 0s.

If the Tx Underrun/EOM bit is set to 1 when the underrun

occurs, the transmitter sends flags without sending the

CRC. If this bit is reset to 0 when the underrun occurs, the

transmitter sends either the accumulated CRC followed by

flags, or an abort followed by flags, depending on the state

of the Abort/Flag on the Underrun bit in the WR10, bit D1.

A summary is shown in Table 4-9.

The SCC does not automatically preset the CRC genera-

tor, so this is done in software. This is accomplished by is-

suing the Reset Tx CRC command, which is encoded in

bits D7 and D6 of WR0. For proper results, this command

is issued while the transmitter is enabled and idling. If the

CRC is to be used, the transmit CRC generator is enabled

by setting bit D0 of WR5 to 1. The CRC is normally calcu-

lated on all characters between opening and closing flags,

so this bit is usually set to 1 at initialization and never

changed. On the 85X30 with Auto EOM Latch reset mode

enabled (WR7' bit D1=1), resetting of the CRC generator

is done automatically.

The Reset Tx Underrun/EOM Latch command is encoded

in bits D7 and D6 of WR0.

Table 4-9. ESCC Action Taken on Tx Underrun

Action taken by

Tx Underrun

ESCC upon

/EOM Latch Bit Abort/Flag transmit underrun

0

1

0

1

x

Sends CRC followed

by ﬂag

Sends abort followed

by ﬂag

Sends ﬂag

Enabling the CRC generator is not sufficient to control the

transmission of the CRC. In the SCC, this function is con-

trolled by Tx Underrun/EOM bit, which may be reset by the

processor and set by SCC. On the 85X30 with Auto EOM

Reset mode enabled (WR7' bit D1=1), resetting of the Tx

Underrun/EOM Latch is done automatically.

The SCC sets the Tx Underrun/EOM latch when the CRC

or abort is loaded into the shift register for transmission.

This event can cause an interrupt, and the status of the Tx

Underrun/EOM latch can be read in RR0.

Ordinarily, a frame is terminated with a CRC and a flag, but

the SCC may be programmed to send an abort and a flag

in place of the CRC. This option allows the SCC to abort a

frame transmission in progress if the transmitter is acci-

dentally allowed to underrun. This is controlled by the

Abort/Flag on Underrun bit (D2) in WR10. When this bit is

set to 1, the transmitter will send an abort and a flag in

place of the CRC when an underrun occurs. The frame is

terminated normally with a CRC and a flag if this bit is 0.

Resetting the Tx Underrun/EOM latch is done by the pro-

cessor via the command encoded in bits D7 and D6 of

WR0. On the 85X30, this also can be accomplished by set-

ting WR7' bit D1 for Auto Tx Underrun/EOM Latch Reset

mode enabled. For correct transmission of the CRC at the

end of a frame, this command must be issued after the first

character is written to the SCC but before the transmitter

underruns after the last character written to the SCC. The

command is usually issued immediately after the first char-

acter is written to the SCC so that the abort or CRC is sent

if an underrun occurs inadvertently. The Abort/Flag on Un-

derrun bit (D2) in WR10 is usually set to 1 at the same time

as the Tx Underrun/EOM bit is reset so that an abort is

sent if the transmitter underruns. The bit is then set to 0

The SCC is also able to send an abort by a command from

the processor. When the Send Abort command is issued

in WR0, the transmitter sends eight consecutive 1s and

then idles. Since up to five consecutive 1s may be sent pri-

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near the end of the frame to allow the correct transmission

of the CRC.

Deeper Transmit FIFO: The ESCC has a four byte deep

Transmit FIFO, where the NMOS/CMOS version has a

one byte deep transmit buffer. To maximize the system’s

performance, there are two modes of operation for the

transmit interrupt and DMA request, which are pro-

grammed by bit D5 of WR7'.

In this paragraph the term “completely sent” means shifted

out of the Transmit Shift register, not shifted out of the zero

inserter, which is an additional five bit times of delay. In

SDLC mode, if the transmitter is disabled during transmis-

sion of a character, that character will be “completely sent.”

This applies to both data and flags. However, if the trans-

mitter is disabled during the transmission of the CRC, the

16-bit transmission will be completed, but the remaining

bits are from the Flag register rather than the remainder of

the CRC.

4

The ESCC sets WR7' bit D5 to 1 following a hardware or

software reset. This is done to provide maximum compat-

ibility with existing SCC designs. In this mode, the ESCC

generates the transmit buffer empty interrupt and DMA

transmit request when the Transmit FIFO is completely

empty. Interrupt driven systems can maximize efficiency

by writing four bytes for each entry into the Transmit Inter-

rupt Service Routine (TISR), filling the Transmit FIFO with-

out having to check any status bits. Since the TBE status

bit is set if the entry location of the FIFO is empty, this bit

can be tested at any time if more data is written. Applica-

tions requiring software compatibility with the

NMOS/CMOS version can test the TBE bit in the TISR af-

ter each data write to determine if more data can be writ-

ten. This allows a system with an ESCC to minimize the

number of transmit interrupts, but not overflow SCC sys-

tems. DMA driven systems originally designed for the SCC

can use this mode to reassert the DMA request for more

data after the first byte written to the FIFO is loaded to the

Transmit Shift register. Consequently, any subsequent re-

assertion allows the DMA sufficient time to detect the High-

to-Low edge.

The initialization sequence for the transmitter in SDLC

mode is:

1. WR4 selects the mode.

2. WR10 modifies it if necessary.

3. WR7 programs the flag.

4. WR3 and WR5 selects the various options.

At this point the other registers should be initialized as nec-

essary. When all of this is complete, the transmitter may be

enabled by setting bit D3 of WR5 to 1. Now that the trans-

mitter is enabled, the CRC generator may be initialized by

issuing the Reset Tx CRC Generator command in WR0.

4.4.1.1 Modem Control signals related to SDLC

Transmit

If WR7' D5 is reset to 0, the transmit buffer empty interrupt

and DMA request are generated when the entry location of

the FIFO is empty. Therefore, if more than one byte is re-

quired to fill the entry location of the FIFO, the ESCC gen-

erates interrupts or DMA requests until the entry location

of the FIFO is filled. The transmit DMA request pin (either

/WAIT//REQ or /DTR//REQ) goes inactive after each data

transfer, then goes active again and, consequently, gener-

ates a High-to-Low edge for each byte. Edge triggered

DMA should be enabled before the transmit DMA function

is enabled in the ESCC to guarantee that the ESCC does

not generate the edge before the DMA is ready.

There are two modem control signals associated with the

transmitter provided by the SCC. The /RTS pin is a simple

output that carries the inverted state of the RTS bit (D1) in

WR5. The /CTS pin is ordinarily a simple input to the CTS

bit in RR0. However, if Auto Enables mode is selected, this

pin becomes an enable for the transmitter. If Auto Enables

is on and the /CTS pin is High, the transmitter is disabled.

The transmitter is enabled if the /CTS pin is Low.

4.4.1.2 ESCC Enhancements for SDLC Transmit

The ESCC has the following enhancements available in

the SDLC mode of operation which can reduce CPU over-

head dramatically. These features are:

CRC takes priority over data: On the NMOS/CMOS

version, the data has higher priority over CRC data. Writ-

ing data before the Tx interrupt, after loading the closing

flag into the Transmit Shift register, terminates the packet

illegally. In this case, CRC byte(s) are replaced with Flag

or Sync patterns, followed by the data written. On the ES-

CC, CRC has priority over the data. Consequently, after

the Underrun/EOM (End of message) interrupt occurs,

the ESCC accepts the data for the next packet without

fear of collapsing the packet. On the ESCC, if data was

written during the time period described above, the TBE

bit (bit D2 of RR0) is NOT set; even if the 2nd TxIP is

guaranteed to set when the flag/sync pattern is loaded

into the Transmit Shift register (Section 2.4.8). For the

detailed timing on this, refer to Figures 2-17 and 2-18.

■ Deeper Transmit FIFO (Four Bytes)

■ CRC takes priority over the data

■ Auto EOM Reset (WR7' bit D1)

■ Auto Tx Flag (WR7' bit D0)

■ Auto RTS Deactivation (WR7' bit D2)

■ TxD pin forced High after closing flag in NRZI mode

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

Hence, on the ESCC, there is no need to wait for the 2nd

TxIP bit to set before writing data for the next packet

which reduces the overhead.

If this feature is enabled by setting bit D2 of WR7', and when

WR5 bit D1 is reset during the transmission of a SDLC

frame, the deassertion of the /RTS pin is delayed until the

last bit of the closing flag clears the TxD pin. The /RTS pin

is deasserted after the rising edge of the transmit clock cycle

on which the last bit of the closing flag is transmitted. This

implies that the ESCC is programmed for Flag on Underrun

(WR10 bit D2=1) for the /RTS pin to deassert at the end of

the frame. (Otherwise, the deassertion occurs when the

next flag is transmitted). This feature works independently

of the programmed transmitter idle state. In Synchronous

modes other than SDLC, the /RTS pin immediately follows

the state programmed into WR5 D1. Note that if the /RTS

pin is connected to one of the general purpose inputs (/CTS

or /DCD), it can be used to generate an external status in-

terrupt when a frame is completely transmitted.

Auto EOM Reset (WR7' bit D1): As described above, the

Tx Underrun/EOM Latch has to be reset before the Trans-

mit Shift register completes shifting out the last character,

but after first character has been written. One of the ways

to reset it is for the CPU to issue the “Reset Tx Under-

run/EOM Latch” command. The other method to accom-

plish it is by the “Automatic EOM Latch Reset feature” by

setting bit D1 in WR7', which is one of the enhancements

made to the ESCC. By setting this bit to one, it eliminates

the need for the CPU command. In this mode, the CRC

generator is automatically reset at the start of every pack-

et, without the CPU command. Hence, it is not required to

reset the CRC generator prior to writing data into the ES-

CC. This is particularly valuable to a DMA driven system

where issuing CPU commands while the DMA is transfer-

ring data is difficult. Also, it is very useful if the data rate is

very high and the CPU may not be able to issue the com-

mand on time.

NRZI forced High after closing flag: On the

CMOS/NMOS version of the SCC in the SDLC mode of

operation with NRZI mode of encoding and mark idle

(WR10 bit D6=0, D5=1, D3=1), the state of the TxD pin af-

ter transmission of the closing flag is undetermined, de-

pending on the last data sent. With the ESCC in the same

operation mode (SDLC, NRZI, with mark idle), the TxD pin

is automatically forced High on the falling edge of the TxC

of the last bit of the closing flag, and then the transmitter

goes to the mark idle state.

Auto Tx Flag (WR7' bit D0): With the NMOS/CMOS ver-

sion of the SCC, in order to accomplish Mark idle, it is re-

quired to enable the transmitter as Mark idle; then re-pro-

gram to Flag idle before writing first data, and then

reprogram again to mark idle as described above. Normal-

ly, during mark idle, the transmitter sends continuous

flags, but the ESCC can idle MARK under program control.

By setting the Mark/Flag idle bit (D3) in WR10 to 1, the

transmitter sends continuous 1s in place of the idle flags.

The closing flag always transmits correctly even when this

mode is selected. Normally, it is necessary to reset WR10

D3 to 0 before writing data for the next frame. However, on

the ESCC, if WR7' bit D0 is set to 1, an opening flag is

transmitted automatically and it is not necessary for the

CPU to turn the Mark Idle feature on and off between

frames.

There are several different ways for a transmitter to go into

the idle state. In each of the following cases, the TxD pin

is forced High when the mark idle condition is reached; da-

ta, CRC (2 bytes), flag and idle; data, flag and idle; data,

abort (on underrun) and idle; data, abort (by command)

and idle; idle, flag and command to idle mark. The force

High feature is disabled when the mark idle bit is reset

(programmed as mark idle). This feature is used in combi-

nation with the automatic SDLC opening flag transmission

feature, WR7' bit D0=1, to assure that data packets are

properly formatted. When these features are used togeth-

er, it is not necessary for the CPU to issue any commands

after sending a closing flag in combination with NRZI data

encoding. (On the NMOS/CMOS version, this is accom-

plished by channel reset, followed by re-initializing the

channel). If WR7' bit D0 is reset, like in the NMOS/CMOS

version, it is necessary to reset the mark idle bit (WR10, bit

D3) to enable flag transmission before a SDLC packet is

transmitted.

Note: When this mode in not in effect (WR7' D0=0), the

Mark/Flag idle bit is clear to 0, allowing a flag to be trans-

mitted before data is written to the transmit buffer. Care

must be exercised in doing this because the continuous 1s

are transmitted eight at a time and all eight must leave the

Transmit Shift register. This allows a flag to be loaded into

it before the first data is written to the Transmit FIFO.

Auto RTS Deactivation (WR7' bit D2): Some applica-

tions require toggling the modem signal to indicate the end

of the packet. With the NMOS/CMOS version, this requires

intensive CPU support; the CPU needs time to determine

whether or not the last bit of the closing flag has left the

TxD pin. The ESCC has a new feature to deactivate the

/RTS signal when the last bit of the closing flag clears the

TxD pin.

4.4.2 SDLC Receive

The receiver in the SCC always searches the receive data

stream for flag characters in SDLC mode. Ordinarily, the

receiver transfers all received data between flags to the re-

ceive data FIFO. However, if the receiver is not in Hunt

mode no data is received. The receiver is in Hunt mode

when first enabled, or the receiver is placed in Hunt mode

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by the processor issuing the Enter Hunt mode command in

WR3. This bit (D4) is a command, and writing a 0 to it has

no effect. The Hunt status of the receiver is reported by the

Sync/Hunt bit in RR0.

The receiver automatically enters Hunt mode if an abort is

received. Because the receiver always searches the

receive data stream for flags, and automatically enters

Hunt Mode when an abort is received, the receiver always

handles frames correctly. The Enter Hunt Mode command

should never be needed. The SCC drives the /SYNC pin

Low to signal that a flag has been recognized. The timing

for the /SYNC signal is shown in Figure 4-12.

4

Sync/Hunt is one of the possible sources of external/status

interrupts, with both transitions causing an interrupt. This

is true even if the Sync/Hunt bit is set as a result of the pro-

cessor issuing the Enter Hunt mode command.

/RTxC

PCLK

/SYNC

State Changes in One

/RTxC Clock Cycle

Figure 4-12. /SYNC as an Output

The SCC assumes the first byte in an SDLC frame is the

address of the secondary station for which the frame is in-

tended. The SCC provides several options for handling

this address.

The number of bits per character is controlled by bits D7

and D6 of WR3. Five, six, seven, or eight bits per character

may be selected via these two bits. The data is right-justi-

fied in the receive buffer. The SCC merely takes a snap-

shot of the receive data stream at the appropriate times, so

the “unused” bits in the receive buffer are only the bits fol-

lowing the character.

If the Address Search Mode bit (D2) in WR3 is set to 0, the

address recognition logic is disabled and all received

frames are transferred to the receive data FIFO. In this

mode the software must perform any address recognition.

An additional bit carrying parity information is selected by

setting bit D6 of WR4 to 1. This also enables parity in the

transmitter. The parity sense is selected by bit D1 of WR4.

Parity is not normally used in SDLC mode.

If the Address Search Mode bit is set to 1, only those

frames whose address matches the address programmed

in WR6 or the global address (all 1s) will be transferred to

the receive data FIFO.

The character length can be changed at any time before

the new number of bits have been assembled by the

receiver. Care should be exercised, however, as

unexpected results may occur. A representative example,

switching from five bits to eight bits and back to five bits, is

shown in Figure 4-13.

The address comparison is across all eight bits of WR6 if

the Sync Character Load inhibit bit (D1) in WR3 is set to 0.

The comparison may be modified so that only the four

most significant bits of WR6 match the received address.

This mode is selected by setting the Sync Character Load

inhibit bit to 1. In this mode, however, the address field is

still eight bits wide. The address field is transferred to the

receive data FIFO in the same manner as data. It is not

treated differently than data.

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

Receive Data Buffer

5 Bits

8 Bits

5 Bits

8

7

6

5

4

3

8

2

7

1

6

Time

13 12 11 10 9

Change from Five to Eight

21 20 19 18 17 16 15 14

29 28 27 26 25 24 23 22

34 33 32 31 30 29 28 27

39 38 37 36 35 34 33 32

Change from Eight to Five

Figure 4-13. Changing Character Length

Most bit-oriented protocols allow an arbitrary number of

bits between opening and closing flags. The SCC allows

for this by providing three bits of Residue Code in RR1.

These indicate which bits in the last three bytes transferred

from the receive data FIFO by the processor are actually

valid data bits (and not part of the frame check sequence

or CRC). Table 4-10 gives the meanings of the different

codes for the four different character length options. The

valid data bits are right-justified, meaning, if the number of

valid bits given by the table is less than the character

length, then the bits that are valid are the right-most or

least significant bits. It should also be noted that the Resi-

due Code is only valid at the time when the End of Frame

bit in RR1 is set to 1.

Table 4-10. Residue Codes

Bits in

Previous Byte

Bits in Second

Previous Byte

Bits in Third

Previous Byte

Residue Code

2

1

0

8B/C 7B/C 6B/C 5B/C

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

0

3

4

5

6

7

8

1

2

3

4

5

6

7

0

1

2

3

4

0

1

8

7

5

6

2

3

4

5

As indicated in the table, these bits allow the processor to

determine those bits in the information (and not CRC) field.

This allows transparent retransmission of the received

frame. The Residue Code bits do not go through a FIFO,

so they change in RR1 when the last character of the

frame is loaded into the receive data FIFO. If there are any

characters already in the receive data FIFO the Residue

Code is updated before they are read by the processor.

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As an example of how the codes are interpreted, consider

the case of eight bits per character and a residue code of

101. The number of valid bits for the previous, second

previous, and third previous bytes are 0, 7, and 8,

respectively. This indicates that the information field (I-

field) boundary falls on the second previous byte as shown

in Figure 4-14.

4

I - Field

7-Bits

CRC Field

Third Previous

Byte

Second Previous

Byte

Figure 4-14. Residue Code 101 Interpretation

A frame is terminated by the detection of a closing flag. are never transferred to the receive data FIFO and are

Upon detection of the flag the following actions take place:

the contents of the Receive Shift Register are transferred

to the receive data FIFO; the Residue Code is latched, the

CRC Error bit is latched; the End of Frame upon reaching

the top of the FIFO can cause a special receive condition.

The processor then reads RR1 to determine the result of

the CRC calculation and the Residue Code.

not recoverable.

On the ESCC, an enhancement has been made allowing

the 2nd byte of the CRC to be received completely. This

feature is useful when the application requires the 2nd

CRC byte as data. For example, applications which oper-

ate in transparent mode or protocols using the error check-

ing mechanism other than CRC-CCITT (like 32-bit CRC).

Only the CRC-CCITT polynomial is used for CRC calcula-

tions in SDLC mode, although the generator and checker

can be preset to all 1s or all 0s. The CRC-CCITT polyno-

mial is selected by setting bit D2 of WR5 to 0. Bit D7 of

WR10 controls the preset value. If this bit is set to 1, the

generator and checker are preset to 1s, and if this bit is re-

set, the generator and checker are preset to all 0s.

Note the following about SCC CRC operation:

■ The normal CRC checking mechanism involves

checking over data and CRC characters. If the division

remainder is 0, there is no CRC error.

■ SDLC is different. The CRC generator, when receiving a

correct frame, has a fixed, non-zero remainder. The

actual remainder in the receive CRC calculation is

checked against this fixed value to determine if a CRC

error exists.

The receiver expects the CRC to be inverted before trans-

mission, so it checks the CRC result against the value

0001110100001111. The SCC presets the CRC checker

whenever the receiver is in Hunt mode or whenever a flag

is received, so a CRC reset command is not necessary.

However, the CRC checker can be preset by issuing the

Reset CRC Checker command in WR0.

A frame is terminated by a closing flag. When the SCC rec-

ognizes this flag:

■ The contents of the Receive Shift register are

The CRC checker is automatically enabled for all data be-

tween the opening and closing flags by the SCC in SDLC

mode, and the Rx CRC Enable bit (D3) in WR3 is ignored.

The result of the CRC calculation for the entire frame is

valid in RR1 only when accompanied by the End of Frame

bit set in RR1. At all other times, the CRC Error bit in RR1

should be ignored by the processor.

transferred to the receive data FIFO.

■ The Residue Code is latched, the CRC Error bit is

latched in the status FIFO and the End of Frame bit is set

in the receive status FIFO.

The End of Frame bit, upon reaching the exit location of

the FIFO, will cause a special receive condition. The pro-

cessor may then read RR1 to determine the result of the

CRC calculation as well as the Residue Code. If either

the Rx Interrupt on Special Condition Only or the Rx In-

terrupt on First Character or Special Condition modes are

On the NMOS/CMOS version, care must be exercised

so that the processor does not attempt to use the CRC

bytes that are transferred as data, because not all of the

bits are transferred properly. The last two bits of CRC

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4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

selected, the processor must issue an Error Reset com-

mand in WR0 to unlock the Receive FIFO.

Up to two modem control signals associated with the re-

ceiver are available in SDLC mode:

In addition to searching the data stream for flags, the re-

ceiver in the SCC also watches for seven consecutive 1s,

which is the abort condition. The presence of seven con-

secutive 1s is reported in the Break/Abort bit in RR0. This

is one of the possible external/status interrupts, so transi-

tions of this status may be programmed to cause inter-

rupts. Upon receipt of an abort the receiver is forced into

Hunt mode where it looks for flags. The Hunt status is also

a possible external/status condition whose transition may

be programmed to cause an interrupt. The transitions of

these two bits occur very close together, but either one or

two external/status interrupts may result. The abort condi-

tion is terminated when a 0 is received, either by itself or

as the leading 0 of a flag. The receiver does not leave Hunt

mode until a flag has been received, so two discrete exter-

nal/status conditions occur at the end of an abort. An abort

received in the middle of a frame terminates the frame re-

ception, but not in an orderly manner because the charac-

ter being assembled is lost.

■ The /DTR//REQ pin carries an inverted state of the DTR

bit (D7) in WR5 unless this pin has been programmed to

carry a DMA Request signal.

■ The /DCD pin is ordinarily a simple input to the DCD bit

in RR0. However, if the Auto Enables mode is selected

by setting bit D5 of WR3 to 1, this pin becomes an

enable for the receiver. That is, if Auto Enables is on and

the /DCD pin is High, the receiver is disabled. While the

/DCD pin is Low, the receiver is enabled.

SDLC Initialization. The initialization sequence for SDLC

mode is WR4 to select SDLC mode first, WR3 and WR5 to

select the various options, WR7 to program flag, and then

WR6 for the receive address. At this point the other regis-

ters should be initialized as necessary. When all this is

completed the receiver is enabled by setting bit D0 of WR3

to a one. A summary is shown in Table 4-11.

Table 4-11. Initializing in SDLC Mode

Bit #

Reg

D7 D6 D5 D4 D3 D2 D1 D0

Description

WR4

0

1

0

Select x1 clock,

SDLC mode, enable sync mode

WR3

r

x

0

1

0

rx=# of Rx bits/char, No auto enable, enter Hunt.

Enable Rx CRC, Address Search, No sync character

load inhibit

WR5

WR7

d

0

t

x

0

1

0

1

0

1

r

1

0

d=inverse of DTR pin, tx=# of Tx bits/char, use SDLC CRC,

r=inverse state of /RTS pin, CRC enable

SDLC Flag

1

WR6

WR15

x

1

Receiver secondary address

Enable access to new register

WR7'

0

1

d

1

r

1

Enable extended read, Tx INT on FIFO empty,

d=REQUEST timing mode, Rx INT on 4 char, r=RTS

deactivation, auto EOM reset, auto ﬂag tx CRC preset to

zero, NRZ data,i=idle line

WR10

0

i

0

CRC preset to zero, NRZ data, i=idle line

WR3

WR5

WR0

r

d

1

x

t

0

x

0

1

0

1

0

1

0

r

0

1

0

Enable Receiver

Enable Transmitter

Reset CRC generator

Note: The receiver searches for synchronization when it is in Note: The SYNC/HUNT bit in RR0 reports the Hunt Status, and

Hunt mode. In this mode, the receiver is idle except for searching an interrupt is generated upon transitions between the Hunt state

the data stream for a flag match.

and the Sync state.

Note: When the receiver detects a flag match it achieves syn- Note: The SCC will drive the /SYNC pin Low for one receive clock

chronization and interprets the following byte as the address field. cycle to signal that the flag has been received.

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Data Communication Modes

Summarizing the operation; data is received, assembled,

and loaded into the eight-byte FIFO before being trans-

ferred to memory by the DMA controller. When a flag is re-

ceived at the end of an SDLC frame, the frame byte count

from the 14-bit counter and five status bits are loaded into

the status FIFO for verification by the CPU. The CRC check-

er is automatically reset in preparation for the next frame

which can begin immediately. Since the byte count and sta-

tus are saved for each frame, the message integrity can be

verified at a later time. Status information for up to 10 frames

can be stored before a status FIFO overrun occurs.

4.4.3 SDLC Frame Status FIFO

This feature is not available on the NMOS version.

On the CMOS version and the ESCC, the ability to receive

high speed back-to-back SDLC frames is maximized by a

10-bit deep by 19-bit wide status FIFO. When enabled

(through WR15, bit D2), it provides a DMA the ability to

continue to transfer data into memory so that the CPU can

examine the message later. For each SDLC frame, a 14-

bit byte count and five status/error bits are stored. The byte

count and status bits are accessed through Read Regis-

ters 6 and 7. Read Registers 6 and 7 are only accessible

when the SDLC FIFO is enabled. The 10x19 status FIFO

is separate from the 8-byte Receive Data FIFO.

4

If a frame is terminated with an ABORT, the byte count will

be loaded to the status FIFO and the counter reset for the

next frame.

When the enhancement is enabled, the status in Read

Register 1 (RR1) and byte count for the SDLC frame is

stored in the 10 x 19 bit status FIFO. This allows the DMA

controller to transfer the next frame into memory while the

CPU verifies the message was properly received.

FIFO Detail. For a better understanding of details of the

FIFO operation, refer to the block diagram in Figure 4-15.

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Data Communication Modes

4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

Frame Status FIFO Circuitr

Reset on Flag Detect

Increment on Byte DET

Enable Count in SDLC

SCC Status Reg

Residue Bits(3)

Overrun, CRC Error

RR1

Byte Counter

End of Frame Signal

Status Read Comp

5 Bits

14 Bits

FIFO Array

10 Deep by 19 Bits Wide

Tail Pointer

4-Bit Counter

Head Pointer

4-Bit Counter

4-Bit Comparator

Over

Equal

5 Bits

EOF = 1

6 Bits

8 Bits

EN

6-Bit MUX

2 Bits

6 Bits

RR1

Bit 7 Bit 6 Bits 5-0

RR6

FIFO Enable

Interface

to SCC

WR(15) Bit 2

Set Enables

Status FIFO

RR7 D5-D0 + RR6 D7 - D0

Byte Counter Contains 14 bits

for a 16 KByte maximum count.

RR7 D6

FIFO Data available status bit Status Bit set to 1

When reading from FIFO.

RR7 D7

FIFO Overflow Status Bit

MSB pf RR(7) is set on Status FIFO overflow

In SDLC Mode the following definitions apply.

- All Sent bypasses MUX and equals contents of SCC Status Register.

- Parity Bits bypasses MUX and does the same.

- EOF is set to 1 whenever reading from the FIFO.

Figure 4-15. SDLC Frame Status FIFO (N/A on NMOS)

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Data Communication Modes

Enable/Disable. The frame status FIFO is enabled when

WR15 bit D2 is set and the CMOS/ESCC is in the

SDLC/HDLC mode. Otherwise, the status register con-

tents bypass the FIFO and go directly to the bus interface

(the FIFO pointer logic is reset either when disabled or via

a channel or Power-On Reset). The FIFO mode is dis-

abled on power-up (WR15 D2 is set to 0 on reset). The

effects of backward compatibility on the register set are

that RR4 is an image of RR0, RR5 is an image of RR1,

RR6 is an image of RR2 and RR7 is an image of RR3. For

the details of the added registers, refer to Chapter 5. The

status of the FIFO Enable signal can be obtained by read-

ing RR15 bit D2. If the FIFO is enabled, the bit is set to 1;

otherwise, it is reset.

Since not all status bits are stored in the FIFO, the All

Sent, Parity, and EOF bits bypass the FIFO. The status

bits sent through the FIFO are Residue Bits (3), Overrun,

and CRC Error.

4

The sequence for proper operation of the byte count and

FIFO logic is to read the register in the following order:

RR7, RR6, and RR1 (reading RR6 is optional). Additional

logic prevents the FIFO from being emptied by multiple

reads from RR1. The read from RR7 latches the FIFO

empty/full status bit (D6) and steers the status multiplexer

to read from the CMOS/ESCC megacell instead of the sta-

tus FIFO (since the status FIFO is empty). The read from

RR1 allows an entry to be read from the FIFO (if the FIFO

was empty, logic was added to prevent a FIFO underflow

condition).

Read Operation. When WR15 bit D2 is set and the FIFO

is not empty, the next read to any of status register RR1 or

the additional registers RR7 and RR6 is from the FIFO.

Reading status register RR1 causes one location of the

FIFO to be emptied, so status is read after reading the byte

count, otherwise the count is incorrect. Before the FIFO

underflows, it is disabled. In this case, the multiplexer is

switched to allow status to read directly from the status

register, and reads from RR7 and RR6 contain bits that are

undefined. Bit D6 of RR7 (FIFO Data Available) is used to

determine if status data is coming from the FIFO or directly

from the status register, since it is set to 1 whenever the

FIFO is not empty.

Write Operation. When the end of an SDLC frame (EOF)

has been received and the FIFO is enabled, the contents

of the status and byte-count registers are loaded into the

FIFO. The EOF signal is used to increment the FIFO. If the

FIFO overflows, the RR7 bit D7 (FIFO Overflow) is set to

indicate the overflow. This bit and the FIFO control logic is

reset by disabling and re-enabling the FIFO control bit

(WR15 bit 2). For details of FIFO control timing during an

SDLC frame, refer to Figure 4-16.

4

0

1

2

3

5

6

7

0

F

1

2

3

5

6

7

0

F

0F0 A

D

D 0D0 D

C

F

A

D

D 0D0 D

C

Internal Byte Strobe

Increments Counter

Internal Byte Strobe

Increments Counter

Don't Load

Counter On

1st Flag

Reset Byte

Counter Here

Reset

Byte Counter

Reset

Byte Counter

Load Counter

Into FIFO and

Increment PTR

Byte Counter

Load Counter

Into FIFO And

Increment PTR

Figure 4-16. SDLC Byte Counting Detail

SDLC Status FIFO Anti-Lock Feature (ESCC only).

When the Frame Status FIFO is enabled and the ESCC

is programmed for Special Receive Condition Only

(WR1 D4=D3=1), the data FIFO is not locked when a

character with End of Frame status is read. When a char-

acter with the EOF status reaches the top of the FIFO,

an interrupt with a vector for receive data is generated.

The command Reset Highest IUS must be issued at the

end of the interrupt service routine regardless of whether

an interrupt acknowledge cycle had been executed (hard-

ware or software). This allows a DMA to complete a trans-

fer of the received frame to memory and then interrupt the

CPU that a frame has been completed without locking the

FIFO. Since in the Receive Interrupt on Special Condition

Only mode the interrupt vector for receive data is not used,

it is used to indicate that the last byte of a frame has been

read from the Receive FIFO. This eliminates having to

read the frame status (CRC and other status is stored in

the status FIFO with the frame byte count).

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Data Communication Modes

4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

When a character with a special receive condition other

than EOF is received (receive overrun, or parity), a special

receive condition interrupt is generated after the character

is read from the FIFO and the Receive FIFO is locked until

the Error Reset command is issued.

There are also restrictions as to when and how a second-

ary station physically becomes part of the loop.

A secondary station that has just powered up must monitor

the loop, without the one-bit-time delay, until it recognizes

an EOP. When an EOP is recognized the one-bit-time de-

lay is switched on. This does not disturb the loop because

the line is marking idle between the time that the controller

sends the EOP and the time that it receives the EOP back.

The secondary station that has gone on-loop cannot place

a message on the loop until the next time that an EOP is

issued by the controller. A secondary station goes off loop

in a similar manner. When given a command to go off-loop,

the secondary station waits until the next EOP to remove

the one-bit-time delay.

4.4.4 SDLC Loop Mode

The SCC supports SDLC Loop mode in addition to normal

SDLC. SDLC Loop mode is very similar to normal SDLC

but is usually used in applications where a point-to-point

network is not appropriate (for example, Point-of-Sale ter-

minals). In an SDLC Loop, there is a primary controller that

manages the message traffic flow on the loop and any

number of secondary stations. In SDLC Loop mode, the

SCC operating in regular SDLC mode can act as the pri-

mary controller.

To operate the SCC in SDLC Loop mode, the SCC must

first be programmed just as if normal SDLC were to be

used. Loop mode is then selected by writing the appropri-

ate control word in WR10.

A secondary station in an SDLC Loop is always listening

to the messages being sent around the loop, and in fact

must pass these messages to the rest of the loop by re-

transmitting them with a one-bit-time delay.

The SCC is now waiting for the EOP so that it can go on

loop. While waiting for the EOP, the SCC ties TxD to RxD

with only the internal gate delays in the signal path. When

the first EOP is recognized by the SCC, the

Break/Abort/EOP bit is set in RR0, generating an Exter-

nal/Status interrupt (if so enabled). At the same time, the

On-Loop bit in RR10 is set to indicate that the SCC is in-

deed on-loop, and a one-bit time delay is inserted in the

TxD to the RxD path.

The secondary station can place its own message on the

loop only at specific times. The controller signals that sec-

ondary stations may transmit messages by sending a spe-

cial character, called an EOP (End of Poll), around the

loop. The EOP character is the bit pattern 11111110.

When a secondary station has a message to transmit and

recognizes an EOP on the line, it changes the last binary

1 of the EOP to a 0 before transmission. This has the effect

of turning the EOP into a flag pattern. The secondary sta-

tion now places its message on the loop and terminates its

message with an EOP. Any secondary stations further

down the loop with messages to transmit can append their

messages to the message of the first secondary station by

the same process.

The SCC is now on-loop but cannot transmit a message

until a flag and the next EOP are received. The require-

ment that a flag be received ensures that the SCC cannot

erroneously send messages until the controller ends the

current polling sequence and starts another one.

If the CPU in the secondary station with the SCC needs to

transmit a message, the Go-Active-On-Poll bit in WR10 is

set. If this bit is set when the EOP is detected, the SCC

changes the EOP to a flag and starts sending another flag.

The EOP is reported in the Break/Abort/EOP bit in RR0

and the CPU writes its data bytes to the SCC, just as in

normal SDLC frame transmission. When the frame is com-

plete and CRC has been sent, the SCC closes with a flag

and reverts to One-Bit-Delay mode. The last zero of the

flag, along with the marking line echoed from the RxD pin,

form an EOP for secondary stations further down the loop.

All secondary stations without messages to send merely

echo the incoming messages and are prohibited from

placing messages on the loop, except upon recognizing

an EOP.

SDLC Loop mode is quite similar to normal SDLC mode

except that two additional control bits are used. Writing a 1

to the Loop Mode bit in WR10 configures the SCC for Loop

mode. Writing a 1 to the Go Active on Poll bit in the same

register normally causes the SCC to change the next EOP

into a flag and then begin transmitting on loop. However,

when the SCC first goes on loop it uses the first EOP as a

signal to insert the one-bit delay, and doesn’t begin trans-

mitting until it receives the second EOP. There are also

two additional status bits in RR10, the On-Loop bit and the

Loop-Sending bit.

While the SCC is actually transmitting a message, the

loop-sending bit in R10 is set to indicate this.

If the Go-Active-On-Poll bit is not set at the time the EOP

passes by, the SCC cannot send a message until a flag

(terminating the current polling sequence) and another

EOP are received.

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Data Communication Modes

If SDLC loop is deselected, the SCC is designed to exit

from the loop gracefully. When the SDLC Loop mode is de-

selected by writing to WR10, the SCC waits until the next

polling cycle to remove the one-bit time delay.

Before Loop mode is selected, both the receiver and trans-

mitter have to be completely initialized for SDLC operation.

Once this is done, Loop mode is selected by setting bit D1

of WR10 to 1. At this point, the SCC connects TxD to RxD

with only gate delays in the path. At the same time, a flag

is loaded into the Transmit Shift register and is shifted to

the end of the zero inserter, ready for transmission. The

SCC remains in this state until the Go-Active-On-Poll bit

(D4) in WR10 is set to 1. When this bit is set to 1, the re-

ceiver begins looking for a sequence of seven consecutive

1s, indicating either an EOP or an idle line. When the re-

ceiver detects this condition, the Break/Abort bit in RR0 is

set to 1, and a one-bit time delay is inserted in the path

from RxD to TxD.

4

If a polling cycle is in progress at the time the command is

written, the SCC finishes sending any message that it is

transmitting, ends with an EOP, and disconnects TxD from

RxD. If no message was in progress, the SCC immediately

disconnects TxD from RxD.

Once the SCC is not sending on the loop, exiting from the

loop is accomplished by setting the Loop Mode bit in

WR10 to 0, and at the same time writing the Abort/Flag on

Underrun and Mark/Flag idle bits with the desired values.

The SCC will revert to normal SDLC operation as soon as

an EOP is received, or immediately if the receiver is al-

ready in Hunt mode because of the receipt of an EOP.

The On-Loop bit in RR10 is also set to 1 at this time, and

the receiver enters the Hunt mode. The SCC cannot trans-

mit on the loop until a flag is received (causing the receiver

to leave Hunt mode) and another EOP (bit pattern

11111110) is received. The SCC is now on the loop and

capable of transmitting on the loop. As soon as this status

is recognized by the processor, the Go-Active-On-Poll bit

in WR10 is set to 0 to prevent the SCC from transmitting

on the loop without a processor acknowledgment.

To ensure proper loop operation after the SCC goes off the

loop, and until the external relays take the SCC completely

out of the loop, the SCC should be programmed for Mark

idle instead of Flag idle. When the SCC goes off the loop,

the On-Loop bit is reset.

Note: With NRZI encoding, removing the stations from the

loop (removing the one-bit time delay) may cause prob-

lems further down the loop because of extraneous transi-

tions on the line. The SCC avoids this problem by making

transparent adjustments at the end of each frame it sends

in response to an EOP. A response frame from the SCC is

terminated by a flag and EOP. Normally, the flag and the

EOP share a zero, but if such sharing would cause the

RxD and TxD pins to be of opposite polarity after the EOP,

the SCC adds another zero between the flag and the EOP.

This causes an extra line transition so that RxD and TxD

are identical after the EOP is sent. This extra zero is com-

pletely transparent because it only means that the flag and

the EOP no longer share a zero. All that a proper loop exit

needs, therefore, is the removal of the one-bit delay.

4.4.4.2 SDLC Loop Mode Transmit

To transmit a message on the loop, the Go-Active-On-Poll

bit in WR10 must be set to 1. Once this is done, the SCC

changes the next received EOP into a Flag and begins

transmitting on the loop.

When the EOP is received, the Break/Abort and Hunt bits

in RR0 are set to 1, and the Loop Sending bit in RR10 is

also set to 1. Data to be transmitted is written after the Go-

Active-On-Poll bit has been set or after the receiver enters

Hunt mode.

If the data is written immediately after the Go-Active-On-

Poll bit has been set, the SCC only inserts one flag after

the EOP is changed into a flag. If the data is not written un-

til after the receiver enters the Hunt mode, the flags are

transmitted until the data is written. If only one frame is to

be transmitted on the loop in response to an EOP, the pro-

cessor must set the Go Active on Poll bit to 0 before the

last data is written to the transmitter. In this case, the trans-

mitter closes the frame with a single flag and then reverts

to the one-bit delay.

The SCC allows the user the option of using NRZI in SDLC

Loop mode by programming WR10 appropriately. With

NRZI encoding, the outputs of secondary stations in the

loop are inverted from their inputs because of messages

that they have transmitted.

Subsections 4.4.4.1 and 4.4.4.2 discuss the SDLC Loop

Mode in Receive and Transmit.

The Loop Sending bit in RR10 is set to 0 when the closing

Flag has been sent. If more than one frame is to be trans-

mitted, the Go-Active-On-Poll bit should not be set to 0 un-

til the last frame is being sent. If this bit is not set to 0 be-

fore the end of a frame, the transmitter sends Flags until

either more data is written to the transmitter, or until the

Go-Active-On-Poll bit is set to 0. Note that the state of the

Abort/Flag on Underrun and Mark/Flag idle bits in WR10 is

ignored by the SCC in SDLC Loop mode.

4.4.4.1 SDLC Loop Mode Receive

SDLC Loop mode is quite similar to SDLC mode except

that two additional control bits are used. They are the Loop

Mode bit (D1) and the Go-Active-On-Poll bit (D4) in WR10.

In addition to these two extra control bits, there are also

two status bits in RR10. They are the On Loop bit (D1) and

the Loop Sending bit (D4).

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Data Communication Modes

4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)

4.4.4.3 SDLC Loop Initialization

should not be set to 1 yet. The flag is written in WR7 and

The initialization sequence for the SCC in SDLC Loop

mode is similar to the sequence used in SDLC mode, ex-

cept that it is longer. The processor should program WR4

first to select SDLC mode, and then WR10 to select the

CRC preset value and program the Mark/Flag idle bit.

The Loop Mode and Go-Active-On-Poll bits in WR10

the various options are selected in WR3 and WR5. At

this point, the other registers are initialized as necessary

(Table 4-12).

Table 4-12. SDLC Loop Mode Initialization

Bit Number

Reg

D7

D6

D5

D4

D3

D2

D1

D0

Description

WR4

WR3

0

r

0

x

1

0

1

0

1

0

1

0

Select x1 clock, SDLC mode, enable sync mode

rx=# of Rx bits/char, No auto enable, enter Hunt,

Enable Rx CRC, Address Search, No sync character

load inhibit

WR5

d

t

x

0

r

1

d=inverse of DTR pin, tx=# of Tx bits/char, use SDLC

CRC, r=inverse state of /RTS pin, CRC enable

SDLC Flag

WR7

WR6

0

x

1

x

1

x

1

x

1

x

1

x

1

x

0

x

Receiver secondary address

WR15

WR7'

x

0

x

1

x

1

x

d

x

1

x

r

x

1

Enable access to new register

Enable extended read, Tx INT on FIFO empty,

d=REQUEST timing mode, Rx INT on 4 char, r=RTS

deactivation, auto EOM reset, auto ﬂag tx

WR10

c

d

e

1

i

0

1

0

Enable Loop Mode, Go Active On Poll, c=CRC preset,

de=data encoding method, i=idle line

Enable Receiver

Enable Transmitter

Reset CRC generator

WR3

WR5

WR0

r

d

1

x

t

0

x

0

1

0

1

0

1

0

r

0

1

0

The Loop Mode bit (D1) in WR10 is set to 1. When all of

this is complete, the transmitter is enabled by setting bit D3

of WR5 to 1. Now that the transmitter is enabled, the CRC

generator is initialized by issuing the Reset Tx CRC Gen-

erator command in WR0. The receiver is enabled by set-

ting the Go-Active-On-Poll bit (D4) in WR10 to 1. The SCC

goes on the loop when seven consecutive 1s are received,

and signals this by setting the On-Loop bit in RR10. Note

that the seven consecutive 1s will set the Break/Abort and

Hunt bits in RR0 also. Once the SCC is on the loop, the

Go-Active-On-Poll bit should be set to 0 until a message is

to be transmitted on the loop. To transmit a message on

the loop, the Go-Active-On-Poll bit should be set to 1. At

this point, the processor may either write the first character

to the transmit buffer and wait for a transmit buffer empty

condition, or wait for the Break/Abort and Hunt bits to be

set in RR10 and the Loop Sending bit to be set in RR10 be-

fore writing the first data to the transmitter. The Go-Active-

On-Poll bit should be set to 0 after the transition of the

frame has begun. To go off of the loop, the processor

should set the Go-Active-On-Poll bit in WR10 to 0 and then

wait for the Loop Sending bit in RR10 to be set to 0. At this

point, the Loop Mode bit (D1) in WR10 is set to 0 to request

an orderly exit from the loop. The SCC exits SDLC Loop

mode when seven consecutive 1s have been received; at

the same time the Break/Abort and Hunt bits in RR0 are

set to 1, and the On Loop bit in RR10 is set to 0.

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5

CHAPTER 5

REGISTER DESCRIPTIONS

5.1 INTRODUCTION

This section describes the functions of the various bits in

the registers of the SCC (Tables 5-1 and 5-2). Reserved

bits are not used in this implementation of the device and

may or may not be physically present in the device. For the

register addresses, also refer to Tables 2-1, 2-2 and 2-5 in

Chapter 2. Reserved bits that are physically present are

readable and writable but reserved bits that are not present

will always be read as zero. To ensure compatibility with fu-

ture versions of the device, reserved bits should always be

written with zeros. Reserved commands are not used for

the same reason.

Table 5-1. SCC Write Registers

Description

.

Table 5-2. SCC Read Registers

Reg

Description

WR0

WR1

Reg. pointers, various initialization commands

Transmit and Receive interrupt enables,

WAIT/DMA commands

RR0

Transmit and Receive buffer status and external

status

Special Receive Condition status

Modiﬁed interrupt vector (Channel B only),

Unmodiﬁed interrupt vector (Channel A only)

RR1

RR2

WR2

Interrupt Vector

2

Receive parameters and control modes

Transmit and Receive modes and parameters

Transmit parameters and control modes

WR3

WR4

RR3

RR4

Interrupt pending bits (Channel A only)

Transmit and Receive modes and parameters

(WR4)

2

WR5

WR6

WR7

Sync Character or SDLC address

Sync Character or SDLC ﬂag

Extended Feature and FIFO Control

(WR7 Prime)

2

3

Transmit parameters and control modes (WR5)

RR5

RR6

SDLC FIFO byte counter lower byte (only when

enabled)

1

WR7'

3

SDLC FIFO byte count and status (only when

enabled)

WR8

WR9

Transmit buffer

Master Interrupt control and reset commands

RR7

RR8

RR9

Receive buffer

Receive parameters and control modes (WR3)

2

Miscellaneous transmit and receive control bits

WR10

2

WR11 Clock mode controls for receive and transmit

WR12 Lower byte of baud rate generator

WR13 Upper byte of baud rate generator

WR14 Miscellaneous control bits

RR10 Miscellaneous status bits

2

Miscellaneous transmit and receive control bits

(WR10)

RR11

RR12 Lower byte of baud rate generator time constant

RR13 Upper byte of baud rate generator time constant

WR15 External status interrupt enable control

2

Extended Feature and FIFO Control (WR7

RR14

Notes for Tables 5-1 and 5-2:

1. ESCC and 85C30 only.

Prime)

2. On the ESCC and 85C30, these registers are readable as

RR9, RR4, RR5, and RR11, respectively, when WR7' D6=1.

Refer to the description of WR7 Prime for enabling the ex-

tended read capability.

RR15 External Status interrupt information

3. This feature is not available on NMOS.

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Register Descriptions

5.1 INTRODUCTION (Continued)

Among these registers, WR9 (Master Interrupt Control and

Reset register) can be accessed through either channel.

The RR2 (Interrupt Vector register) returns the interrupt

vector modified by status, if read from Channel B, and writ-

ten value (without modification), if read from Channel A.

On the ESCC and 85C30, there is one additional register

(WR7') to control enhanced features.

See Table 5-1 for a summary of Write registers.

Read Registers. Four read registers indicate status infor-

mation; two are for baud rate generation; one for the re-

ceive buffer. In addition, there are two read registers which

are shared by both channels; one for the interrupt pending

bits; another for the interrupt vector. On the CMOS/ESCC,

there are two additional registers, RR6 and RR7. They are

available if the Frame Status FIFO feature was enabled in

the SDLC mode of operation. On the ESCC, there is an

“extended read” option and if its enabled, certain write reg-

isters can be read back.

Channel A has an additional read register which contains

all the Interrupt Pending bits (RR3A).

Write Registers. Eleven write registers are used for con-

trol (includes transmit buffer/FIFO); two for sync character

generation/detection; two for baud rate generation. In ad-

dition, there are two write registers which are shared by

both channels; one is the interrupt vector register (WR2);

the other is the Master Interrupt and Reset register (WR9).

See Table 5-2 for a summary of Read registers.

5.2 WRITE REGISTERS

The SCC write register set in each channel has 11 control

registers (includes transmit buffer/FIFO), two sync charac-

ter registers, and two baud rate time constant registers.

The interrupt control register and the master interrupt con-

trol and reset register are shared by both channels. In ad-

dition to these, the ESCC and 85C30 has a register (WR7';

prime 7) to control the enhancements.

Null Command (00). This command has no effect on the

SCC and is used when a write to WR0 is necessary for

some reason other than a CRC Reset command.

Reset Receive CRC Checker Command (01). This com-

mand is used to initialize the receive CRC circuitry. It is

necessary in synchronous modes (except SDLC) if the En-

ter Hunt Mode command in Write Register 3 is not issued

between received messages. Any action that disables the

receiver initializes the CRC circuitry. Resetting the Re-

ceive CRC Checker command is accomplished automati-

cally in SDLC mode.

Between 80X30 and 85X30, the variation in register defini-

tion is a command decode structure; Write Register 0

(WR0). The following sections describe in detail each write

register and the associated bit configuration for each.

The following sections describe WR registers in detail:

Reset Transmit CRC Generator Command (10). This

command initializes the CRC generator. It is usually is-

sued in the initialization routine and after the CRC has

been transmitted. A Channel Reset does not initialize the

generator and this command is not issued until after the

transmitter has been enabled in the initialization routine.

5.2.1 Write Register 0 (Command Register)

WR0 is the command register and the CRC reset code

register. WR0 takes on slightly different forms depending

upon whether the SCC is in the Z85X30 or the Z80X30.

Figure 5-1 shows the bit configuration for the Z85X30 and

includes register select bits in addition to command and re-

set codes.

On the ESCC and 85C30, this command is not needed if

Auto EOM Reset mode is enabled (WR7' D1=1).

Reset Transmit Underrun/EOM Latch Command (11).

This command controls the transmission of CRC at the

end of transmission (EOM). If this latch has been reset,

and a transmit underrun occurs, the SCC automatically

appends CRC to the message. In SDLC mode with Abort

on Underrun selected, the SCC sends an abort and Flag

on underrun if the TX Underrun/EOM latch has been reset.

Figure 5-2 shows the bit configuration for the Z80X30 and

includes (in Channel B only) the address decoding select

described later.

The following bit description for WR0 is identical for both

versions except where specified:

Bits D7 and D6: CRC Reset Codes 1 And 0.

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SCC™/ESCC™ User’s Manual

Register Descriptions

At the start of the CRC transmission, the Tx Under-

run/EOM latch is set. The Reset command can be issued

at any time during a message. If the transmitter is disabled,

this command does not reset the latch. However, if no Ex-

ternal Status interrupt is pending, or if a Reset External

Status interrupt command accompanies this command

while the transmitter is disabled, an External/Status inter-

rupt is generated with the Tx Underrun/EOM bit reset in

RR0.

Write Register 0 (non-multiplexed bus mode)

D7 D6 D5 D4 D3 D2 D1 D0

5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register 0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

Register 7

Register 8

Register 9

Register 10

Register 11

Register 12

Register 13

Register 14

Register 15

Bits D5-D3: Command Codes for the SCC.

Null Command (000). The Null command has no effect on

the SCC.

*

Point High Command (001). This command effectively

adds eight to the Register Pointer (D2-D0) by allowing

WR8 through WR15 to be accessed. The Point High com-

mand and the Register Pointer bits are written simulta-

neously. This command is used in the Z85X30 version of

the SCC. Note that WR0 changes form depending upon

the SCC version. Register access for the Z80X30 version

of the SCC is accomplished through direct addressing.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Null Code

Point High

Reset Ext/Status Interrupts

Send Abort (SDLC)

Enable Int on Next Rx Character

Reset Tx Int Pending

Error Reset

Reset Highest IUS

0

1

0

1

0

1

Null Code

Reset Rx CRC Checker

Reset Tx CRC Generator

Reset Tx Underrun/EOM Latch

Reset External/Status Interrupts Command (010). After

an External/Status interrupt (a change on a modem line or

a break condition, for example), the status bits in RR0 are

latched. This command re-enables the bits and allows in-

terrupts to occur again as a result of a status change.

Latching the status bits captures short pulses until the

CPU has time to read the change.

With Point High Command

*

Figure 5-1. Write Register 0 in the Z85X30

The SCC contains simple queueing logic associated with

most of the external status bits in RR0. If another Exter-

nal/Status condition changes while a previous condition is

still pending (Reset External/Status Interrupt has not yet

been issued) and this condition persists until after the com-

mand is issued, this second change causes another Exter-

nal/Status interrupt. However, if this second status change

does not persist (there are two transitions), another inter-

rupt is not generated. Exceptions to this rule are detailed

in the RR0 description.

Write Register 0 (multiplexed bus mode)

D7 D6 D5 D4 D3 D2 D1 D0

Null Code

Select Shift Left Mode

Select Shift Right Mode

0

1

0

1

0

1

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Null Code

Reset Ext/Status Interrupts

Send Abort Command (011). This command is used in

SDLC mode to transmit a sequence of eight to thirteen 1s.

This command always empties the transmit buffer and

sets Tx Underrun/EOM bit in Read Register 0.

Send Abort

Enable Int on Next Rx Character

Reset Tx Int Pending

Error Reset

Reset Highest IUS

Enable Interrupt On Next Rx Character Command

(100). If the interrupt on First Received Character mode is

selected, this command is used to reactivate that mode af-

ter each message is received. The next character to enter

the Receive FIFO causes a Receive interrupt. Alternative-

ly, the first previously stored character in the FIFO causes

a Receive interrupt.

0

1

0

1

0

1

Null Code

Reset Rx CRC Checker

Reset Tx CRC Generator

Reset Tx Underrun/EOM Latch

* B Channel Only

Figure 5-2. Write Register 0 in the Z80X30

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SCC™/ESCC™ User’s Manual

Register Descriptions

5.1 INTRODUCTION (Continued)

Reset Tx Interrupt Pending Command (101). This com-

mand is used in cases where there are no more characters

to be sent; e.g., at the end of a message. This command

prevents further transmit interrupts until after the next

character has been loaded into the transmit buffer or until

CRC has been completely sent. This command is neces-

sary to prevent the transmitter from requesting an interrupt

when the transmit buffer becomes empty (with Transmit

Interrupt Enabled).

Bit 7: WAIT/DMA Request Enable.

This bit enables the Wait/Request function in conjunction

with the Request/Wait Function Select bit (D6).

Write Register 1

D7 D6 D5 D4 D3 D2 D1 D0

Ext Int Enable

Tx Int Enable

Error Reset Command (110). This command resets the

error bits in RR1. If interrupt on first Rx Character or Inter-

rupt on Special Condition modes is selected and a special

condition exists, the data with the special condition is held

in the Receive FIFO until this command is issued. If either

of these modes is selected and this command is issued be-

fore the data has been read from the Receive FIFO, the

data is lost.

Parity is Special Condition

0

1

0

1

0

1

Rx Int Disable

Rx Int On First Character or Special Condition

Int On All Rx Characters or Special Condition

Rx Int On Special Condition Only

WAIT/DMA Request On

Receive//Transmit

/WAIT/DMA Request Function

WAIT/DMA Request Enable

Reset Highest IUS Command (110). This command re-

sets the highest priority Interrupt Under Service (IUS) bit,

allowing lower priority conditions to request interrupts. This

command allows the use of the internal daisy chain (even

in systems without an external daisy chain) and is the last

operation in an interrupt service routine.

Figure 5-3. Write Register 1

When programmed to 0, the selected function (bit 6) forces

the /W//REQ pin into the appropriate inactive state (High

for Request, floating for Wait).

Bits 2 through 0: Register Selection Code

When programmed to 1, the state of bit 6 determines the

activity of the /W//REQ pin (Wait or Request).

On the Z85X30, these three bits select Registers 0 through

7. With the Point High command, Registers 8 through 15

are selected (Table 5-3).

Bit 6: WAIT/DMA Request Function

When programmed to 0, the Wait function is selected. In

the Wait mode, the /W//REQ pin switches from floating to

Low when the CPU attempts to transfer data before the

SCC is ready.

In the multiplexed bus mode, bits D2 through D0 have the

following function.

Bit D2 must be programmed as 0. Bits D1 and D0 select

Shift Left/Right; that is WR0 (1-0)=10 for shift left and WR0

(1-0)=11 for shift right. See Section 2.1.4 for further details

on Z80X30 register access.

When programmed to 1, the Request function is selected.

In the Request mode, the /W//REQ pin switches from High

to Low when the SCC is ready to transfer data.

5.2.2 Write Register 1 (Transmit/Receive In-

terrupt and Data Transfer Mode Definition)

Bit 5: /WAIT//REQUEST on Transmit or Receive

When programmed to 0, the state of the /W//REQ pin is de-

termined by bit 6 and the state of the transmit buffer.

Write Register 1 is the control register for the various SCC

interrupt and Wait/Request modes. Figure 5-3 shows the

bit assignments for WR1.

Note: A transmit request function is available on the

/DTR//REQ pin. This allows full-duplex operation under

DMA control for both channels.

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Register Descriptions

Table 5-3. Z85X30 Register Map

85C30/85230W

85C30/230*

WR15 D2 = 0

RR0B

85C30/230

WR15 D2=1

RR0B

R15 D2=1

WR7' D6=1

RR0B

5

A//B

PNT2

PNT1

PNT0

WRITE

WR0B

WR1B

WR2

0

1

0

1

0

1

RR1B

RR2B

RR3B

RR1B

RR2B

RR3B

RR1B

RR2B

RR3B

WR3B

0

1

0

1

0

1

0

1

WR4B

WR5B

WR6B

WR7B

(RR0B)

(RR1B)

(RR2B)

(RR3B)

(RR0B)

(RR1B)

RR6B

(WR4B)

(WR5B)

RR6B

RR7B

1

0

1

0

1

0

1

WR0A

WR1A

WR2

RR0A

RR1A

RR2A

RR3A

RR0A

RR1A

RR2A

RR3A

RR0A

RR1A

RR2A

RR3A

WR3A

1

0

1

0

1

0

1

WR4A

WR5A

WR6A

WR7A

(RR0A)

(RR1A)

(RR2A)

(RR3A)

(RR0A)

(RR1A)

RR6A

(WR4A)

(WR5A)

RR6A

RR7A

With Point High Command

0

1

0

1

0

1

WR8B

WR9

WR10B

WR11B

RR8B

(RR13B)

RR10B

(RR15B)

(RR13B)

RR10B

(RR15B)

(WR3B)

RR10B

(WR10B)

0

1

0

1

0

1

0

1

WR12B

WR13B

WR14B

WR15B

RR12B

RR13B

RR14B

RR15B

RR12B

RR13B

RR14B

RR15B

RR12B

RR13B

(WR7’B)

RR15B

1

0

1

0

1

0

1

WR8A

WR9A

WR10A

WR11A

RR8A

(RR13A)

RR10A

(RR15A)

(RR13A)

RR10A

(RR15A)

(WR3A)

RR10A

(WR10A)

1

0

1

0

1

0

1

WR12A

WR13A

WR14A

WR15A

RR12A

RR13A

RR14A

RR15A

RR12A

RR13A

RR14A

RR15A

RR12A

RR13A

(WR7’A)

RR15A

Notes:

WR15 bit D2 enables status FIFO function. (Not available on NMOS)

WR7' bit D6 enables extend read function. (Only on ESCC and 85C30)

* Includes 85C30 and 85230 with WR15 D2=0.

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5.1 INTRODUCTION (Continued)

When programmed to 1, this bit allows the Wait/Request

function to follow the state of the receive buffer. Thus, de-

pending on the state of bit 6, the /W//REQ pin is active or

inactive in relation to the empty or full state of the receive

buffer.

ESCC:

See the description of WR7' on how this function can

be changed.

Interrupt on All Receive Characters or Special Condi-

tion (10). This mode allows an interrupt for every character

received (or character in the Receive FIFO) and provides

a unique vector when a special condition exists. The Re-

ceiver Overrun bit and the Parity Error bit in RR1 are two

special conditions that are latched. These two bits are re-

set by the Error Reset command. Receiver overrun is al-

ways a special receive condition, and parity can be pro-

grammed to be a special condition.

The request function occurs only when the SCC is not se-

lected; e.g., if the internal request becomes active while

the SCC is in the middle of a read or write cycle, the exter-

nal request does not become active until the cycle is com-

plete. An active request output causes a DMA controller to

initiate a read or write operation. If the request on Transmit

mode is selected in either SDLC or Synchronous Mode,

the Request pin is pulsed Low for one PCLK cycle at the

end of CRC transmission to allow the immediate transmis-

sion of another block of data.

Data characters with special receive conditions are not

held in the Receive FIFO in the Interrupt On All Receive

Characters or Special Conditions Mode as they are in the

other receive interrupt modes.

In the Wait On Receive mode, the /WAIT pin is active if the

CPU attempts to read SCC data that has not yet been re-

ceived. In the Wait On Transmit mode, the /WAIT pin is ac-

tive if the CPU attempts to write data when the transmit

buffer is still full. Both situations occur frequently when

block transfer instructions are used.

Receive Interrupt on Special Condition (11). This mode

allows the receiver to interrupt only on characters with a

special receive condition. When an interrupt occurs, the

data containing the error is held in the Receive FIFO until

an Error Reset command is issued. When using this mode

in conjunction with a DMA, the DMA is initialized and en-

abled before any characters have been received by the

ESCC. This eliminates the time-critical section of code re-

quired in the Receive Interrupt on First Character or Spe-

cial Condition mode. Hence, all data can be transferred via

the DMA so that the CPU need not handle the first re-

ceived character as a special case. In SDLC mode, if the

SDLC Frame Status FIFO is enabled and an EOF is re-

ceived, an interrupt with vector for receive data available is

generated and the Receive FIFO is not locked.

Bits 4 and 3: Receive Interrupt Modes

Receive Interrupts Disabled (00). This mode prevents

the receiver from requesting an interrupt. It is normally

used in a polled environment where either the status bits

in RR0 or the modified vector in RR2 (Channel B) are mon-

itored to initiate a service routine. Although the receiver in-

terrupts are disabled, a special condition can still provide a

unique vector status in RR2.

Receive Interrupt on First Character or Special Condi-

tion (01). The receiver requests an interrupt in this mode

on the first available character (or stored FIFO character)

or on a special condition. Sync characters, stripped from

the message stream, do not cause interrupts.

Bit 2: Parity Is Special Condition

If this bit is set to 1, any received characters with parity not

matching the sense programmed in WR4 give rise to a

Special Receive Condition. If parity is disabled (WR4), this

bit is ignored. A special condition modifies the status of the

interrupt vector stored in WR2. During an interrupt ac-

knowledge cycle, this vector can be placed on the data

bus.

Special receive conditions are: receiver overrun, framing

error, end of frame, or parity error (if selected). If a special

receive condition occurs, the data containing the error is

stored in the Receive FIFO until an Error Reset command

is issued by the CPU.

Bit 1: Transmitter Interrupt Enable

If this bit is set to 1, the transmitter requests an interrupt

whenever the transmit buffer becomes empty.

This mode is usually selected when a Block Transfer mode

is used. In this interrupt mode, a pending special receive

condition remains set until either an error Reset command,

a channel or hardware reset, or until receive interrupts are

disabled.

Bit 0: External/Status Master Interrupt Enable

This bit is the master enable for External/Status interrupts

including /DCD, /CTS, /SYNC pins, break, abort, the begin-

ning of CRC transmission when the Transmit/Under-

run/EOM latch is set, or when the counter in the baud rate

generator reaches 0. Write Register 15 contains the individ-

ual enable bits for each of these sources of External/Status

interrupts. This bit is reset by a channel or hardware reset.

The Receive Interrupt on First Character or Special Condi-

tion mode can be re-enabled by the Enable Rx Interrupt on

Next Character command in WR0.

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Register Descriptions

Bits 7 and 6: Receiver Bits/Character

5.2.3 Write Register 2 (Interrupt Vector)

The state of these two bits determines the number of bits

to be assembled as a character in the received serial data

stream. The number of bits per character can be changed

while a character is being assembled, but only before the

number of bits currently programmed is reached. Unused

bits in the Received Data Register (RR8) are set to 1 in

asynchronous modes. In Synchronous and SDLC modes,

the SCC merely transfers an 8-bit section of the serial data

stream to the Receive FIFO at the appropriate time. Table

5-4 lists the number of bits per character in the assembled

character format.

WR2 is the interrupt vector register. Only one vector

register exists in the SCC, and it can be accessed through

either channel. The interrupt vector can be modified by

status information. This is controlled by the Vector

Includes Status (VIS) and the Status High/Status Low bits

in WR9. The bit positions for WR2 are shown in Figure 5-4.

5

Write Register 2

D7 D6 D5 D4 D3 D2 D1 D0

Table 5-4. Receive Bits per Character

V0

V1

V2

D7

D6

Bits/Character

0

1

0

1

0

1

5

7

6

8

V3

V4

V5

V6

V7

Interrupt

Vector

Bit 5: Auto Enable

This bit programs the function for both the /DCD and /CTS

pins. /CTS becomes the transmitter enable and /DCD be-

comes the receiver enable when this bit is set to 1. How-

ever, the Receiver Enable and Transmit Enable bits must

be set before the /DCD and /CTS pins can be used in this

manner. When the Auto Enable bit is set to 0, the /DCD

and /CTS pins are inputs to the corresponding status bits

in Read Register 0. The state of /DCD is ignored in the Lo-

cal Loopback mode. The state of /CTS is ignored in both

Auto Echo and Local Loopback modes.

Figure 5-4. Write Register 2

5.2.4 Write Register 3 (Receive Parameters

and Control)

This register contains the control bits and parameters for

the receiver logic as illustrated in Figure 5-5. On the ESCC

and 85C30, with the Extended Read option enabled, this

register may be read as RR9.

Bit 4: Enter Hunt Mode

This command forces the comparison of sync characters

or flags to assembled receive characters for the purpose

of synchronization. After reset, the SCC automatically en-

ters the Hunt mode (except asynchronous). Whenever a

flag or sync character is matched, the Sync/Hunt bit in

Read Register 0 is reset and, if External/Status Interrupt

Enable is set, an interrupt sequence is initiated. The SCC

automatically enters the Hunt mode when an abort condi-

tion is received or when the receiver is enabled.

Write Register 3

D7 D6 D5 D4 D3 D2 D1 D0

Rx Enable

Sync Character Load Inhibit

Address Search Mode (SDLC)

Rx CRC Enable

Enter Hunt Mode

Auto Enables

Bit 3: Receiver CRC Enable

0

Rx 5 Bits/Character

This bit is used to initiate CRC calculation at the beginning

of the last byte transferred from the Receiver Shift register

to the Receive FIFO. This operation occurs independently

of the number of bytes in the Receive FIFO. When a par-

ticular byte is to be excluded from the CRC calculation, this

bit should be reset before the next byte is transferred to the

Receive FIFO. If this feature is used, care must be taken

to ensure that eight bits per character is selected in the re-

ceiver because of an inherent delay from the Receive Shift

register to the CRC checker.

0

1

Rx 7 Bits/Character

1

0

Rx 6 Bits/Character

1

Rx 8 Bits/Character

Figure 5-5. Write Register 3

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5.1 INTRODUCTION (Continued)

This bit is internally set to 1 in SDLC mode and the SCC

calculates the CRC on all bits except zeros inserted be-

tween the opening and closing flags. This bit is ignored in

asynchronous modes.

5.2.5 Write Register 4 (Transmit/Receive Mis-

cellaneous Parameters and Modes)

WR4 contains the control bits for both the receiver and the

transmitter. These bits should be set in the transmit and

receiver initialization routine before issuing the contents of

WR1, WR3, WR6, and WR7. Bit positions for WR4 are

shown in Figure 5-6. On the ESCC and 85C30, with the

Extended Read option enabled, this register is read as

RR4.

Bit 2: Address Search Mode (SDLC)

Setting this bit in SDLC mode causes messages with ad-

dresses not matching the address programmed in WR6 to

be rejected. No receiver interrupts occur in this mode un-

less there is an address match. The address that the SCC

attempts to match is unique (1 in 256) or multiple (16 in

256), depending on the state of Sync Character Load In-

hibit bit. Address FFH is always recognized as a global ad-

dress. The Address Search mode bit is ignored in all

modes except SDLC.

Write Register 4

D7 D6 D5 D4 D3 D2 D1 D0

Parity Enable

Bit 1: SYNC Character Load Inhibit

Parity EVEN//ODD

If this bit is set to 1 in any mode except SDLC, the SCC com-

pares the byte in WR6 with the byte about to be stored in the

FIFO, and it inhibits this load if the bytes are equal. (Caution:

this also occurs in the asynchronous mode if the received

character matches the contents of WR6.) The SCC does

not calculate the CRC on bytes stripped from the data

stream in this manner. If the 6-bit sync option is selected

while in Monosync mode, the comparison is still across

eight bits, so WR6 is programmed for proper operation.

0

1

0

1

0

1

Sync Modes Enable

1 Stop Bit/Character

1 1/2 Stop Bits/Character

2 Stop Bits/Character

0

1

0

1

0

1

8-Bit Sync Character

16-Bit Sync Character

SDLC Mode (01111110 Flag)

External Sync Mode

0

1

0

1

0

1

X1 Clock Mode

X16 Clock Mode

X32 Clock Mode

X64 Clock Mode

If the 6-bit sync option is selected with this bit set to 1, all

sync characters except the one immediately preceding the

data are stripped from the message. If the 6-bit sync option

is selected while in the Bisync mode, this bit is ignored.

Figure 5-6. Write Register 4

The address recognition logic of the receiver is modified in

SDLC mode if this bit is set to 1, i.e., only the four most sig-

nificant bits of WR6 must match the receiver address. This

procedure allows the SCC to receive frames from up to 16

separate sources without programming WR6 for each

source (if each station address has the four most signifi-

cant bits in common). The address field in the frame is still

eight bits long. Address FFH is always recognized as a

global address.

Bits 7 and 6: Clock Rate bits 1 and 0

These bits specify the multiplier between the clock and

data rates. In synchronous modes, the 1X mode is forced

internally and these bits are ignored unless External Sync

mode has been selected.

1X Mode (00). The clock rate and data rate are the same.

In External Sync mode, this bit combination specifies that

only the /SYNC pin is used to achieve character synchro-

nization.

The bit is ignored in SDLC mode if Address Search mode

has not been selected.

16X Mode (01). The clock rate is 16 times the data rate. In

External Sync mode, this bit combination specifies that only

the /SYNC pin is used to achieve character synchronization.

Bit 0: Receiver Enable

When this bit is set to 1, receiver operation begins. This bit

should be set only after all other receiver parameters are

established and the receiver is completely initialized. This

bit is reset by a channel or hardware reset command, and

it disables the receiver.

32X Mode (10). The clock rate is 32 times the data rate. In

External Sync mode, this bit combination specifies that ei-

ther the /SYNC pin or a match with the character stored in

WR7 will signal character synchronization. The sync char-

acter can be either six or eight bits long as specified by the

6-bit/8-bit sync bit in WR10.

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SCC™/ESCC™ User’s Manual

Register Descriptions

64X Mode (11). The clock rate is 64 times the data rate.

With this bit combination in External Sync mode, both the

receiver and transmitter are placed in SDLC mode. The only

variation from normal SDLC operation is that the /SYNC pin

is used to start or stop the reception of a frame by forcing the

receiver to act as though a flag had been received.

1 1/2 Stop Bits/Character (10). These bits select Asyn-

chronous mode with 1-1/2 stop bits per character. This

mode is not used with the 1X clock mode.

5

2 Stop Bits/Character (11). These bits select Asynchro-

nous mode with two stop bits per transmitted character

and checks for one received stop bit.

Bits 5 and 4: SYNC Mode selection bits 1 and 0

These two bits select the various options for character syn-

chronization. They are ignored unless synchronous modes

are selected in the stop bits field of this register.

Bit 1: Parity Even//Odd select bit

This bit determines whether parity is checked as even or

odd. A 1 programmed here selects even parity, and a 0 se-

lects odd parity. This bit is ignored if the Parity enable bit

is not set.

Monosync Mode (00). In this mode, the receiver achieves

character synchronization by matching the character

stored in WR7 with an identical character in the received

data stream. The transmitter uses the character stored in

WR6 as a time fill. The sync character is either six or eight

bits, depending on the state of the 6-bit/8-bit sync bit in

WR10. If the Sync Character Load Inhibit bit is set, the re-

ceiver strips the contents of WR6 from the data stream if

received within character boundaries.

Bit 0: Parity Enable

When this bit is set, an additional bit position beyond those

specified in the bits/character control is added to the trans-

mitted data and is expected in the receive data. The Re-

ceived Parity bit is transferred to the CPU as part of the data

unless eight bits per character is selected in the receiver.

5.2.6 Write Register 5 (Transmit Parameters

and Controls)

Bisync Mode (01). The concatenation of WR7 with WR6

is used for receiver synchronization and as a time fill by the

transmitter. The sync character is 12 or 16 bits in the re-

ceiver, depending on the state of the 6-bit/8-bit sync bit in

WR10. The transmitted character is always 16 bits.

WR5 contains control bits that affect the operation of the

transmitter. D2 affects both the transmitter and the

receiver. Bit positions for WR5 are shown in Figure 5-7. On

the 85X30 with the Extended Read option enabled, this

register is read as RR5.

SDLC Mode (10). In this mode, SDLC is selected and re-

quires a Flag (01111110) to be written to WR7. The receiv-

er address field is written to WR6. The SDLC CRC polyno-

mial is also selected (WR5) in SDLC mode.

Write Register 5

D7 D6 D5 D4 D3 D2 D1 D0

External Sync Mode (11). In this mode, the SCC expects

external logic to signal character synchronization via the

/SYNC pin. If the crystal oscillator option is selected (in

WR11), the internal /SYNC signal is forced to 0. In this

mode, the transmitter is in Monosync mode using the con-

tents of WR6 as the time fill with the sync character length

specified by the 6-bit/8-bit Sync bit in WR10.

Tx CRC Enable

RTS

/SDLC/CRC-16

Tx Enable

Send Break

0

1

0

1

0

1

Tx 5 Bits(Or Less)/Character

Tx 7 Bits/Character

Tx 6 Bits/Character

Tx 8 Bits/Character

Bits 3 and 2: Stop Bits selection, bits 1 and 0

These bits determine the number of stop bits added to

each asynchronous character that is transmitted. The re-

ceiver always checks for one stop bit in Asynchronous

mode. A special mode specifies that a Synchronous mode

is to be selected. D2 is always set to 1 by a channel or

hardware reset to ensure that the /SYNC pin is in a known

state after a reset.

DTR

Figure 5-7. Write Register 5

Bit 7: Data Terminal Ready control bit

Synchronous Modes Enable (00). This bit combination

selects one of the synchronous modes specified by bits

D4, D5, D6, and D7 of this register and forces the 1X Clock

mode internally.

This is the control bit for the /DTR//REQ pin while the pin

is in the DTR mode (selected in WR14). When set, /DTR

is Low; when reset, /DTR is High. This bit is ignored when

/DTR//REQ is programmed to act as a /REQ pin. This bit

is reset by a channel or hardware reset.

1 Stop Bit/Character (01). This bit selects Asynchronous

mode with one stop bit per character.

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5.1 INTRODUCTION (Continued)

Bits 6 and 5: Transmit Bits/Character select bits

1 and 0

These bits control the number of bits in each byte trans-

ferred to the transmit buffer. Bits sent must be right justified

with the least significant bits first.

Bit 2: SDLC/CRC-16 polynomial select bit

This bit selects the CRC polynomial used by both the

transmitter and receiver. When set, the CRC-16 polynomi-

al is used; when reset, the SDLC polynomial is used. The

SDLC/CRC polynomial is selected when SDLC mode is

selected. The CRC generator and checker can be preset

to all 0s or all 1s, depending on the state of the Preset

1/Preset 0 bit in WR10.

The Five Or Less mode allows transmission of one to five

bits per character. For five or fewer bits per character, the

data character must be formatted as shown below in Table

5-5. In the Six or Seven Bits/Character modes, unused

data bits are ignored.

Bit 1: Request To Send control bit

This is the control bit for the /RTS pin. When the RTS bit is

set, the /RTS pin goes Low; when reset, /RTS goes High.

When Auto Enable is set in asynchronous mode, the /RTS

pin immediately goes Low when the RTS bit is set. Howev-

er, when the RTS bit is reset, the /RTS pin remains Low

until the transmitter is completely empty and the last stop

bit has left the TxD pin. In synchronous modes, the

/RTS pin directly follows the state of this bit, except in

SDLC mode under specific conditions. In SDLC mode, if

Flag On Underrun bit (WR10, D2) is set, RTS bit in WR5 is

reset, and D2 in WR7' is set. The /RTS pin deasserts au-

tomatically at the last bit of the closing flag triggered by the

rising edge of the Tx clock. This bit is reset by a channel or

hardware reset.

Bit 4: Send Break control bit

When set, this bit forces the TxD output to send continuous

0s beginning with the following transmit clock, regardless

of any data being transmitted at the time. This bit functions

whether or not the transmitter is enabled. When reset, TxD

continues to send the contents of the Transmit Shift regis-

ter, which might be syncs, data, or all 1s. If this bit is set

while in the X21 mode (Monosync and Loop mode select-

ed) and character synchronization is achieved in the re-

ceiver, this bit is automatically reset and the transmitter be-

gins sending syncs or data. This bit is also reset by a

channel or hardware reset.

Table 5-5. Transmit Bits per Character

Bit 0: Transmit CRC Enable

This bit determines whether or not the CRC is calculated

on a transmit character. If this bit is set at the time the char-

acter is loaded from the transmit buffer to the Transmit

Shift register, the CRC is calculated on that character. The

CRC is not automatically sent unless this bit is set when

the transmit underrun exists.

Bit 7

Bit 6

0

1

0

1

0

1

5 or less bits/character

7 bits/character

6 bits/character

8 bits/character

Note: For five or less bits per character selection in WR5, the fol-

lowing encoding is used in the data sent to the transmitter. D is

the data bit(s) to be sent.

5.2.7 Write Register 6 (Sync Characters or

SDLC Address Field)

WR6 is programmed to contain the transmit sync

character in the Monosync mode, or the first byte of a 16-

bit sync character in the External Sync mode. WR6 is not

used in asynchronous modes. In the SDLC modes, it is

programmed to contain the secondary address field used

to compare against the address field of the SDLC Frame.

In SDLC mode, the SCC does not automatically transmit

the station address at the beginning of a response frame.

Bit positions for WR6 are shown in Figure 5-8.

D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

1

0

1

0

D

0

D

0

D

0

D

Sends one data bit

Sends two data bits

Sends three data bits

Sends four data bits

Sends ﬁve data bits

D

Bit 3: Transmit Enable

Data is not transmitted until this bit is set, and the TxD out-

put sends continuous 1s unless Auto Echo mode or SDLC

Loop mode is selected. If this bit is reset after transmission

starts, the transmission of data or sync characters is com-

pleted. If the transmitter is disabled during the transmis-

sion of a CRC character, sync or flag characters are sent

instead of CRC. This bit is reset by a channel or hardware

reset.

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Register Descriptions

Write Register 6

D7 D6 D5 D4 D3 D2 D1 D0

5

Sync7 Sync6 Sync5 Sync4

Sync3 Sync2 Sync1 Sync0 Monosync, 8 Bits

Sync3 Sync2 Sync1 Sync0 Monosync, 6 Bits

Sync1 Sync0 Sync5 Sync4

Sync7 Sync6 Sync5 Sync4

Sync3 Sync2 Sync1 Sync0

ADR7 ADR6 ADR5 ADR4

Sync3 Sync2 Sync1 Sync0

Bisync, 16 Bits

Bisync, 12 Bits

SDLC

1

ADR3 ADR2 ADR1 ADR0

x

SDLC (Address Range)

Figure 5-8. Write Register 6

character (01111110) in the SDLC modes. WR7 holds the

receive sync character or a flag if one of the special

versions of the External Sync mode is selected. WR7 is not

used in Asynchronous mode. Bit positions for WR7 are

shown in Figure 5-9.

5.2.8 Write Register 7 (Sync Character or

SDLC Flag)

WR7 is programmed to contain the receive sync character

in the Monosync mode, a second byte (the last eight bits)

of a 16-bit sync character in the Bisync mode, or a Flag

Write Register 7

D7 D6 D5 D4 D3 D2 D1 D0

Sync7 Sync6 Sync5 Sync4

Sync5 Sync4 Sync3 Sync2

Sync15 Sync14 Sync13 Sync12 Sync11 Sync10 Sync9 Sync8

Sync11 Sync10 Sync9 Sync8

Sync7 Sync6 Sync5 Sync4

Sync3 Sync2 Sync1 Sync0

Monosync, 8 Bits

Monosync, 6 Bits

Bisync, 16 Bits

Bisync, 12 Bits

SDLC

Sync1 Sync0

x

0

1

0

Figure 5-9. Write Register 7

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5.1 INTRODUCTION (Continued)

Bit 4: /DTR//REQ Timing

5.2.9 Write Register 7 Prime (ESCC only)

If this bit is set and the /DTR//REQ pin is used for Request

Mode (WR14 bit D2 = 1), the deactivation of the

/DTR//REQ pin is identical to the /W//REQ pin. Refer to the

chapter on interfacing for further details. If this bit is reset

(0), the deactivation time for the /DTR//REQ pin is 4TcPc.

This latter operation is identical to that of the SCC.

This Register is used only with the ESCC. Write Register

7 Prime is located at the same address as Write Register

7. This register is written to by setting bit D0 of WR15 to a

1. Refer to the description in the section on Write Register

15. Features enabled in WR7 Prime remain enabled

unless otherwise disabled; a hardware or channel reset

leaves WR7 Prime with all features intact (register

contents are 0) (Figure 5-10).

Bit 3: Receive FIFO Interrupt Level

If WR7' D3=1 and “Receive Interrupt on All Characters and

Special Conditions” is enabled, the Receive Character

Available interrupt is triggered when the Rx FIFO is half full,

i.e., the four byte slots of the Rx FIFO are empty. However,

if any character has a special condition, a special condition

interrupt is generated when the character is loaded into the

Receive FIFO. Therefore, the special condition interrupt

service routine should read RR1 before reading the data to

determine which byte has which special condition.

WR7'

D7 D6 D5 D4 D3 D2 D1 D0

Auto Tx Flag

Auto EOM Reset

Auto/RTS Deactivation

Rx FIFO Half Full

If WR7' D3=0, the ESCC sets the receiver and generates

the receive character available interrupt on every received

character, regardless of any special receive condition.

DTR/REQ Timing Mode

Tx FIFO Empty

Extended Read Enable

Reserved (Must be 0)

Bit 2: Auto /RTS pin Deactivation

This bit controls the timing of the deassertion of the /RTS

pin. If the ESCC is programmed for SDLC mode and Flag-

On-Underrun (WR10 D2=0), this bit is set and the RTS bit

is reset. The /RTS is deasserted automatically at the last

bit of the closing flag, triggered by the rising edge of the

Transmit Clock. If this bit is reset, the /RTS pin follows the

state programmed in WR5 D1.

Figure 5-10. Write Register 7 Prime

Bit 7: Reserved

This bit is not used and must always be written zero.

Bit 6: Extended Read Enable bit

Bit 1: Automatic EOM Reset

Setting this bit enables the reading of WR3, WR4, WR5,

WR7 Prime and WR10. When this feature is enabled,

these registers can be accessed by reading RR9, RR4,

RR5, RR14, and RR11, respectively. When the extended

read is not enabled, register access is identical to that of

the NMOS/CMOS version. Refer to Chapter Two on how

this feature affects the mapping of read registers.

If this bit is set, the ESCC automatically resets the Tx Un-

derrun/EOM latch and presets the transmit CRC generator

to its programmed preset state (per values set in WR5 D2

& WR10 D7). Therefore, it is not necessary to issue the

Reset Tx Underrun/EOM latch command when this feature

is enabled. If this bit is reset, ESCC operation is identical

to the SCC.

Bit 5: Transmit FIFO Interrupt Level

Bit 0: Automatic Tx SDLC Flag

If this bit is set, the transmit buffer empty interrupt is gen-

erated when the Transmit FIFO is completely empty. If this

bit is reset (0), the transmit buffer empty interrupt is gener-

ated when the entry location of the Transmit FIFO is emp-

ty. This latter operation is identical to that of the

NMOS/CMOS version.

If this bit is set, the ESCC automatically transmits an SDLC

flag before transmitting data. This removes the require-

ment to reset the mark idle bit (WR10 D3) before writing

data to the transmitter, or having to enable the transmitter

before writing data to the Transmit FIFO. Also, this feature

enables a transmit data write before enabling the transmit-

ter. If this bit is reset, operation is identical to that of the

SCC.

In the DMA Request on Transmit Mode, when using either

the /W//REQ or /DTR//REQ pins, the request is asserted

when the Transmit FIFO is completely empty if the Trans-

mit FIFO Interrupt Level bit is set. The request is asserted

when the entry location of the Transmit FIFO is empty if the

Transmit FIFO Interrupt Level bit is reset (0).

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Register Descriptions

data is actually formed with the six Least Significant Bits of

the 2nd CRC byte.

5.2.10 Write Register 7 Prime (85C30 only)

This Register is used only with the CMOS 85C30 SCC.

WR7' is written to by first setting bit D0 of WR15 to 1, and

pointing to WR7 as normal. All writes to register 7 will be

to WR7' so long as WR D0 is set. WR 15 bit D0 must be

reset to 0 to address the sync register, WR7. If bit D6 of

WR7' was set during the write, then WR7' can be read by

accessing to RR14. The features remain enabled until

specifically disabled, or disabled by a hardware or

software reset. Figure 5-10a. shows WR7'.

Bit 4: /DTR//REQ Timing Fast Mode.

5

If this bit is set and the /DTR//REQ pin is used for Request

Mode (WR14, bit D2=1), the deactivation of the

/DTR//REQ pin is identical to the /W//REQ pin, which is

triggered on the falling edge of the /WR signal, and the

/DTR//REQ pin goes inactive below 200 ns (this number

varies depending on the speed grade of the device). When

this bit is reset to 0, the deactivation time for the

/DTR//REQ pin is 4TcPc.

WR7' Prime

Bit 3: Force TxD High.

D7 D6 D5 D4 D3 D2 D1 D0

In the SDLC mode of operation with the NRZI encoding

mode, there is an option to force TxD High. If bit D0 of

WR15 is set to 1, bit D3 of WR7' can be used to set TxD

pin High.

Auto Tx Flag

Auto EOM Reset

Auto/RTS Deactivation

Note that the operation of this bit is independent of the Tx

Enable bit in WR5 is used to control transmission activities,

whereas bit D3 of WR7' acts as a pseudo transmitter may

actually be mark or flag idling. Care must be exercised

when setting this bit because any character being trans-

mitted at the time that bit is set is “chopped off”; data writ-

ten to the Transmit Buffer while this bit is set is lost.

Force TxD High

/DTR//REQ Fast Mode

Complete CRC Reception

Extended Read Enable

Reserved (Program as 0)

Figure 5-10a. Write Register 7 Prime (WR7')

Bit 2: Auto /RTS pin Deactivation

This bit controls the timing of the deassertion of the /RTS

pin. If this device is programmed for SDLC mode and Flag-

On-Underrun (WR10 D2=0), this bit is set and the RTS bit

is reset. The /RTS is deasserted automatically at the last

bit of the closing flag, triggered by the rising edge of the

TxC. If this bit is reset to 0, the /RTS pin follows the state

programmed in WR5 bit D1.

Bit 7: Reserved.

This bit is reserved and must be programmed as 0.

Bit 6: Extended Read Enable bit

This bit enables the Extended Read. Setting this bit en-

ables the reading of WR3, WR4, WR5, WR7' and WR10.

When this feature is enabled, these registers can be ac-

cessed by reading RR9, RR4, RR5, RR14, and RR11, re-

spectively. When this feature is not enabled, register ac-

cess is to the SCC. In this case, read to these register

locations returns RR13, RR0, RR1, RR10, and RR15 re-

spectively.

Bit 1: Automatic Tx Underrun/EOM Latch Reset

If this bit is set, this version automatically resets the Tx Un-

derrun/EOM latch and presets the transmit CRC generator

to its programmed preset state (the values set in WR5 D2

& WR10 D7). This removes the requirement to issue the

Reset Tx Underrun/EOM latch command. Also, this fea-

ture enables a write transmit data before enabling the

transmitter.

Bit 5: Receive Complete CRC

On this version, with this bit set to 1, the 2nd byte of the

CRC is received completely. This feature is ideal for appli-

cations which require a 2nd CRC byte for complete data;

for example, a protocol analyzer or applications using oth-

er than CRC-CCITT CRC (i.e., 32bit CRC).

Bit 0: Automatic SDLC Opening Flag Transmission.

If this bit is set, the device automatically transmits an

SDLC opening flag before transmitting data. This removes

the requirement to reset the mark idle bit (WR10, bit D3)

before writing data to the transmitter, or having to enable

the transmitter before writing data to the Transmit buffer.

Also, this feature enables a write transmit data before en-

abling the transmitter.

In SDLC mode of operation, the CMOS SCC, on this bit is

programmed as 0. In this case on the EOF condition (when

the closing flag is detected), the contents of the Receive

Shift Register are transferred to the Receive Data FIFO re-

gardless of the number of bits assembled. Because of the

three-bit delay path between the sync register and the Re-

ceive Shift register, the last two bits of the 2nd byte of the

CRC are never transferred to the Receive Data FIFO. The

5.2.11 Write Register 8 (Transmit Buffer)

WR8 is the transmit buffer register.

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5.1 INTRODUCTION (Continued)

Bit 5: Software Interrupt Acknowledge control bit

If bit D5 is set, reading Read Register 2 (RR2) results in an

interrupt acknowledge cycle to be executed internally. Like

a hardware INTACK cycle, a software acknowledge caus-

es the INT pin to return High, the IEO pin to go Low, and

sets the IUS latch for the highest priority interrupt pending.

5.2.12 Write Register 9 (Master Interrupt

Control)

WR9 is the Master Interrupt Control register and contains

the Reset command bits. Only one WR9 exists in the SCC

and is accessed from either channel. The Interrupt control

bits are programmed at the same time as the Reset

command, because these bits are only reset by a

hardware reset. Bit positions for WR9 are shown in Figure

5-11.

This bit is reserved on NMOS, and always writes as 0.

Bit 4: Status High//Status Low control bit

This bit controls which vector bits the SCC modifies to in-

dicate status. When set to 1, the SCC modifies bits V6, V5,

and V4 according to Table 5-6. When set to 0, the SCC

modifies bits V1, V2, and V3. This bit controls status in

both the vector returned during an interrupt acknowledge

cycle and the status in RR2B. This bit is reset by a hard-

ware reset.

Write Register 9

D7 D6 D5 D4 D3 D2 D1 D0

VIS

NV

DLC

Table 5-6. Interrupt Vector Modiﬁcation

MIE

V3

V4

V2

V5

V1

V6

Status High/Status Low =0

Status High/Status Low =1

Status High//Status Low

Software INTACK Enable

(Reserved on NMOS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Ch B Transmit Buffer Empty

Ch B External/Status Change

Ch B Receive Char. Available

Ch B Special Receive Condition

Ch A Transmit Buffer Empty

Ch A External/Status Change

Ch A Receive Char. Available

Ch A Special Receive Condition

0

1

0

1

0

1

No Reset

Channel Reset B

Channel Reset A

Force Hardware Reset

Figure 5-11. Write Register 9

Bit 7 and 6: Reset Command Bits

Together, these bits select one of the reset commands for

the SCC. Setting either of these bits to 1 disables both the

receiver and the transmitter in the corresponding channel;

forces TxD for that channel marking, forces the modem

control signals High in that channel, resets all IPs and IUSs

and disables all interrupts in that channel. Four extra PCLK

cycles must be allowed beyond the usual cycle time after

any of the reset commands is issued before any additional

commands or controls are written to the channel affected.

Bit 3: Master Interrupt Enable

This bit is set to 1 to globally enable interrupts, and cleared

to zero to disable interrupts. Clearing this bit to zero forces

the IEO pin to follow the state of the IEI pin unless there is

an IUS bit set in the SCC. No IUS bit is set after the MIE

bit is cleared to zero. This bit is reset by a hardware reset.

Bit 2: Disable Lower Chain control bit

The Disable Lower Chain bit is used by the CPU to control

the interrupt daisy chain. Setting this bit to 1 forces the IEO

pin Low, preventing lower priority devices on the daisy

chain from requesting interrupts. This bit is reset by a hard-

ware reset.

Null Command (00). This command has no effect. It is

used when a write to WR9 is necessary for some reason

other than an SCC Reset command.

Channel Reset B Command (01). Issuing this command

causes a channel reset to be performed on Channel B.

Bit 1: No Vector select bit

The No Vector bit controls whether or not the SCC re-

sponds to an interrupt acknowledge cycle. This is done by

placing a vector on the data bus if the SCC is the highest

priority device requesting an interrupt. If this bit is set, no

vector is returned; i.e., AD7-AD0 remains tri-stated during

an interrupt acknowledge cycle, even if the SCC is the

highest priority device requesting an interrupt.

Channel Reset A Command (10). Issuing this command

causes a channel reset to be performed on Channel A.

Force Hardware Reset Command (11). The effects of

this command are identical to those of a hardware reset,

except that the Shift Right/Shift Left bit is not changed and

the MIE, Status High/Status Low and DLC bits take the

programmed values that accompany this command.

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Register Descriptions

Bit 0: Vector Includes Status control bit

Bit 7: CRC Presets I/O select bit

The Vector Includes Status Bit controls whether or not the

SCC includes status information in the vector it places on

the bus in response to an interrupt acknowledge cycle. If

this bit is set, the vector returned is variable, with the vari-

able field depending on the highest priority IP that is set.

Table 5-5 shows the encoding of the status information.

This bit is ignored if the No Vector (NV) bit is set.

This bit specifies the initialized condition of the receive

CRC checker and the transmit CRC generator. If this bit is

set to 1, the CRC generator and checker are preset to 1. If

this bit is set to 0, the CRC generator and checker are pre-

set to 0. Either option can be selected with either CRC

polynomial. In SDLC mode, the transmitted CRC is invert-

ed before transmission, and the received CRC is checked

against the bit pattern 0001110100001111. This bit is re-

set by a channel or hardware reset. This bit is ignored in

Asynchronous mode.

5

5.2.13 Write Register 10 (Miscellaneous

Transmitter/Receiver Control Bits)

WR10 contains miscellaneous control bits for both the

receiver and the transmitter. Bit positions for WR10 are

shown in Figure 5-12. On the ESCC and 85C30 with the

Extended Read option enabled, this register may be read

as RR11.

Bits 6 and 5: Data Encoding select bits.

These bits control the coding method used for both the

transmitter and the receiver, as illustrated in Table 5-7. All

of the clocking options are available for all coding

methods. The DPLL in the SCC is useful for recovering

clocking information in NRZI and FM modes. Any coding

method can be used in X1 mode. A hardware reset forces

NRZ mode. Timing for the various modes is shown in

Figure 5-13.

Write Register 10

D7 D6 D5 D4 D3 D2 D1 D0

Table 5-7. Data Encoding

6-Bit//8-Bit Sync

Loop Mode

Bit 6

Bit 5

Encoding

Abort//Flag On Underrun

Mark//Flag Idle

0

1

0

1

0

1

NRZ

NRZI

FM1 (transition = 1)

FM0 (transition = 0)

Go Active On Poll

0

1

0

1

0

1

NRZ

NRZI

FM1 (Transition = 1)

FM0 (Transition = 0)

CRC Preset I//O

Figure 5-12. Write Register 10

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5.1 INTRODUCTION (Continued)

Data

NRZ

1

0

1

0

NRZI

FM1

FM0

Manchester

Figure 5-13. NRZ (NRZI), FM1 (FM0) Timing

Bit 4: Go-Active-On-Poll control bit

frame to ensure that the SCC does not go on-loop without

the CPU noticing it.

When Loop mode is first selected during SDLC operation,

the SCC connects RxD to TxD with only gate delays in the

path. The SCC does not go on-loop and insert the 1-bit de-

lay between RxD and TxD until this bit has been set and

an EOP received. When the SCC is on-loop, the transmit-

ter does not go active unless this bit is set at the time an

EOP is received. The SCC examines this bit whenever the

transmitter is active in SDLC Loop mode and is sending a

flag. If this bit is set at the time the flag is leaving the Trans-

mit Shift register, another flag or data byte (if the transmit

buffer is full) is transmitted.

In synchronous modes other than SDLC with the Loop

Mode bit set, this bit is set before the transmitter goes ac-

tive in response to a received sync character.

This bit is always ignored in Asynchronous mode and Syn-

chronous modes unless the Loop Mode bit is set. This bit

is reset by a channel or hardware reset.

Bit 3: Mark//Flag Idle line control bit

This bit affects only SDLC operation and is used to control

the idle line condition. If this bit is set to 0, the transmitter

send flags as an idle line. If this bit is set to 1, the transmit-

ter sends continuous 1s after the closing flag of a frame.

The idle line condition is selected byte by byte i.e., either a

flag or eight 1s are transmitted. The primary station in an

SDLC loop should be programmed for Mark Idle to create

the EOP sequence. Mark Idle must be deselected at the

beginning of a frame before the first data is written to the

SCC, so that an opening flag is transmitted. This bit is ig-

nored in Loop mode, but the programmed value takes ef-

fect upon exiting the Loop mode. This bit is reset by a

channel or hardware reset.

If the Go-Active-On-Poll bit is not set at this time, the trans-

mitter finishes sending the flag and reverts to the 1-Bit De-

lay mode. Thus, to transmit only one response frame, this

bit is reset after the first data byte is sent to the SCC, but

before CRC has been transmitted. If the bit is not reset be-

fore CRC is transmitted, extra flags are sent, slowing down

response time on the loop. If this bit is reset before the first

data is written, the SCC completes the transmission of the

present flag and reverts to the 1-Bit Delay mode.

After gaining control of the loop, the SCC is not able to

transmit again until a flag and another EOP are received.

It is good practice to set this bit only upon receipt of a poll

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Register Descriptions

On the ESCC and 85C30 with the Automatic TX SDLC

Flag mode enabled (WR7', D0=1), this bit can be left as

mark idle. It will send an opening flag automatically, as well

as sending a closing flag followed by mark idle after the

frame transmission is completed.

SDLC and Asynchronous modes, but still has effect in the

special external sync modes. This bit is reset by a chan-

nel or hardware reset.

5

5.2.14 Write Register 11 (Clock Mode

Control)

Bit 2: Abort//Flag On Underrun select bit

WR11 is the Clock Mode Control register. The bits in this

register control the sources of both the receive and

transmit clocks, the type of signal on the /SYNC and /RTxC

pins, and the direction of the /TRxC pin. Bit positions for

WR11 are shown in Figure 5-14; also, refer to Section 3.5

Clock Selection.

This bit affects only SDLC operation and is used to control

how the SCC responds to a transmit underrun condition. If

this bit is set to 1 and a transmit underrun occurs, the SCC

sends an abort and a flag instead of a CRC. If this bit is re-

set, the SCC sends a CRC on a transmit underrun. At the

beginning of this 16-bit transmission, the Transmit Under-

run/EOM bit is set, causing an External/Status interrupt.

The CPU uses this status, along with the byte count from

memory or the DMA, to determine whether the frame must

be retransmitted.

Write Register 11

D7 D6 D5 D4 D3 D2 D1 D0

To start the next frame, a Transmit Buffer Empty interrupt

occurs at the end of this 16-bit transmission. If both this bit

and the Mark/Flag Idle bit are set to 1, all 1s are transmit-

ted after the transmit underrun. This bit should be set after

the first byte of data is sent to the SCC and reset immedi-

ately after the last byte of data, terminating the frame prop-

erly with CRC and a flag. This bit is ignored in Loop mode,

but the programmed value is active upon exiting Loop

mode. This bit is reset by a channel or hardware reset.

0

1

0

1

0

1

/TRxC Out = Xtal Output

/TRxC Out = Transmit Clock

/TRxC Out = BR Generator Output

/TRxC Out = DPLL Output

/TRxC O/I

0

1

0

1

0

1

Transmit Clock = /RTxC Pin

Transmit Clock = /TRxC Pin

Transmit Clock = BR Generator Output

Transmit Clock = DPLL Output

0

1

0

1

0

1

Receive Clock = /RTxC Pin

Bit 1: Loop Mode control bit

Receive Clock = /TRxC Pin

Receive Clock = BR Generator Output

Receive Clock = DPLL Output

In SDLC mode, the initial set condition of this bit forces the

SCC to connect TxD to RxD and to begin searching the in-

coming data stream so that it can go on loop. All bits perti-

nent to SDLC mode operation in other registers are set be-

fore this mode is selected. The transmitter and receiver are

not enabled until after this mode has been selected. As

soon as the Go-Active-On-Poll bit is set and an EOP is re-

ceived, the SCC goes on-loop. If this bit is reset after the

SCC goes on-loop, the SCC waits for the next EOP to go

off-loop.

/RTxC Xtal//No Xtal

Figure 5-14. Write Register 11

Bit 7: RTxC-XTAL//NO XTAL select bit

This bit controls the type of input signal the SCC expects

to see on the /RTxC pin. If this bit is set to 0, the SCC ex-

pects a TTL-compatible signal as an input to this pin. If this

bit is set to 1, the SCC connects a high-gain amplifier be-

tween the /RTxC and /SYNC pins in expectation of a

quartz crystal being placed across the pins.

In synchronous modes, the SCC uses this bit, along with

the Go-Active-On-Poll bit, to synchronize the transmitter to

the receiver. The receiver should not be enabled until after

this mode is selected. The TxD pin is held marking when

this mode is selected unless a break condition is pro-

grammed. The receiver waits for a sync character to be re-

ceived and then enables the transmitter on a character

boundary. The break condition, if programmed, is re-

moved. This mode works properly with sync characters of

6, 8, or 16 bits. This bit is ignored in Asynchronous mode

and is reset by a channel or hardware reset.

The output of this oscillator is available for use as a clock-

ing source. In this mode of operation, the /SYNC pin is un-

available for other use. The /SYNC signal is forced to zero

internally. A hardware reset forces /NO XTAL. (At least 20

ms should be allowed after this bit is set to allow the oscil-

lator to stabilize.)

Bits 6 and 5: Receiver Clock select bits 1 and 0

These bits determine the source of the receive clock as

shown in Table 5-8. They do not interfere with any of the

modes of operation in the SCC, but simply control a multi-

plexer just before the internal receive clock input. A hard-

ware reset forces the receive clock to come from the /RTxC

pin.

Bit 0: 6-Bit/8-Bit SYNC select bit

This bit is used to select a special case of synchronous

modes. If this bit is set to 1 in Monosync mode, the receiv-

er and transmitter sync characters are six bits long in-

stead of the usual eight. If this bit is set to 1 in Bisync

mode, the received sync is 12 bits and the transmitter

sync character remains 16 bits long. This bit is ignored in

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5.1 INTRODUCTION (Continued)

Table 5-8. Receive Clock Source

used by the receiver. Hardware reset selects the XTAL os-

cillator as the output source.

Bit 6

Bit 5

Receive Clock

Table 5-10. Transmit External Control Selection

0

1

0

1

0

1

/RTxC Pin

/TRxC Pin

BR Output

DPLL Output

Bit 1

Bit 0

TRxC Pin Output

0

1

0

1

0

1

XTAL Oscillator Output

Transmit Clock

BR Output

Bits 4 and 3: Transmit Clock select bits 1 and 0.

These bits determine the source of the transmit clock as

shown in Table 5-9. They do not interfere with any of the

modes of operation of the SCC, but simply control a multi-

plexer just before the internal transmit clock input. The

DPLL output that is used to feed the transmitter in FM

modes lags by 90 degrees the output of the DPLL used by

the receiver. This makes the received and transmitted bit

cells occur simultaneously, neglecting delays. A hardware

reset selects the /TRxC pin as the source of the transmit

clocks.

DPLL Output (receive)

5.2.15 Write Register 12 (Lower Byte of Baud

Rate Generator Time Constant)

WR12 contains the lower byte of the time constant for the

baud rate generator. The time constant can be changed at

any time, but the new value does not take effect until the

next time the time constant is loaded into the down

counter. No attempt is made to synchronize the loading of

the time constant into WR12 and WR13 with the clock driv-

ing the down counter. For this reason, it is advisable to dis-

able the baud rate generator while the new time constant

is loaded into WR12 and WR13. Ordinarily, this is done

anyway to prevent a load of the down counter between the

writing of the upper and lower bytes of the time constant.

Table 5-9. Transmit Clock Source

Bit 4

Bit 3

Transmit Clock

0

1

0

1

0

1

/RTxC Pin

/TRxC Pin

BR Output

DPLL Output

The formula for determining the appropriate time constant

for a given baud is shown below, with the desired rate in

bits per second and the BR clock period in seconds. This

formula is derived because the counter decrements from N

down to zero-plus-one-cycle for reloading the time con-

stant. This is then fed to a toggle flip-flop to make the out-

put a square wave. Bit positions for WR12 are shown in

Figure 5-15.

Bit 2: TRxC Pin I/O control bit

This bit determines the direction of the /TRxC pin. If this bit

is set to 1, the /TRxC pin is an output and carries the signal

selected by D1 and D0 of this register. However, if either

the receive or the transmit clock is programmed to come

from the /TRxC pin, /TRxC is an input, regardless of the

state of this bit. The /TRxC pin is also an input if this bit is

set to 0. A hardware reset forces this bit to 0.

Clock Frequency

Time

=

- 2

Constant

2 x (Desired Rate) x (BR Clock Period)

Bits 1 and 0: /TRxC Output Source select bits 1 and 0

These bits determine the signal to be echoed out of the

SCC via the /TRxC pin as given in Table 5-10. No signal is

produced if /TRxC has been programmed as the source of

either the receive or the transmit clock. If /TRxC O/I (bit 2)

is set to 0, these bits are ignored.

Write Register 12

D7 D6 D5 D4 D3 D2 D1 D0

TC0

TC1

TC2

TC3

TC4

TC5

TC6

TC7

If the XTAL oscillator output is programmed to be echoed,

and the XTAL oscillator is not enabled, the /TRxC pin goes

High. The DPLL signal that is echoed is the DPLL signal

Lower Byte of

Time Constant

Figure 5-15. Write Register 12

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Register Descriptions

source to the /RTxC pin and selects NRZI mode. The Enter

Search Mode command enables the DPLL after a reset.

5.2.16 Write Register 13 (Upper Byte of Baud

Rate Generator Time Constant)

WR13 contains the upper byte of the time constant for the

baud rate generator. Bit positions for WR13 are shown in

Figure 5-16.

Null Command (000). This command has no effect on

the DPLL.

5

Enter Search Mode Command (001). Issuing this com-

mand causes the DPLL to enter the Search mode, where

the DPLL searches for a locking edge in the incoming data

stream. The action taken by the DPLL upon receipt of this

command depends on the operating mode of the DPLL.

Write Register 13

D7 D6 D5 D4 D3 D2 D1 D0

TC8

TC9

TC10

In NRZI mode, the output of the DPLL is High while the

DPLL is waiting for an edge in the incoming data stream.

After the Search mode is entered, the first edge the DPLL

sees is assumed to be a valid data edge, and the DPLL be-

gins the clock recovery operation from that point. The

DPLL clock rate must be 32x the data rate in NRZI mode.

Upon leaving the Search mode, the first sampling edge of

the DPLL occurs 16 of these 32x clocks after the first data

edge, and the second sampling occurs 48 of these 32x

clocks after the first data edge. Beyond this point, the

DPLL begins normal operation, adjusting the output to re-

main in sync with the incoming data.

TC11

Upper Byte of

Time Constant

TC12

TC13

TC14

TC15

Figure 5-16. Write Register 13

5.2.17 Write Register 14 (Miscellaneous Con-

trol Bits)

In FM mode, the output of the DPLL is Low while the DPLL

is waiting for an edge in the incoming data stream. The first

edge the DPLL detects is assumed to be a valid clock

edge. For this to be the case, the line must contain only

clock edges; i.e. with FM1 encoding, the line must be con-

tinuous 0s. With FM0 encoding the line must be continu-

ous 1s, whereas Manchester encoding requires alternat-

ing 1s and 0s on the line. The DPLL clock rate must be 16

times the data rate in FM mode. The DPLL output causes

the receiver to sample the data stream in the nominal cen-

ter of the two halves of the bit to decide whether the data

was a 1 or a 0.

WR14 contains some miscellaneous control bits. Bit

positions for WR14 are shown in Figure 5-17. For DPLL

function, refer to section 3.4 as well.

Write Register 14

D7 D6 D5 D4 D3 D2 D1 D0

BR Generator Enable

BR Generator Source

/DTR/Request Function

Auto Echo

After this command is issued, as in NRZI mode, the DPLL

starts sampling immediately after the first edge is detect-

ed. (In FM mode, the DPLL examines the clock edge of ev-

ery other bit to decide what correction must be made to re-

main in sync.) If the DPLL does not see an edge during the

expected window, the one clock missing bit in RR10 is set.

If the DPLL does not see an edge after two successive at-

tempts, the two clocks missing bits in RR10 are set and the

DPLL automatically enters the Search mode. This com-

mand resets both clocks missing latches.

Local Loopback

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Null Command

Enter Search Mode

Reset Missing Clock

Disable DPLL

Set Source = BR Generator

Set Source = /RTxC

Set FM Mode

Set NRZI Mode

Reset Clock Missing Command (010). Issuing this com-

mand disables the DPLL, resets the clock missing latches

in RR10, and forces a continuous Search mode state.

Figure 5-17. Write Register 14

Bits D7-D5: Digital Phase-Locked Loop Command

Bits.

Disable DPLL Command (011). Issuing this command

disables the DPLL, resets the clock missing latches in

RR10, and forces a continuous Search mode state.

These three bits encode the eight commands for the Digi-

tal Phase-Locked Loop. A channel or hardware reset dis-

ables the DPLL, resets the missing clock latches, sets the

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5.1 INTRODUCTION (Continued)

Set Source to BRG Command (100). Issuing this com-

mand forces the clock for the DPLL to come from the out-

put of the BRG.

as the /W/REQ pin if WR7' D4=1. This bit is reset by a

channel or hardware reset.

Bit 1: Baud Rate Generator Source select bit

Set Source to /RTxC Command (101). Issuing the com-

mand forces the clock for the DPLL to come from the

/RTxC pin or the crystal oscillator, depending on the state

of the XTAL/no XTAL bit in WR11. This mode is selected

by a channel or hardware reset.

This bit selects the source of the clock for the baud rate

generator, If this bit is set to 0. The baud rate generator

clock comes from either the /RTxC pin or the XTAL oscil-

lator (depending on the state of the XTAL//no XTAL bit). If

this bit is set to 1, the clock for the baud rate generator is

the SCC’s PCLK input. Hardware reset sets this bit to 0,

select the /RTxC pin as the clock source for the BRG.

Set FM Mode Command (110). This command forces the

DPLL to operate in the FM mode and is used to recover the

clock from FM or Manchester-Encoded data. (Manchester

is decoded by placing the receiver in NRZ mode while the

DPLL is in FM mode.)

Bit 0: Baud Rate Generator Enable

This bit controls the operation of the BRG. The counter in

the BRG is enabled for counting when this bit is set to 1,

and counting is inhibited when this bit is set to 0. When this

bit is set to 1, change in the state of this bit is not reflected

by the output of the BRG for two counts of the counter.

This allows the command to be synchronized. However,

when set to 0, disabling is immediate. This bit is reset by a

hardware reset.

Set NRZI Mode Command (111). Issuing this command

forces the DPLL to operate in the NRZI mode. This mode

is also selected by a hardware or channel reset.

Bit 4: Local Loopback select bit

Setting this bit to 1 selects the Local Loopback mode of op-

eration. In this mode, the internal transmitted data is routed

back to the receiver, and to the TxD pin. The /CTS and

/DCD inputs are ignored as enables in Local Loopback

mode, even if auto enable is selected. (If so programmed,

transitions on these inputs still cause interrupts.) This

mode works with any Transmit/Receive mode except Loop

mode. For meaningful results, the frequency of the trans-

mit and receive clocks must be the same. This bit is reset

by a channel or hardware reset.

5.2.18 Write Register 15 (External/Status In-

terrupt Control)

WR15 is the External/Status Source Control register. If the

External/Status interrupts are enabled as a group via

WR1, bits in this register control which External/Status

conditions cause an interrupt. Only the External/Status

conditions that occur after the controlling bit is set to 1

cause an interrupt. This is true, even if an External/Status

condition is pending at the time the bit is set. Bit positions

for WR15 are shown in Figure 5-18.

Bit 3: Auto Echo select bit

Setting this bit to 1 selects the Auto Echo mode of opera-

tion. In this mode, the TxD pin is connected to RxD as in

Local Loopback mode, but the receiver still listens to the

RxD input. Transmitted data is never seen inside or out-

side the SCC in this mode, and /CTS is ignored as a trans-

mit enable. This bit is reset by a channel or hardware reset.

On the CMOS version, bits D2 and D0 are reserved. On

the NMOS version, bit D2 is reserved. These reserved bits

should be written as 0s.

Write Register 15

D7 D6 D5 D4 D3 D2 D1 D0

Bit 2: DTR/Request Function select bit

This bit selects the function of the /DTR//REQ pin following

the state of the DTR bit in WR5. If this is set to 0, the

/DTR//REQ pin follows the state of the DTR bit in WR5. If

this bit is set to 1, the /DTR//REQ pin goes Low whenever

the transmit buffer becomes empty and in any of the syn-

chronous modes when the CRC has been sent at the end

of a message. The request function on the /DTR//REQ pin

differs from the transmit request function available on the

/W//REQ pin. The /REQ does not go inactive until the inter-

nal operation satisfying the request is complete, which oc-

curs three to four PCLK cycles after the falling edge of /DS,

/RD or /WR. If the DMA used is edge-triggered, this differ-

ence is unimportant. The deassertion timing of the REQ

mode can be programmed to occur with the same timing

WR7' SDLC Feature Enable

(Reserved on NMOS/CMOS)

Zero Count IE

SDLC FIFO Enable (Reserved on NMOS)

DCD IE

Sync/Hunt IE

CTS IE

Tx Underrun/EOM IE

Break/Abort IE

Figure 5-18. Write Register 15

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Register Descriptions

Bit 7: Brea/Abort Interrupt Enable

Residue, Overrun, and CRC Error) and fourteen bits of

byte count are held in the Status FIFO until read. Status in-

formation for up to ten frames can be stored. If this bit is

reset (0) or if the CMOS/ESCC is not in the SDLC/HDLC

Mode, the FIFO is not operational and status information

read reflects the current status only. This bit is reset to 0

by a channel or hardware reset. For details on this func-

tion, refer to Section 4.4.3.

If this bit is set to 1, a change in the Break/Abort status of

the receiver causes an External/Status interrupt. This bit is

set by a channel or hardware reset.

5

Bit 6: Transmit Underrun/EOM Interrupt Enable

If this bit is set to 1, a change of state by the Tx Under-

run/EOM latch in the transmitter causes an Exter-

nal/Status interrupt. This bit is set to 1 by a channel or

hardware reset.

On the NMOS version, this bit is reserved and should be

programmed as 0.

Bit 5: CTS Interrupt Enable

If this bit is set to 1, a change of state on the /CTS pin caus-

es an External/Status Interrupt. This bit is set by a channel

or hardware reset.

Bit 1: Zero Count Interrupt Enable

If this bit is set to 1, an External/Status interrupt is gener-

ated whenever the counter in the baud rate generator

reaches 0. This bit is reset to 0 by a channel or hardware

reset.

Bit 4: SYNC/Hunt Interrupt Enable

If this bit is set to 1, a change of state on the /SYNC pin

causes an External/Status interrupt in Asynchronous

mode, and a change of state in the Hunt bit in the receiver

causes and External/Status interrupt in synchronous

modes. This bit is set by a channel or hardware reset.

Bit 0: Point to Write Register WR7 Prime (ESCC and

85C30 only)

When this bit is programmed to 0, writes to the WR7 ad-

dress are made to WR7. When this bit is programmed to

1, writes to the WR7 address are made to WR7 Prime.

Once set, this bit remains set unless cleared by writing a 0

to this bit or by a hardware or software reset. Note that if

the extended read option is enabled, WR7 Prime is read in

RR14. For details about WR7', refer to Section 4.4.1.2 and

Section 5.2.9.

Bit 3: DCD Interrupt Enable

If this bit is set to 1, a change of state on the /DCD pin

causes an External/Status interrupt. This bit is set by a

channel or hardware reset.

Bit 2: Status FIFO Enable control bit (CMOS/ESCC)

If this bit is set and if the CMOS/ESCC is in the

SDLC/HDLC Mode, status (five bits from Read Register 1:

On the NMOS/CMOS version, this bit is reserved and

should be programmed as 0.

5.3 READ REGISTERS

The SCC Read register set in each channel has four status

registers (includes receive data FIFO), and two baud rate

time constant registers in each channel. The Interrupt Vec-

tor register (RR2) and Interrupt Pending register (RR3) are

shared by both channels. In addition to these, the

CMOS/ESCC has two additional registers for the SDLC

Frame Status FIFO. On the ESCC, if that function is en-

abled (WR7' bit D6=1), five more registers are available

which return the value written to the write registers.

An enhancement allows the ESCC and 85C30 to latch the

contents of RR0 during read transactions for this register.

The latch is released on the rising edge of the /RD of the

read transaction to this register. This feature prevents

missed status due to changes that take place when the

read cycle is in progress.

Read Register 0

D7 D6 D5 D4 D3 D2 D1 D0

The status of these registers is continually changing and

depends on the mode of communication, received and

transmitted data, and the manner in which this data is

transferred to and from the CPU. The following description

details the bit assignment for each register.

Rx Character Available

Zero Count

Tx Buffer Empty

DCD

5.3.1 Read Register 0 (Transmit/Receive

Buffer Status and External Status)

Sync/Hunt

CTS

Read Register 0 (RR0) contains the status of the receive

and transmit buffers. RR0 also contains the status bits for

the six sources of External/Status interrupts. The bit con-

figuration is illustrated in Figure 5-19.

Tx Underrun/EOM

Break/Abort

Figure 5-19. Read Register 0

On the NMOS/CMOS version, note that the status of this

register might be changing during the read.

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5.3 READ REGISTERS (Continued)

Bit 7: Break/Abort status

In Asynchronous mode, the operation of this bit is identical

to that of the CTS status bit, except that this bit reports the

state of the /SYNC pin.

In the Asynchronous mode, this bit is set when a Break se-

quence (null character plus framing error) is detected in

the receive data stream. This bit is reset when the se-

quence is terminated, leaving a single null character in the

Receive FIFO. This character is read and discarded. In

SDLC mode, this bit is set by the detection of an Abort se-

quence (seven or more 1s), then reset automatically at the

termination of the Abort sequence. In either case, if the

Break/Abort IE bit is set, an External/Status interrupt is ini-

tiated. Unlike the remainder of the External/Status bits,

both transitions are guaranteed to cause an External/Sta-

tus interrupt, even if another External/Status interrupt is

pending at the time these transitions occur. This procedure

is necessary because Abort or Break conditions may not

persist.

In External sync mode the /SYNC pin is used by external

logic to signal character synchronization. When the Enter

Hunt Mode command is issued in External Sync mode, the

/SYNC pin must be held High by the external sync logic un-

til character synchronization is achieved. A High on the

/SYNC pin holds the Sync/Hunt bit in the reset condition.

When external synchronization is achieved, /SYNC is driv-

en Low on the second rising edge of the Receive Clock af-

ter the last rising edge of the Receive Clock on which the

last bit of the receive character was received. Once /SYNC

is forced Low, it is good practice to keep it Low until the

CPU informs the external sync logic that synchronization is

lost or that a new message is about to start. Both transi-

tions on the /SYNC pin cause External/Status interrupts if

the Sync/Hunt IE bit is set to 1.

Bit 6: Transmit Underrun/EOM status

This bit is set by a channel or hardware reset when the

transmitter is disabled or a Send Abort command is issued.

This bit is only reset by the reset Tx Underrun/EOM Latch

command in WR0. When the Transmit Underrun occurs,

this bit is set and causes an External/Status interrupt (if the

Tx Underrun/EOM IE bit is set).

The Enter Hunt Mode command should be issued when-

ever character synchronization is lost. At the same time,

the CPU should inform the external logic that character

synchronization has been lost and that the SCC is waiting

for /SYNC to become active.

Only the 0-to-1 transition of this bit causes an interrupt.

This bit is always 1 in Asynchronous mode, unless a reset

Tx Underrun/EOM Latch command has been erroneously

issued. In this case, the Send Abort command can be used

to set the bit to one and at the same time cause an Exter-

nal/Status interrupt.

In the Monosync and Bisync Receive modes, the

Sync/Hunt status bit is initially set to 1 by the Enter Hunt

Mode command. The Sync/Hunt bit is reset when the SCC

established character synchronization. Both transitions

cause External/Status interrupts if the Sync/Hunt IE bit is

set. When the CPU detects the end of message or the loss

of character synchronization, the Enter Hunt Mode com-

mand should be issued to set the Sync/Hunt bit and cause

an External/Status interrupt. In this mode, the /SYNC pin

is an output, which goes Low every time a sync pattern is

detected in the data stream.

Bit 5: Clear to Send pin status

If the CTS IE bit in WR15 is set, this bit indicates the state

of the /CTS pin while no interrupt is pending, latches the

state of the /CTS pin and generates an External/Status in-

terrupt. Any odd number of transitions on the /CTS pin

causes another External/Status interrupt condition. If the

CTS IE bit is reset, it merely reports the current unlatched

state of the /CTS pin.

In the SDLC modes, the Sync/Hunt bit is initially set by

the Enter Hunt Mode command or when the receiver is

disabled. It is reset when the opening flag of the first

frame is detected by the SCC. An External/Status inter-

rupt is also generated if the Sync/Hunt IE bit is set. Unlike

the Monosync and Bisync modes, once the Sync/Hunt bit

is reset in SDLC mode, it does not need to be set when

the end of the frame is detected. The SCC automatically

maintains synchronization. The only way the Sync/Hunt

bit is set again is by the Enter Hunt Mode command or by

disabling the receiver.

Bit 4: Sync/Hunt status

The operation of this bit is similar to that of the CTS bit, ex-

cept that the condition monitored by the bit varies depend-

ing on the mode in which the SCC is operating.

When the XTAL oscillator option is selected in asynchro-

nous modes, this bit is forced to 0 (no External/Status in-

terrupt is generated). Selecting the XTAL oscillator in syn-

chronous or SDLC modes has no effect on the operation

of this bit.

Bit 3: Data Carrier Detect status

The XTAL oscillator should not be selected in External

Sync mode.

If the DCD IE bit in WR15 is set, this bit indicates the state

of the /DCD pin the last time the Enabled External/Status

bits changed. Any transition on the /DCD pin, while no in-

terrupt is pending, latches the state of the /DCD pin and

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Register Descriptions

generates an External/Status interrupt. Any odd number of

transitions on the /DCD pin while another External/Status

interrupt condition. If the DCD IE is reset, this bit merely re-

ports the current, unlatched state of the /DCD pin.

5.3.2 Read Register 1

RR1 contains the Special Receive Condition status bits

and the residue codes for the l-field in SDLC mode. Figure

5-20 shows the bit positions for RR1.

5

Bit 2: TX Buffer Empty status

This bit is set to 1 when the transmit buffer is empty. It is

reset while the CRC is sent in a synchronous or SDLC

mode and while the transmit buffer is full. The bit is reset

when a character is loaded into the transmit buffer.

Read Register 1

D7 D6 D5 D4 D3 D2 D1 D0

All Sent

On the ESCC, the status of this bit is not related to the

Transmit Interrupt Status or the state of WR7' bit D5, but it

shows the status of the entry location of the Transmit

FIFO. This means more data can be written without being

overwritten. This bit is set to 1 when the entry location of

the Transmit FIFO is empty. It is reset when a character is

loaded into the entry location of the Transmit FIFO.

Residue Code 2

Residue Code 1

Residue Code 0

Parity Error

Rx Overrun Error

CRC/Framing Error

End of Frame (SDLC)

This bit is always in the set condition after a hardware or

channel reset.

Figure 5-20. Read Register 1

For more information on this bit, refer to Section 2.4.8

“Transmit Interrupts and Transmit Buffer Empty bit”.

Bit 7: End of Frame (SDLC) status

This bit is used only in SDLC mode and indicates that a

valid closing flag has been received and that the CRC Er-

ror bit and residue codes are valid. This bit is reset by is-

suing the Error Reset command. It is also updated by the

first character of the following frame. This bit is reset in any

mode other than SDLC.

Bit 1: Zero Count status

If the Zero Count interrupt Enable bit is set in WR15, this

bit is set to one while the counter in the baud rate genera-

tor is at the count of zero. If there is no other External/Sta-

tus interrupt condition pending at the time this bit is set, an

External/Status interrupt is generated. However, if there is

another External/Status interrupt pending at this time, no

interrupt is initiated until interrupt service is complete. If the

Zero Count condition does not persist beyond the end of

the interrupt service routine, no interrupt is generated. This

bit is not latched High, even though the other External/Sta-

tus latches close as a result of the Low-to-High transition

on ZC. The interrupt routine checks the other External/Sta-

tus conditions for changes. If none changed, ZC was the

source. In polled applications, check the IP bit in RR3A for

a status change and then proceed as in the interrupt ser-

vice routine.

Bit 6: CRC/Framing Error status

If a framing error occurs (in Asynchronous mode), this bit

is set (and not latched) for the receive character in which

the framing error occurred. Detection of a framing error

adds an additional one-half bit to the character time so that

the framing error is not interpreted as a new Start bit. In

Synchronous and SDLC modes, this bit indicates the re-

sult of comparing the CRC checker to the appropriate

check value. This bit is reset by issuing an Error Reset

command, but the bit is never latched. Therefore, it is al-

ways updated when the next character is received. When

used for CRC error status in Synchronous or SDLC

modes, this bit is usually set since most bit combinations,

except for a correctly completed message, result in a non-

zero CRC.

Bit 0: Receive Character Available

This bit is set to 1 when at least one character is available

in the receive data FIFO. It is reset when the receive data

FIFO is completely empty. A channel or hardware reset

empties the receive data FIFO.

On the CMOS and ESCC, if the Status FIFO is enabled (re-

fer to the description in Write Register 15, bit D2 and the de-

scription in Read Register 7, bits D7 and D6), this bit reflects

the status stored at the exit location of the Status FIFO.

On the ESCC, the status of this bit is independent of WR7'

bit D3.

For details on this bit, refer to Section 2.4.7, The Receive

Interrupt.

Bit 5: Receiver Overrun Error status

This bit indicates that the Receive FIFO has overflowed.

Only the character that has been written over is flagged

with this error. When that character is read, the Error con-

dition is latched until reset by the Error Reset command.

5-23

UM010901-0601

SCC™/ESCC™ User’s Manual

Register Descriptions

5.3 READ REGISTERS (Continued)

Also, a Special Receive Condition vector is returned,

caused by the overrun characters and all subsequent char-

acters received until the Error Reset command is issued.

is not an integral multiple of the character length, these

three bits indicate the length of the I-Field and are mean-

ingful only for the transfer in which the end of frame bit is

set. This field is set to 011 by a channel or hardware reset

and is forced to this state in Asynchronous mode. These

three bits can leave this state only if SDLC is selected and

a character is received. The codes signify the following

(Reference Table 5-11) when a receive character length is

eight bits per character.

On the CMOS and ESCC, if the Status FIFO is enabled

(refer to the description in Write Register 15, bit D2 and the

description in Read Register 7, bits D7 and D6), this bit re-

flects the status stored at the exit location of the Status

FIFO.

Bit 4: Parity Error status.

On the CMOS and ESCC, if the Status FIFO is enabled

(refer to the description in Write Register 15, bit D2 and the

description in Read Register 7, bits D7 and D6), these bits

reflect the status stored at the exit location of the Status

FIFO.

When parity is enabled, this bit is set for the characters

whose parity does not match the programmed sense

(even/odd). This bit is latched so that once an error occurs,

it remains set until the Error Reset command is issued. If

the parity in Special Condition bit is set, a parity error caus-

es a Special Receive Condition vector to be returned on

the character containing the error and on all subsequent

characters until the Error Reset command is issued.

I-Field bits are right-justified in all cases. If a receive

character length other than eight bits is used for the I-Field,

a table similar to Table 5-11 can be constructed for each

different character length. Table 5-12 shows the residue

codes for no residue (The I-Field boundary lies on a

character boundary).

Bits 3, 2, and 1: Residue Codes, bits 2, 1, and 0

In those cases in SDLC mode where the received I-Field

Table 5-11. I-Field Bit Selection (8 Bits Only)

I-Field Bits in Last

I-Field Bits in

Previous Byte

Bit 3

Bit 2

Bit 1

Byte

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

Table 5-12. Bits per Character Residue Decoding

5.3.3 Read Register 2

RR2 contains the interrupt vector written into WR2. When

the register is accessed in Channel A, the vector returned

is the vector actually stored in WR2. When this register is

accessed in Channel B, the vector returned includes

status information in bits 1, 2 and 3 or in bits 6, 5 and 4,

depending on the state of the Status High/Status Low bit

in WR9 and independent of the state of the VIS bit in

WR9. The vector is modified according to Table 5-6

shown in the explanation of the VIS bit in WR9 (Section

5.2.11). If no interrupts are pending, the status is

V3,V2,V1 -011, or V6,V5,V4-110. Figure 5-21 shows the

bit positions for RR2.

Bits per Character

Bit 3

Bit 2

Bit 1

8

7

6

5

0

1

0

1

0

1

0

1

Bit 0: All Sent status

In Asynchronous mode, this bit is set when all characters

have completely cleared the transmitter pins. Most mo-

dems contain additional delays in the data path, which re-

quires the modem control signals to remain active until af-

ter the data has cleared both the transmitter and the

modem. This bit is always set in synchronous and SDLC

modes.

UM010901-0601

5-24

SCC™/ESCC™ User’s Manual

Register Descriptions

5.3.6 Read Register 5 (ESCC and 85C30 Only)

Read Register 2

On the ESCC, Read Register 5 reflects the contents of

Write Register 5 provided the Extended Read option is en-

abled. Otherwise, this register returns an image of RR1.

D7 D6 D5 D4 D3 D2 D1 D0

5

V0

V1

V2

V3

V4

V5

V6

V7

On the NMOS/CMOS version, a read to this register re-

turns an image of RR1.

Interrupt

Vector

5.3.7 Read Register 6 (Not on NMOS)

*

On the CMOS and ESCC, Read Register 6 contains the

least significant byte of the frame byte count that is current-

ly at the top of the Status FIFO. RR6 is shown in Figure 5-

23. This register is readable only if the FIFO is enabled (re-

fer to the description Write Register 15, bit D2 and Section

4.4.3). Otherwise, this register is an image of RR2.

*

Modified In B Channel

On the NMOS version, a read to this register location re-

turns an image of RR2.

Figure 5-21. Read Register 2

5.3.4 Read Register 3

5.3.8 Read Register 7 (Not on NMOS)

RR3 is the interrupt Pending register. The status of each

of the interrupt Pending bits in the SCC is reported in this

register. This register exists only in Channel A. If this

register is accessed in Channel B, all 0s are returned. The

two unused bits are always returned as 0. Figure 5-22

shows the bit positions for RR3.

On the CMOS and ESCC, Read Register 7 contains the

most significant six bits of the frame byte count that is

currently at the top of the Status FIFO. Bit D7 is the FIFO

Overflow Status and bit D6 is the FIFO Data Available

Status. The status indications are given in Table 5-13. RR7

is shown in Figure 5-24. This register is readable only if the

FIFO is enabled (refer to the description Write Register 15,

bit D2). Otherwise this register is an image of RR3. Note,

for proper operation of the FIFO and byte count logic, the

registers should be read in the following order: RR7, RR6,

RR1.

Read Register 3

D7 D6 D5 D4 D3 D2 D1 D0

Channel B Ext/Status IP

Channel B Tx IP

Read Register 6

*

Channel B Rx IP

*

Channel A Ext/Status IP

D7 D6 D5 D4 D3 D2 D1 D0

Channel A Tx IP

Channel A Rx IP

BC0

BC1

BC2

BC3

BC4

BC5

BC6

BC7

0

* ^{Always 0 In B Channel}

Figure 5-22. Read Register 3

5.3.5 Read Register 4 (ESCC and 85C30 Only)

*

Can only be accessed if the SDLC FIFO enhancement

is enabled (WR15 bit D2 set to 1)

On the ESCC, Read Register 4 reflects the contents of

Write Register 4 provided the Extended Read option is en-

abled. Otherwise, this register returns an image of RR0.

SDLC FIFO Status and Byte Count (LSB)

On the NMOS/CMOS version, a read to this location re-

turns an image of RR0.

Figure 5-23. Read Register 6 (Not on NMOS)

5-25

UM010901-0601

SCC™/ESCC™ User’s Manual

Register Descriptions

5.3 READ REGISTERS (Continued)

5.3.11 Read Register 10

Read Register 7 *

RR10 contains some miscellaneous status bits. Unused

bits are always 0. Bit positions for RR10 are shown in

Figure 5-25.

D7 D6 D5 D4 D3 D2 D1 D0

BC8

BC9

Read Register 10

BC10

BC11

BC12

D7 D6 D5 D4 D3 D2 D1 D0

BC13

0

FDA: FIFO Data Available

1 = Status Reads from FIFO

0 = Status Reads from ESCC

On Loop

0

FOS: FIFO Overflow Status

1 = FIFO Overflowed

0

0 = Normal

Loop Sending

0

* Can only be accessed if the SDLC FIFO enhancement

is enabled (WR15 bit D2 set to 1)

Two Clocks Missing

One Clock Missing

SDLC FIFO Status and Byte Count (MSB)

Figure 5-24. Read Register 7 (Not on NMOS)

Figure 5-25. Read Register 10

Table 5-13. .Read Register 7 FIFO Status Decoding

Bit 7: One Clock Missing status

Bit D7

FIFO Data Available Status

While operating in the FM mode, the DPLL sets this bit to

1 when it does not see a clock edge on the incoming lines

in the window where it expects one. This bit is latched until

reset by a Reset Missing Clock or Enter Search Mode

command in WR14. In the NRZI mode of operation and

while the DPLL is disabled, this bit is always 0.

1

Status reads come from FIFO

(FIFO is not Empty)

Status reads bypass FIFO

because FIFO is Empty)

0

Bit D6

FIFO Overﬂow Status

Bit 6: Two Clocks Missing status

1

0

FIFO has overﬂowed

Normal operation

While operating in the FM mode, the DPLL sets this bit to

1 when it does not see a clock edge in two successive

tries. At the same time the DPLL enters the Search mode.

This bit is latched until reset by a Reset Missing Clock or

Enter Search Mode command in WR14, bit 5-7. In the

NRZI mode of operation and while the DPLL is disabled,

this bit is always 0.

If the FIFO overflows, the FIFO and the FIFO Overflow

Status bit are cleared by disabling and then re-enabling the

FIFO through the FIFO control bit (WR15, D2). Otherwise,

this register returns an image of RR3.

On the NMOS version, a read to this location returns an

image of RR3.

Bit 4: Loop Sending status

This bit is set to 1 in SDLC Loop mode while the transmitter

is in control of the Loop, that is, while the SCC is actively

transmitting on the loop. This bit is reset at all other times.

5.3.9 Read Register 8

RR8 is the Receive Data register.

This bit can be polled in SDLC mode to determine when

the closing flag has been sent.

5.3.10 Read Register 9 (ESCC and 85C30

Only)

Bit 1: On Loop status

On the ESCC, Read Register 9 reflects the contents of

Write Register 3 provided the Extended Read option has

been enabled.

This bit is set to 1 while the SCC is actually on loop in

SDLC Loop mode. This bit is set to 1 in the X21 mode

(Loop mode selected while in monosync) when the trans-

mitter goes active. This bit is 0 at all other times. This bit

can also be pulled in SDLC mode to determine when the

closing flag has been sent.

On the NMOS/CMOS version, a read to this location re-

turns an image of RR13.

5-26

UM010901-0601

SCC™/ESCC™ User’s Manual

Register Descriptions

5.3.12 Read Register 11 (ESCC and 85C30

Only)

5.3.15 Read Register 14 (ESCC and 85C30

Only)

On the ESCC, Read Register 11 reflects the contents of

Write Register 10 provided the Extended Read option has

been enabled. Otherwise, this register returns an image of

RR15.

5

On the ESCC, Read Register 14 reflects the contents of

Write Register 7 Prime provided the Extended Read option

has been enabled. Otherwise, this register returns an im-

age of RR10.

On the NMOS/CMOS version, a read to this location re-

turns an image of RR15.

On the NMOS/CMOS version, a read to this location re-

turns an image of RR10.

5.3.13 Read Register 12

5.3.16 Read Register 15

RR12 returns the value stored in WR12, the lower byte of

the time constant, for the BRG. Figure 5-26 shows the bit

positions for RR12.

RR15 reflects the value stored in WR15, the

External/Status IE bits. The two unused bits are always

returned as Os. Figure 5-28 shows the bit positions for

RR15.

Read Register 12

D7 D6 D5 D4 D3 D2 D1 D0

Read Register 15

TC0

D7 D6 D5 D4 D3 D2 D1 D0

TC1

TC2

0

TC3

Lower Byte

of Time Constant

Zero Count IE

0

TC4

TC5

TC6

DCD IE

Sync/Hunt IE

CTS IE

TC7

Tx Underrun/EOM IE

Break/Abort IE

Figure 5-26. Read Register 12

Figure 5-28. Read Register 15

5.3.14 Read Register 13

RR13 returns the value stored in WR13, the upper byte of

the time constant for the BRG. Figure 5-27 shows the bit

positions for RR13.

Read Register 13

D7 D6 D5 D4 D3 D2 D1 D0

TC8

TC9

TC10

TC11

Upper Byte

of Time Constant

TC12

TC13

TC14

TC15

Figure 5-27. Read Register 13

5-27

UM010901-0601

5-28

UM010901-0601

APPLICATION NOTE

6

®

INTERFACING Z80 CPUS TO THE Z8500

PERIPHERAL FAMILY

6

INTRODUCTION

The Z8500 Family consists of universal peripherals that

interfacing the Z8500 peripherals to the Z80 CPUs.

can interface to a variety of microprocessor systems that

use a non-multiplexed address and data bus. Though

similar to Z80 peripherals, the Z8500 peripherals differ in

the way they respond to I/O and Interrupt Acknowledge

cycles. In addition, the advanced features of the Z8500

peripherals enhance system performance and reduce

processor overhead.

Discussions center around each of the following situations:

■ Z80A 4 MHz CPU to Z8500 4 MHz peripherals

■ Z80B 6 MHz CPU to Z8500A 6 MHz peripherals

■ Z80H 8 MHz CPU to Z8500 4 MHz peripherals

■ Z80H 8 MHz CPU to Z8500A 6 MHz peripherals

To design an effective interface, the user needs an

understanding of how the Z80 Family interrupt structure

works, and how the Z8500 peripherals interact with this

structure. This application note provides basic information

on the interrupt structures, as well as a discussion of the

hardware and software considerations involved in

This application note assumes the reader has a strong

working knowledge of the Z8500 peripherals; it is not

intended as a tutorial.

CPU HARDWARE INTERFACING

The hardware interface consists of three basic groups of

signals; data bus, system control, and interrupt control,

described below. For more detailed signal information,

refer to Zilog’s DataBook, Universal Peripherals.

/WR* Write (input, active Low). /WR strobes data from the

data bus into the peripheral.

*Chip reset occurs when /RD and /WR are active

simultaneously.

Data Bus Signals

Interrupt Control

D7-D0. Data Bus (bidirectional tri-state). This bus transfers

/INTACK. Interrupt Acknowledge (input, active Low). This

signal indicates an Interrupt Acknowledge cycle and is

used with /RD to gate the interrupt vector onto the data

bus.

data between the CPU and the peripherals.

System Control Signals

AD-A0. Address Select Lines (optional). These lines

select the port and/or control registers.

/INT. Interrupt Request (output, open-drain, active Low).

/CE. Chip Enable (input, active Low). /CE is used to select

the proper peripheral for programming. /CE should be

gated with /IORQ or /MREQ to prevent spurious chip

selects during other machine cycles.

The IUS bit indicates that an interrupt is currently being

serviced by the CPU. The IUS bit is set during an Interrupt

Acknowledge cycle if the IP bit is set and the IEI line is

High. If the IEI line is Low, the IUS bit is not set, and the

device is inhibited from placing its vector onto the data bus.

In the Z80 peripherals, the IUS bit is normally cleared by

decoding the RETI instruction, but can also be cleared by

a software command (SIO). In the Z8500 peripherals, the

IUS bit is cleared only by software commands.

/RD* Read (input, active Low). /RD activates the chip-read

circuitry and gates data from the chip onto the data bus.

6-1

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

CPU HARDWARE INTERFACING (Continued)

Z80^®Interrupt Daisy-Chain Operation

Table 1. Z8500 Daisy-Chain Control Signals

In the Z80 peripherals, both the IP and IUS bits control the

IEO line and the lower portion of the daisy chain.

Truth Table for

Daisy Chain Signals

During Idle State

Truth Table for

Daisy Chain Signals

During /INTACK Cycle

When a peripheral’s IP bit is set, its IEO line is forced Low.

This is true regardless of the state of the IEI line.

Additionally, if the peripheral’s IUS bit is clear and its IEI

line High, the /INT line is also forced Low.

IEI

IP

IUS IEO

IEI IP

IUS

IEO

0

1

X

0

X

0

1

0

1

0

1

0

1

X

1

X

1

0

The Z80 peripherals sample for both /M1 and /IORQ

active, and /RD inactive to identify and Interrupt

Acknowledge cycle. When /M1 goes active and /RD is

inactive, the peripheral detects an Interrupt Acknowledge

cycle and allows its interrupt daisy chain to settle. When

the /IORQ line goes active with /M1 active, the highest

priority interrupting peripheral places its interrupt vector

onto the data bus. The IUS bit is also set to indicate that

the peripheral is currently under service. As long as the

IUS bit is set, the IEO line is forced Low. This inhibits any

lower priority devices from requesting an interrupt. When

the Z80 CPU executes the RETI instruction, the

peripherals monitor the data bus and the highest priority

device under service resets its IUS bit.

IEI. Interrupt Enable In (Input, active High).

IEO. Interrupt Enable Out (output, active High).

These lines control the interrupt daisy chain for the

peripheral interrupt response.

Z8500 I/O Operation

The Z8500 peripherals generate internal control signals

from /RD and /WR. Since PCLK has not required phase

relationship to /RD or /WR, the circuitry generating these

signals provides time for metastable conditions to

disappear.

Z8500 Interrupt Daisy-Chain Operation

The Z8500 peripherals are initialized for different operating

modes by programming the internal registers. These

internal registers are accessed during I/O Read and Write

cycles, which are described below.

In the Z8500 peripherals, the IUS bit normally controls the

state of the IEO line. The IP bit affects the daisy chain only

during an Interrupt Acknowledge cycle. Since the IP bit is

normally not part of the Z8500 peripheral interrupt daisy

chain, there is no need to decode the RETI instruction. To

allow for control over the daisy chain, Z8500 peripherals

have a Disable Lower Chain (DLC) software command

that pulls IEO Low. This can be used to selectively

deactivate parts of the daisy chain regardless of the

interrupt status. Table 1 shows the truth tables for the

Z8500 interrupt daisy-chain control signals during certain

cycles. Table 2 shows the interrupt state diagram for the

Z8500 peripherals.

Read Cycle Timing

Figure 1 illustrates the Z8500 Read cycle timing. All

register addresses and /INTACK must remain stable

throughout the cycle. If /CE goes active after /RD goes

active, or if /CE goes inactive before /RD goes inactive,

then the effective Read cycle is shortened.

6-2

UM010901-0601

Application Note

Interfacing Z80 CPUs to the Z8500 Peripheral Family

®

6

Figure 1. Z8500 Peripheral I/O Read Cycle Timing

Write Cycle Timing

Figure 2 illustrates the Z8500 Write cycle timing. All

register addresses and /INTACK must remain stable

throughout the cycle. If /CE goes active after /WR goes

active, or if /CE goes inactive before /WR goes inactive,

then the effective Write cycle is shortened. Data must be

available to the peripheral prior to the falling edge of /WR.

Figure 2. Z8500 Peripheral I/O Write Cycle Timing

6-3

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

PERIPHERAL INTERRUPT OPERATION

Understanding peripheral interrupt operation requires a

basic knowledge of the Interrupt Pending (IP) and Interrupt

Under Service (IUS) bits in relation to the daisy chain. Both

Z80 and Z8500 peripherals are designed in such a way

that no additional interrupts can be requested during an

Interrupt Acknowledge cycle. This allows that interrupt

daisy chain to settle, and ensures proper response of the

interrupting device.

is completed (i.e., reading a character, writing data,

resetting errors, or changing the status). When the

interrupt has been serviced, other interrupts can occur.

The Z8500 peripherals use /INTACK (Interrupt

Acknowledge) for recognition of an Interrupt Acknowledge

cycle. This pin, used in conjunction with /RD, allows the

Z8500 peripheral to gate its interrupt vector onto the data

bus. An active /RD signal during an Interrupt Acknowledge

cycle performs two functions. First, it allows the highest

priority device requesting an interrupt to place its interrupt

vector on the data bus. Secondly, it sets the IUS bit in the

highest priority device to indicate that the device is

currently under service.

The IP bit is set in the peripheral when CPU intervention is

required (such conditions as buffer empty, character

available, error detection, or status changes). The

Interrupt Acknowledge cycle does not necessarily reset

the IP bit. This bit is cleared by a software command to the

peripheral, or when the action that generated the interrupt

Figure 3. Z8500 Interrupt State Diagram

6-4

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

INPUT/OUTPUT CYCLES

Although Z8500 peripherals are designed to be as

universal as possible, certain timing parameters differ from

the standard Z80 timing. The following sections discuss

the I/O interface for each of the Z80 CPUs and the Z8500

peripherals. Figure 9 depicts logic for the Z80A CPU to

Z8500 peripherals (and Z80B CPU to Z8500A peripherals)

I/O interface as well as the Interrupt Acknowledge

interface. Figures 4 and 7 depict some of the logic used to

interface the Z80H CPU to the Z8500 and Z8500A

peripherals for the I/O and Interrupt Acknowledge

interfaces. The logic required for adding additional Wait

states into the timing flow is not discussed in the following

sections.

All setup and pulse width times for the Z8500 peripherals

are met by the standard Z80A timing. In determining the

interface necessary, the /CE signal to the Z8500

peripherals is assumed to be the decoded address

qualified with the /IORQ signal.

6

Figure 4 shows the minimum Z80A CPU to Z8500

peripheral interface timing for I/O cycles. If additional Wait

states are needed, the same number of Wait states can be

inserted for both I/O Read and Write cycles to simplify

interface logic. There are several ways to place the Z80A

CPU into a Wait condition (such as counters or shift

registers to count system clock pulses), depending upon

whether or not the user wants to place Wait states in all

I/O cycles, or only during Z8500 I/O cycles. Tables 3 and

4 list the Z8500 peripheral and the Z80A CPU timing

parameters (respectively) of concern during the I/O cycles.

Tables 5 and 6 list the equations used in determining if

these parameters are satisfied. In generating these

equations and the values obtained from them, the required

number of Wait states was taken into account. The

reference numbers in Tables 3 and 4 refer to the timing

diagram in Figure 4.

Z80A CPU to Z8500 Peripherals

No additional Wait states are necessary during the I/O

cycles, although additional Wait states can be inserted to

compensate for timing delays that are inherent in a

system. Although the Z80A timing parameters indicate a

negative value for data valid prior to /WR, this is a worse

than “worst case” value. This parameter is based upon the

longest (worst case) delay for data available from the

falling edge of the CPU clock minus the shortest (best

case) delay for CPU clock High to /WR low. The negative

value resulting from these two parameters does not occur

because the worst case of one parameter and the best

case of the other do not occur within the same device. This

indicates that the value for data available prior to /WR will

always be greater than zero.

6-5

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

INPUT/OUTPUT CYCLES (Continued)

Table 2. Z8500 Timing Parameters I/O Cycles

Worst Case

Min

Max

Units

6.

1.

2.

TsA(WR)

Address to /WR to Low Setup

Address to /RD Low Setup

Address to Read Data Valid

/CE Low to /WR Low Setup

/CE Low to /RD Low Setup

/RD Low Width

/WR Low Width

/RD Low to Read Data Valid

Write Data to /WR Low Setup

80

ns

TsA(RD)

TdA(DR)

TsCEI(WR)

TsCEI(RD)

TwRDI

TwWRI

TdRDf(DR)

TsDW(WR)

590

ns

4.

8.

3.

7.

390

ns

255

0

Table 3. Z80A Timing Parameters I/O Cycles

Min

Worst Case

Max

Units

TcC

TwCh

TfC

TdCr(A)

TdCr(RDf)

TdCr(IORQf)

TdCr(WRf)

Clock Cycle Period

Clock Cycle High Width

Clock Cycle Fall Time

Clock High to Address Valid

Clock High to /RD Low

Clock High to /IORQ Low

Clock High to /WR Low

Data to Clock Low Setup

250

110

ns

30

110

85

75

65

5.

TsD(Cf)

50

Table 4. Parameter Equations

Z8500

Z80A

Parameter

Equation

Value

Units

TsA(RD)

TdA(DR)

TdRDf(DR)

TwRD1

TsA(WR)

TsDW(WR)

TwWR1

TcC-TdCr(A)

3TcC+TwCh-TdCr(A)-TsD(Cf)

2TcC+TwCh-TsD(Cf)

2TcC+TwCh+TfC-TdCr(RDf)

TcC-TdCr (A)

140 min

800 min

460 min

525 min

140 min

>0 min

ns

2TcC+TwCh+TfC-TdCr(WRf)

560 min

.

Table 5. Parameter Equations

Z80A

Z8500

Parameter

Equation

Value

Units

TsD(Cf)

3TcC+TwCh-TdCr(A)-TdA(DR)

/RD

160 min

ns

2TcC+TwCh-TdCr(RDf)-TdRD(DR)

135 min

ns

6-6

UM010901-0601

Application Note

Interfacing Z80 CPUs to the Z8500 Peripheral Family

®

6

Figure 4. Z80A CPU to Z8500 Peripheral Minimum I/O Cycle Timing

6-7

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

Z80B CPU TO Z8500A PERIPHERALS

No additional Wait states are necessary during I/O cycles,

although Wait states can be inserted to compensate for

any systems delays. Although the Z80B timing parameters

indicate a negative value for data valid prior to /WR, this is

a worse than “worst case” value. This parameter is based

upon the longest (worst case) delay for data available from

the falling edge of the CPU clock minus the shortest (best

case) delay for CPU clock High to /WR Low. The negative

value resulting from these two parameters does not occur

because the worst case of one parameter and best case of

the other do not occur within the same device. This

indicates that the value for data available prior to /WR will

always be greater than zero.

Figure 5 shows the minimum Z80B CPU to Z8500A

peripheral interface timing for I/O cycles. If additional Wait

states are needed, the same number of Wait states can be

inserted for both I/O Read and I/O Write cycles in order to

simplify interface logic. There are several ways to place

the Z80B CPU into a Wait condition (such as counters or

shift registers to count system clock pulses), depending

upon whether or not the user wants to place Wait states in

all I/O cycles, or only during Z8500A I/O cycles. Tables 6

and 7 list the Z8500A peripheral and Z80B CPU timing

parameters (respectively) of concern during the I/O cycles.

Tables 8 and 9 list the equations used in determining if

these parameters are satisfied. In generating these

equations and the values obtained from them, the required

number of Wait states was taken into account. The

reference numbers in Tables 6 and 7 refer to the timing

diagram of Figure 5.

All setup and pulse width times for the Z8500A peripherals

are met by the standard Z80B timing. In determining the

interface necessary, the /CE signal to the Z8500A

peripherals is assumed to be the decoded address

qualified with /IORQ signal.

Figure 5. Z80B CPU to Z8500A Peripheral Minimum I/O Cycle Timing

6-8

UM010901-0601

Application Note

Interfacing Z80 CPUs to the Z8500 Peripheral Family

®

Table 6. Z8500A Timing Parameters I/O Cycles

Min

6

Worst Case

Max

Units

6.

1.

2.

TsA(WR)

TsA(RD)

TdA(DR)

Address to /WR Low Setup

Address to /RD Low Setup

Address to Read Data Valid

/CE Low to /WR Low Setup

/CE Low to /RD Low Setup

/RD Low Width

80

ns

420

ns

TsCE1(WR)

TsCE1(RD)

TwRD1

TwWR1

TdRDf(DR)

TsDW(WR)

4.

8.

3.

7.

250

ns

/WR Low Width

/RD Low to Read Data Valid

Write Data to /WR Low Setup

180

0

Table 7. Z80B Timing Parameters I/O Cycles

Worst Case

Min

Max

Units

TcC

TwCh

TfC

TdCr(A)

TdCr(RDf)

TdCR(IORQf)

TdCr(WRf)

Clock Cycle Period

165

65

ns

Clock Cycle High Width

Clock Cycle Fall Time

Clock High to Address Valid

Clock High to /RD Low

Clock High to /IORQ Low

Clock High to /WR Low

Data to Clock Low Setup

20

90

70

65

60

5.

TsD(Cf)

40

Table 8. Parameter Equations

Z8500A

Z80B

Parameter

Equation

Value

Units

TsA(RD)

TdA(DR)

TdRDf(DR)

TwRD1

TsA(WR)

TsDW(WR)

TwWR1

TcC-TdCr(A)

>75 min

430 min

345 min

325 min

75 min

ns

3TcC+TwCh-TdCr(A)-TsD(Cf)

2TcC+TwCh+TsD(Cf)

2TcC+TwCh+TfC-TdCr(RDf)

TcC-TdCr(A)

> 0 min

352 min

2 TcC+Twch+TfC-TdCr(WRf)

Table 9. Parameter Equations

Z8500A

Equation

Value

Units

3TcC+TwCh-TdCr(A)-TdA(DR)

2TcC+TwCh-TdCr(RDf)-TdRD(DR)

Z80H CPU to Z8500 Peripherals

50 min

75 min

ns

6-9

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

Z90H CPU TO Z8500 PERIPHERALS

During an I/O Read cycle, there are three Z8500

parameters that must be satisfied. Depending upon the

loading characteristics of the /RD signal, the designer may

need to delay the leading (falling) edge of /RD to satisfy the

Z8500 timing parameter TsA(RD) (Addresses Valid to /RD

Setup). Since Z80H timing parameters indicate that the

/RD signal may go Low after the falling edge of T2, it is

recommended that the rising edge of the system clock be

used to delay /RD (if necessary). The CPU must also be

placed into a Wait condition long enough to satisfy

TdA(DR) (Address Valid to Read Data Valid Delay) and

TdRDf(DR) (/RD Low to Read Data Valid Delay).

additional Wait states are needed during an I/O Write cycle

when interfacing the Z80H CPU to the Z8500 peripherals.

To simplify the I/O interface, the designer can use the

same number of Wait states for both I/O Read and I/O

Write cycles. Figure 6 shows the minimum Z80H CPU to

Z8500 peripheral interface timing for the I/O cycles

(assuming that the same number of Wait states are used

for both cycles and that both /RD and /WR need to be

delayed). Figure 8 shows two suits that can be used to

delay the leading (falling) edge of either the /RD or the /WR

signals. There are several ways to place the Z80A CPU

into a Wait condition (such as counters or shift registers to

count system clock pulses), depending upon whether or

not the use wants to place Wait states in all I/O cycles, or

only during Z8500 I/O cycles. Tables 3 and 10 list the

Z8500 peripheral and the Z80H CPU timing parameters

(respectively) of concern during the I/O cycles. Tables 13

and 14 list the equations used in determining if these

parameters are satisfied. In generating these equations

and the values obtained from them, the required number

of Wait states was taken into account. The reference

numbers in Tables 3 and 10 refer to the timing diagram of

Figure 6.

During an I/O Write cycle, there are three other Z8500

parameters that must be satisfied. Depending upon the

loading characteristics of the /WR signal and the data bus,

the designer may need to delay the leading (falling) edge

of /WR to satisfy the Z8500 timing parameters TsA(WR)

(Address Valid to /WR setup). Since Z80H timing

parameters indicate that the /WR signal may go Low after

the falling edge of T2, it is recommended that the rising

edge of the system clock be used to delay /WR (if

necessary). This delay will ensure that both parameters

are satisfied. The CPU must also be placed into a Wait

condition long enough to satisfy TwWR1 (/WR Low Pulse

Width). Assuming that the /WR signal is delayed, only two

Table 10. Z80H Timing Parameter I/O Cycles

Equation

Min

Max

Units

TcC

TwCh

TfC

TdCr(A)

TdCr(RDf)

TdCr(IORQf)

TdCr(WRf)

TsD(Cf)

Clock Cycle Period

125

55

Clock Cycle High Width

Clock Cycle Fall Time

Clock High to Address Valid

Clock High to /RD Low

Clock High to /IORQ Low

Clock High to /WR Low

Data to Clock Low Setup

ns

10

80

60

55

5.

30

Table 11. Parameter Equations

Z8500

Z80H

Parameter

Equation

Value

Units

TsA(RD)

TdA(DR)

TdRDf(DR)

TwRD1

2TcC-TdCr(A)

170 min

695 min

523 min

503 min

ns

6TcC+TwCh-TdCr(A)-TsD(Cf)

4TcC+TwCh-TsD(Cf)

4TcC+TwCh+TfC-TdCr(RDf)

/WR - delayed

TsA(WR)

2TcC-TdCr(A)

170 min

>0 min

563 min

ns

TsDW(WR)

TwWR1

4TcC+TwCh+TfC

6-10

UM010901-0601

Application Note

Interfacing Z80 CPUs to the Z8500 Peripheral Family

®

6

Figure 6. Z80H CPU to Z8500 Peripheral Minimum I/O Cycle Timing

6-11

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

Z80H CPU TO Z8500A PERIPHERALS

During an I/O Read cycle, there are three Z8500A

parameters that must be satisfied. Depending upon the

loading characteristics of the /RD signal, the designer may

need to delay the leading (falling) edge of /RD to satisfy the

Z8500A timing parameter TsA(RD) (Address Valid to /RD

Setup). Since Z80H timing parameters indicate that the

/RD signal may go Low after the falling edge of T2, it is

recommended that the rising edge of the system must also

be placed into Wait condition long enough to satisfy

TdA(DR) (Address Valid to Read Data Valid Delay) and

TdRDf(DR) (/RD Low to Read Data Valid Delay).

Assuming that the /RD signal is delayed, then only one

additional Wait state is needed during an I/O Read cycle

when interfacing the Z80H CPU to the Z8500A

peripherals.

CPU must also be placed into a Wait condition long

enough to satisfy TwWR1 (/WR Low Pulse Width).

Assuming that the /WR signal is delayed, then only one

additional Wait state is needed during an I/O Write cycle

when interfacing the Z80H CPU to the Z8500A

peripherals.

Figure 7 shows the minimum Z80H CPU to Z8500A

peripheral interface timing for the I/O cycles (assuming

that the same number of Wait states are used for both

cycles and that both /RD and /WR need to be delayed).

Figure 8 shows two circuits that may be used to delay

leading (falling) edge of either the /RD or the /WR signals.

There are several methods used to place the Z80A CPU

into a Wait condition (such as counters or shift registers to

count system clock pulses), depending upon whether or

not the user wants to place Wait states in all I/O cycles, or

only during Z8500A I/O cycles, Tables 7 and 11 list the

Z8500A peripheral and the Z80H CPU timing parameters

(respectively) of concern during the I/O cycles. Tables 14

and 15 list the equations used in determining if these

parameters are satisfied. In generating these equations

and the values obtained from them, the required number

of Wait states was taken into account. The reference

numbers in Table 4 and 11 refer to the timing diagram of

Figure 7.

During an I/O Write cycle, there are three other Z850A

parameters that have to be satisfied. Depending upon the

loading characteristics of the /WR signal and the data bus,

the designer may need to delay the leading (falling) edge

of /WR to satisfy the Z8500A timing parameters TsA(WR)

(Address Valid to /WR Setup) and TsDW(WR) (Data Valid

Prior to /WR Setup). Since Z80H timing parameters

indicate that the /WR signal may go Low after the falling

edge of T2, it is recommended that the rising edge of the

system clock be used to delay /WR (if necessary). This

delay will ensure that both parameters are satisfied. The

Table 12. Parameter Equations

Z80H

Z8500

Parameter

Equation

Value

Units

TsD(Cf)

6TcC+TwCh-TdCr(A)-TdA(DR)

/RD - delayed

135 min

ns

4TcC+TwCh+TfC-TdRD(DR)

300 min

ns

Table 13. Parameter Equations

Z8500A

Z80H

Parameter

Equation

Value

Units

TsA(RD)

TdA(DR)

TdRDf(DR)

TwRD1

2TcC-TdCr(A)

170 min

695 min

525 min

503 min

ns

6TcC+TwCh-TdCr(A)-TsD(Cf)

4TcC+TwCh-TsD(Cf)

4TcC+TwCh+TfC-TdCr(RDf)

/WR - delayed

TsA(WR)

2TcC-TdCr(A)

170 min

>0 min

313 min

ns

TsDW(WR)

TwWR1

2TcC+TwCh+TfC

6-12

UM010901-0601

Application Note

Interfacing Z80 CPUs to the Z8500 Peripheral Family

®

6

Figure 7. Z80H CPU to Z8500A Peripheral Minimum I/O Cycle Timing

6-13

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

Z80H CPU TO Z8500A PERIPHERALS (Continued)

Figure 8. Delaying /RD or /WR

Table 14. Parameter Equations

Z80H

Z8500A

Parameter

Equation

Value

Units

TsD(Cf)

4TcC+TwCh-TdCr(A)-TdA(DR)

/RS - delayed

55 min

ns

2TcC+TwCh-TdRD(DR)

125 min

ns

6-14

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

INTERRUPT ACKNOWLEDGE CYCLES

The primary timing differences between the Z80 CPUs and

Z8500 peripherals occur in the Interrupt Acknowledge

cycle. The Z8500 timing parameters that are significant

during Interrupt Acknowledge cycles are listed in Table 16,

while the Z80 parameters are listed in Table 17. The

reference numbers in Tables 16 and 17 refer to Figures 10,

12 and 13.

times. Since the Z80 CPUs do not issue either /INTACK or

/RD, external logic must generate these signals.

6

Generating these two signals is easily accomplished, but

the Z80 CPU must be placed into a Wait condition until the

peripheral interrupt vector is valid. If more peripherals are

added to the daisy chain, additional Wait states may be

necessary to give the daisy chain time to settle. Sufficient

time between /INTACK active and /RD active should be

allowed for the entire daisy chain to settle.

If the CPU and the peripherals are running at different

speeds (as with the Z80H interface), the /INTACK signal

must be synchronized to the peripheral clock.

Synchronization is discussed in detail under Interrupt

Acknowledge for Z80H CPU to Z8500/8500A Peripherals.

Since the Z8500 peripheral daisy chain does not use the

IP flag except during interrupt acknowledge, there is no

need for decoding the RETI instruction used by the Z80

peripherals. In each of the Z8500 peripherals, there are

commands that reset the individual IUS flags.

During an Interrupt Acknowledge cycle, Z8500 peripherals

require both /INTACK and /RD to be active at certain

EXTERNAL INTERFACE LOGIC

The following sections discuss external interface logic

required during Interrupt Acknowledge cycles for each

interface type.

peripherals during an Interrupt Acknowledge cycle. The

primary component in this logic is the Shift register

(74LS164), which generates /INTACK, /READ, and /WAIT.

CPU/Peripheral Same Speed

Figure 9 shows the logic used to interface the Z80A CPU

to the Z8500 peripherals and the Z80B CPU to Z8500A

Table 15. Z8500 Timing Parameters Interrupt Acknowledge Cycles

4 MHz

6 MHz

Worst Case

Min

Max

Min

Max

Units

1.

TsIA(PC)

/INTACK Low to PCLK High Setup

/INTACK Low to PCLK High Hold

/INTACK Low to RD (Acknowledge) Low

/RD (Acknowledge) Width

/RD (Acknowledge) to Data Valid

IEI to /RD (Acknowledge) Setup

IEI to /RD (Acknowledge) Hold

IEI to IEO Delay

100

350

100

250

ns

ThIA(PC)

TdIAi(RD)

TwRDA

TdRDA(DR)

TsIEI(RDA)

ThIEI(RDA)

TdIEI(IE)

2.

5.

3.

250

150

180

100

120

100

70

.

Table 16. Z80 CPU Timing Parameters Interrupt Acknowledge Cycles

4 MHz 6 MHz 8 MHz

Worst Case

Min

Max

100

Min

Max

80

Min

Max

70

Units

TdC(M1f)

TdM1f(IORQf)

4. TsD(Cr)

Clock High to /M1 Low Delay

/M1 Low to /IORQ Low Delay

Data to Clock High Setup

ns

575*

35

*345

30

275*

25

*Z80A: 2TcC + TwCh + TfC - 65

Z80B: 2 TcC + TwCh + TfC - 50

Z80H: 2TcC + TwCh + TfC - 45

6-15

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

EXTERNAL INTERFACE LOGIC (Continued)

Figure 9. Z80A/Z80B CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic

During I/O and normal memory access cycles, the Shift

registers remains cleared because the /M1 signal is

inactive. During opcode fetch cycles, also, the Shift

register remains cleared, because only 0s can be clocked

through the register. Since Shift register outputs are Low,

/READ, /WRITE, and /WAIT are controlled by other

system logic and gated through the AND gates (74LS11).

During I/O and normal memory access cycles, /READ and

/WRITE are active as a result of the system /RD and /WR

signals (respectively) becoming active. If system logic

requires that the CPU be placed into a Wait condition, the

/WAIT signal controls the CPU. Should it be necessary to

reset the system, /RESET causes the interface logic to

generate both /READ and /WRITE (the Z8500 peripheral

Reset condition).

Since it is the presence of /INTACK and an active /READ

that gates the interrupt vector onto the data bus, the logic

must also generate /READ at the is Td1Ai(RD) /INTACK to

/RD (Acknowledge) Low Delay]. This time delay allows the

interrupt daisy chain to settle so that the device requesting

the interrupt can place its interrupt vector onto the data

bus. The shift register allows a sufficient time delay from

the generation of /INTACK before it generates /READ.

During this delay, it places the CPU into a Wait state until

the valid interrupt vector can be placed onto the data bus.

If the time between these two signals is insufficient for

daisy chain settling, more time can be added by taking

/READ and /WAIT from a later position on the Shift

register.

Figure 10 illustrates Interrupt Acknowledge cycle timing

resulting from the Z80A CPU to Z8500 peripheral and the

Z80B CPU to A8500A peripheral interface. This timing

comes from the logic illustrated in Figure 9, which can be

used for both interfaces. Should more Wait states be

required, the additional time can be calculated in terms of

system clocks, since the CPU clock and PCLK are the

same.

Normally an Interrupt Acknowledge cycle is indicated by

the Z80 CPU when /M1 and /IORQ are both active (which

can be detected on the third rising clock edge after T1). To

obtain an early indication of an Interrupt Acknowledge

cycle, the Shift register decodes an active /M1 in the

presence of an inactive /MREQ on the rising edge of T2.

During an Interrupt Acknowledge cycle, the /INTACK

signal is generated on the rising edge of T2.

6-16

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

6

Figure 10. Z80A/Z80B CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Timing

/WAIT signal is removed when sufficient time has been

allowed for the interrupt vector data to be valid.

Z8500/Z8500A Peripherals

Figure 11 depicts logic that can be used in interfacing the

Z80H CPU to the Z8500/Z8500A peripherals. This logic is

the same as that shown in Figure 5, except that a

synchronizing flip-flop is used to recognize an Interrupt

Acknowledge cycle. Since Z8500 peripherals do not rely

upon PCLK except during Interrupt Acknowledge cycles,

synchronization need occur only at that time. Since the

CPU and the peripherals are running at different speeds,

/INTACK and /RD must be synchronized to the Z8500

peripherals clock.

Figure 12 illustrates Interrupt Acknowledge cycle timing for

the Z80H CPU to Z8500 peripheral interface. Figure 13

illustrates Interrupt Acknowledge cycle timing for the Z80H

CPU to Z8500A peripheral interface. These timing result

from the logic in Figure 11. Should more Wait states be

required, the needed time should be calculated in terms of

PCLKs, not CPU clocks.

Z80 CPU to Z80 and Z8500 Peripherals

In a Z80 system, a combination of Z80 peripherals and

Z8500 peripherals can be used compatibly. While there is

no restriction on the placement of the Z8500 peripherals in

the daisy chain, it is recommended that they be placed

early in the chain to minimize propagation delays during

RET1 cycles.

During I/O and normal memory access cycles, the

synchronizing flip-flop and the Shift register remain

cleared because the /M1 signal is inactive. During opcode

fetch cycles, the flip-flop and the Shift register again

remain cleared, but this time because the /MREQ signal is

active. The synchronizing flip-flop allows an Interrupt

Acknowledge cycle to be recognized on the rising edge of

T2 when /M1 is active and /MREQ is inactive, generating

the INTA signal. When INTA is active, the Shift register can

clock and generate /INTACK to the peripheral and /WAIT

to the CPU. The Shift register delays the generation of

/READ to the peripheral until the daisy chain settles. The

During an Interrupt Acknowledge cycle, the IEO line from

Z8500 peripherals changes to reflect the interrupt status.

Time should be allowed for this change to ripple through

the remainder of the daisy chain before activating /IORQ

to the Z80 peripherals, or /READ to the Z8500 peripherals.

6-17

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

EXTERNAL INTERFACE LOGIC (Continued)

Figure 11. Z80H to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic

During RETI cycles, the IEO line from the Z8500 peripherals

does not change state as in the Z80 peripherals. As long as

the peripherals are at the top of the daisy chain, propagation

delays are minimized.

The logic necessary to create the control signals for both

Z80 and Z8500 peripherals is shown in Figure 9. This logic

delays the generation of /IORQ to the Z80 peripherals by

the same amount of time necessary to generate /READ for

the Z8500 peripherals. Timing for this logic during an

Interrupt Acknowledge cycle is depicted in Figure 10.

6-18

UM010901-0601

Application Note

Interfacing Z80 CPUs to the Z8500 Peripheral Family

®

6

Figure 12. Z80H CPU to Z8500 Peripheral Interrupt Acknowledge Interface Timing

Figure 13. Z80H CPU to Z8500A Peripheral Interrupt Acknowledge Interface Timing

6-19

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

EXTERNAL INTERFACE LOGIC (Continued)

Figure 14. Z80 and Z8500 Peripheral Interrupt Acknowledge Interface Logic

6-20

UM010901-0601

Application Note

Interfacing Z80 CPUs to the Z8500 Peripheral Family

®

6

Figure 15. Z80 and Z8500 Peripheral Interrupt Acknowledge Interface Timing

6-21

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

SOFTWARE CONSIDERATIONS - POLLED OPERATION

There are several options available for servicing interrupts

on the Z8500 peripherals. Since the vector of IP registers

can be read at any time, software can be used to emulate

the Z80 interrupt response. The interrupt vector read

reflects the interrupt status condition even if the device is

programmed to return to vector that does not reflect the

status change (SAV or VIS is not set). The code below is

a simple software routine that emulates the Z80 vector

response operation.

Z80 Vector Interrupt Response, Emulation by

Software

;This code emulates the Z80 vector interrupt

;operation by reading the device interrupt

;vector and forming an address from a vector

;table. It then executes an indirect jump to

;the interrupt service routine.

INDX: LD

OUT

A,CIVREG

;CURRENT INT. VECT. REG

(CTRL), A

A, (CTRL)

A

;WRITE REG. PTR.

;READ VECT. REG.

;VALID VECTOR?

;NO INT - RETURN

;MASK OTHER BITS

IN

INC

RET

AND

LD

Z

00001110B

E,A

LD

D,0

;FORM INDEX VALUE

LD

ADD

LD

INC

LD

HL,VECTAB

HL,DE

A, (HL)

HL

H, (HL)

L,A

;ADD VECT. TABLE ADDR.

;GET LOW BYTE

;GET HIGH BYTE

;FORM ROUTINE ADDR.

;JUMP TO IT

JP

(HL)

VECTAB:

DEFW

INT1

INT2

INT3

INT4

INT5

INT6

INT7

INT8

6-22

UM010901-0601

Application Note

®

Interfacing Z80 CPUs to the Z8500 Peripheral Family

A SIMPLE Z80-Z8500 SYSTEM

The Z8500 devices interface easily to the Z80 CPU, thus

providing a system of considerable flexibility. Figure 16

illustrates a simple system using the Z80A CPU and Z8536

Counter/Timer and Parallel I/O Unit (CIO) in a mode 1 or

non-interrupt environment. Since interrupt vectors are not

used, the /INTACK line is tied High and no additional logic

is needed. Because the CIO can be used in a polled

interrupt environment, the /INT pin is connected to the

CPU. The Z80 should not be set for mode 2 interrupts

since the CIO will never place a vector onto the data bus.

Instead, the CPU should be placed into mode 1 interrupt

mode and a global interrupt service routine can poll the

CIO to determine what caused the interrupt to occur. In this

system, the software emulation procedure described

above is effective.

6

Figure 16. Z80 to Z8500 Simple System Mode 1 Interrupt or Non-Interrupt Structure

The Z8000 User’s Manual features technical information

on the Z8536 CIO and Z8038 FIO.

Additional Information in Zilog Publications:

The Z80 Family User’s Manual includes technical

information on the Z80 CPU, DMA, PIO, CTC, and SIO.

Technical information on the Z80 CPU AC Characteristics

and the Z80 Family Interrupt Structure Tutorial can be

found in the Z80 Databook.

6-23

UM010901-0601

6-24

UM010901-0601

APPLICATION NOTE

7

™

THE Z180 INTERFACED

WITH THE SCC AT MHZ

7

uild a simple system to prove and test the Z180 MPU interfacing the SCC at 10 MHz.

Replacing the Z80 with the Z180 provides higher integration, reduced parts, more board

space, increased processing speed, and greater reliability.

B

INTRODUCTION

This Application Note describes the design of a system

using a Z80180 MPU (Microprocessor Unit) and a Z85C30

SCC (Serial Communications Controller), both running at

10 MHz. Hereinafter, all references are to the Z180™ and

SCC.

The serial communication devices on the Z180 are: two

asynchronous channels and one clocked serial channel.

This means handling synchronous serial communications

protocols requires an off-chip “multi-protocol serial

communication controller.” The SCC is the ideal device for

this purpose.

The system board is a vehicle for demonstration and

evaluation of the 10 MHz interface and includes the

following parts:

Zilog’s SCC is the multi-protocol (@ 10 MHz) universal

serial communication controller which supports most serial

communication applications including Monosync, Bisync

and SDLC at 2.5 Mbits/sec speeds. Further, the wide

acceptance of this device by the market ensures it is an

“industry standard” serial communication controller. Also,

the Z180 has special numbers for system clock

frequencies of 6.144 - and 9.216 MHz which generate

exact baud rates for on-chip asynchronous serial

communication channels. This is due to the SCC’s on-

chip, 16-bit wide baud rate generator for asynchronous

ASCI communications.

■ Z8018010VSC Z180 MPU 10 MHz, PLCC package

■ Z85C3010VSC C-MOS Z8530 SCC Serial Com-

munication Controller, 10 MHz, PLCC package

■ 27C256 EPROM

■ 55257 Static RAM

The Z180 is a Z80-compatible High Integration device with

various peripherals on-board. Using this device as an

alternative to the Z80 CPU, reduces the number of parts

and board space while increasing processing speed and

reliability.

The following 10 MHz interface explanation defines how

the interrupt structure works. Also included is a discussion

of the hardware and software considerations involved in

running the system’s communication board. This

Application Note assumes the reader has a strong working

knowledge of the Z180 and SCC; this is not a tutorial for

each device.

6-25

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

INTERFACES

The following subsections explain the interfaces between

the:

■ Using EPLD for glue wherever possible

■ Expendability

■ Z180 and Memory

The design method for EPLD is using TTLs (74HCT) and

then translating them into EPLD logic. This design uses

TTLs and EPLDs. With these goals in mind, the discussion

begins with the Z180-to-memory interface.

■ Z180 and I/O

■ Z180 and SCC

Basic goals of this system design are:

■ System clock up to 10 MHz

Z180 to Memory Interface

The memory access cycle timing of the Z180 is similar to

the Z80 CPU memory access cycle timing. The three

classifications are:

■ Using the Z8018010VSC (Z180 10 MHz PLCC

package) to take advantage of 1M byte addressing

space and compactness (DIP versions’ addressing

range is half; 512K bytes)

■ Opcode fetch cycle (Figure 1)

■ Memory read cycle (Figure 2)

■ Memory write cycle (Figure 3)

■ Using Z85C3010VSC (CMOS SCC 10 MHz PLCC

package)

Table 1 shows the Z180’s basic timing elements for the

opcode’s fetch/memory read/write cycle.

■ Minimum parts count

■ Worst case design

T1

T2

Tw

T3

T1

Ø

Address

6

7

/MREQ

/RD

8

9

11

12

13

11

Data

Read Data

15

16

/M1

10

14

Figure 1. Z180 Opcode Fetch Cycle Timing (One Wait State)

6-26

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Table 1. Z8018010 Timing Parameters for Opcode Fetch Cycle (Worst Case: Z180 10 MHz)

No

Symbol

Parameter

Min

Max

Units

1

2

3

4

tcyc

Clock Cycle Period

Clock Cycle High Width

Clock Cycle Low Width

Clock Fall Time

100

40

ns

7

tCHW

tCLW

tcf

10

6

8

9

11

tAD

Clock High to Address Valid

Clock Low to /MREQ Low

Clock Low to /RD Low

Address Hold Time

70

50

ns

tMED1

tRDD1

tAH

10

12

15

16

22

23

tMED2

tDRS

tDRH

tWRD1

tWDD

Clock Low to /MREQ High

Data to Clock Setup

Data Read Hold Time

Clock High to /WR Low

Clock Low to Write Data Delay

50

ns

25

0

50

60

24

25

26

27

tWDS

tWRD2

tWRP

tWDH

Write Data Setup to /WR Low

Clock Low to /WR High

/WR Pulse Width

15

10

ns

50

110

/WR High to Data Hold Time

Note: Parameter numbers in this table are in the Z180 technical manual.

T1

T2

Tw

T3

T1

Ø

Address

6

7

/MREQ

8

9

11

12

13

/RD

11

Data

Read Data

15

16

Figure 2. Z180 Memory Read Cycle Timing (One Wait State)

6-27

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

EPROM INTERFACE

During an Opcode fetch cycle, data sampling of the bus is

on the rising PHI clock edge of T3 and on the falling edge

of T3 during a memory read cycle. Opcode fetch cycle data

sample timing is half a clock cycle earlier. Table 2 shows

how a memory read cycles’ timing requirements are easier

than an opcode fetch cycle by half a PHI cycle time. If the

timing requirements for an Opcode fetch cycle meet

specifications, the design satisfies the timing requirements

for a memory read cycle.

Table 2 has some equations for an opcode fetch, memory

read/write cycle.

Table 2. Parameter Equations (10 MHz) Opcode Fetch/Memory Read/Write Cycle

Parameters

Z180 Equation

Value

Units

Address Valid to Data Valid (Opcode Fetch)

Address Valid to Data Valid (Memory Read

/MREQ Active to Data Valid (Opcode Fetch)

2(1+w)tcyc-tAD-tDRS

2(1+w)tcyc+tCHW+tcf-tAD-tDRS

(1+w)tcyc+tCLW-tMED1-tDRS

105+100w min

155+100w min

55+100w min

ns

/MREQ Active to Data Valid (Memory Read)

/RD Active to Data Valid (Opcode Fetch)

/RD Active to Data Valid (Memory Read)

Memory Write Cycle /WR Pulse Width

Note: * w is the number of wait states.

(2+w)tcyc-tMED1-tDRS

(1+w)tcyc+tCLW-tRRD1-tDRS

(2+w)tcyc-tRRD1-tDRS

tWRP+w*tcyc

105+100w min

55+100w min

105+100w min

110+100w min

ns

The propagation delay for the decoded address and gates

in the previous calculation is zero. Hence, on the real

design, subtracting another 20-30 ns to pay for

propagation delays, is possible. The 27C256 provides the

EPROM for this board. Typical timing parameters for the

27C256 are in Table 3.

Table 4. 256K SRAM Key Timing parameters

(Values May Vary Depending On Mfg.)

Access Time

85 ns 100 ns 150 ns

Parameter

Min

Table 3. EPROM (27C256) Key Timing Parameters

(Values May Vary Depending On Mfg.)

Read Cycle:

/E to Data Valid

/G to Data Valid

85

45

100

40

150

60

Access Time

Write Cycle:

170 ns 200 ns 250 ns

Write Cycle Time

85

75

40

60

0

100

80

40

60

0

150

100

60

90

0

Parameter

Max

Addr Valid to End of Write

Chip Select to End of Write

Data Select to End of Write

Write Pulse Width

Addr Access Time

/E to Data Valid

/OE to Data Valid

170

75

200

75

250

100

Note: Table 3 shows “Access Time” as applying /E to data valid.

“/OE active to data valid” is shorter than “address access time”.

Hence, the interface logic for the EPROM is: Realize a 170 ns or

faster EPROM access time by adding one wait state (using the

on-chip wait state generator of the Z180). A 200 ns requirement

uses two wait states for memory access.

Addr Setup Time

SRAM Read Cycle. An SRAM read cycle shares the

same considerations as an EPROM interface.

Like EPROM, SRAMs’ “access time” applies /G to data

valid, and “/E active to data valid” is shorter than “access

time.” This design allows the use of a 150 ns access time

SRAM by adding one wait state (using the on-chip wait

state generator of the Z180). The circuit is common to the

EPROM memory read cycle.

SRAM Interface

Table 4 has timing parameters for 256K bit SRAM for this

design.)

No wait states are necessary if there is a 85 ns, or faster,

access time by using SRAMs. Since the Z180 has on-chip

MMU with 85 ns or faster SRAM just copy the contents of

EPROM (application program starts at logical address

0000h) into SRAM after power on. Set up the MMU to

SRAM area to override the EPROM area and stop

6-28

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

inserting wait states. With this scheme, you can get the

highest performance with moderate cost.

(Z180 parameter #24; 15 ns min at 10 MHz). It is stable

throughout the write cycle (Z180 parameter #27; 10 ns min

at 10 MHz). Further, the address is fixed before the falling

edge of /WR. As long as the /WR pulse width meets the

SRAM’s spec, there is no problem (reference Table 2).

SRAM Write Cycle. During a Z180 memory write cycle,

the Z180 write data is stable before the falling edge of /WR

7

T1

T2

Tw

T3

T1

Ø

Address

/MREQ

6

8

11

12

25

/WR

Data

22

26

24

27

23

Figure 3. Z180 Memory Write Cycle Timing (One Wait State)

Memory Interface Logic

Interrupt Acknowledge cycle, /WR and /RD signals are

inactive.

The memory devices (EPROM and SRAM) for this design

are 256K bit (32K byte). There are two possible memory

interface designs:

To keep the design simple and flexible, use the second

method (Figure 4b). To expand memory, decode the

address A15 NANDed with /USRRAM//USRROM and

/IORQ to produce /CSRAM or /CSROM. These are chip

select inputs to chips 55257 or 27C256, respectively. This

either disables or enables on-board ROM or RAM

depending upon selection control.

Connect Address Decode output to /E input. Put the

signal generated by /RD and /MREQ ANDed together to

/OE of EPROM and SRAM. Put the signal generated by

/WR and /MREQ ANDed together to the /WE pin of

SRAM (Figure 4a).

Connect the signal Address ANDed together with inactive

/IORQ to the /E input. Connect /RD to /OE of EPROM and

SRAM, and /WR to /WE pin of SRAM (Figure 4b).

The circuit on Figure 4b gives the physical memory

address as shown on Figure 5.

If there are no Z80 peripherals and /M1 is enabled (M1E

bit in Z180 OMCR register set to 1), active wait states

occur only during opcode fetch cycles (Figure 6). If the

M1E bit is cleared to 0, /M1E is active only during the

Interrupt Acknowledge cycle and Return from Interrupt

cycle. This case depends on the propagation delay of the

address decoder which uses 135 ns or faster EPROM

assess time (assume there is 20 ns propagation delay).

Figure 6 shows the example of this implementation.

Using the second method, there could be a narrow glitch

on the signal to the /E-pin during I/O cycles and the

Interrupt acknowledge cycle. During I/O cycles, /IORQ and

/RD or /WR go active at almost the same time. Since the

delay times of these signals are similar there is no

“overlapping time” between /CE generated by the address

(/IORQ inactive), and /WR or /RD active. During the

6-29

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

HCT138

G

/Y9

/Y6

/Y5

/Y4

/Y3

/Y2

/Y1

/Y0

/38000 ~

/30000 ~

A9

/G2A

/G2B

/28000 ~

A18

/20000 ~

A17

A16

A15

C

B

A

/18000 ~

/10000 ~

/08000 ~ To 55257 /E Pin

/00000 ~ To 27C256 /E Pin

/RD

/MREQ

/WR

* /MEMR To 27C56 /OE,

55257 /OE Pin

* /MEMW To 55257 /WE Pin

/RD to /OE Pin of 27C256 and 55257

/WR To /WE Pin of 55257

*

Figure 4a. Memory Interface Logic

4.7 K Ω x2

/USRRAM

/IORQ

A15

/CSRAM To 55257 /CE Pin

/CSROM To 27C256 /CE Pin

HCT10

/USRROM

Figure 4b. Memory Interface Logic

6-30

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

FFFFFH

F8000H

F0000H

S-RAM Image

CL

7

/M1

D

Q

D

Q

'74

EP-ROM Image

CK

PR

CK

PR

Image can be

killed trhrough

/USRRAM and

/USRROM

Ø

/M1 /WAIT

S-RAM Image

28000H

20000H

18000H

10000H

08000H

00000H

Figure 6. Wait State Generator Logic

/EP-ROM Image

S-RAM Image

(Extends Opcode Fetch Cycle Only; Not Working in Z

Mode of Operation)

EP-ROM Image

256K SRAM

EP-ROM

27C256

Figure 5. Physical Memory Address Map

6-31

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Z180 TO I/O INTERFACE

The Z180 I/O read/write cycle is similar to the Z80 CPU if

you clear the /IOC bit in the OMCR register to 0 (Figures 7

and 8). Table 5 shows the Z180 key parameters for an I/O

cycle.

T1

T2

T

T3

T1

WA

Ø

Address

/IORQ

6

28

29

13

11

/RD

19

11

Data

15

16

Figure 7. Z180 I/O Read Cycle Timing (/IOC = 0)

T1

T2

Tw

T3

T1

Ø

Address

/IORQ

6

25

29

25

11

/WR

Data

22

26

23

27

21

24

Figure 8. Z180 I/O Write Cycle Timing

6-32

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

.

Table 5. Z8018010 Timing Parameters for I/O Cycle (Worst Case)

7

No Symbol

Parameter

Min

Max

Units

1

2

3

4

tcyc

Clock Cycle Period

Clock Cycle High Width

Clock Cycle Low Width

Clock Fall Time

100

40

ns

tCHW

tCLW

tcf

10

6

9

tAD

tRDD1

Clock High to Address Valid

Clock High to /RD Low IOC=0

Address Hold Time

70

55

ns

11 tAH

13 tRDD2

10

Clock Low to /RD High

50

15 tDRS

16 tDRH

21 tWDZ

22 tWRD1

Data to Clock Setup

Data Read Hold Time

Clock High to Data Float Delay

Clock High to /WR Low

25

0

ns

60

50

23 tWDD

24 tWDS

25 tWRD2

26a tWRP

Clock Low to Write Data Delay

Write Data Setup to /WR Low

Clock Low to /WR High

60

ns

15

50

/WR Pulse Width (I/O Write)

210

10

27 tWDH

28 tIOD1

29 tIOD2

/WR High to Data Hold Time

Clock High to /IORQ Low IOC=0

Clock Low to /IORQ High

ns

55

50

Note: Parameter numbers in this table are the numbers in the Z180 technical manual.

If you are familiar with the Z80 CPU design, the same

interfacing logic applies to the Z180 and I/O interface (see

Figure 9a). This circuit generates /IORD (Read) or IORD

(Write) for peripherals from inputs /IORQ, /RD, and /WR.

The address decodes the Chip Select signal. Note, if you

have Z80 peripherals, the decoder logic decodes only from

addresses (does not have /IORQ). The Z180 signals

/IORQ, /RD, and /WR are active at about the same time

(Parameters #9, 22, 28). However, most of the Z80

peripherals require /CE to /RD or /WR setup time.

Since the Z180 occupies 64 bytes of I/O addressing space

for system control and on-chip peripherals, there are no

overlapping I/O addresses for off-chip peripherals. In this

design, leave the area as default or assign on-chip

registers at I/O address 0000h to 003Fh.

Figure 9 shows a simple address decoder (the required

interface signals, other than address decode outputs, are

discussed later).

HCT138

/Y9

50 ~

58 ~

54 ~

A6

A17

A2

G1

/Y6

/Y5

/Y4

/Y3

/Y2

/Y1

/Y0

/G2A

/G2B

50 ~

Chip Select Signals

for Peripherals

A5

A4

A3

C

B

A

40 ~

48 ~

44 ~

40 ~

/IORQ

/RD

/IORD To Each

Peripherals' /RD

/IOWR To Each

Peripherals' /WR

/WR

Figure 9a. I/O Interface Logic (Example)

6-33

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

4.7 K Ω

/USRRAM

/CSSCC

(To SCC Interface Logic)

A7

A6

HCT10

Figure 9b. I/O Address Decoder for this Board

When expanding this board to enable other peripherals,

If there is a Z80 PIO on board in a Z-mode of operation

(that is, clear /M1E in OMCR register to zero) and after

enabling a Z80 PIO interrupt, zero is written to M1TE in the

OMCR register. Without a zero, there is no interrupt from

the Z80 PIO. The Z80 PIO requires /M1 to activate an

interrupt circuit after enabling interrupt by software.

the decoded address A6/A7 is NANDed with USRIO to

produce the Chip Enable (CSSCC) output signal (HC10).

The SCC registers are assigned from address xxC0h to

xxC3h; with image, they occupy xxC0h to xxFFh. To add

wait states during I/O transactions, use the Z180 on-chip

wait state generator instead of external hardware logic.

Z180 TO SCC INTERFACE

The following subsections discuss the various parameters

between the Z180/SCC interface: CPU hardware, I/O

operation (read/write), SCC interrupts, Z80 interrupt daisy-

chain operation, SCC interrupt daisy-chain operation, I/O

cycles.

Chip reset occurs when /RD and /WR are active

simultaneously.

Interrupt Control

/INTACK. Interrupt Acknowledge (input, active low). This

signal shows an Interrupt Acknowledge cycle which

combines with /RD to gate the interrupt vector onto the

data bus.

CPU Hardware Interfacing

The hardware interface has three basic groups of signals:

Data bus, system control, and interrupt control. For more

detailed signal information, refer to Zilog’s Technical

Manuals, and Product Specifications for each device.

/INT. Interrupt request (output, open-drain, active low).

IEI. Interrupt Enable In (input, active high).

Data Bus Signals

IEO. Interrupt Enable Out (Output, active high).

D7-D0. Data bus (Bidirectional, tri-state). This bus

transfers data between the Z180 and SCC.

These lines control the interrupt daisy chain for the

peripheral interrupt response.

System Control Signals

SCC I/O Operation

A//B, C//D. Register select signals (Input). These lines

select the registers.

The SCC generates internal control signals from /RD or

/WR. Since PCLK has no required phase relationship to

/RD or /WR, the circuitry generating these signals provides

time for meta stable conditions to disappear.

/CE. Chip enable (Input, active low). /CE selects the

proper peripheral for programming. /CE is gated with

/IORQ or /MREQ to prevent false chip selects during other

machine cycles.

The SCC starts the different operating modes by

programming the internal registers. Accessing these

internal registers occurs during I/O Read and Write cycles,

described below.

/RD+. Read (input, active low). /RD activates the chip-

read circuitry and gates data from the chip onto the data

bus.

Read Cycle Timing

Figure 10 illustrates the SCC Read cycle timing. All

register addresses and /INTACK are stable throughout the

cycle. The timing specification of SCC requires that the

/CE signal (and address) be stable when /RD is active.

/WR+. Write (Input, active low). /WR strobes data from the

data bus into the peripheral.

UM010901-0601

6-34

Application Note

The Z180™ Interfaced with the SCC at MHZ

Address

/INTACK

/CE

Address Valid

7

/RD

D7-D0

Data Valid

Figure 10. SCC Read Cycle Timing

Write Cycle Timing

/CE signal (and address) be stable when /RD is active.

Data is available to the SCC before the falling edge of /WR

and remains active until /WR goes inactive.

Figure 11 illustrates the SCC Write cycle timing. All

register addresses and /INTACK are stable throughout the

cycle. The timing specification of the SCC requires that the

Address

/INTACK

/CE

Address Valid

/WR

D7-D0

Data Valid

Figure 11. SCC Write Cycle Timing

6-35

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

The Z80 peripherals sample for both /M1 and /IORQ active

(and /RD inactive) to identify an Interrupt Acknowledge

cycle. When /M1 goes active and /RD is inactive, the

peripheral detects an Interrupt Acknowledge cycle and

allows its interrupt daisy chain to settle. When the /IORQ

line goes active with /M1 active, the highest priority

interrupting peripheral places its interrupt vector onto the

data bus. The IUS bit also sets to show that the peripheral

is now under service. As long as the IUS bit sets, the IEO

line remains low. This inhibits any lower priority devices

from requesting an interrupt.

SCC Interrupt Operation

Understanding SCC interrupt operations requires a basic

knowledge of the Interrupt Pending (IP) and Interrupt

Under Service (IUS) bits in relation to the daisy chain. The

Z180 and SCC design allow no additional interrupt

requests during an Interrupt Acknowledge cycle. This

permits the interrupt daisy chain to settle, ensuring proper

response of the interrupt device.

The IP bit sets in the SCC for CPU intervention

requirements (that is, buffer empty, character available,

error detection, or status changes). The interrupt

acknowledge cycle does not reset the IP bit. The IP bit

clears by a software command to the SCC, or when the

action that generated the interrupt ends, for example,

reading a receive character for receive interrupt. Others

are, writing data to the transmitter data register, issuing

Reset Tx interrupt pending command for Tx buffer empty

interrupt, etc.). After servicing the interrupt, other interrupts

can occur.

When the Z180 CPU executes the RETI instruction, the

peripherals check the data bus and the highest priority

device under service resets its IUS bit.

SCC Interrupt Daisy-Chain Operation

In the SCC, the IUS bit normally controls the state of the

IEO line. The IP bit affects the daisy chain only during an

Interrupt Acknowledge cycle. Since the IP bit is normally

not part of the SCC interrupt daisy chain, there is no need

to decode the RETI instruction. To allow for control over

the daisy chain, the SCC has a Disable Lower Chain (DLC)

software command that pulls IEO low. This selectively

deactivates parts of the daisy chain regardless of the

interrupt status. Table 6 shows the truth table for the SCC

interrupt daisy chain control signals during certain cycles.

Table 12 shows the interrupt state diagram for the SCC.

The IUS bit means the CPU is servicing an interrupt. The

IUS bit sets during an Interrupt Acknowledge cycle if the IP

bit sets and the IEI line is High. If the IEI line is low, the IUS

bit is not set. This keeps the device from placing its vector

onto the data bus.

The IUS bit clears in the Z80 peripherals by decoding the

RETI instruction. A software command also clears the IUS

bit in the Z80 peripherals. Only software commands clear

the IUS bit in the SCC.

Table 6. SCC Daisy Chain Signal Truth Table

During Idle State

During INTACK Cycle

Z80 Interrupt Daisy-Chain Operation

IEI

IP

IUS

IEO IEI

IP

IUS IEO

In the Z80 peripherals, both IP and IUS bits control the IEO

line and the lower portion of the daisy chain. When a

peripheral’s IP bit sets, the IEO line goes low. This is true

regardless of the state of the IEI line. Additionally, if the

peripheral’s IUS bit clears and its IEI line is High, the /INT

line goes low.

0

1

X

0

X

0

1

0

1

0

1

0

1

X

1

X

1

0

6-36

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Interrupt Condition

7

IP

Set

IUS

Set

IEI High?

CPU Read, Write, or Reset

Wait For CPU

/INTACK Cycle

INT

Active

IP

Cleared

IEO High?

/INTACK * IEI * /RD

IUS

Cleared

Return To Main Program

Figure 12. SCC Interrupt Status Diagram

The SCC uses /INTACK (Interrupt Acknowledge) for

the highest priority device requesting an interrupt to place

its vector on the data bus. Secondly, it sets the IUS bit in

the highest priority device to show the device is now under

service.

recognition of an interrupt acknowledge cycle. This pin,

used with /RD, allows the SCC to gate its interrupt vector

onto the data bus. An active /RD signal during an interrupt

acknowledge cycle performs two functions. First, it allows

6-37

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

INPUT/OUTPUT CYCLES

Although the SCC is a universal design, certain timing

parameters differ from the Z180 timing. The following

subsections discuss the I/O interface for the Z180 MPU

and SCC.

Z180 MPU to SCC Interface

Table 7 shows key parameters of the 10 MHz SCC for I/O

read/write cycles.

Table 7. 10 MHz SCC Timing Parameters for I/O Read/Write Cycle (Worst Case)

No Symbol

Parameter

Address to /WR Low Setup

Address to /WR High Hold

Address to /RD Low Setup

Address to /RD High Hold

Min

50

0

50

0

Max

Units

6

7

8

9

TsA(WR)

ThA(WR)

TsA(RD)

ThA(RD)

ns

16 TsCEI(WR)

17 ThCE(WR)

19 TsCEI(RD)

20 ThCE(RD)

/CE Low to /WR Low Setup

/CE to /WR High Hold

/CE Low to /RD Low Setup

/CE to /RD High Hold

0

ns

22 TwRDI

/RD Low Width

125

ns

25 TdRDf(DR)

27 TdA(DR)

28 TwWRI

29 TsDW(WR)

30 TdWR(W)

/RD Low to Read Data Valid

Address to Read Data Valid

/WR Low Width

Write Data to /WR Low Setup

Write Data to /WR High Hold

120

180

125

10

0

I/O Write Cycle

SCC I/O Read/Write Cycle

Parameters 6 and 7 mean that Address is stable 50 ns

before the falling edge of /WR and is stable until /WR goes

inactive.

Assume that the Z180 MPU’s /IOC bit in the OMCR

(Operation Mode Control Register) clears to 0 (this

condition is a Z80 compatible timing mode for /IORQ and

/RD). The following are several design points to consider

(also see Table 3).

Parameters 16 and 17 mean that /CE is stable at the falling

edge of /WR and is stable until /W goes inactive.

I/O Read Cycle

Parameters 8 and 9 mean that Address is stable 20 ns

before the falling edge of /RD and until /RD goes inactive.

Parameter 28 means /WR pulse width is wider than 125

ns.

Parameters 28 and 29 mean that Write data is on the data

bus 10 ns before the falling edge of /WR. It is stable until

the rising edge of /WR.

Parameters 19 and 20 mean that /CE is stable at the falling

edge of /RD and until /RD goes inactive.

Parameter 22 means the /RD pulse width is wider than

125 ns.

Tables 8 and 9 show the worst case SCC parameters

calculating Z180 parameters at 10 MHz.

Parameters 25 and 27 mean that Read data is available on

the data bus 120 ns later than the falling edge of /RD and

180 ns from a stable Address.

6-38

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Table 8. Parameter Equations Worst Case (Without Delay Signals - No Wait State)

SCC

Z180

Parameters

Equation

Value

Units

7

TsA(RD)

TdA(DR)

TdRDf(DR)

tcyc-tAD+tRDD1

3tcyc+tCHW+tcf-tAD-tDRS

2tcyc+tCHW+tcf-tRDD1-tDRS

30 min

245 min

160 min

ns

TwRDI

2tcyc+tCHW+tcf-tDRS+tRDD2

tcyc-tAD+tWRD1

tWDS

185 min

30 min

15 min

210 min

ns

TsA(WR)

TsDW(WR)

TwWRI

tWRP

Table 9. Parameter Equations

Z180

SCC

Parameters

Equation

Value

Units

tDRS

Address

3tcyc+tCHW-tAD-TdA(DR)

RD

2tcyc+tCHW-tRDD1-TdRD(DR)

241 min

184 min

ns

I/O Read Cycle

ns min worst case. Further, the Z180 timing specifications

tAH (Address Hold time) and tWDH (/WR high to data hold

time) are both 10 ns min. The SCC timing parameters

ThA(WR) {Address to /WR High Hold}, ThCE(WR) {/CE to

/WR High Hold} and TdWR(W) {Write data to /WR High

hold} are a minimum of 0 ns. The rising edge of /WR is

early to guarantee these parameter requirements.

These tables show that a delay of the falling edge of /RD

satisfies the SCC TsA(RD) timing requirement of 50 ns

min. The Z180 calculated value is 30 ns min for the worst

case. Also, Z180 timing specification tAH (Address Hold

time) is 10 ns min. The SCC timing parameters ThA(RD)

{Address to /RD High Hold} and ThCE(RD) {/CE to /RD

High Hold} are minimum at 0 ns. The rising edge of /RD is

early to guarantee these parameters when considering

address decoders and gate propagation delays.

This circuit depicts logic for the I/O interface and the

Interrupt Acknowledge Interface for 10 MHz clock of

operation. Figure 13 is the I/O read/write timing chart

(discussions of timing considerations on the Interrupt

Acknowledge cycle and the circuit using EPLD occur

later).

I/O Write Cycle

Delay the falling edge of /WR to satisfy the SCC TsA(/WR)

timing requirement of 50 ns min. The Z180 calculates 30

6-39

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

To

/CSSCC

85C30

/CE

/WR

HCT74

HCT164

D

Q

HCT27

HCT02

HCT27

Q0

A

To

85C30

/WR

CK

Ø

Q1

Q2

Q3

Q4

Q5

Q6

Q7

B

/CLR

To

85C30

/RD

HCT04

CK

/RD

HCT04

/RESET

HCT164

HCT04

/INTACK

To 85C30

/INTACK

Q0

/MREQ

/M1

A

Q1

Q2

Q3

Q4

Q5

Q6

Q7

B

HCT02

HCT04

CLR

To

Z180

/WAIT

CK

HCT02

4.7K

Internal

/WAIT

Input

Figure 13. SCC I/O Read/Write Cycle Timing

This circuit works when [(Lower HCT164’s CLK ≠ to Z180 /WAIT≠) + tws <tCHW]

If you are running your system slower than 8 MHz, remove

the HCT74, D-Flip/Flop in front of HCT164. Connect the

inverted CSSCC to the HCT164 B input. This is a required

Flip/Flop because the Z180 timing specification on tIOD1

(Clock High to /IORQ Low, IOC=0) is maximum at 55 ns

This is longer than half the PHI clock cycle. Sample it using

the rising edge of clock, otherwise, HCT164 does not

generate the same signals.

Interrupt Acknowledge Cycle Timing

The primary timing differences between the Z180 and

SCC occur in the Interrupt Acknowledge cycle. The SCC

timing parameters that are significant during Interrupt

Acknowledge cycles are in Table 10. The Z180 timing

parameters are in Table 10. The reference numbers in

Tables 10 and 11 refer to Figure 13.

The RESET signal feeds the SCC /RD and /WR through

HCT27 and HCT02 to supply the hardware reset signal. To

reduce the gate count, drop these gates and make the

SCC reset by its software command. The SCC software

reset - 0C0h to Write Register 9, “Hardware Reset

command” has the same effect as hardware reset by

“Hardware.”

6-40

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Table 10. 10 MHz SCC Timing Parameters for Interrupt Acknowledge Cycle

No Symbol

Parameter

Min

Max

Units

13 TsIAi(RD)

14 ThIA(RD)

15 ThIA(PC)

38 TwRDA

/INTACK Low to /RD Low Setup

/INTACK High to /RD High Hold

/INTACK to PCLK High Hold

/INTACK Low to /RD Low Delay

(Acknowledge)

130

0

30

ns

7

125

39 TwRDA

40 TdRDA(DR)

/RD (Acknowledge) Width

/RD Low (Acknowledge) to

Read Data Valid Delay

IEI to /RD Low (Acknowledge)

Setup Time

125

ns

120

175

41 TsIEI(RDA)

95

0

ns

42 ThIEI(RDA)

43 TdIEI(IEO)

IEI to /RD High (Acknowledge)

Hold Time

IEI to IEO Delay

ns

Table 11. Z180 Timing Parameters Interrupt Acknowledge Cycles (Worst Case Z180)

No Symbol

Parameter

Min

Max

Units

10 tM1D1

14 tM1D2

15 tDRS

Clock High to /M1 Low

Clock High to /M1 High

Data to Clock Setup

60

ns

25

0

16 tDRH

28 tIOD1

29 tIOD2

30 tIOD3

Data Read Hold Time

ns

Clock LOW to /IORQ Low

Clock LOW to /IORQ High

/M1 Low to /IORQ Low Delay

50

200

Note: Parameter numbers in this table are the numbers in the Z180 technical manual.

During an Interrupt Acknowledge cycle, the SCC requires

both /INTACK and /RD to be active at certain times. Since

the Z180 does not issue either /INTACK or /RD, external

logic generates these signals.

There is no need of decoding the RETI instruction used by

the Z80 peripherals since the SCC daisy chain does not

use IP, except during Interrupt Acknowledge. The SCC

and other Z8500 peripherals have commands that reset

the individual IUS flag.

The Z180 is in a Wait condition until the vector is valid. If

there are other peripherals added to the interrupt priority

daisy chain, more Wait states may be necessary to give it

time to settle. Allow enough time between /INTACK active

and /RD active for the entire daisy chain to settle.

External Interface for Interrupt Acknowledge Cycle: The

bottom half of Figure 14 is the interface logic for the

Interrupt Acknowledge cycle.

6-41

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

T1

T2

Tw

T3

1

100 ns

Address

/IORQ

6

70 ns max

11 10 ns min

28

55 ns max

50 ns max

28

/SCCSEL

20 ns max

10 ns max

HC74 /Q

10 ns max

HCT164 /CLR

HCT164 CLK

HCT164 Q0

HCT164 Q1

/RD (or, /WR)

10 ns max

20 ns max

9

13

55 ns max

15 ns max

RD* Q1

*SCCSEL

15 ns max

/SCCRD /[(RD*

/Q1* SCCSEL)

+ RESET]

15 ns max

30 ns ( > 0 ns)

15 ns max

> 0 ns

200 ns typ. ( > 125 ns)

Data (RD)

SCC

Valid Data

25

15

120 ns max

> 25 ns

/SCCWR

Data (RD)

24 15 ns min

29

22

0 ns min

SCC

210 ns

30

> 0 ns

Figure 14. Z180 to SCC Interface Logic (Example)

6-42

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

The primary chip in this logic is the Shift register (HCT164),

which generates /INTACK, /SCCRD and /WAIT. During

I/O and normal memory access cycles, the Shift Register

(HCT164) remains cleared because the /M1 signal is

inactive during the opcode fetch cycle. Since the Shift

Register output is Low, control of /SCCRD and /WAIT is by

other system logic and gated through the NOR gate

(HCT27). During I/O and normal memory access cycles,

/SCCRD and /SCCWR are generated from the system /RD

and /WR signals, respectively. The generation is by the

logic at the top of Figure 15.

7

T1

T2

T

WA

T3

/M1

/IORQ

10

60 ns max

14

28

50 ns max

50 ns max 29

/INTACK

/WAIT

/SCCRD

VECTOR

15

13

SCC

Valid Data

120 ns max

10

15

> 25 ns

SCC

Figure 15. SCC Interrupt Acknowledge Cycle Timing

Normally, an Interrupt Acknowledge cycle appears from

the Z180 during /M1 and /IORQ active (which is detected

on the third rising edge of PHI after T1). To get an early

sign of an Interrupt Acknowledge cycle, the Shift register

decodes an active /M1. This is during the presence of an

inactive /MREQ on the rising edge of T2.

(Acknowledge) Low delay]. This time delay allows the

interrupt daisy chain to settle so the device requesting the

interrupt places its interrupt vector onto the data bus.

The Shift Register allows enough time delay from the

generation of /INTACK before it generates /SCCRD.

During this delay, it places the Z180 into a Wait state until

the valid interrupt vector is placed onto the data bus. If the

time between these two signals is not enough for daisy

chain settling, more time is added by taking /SCCRD and

/WAIT from a later position on the Shift Register. If there is

a requirement for more wait states, the time is calculated

by PHI cycles.

During an Interrupt Acknowledge cycle, the /INTACK

signal is generated on the rising edge of T2. Since it is the

presence of /INTACK and an active SCCRD that gates the

interrupt vector onto the data bus, the logic also generates

/SCCRD at the proper time. The timing parameter of

concern here is TdIAi(RD) [/INTACK to /RD

USING EPLD

Figure 16a and Figure 16b show the logic using either

EPLD or the circuit of this system. The EPLD is ALTERA

610 which is a 24-Pin EPLD. The method to convert

random gate logic to EPLD is to disassemble MSIs’ logic

into SSI level, and then simplify the logic.

6-43

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

Figure 16a. ELPD Circuit Implementation

6-44

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

7

Figure 16b. ELPD Circuit Implementation

6-45

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

System Checkout

Interrupt Acknowledge Cycle

After completion of the board (PC board or wire wrapped

board, etc.), the following methods verify that the board is

working.

Checking an Interrupt Acknowledge (/INTACK) cycle

consists of several steps. First, the SCC makes an

Interrupt Request (/INT) to the Z180. When the processor

is ready to service the interrupt, it shows an Interrupt

Acknowledge (/INTACK) cycle. The SCC then puts an 8-

bit vector on the bus and the Z180 uses that vector to get

the correct service routine. The following test checks the

simplest case.

Software Considerations

Based on the previous discussion, it is necessary to

program the Z180 internal registers, as follows, before

system checkout:

First, load the Interrupt Vector Register (WR2) with a

vector, disable the Vector Interrupt Status (VIS) and

enable interrupts (IE=1, MIE=1 IEI=1). Disabling VIS

guarantees only one vector on the bus. The address of the

service routine corresponding to the 8-bit vector number

loads the Z180 vector table, and the Z180 is under

Interrupt Mode 2.

■ Z80 mode of operation - Clear /M1E bit in OMCR

register to zero (to provide expansion for Z80

peripherals).

■ Z80 compatible mode - Clear IOC bit in OMCR register

to zero.

■ Put one wait state in memory cycle, and no wait state for

I/O cycle DMCR register bits 7 and 6 to “1” and bits 5 and

4 to “0”.

Because the user cannot set the SCC Interrupt Pending Bit

(IP), setting an interrupt sequence is difficult. An interrupt

is generated indirectly via the CTS pin by enabling the

following explanation.

SCC Read Cycle Proof

Read cycle checking is first because it is the simplest

operation. The SCC Read cycle is checked by reading the

bits in RR0. First, the SCC is hardware reset by

simultaneously pulling /RD and /WR LOW (The circuit

above includes the circuit for this). Then, reading out the

Read Register 0 returns:

Enable interrupt by /CTS (WR15, 20h), External/Status

Interrupt Enable (WR1, 01h), and Master Interrupt Enable

(WR9, 08h). Any change on the /CTS pin begins the

interrupt sequence. The interrupt is re-enabled by Reset

External/Status Interrupt (WR0, 10h) and Reset Highest

IUS (WR0, 38h).

D7-D0 = 01xxx100b

Bit D2, D6:1

Bit D7, D1, D0:0

Bit D5: Reflects /CTS pin

Bit D4: Reflects /SYNC

Bit D3: Reflects /DCD pin

A sample program of an SCC Interrupt Test is shown in

Table 12. The following programs in Tables 12, 13, and 14

assume that the 180 is correctly initialized. Table 12 uses

the Assembler for the Z80 CPU.

SCC Write Cycle Proof

Write cycle checking involves writing to a register and

reading back the results to the registers which return the

written value. The Time Constant registers (WR12 and

WR13) and External/Status Interrupt Enable register

(WR15) are on the SCC.

6-46

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Table 12. SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interrupt)

;*

B register returns status info:

Bit D0: current /cts stat

D1set: /cts int received

7

;*

.z800

;Read in Z180 register names and

*include 180macro.lib

;macro for Z180 new instructions

;SCC

Registers

scc_ad:

scc_ac:

scc_bd:

scc_bc:

equ

0C3h

0C2h

0C1h

0C0h

;addr of scc ch a - data

;addr of scc ch a - control

;addr of scc ch b - data

;addr of scc ch b - control

scc_a:

equ

000h

;set 0ffh to test ch a

;clear 00h to test ch b.

if

scc_cont:

else

scc_cont:

endif

scc_a

equ

scc_ac

scc_bc

equ

org

09000h

;top of user ram area

inttest:

ld

sp,top_of_sp

;init sp

ld

a,high sccvect and 0ffh

;init i reg

ld

i,a

im

call

ld

2

;set interrupt mode 2

;initialize scc

;clear status

initscc

b,0

ei

;enable interrupt

wait_loop:

wait_here:

bit

jr

1,b

z,wait_loop

;check int status

;if not, loop again

jr

$

;interrupt has been received

;you can set breakpoint here!

;subroutine to initialize scc registers

;initialization table format is

;register number, then followed by the data to be written

;and the register number is 0ffh, then return

initscc:

init0:

ld

hl,scctab

a,(hl)

0ffh

z

(scc_cont),a

hl

a,(hl)

(scc_cont),a

;initialize scc

;get register number

;reached at the end of table?

;yes, return.

cp

ret

out

inc

ld

out

inc

jr

;write it

;point to next data

;get the data to be written

;write it

;point to next data

;then loop

hl

init0

6-47

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

Table 12. SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interrupt) (Continued)

;external/status interrupt

service routine

ext_stat:

ld

a,10h

out

in

(scc_cont),a

a,(scc_cont)

00100000b

;reset ext/stat int

;read stat

;mask off bits other than /cts

;shift into D0 loc

and

rra

set

ld

1,a

b,a

;set interrupt ﬂag

;save it

ld

out

ei

a,38h

(scc_cont),a

;reset highest ius

;enable int

ret

;return from int

;initialization data table for scc

;table format - register number, then value for the register

;and ends with 0ffh - since scc doesn’t have

;register 0ffh...

scctab:

db

scc_a

db

09h

;select WR9

;ch a reset

;ch b reset

if

10000000b

01000000b

else

endif

db

0eh

20h

;select WR15

;only enable /cts int

db

01h

00000001b

;select WR1

;enable ext/stat int

db

10h

;reset ext/stat int

;twice

db

09h

08h

;select WR9

;mie, vect not incl. stat

db

0ffh

;end of table

;interrupt vector table

sccvect:

org

dw

inttest + 100h

ext_stat

.block

end

100h

;reserve area for stack

top_of_sp:

6-48

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Table 13 shows a “macro” to enable the Z180 to use the

Z80 Assembler, as well as register definitions.

chip DMA. The SCC self loop-back test transfers data

using the Z180 DMA at the highest transmission rate

(Table 13).

There is one good test to ensure proper function. Generate

a data transfer between the Z180/SCC using the Z180 on-

7

Table 13. Program Example – Z180 CPU Macro Instructions

File name - 180macro.lib

Macro library for Z180 new instructions for asm800

;*

;

;Z180 System Control Registers

;ASCI Registers

cntla0:

cntla1:

cntlb0:

cntlb1:

stat0:

stat1:

tdr0:

tdr1:

rdr0:

rdr1:

equ

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

; ASCI Cont Reg A Ch0

; ASCI Cont Reg A Ch1

; ASCI Cont Reg B Ch0

; ASCI Cont Reg B Ch1

; ASCI Stat Reg Ch0

; ASCI Stat Reg Ch1

; ASCI Tx Data Reg Ch0

; ASCI Tx Data Reg Ch1

; ASCI Rx Data Reg Ch0

; ASCI Rx Data Reg Ch1

;CSI/O Registers

cntr:

trdr:

equ

0ah

0bh

; CSI/O Cont Reg

; CSI/O Tx/Rx Data Reg

;Timer Registers

tmdr0l:

tmdr0h:

rldr0l:

rldr0h:

tcr:

tmdr1l:

tmdr1h:

rldr1l:

rldr1h:

frc:

equ

0ch

0dh

0eh

0fh

10h

14h

15h

16h

17h

18h

; Timer Data Reg Ch0-low

; Timer Data Reg Ch0-high

; Timer Reload Reg Ch0-low

; Timer Reload Reg Ch0-high

; Timer Cont Reg

; Timer Data reg Ch1-low

; Timer Data Reg Ch1-high

; Timer Reload Reg Ch1-low

; Timer Reload Reg Ch1-high

; Free Running Counter

;DMA Registers

sar0l:

equ

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2ah

2bh

2ch

; DMA Source Addr Reg Ch0-low

; DMA Source Addr Reg Ch0-high

; DMA Source Addr Reg Ch0-b

; DMA Dist Addr Reg Ch0-low

; DMA Dist Addr Reg Ch0-high

; DMA Dist Addr Reg Ch0-B

; DMA Byte Count Reg Ch0-low

; DMA Byte Count Reg Ch0-high

; DMA Memory Addr Reg Ch1-low

; DMA Memory Addr Reg Ch1-high

; DMA Memory Addr Reg Ch1-b

; DMA I/O Addr Reg Ch1-low

; DMA I/O Addr Reg Ch1-high

sar0h:

sar0b:

dar0l:

dar0h:

dar0b:

bcr0l:

bcr0h:

mar1l:

mar1h:

mar1b:

iar1l:

equ

iar1h:

6-49

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

Table 13. Program Example – Z180 CPU Macro Instructions (Continued)

bcr1l:

bcr1h:

dstat:

dmode:

dcntl:

equ

2eh

2fh

30h

31h

32h

; DMA Byte Count Reg Ch1-low

; DMA Byte Count Reg Ch1-high

; DMA Stat Reg

; DMA Mode Reg

; DMA/WAIT Control Reg

;System Control Registers

il:

itc:

equ

33h

34h

36h

38h

39h

3ah

3eh

3fh

; INT Vector Low Reg

; INT/TRAP Cont Reg

; Refresh Cont Reg

; MMU Common Base Reg

; MMU Bank Base Reg

; MMU Common/Bank Area Reg

; Operation Mode Control Reg

; I/O Control Reg

rcr:

cbr

bbr:

cbar:

omcr:

icr:

?b

?c

?d

?e

?h

?l

equ

0

1

2

3

4

5

7

?a

??bc

??de

??hl

equ

0

1

2

3

??sp

slp

mlt

in0

macro

db

11101101B

01110110B

endm

macro

db

?r

11101101B

01001100B+(??&?r AND 3) SHL 4

endm

macro

?r, ?p

out0

macro

db

?p, ?r

11101101B

db

00000001B+(?&?r AND 7) SHL 3

?p

endm

otim

6-50

macro

db

11101101B

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Table 13. Program Example – Z180 CPU Macro Instructions (Continued)

db

10000011B

endm

7

otimr

otdm

otdmr

tstio

macro

db

11101101B

10010011B

endm

macro

db

11101101B

10001011B

endm

macro

db

11101101B

10011011B

endm

macro

db

?p

11101101B

01110100B

?p

db

endm

tst

macro

db

iﬁdn

?r

11101101B

<?r>,<(hl)>

db

00110100B

else

ifdef

?&?r

db

00000100B+(?&?r AND 7) SHL 3

else

db

01100100B

?r

endif

endm

.list

end

6-51

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

Table 14 lists a program example for the Z180/SCC DMA transfer test.

Table 14. Test Program – Z180/SCC DMA Transfer

;

;* Test program for 180 DMA/SCC

;*

;* Test 180’s DMA function with SCC

;*

;* 180 dma - dma0 for scc rx data

;*

dma1 for scc tx data

async, X1 mode, 1 stop, speed = pclk/4

self loop-back

Connect W/REQ to DREQ0 of 180

DTR/REQ to DREQ1 of 180

B register returns status info:

Bit D0 set : Tx DMA end

D1 set : Rx DMA end

D2 set : Data doesn’t match

.z800

;

Read in Z180 register names and

;macro for Z180 new instructions

*include 180macro.lib

;SCC Registers

scc_ad:

scc_ac:

scc_bd:

scc_bc:

scc_a:

equ

0C3h

0C2h

0C1h

0C0h

00h

;addr of scc ch a - data

;addr of scc ch a - control

;addr of scc ch b - data

;addr of scc ch b - control

;if test ch. a, set this to 0ffh

;for ch.b, set this to 00h

if

scc_cont:

scc_data:

else

scc_a

equ

scc_ac

scc_ad

scc_cont:

scc_data:

endif

equ

scc_bc

scc_bd

length:

equ

org

1000h

;transfer length

;top of user ram area

;init sp

09000h

sccdma:

ld

sp,tx_buff

ld

a,(high z180vect) and 0ffh ;init i reg

i,a

ld

a,00h

(il),a

2

ﬁll_mem

initscc

;init il

out0

im

call

;Set interrupt mode 2

;initialize tx/rx buffer area

;initialize scc

6-52

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Table 14. Test Program – Z180/SCC DMA Transfer (Continued)

call

ld

initdma

b,0

;init status

7

ld

a,00h

;load 1st data to be sent

out

(scc_data),a

ld

out0

a,11001100b

(dstat),a

;enable dmac and int from DMA0

ld

out

ld

a,05h

;select WR5

;start tx

(scc_cont),a

a,01101000b

(scc_cont),a

out

ei

;wait here for completion

loop:

bit

jr

1,b

z,loop

;rx dma end?

;not, then loop again

push

ld

bc

;save bc reg

;compare tx data with rx data

bc,length

de,tx_buff

hl,rx_buff

ld

chkloop:

ld

a,(de)

cpi

jr

nz,bad_data

v,good

de

chkloop

bc

2,b

enddma

bc

jp

inc

jr

pop

set

jr

bad_data:

good:

;restore bc

;set error ﬂag

pop

;restore bc

enddma:

;

jr

$

;tx/rx completed

you can put breakpoint here

ﬁll_mem:

l

d

ld

hl,temp

; prepare data to be sent

; set length

bc,length

de,tx_buff

(hl),00h

ﬁll_loop:

ldi

jp

nv,ﬁll_00

hl

(hl)

dec

inc

jr

ﬁll_loop

ﬁll_00:

ﬁll_00l:

ld

ldi

ret

dec

jr

bc,length

de,rx_buff

(hl),00h

; clear rx buffer area to zero

nv

hl

ﬁll_00l

6-53

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

Table 14. Test Program – Z180/SCC DMA Transfer (Continued)

initscc:

init0:

ld

hl,scctab

a,(hl)

; initialize scc

cp

ret

out

inc

ld

0ffh

z

(scc_cont),a

hl

a,(hl)

out

inc

jr

(scc_cont),a

hl

init0

;initialize z180’s scc

;

initdma:

ld

hl,addrtab

;initialize DMA

ld

c,sar0l

ld

b,dstat - sar0l

otimr

ld

out0

ld

a,00001100b

(dmode),a

a,01001000b

;dmac0 - i/o to mem++

;1 mem wait, no i/o wait,

;should be EDGE for Tx DMA

;NOT level

;- because of DTR/REQ timing

ret

txend:

ld

a,00010100b

(dstat),a

0,b

;isr for dma1 int-complete tx

;disable dma1

;set status

out0

set

ei

ret

rxend:

ld

a,00100000b

(dstat),a

1,b

;isr for dma0 int

;disable dma0

;set status

out0

set

ei

ret

;initialization data table for scc

;table format - register number, then value for the register

;and ends with 0ffh - since scc doesn’t have

;register 0ffh...

scctab:

db

09h

;select WR9

;reset ch a

if scc_a

else

10000000b

01000000b

;Reset Ch B

endif

db

04h

00000100b

;select WR4

;async,x1,1stop,parity off

6-54

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

Table 14. Test Program – Z180/SCC DMA Transfer (Continued)

db

01h

01100000b

;select WR1

;REQ on Rx

7

db

02h

00h

;select WR2

;00h as vector base

db

03h

11000000b

;select WR3

;Rx 8bit/char

db

05h

01100000b

;select WR5

;tx 8bit/char

db

06h

00h

;select WR6

;

db

07h

00h

;select WR7

;

db

09h

00000001b

;select WR9

;stat low, vis

db

;

0ah

00000000b

0bh

01010110b

0

;select WR10

;set as default

;select WR11

;

No xtal

;

1010

TxC,RxC from BRG

TRxC = BRG output

110

db

0ch

00h

;select WR12

;BR TC Low

db

0dh

00h

;select WR12

;BR TC high

db

0eh

;select WR14

db

00010110b

;

000

1

nothing about DPLL

Local loopback

No local echo

0

1

DTR/REQ is req

BRG source = PCLK

Not enabling BRG yet

0

db

0eh

00010111b

;select WR14

;

000

1

nothing about DPLL

Local loopback

No local echo

DTR/REQ is REQ

BRG source = PCLK

Enable BRG

0

1

db

03h

11000001b

;select WR3

;rx enable

6-55

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

(Continued)

Table 14. Test Program – Z180/SCC DMA Transfer (Continued)

db

01h

11100000b

;select WR1

;enable DMA

db

0fh

00000000b

10h

;select WR15

;don’t use any of ext/stat int

;reset ext/stat twice

10h

db

01h

11100000b

;select WR1

;no int

db

09h

00001001b

;select WR9

;enable int

db

0ffh

;end of table

;source/dist addr table for Z180’s dma

addrtab:

db

scc_data

00h

;dmac0 source

dw

db

rx_buff

00h

;dmac0 dist

dw

length

;byte count

;mar

dw

db

tx_buff+1

00h

db

scc_data

00h

;iar

db

00h

;dummy!

dw

length-1

;byte count

;interrupt vector table

z180vect:

org

sccdma + 200h

2

.block

dw

;180 int1 vect 00000

;180 int2 vect 00010

;180 prt0 vect 00100

;180 prt1 vect 00110

;180 dmac0 vect 01000

;180 dmac1 vect 01010

;180 csi/o vect 01100

;180 asci0 vect 01110

;180 asci1 vect 10000

2

rxend

txend

2

dw

.block

org

sccdma + 1000h

tx_buff:

rx_buff:

temp:

.block

length

1

end

6-56

UM010901-0601

Application Note

The Z180™ Interfaced with the SCC at MHZ

First, this program (Table 14) initializes the SCC by:

DMAC1: For Tx data transfer: Mem to I/O, Source

address-increasing, Destination address - fixed. Edge

sense mode: Interrupt on end of transfer.

Async, X1 mode, 8-bit 1 stop, Non-parity.

Tx and Rx clock from BRG, and BRG set to

PCLK/4.Self Loopback

7

Now, start sending with DMA.

Then, it initializes 4K bytes of memory with a repeating

pattern beginning with 00h and increases by one to FFh

(uses this as Tx buffer area). Also, it begins another 4K

bytes of memory as a Rx buffer with all zeros. After

starting, DMA initialization follows:

On completion of the transfer, the Z180 DMAC1 generates

an interrupt. Then, wait for the interrupt from DMAC0

which shows an end of receive. Now, compare received

data with sent data. If the transfer was successful (source

data matched with destination), 00h is left in the

accumulator. If not successful, 0FFh is left in the

accumulator.

DMAC0: For Rx data transfer: I/O to Mem, Source

address- fixed, Destination address-increasing. Edge

sense mode: Interrupt on end of transfer.

This program example specifies a way to initialize the SCC

and the Z180 DMA.

CONCLUSION

This Application Note describes only one example of

implementation, but gives you an idea of how to design the

system using the Z180™ and SCC.

For further design assistance, a completed board together

with the Debug/Monitor program and the listed sample

program are available. If interested, please contact your

local Zilog sales office.

6-57

UM010901-0601

7-58

UM010901-0601

APPLICATION NOTE

8

THE ZILOG DATACOM FAMILY WITH THE 80186 CPU

8

ilog’s datacom family evaluation board features the 80186 along with four multiprotocol

serial controllers, and allows customers to evaluate these components in an Intel

environment.

Z

INTRODUCTION

Zilog’s customers need a way to evaluate its serial

communications controllers with a central CPU. This App

Note (Application Note) explains and illustrates how the

datacom family interfaces and communicates with the

80186 on this evaluation board. The board helps the

potential customer to evaluate Zilog’s data communications

controllers in an Intel environment.

The most advanced and complex component of the serial

family is the IUSC. One of the highlights of this App Note

is how the IUSC adapts to the 80186 CPU with a minimum

of difficulty and a maximum of bus and functional flexibility.

GENERAL DESCRIPTION

The evaluation board includes the following hardware.

(Reference two page Schematic diagram at rear of the App

Note - Figures 5A and 5B.)

■ Four Altera EPLD circuits comprising the glue logic

(Figures 1-4 at rear of the App Note) and Evaluation

Board Schematic (Figures 5a, 5b)

■ Intel 80186 Integrated 16-bit Microprocessor

■ RS-232 and RS-422 line drivers and receivers

■ Zilog Z16C32 Integrated Universal Serial Controller

■ Pin headers for configuring and interconnecting the

(IUSC™)

above to serial applications

■ Zilog Z16C33 Monochannel Universal Serial Controller

Notes:

®

(MUSC™) or USC

All Signals with a preceding front slash, “/”, are active Low,

e.g.: B//W (WORD is active Low); /B/W (BYTE is active

Low, only).

■ Zilog Z16C35 Integrated Serial Communications

Controller (ISCC™)

Power connections follow conventional descriptions

below:

■ Zilog Z85230 Enhanced Serial Communications

Controller (ESCC™) or SCC

Connection

Power

Circuit

Device

■ Two 28-pin EPROM sockets, suitable for 2764’s through

V

27512’s

CC

DD

Ground

GND

V

SS

■ Six 32-pin (or 28-pin) SRAM sockets, suitable for

32K x 8 or 128K x 8 devices

6-59

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

GENERAL DESCRIPTION (Continued)

The 80186’s mid-range memory chip select feature

(specifically, the /MCS2 output) is used to give the

software a way to hardware Reset the ISCC, IUSC, and

(M)USC. This allows a customer’s program to operate as

if it were in a target system starting from Reset, including

the initial write to the Bus Configuration Register (BCR).

Processor

The 80186 may be operated at rates up to 16 MHz. To use

the CPU clock for accurate serial bit clocking, a 9.8304

MHz CPU clock can be used. The crystal connected to the

processor is 2X the operating frequency.

The processor’s 1 Mbyte address space is well filled if the

maximum RAM complement is installed. Of the integrated

Chip Select outputs provided by the 80186, the /UCS

output is used for the EPROMs, and all of the /PCS6-

/PCS0 outputs are used for the datacom controllers. A

hardware address decoder is used for the SRAMs instead

of the 80186’s /LCS and /MCS3-/MCS0 outputs because

the RAMs must be accessible to the on-chip DMA

functions of the ISCC and IUSC as well as the 80186. The

80186 does not decode addresses from external bus

masters. Both 8-bit and 16-bit accesses are provided for

RAM. The EPROMs are only accessible to the 80186.

The 80186’s two integrated DMA channels can be used for

any two of the four or six serial data streams in the B side

of the (E)SCC and the (M)USC. The “DMA EPLD” derives

requests for the 80186’s two DMA channels from six

inputs, two each for (E)SCC channel B and the one or two

channels in the (M)USC. It asserts DREQ0 or DREQ1

(High) if any of the inputs for that channel is low, and the

80186 is not performing an Interrupt Acknowledge cycle.

Jumper blocks J22, J23, J24, and J29 control the

assignment of the 80186’s internal DMA controllers,

including provision for a clipped Tx request that is needed

if a standard SCC is installed in place of the ESCC. The

various possibilities are summarized in Table 1.

Table 1. 80186 DMA Jumper Connections

To enable the following to use 80186 DMA Channel 0:

Install this jumper:

(E)SCC B Rx

J23-1 to J23-2

J22-1 to J22-2

J22-4 to J22-2

J29-1 to J29-2

J29-4 to J29-2

MUSC Rx or USC A Rx

MUSC Tx or USC A Tx

USC B Rx

USC B Tx

To enable the following to use 80186 DMA Channel 1:

Install this Jumper:

ESCC B Tx

J24-1 to J24-3

J24-1 to J24-2

J22-1 to J22-3

J22-4 to J22-3

J29-1 to J29-3

J29-4 to J29-3

(E)SCC B Tx w/early release

MUSC Rx or USC A Rx

MUSC Tx or USC A Tx

USC B Rx

USC B Tx

If more than one channel among the ESCC B and (M)USC

are enabled for one of the 80186’s internal DMA channels,

software must ensure that only one of the enabled devices

makes requests during a given block transfer. This can be

done by leaving an entire Receiver or Transmitter idle or

disabled, or by programming the device so that the DMA

request is not output on the pin.

header labelled J26 so that they can be used in

applications (Table 2).

Table 2. Counter/Timer Signal Locations

J26 pin

Signal

1

2

3

4

5

6

Timer In 1

Timer Out 1

Timer In 0

Timer Out 0

N/C

The ISCC and IUSC handle their own DMA transfers via

the 80186’s HOLD/HLDA facility.

Note: Either a Z16C33 MUSC or a Z16C30 USC can be

installed in socket U5. If this is done, references to the

(M)USC herein after may mean the USC as a whole or just

its channel A; which one should be clear from the context.

Ground

The 80186’s integrated interrupt controller is largely

bypassed in favor of the traditional Zilogical interrupt

daisy-chain structure.

The inputs and outputs associated with the processor’s

integrated counter/timer facility are brought to the pin

6-60

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

Push buttons are provided for Reset and Non-Maskable

Interrupt (NMI). A means to generate an NMI, in response

to a Start bit received from the user’s PC or terminal, is

also provided. The first transmitted Start bit on the RS-232.

Console connector J1, after a Reset, also produces an

NMI; this feature can be used to find which serial controller

channel is connected to the Console connector.

addresses of the datacom controllers are programmed in

the 80186 for the /PCS6-/PCS0 outputs, as a block of

128x7=896 bytes starting at a 1 Kbyte boundary. The

block can be in I/O space or in a part of memory space that

is not used for SRAM or EPROM. The starting 1 Kbyte

boundary is called (PBA) in the following sections.

8

RAM extends upward from address 0.

Address Map

Using 128K x 8 SRAMs and 64K x 8 EPROMs, the

address map might be as shown in Table 3.

EPROM is located at the highest addresses, and its size is

programmable in the 80186 for the /UCS output. The

Table 3. Suggested Address Map

RAM

00000-BFFFF

(E)SCC

ISCC

(M)USC

D8000, 2, 4, 6 or D8000-D803E (even addrs only)

D8080-D80FE (even addrs only)

D8100-D81FF

IUSC

D8200-D837F

ISCC-IUSC-(M)USC Reset

27512 EPROM

DB000-DB7FF (if enabled)

E0000-FFFFF

EPROM

Two 28-pin EPROM sockets are provided; both must be

populated in order to handle the 80186’s 16-bit instruction

fetches. Jumper header J18 allows the sockets to be

compatible with 2764s, 27128s, 27256s, or 27512s; it is

jumpered at the factory to match the EPROMs provided.

For 27512s only, jumper J18-J2 to J18-J3 and leave J18-

J1 open. For 2764s, 27128s, or 27256s, jumper J18-J2 to

J18-J1 and leave J18-J3 open.

must be programmed to correspond to the size of

EPROMs used (Table 4).

Table 4. EPROM Address Ranges

EPROM

Type

Address

EPROM Range

UMCS Value

2764

27128

27256

27512

FC3C FC000-FFFFF

F83C

F03C

E03C

F8000-FFFFF

F0000-FFFFF

E0000-FFFFF

Note: J18 connects pin 1 of both sockets to either A16 or

Vcc. This is done because for 2764s, 27128s, and 27256s,

pin 1 is Vpp which may require a high voltage and/or draw

more current than a normal logic input. For 2764s and

27128s, a similar jumper might be provided in some

designs for pin 27 (/PGM). As long as the address for /UCS

is programmed as described in the next paragraph, A15

(which is connected to pin 27) is High whenever /UCS is

Low, so that 2764s and 27128s operate correctly.

The three LSBs of the above UMCS values are all 100,

which signifies no external Ready/WAIT is used and no

wait states are required. If the EPROMs are not fast

enough for no-wait-state operation, making the three LSBs

101, 110, or 111 extends EPROM cycles by 1, 2, or 3 wait

states, respectively.

The first code executed after Reset should program the

80186’s Chip Select Control Registers to set up the

address ranges for which outputs like /UCS and /PCS6-

/PCS0 are asserted. In particular, the UMCS register

(address A0H within the 80186’s Peripheral Control Block)

6-61

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

RAM

Six 32-pin sockets are provided; they should be populated

in pairs, starting with the lower-numbered sockets, to allow

for 16-bit accesses. V_CCis provided at both pin 32 and pin

30 so that 28-pin 32K x 8 SRAMs can be installed in pins

3-30 of the sockets. Jumper block J19 allows decoding of

the Chip Select signals from A17-A16 for 32K x 8 SRAMs

or from A19-A18 for 128K x 8 SRAMs. The six standard

memory populations are:

One pair of 32K x 8 devices:

Two pairs of 32K x 8 devices:

Three pairs of 32K x 8 devices:

One pair of 128K x 8 devices:

Two pairs of 128K x 8 devices:

Three pairs of 128K x 8 devices:

64 Kbytes at 00000-0FFFF

128 Kbytes at 00000-1FFFF

192 Kbytes at 00000-2FFFF

256 Kbytes at 00000-3FFFF

512 Kbytes at 00000-7FFFF

768 Kbytes at 00000-BFFFF

J19 is factory set according to the size of the SRAMs

provided. For 32K x 8 SRAMs, jumpers are installed

between J19-J2 and J19-J3, and between J19-J5 and J19-

J6, with J19-J1 and J19-J4 left open. For 128K x 8 SRAMs,

jumpers are installed between J19-J1 and J19-J2, and

between J19-J4 and J19-J5, with J19-J3 and J19-J6 left

open.

■ Using 27256 EPROMs, or

■ Using 27512 EPROMs but programming the size of

/UCS like they are 27256s.

Since the /LCS output of the 80186 is not used, the LMCS

register in the 80186 is not written with any value.

Programming the Peripheral Chip Selects

32K x 8 SRAMs have cyclic/redundant addressing starting

at 40000, 80000, and C0000. The only configuration in

which this causes problems is with three pairs of 32K x 8

SRAMs and 27512 EPROMs; in this case, there is a

conflict in the range E0000-EFFFF. This conflict can be

avoided by any of the following means:

The 80186 allows the /PCS6-/PCS0 pins, which in this

case select the various datacom controllers, to be

asserted for a selected 896-byte block of addresses. The

block may reside in either memory or I/O space depending

on the values programmed into the PACS and MPCS

registers, locations A4H and A8H of the 80186’s

Peripheral Control Block, respectively. The choice of

address space depends on the needs of the customer’s

application and the configuration of software supplied with

the board (Table 5).

■ Using two pairs of 32K x 8 SRAMs;

■ Using one pair of 128K x 8 SRAMs;

Table 5. Three Standard Alternatives for Serial Controller Addressing

Basic Requirement

Base Address (PBA)

PACS value

MPCS value

I/O Space

Memory Space, 32K x 8 SRAMS used

Memory Space, 128K x 8 SRAMs used

8000

38000

D8000

0838

3838

D838

81B8

81F8

The three LSBs of the PACS value specify the

Ready/WAIT handling for the /PCS3-/PCS0 lines which

select the (E)SCC, ISCC, and (M)USC. The three LSBs of

the MPCS value specify the Ready/WAIT handling for the

/PCS4, 5, and 6 lines, which select the IUSC. Both fields

are shown here with the LSB’s 000, signifying that the

80186 should honor a WAIT on the external Ready/WAIT

signal, but that it should not provide any minimum wait.

software, it includes a means whereby software (e.g., the

debug monitor) can assert the /RESET input of these three

devices. Specifically, assertion of the /MCS2 output of the

80186 causes such a Reset.

The 81 in the MS Byte of the MPCS values, shown in Table

5, makes each of the /MCS3-/MCS0 pins correspond to a

2 Kbyte block of addresses in memory space. The actual

active pin addresses are determined by the value written

into the MMCS register; location A6H of the 80186'

Peripheral Control Block. Table 6 shows suggested

MMCS values as a function of the RAM chip size, and the

corresponding range of addresses for which any read or

write access causes the three controllers to be reset.

Programming the Mid-Range Memory to Reset the

ISCC, IUSC, and (M)USC

A Reset puts the ISCC, IUSC, and (M)USC in a special

and unique state in which the first write to each device

implicitly goes to a Bus Configuration Register (BCR) that

controls the device’s basic bus operation; the BCR is not

accessible thereafter. So that this board can serve as a

complete development environment for customers’

6-62

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

Table 6. Address Ranges for Reset

Address Range for which ISCC,

IUSC, and (M)USC are Reset:

RAM Size

MMCS value

8

32K x 8

128K x 8

3BFF

DBFF

3B000-3B7FF

DB000-DB7FF

The three LSBs of the above MMCS values are 111 so that

the longest possible Reset pulse is generated when any of

the locations in the indicated range are accessed.

Interrupt Daisy Chain (Priority) Order

Jumper block J25 selects whether the (E)SCC device is at

the start or the end of the interrupt daisy chain.

Note that if this feature is not needed, it can be disabled by

simply not programming the MMCS register.

To make the interrupt priority be:

Jumper J25 as follows:

(E)SCC highest, IUSC, ISCC, (M)USC lowest

IUSC highest, ISCC, MUSC, (E)SCC lowest

IUSC highest, ISCC, USC, (E)SCC lowest

J25-J2 to J25-J3, J25-J4 to J25-J5 (J25-J1, J25X open)

J25-J1 to J25-J2, J25-J to J25-J4 (J25-5J, J25X open)

J25X to J25-J2, J25-J3 to J25-J4 (J25-J1, J25-J5 open)

This variability is provided in part because early versions

of the 85230 ESCC had trouble passing an interrupt

acknowledge down the daisy chain if it occurred in

response to a lower-priority device’s request just as the

ESCC was starting to make its own request. Current

85230’s don’t have the problem.

6-63

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

(E)SCC

Socket U2 can be configured for either an ESCC or SCC,

and for versions thereof that use either multiplexed or non-

multiplexed address and data. Jumper blocks J20 and J21

select certain signals accordingly. For a part with

multiplexed addresses and data (80x30), jumper J20-J1 to

J20-J2 and leave J20-J3 open, and jumper J21-J1 to J21-

J2 and J21-J4 to J21-J5, leaving J21-J3 and J21-J6 open.

With such a part, software can directly address the

(E)SCC’s registers, and need not concern itself with

writing register addresses to Write Register 0 (WR0).

Jumper block J24 determines how channel B’s /DTR/

/REQB output is used. To use this output for the Data

Terminal Ready function, jumper J24-J3 to J24-J4 and

leave J24-J1 and J24-J2 open. To use this output directly

as a Transmit DMA Request (using the ESCC’s early-

release capability), jumper J24-J1 to J24-J3 and leave

J24-J2 and J24-J4 open. To drive the Transmit DMA

Request with a clipped version of this signal that is forced

High earlier than a standard SCC drives it High, jumper

J24-J1 to J24-J2 and leave J24-J3 and J24-J4 open.

For a part having a non-multiplexed bus (85x30), jumper

J20-J2 to J20-J3, J21-J2 to J21-J3, and J21-J5 to J21-J6,

leaving J20-J1, J21-J1, and J21-J4 open. In this case,

software must handle the (E)SCC by writing register

addresses into its WR0 in order to access any register

other than WR0, RR0, or the data registers.

The “SCC EPLD” handles the (E)SCC’s signalling

requirements. Among other things, this EPLD configures

the (E)SCC socket’s pins 35 and 36 for either a

multiplexed or non-multiplexed part, based on whether J20

is jumpered to connect the 80186 ALE signal to one of its

input pins. If the device detects high-going pulses on this

input, it drives corresponding low-going Address Strobe

pulses onto (E)SCC pin 35 and drives low-going Data

Strobe pulses onto (E)SCC pin 36.

Channels A and B can be handled on a polled or interrupt-

driven basis. Channel A of the (E)SCC is suggested for

connecting the user’s PC or terminal for use with the

Debug Monitor included in this evaluation kit. Channel B

(but not A) can be handled on a DMA basis using the

80186’s internal DMA channels, or on a polled or interrupt

driven basis.

If the SCC EPLD’s pin 9 stays at Ground, the part drives

Read strobes onto pin 36 and drives delayed Write strobes

onto pin 35, for a non-multiplexed 85x30 device.

While the ESCC’s relaxed timing capability allows the

80186’s /WR output to be connected directly to the /WR

input of a non-multiplexed ESCC, the SCC EPLD delays

start of an SCC’s write cycle until write data is valid, even

though this is not necessary for an ESCC.

Jumper block J23 allows channel B’s /W//REQB output to

be used for either a Wait function or a Receive DMA

Request function. To use the output for Wait, jumper J23-

J2 to J23-J3 and leave J23-J1 open. The Wait function is

only significant if the software wants to delay completion of

a Read from the (E)SCC’s Receive Data register until data

is available, and/or if it wants to delay completion of a Write

to the Transmit Data register until the previously-written

character has been transferred to the Transmit Shift

register. These modes are alternatives to checking the

corresponding status flags and can be used to achieve

operating speeds higher than those possible with such

traditional polling, although not as fast as the speeds

possible with a DMA approach.

The SCC EPLD also generates the clipped-DMA-request

signal mentioned in connection with J24, and logically ORs

Reset onto pins 35 and 36. The device also tracks the two

IACK cycles provided by the 80186 for each Interrupt

Acknowledge cycle. For a multiplexed address/data port, it

drives the address strobe (only) on the first cycle, and it

provides the /RD or /DS pulse needed by the (E)SCC

(only) on the second cycle. The “DMA EPLD” provides the

INTACK signal needed by the (E)SCC.

The (E)SCC is only accessible at even addresses. For a

non-multiplexed part (85x30), the following four register

locations are repeated throughout the even addresses

from (PBA) through (PBA)+126:

To use the /W//REQB output as a Receive DMA Request,

jumper J23-J1 to J23-J2 and leave J23-J3 open.

(PBA), (PBA)+8,... (PBA)+120

(PBA)+2, +10,... (PBA)+122

(PBA)+4, +12, ... (PBA)+124

(PBA)+6, +14, ... (PBA)+126

Channel B Command/Status register

Channel B Data register

Channel A Command/Status register

Channel A Data register

6-64

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

For a multiplexed part (80 x 30), the Select Shift Left

command (D1-0=11) should be written to Channel B’s

WR0 before any other registers are accessed. Then the

basic (E)SCC register map occurs twice in the even

addresses from (PBA) through (PBA)+126:

8

(PBA), (PBA)+2, ... (PBA)+30

(PBA)+32, +34, ... (PBA)+62

(PBA)+64, +66, ... (PBA)+94

(PBA)+96, +98, ... (PBA)+126

Channel B registers 0-15

Channel A registers 0-15

Channel B registers 0-15

Channel A registers 0-15

The redundant addressing of the (E)SCC is used to control

a feature that can be used by software to allow the user to

interrupt software execution from his keyboard. If the

(E)SCC is read at an address with A6-A5=11 (for a

multiplexed part this means in the higher-addressed A

channel), a mode is set in which a low on the console

Received Data line (i.e., a Start bit on pin 3 of the J1

connector) causes a Non-Maskable Interrupt on the

80186. The mode is cleared by Reset, or when the (E)SCC

is read at an address with A6-A5=10 (on a multiplexed

part, in the higher-addressed B channel). The NMI handler

should do the latter fairly quickly to prevent subsequent

data bits on Received Data from causing further NMIs.

ISCC

Since the 80186 processor provides multiplexed

addresses and data, the ISCC is configured to use the

addresses on the AD lines. Therefore, software can

address the various ISCC registers directly, and need not

be concerned with writing register addresses into the

indirect address fields of the ISCC’s WR0 and CCAR.

■ A Low on the ISCC’s SCC//DMA input, which is

connected to A6, is required by the internal logic of the

ISCC. This is why the BCR write is restricted to the first

half of the ISCC’s address range.

■ As with all transactions between the 80186 and ISCC,

the address must be even because the ISCC only

accepts slave-mode data on the AD7-AD0 pins.

Because the ISCC includes four DMA channels, its

Channel A and B Transmitters and Receivers can be

handled on a polled, interrupt-driven, and/or DMA basis, in

any mixture.

■ The MSB of the data (D7) is 1 to enable the Byte Swap

feature, so that when the ISCC’s DMA controller is

reading transmit data from RAM, it takes alternate bytes

from AD7-AD0 and AD15-AD8.

Since the ISCC can only be programmed as an 8-bit

device on the AD7-AD0 lines, it occupies only the even-

addressed bytes within its address range, (PBA)+128

through (PBA)+254.

■ D6 of the data is 1 so that when the ISCC’s DMA

controller is reading transmit data from RAM, it takes

even-addressed bytes from D7-D0 and odd-addressed

bytes from D15-D8 (same function as the 80186).

The first write to this address range, after a Reset,

implicitly writes the ISCC’s Bus Configuration Register

(BCR). To match up with the rest of the board’s hardware,

this first write should be a byte write that stores the

hexadecimal value C6 in any even address in the first half

of the ISCC’s address range [(PBA)+128 through

(PBA)+190]. Details of this transaction are as follows:

■ D2-D1 of the data are 11 to select double-pulsed mode

for the ISCC’s /INTACK input. Again, this is how the

80186 works.

■ D0 of the data is 0 to select Shift Left Address mode so

that the ISCC subsequently takes register addressing

from the AD5-AD1 lines rather than from AD4-AD0. This

is because the 80186 is a 16-bit processor that locates

even-addressed bytes on AD7-AD0 and odd-addressed

bytes on AD15-AD8, but the ISCC only accepts slave-

mode writes on the AD7-AD0 pins.

■ The High induced by a pull-up resistor on the ISCC’s A/B

input selects the WAIT protocol on the /WAIT//RDY pin,

which corresponds to how the 80186 works. (In

subsequent register accesses, the A/B selection is

taken from A5 of the multiplexed address.)

6-65

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

■ The fact that the ISCC’s internal logic sees activity on its

Given that the BCR is written as above, the ISCC’s slave-

mode address map is as follows:

/AS pin, which is inverted from the 80186' ALE signal,

automatically conditions it for

Address/Data bus.

a

multiplexed

(PBA)+128, 130, ..., (PBA)+190

(PBA)+192, 194, ..., (PBA)+222

(PBA)+224, 226, ..., (PBA)+254

DMA Controller Registers

ISCC Serial Channel B registers 0-15

ISCC Serial Channel A registers 0-15

(M)USC

Since the 80186 processor provides multiplexed

addresses and data, the (M)USC is configured to use the

addresses on the AD lines. Therefore, the software need

not write register addresses into the indirect address field

of the (M)USC’s CCAR.

range of the (M)USC is 256 bytes, between (PBA)+256

and (PBA)+511.

The first write to this address range, after a Reset,

implicitly writes the (M)USC’s Bus Configuration Register

(BCR). To match the rest of the board’s hardware, this first

write should be a 16-bit write, storing the hex value 0007

at any address in the second half of the (M)USC’s range

[any address in (PBA)+384 through 510, i.e., in the A

channel of a USC]. Details of this transaction are as

follows:

The (M)USC’s Transmitter and Receiver can be handled

on a polled or interrupt-driven basis. In addition, any two of

the Receivers and Transmitters in the (M)USC and

Channel B of the (E)SCC can be handled on a DMA basis,

using the 80186’s integrated DMA controllers.

Jumper block J22 connects the (M)USC’s /RxREQ and

/TxREQ outputs to the “DMA EPLD” that makes the DMA

Requests to the 80186. As shipped from the factory,

jumpers are installed between J22-J1 and J22-J2, and

between J22-J3 and J22-J4. In this configuration, the

(M)USC’s /RxREQ drives the 80186 DREQ0, and (M)USC

/TxREQ drives the 80186 DREQ1. To reverse this

assignment, jumper J22-J1 to J22-J3 and J22-J2 to J22-

J4. To disconnect the (M)USC from one or both of the

80186’s DMA channels, remove one or both jumpers (put

them in a safe place in case you change your mind).

Jumper block J29 provides the same connection-variability

for the /RxREQ and /TxREQ outputs of Channel B of a

USC.

■ The High on the PS or A//B input, which is connected to

A7, selects the WAIT protocol on the /WAIT//RDY pin,

corresponding to how the 80186 works.

■ The MSB of the data (D15) is 0 because a separate non-

multiplexed address is not wired to pins AD13:8 of the

(M)USC.

■ Bits 14-3 are required to be all zeros by the (M)USC’s

internal logic.

■ D2 of the data is 1 to tell the (M)USC that the data bus is

16 bits wide.

■ D1 of the data is 1 to select double-pulsed mode for the

(M)USC’s /INTACK input. This is how the 80186 works.

Since the 80186’s DMA channels are not capable of fly-by

operation, the (M)USC’s /RxACK and /TxACK pins have

no dedicated function. They can be used for Request to

Send and Data Terminal Ready; the two signals are lightly

pulled up since they are not driven after Reset.

■ D0 of the data is 1 to select Shift Right Address mode so

that the (M)USC subsequently takes register addressing

from the AD6-AD0 lines rather than from AD7-AD1.

■ The fact that the (M)USC’s internal logic sees activity

on its /AS pin, which is inverted from the 80186' ALE

signal, automatically conditions it for a multiplexed

Address/Data bus.

The (M)USC can be programmed using 16-bit data on the

AD15-AD0 lines or 8-bit data on AD15-AD8 and AD7-AD0.

It makes the distinction between 8-bit and 16-bit

operations as part of its address map rather than through

a control input. The PS pin of an MUSC, or the A//B pin of

a USC, is connected to a latched version of 80186 A7. The

D//C pin of the (M)USC is grounded. The overall address

Given that the BCR is written as above, the (M)USC

address map is as follows:

6-66

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

Starting Addr

Ending Addr

Registers Accessed

(PBA)+256

(PBA)+320

(PBA)+384

(PBA)+448

(PBA)+319

(PBA)+383

(PBA)+447

(PBA)+511

16-bit access to MUSC regs or USC channel B regs

8-bit access to MUSC regs or USC channel B regs

16-bit access to MUSC regs or USC channel A regs

8-bit access to MUSC regs or USC channel A regs

8

Note: To maximize compatibility, program an MUSC using the second half of this range, (PBA)+384 through (PBA)+511.

While the ESCC and ISCC can drive their Baud Rate

Generators from their PCLK inputs, the (M)USC has no

such input. The 80186 clock output SYSCLK is brought to

pins 7 of J9, J10, and J12, at which point it can be

jumpered to pin 9 or 8 so that it is routed to the /TxC or

/RxC pin of the device.

IUSC

Since the 80186 processor provides multiplexed

addresses and data on the AD lines, the IUSC is

configured to use these addresses. Software need not

write register addresses into the indirect address fields of

the IUSC’s CCAR and DCAR.

■ D7-D6 are 11 to allow the DMA controllers to do either

16-bit transfers, or alternating byte transfers on AD7-

AD0 for even-addressed bytes and on AD15-AD8 for

odd-addressed bytes. This is compatible with 80186

byte ordering.

The IUSC’s two DMA channels allow its Receiver and

Transmitter to be handled on a polled, interrupt-driven, or

DMA basis, in any combination.

■ D5-D4 of the data are 11 to select double-pulsed mode

for the IUSC’s /INTACK input. Again, this is how the

80186 works.

The IUSC can be programmed using 16-bit data on the

AD15-AD0 lines or 8-bit data on AD15-AD8 and AD7-AD0.

The distinction between 8-bit and 16-bit operations is

made as part of the address map rather than via a control

input. The D//C pin of the IUSC is driven from A7 during

slave cycles, and the S//D pin is driven from A8. The

overall address range of the IUSC is 384 bytes from

(PBA)+512 through (PBA)+895.

■ D3 of the data is 0 to select open-drain mode on the

IUSC’s /BUSREQ pin. The board’s control logic also

drives this signal low when the ISCC asserts its Bus

Request output.

■ D2 of the data is 1 to tell the IUSC that the data bus is 16

bits wide.

■ D1 of the data is 1 to select open-drain mode on the

IUSC’s /INT pin which is OR-tied with the interrupt

request from the (E)SCC.

The first write to this address range, after a Reset,

implicitly writes the IUSC’s Bus Configuration Register

(BCR). To match up with the rest of the board’s hardware,

this first write is a 16-bit write, storing the recommended

hex value 00F7 at any word address in the range

(PBA)+768 through (PBA)+830. Details of this transaction

are as follows:

■ D0 of the data is 1 to select Shift Right Address mode,

so that the IUSC subsequently takes register addressing

from the AD6-AD0 lines rather than from AD7-AD1.

■ The fact that the IUSC’s internal logic sees activity on its

/AS pin, which is inverted from the 80186' ALE signal,

■ The High on the IUSC’s S//D input, which is connected

to A8, selects the WAIT protocol on the /WAIT//RDY pin,

which is how the 80186 works.

automatically conditions it for

Address/Data bus.

a

multiplexed

Given that the BCR is written as above, the IUSC slave-

mode address map is as follows:

■ It may not be required for this initial write, but it is good

programming form for A6 to be zero since this is a word

write. This and the previous point determine the

recommended address range.

■ The MSB of the data (D15) is 0 because a separate non-

multiplexed address is not wired to pins AD13:8 of the

IUSC.

■ Bits 14-8 are more or less required to be all 0 by the

IUSC’s internal logic.

6-67

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

IUSC (Continued)

Starting Addr

Ending Addr

Registers Accessed

(PBA)+512

(PBA)+576

(PBA)+640

(PBA)+704

(PBA)+768

(PBA)+832

(PBA)+575

(PBA)+639

(PBA)+703

(PBA)+767

(PBA)+831

(PBA)+895

16-bit access to IUSC Transmit DMA registers

8-bit access to IUSC Transmit DMA registers

16-bit access to IUSC Receive DMA registers

8-bit access to IUSC Receive DMA registers

16-bit access to IUSC Serial Controller registers

8-bit access to IUSC Serial Controller registers

While the ESCC and ISCC can drive their Baud Rate

Generators from their PCLK inputs, the IUSC cannot do

this from its CLK input. The 80186 clock output SYSCLK is

brought to pins 7 of J9, J10, and J12 at which point it can

be jumpered to pin 9 or 8 so that it is routed to the /TxC or

/RxC pin of the device.

Since the IUSC contains its own DMA channels, its

/RxREQ and /TxREQ pins have no dedicated function.

They can be used for Request to Send and Data Terminal

Ready; the two signals are lightly pulled up to allow for the

fact that they are not driven after Reset.

SERIAL INTERFACING

The serial I/O pins of the four serial controllers are

connected to the six connector blocks labelled J5 through

J10. In addition, the port pins of the IUSC are connected to

the J11 connector block, and the port pins of an MUSC or

the B channel of a USC are connected to J12. These

connector blocks can be interconnected for communication

between on-board serial controllers, or they can be

connected to the user’s custom communications hardware

on another board. As a third option, they can be connected

to three on-board serial interfaces via the connector blocks

labelled J13 through J15.

connecting one of J5-J10 to J13 or J14, respectively. J1B

is typically used for connection to the user’s PC or

terminal.

The third on-board serial interface uses EIA-422 signal

levels on connector J3A,J3B, or J4, and is used by

connecting one of J5-J10 to J15. The 25-pin D connector

J3A uses the DTE pin arrangement put forth in the EIA-530

standard. J3B is a DCE version of EIA-530, while the 8-pin

circular DIN connector, J4, is compatible with the Apple

Macintosh Plus and later Macintoshes, and thus with

AppleTalk/LocalTalk equipment.

Two of the on-board serial interfaces use EIA-RS-232

signal levels and pin arrangement. 25-pin D connectors

J1A or J2A are configured as DTE, while J1B and J2B are

configured as DCE. These serial interfaces are used by

The serial interface connectors are summarized in the

following tables:

Table 7. Controller Port Connectors

To use the following serial controller channel

with off-board or on-board serial hardware:

Connect to this (these) 10-pin

connector block(s):

(E)SCC Channel A

(E)SCC Channel B

ISCC Channel A

ISCC Channel B

IUSC

J5

J6

J7

J8

J9 (J11 for Port pins)

J10 (J12 for MUSC Port pins

or USC channel B)

(M)USC

6-68

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

Table 8. On-Board Line Driver/Receiver Connectors

To use a serial chip controller with the

following on-chip serial interface:

Connect the connector(s)

from the previous table to:

8

J1A or J1B EIA-RS-232 Console

J2A or J2B EIA-RS-232

RS-422 differential: J3A or J3B EIA-530 or J4 Circular-8 (DIN)

J13

J14

J15

The pin-out of the J5-J10 connectors is fairly consistent,

but of necessity not identical because of differences

among the various serial controllers:

Table 9. Pin Assignments of Standard Controller Connectors

J5: (E)SCC J6: (E)SCC

J7,8: ISCC

J9: IUSC

J10: MUSC

J12: USC

B pin

Pin#

A pin

B pin

or USC A pin

1

TxD

2

RxD

3

4

5

6

7

8

9

10

11

12

/RTS

/CTS

/DTR

/DCD

/SYNC

/RTxC

/TRxC

GND

NA

/RTS

/CTS

/RTS

/CTS

/DTR

/DCD

/SYNC

/RTxC

/TRxC

GND

NA

(N/C)

/CTS

(N/C)

/DCD

(SYSCLK)

/RxC

/TxC

GND

/RxACK

/CTS

/TxACK

/DCD

(SYSCLK)

/RxC

/TxC

GND

/TxREQ

/RxREQ

/RxACK

/CTS

/TxACK

/DCD

(SYSCLK)

/RxC

/TxC

GND

/TxREQ

/RxREQ

/DTR or (N/C) [1]

/DCD

/SYNC

/RTxC

/TRxC

GND

NA

/TxREQ

/RxREQ

NA

Note:

[1] Controlled by the J24 jumper block: must be N/C if (E)SCC channel B transmitter is to be handled by an 80186 DMA channel.

The ground pins are included as signal references with off-

board hardware.

enough opposing inputs and outputs as needed to make

the communication protocol meaningful.

When interconnecting between two connectors among J5-

J10, DO NOT jumper corresponding pins straight across,

as this connects outputs to outputs and inputs to inputs.

Rather, connect at least each pin 1 to the other pin 2, and

The pin-out of the 12-pin J13-J15 connectors is similar to

that of J5-J10, but more extensive. To allow for the “DCE”

connectors that were added in revision “B” of the board,

J13 and J14 are 16-pin headers and J15 is a 14-pin one:

Table 10. Pin Assignments of Line Driver/Receiver Connectors

J13-J14

J15

Pin #

DTE signal

DCE signal

DTE signal

DCE signal

Direction/where used

1

2

3

4

5

6

TxD

RxD

/RTS

/CTS

/DTR

/DSR

RxD

TxD

/CTS

/RTS

/DSR

/DTR

TxD

RxD

/RTS

/CTS

/DTR

/DSR

RxD

TxD

/CTS

/RTS

/DSR

/DTR

Output to J1-J4

Input from J1-J4

Output to J1-J3

Input from J1-J4 [3]

Output to J1-J4

Input from J1-J4

Note:

[3] Various conventions have been used to combine synchronous clock inputs and modem control inputs on Apple Macintosh connectors

similar to J4, as described in a later section.

6-69

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

SERIAL INTERFACING (Continued)

Table 10. Pin Assignments of Line Driver/Receiver Connectors

J13-J14

J15

Pin #

DTE signal

DCE signal

DTE signal

DCE signal

Direction/where used

7

/DCD

Output to J1B, J2B, J3B

8

9

/DCD

GND

/DDC

GND

Input from J1A, J2A, J3A, J4

10

11

12

13

14

15

16

GND

/RxC

GND

/RxC

Output to J1B, J2B, J3B

Input from J1A, J2A, J3A

Output to J1-3

Input from J1-3 [3]

Output to J1B, J2B

Input from J1A, J2A

/RxC

/TxCO

/TxCI

/RxC

/TxCO

/TxCI

/TxCO

/RI

/TxCI

/TxCO

/RI

Note:

[3] Various conventions have been used to combine synchronous clock inputs and modem control inputs on Apple Macintosh connectors

similar to J4, as described in a later section.

Comparison of the two preceding charts leads to several

conclusions:

The 10-pin J11 and J12 jumper blocks provide for

connections to the Port pins of the IUSC and (M)USC,

respectively. As with J5-J10, these connections may be to

the customer’s off-board custom circuits and/or to certain

pins in the J13-J15 blocks. The following pin assignment is

determined so that if a 2-channel USC is plugged into the

(M)USC socket, J12 has the same pin-out for the USC’s B

channel as do J5-J10 for other channels.

■ Pins 1-5 can always be jumpered straight across from a

J5-J10 connector block to a J13-J15 connector block.

■ In a synchronous environment, the Transmit clock can

be either driven or received and the Receive clock can

be received from the DTE connector or sent on the DCE

connector.

Table 11. Pin Assignments of Controller Port Connectors

Pin #

J11: IUSC Signal

J12: (M)USC Signal

1

2

3

PORT1 (Clock 1 In)

PORT4 (Xmit TSA Gate Out)

(N/C)

PORT1

PORT4 (Xmit TSA Gate Out)

(N/C)

4

5

PORT0 (Clock 0 In)

(N/C)

PORT0

(N/C)

6

7

PORT3 (Rcv TSA Gate Out)

(N/C)

PORT3 (Rcv TSA Gate Out)

(SYSCLK)

8

9

PORT5 (Rcv Sync Out)

PORT2

PORT5 (Rcv Sync Out)

PORT2

10

11

12

GND

PORT6 (Rcv Sync In)

PORT7 (Xmit Complete Out)

PORT6 (Rcv Sync In)

PORT7 (Xmit Complete Out)

Finally, an unpopulated 4-pin oscillator socket is included

on the board with its output connected to a single

jumper/wire-wrap pin. This socket can be populated with a

user-supplied oscillator and connected to various clock

pin(s) among J5-J15.

6-70

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

Sensing which Serial Controller Channel is

connected to the Console

Notes on J4/Macintosh/AppleTalk/LocalTalk

The J4 connector is similar to that offered on various

Macintosh systems. The ESCC and ISCC are particularly

well adapted for use with this port, and development of

USC family capability for AppleTalk/LocalTalk is of

interest.

In order to use the software provided with this evaluation

board, one of the serial controller channels must be

connected to a Personal Computer (or a dumb terminal)

via the J1 and J13 connectors. Some versions of this

software may restrict the choice to (E)SCC Channel A or

the (M)USC, depending on the user’s applications needs,

but there is nothing in the hardware that limits the choice

of which serial channel is used for the Console. However,

on the J1-J4 (J13-J15) side there are two things that are

special about the J1/J13 section as compared to the

others. One is the provision for a Non-Maskable Interrupt

in response to a received Start bit, as described earlier in

the section on (E)SCC addressing.

8

The J3 and J4 connectors cannot be used simultaneously.

The J16 jumper block controls whether the RS-422 driver

for Transmit Data is turned “on” and “off” under control of

the associated Request to Send signal, as on the Mac, or

is “on” full time, which is more suitable for the use of J3. To

put the TxD driver under control of RTS, jumper J16-1 to

J16-J2 and leave J16-J3 open. For full-time drive on TxD

(and also the J3 RTS pins), jumper J16-J2 to J16-J3 and

leave J16-J1 open.

Software can use the other special feature of the J1/J13

section, after a Reset, to sense which serial channel is

connected to the Console port. A Reset signal (from

power-on or the Reset button, but not from the Reset-the-

ISCC, etc., address decode as described earlier) puts the

“NMI” EPLD in a special mode wherein the first Start bit on

the Console’s Transmit Data lead causes an NMI. This

feature can be used in a start-up procedure like the

following, to tell which serial controller channel is used for

the Console:

The J17 jumper block controls whether the reception of

Data Carrier Detect and Clear to Send is differential (on

J3) or unbalanced, as on J4. To use differential signalling

from J3, remove all jumpers from J17.

On the initial Macintosh and subsequent ones as well,

Apple did the unbalanced signalling backward from

standard RS-423 and RS-232 polarity for the CTS lead

(also called HSK and HSKI). If you are developing code for

Macintosh hardware, you can preserve Mac compatibility

by jumpering J17-J3 to J17-J5 and J17-J4 to J17-J6. This

grounds the CTS- lead and connects the CTS+ lead to J4-

J2. It also (assuming a standard source at the other end)

inverts CTS to the opposite sense from that expected by

the serial controller for functions such as auto-enabling. To

make the CTS input of the serial controller have its normal

(low-true) sense, jumper J17-J3 to J17-J4, and J17-J5 to

J17-J6– this grounds the CTS+ lead and connects the

CTS- lead to J4-J2.

For each serial controller channel that the software can

use for the Console:

1. Initialize the channel.

2. Send a NUL character to the channel.

3. Wait a short time to see if an NMI occurs. If so, the

current channel is the Console. If not, go on to the next

serial channel and try again.

The DTR (HSKO) output is provided in Apple systems from

Mac Plus onward and has standard RS-423 (and RS-232)

polarity.

If none of the allowed serial channels produces an NMI,

the user has not properly jumpered any J5-J10 connector

block to the J13 block.

The DCD input on J4-J7 is provided in Apple systems from

the Mac II and SE onward, and also has standard polarity

on Apple hardware. Jumper J17-J1 to J17-J2 to ground the

“+” input of the receiver; the “–” lead is connected to J4-J7.

Basic software should use the serial controller channel for

the Console in a very basic, polled way. Because of this

and because of similarities between the (E)SCC and the

ISCC, and between the (M)USC and the IUSC, note that

software allows the Console to be connected to either the

(E)SCC channel A or to the (M)USC; in fact, it includes

most of the code necessary to use any of the six serial

controller channels for the Console.

6-71

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

SERIAL INTERFACING (Continued)

With jumpers installed to make DCD and CTS unbalanced,

J4 can also be used for an additional RS-232 serial link.

Connect a “Mac to Hayes modem” cable to J4, and

optionally a null modem interconnect module to the other

end. The cable internally grounds the RxD+ and TxD+

leads so that RxD– and TxD– act like RS-232 signals.

On the Mac SE, Mac II, and later models, a multiplexing

scheme is provided on SCC channel A’s RTxC pin to drive

from either the same signal as DCD, or from an on-board

3.672 MHz clock. (Channel B always had the 3.672 MHz

clock.) The former capability can be provided by

connecting J15-J6 to pins 6 and 8 of the selected

connector among J5-J10. The latter capability can be only

approximated using the 80186 clock with different baud

rate divisors, or by using another oscillator. (The board

includes an unpopulated 4-pin oscillator socket that might

be useful in this regard.)

Macintosh systems also include provisions for

synchronous clock inputs. It is not known whether these

features are used by any applications, or attached

hardware. On all known Macs, the SCC’s TRxC pin is

driven from the same signal as CTS; to be compatible with

this feature, connect J15-J4 to pins 4 and 9 of the selected

connector among J5-J10.

6-72

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

JUMPER SUMMARY

Table 12 includes only those connector blocks intended to

be populated by 2-pin option jumpers. J1-J15 and J26 are

actual connectors meant for use with cables, jumper wires,

or wire-wrapped connections.

8

Table 12. Two-Pin Option Jumpers

Jumpers

Installed

Open

J9-J7 thru -9

7 to 8: 80186 SYSCLK is IUSC /RxC

7 to 9: 80186 SYSCLK is IUSC /TxC

8: Something else on /RxC, or N/C

9: Something else on /TxC, or N/C

J10-J7 thru -9

J12-J7 thru -9

J16-J1 thru -3

7 to 8: 80186 SYSCLK is MUSC (USC A) /RxC

7 to 9: 80186 SYSCLK is MUSC (USC A) /TxC

8: Something else on /RxC, or N/C

9: Something else on /TxC, or N/C

7 to 8: 80186 SYSCLK is USC B /RxC

7 to 9: 80186 SYSCLK is USC B /TxC

8: Something else on /RxC, or N/C

9: Something else on /TxC, or N/C

1 to 2: J3, J4 TxD driven when RTS

2 to 3: J3, J4 TxD, RTS driven full-time

Must install one or the other

J17-J1 to -2

J17-J3 thru -6

Unbalanced DCD- on J3 or J4

3 to 5 and 4 to 6: CTS+ on J4-J2

3 to 4 and 5 to 6: CTS- on J3 or J4

Differential DCD+, DCD- on J3

Differential CTS+, CTS- on J3

J18-J1 thru -3

J19-J1 thru -6

J20-J1 thru -3

J21-J1 thru -6

J22-J1 thru -4

1 to 2: 2764, 27128, 27256 EPROMs

2 to 3: 27512 EPROMs

Must install one or the other

1 to 2 and 4 to 5: 128K x 8 SRAMs

2 to 3 and 5 to 6: 32K x 8 SRAMs

Must install one way or the other

1 to 2: U2 contains 80C30 or 80230

2 to 3: U2 contains 85C30 or 85230

1 to 2 and 4 to 5: U2 contains 80C30 or 80230

2 to 3 and 5 to 6: U2 contains 85C30 or 85230

1 to 2: MUSC (USC A) RxREQ on DMA 0

1 to 3: MUSC (USC A) RxREQ on DMA 1

2 to 4: MUSC (USC A) TxREQ on DMA 0

3 to 4: MUSC (USC A) TxREQ on DMA 1

1: MUSC (USC A) Rx no DMA

4: MUSC (USC A) Tx no DMA

J23-J1 thru -3

J24-J1 thru -4

1 to 2: (E)SCC B RxRQ on DMA 0

2 to 3: (E)SCC B Wait function

(E)SCC B neither Rx DMA

nor Wait

1 to 2: clipped SCC B TxREQ on DMA 1

1 to 3: direct ESCC B TxREQ on DMA 1

3 to 4: /DTR output from ESCC B

(E)SCC B neither Tx DMA

nor /DTR

J25-J1 thru - 5 and J25X 1 to 2 and 3 to 4: (E)SCC last on IACK chain,

MUSC second to last

Must be one of these three ways

J25X to 2 and 3 to 4: (E)SCC last, USC 2nd to last

2 to 3 and 4 to 5: (E)SCC ﬁrst on IACK chain

J28-J1 thru -6

J29-J1 thru -4

1 to 2: 80186 SYSCLK is (E)SCC PCLK

3 to 4: 80186 SYSCLK is ISCC PCLK

5 to 6: 80186 SYSCLK is IUSC CLK

Connect some other clock to 2, 4, or 6

1 to 2: USC B RxREQ on DMA 0

1 to 3: USC B RxREQ on DMA 1

2 to 4: USC B TxREQ on DMA 0

3 to 4: USC B TxREQ on DMA 1

1: USC B Rx no DMA

4: USC B Tx no DMA

6-73

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

DMA/EPLD LOGIC

Figure 1. Control EPLD for 186 Board

6-74

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

8

Figure 2. SCC EPLD for 186 Board

6-75

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

DMA/EPLD LOGIC (Continued)

Figure 3. DMA EPLD for 186 Board

6-76

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

8

Figure 4. NMI Field for 186 Board

6-77

UM010901-0601

Application Note

The Zilog Datacom Family with the 80186 CPU

Figure 5. Schematic of the Evaluation Board

6-78

UM010901-0601

APPLICATION NOTE

9

SCC IN BINARY

SYNCHRONOUS COMMUNICATIONS

9

INTRODUCTION

Zilog’s Z8030 Z-SCC Serial Communications Controller is

one of a family of components that are Z-BUS compatible

One channel of the Z-SCC is used to communicate with

the remote station in Half Duplex mode at 9600

bits/second. To test this application, two Z8000

Development Modules are used. Both are loaded with the

same software routines for initialization and for

transmitting and receiving messages. The main program

of one module requests the transmit routine to send a

message of the length indicated in the ‘COUNT’

parameter. The other system receives the incoming data

stream, storing the message in its resident memory.

®

with the Z8000™ CPU. Combined with a Z8000 CPU (or

other existing 8- or 16-bit CPUs with nonmultiplexed buses

when using the Z8530 SCC), the Z-SCC forms an

integrated data communications controller that is more

cost effective and more compact than systems

incorporating UARTs, baud rate generators, and phase-

locked loops as separate entities.

The approach examined here implements a communications

controller in a Binary Synchronous mode of operation, with a

Z8002 CPU acting as controller for the Z-SCC.

DATA TRANSFER MODES

The Z-SCC system interface supports the following data

transfer modes:

■ Block/DMA Mode. Using the Wait/Request (/W//REQ)

signal, the Z-SCC introduces extra wait cycles to

synchronize data transfer between a CPU or DMA

controller and the Z-SCC.

■ Polled Mode. The CPU periodically polls the Z-SCC

status registers to determine the availability of a

received character, if a character is needed for

transmission, and if any errors have been detected.

The example given here uses the block mode of data

transfer in its transmit and receive routines.

■ Interrupt Mode. The Z-SCC interrupts the CPU when

certain previously defined conditions are met.

6-79

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

SYNCHRONOUS MODES

Three variations of character-oriented synchronous

communications are supported by the Z-SCC: Mono-sync,

Bisync, and External Sync (Figure 1). In Monosync mode,

a single sync character is transmitted, which is then

compared to an identical sync character in the receiver.

When the receiver recognizes this sync character,

synchronization is complete; the receiver then transfers

subsequent characters into the receiver FIFO in the Z-

SCC.

Bisync mode uses a 16-bit or 12-bit sync character in the

same way to obtain synchronization. External Sync mode

uses an external signal to mark the beginning of the data

field; i.e., an external input pin (SYNC) indicates the start

of the information field.

In all synchronous modes, two Cyclic Redundancy Check

(CRC) bytes can be concatenated to the message to

detect data transmission errors. The CRC bytes inserted in

the transmitted message are compared to the CRC bytes

computed to the receiver. Any differences found are held

in the receive error FIFO.

SYNC

DATA

CRC1

CRC2

A. MONOSYNC Mode

SYNC

DATA

B. BISYNC Mode

External

DATA

SYNC Symbol

DATA

CRC1

CRC2

C. External SYNC Mode

Figure 1. Synchronous Modes of Communication

SYSTEM INTERFACE

The Z8002 Development Module consists of a Z8002 CPU,

16K words of dynamic RAM, 2K words of EPROM monitor,

a Z80A SIO providing dual serial ports, a Z80A CTC

peripheral device providing four counter/timer channels, two

Z80A PIO devices providing 32 programmable I/O lines,

and wire wrap area for prototyping. The block diagram is

depicted in Figure 2. Each of the peripherals in the

development module is connected in a prioritized daisy-

chain configuration. The Z-SCC is included in this

configuration by tying its IEI line to the IEO line of another

device, thus making it one stop lower in interrupt priority

compared to the other device.

Two Z8000 Development Modules containing Z-SCCs are

connected as shown in Figure 3 and Figure 4. The

Transmit Data pin of one is connected to the Receive Data

pin of the other and vice versa. The Z8002 is used as a

host CPU for loading the modules’ memories with software

routines.

The Z8000 CPU can address either of the two bytes

contained in 16-bit words. The CPU uses an even address

(16 bits) to access the most-significant byte of a word and

an odd address for the least-significant byte of a word.

6-80

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

Address/

Data

Buffer

Serial

Output

Buffers

RS-232C

Serial

Channels

(2)

Address

Data

Wire Wrap Area

Reset

Switch

9

Reset

NMI

Switch

Non-maskable

Interrupt

Segment

Address

Buffer

Z80A PIO's

(2)

Segment

Address

Z80A CTC

SIO2

Status

Decoder

Status

ADDRESS/DATA BUS

I/O

Control

Out

I/O BUS

Eprom

Control

Inputs

EPROM CONTROL BUS

RAM CONTROL BUS

Buffer

Memory

(8k Words Max)

Dynamic

Ram Memory

(32k Words Max)

Ram

Control

Clock

External

Clock

In/Out

Clock

Generator

Figure 2. Block Diagram of Z8000 DM

TxD

RxD

RTxC

TRxC

TxD

TRxC

RTxC

RxD

Z8002

Z-SCC

Z8002

Z-SCC

Local

Remote

Figure 3. Block Diagram of Two Z8000 Development Modules

6-81

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

SYSTEM INTERFACE (Continued)

Figure 4. Z8002 with SCC

6-82

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

When the Z8002 CPU uses the lower half of the

Address/Data bus (AD0-AD7 the least significant byte) for

byte read and write transactions during I/O operations,

these transactions are performed between the CPU and

I/O ports located at odd I/O addresses. Since the Z-SCC is

attached to the CPU on the lower half of the A/D bus, its

registers must appear to the CPU at odd I/O addresses. To

achieve this, the Z-SCC can be programmed to select its

internal registers using lines AD5-AD1. This is done either

automatically with the Force Hardware Reset command in

WR9 or by sending a Select Shift Left Mode command to

WR0B in channel B of the Z-SCC. For this application, the

Z-SCC registers are located at I/O port address ‘FExx’.

The Chip Select signal (/CS0) is derived by decoding I/O

address ‘FE’ hex from lines AD15-AD8 of the controller.

The Read/Write registers are automatically selected by the

Z-SCC when internally decoding lines AD5-AD1 in Shift

Left mode. To select the Read/Write registers

automatically, the Z-SCC decodes lines AD5-AD1 in Shift

Left mode. The register map for the Z-SCC is depicted in

Table 1.

9

INITIALIZATION

The Z-SCC can be initialized for use in different modes by

setting various bits in its Write registers. First, a hardware

reset must be performed by setting bits 7 and 6 of WR9 to

one; the rest of the bits are disabled by writing a logic zero.

Table 1. Register Map

Address

(hex)

Write Register

Read Register

FE01

FE03

FE05

FE07

WR0B

WR1B

WR2

RR0B

RR1B

RR2B

RR3B

Bisync mode is established by selecting a 16-bit sync

character, Sync Mode Enable, and a Xl clock in WR4. A

data rate of 9600 baud, NRZ encoding, and a data

character length of eight bits are among the other options

that are selected in this example (Table 2).

WR3B

FE09

FE0B

FE0D

FE0F

FE11

WR4B

WR5B

WR6B

WR7B

B DATA

Note that WR9 is accessed twice, first to perform a

hardware reset and again at the end of the initialization

sequence to enable the interrupts. The programming

sequence depicted in Table 2 establishes the necessary

parameters for the receiver and the transmitter so that,

when enabled, they are ready to perform communication

tasks. To avoid internal race and false interrupt conditions,

it is important to initialize the registers in the sequence

depicted in this application note.

B DATA

RR10B

FE13

FE15

FE17

FE19

FE1B

WR9

WR10B

WR11B

WR12B

WR13B

RR12B

RR13B

FE1D

FE1F

FE21

FE23

FE25

WR14B

WR15B

WR0A

WR1A

WR2

RR15B

RR0A

RR1A

RR2A

FE27

FE29

FE2B

FE2D

FE2F

WR3A

WR4A

WR5A

WR6A

WR7A

RR3A

FE31

FE33

FE35

FE37

A DATA

WR9

WR10A

WR11A

A DATA

RR10A

FE39

FE3B

FE3D

FE3F

WR12A

WR13A

WR14A

WR15A

RR12A

RR13A

RR15A

6-83

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

INITIALIZATION (Continued)

The Z8002 CPU must be operated in System mode in

order to execute privileged I/O instructions, so the Flag

Control Word (FCW) should be loaded with

System/Normal (S//N), and the Vectored Interrupt Enable

(VIE) bits set. The Program Status Area Pointer (PSAP) is

loaded with address %4400 using the Load Control

instruction (LDCTL). If the Z8000 Development Module is

intended to be used, the PSAP need not be loaded by the

programmer as the development modules monitor loads it

automatically after the NMI button is pressed.

Since VIS and Status Low are selected in WR9, the

vectors listed in Table 3 will be returned during the

Interrupt Acknowledge cycle. Of the four interrupts listed,

only two, Ch A Receive Character Available and Ch A

Special Receive Condition, are used in the example given

here.

Table 3. Interrupt Vectors

PS

Vector

(hex)

Address*

(hex)

Interrupt

Table 2. Programming Sequence for Initialization

Value

28

2A

2C

2E

446E

4472

4476

447A

Ch A Transmit Buffer Empty

Ch A External Status Change

Ch A Receive Char. Available

Ch A Special Receive Condition

Register

(hex)

Effect

WR9

WR4

C0

10

Hardware reset

x1 clock, 16-bit sync,

sync mode enable

* “PS Address” refers to the location in the Program Status

Area where the service routine address is stored for that

particular interrupt, assuming that PSAP has been set to

4400 hex.

WR10

WR6

0

AB

NRZ, CRC preset to zero

Any sync character “AB”

WR7

WR2

WR11

CD

20

16

Any sync character “CD”

Interrupt vector “20”

Tx clock from BRG output,

TRxC pin = BRG out

Lower byte of time constant =

“CE” for 9600 baud

WR12

CE

WR13

WR14

0

Upper byte = 0

03

BRG source bit = 1 for PCLK

as input, BRG enable

WR15

WR5

00

64

External interrupt disable

Tx 8 bits/character, CRC-16

WR3

WR1

WR9

C1

08

09

Rx8 bits/character, Rx enable

(Automatic Hunt mode)

RxInt on 1st char & sp. cond.,

ext. int. disable)

MIE, VIS, Status Low

6-84

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

TRANSMIT OPERATION

To transmit a block of data, the main program calls up the

transmit data routine. With this routine, each message

block to be transmitted is stored in memory, beginning with

location ‘TBUF’. The number of characters contained in

each block is determined by the value assigned to the

‘COUNT’ parameter in the main module.

the characters sent to the Z-SCC in the CRC calculation,

until the Transmit CRC bit is disabled. CRC generation can

be disabled for a particular character by resetting the

TxCRC bit within the transmit routine. In this application,

however, the Transmit CRC bit is not disabled, so that all

characters sent to the Z-SCC are included in the CRC

calculation.

9

To prepare for transmission, the routine enables the

transmitter and selects the Wait On Transmit function; it

then enables the wait function. The Wait On Transmit

function indicates to the CPU whether or not the Z-SCC is

ready to accept data from the CPU. If the CPU attempts to

send data to the Z-SCC when the transmit buffer is full, the

Z-SCC asserts its Wait line and keeps it Low until the

buffer is empty. In response, the CPU extends its I/O

cycles until the Wait line goes inactive, indicating that the

Z-SCC is ready to receive data.

The Z-SCC’s transmit underrun/EOM latch must be reset

sometime after the first character is transmitted by writing

a Reset Tx Underrun/EOM command to WR0. When this

latch is reset, the Z-SCC automatically appends the CRC

characters to the end of the message in the case of an

underrun condition.

Finally, a five-character delay is introduced at the end of

the transmission, which allows the Z-SCC sufficient time to

transmit the last data byte, two CRC characters, and two

sync characters before disabling the transmitter.

The CRC generator is reset and the Transmit CRC bit is

enabled before the first character is sent, thus including all

RECEIVE OPERATION

Once the Z-SCC is initialized, it can be prepared to receive

data. First, the receiver is enabled, placing the Z-SCC in

Hunt mode and thus setting the Sync/Hunt bit in status

register RR0 to 1. In Hunt mode, the receiver is idle except

that it searches the incoming data stream for a sync

character match. When a match is discovered between the

incoming data stream and the sync characters stored in

WR6 and WR7, the receiver exits the Hunt mode, resetting

the Sync/Hunt bit in status register RR0 and establishing

the Receive Interrupt On First Character mode. Upon

detection of the receive interrupt, the CPU generates an

Interrupt Acknowledge cycle. The Z-SCC sends to the

CPU vector %2C, which points to the location in the

Program Status Area from which the receive interrupt

service routine is accessed.

Transmission character (%04) is received, the two CRC

bytes are read. The result of the CRC check becomes valid

two characters later, at which time, RR1 is read and the

CRC error bit is checked. If the bit is zero, the message

received can be assumed correct; if the bit is 1, an error in

the transmission is indicated.

Before leaving the interrupt service routine, Reset Highest

IUS (Interrupt Under Service), Enable Interrupt on Next

Receive Character, and Enter Hunt Mode commands are

issued to the Z-SCC.

If a receive overrun error is made, a special condition

interrupt occurs. The Z-SCC presents the vector %2E to

the CPU, and the service routine located at address

%447A is executed. The Special Receive Condition

register RR1 is read to determine which error occurred.

Appropriate action to correct the error should be taken by

the user at this point. Error Reset and Reset Highest IUS

commands are given to the Z-SCC before returning to the

main program so that the other lower priority interrupts can

occur.

The receive data routine is called from within the receive

interrupt service routine. While expecting a block of data,

the Wait On Receive function is enabled. Receive data

buffer RR8 is read, and the characters are stored in

memory locations starting at RBUF. The Start of Text

(%02) character is discarded. After the End of

SOFTWARE

Software routines are presented in the following pages.

These routines can be modified to include various versions of

Bisync protocol, such as Transparent and Nontransparent

modes. Encoding methods other than NRZ (e.g., NRZI, FM0,

FM1) can also be used by modifying WR10.

6-85

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

APPENDIX

SOFTWARE ROUTINES

plzasm 1.3

LOC OBJ CODE STMT SOURCE STATEMENT

1

BISYNC MODULE

$TTY

$LISTON

CONSTANT

WR0A

:=

%FE21

%5400

%4400

12

!BASE ADDRESS FOR WR0 CHANNEL A!

!BASE ADDRESS FOR RR0 CHANNEL A!

!BUFFER AREA FOR RECEIVE CHARACTER!

!START ADDRESS FOR PROGRAM STAT AREAS!

!NO. OF CHAR FOR TRANSMIT ROUTINE!

RR0A

RBUF

PSAREA

COUNT

0000

GLOBAL MAIN PROCEDURE

ENTRY

0000

0002

0004

0006

0008

7601

4400

7D1D

2100

5000

LDA

R1, PSAREA

LDCTL

LD

PSAPOFF,R1

RO,#%5000

!LOAD PSAP

000A 3310

000C 001C

LD

Rl(#%lC),R0

!FCW VALUE(%5000) AT %441C FOR VECTORED!

!INTERRUPTS!

000E 7600

LDA

LD

R0,REC

0010

0012

0014

00F4'

3310

0076

Rl(#%76),R0

!EXT. STATUS SERVICE ADDR. AT %4476 IN!

!PSA!

0016

0018

00IA

7600

011E'

3310

LDA

LD

R0, SPCOND

R1(#%7A),R0 !SP.COND.SERVICE ADDR AT %447A IN PSA!

001C 007A

001E 5F00

CALL

INIT

0020

0022

0024

0026

0028

0029

0034'

5F00

00A6'

E8FF

02

TRANSMIT

$

JR

TBUF:

BVAL

END

%02

‘1'

!START OF TEXT!

31

!BVAL MEANS BYTE VALUE. MESSAGE CHAR.!

002A 32

002B 33

002C 34

002D 35

002E 36

002F 37

‘2'

‘3'

‘4'

‘5'

‘6'

‘7'

0030

0031

0032

0033

0034

38

39

30

31

‘8'

‘9'

‘0'

‘1'

MAIN

6-86

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

INITIALIZATION ROUTINE FOR Z-SCC

0034

GLOBAL

ENTRY

INIT

LD

PROCEDURE

9

0634

0036

0038

003A

003C

003E

0040

0042

0044

0046

0048

004A

004C

004E

004F

0050

0051

0052

0053

0054

0055

0056

0057

0058

0059

005A

005B

005C

005D

005E

005F

0060

0061

0062

0063

0064

0065

0066

0067

0068

0069

2100

000F

7602

004E'

2101

FE21

0029

A920

3A22

0018

8D04

EEF8

9E08

12

R0, #15

!NO.OF PORTS TO WRITE TO!

LDA

LD

R2, SCCTAB !ADDRESS OF DATA FOR PORTS!

R1, #WR0A

ALOOP:

ADDB

INC

RL1, @R2

R2

OUTIB @Rl, @R2,R0 !POINT TO WR0A,WR1A ETC THRO LOOP!

TEST

JR

R0

!END OF LOOP?!

NZ, ALOOP

!NO, KEEP LOOPING!

RET

SCCTAB:

BVAL

BVAL.

BVAL

2*9

CO

08

%C0

2*4

!WR9=HARDWARE RESET!

10

%10

2*10

0

!WR4=X1 CLK, 16 BIT SYNC MODE!

!WRIO=CRC PRESET ZERO, NRZ,16 BIT SYNC!

!WR6=ANY SYNC CHAR %AB!

!WR7=ANY SYNC CHARR %CD!

!WR2=NT VECTOR %20!

14

00

0C

2*6

AB

%AB

2*7

0E

CD

04

%CD

2*2

20

%20

2*11

%16

2*12

%CE

2*13

0

16

!WR11=TxCLOCK & TRxC OUT=BRG OUT!

!WR12= LOWER TC=%CE!

18

CE

IA

00

!WR13= UPPER TC=01

1C

2*14

%03

2*15

%00

2*5

03

!WRI4=BRG ON, ITS SRC=PCLK!

!WRI5=NO EXT INT EN.!

1E

00

0A

64

%64

2*3

!WR5= TX 8 BITS/CHAR, CRC-16!

IWR3=RX 8 BITS/CHAR, REC ENABLE!

06

Cl

&CI

2*1

02

08

%C1

!WR1=RxINT ON 1ST OR SP COND!

!EXT INT DISABLE!

006A

006B

006C

12

09

BVAL

2*9

%09

!WR9=MIE, VIS, STATUS LOW!

END INIT

6-87

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

RECEIVE ROUTINE

RECEIVE A BLOCK OF MESSAGE

THE LAST CHARACTER SHOULD BE EOT (%04)

GLOBAL

006C

ENTRY

RECEIVE

PROCEDURE

006C

0070

0072

0074

0076

0078

007A

007C

007E

0080

0082

0084

0086

0088

008A

008C

008E

0090

0092

0094

0096

0098

009A

009C

C828

3A86

FE23

6000

00AB

3A86

FE23

2101

FE31

3Cl8

LDB

RL0,#428

!WAIT ON RECV.!

OUTB

WR0A+2,RL0

LDB

OUTB

LD

RL0,%A8

WR0A+2,RL0

Rl,#RR0A+16

!ENABLE WAIT 1ST CHAR,SP.COND. INT!

INB

RL0,@R1

!READ STX CHARACTER!

!Rx CRC ENABLE!

C8C9

3AB6

FE27

2103

5400

3C18

2E38

AB30

0A08

0404

EEFA

3C18

3A84

FE23

LDB

OUTB

RL0,#%C9

WR0A+6,RL0

LD

R3,#RBUF

READ:

INB

RL0,@R1

@R3,RL0

R3,#l

!READ MESSAGE!

LDB

DEC

CPB

!STORE CHARACTER IN RBUF!

RL0,#%04

!IS IT END OF TRANSMISSION ?!

JR

NZ,READ

RL0,@R1

RL0,RR0A+2

INB

!READ PAD1!

!READ PAD2!

!READ CRC STATUS!

! PROCESS CRC ERROR IF ANY, AND GIVE ERROR RESET COMMAND IN WR0A!

009E

00A0

00A2

00A4

00A6

C800

3A86

FE27

9E08

LDB

RL0,#0

OUTB

WR0A+6,RL0

!DISABLE RECEIVER!

RET

END RECEIVE

6-88

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

TRANSMIT ROUTINE

SEND A BLOCK OF DATA CHARACTERS

THE BLOCK STARTS AT LOCATION TBUP

9

GLOBAL

OA6

ENTRY

TRANSMIT PROCEDURE

00A6

00AB

00AA

00AC

00AE

00B0

00B2

00B4

00B6

00B8

00BA

00BC

00BE

00C0

00C2

00C4

00C6

00C8

00CA

00CC

00CE

00D0

00D2

00D4

00D6

00D8

00DA

00DC

00DE

00E0

00E2

00E4

00E6

00E8

00EA

00EC

00EE

00F0

00F2

00F4

2102

0028'

C86C

3AB6

FE2B

C800

3A86

FE23

C888

3AB6

FE23

C880

3A86

FE21

2101

FE31

C86D

3A86

FE2B

2100

0001

3A22

0010

C8C0

3AB6

FE21

2100

000B

3A22

0010

C804

3EI8

LD

R2, #TBUF

!PTR TO START OF BUFFER!

LDB

RL0, #%6C

OUTB

WR0A+10, RL0

!ENABLE TRANSMITTER!

!WAIT ON TRANSMIT!

LDB

RL0, #%00

OUTB

WR0A+2 , RL0

LDB

RL0, #%88

OUTB

WR0A+2, RL0

!WAIT ENABLE, INT ON 1ST & SP COND!

LDB

RL0, #%80

WR0A, RL0

OUTB

!RESET TxCRC GENERATOR!

!WR8A SELECTED!

LD

R1, #WR0A+16

LDB

RL0, #%6D

OUTB

WR0A+10, RL0

!Tx CRC ENABLE!

LD

R0, #1

OTIRB

@Rl, @R2,R0

!SEND START OF TEXT!

LDB

RL0, #%C0

WR0A, RL0

OUTB

!RESET TxUND/EOM LATCH!

LD

R0, #COUNT-1

@Rl, @R2, R0

OTIRB

!SEND MESSAGE!

LDB

OUTB

LD

RL0, #%04

@R1, RL0

R0, #1670

!SEND END OF TRANSMISSION CHARACTER!

!CREATE DELAY BEFORE DISABLING!

2100

0686

F081

C800

3AB6

FE2B

9E0B

DEL:

DJNZ

LDB

R0, DEL

RL0, #0

OUTB

WR0A+10, RL0

!DISABLE TRANSMITTER!

RET

END TRANSMIT

6-89

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

RECEIVE INT. SERVICE ROUTINE

GLOBAL

00F4

ENTRY

REC

PROCEDURE

00F4

00F6

00F8

00FA

00FC

00FE

0100

0102

0104

0106

0108

010A

010C

010E

0110

0112

0114

0116

0118

011A

011C

0IIE

93F0

3A84

FE21

A684

EE02

5F00

006C’

C808

3A86

FE23

C8D1

3A86

FE27

C820

3A86

FE21

C838

3A86

FE21

97F0

7B00

PUSH

INB

@RI5, R0

RL0, RR0A

!READ STATUS FROM RR0A!

BITB

JR

RL0, #4

!TEST IF SYNC HUNT RESET!

!YES CALL RECEIVE ROUTINE!

NZ, RESET

RECEIVE

CALL

RESET:

LDB

RL0, #%08

OUTB

WR0A+2, RL0

!WAIT DISABLE!

LDB

RL0, #%D1

OUTB

WR0A+6, RL0

!ENTER HUNT MODE!

!ENABLE INT ON NEXT CHAR!

!RESET HIGHEST IUS!

LDB

RL0, #%20

WR0A, RL0

OUTB

LDB

RL0, #%38

WR0A, RL0

OUTB

POP

IRET

R0, @RI5

END REC

6-90

UM010901-0601

Application Note

SCC in Binary Synchronous Communications

SPECIAL CONDITION INTERRUPT SERVICE ROUTINE

GLOBAL

ENTRY

9

011E

SPCOND

PROCEDURE

011E

0120

0122

93F0

3A84

FE23

PUSH

INB

@Rl5, R0

RL0, RR0A+2 !READ ERRORS!

!PROCESS ERRORS!

0124

0126

0128

012A

012C

012E

0130

0132

0134

0136

0138

013A

013C

013E

C830

3A8B6

FE21

C808

3A86

FE23

C0D1

3A86

FE27

C838

3A86

FE21

97F0

7B00

LDB

RL0, #%30

OUTB

WR0A, RL0

!ERROR RESET!

LDB

RL0, #%08

OUTB

WR0A+2, RL0 !WAIT DISABLE, RxINT ON 1ST OR SP COND.!

LDB

RL0, #%D1

OUTB

WR0A+6, RL0 !HUNT MODE, REC. ENABLE!

LDB

RL0, #%38

OUTB

WR0A, RL0

!RESET HIGHEST IUS!

POP

IRET

R0, @Rl5

0140

END SPCOND

END BISYNC

o errors

Assembly complete

6-91

UM010901-0601

9-92

UM010901-0601

APPLICATION NOTE

1

™

SERIAL COMMUNICATION CONTROLLER (SCC ):

SDLC MODE OF OPERATION

10

nderstanding the transactions which occur within a Serial Communication Controller

operating in the SDLC mode simplifies working in this complex area.

U

INTRODUCTION

Zilog’s SCC (Serial Communication Controller) is a

popular USART (Universal Synchronous/Asynchronous

Receiver/Transmitter) device, used for a wide range of

applications. For instance, Macintosh systems use the

SCC as a standard communication controller device.

There are several different types of devices in the SCC

family. The family consists of the Z8530 NMOS SCC, the

Z85C30 CMOS SCC, the Z85230 ESCC (Enhanced

SCC), Z85233 EMSCC (Mono Enhanced SCC), and

Superintegration devices such as the Z181 ZIO™ and

Z182 ZIP™.

■ Receiving Back-to-back Frame under DMA control

■ SDLC Loop mode

Each section explains the transmit/receive process for

packets with the following characteristics:

■ Initial state is mark idle

■ Address field has 81H

■ Control field has 42H

Since the SCC may be used in many different ways, it may

not be easy to understand all the transactions involved

between the CPU and the SCC. In particular, the SDLC

mode of operation is highly complicated, and many

transactions are involved to make it work properly. This

application note describes the sequence of events which

occurs in the SDLC mode of operation.

■ Two bytes of I-field, 42H and 0FFH

■ After the closing flag, mark idling

Note:

This application note describes the SCC, but not the

ESCC. The ESCC, since it incorporates enhancements

like deeper FIFOs and SDLC mode supporting logic,

handles the packets much more simply than the SCC.

Refer to the section on CMOS SCC and ESCC of this

appnote for more general information on the ESCC.

The following sequences of events are covered:

■ SDLC Transmission

■ SDLC receive

–

With Receive Interrupts on all received characters

or Special Conditions

With Receive Interrupts on First Character or

Special Condition

With Receive Interrupts on Special Conditions

only

6-93

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

SDLC TRANSMIT

Figure 1 shows the time chart for the transmitting SDLC

packet under interrupt control. When transmit is engaged,

data is shifted out of the transmitter on the falling edge of

the transmit clock. Transitions on the diagram are shown

coincident with TxCLK fall — in actual practice, there are

some associated delay times (which are specified in the

data sheet).

Figure 1. Typical SDLC Trsnsmission Sequence

6-94

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

Notes on Figure 1:

4. Transmit Buffer Empty Interrupt for data 42H. Data

0FFH is written to the Transmit Buffer at this point.

1. The SCC has two possible idle states, Mark idle

(contiguous logic 1) or Flag idle (repeating flag pattern

7EH). In this figure, the SCC has to be switched to flag

idle in order to send the opening flag of the frame.

Care must be taken not to put the first data byte (in this

case, address 81H) into the Transmit Buffer too soon

after the switchover from Mark idle to Flag idle has

been made; otherwise, the data may be loaded into

the Transmit Shift Register before the flag is loaded.

To ensure that this cannot happen, a delay must be

executed before the first data byte is put into the

buffer. The delay time is dependent on the data rate

and a safe minimum duration is 8 bit-times.

5. Transmit Buffer Empty Interrupt for data 0FFH. Data

42H is written to the Transmit Buffer at this point.

1

6. The time between interrupts depends on the data

character length and the number of zero insertions in

the character. For 8 bits/character it can vary between

8 and 10 bit-times. The particular instance shown

corresponds to the single zero insertion when the byte

0FFH is transmitted.

7. Transmit Buffer Empty Interrupt for data 42H. Since

this is the last byte to be transmitted, the Reset

Transmit Interrupt Pending command is issued

instead of writing another byte to the Transmit Buffer.

2. Transmit Buffer Empty Interrupt for 81H. At this point

the data has just been transferred to the Transmit Shift

Register and data 42H is written to the Transmit

Buffer.

8. Transmitter Underrun/EOM Interrupt. This occurs

when both the Transmit Shift Register and the

Transmit Buffer are empty. It is an External/Status

interrupt. The data sent when this occurs is

summarized in the table below:

3. The time between the first data byte being transferred

to the Shift Register and the first bit appearing at the

TxD pin is always six bit-times.

Abort/Flag on

Underrun bit

Tx Underrun/EOM Latch

State when Underrun occurs

Data

Sent

0

1

0

1

Reset

Set

CRC and Flag

Abort and Flag

Flags

Set

Flags

9. The transmitted CRC is 16 bits long provided that

there are no zero insertions. In theory it could be as

long as 19 bits.

frame is to be transmitted, the first character of the

next frame can be loaded. The two frames will then be

separated by a single flag (Back-to-back frame).

10. The last interrupt generated occurs after the CRC is

shifted out of the transmitter and a flag is loaded to be

sent. It is a Transmit Buffer Empty Interrupt. If another

11. If the SCC is set up for mark on idle and a new

character is not loaded when the last interrupt occurs,

only a single flag is sent.

6-95

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

SDLC RECEIVE

There are several different ways to receive a SDLC packet

on the SCC; by polling, by Interrupts and by DMA. The

SCC has the following four Receive Interrupt Modes:

Status FIFO can give byte count and error status without

interrupting data transfer operations.

Each of the four cases is covered in this application note

except Receive Interrupt disabled. For polling, the basic

operation is identical to that used for “interrupt on all

characters or Special Condition” mode. Instead of waiting

for an interrupt, polling Reads Registers to determine if

service is needed or not.

■ Disabled. This should be used in the Polling mode.

■ Interrupts on all received characters or Special

Conditions. This mode should be used for normal

interrupt-driven operation.

■ Interrupts on First Character or Special Condition. This

mode is intended for received data transfer by the DMA,

and enables the DMA when the interrupt is received by

the First Character of the packet.

On the SCC, data is sampled by the receiver on the rising

edge of the receive clock. Set-up and hold times for RxD

with respect to RxC are specified in the product

specifications.

■ Interrupt on Special Condition only. This mode allows

the DMA to free-run and keep transferring data to the

buffer. This is an ideal mode for the CMOS SCC as well

as the ESCC with Status FIFO enabled, because the

In general, receiver status changes are triggered by RxC.

In the following Figures, they are shown as being

coincident with this edge — in actual practice, there are

some associated delay times (which are specified in the

data sheet).

RECEIVE INTERRUPTS ON ALL RECEIVE CHARACTERS OR SPECIAL CONDITIONS

SCC is placed in this mode by programming Bit D4-3 of

WR1 to 10. Once programmed in this mode, the SCC

generates interrupts whenever character(s) are in the

receive buffer or when Special Conditions occur. This

mode is the most common operational mode.

6. Receive Character Available Interrupt for data 42H.

7. Receive Character Available Interrupt for the first CRC

byte. The SCC treats the CRC as data, since the SCC

does not yet distinguish a difference between CRC

and data!

Notes on Figure 2:

8. The closing flag is recognized two bit-times before the

second CRC byte is completely assembled in the

Receive Shift Register. As soon as it is recognized, a

Special Condition interrupt is generated. The EOF bit

is set at this point and the CRC error bit can be

checked. The six least significant bits of the second

CRC byte are present at the top of the first CRC byte.

The status information must be read before the

second CRC byte is read from the buffer. The CRC

bytes should be discarded. The CRC checker is

automatically reset for the next frame.

1. The receiver is usually in hunt mode when waiting for

a frame. When the opening flag is received, an

External/Status Interrupt is generated, indicating the

change from hunt mode to sync mode.

2. The /SYNC output follows the state of the sync register

comparison output. The comparison is done on a bit

by bit basis, so the /SYNC pin is only active for one bit-

time. /SYNC goes active one bit-time after the last bit

of the sync character is sampled at the RxD pin.

3. A Receive Character Available Interrupt is generated

11 bit-times 8 bits for the shifter and a 3-bit delay) after

the last bit of the character is sampled at the RxD pin.

The status bits corresponding to that character must

be read before the data character is read from the

Receive Buffer. This interrupt is for data 81H.

9. External/Status interrupt for the Sync/Hunt change.

This occurs when the SCC recognizes an Abort

(Marking line) and forces the receiver into hunt mode.

The SCC can be programmed so that the Abort itself

generates an interrupt if required. If flag idle was set,

this interrupt will not occur.

4. Receive Character Available Interrupt for data 42H.

5. Receive Character Available Interrupt for data 0FFH.

6-96

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

1

Figure 2. Typical SDLC Receive Sequence with Receive Interrupts on all Received

Characters or Special Condition

6-97

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

RECEIVE INTERRUPTS ON FIRST CHARACTER OR SPECIAL CONDITIONS

The sequence of events in this mode is similar to that in

“Receive Interrupts on all received characters and Special

Conditions”, except that it generates Receive Character

Interrupt on the first received character only, and

subsequent data is read by the DMA.

generates interrupts when it receives the First Character of

the packet or a Special Condition occurs. This mode is for

operation with the DMA. On the interrupt for the first

received character, DMA is enabled. On Special

Conditions (either End-of-Message, overrun, or Parity

error, — parity on the SDLC is not normal, however), the

service routine stops the DMA and starts over again.

The SCC is placed in this mode by programming Bit D4-3

of WR1 to 01. Once programmed in this mode, the SCC

Figure 3. Typical SDLC Receive Sequence with Receive Interrupts on First Character or Special Condition

6-98

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

Notes on Figure 3:

10. This interrupt is EOF (End of Frame), a Special

1. The receiver is usually in hunt mode when waiting for

a frame. When the opening flag is received, an

External/Status Interrupt is generated, indicating the

change from hunt mode to sync mode.

Condition interrupt. This will not occur until the DMA

has read the 2nd CRC byte from the Receive Buffer.

When it occurs, the Receive Buffer is locked and no

more DMA requests can be generated until the

Receive Buffer is unlocked by issuing the Error Reset

command. Before issuing this command, all of the

status bits required (e.g., the CRC error status) must

be read, and the last two bytes read by the DMA

discarded. The enable interrupt on next Receive

Character command must be sent to the SCC so that

the next character (i.e., the First Character of the next

frame) will produce an interrupt. If this is not done, the

character will generate a DMA request, not an

interrupt.

1

2. The /SYNC output follows the state of the sync register

comparison output. The comparison is done on a bit

by bit basis, so the /SYNC pin is only active for one bit-

time. /SYNC goes active one bit-time after the last bit

of the sync character is sampled at the RxD pin.

3. A Receive Character Available Interrupt is generated

11 bit-times after the last bit of the character is

sampled at the RxD pin. In this mode, enable the DMA

on this interrupt. This interrupt is for data 81H.

Should a Special Condition occur within the data

stream (i.e., for a condition other than EOF) the /INT

pin will not go active until the character with the

Special Condition has been read by the DMA.

4. If SCC’s DMA request function has been enabled,

/REQ becomes active here.

5. DMA request for data 42H.

6. DMA request for data 0FFH.

7. DMA request for data 42H.

11. DMA request for 2nd CRC bytes. This occurs when

the EOF interrupt service routine has not disabled the

DMA function of the SCC, and did not read the data

after unlocking the buffer by issuing an Error Reset

command.

8. DMA request for the first CRC byte. The SCC treats

the CRC as data, since the SCC does not yet

distinguish a difference between CRC and data!

12. External/Status Interrupt for the Sync/Hunt change.

This occurs when the SCC recognizes an Abort

(Marking line) and forces the receiver into hunt mode.

The SCC can be programmed so that the Abort itself

generates an interrupt if required. If flag idle was set,

this interrupt would not occur.

9. DMA request for the second CRC byte. The closing

flag is recognized two bit-times before the second

CRC byte is completely assembled in the Receive

Shift Register. As soon as it is transferred to the

Receive Buffer, it generates a DMA request.

6-99

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

RECEIVE INTERRUPTS ON SPECIAL CONDITIONS ONLY

The sequence of event in this mode is similar to that for

“Receive Interrupts on first received character or Special

Condition,” except it will not generate Receive Character

Available interrupt at all. This mode is designed for

operations where the DMA is pre-programmed, or the

application does not have enough time to set up DMA

transfer on First Character interrupt.

DMA to transfer several packets. The SDLC Frame Status

Buffer holds information which tells you how many bytes

were in the received packet and reports whether or not

error conditions (overrun/CRC error/parity error) have

occurred.

The sequence of events in this mode is identical to the

“Receive Interrupts on First Character or Special

Condition” mode (Figure 3); Note 3, however, does not

apply, and Note 4 should read as follows for this case:

The SCC is placed in this mode by programming Bit D4-3

of WR1 to 11. Once programmed in this mode, the SCC

generates interrupts when Special Conditions occur. On

Note 4 in Receive Interrupts on Special Condition only

mode:

DMA request for data 81H. The DMA function of the SCC

should be enabled by this time frame.

Special

Condition

(either

End-Of-Message

or

overrun/Parity error, if enabled), corrective action can be

taken for that packet.

The SDLC Frame Status Buffer (not available on the

NMOS version) is very useful in this mode. First of all, set

RECEIVING BACK TO BACK FRAME IN RECEIVE INTERRUPTS ON SPECIAL CONDITION

ONLY MODE

“Back to Back” frame means there are two frames

separated with only one flag — the closing flag of the

previous packet also acts as the opening flag of the

following packet. Receiving such packets is identical to

receiving a single packet, except that the sequence of

events happens in a short time around the shared flag.

Receive Buffer is unlocked by issuing the Error Reset

command. Before this command is issued, all of the

status bits required (e.g., the CRC error status) must

be read, and the last two bytes read by the DMA

discarded. The Enable Interrupt on Next Receive

Character command must be sent to the SCC so that

the next character (i.e., the First Character of the next

frame) will produce an interrupt. If this is not done, the

character will generate a DMA request, not an

interrupt.

Assuming SCC is running under Receive Interrupts on

Special Condition only mode (under DMA Control), a

typical sequence of events is shown in Figure 4. It is

identical to that used for “Receive Interrupts on Special

Condition Only” mode, with the addition of another

following packet.

On unlocking the Receive Buffer after the EOF

interrupt, no initialization is required with respect to the

receiver. All characters have been removed by the

DMA and the receiver is ready for the next frame.

While the Buffer is locked the SCC can receive 2 7/8

characters (8 bits/character) before there is a danger

of the receiver overrunning. The only way that this can

be specified is by referencing it to the falling edge of

the request for the last CRC byte. This time is a worst

case minimum of 33 bit-times (possibly more if there

are any characters with inserted zeros). As soon as

the Buffer is unlocked an additional 8 (minimum) bit-

times become available because the top byte of the

Buffer is freed up.

Notes on Figure 4:

1. DMA request data before 0FFH.

2. DMA request for data 0FFH.

3. DMA request for data 42H.

4. DMA request for the first CRC byte. The SCC treats

the CRC as data, since the SCC does not yet

distinguish a difference between CRC and data!

5. DMA request for the second CRC byte. The closing

flag is recognized two bit-times before the second

CRC byte is completely assembled in the Receive

Shift Register. As soon as it is transferred to the

Receive Buffer, it generates a DMA request.

7. DMA request for second CRC byte. This occurs when

the EOF interrupt service routine has not disabled the

DMA function of the SCC, and fails to read the data

after unlocking the FIFO by issuing Error Reset

command.

6. This interrupt is EOF (End of Frame), a Special

Condition Interrupt. This will not occur until the DMA

has read the 2nd CRC byte from the Receive Buffer.

When it occurs the Receive Buffer is locked and no

more DMA requests can be generated until the

8. DMA request for data 01H.

9. MA request for data 03H.

6-100

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

1

Figure 4. Receiving “Back to Back” frame with Receive Interrupts on Special Condition

Only Mode (DMA Controlled)

6-101

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

THE SDLC LOOP MODE

The SDLC Loop mode is one of the protocols used in the

ring configuration network topology. The typical network

configuration is shown in Figure 5. As shown, there is one

Master (or primary) station and several slave (or

secondary) stations. This figure does not have a clock

connection, but each station’s transmit clock must be

synchronized to the master SCC. This can be done by

feeding the clock using a separate clock line, or by using

Phase Locked Loop (PLL) to recover the clock.

Master SCC

Tx

Rx

Tx

Rx

Tx

Rx

Tx

Slave SCC #1

Slave SCC #n

Slave SCC #2

Figure 5. SDLC Loop Mode Conﬁguration

This mode is similar to the normal SDLC mode, other than

that secondary stations are not allowed to freely send out

packets. When a secondary station wants to send a

packet, it needs to wait for a special pattern to be received.

The pattern is called EOP (End Of Poll), and consists of a

0 followed by seven 1s on the transmission line (as data, it

is 11111110). This pattern resembles the SDLC Flag

pattern (7EH; 0111110), except the last bit has been

changed to a 1 thus turning this pattern into a flag.

When it has a message to send out, it waits for an EOP.

When it detects EOP in this phase, it changes the last bit

of the EOP to zero, making it a Flag, then begins to send

its own message. From this point on, normal SDLC

transmission modes apply. Packets conclude with Mark

idle, identifying it as an EOP pattern. The secondary

station then reverts back to one bit delay mode.

Figure 6 illustrates this mode’s sequence of events. To

simplify the example, this figure assumes there is one

Master station and one Slave station. If there are more

Slave stations, there will be additional one bit time delay

per station after the network has initialized for loop mode

of operation.

Upon network initialization, secondary station TxD and

RxD connections use gate propagation delay. On the first

EOP, a secondary station inserts one bit -time delay

between RxD and TxD, and relays RxD input to TxD.

6-102

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

1

➘

Figure 6. SDLC Loop Mode

6-103

UM010901-0601

Application Note

™

Serial Communication Controller (SCC ): SDLC Mode of Operation

THE SDLC LOOP MODE (Continued)

Notes on Figure 6:

5. When the Slave wants to transmit it must first receive

1. The master SCC sends EOP by switching from flag on

idle to mark on idle

an EOP and have GAOP set.

6. On receiving an EOP, the Slave interrupts with

Break/Abort clear. The EOP is converted to a flag, the

loop sending bit is set, and the transmitter will send

flags until data is written into the Transmit Buffer.

2. At initialization, all Slave stations were set up for SDLC

loop mode At this point, the Slave station connects its

RxD pin to TxD pin with gate propagation delay, and

starts to monitor Rx data for the EOP sequence.

7. Note that the flags overlap.

3. On receiving the EOP, the slave generates an

External/Status Interrupt with Break/Abort bit set. A

one bit time delay is inserted between RxD and TxD.

(The GAOP,Go active on Poll, bit should be reset at

this point to avoid unexpected loop entry by the Slave

transmitter.) The Slave’s on-loop bit is set and the

receiver is in hunt mode.

8. When the slave has sent all of its data the GAOP flag

should be cleared so that the CRC is sent on

underrun.

9. When the closing flag has been sent the Slave reverts

to a one bit delay, which produces another EOP.

10. The master must keep its output marking until its

receiver has received all frames sent by secondaries.

4. Note that there is a one bit time delay between

received data and transmitted data.

CMOS SCC AND ESCC

The discussion above applies to the NMOS SCC and the

CMOS SCC without the SDLC Frame Status FIFO feature.

The CMOS version and the ESCC have a SDLC Frame

Status FIFO for easier handling of the SDLC mode of

operation. The SDLC Status FIFO is designed for DMA

controlled SDLC receive for high speed SDLC data

transmission, or for systems whose CPU interrupt

processing is not fast.

■ Deeper FIFO (4 Bytes Transmit, and 8 Bytes receive)

■ Automatic Opening Flag transmission

■ Automatic EOM reset

■ Automatic /RTS deactivation

■ Fast /DTR//REQ mode

This FIFO is able to store up to 10 packets’ worth of byte

■ Complete CRC reception

count

(14-bit

count)

and

status

information

(Overrun/Parity/CRC error status). To use this feature,

simply enable this FIFO and let DMA transfer data to

memory. While DMA is transferring received data to the

memory, the CPU will check the FIFO and locate the data

in memory, as well as the status information of the

received packet.

■ Receive FIFO Antilock feature

■ Programmable DMA and interrupt request level

■ Improved data setup time specification

For more details on these functions, please refer to the

SCC/ESCC Technical manual and related documents.

Other ESCC enhancements make it easier to handle the

SDLC mode of operation. These include:

CONCLUSION

This application note describes the basic operation of the

SCC in SDLC operational modes. With minor variations,

most of these operations also apply to the CMOS SCC

with Status FIFO enabled and the ESCC.

6-104

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APPLICATION NOTE

1

USING SCC WITH Z8000 IN SDLC PROTOCOL

11

INTRODUCTION

This application note describes the use of the Z8030 Serial

Communications Controller (SCC) with the Z8000™ CPU

to implement communications controller in

Synchronous Data Link Control (SDLC) mode of

operation. In this application, the Z8002 CPU acts as a

controller for the SCC. This application note also applies to

the non-multiplexed Z8530.

this application, two Z8000 Development Modules are

used. Both are loaded with the same software routines for

initialization and for transmitting and receiving messages.

The main program of one module requests the transmit

routine to send a message of the length indicated by

“COUNT” parameter. The other system receives the

incoming data stream, storing the message in its resident

memory.

a

One channel of the SCC communicates with the remote

station in Half Duplex mode at 9600 bits/second. To test

DATA TRANSFER MODES

The SCC system interface supports the following data

transfer modes:

■ Block/DMA Mode. Using the Wait/Request (/W//REQ)

signal, the SCC introduces extra wait cycles in order to

synchronize the data transfer between a controller or

DMA and the SCC.

■ Polled Mode. The CPU periodically polls the SCC

status registers to determine if a received character is

available, if a character is needed for transmission, and

if any errors have been detected.

The example given here uses the block mode of data

transfer in its transmit and receive routines.

■ Interrupt Mode. The SCC interrupts the CPU when

certain previously defined conditions are met.

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Application Note

Using SCC with Z8000 in SDLC Protocol

SDLC PROTOCOL

Data communications today require a communications

protocol that can transfer data quickly and reliably. One

such protocol, Synchronous Data Link Control (SDLC), is

the link control used by the IBM Systems Network

Architecture (SNA) communications package. SDLC is a

subset of the International Standard Organization (ISO)

link control called High-Level Data Link Control (HDLC),

which is used for international data communications.

The address field contains one of more octets, which are

used to select a particular station on the data link. An

address of eight 1s is a global address code that selects all

the devices on the data link. When a primary station sends

a frame, the address field is used to select one of several

secondary stations. When a secondary station sends a

message to the primary station, the address field contains

the secondary station address, i.e., the source of the

message.

SDLC is a bit-oriented protocol (BOP). It differs from byte-

control protocols (BCPs), such as Bisync, in that it uses

only a few bit patterns for control functions instead of

several special character sequences. The attributes of the

SDLC protocol are position dependent rather than

character dependent, so the data link control is determined

by the position of the byte as well as by the bit pattern.

The control field follows the address field and contains

information about the type of frame being sent. The control

field consists of one octet that is always present.

The information field contains any actual transferred data.

This field may be empty or it may contain an unlimited

number of octets. However, because of the limitations of

the error-checking algorithm used in the frame-check

sequence, however, the maximum recommended block

size is approximately 4096 octets.

A character in SDLC is sent as an octet, a group of eight

bits. Several octets combine to form a message frame, in

which each octet belongs to a particular field. Each

message contains: opening flag, address, control,

information, Frame Check Sequence (FCS), and closing

flag (Figure 1).

The frame check sequence field follows the information or

control field. The FCS is a 16-bit Cyclic Redundancy

Check (CRC) of the bits in the address, control, and

information fields. The FCS is based on the CRC-CCITT

16

12

5

code, which uses the polynomial (x + x + x + 1). The

Z8030 SCC contains the circuitry necessary to generate

and check the FCS field.

Zero insertion and deletion is a feature of SDLC that allows

any data pattern to be sent. Zero insertion occurs when

five consecutive 1s in the data pattern are transmitted.

After the fifth 1, a 0 is inserted before the next bit is sent.

The extra 0 does not affect the data in any way and is

deleted by the receiver, thus restoring the original data

pattern.

Figure 1. Fields of the SDLC Transmission Frame

Both flag fields contain a unique binary pattern, 0111110,

which indicates the beginning or the end of the message

frame. This pattern simplifies the hardware interface in

receiving devices so that multiple devices connected to a

common link do not conflict with one another. The

receiving devices respond only after a valid flag character

has been detected. Once communication is established

with a particular device, the other devices ignore the

message until the next flag character is detected.

Zero insertion and deletion insures that the data stream

will not contain a flag character or abort sequence. Six 1s

preceded and followed by 0s indicate a flag sequence

character. Seven to fourteen 1s signify and abort; Seven

to fourteen 1s signify an abort; 15 or more 1s indicate an

idle (inactive) line. Under these three conditions, zero

insertion and deletion are inhibited. Figure 2 illustrates the

various line conditions.

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Application Note

Using SCC with Z8000 in SDLC Protocol

1

Figure 2. Bit Patterns for Various Line Conditions

The SDLC protocol differs from other synchronous

protocols with respect to frame timing. In Bisync mode, for

example, a host computer might temporarily interrupt

transmission by sending sync characters instead of data.

This suspended condition continues as long as the

receiver does not time out. With SDLC, however, it is

invalid to send flags in the middle of a frame to idle the line.

Such action causes an error condition and disrupts orderly

operation. Thus, the transmitting device must send a

complete frame without interruption. If a message cannot

be transmitted completely, the primary station sends an

abort sequence and restarts the message transmission at

a later time.

SYSTEM INTERFACE

The Z8002 Development Module consists of a Z8002

CPU, 16K words of dynamic RAM, 2K words of EPROM

monitor, a Z80A SIO providing dual serial ports, a

counter/timer channels, two Z80A PIO devices providing

32 programmable I/O lines, and wire wrap area for

prototyping. The block diagram is depicted in Figure 3.

Each of the peripherals in the development module is

connected in a prioritized daisy chain configuration. The

SCC is included in this configuration. The SCC is included

in this configuration by tying its IEI line to the IEO line of

another device, thus making it one step lower in interrupt

priority compared to the other device.

Figure 3. Block Diagram of Z8000 DM

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Application Note

Using SCC with Z8000 in SDLC Protocol

SYSTEM INTERFACE (Continued)

Two Z8000 Development Modules containing SCCs are

connected as shown in Figure 4 and Figure 5. The

Transmit Data pin of one is connected to the Receive Data

pin of the other and vice versa. The Z8002 is used as a

host CPU for loading the modules; memories with software

routines.

To select the read/write registers automatically, the SCC

decodes lines AD5-AD1 in Shift Left mode. The register

map for the SCC is depicted in Table 1.

Table 1. Register Map

Address

(Hex)

Write

Read

Register

FE01

FE03

FE05

FE07

FE09

FE0B

FE0D

FE0F

FE11

FE13

FE15

FE17

FE19

FE1B

FE1D

FE1F

FE21

FE23

FE25

FE27

FE29

FE2B

FE2D

FE2F

FE31

FE33

FE35

FE37

FE39

FE3B

FE3D

FE3F

WR0B

WR1B

WR2

WR3B

WR4B

WR5B

WR6B

WR7B

B DATA

WR9

WR10B

WR11B

WR12B

WR13B

WR14B

WR15B

WR0A

WR1A

WR2

WR3A

WR4A

WR5A

WR6A

WR7A

A DATA

WR9

RR0B

RR1B

RR2B

RR3B

Figure 4. Block Diagram of Two Z8000 CPUs

B DATA

RR10B

The Z8002 CPU can address either of the two bytes

contained in 16-bit words. The CPU uses an even address

(16 bits) to access the most significant byte of a word and

an odd address for the least significant byte of a word.

RR12B

RR13B

When the Z8002 CPU uses the lower half of the

Address/Data bus (AD7-AD0 the least significant byte) for

byte read and write transactions during I/O operations,

these transactions are performed between the CPU and

I/O ports located at odd I/O addresses. Since the SCC is

attached to the CPU on the lower half of the A/D bus, its

registers must appear to the CPU at odd I/O addresses. To

achieve this, the SCC can be programmed to select its

internal registers using lines AD5-AD1. This is done either

automatically with the Force Hardware Reset command in

WR9 or by sending a Select Shift Left Mode command to

WR0B in channel B of the SCC. For this application, the

SCC registers are located at I/O port address “Fexx”. The

Chip Select signal (/CSO) is derived by decoding I/O

address “FE” hex from lines AD15-AD8 of the controller.

RR15B

RR0A

RR1A

RR2A

RR3A

A DATA

RR10A

WR10A

WR11A

WR12A

WR13A

WR14A

WR15A

RR12A

RR13A

RR15A

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Application Note

Using SCC with Z8000 in SDLC Protocol

1

Figure 5. Z8002 With SCC

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Application Note

Using SCC with Z8000 in SDLC Protocol

INITIALIZATION

The SCC can be initialized for use in different modes by

setting various bits in its write registers. First, a hardware

reset must be performed by setting bits 7 and 6 of WR9 to

one; the rest of the bits are disabled by writing a logic zero.

The Z8002 CPU must be operated in System mode to

execute privileged I/O instructions. So the Flag and

Control Word (FCW) should be loaded with system normal

(S//N), and the Vectored Interrupt Enable (VIE) bits set.

The Program Status Area Pointer (PSAP) is loaded with

address %4400 using the Load Control Instruction

(LDCTL). If the Z8000 Development Module is intended to

be used, the PSAP need not be loaded by the programmer

because the development module’s monitor loads it

automatically after the NMI button is pressed.

SDLC protocol is established by selecting a SDLC mode,

sync mode enable, and a x1 clock in WR4. A data rate of

9600 baud, NRZ encoding, and a character length of eight

bits are among the other options that are selected in this

example (Table 2).

Note that WR9 is accessed twice, first to perform a

hardware reset and again at the end of the initialization

sequence to enable the interrupts. The programming

sequence depicted in Table 2 establishes the necessary

parameters for the receiver and transmitter so that they are

ready to perform communication tasks when enabled.

Since VIS and Status Low are selected in WR9, the

vectors listed in Table 3 will be returned during the

Interrupt Acknowledge cycle. Of the four interrupts listed,

only two, Ch A Receive Character Available and Ch A

Special Receive Condition, are used in the example given

here.

Table 2. Programming Sequence for Initialization

Table 3. Interrupt Vectors

Value

Vector PS

Interrupt

Register (Hex) Effect

(Hex)

Address

WR9

WR4

C0

20

Hardware reset

x1 clock, SDLC mode,

sync mode enable

NRZ, CRC preset to one

Any station address e.g. “AB”

SDLC ﬂag (01111110) = “7E”

Interrupt vector “20”

Tx clock from BRG output, /TRxC pin

= BRG out

28

2A

2C

2E

446E

4472

4476

447A

Ch A Transmit Buffer Empty

Ch A External Status Change

Ch A Receive Char. Available

Ch A Special Receive Condition

WR10

WR6

WR7

WR2

WR11

80

AB

7E

20

16

* Assuming that PSAP has been set to 4400 hex, “PS

Address” refers to the location in the Program Status Area

where the service routine address is stored for that

particular interrupt.

WR12

CE

Lower byte of time constant = “CE” for

9600 baud

WR13

WR14

0

03

Upper byte = 0

BRG source bit =1 for PCKL as input,

BRG enable

WR15

WR5

WR3

00

60

C1

External Interrupt Disable

Transmit 8 bits/character SDLC CRC

Rx 8 bits/character, Rx enable

(Automatic Hunt mode)

ext int. disable

WR1

WR9

08

09

MIE, VIS, status Low

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Application Note

Using SCC with Z8000 in SDLC Protocol

TRANSMIT OPERATION

To transmit a block of data, the main program calls up the

transmit data routine. With this routine, each message

block to be transmitted is stored in memory, beginning with

location “TBUF” The number of characters contained in

each block is determined by the value assigned to the

“COUNT” parameter in the main module.

The CRC generator is reset and the Transmit CRC bit is

enabled before the first character is sent, thus including all

the characters sent to the SCC in the CRC calculation.

1

The SCC transmit underrun/EOM latch must be reset

sometime after the first character is transmitted by writing

a Reset Tx Underrun/EOM command to WR0. When this

latch is reset, the SCC automatically appends the CRC

characters to the end of the message in the case of an

underrun condition.

To prepare for transmission, the routine enables the

transmitter and selects the Wait On Transmit function; it

then enables the wait function. The Wait on Transmit

function indicates to the CPU whether or not the SCC is

ready to accept data from the CPU. If the CPU attempts to

send data to the SCC when the transmit buffer is full, the

SCC asserts its /WAIT line and keeps it Low until the buffer

is empty. In response, the CPU extends its I/O cycles until

the /WAIT line goes inactive, indicating that the SCC is

ready to receive data.

Finally, a three-character delay is introduced at the end of

the transmission, which allows the SCC sufficient time to

transmit the last data byte and two CRC characters before

disabling the transmitter.

RECEIVE OPERATION

Once the SCC is initialized, it can be prepared to receive

the message. First, the receiver is enabled, placing the

SCC in Hunt mode and thus setting the Sync/Hunt bit in

status register RR0 to 1. In Hunt mode, the receiver

searches the incoming data stream for flag characters.

Ordinarily, the receiver transfers all the data received

between flags to the receive data FIFO. If the receiver is in

Hunt mode, however, no data transfer takes place until an

opening flag is received. If an abort sequence is received,

the receiver automatically re-enters Hunt mode. The Hunt

status of the receiver is reported by the Sync/Hunt bit in

RR0.

Interrupt on First Character mode. Upon detection of the

receive interrupt, the CPU generates an Interrupt

Acknowledge Cycle. The SCC returns the programmed

vector %2C. This vector points to the location %4472 in the

Program Status Area which contains the receive interrupt

service routine address.

The receive data routine is called from within the receive

interrupt service routine. While expecting a block of data,

the Wait on Receive function is enabled. Receive read

buffer RR8 is read and the characters are stored in

memory location RBUF. The SCC in SDLC mode

automatically enables the CRC checker for all data

between opening and closing flags and ignores the

Receive CRC Enable bit (D3) in WR3. The result of the

CRC calculation for the entire frame in RR1 becomes valid

only when the End of Frame bit is set in RR1. The

processor does not use the CRC bytes, because the last

two bits of the CRC are never transferred to the receive

data FIFO and are not recoverable.

The second byte of an SDLC frame is assumed by the

SCC to be the address of the secondary stations for which

the frame is intended. The SCC provides several options

for handling this address. If the Address Search Mode bit

D2 in WR3 is set to zero, the address recognition logic is

disabled and all the received data bytes are transferred to

the receive data FIFO. In this mode, software must

perform any address recognition. If the Address Search

Mode bit is set to one, only those frames with addresses

that match the address programmed in WR6 or the global

address (all 1s) will be transferred to the receive data

FIFO. If the Sync Character Load Inhibit bit (D1) in WR3 is

set to zero, the address comparison is made across all

eight bits of WR6. The comparison can be modified so that

only the four most significant bits of WR6 need match the

received address. This alterations made by setting the

Sync Character Load Inhibit bit to one. In this mode, the

address field is still eight bits wide and is transferred to the

FIFO in the same manner as the data. In this application,

the address search is performed.

When the SCC recognizes the closing flag, the contents of

the Receive Shift register are transferred to the receive

data FIFO, the Residue Code (not applicable in this

application) is latched, the CRC error bit is latched in the

status FIFO, and the End of Frame bit is set in the receive

status FIFO, a special receive condition interrupt occurs.

The special receive condition register RR1 is read to

determine the bit is zero, the frame received is assumed to

be correct; if the bit is 1, an error in the transmission is

indicated.

Before leaving the interrupt service routine, Reset Highest

IUS (Interrupt Under Service), Enable Interrupt on Next

Receive Character, and Enter Hunt Mode commands are

issued to the SCC.

When the address match is accomplished, the receiver

leaves the Hunt mode and establishes the Receive

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Application Note

Using SCC with Z8000 in SDLC Protocol

RECEIVE OPERATION (Continued)

If receive overrun error is made, a special condition

interrupt occurs. The SCC presents vector %2E to the

CPU, and the service routine located at address %447A is

executed. Register RR1 is read to determine which error

occurred. Appropriate action to correct the error should be

taken by the user at this point. Error Reset and Reset

Highest IUS commands are given to the SCC before

returning to the main program so that the other low-priority

interrupts can occur.

In addition to searching the data stream for flags, the

receiver also scans for seven consecutive 1s, which

indicates an abort condition. This condition is reported in

the Break/Abort bit (D7) in RR0. This is one of many

possible external status conditions. As a result transitions

of this bit can be programmed to cause an external status

interrupt. The abort condition is terminated when a zero is

received, either by itself or as the leading zero of a flag.

The receiver leaves Hunt mode only when a flag is found.

SOFTWARE

Software routines are presented in the following pages.

These routines can be modified to include various other

options (e.g., SDLC Loop, Digital Phase Locked Loop

etc.). By modifying the WR10 register, different encoding

methods (e.g., NRZI, FM0, FM1) other than NRZ can be

used.

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Using SCC with Z8000 in SDLC Protocol

1

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Application Note

Using SCC with Z8000 in SDLC Protocol

SOFTWARE (Continued)

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Application Note

Using SCC with Z8000 in SDLC Protocol

1

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Application Note

Using SCC with Z8000 in SDLC Protocol

RECEIVE OPERATION (Continued)

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APPLICATION NOTE

1

BOOST YOUR SYSTEM PERFORMANCE USING

™

THE ZILOG ESCC

12

for greater testability, larger interface flexibility, and increased CPU/DMA offloading,

™

replace the SCC with the ESCC Controller... and utilize the ESCC to its full potential.

F

INTRODUCTION

This App Note (Application Note) describes the differences

between the SCC (Z8030/8530, Z80C30/85C30) and

ESCC (Z80230/85230). It outlines the procedures in

utilizing the ESCC to its full potential. Application details

such as Schematics and Program Listings are not included

since these materials are in our various application

support products.

Notes: All Signals with a preceding front slash, “/”, are

active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE

is active Low, only).

Power connections follow conventional descriptions

below:

Connection

Power

Circuit

Device

Note: The author assumes the audience has fundamental

Datacommunications knowledge and basic familiarity with

Zilog SCC products.

V

DD

CC

Ground

GND

V

SS

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Application Note

Boost Your System Performance Using The Zilog ESCC

™

ESCC/SCC DIFFERENCES

The differences between the ESCC and SCC are shown

below:

ESCC ENHANCEMENT

PERFORMANCE BENEFITS

- Improves Testability

1. Extended Read Enable of Write Registers

- Ability to examine SDLC status on-the-ﬂy

2. Hardware Improvement

- Modiﬁed WRITE Timing

- Modiﬁed DMA Request on

- Transmit Deactivation Timing

- Improves Interface to 80X86 CPU

- Improves Interface DMA-driven system

3. Throughput improvement

- Deeper Transmit FIFO

- Deeper Receive FIFO

- FIFO Interrupt Level

- Reduces TBE Interrupt Frequency by 3/4

- Reduces RCA Interrupt Frequency by 3/4

- Flexibility in Adapting CPU Workload

4 SDLC End Of Frame Improvement

- Automatic RTS Deassertion after Closing Flag

- Automatic Opening Flag Transmission

- Reduces CPU and DMA Controller Overhead after

End Of Frame

- Automatic TxD Forced High in SDLC with NRZI Encoding

When Marking Idle After End Of Frame

- Allows Optimal SDLC Line Utilization

- Improvement to Allow Transmission of Back-to-Back

Frames with a Shared Flag

- Status FIFO Anti-Lock Feature in DMA-Driven System

The differences between the ESCC and SCC are

summarized by a new register, WR7' (Figure 1).

The advantages of the new features are illustrated in the

following examples.

One of the features that is offered by the ESCC, but not the

SCC, is Extended Read Enable. Write Register values

from the WR3, WR4, WR5, WR7', and WR10 can be

examined in the ESCC but not the SCC. This feature

improves system testability. It is also crucial for

SCC/ESCC differentiation and allows generic software

structures for all SCC/ESCC devices.

RR7' Prime

D7 D6 D5 D4 D3 D2 D1 D0

Auto Tx Flag

Auto EOM Reset

Auto RTS Deactivate

Rx FIFO Int Level

DTR/REQ Timing

Tx FIFO Int Level

Extended RD Enable

Not Used, Always 0

Flowchart 1 (Figure 2) shows a generic software structure

applicable for all SCC/ESCC initializations. Flowchart 2

(Figure 3) suggests a method for determining which type

of SCC/ESCC™ device is in the socket. This software

structure helps the development of software drivers

independent of the device type.

Addressing:

WR15 D0

WR7

'1'

'XX'

Figure 1. WR7' Deﬁnition

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Application Note

™

Boost Your System Performance Using The Zilog ESCC

Reset

1

Determine

SCC/ESCC Type

1

2

SCC

Z85C30

ESCC

Z85230

Z85C30

Initialization

Z85230

Initialization

Figure 2. Generic SCC/ESCC Drivers

Reset

WR15

'01' H

N

Y

RR15 = '01' H

?

2

1

SCC

ESCC

Z85C30

Z85230

End

Figure 3. SCC/ESCC Differentiation Flowchart

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Application Note

Boost Your System Performance Using The Zilog ESCC

™

ESCC SYSTEM BENEFITS

The Software Overhead sets the System Performance

Limits. The ESCC’s deeper FIFOs and other features

significantly reduce the software overhead for each

channel. This allows:

■ Faster Data Rates on Channels

■ More CPU bandwidth available for other tasks

■ Lower CPU Costs

■ More Channels Per System

Data Fl

SCC

Interru

Syste

Data Fl

Interru

Syste

ESCC

Interrupt Frequency Reduction

SCC Systems

Other CPU T

Transmit

Interrupt Ove

Time

ESCC Systems

Other CPU T

Additional Perfor

Transmit

Interrupt Ove

Time

ESCC Reduces System Workload and Allows Extra Performance

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Application Note

™

Boost Your System Performance Using The Zilog ESCC

TRANSMIT FIFO INTERRUPT

In the ESCC, transmit interrupt frequencies are reduced by

a deeper Transmit FIFO and the revised transmit interrupt

structure. If the WR7' D5 Transmit FIFO Interrupt Level bit

is reset, the transmit interrupt is generated when the entry

location of the FIFO is empty, i.e., more data can be

written. This is downward compatible with a SCC Transmit

Interrupt since the SCC only has a one-byte transmit buffer

instead of a four-byte Transmit FIFO.

If WR7' D5 is set, the transmit buffer empty interrupt is

generated when the transmit FIFO is completely empty.

Enabling the transmit FIFO interrupt level, together with

polling the Transmit Buffer Empty (TBE) bit in RR0, causes

significant transmit interrupt frequency reduction. Transmit

data is sent in blocks of four bytes (algorithm is illustrated

in Figure 4). This helps to offload those systems which

have long interrupt latency or a fully loaded Operating

System.

1

TX FIFO Int.

Level Enabled

TBE Interrupt

Service

NO

RR0

TBE = '1'?

YES

Write Data To

Transmit FIFO

Full

Transmit FIFO

Is Loaded

With Data

Figure 4. Flowchart of Transmit Interrupt Service Routine to Reduce Transmit Interrupt Frequencies

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Boost Your System Performance Using The Zilog ESCC

™

RECEIVE FIFO INTERRUPT

In the ESCC, receive interrupt frequencies are reduced

due to a deeper Receive FIFO and the revised receive

interrupt structure.

when the Receive FIFO is half full; the first four locations

from the entry are still empty. By enabling the receive FIFO

interrupt level, together with polling the Receive Character

Available (RCA) bit in RR0, the receive interrupt

frequencies are reduced significantly. Receive data is read

in blocks of four bytes (Figure 5). This would help to offload

systems which have a long interrupt latency and heavily

loaded Operating Systems.

If WR7' D3 Receive FIFO Interrupt Level bit is reset, the

ESCC generates the receive character available interrupt

on every received character. This is compatible with SCC

Receive Character Available Interrupt. If WR7' D3 is set,

the Receive Character Available Interrupt is triggered

RX FIFO Int.

Level Enabled

RCA Interrupt

Service

NO

RR0

RCA = '1'?

YES

RX FIFO

Empty

Read Data

From RX FIFO

All Data in

RX FIFO Have

Been Read

Figure 5. Flowchart of Receive Interrupt Service Routine to Reduce Receive Interrupt Frequencies

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™

Boost Your System Performance Using The Zilog ESCC

AUTOMATIC /RTS DEASSERTION

Several SDLC enhancements are provided in the ESCC.

The ESCC allows automatic /RTS deassertion at End Of

Frame (EOF). The automatic /RTS deassertion is enabled

by setting WR7' D2. If ESCC is programmed for SDLC

mode and the Flag-On-Underrun bit (WR10 D2) is reset,

with the RTS bit (WR5 D1) reset, /RTS is deasserted

automatically at the last bit of the closing flag. It is triggered

by the rising edge of the Transmit Clock (TxC - Figures 6

and 7).

/RTS is normally used in SDLC for switching the direction

of line drivers. Automatic /RTS deassertion allows optimal

line switching without any software intervention. The

typical procedures are as follows:

1

1. Enable Automatic /RTS Deassertion

2. Before frame transmission, set RTS bit

3. Enable frame transmission

4. Reset RTS bit

5. RTS pin deassertion is delayed until the last rising TxC

edge closing flag.

Data Being Sent

Data CRC1

CRC2

Flag

TX Underrun/EOM

RTS Bit

(WR5, D1)

/RTS Pin

Figure 6. /RTS Deassertion Timing

Automatic RTS Pin Deactivation

TXC

TXD

Mark

TX Closing

Flag

/RTS

Figure 7. /RTS Deassertion Sequence

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Application Note

Boost Your System Performance Using The Zilog ESCC

™

AUTOMATIC OPENING FLAG TRANSMISSION

When Auto Tx Flag (WR7', D0) is enabled, the ESCC

automatically transmits a SDLC opening flag before

transmitting data. This removes:

feature is used in combination with the automatic SDLC

opening flag transmission to format the data packets

between successive frames properly without any

requirement in software intervention.

1. Requirements to reset the mark idle bit (WR10 D3)

before writing data to the transmitter, or;

Status FIFO Enhancement

ESCC SDLC Frame Status FIFO implementation has

been improved to maximize ESCC ability to interface with

a DMA-driven system (Technical Manual, 4.4.3). The

Status FIFO and its relationship with RR1, RR6 and RR7

is shown in Figure 8.

2. Waiting for eight bit times to load the opening flag.

TxD Forced High In SDLC With NRZI Encod-

ing When Marking Idle After End Of Frame

When the ESCC is programmed for SDLC mode with NRZI

encoding and mark idle (WR10 D6=0,D5=1,D3=1), TxD is

automatically forced high when the transmitter goes to the

mark idle state at EOF or when Abort is detected. This

Other special conditions (e.g., Overrun) generates special

receive conditions and lock the Receiver FIFO (Figures 9

and 10).

Status

FIFO

Loaded If

Status FIFO

Is Enabled

RR1

Residue

Code

RR7

RR6

Byte Count

RX

Overrun

Error

CRC/Framing

Error

Figure 8. Status FIFO

6-124

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Application Note

™

Boost Your System Performance Using The Zilog ESCC

SDLC Frame Status FIFO enhancement is enabled by

setting WR15 D2. If it is enabled when EOF is detected,

byte count and status from the Status FIFO are loaded into

RR6, RR7 and RR1. This is used in DMA-driven systems.

Historically, EOF is treated as a special condition. Special

condition interrupts are triggered if any one of the below

interrupts is enabled:

and high data rate communications. The reason is the

ERROR RESET command is necessary to unlock the

FIFO. Data from the next frame may be lost if ERROR

RESET fails to issue early.

1

This drawback is improved in the ESCC for a DMA driven

system. By enabling interrupts on “Special Receive

Conditions only” and SDLC status FIFO, EOF is treated

differently from other special conditions. When EOF status

reached the exit location of the FIFO:

1. Receive Interrupt on First Character or Special

Condition.

2. Interrupt on All Receive Characters or Special

Conditions.

1. A “Receive Data Available” interrupt is generated to

signal that EOF has been reached.

3. Special Receive Condition Only.

2. Receive Data FIFO is not locked.

If 1 or 3 (above) is enabled, the data FIFO is locked after

the interrupt is serviced by reading RR1 in the Status

FIFO, as shown in Figure 11. This is commonly used in a

DMA-driven system to avoid delivering useless

information (e.g., EOF) to the data buffer. Locking the data

FIFO is not desirable in systems with long interrupt latency

Because of these changes, the data from the next frame is

securely loaded and the system processes the EOF

interrupt. The only responsibility of the software is issuing

the Reset Highest IUS before resuming normal operation

(Figure 12).

Data n,N

EOF

Data 1,N+1

Packet N

Packet N+1

Data Flow Into

ESCC Receive

Data FIFO

Data 1,N+1

EOF

Set

FIFO Data

Available

Set FIFO

Overflow If

Required

Data n,N

Status

FIFO

Y

Enabled?

Packet N

Status Is

Loaded

n

Increment

FIFO Pointer

Byte Count

of Packet N

Packet 10

SDLC

Status

FIFO

Packet 2

Packet 1

Byte Count

(RRT = RR6)

Status

(RR1)

Figure 9. Status FIFO Operation at End Of Frame

6-125

UM010901-0601

Application Note

Boost Your System Performance Using The Zilog ESCC

™

AUTOMATIC OPENING FLAG TRANSMISSION (Continued)

Data with Special Condition

Data Data* Data

End of Frame Flag

Data

EOF

Data

Packet N

Packet N+1

Special Condition

Interrupt

Data

Rx

Data

FIFO

Data*

Data

Rx

Data

FIFO

Receive Character

Available Interrupt

EOF

Data

1. Enable Receive Interrupt on Special Conditions only.

2. Receive Data FIFO locked.

3. Special Condition Interrupt generated.

1. Enable Receive Interrupt on Special Conditions only.

2. Receive Data FIFO not locked.

3. Receive Character Available Interrupt generated

even if it has not been enabled to indicate detection of EOF.

Figure 10. SDLC Status FIFO Anti-Lock

SDLC FIFO Ena

Receive Interr

Special Conditi

CRC err

Overrr

Error

Specia

Conditi

Interr

Data

FIFO

Locke

Data

FIFO

Unloc

Erro

Rese

Pari

Erro

"Reset Hig

IUS" to R

EOF Inter

End o

Frame

Receive Char

Available In

Figure 11. Receive Interrupt Mechanism 1

6-126

UM010901-0601

Application Note

™

Boost Your System Performance Using The Zilog ESCC

1

Receive Interrupt on 1st

Special Conditions or In

Receive Characters or Spec

CRC err

Overrr

Error

Specia

Conditi

Interr

Data

FIFO

Locke

Data

FIFO

Unloc

Erro

Rese

Pari

Erro

End o

Frame

Receiv

Char.

Availa

Receive Char

Available In

Figure 12. Receive Interrupt Mechanism 2

In the SCC, Transmission of Back-to-Back Frames is more

difficult because (Figure 14):

DMA Request on Transmit Deactivation

Timing /DTR//REQ.

Timing implementation in the ESCC has been improved to

make it more compatible with the DMA cycle timing

(Reference Tech Manual, Section 2.5.2; DMA Request on

Transmit).

1. Data cannot be written to the transmitter at EOF until

a Transmit Buffer Empty interrupt is generated after

CRC has completed transmission.

2. Automatic EOM Reset is not available in the SCC.

Application software has to issue the “Reset

Tx/Underrun EOM” command manually. The software

overhead limits the next frame data to deliver

immediately after the preceding frame has been

concluded with CRC and Flag.

Transmission of Back-To-Back Frames with

a Shared Flag.

The ESCC provides facilities to allow transmission of

back-to-back frames with a shared flag between frames

(Figure 13).

In the ESCC, if the Automatic End Of Message (EOM)

Reset feature is enabled (WR7' D1=1), data for a second

frame is written to the transmit FIFO when Tx

Underrun/EOM interrupt has occurred. This allows

application software sufficient time to write the data to the

transmit FIFO while allowing the current frame to be

concluded with CRC and flag.

6-127

UM010901-0601

Application Note

Boost Your System Performance Using The Zilog ESCC

™

AUTOMATIC OPENING FLAG TRANSMISSION (Continued)

Requirements: Automatic EOM Reset and Automatic Opening Flag features are enabled.

Flag

Closing

Flag

Frame N

Opening

Flag

Frame N+1

Figure 13. Transmission of Back-to-Back Frames with a Shared Flag

Enable Automatic EOM Reset

Data

CRC1

CRC2

Flag

Data

TX Underrun/EOM

Tx BE

ESCC Loa

Data He

SCC Loa

Data He

Figure 14. Operation of Shared Flag Transmission

6-128

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Application Note

™

Boost Your System Performance Using The Zilog ESCC

MODIFIED WRITE TIMING

In the SCC write cycle, the SCC assumes the data is valid

when /WR is asserted (Figure 15). This assumption is not

valid for some CPUs, e.g., the Intel 80X86. The /WR signal

from this CPU needs to delay for one more clock to initiate

the write cycle. Additional hardware is required.

In the ESCC, write cycle timing has been modified so that

data becomes valid a short time after write (approx. 20 ns).

Therefore, if the data pins from the Intel CPU are

connected directly to the ESCC, no additional logic is

required.

1

/WR

SCC

Databus Valid

SCC Spec:

WR Falling

Databus Va

Minimum

29

ESCC Spec:

Databus Valid to WR Fallin

29

ESCC

Databus Valid

Databus latched after falling edge of WR saves external logic required

to delay WR until databus is valid. Typically needed with Intel CPUs.

Figure 15. Modiﬁed Write Timing

6-129

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12-130

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APPLICATION NOTE

1

TECHNICAL CONSIDERATIONS WHEN IMPLEMENTING

LOCALTALK LINK ACCESS PROTOCOL

13

he LLAP Protocol is an important part of the Appletalk network system. It manages

access to the node-to-node transmission of network data packets, governs access to the

link, and provides a means for nodes to discover valid addresses...all error free.

T

INTRODUCTION

The LLAP (LocalTalk Link Access Protocol) is the ISO/OSI

(International Standards Organization/Open Systems

Interconnection) link layer protocol of the AppleTalk

network system. This protocol manages the node-to-node

transmission of data packets in the network. LLAP governs

access to the link and provides a means for nodes to

discover valid addresses. It does not guarantee packet

delivery; it does guarantee that those packets that are

delivered are error-free.

This Appnote (Application Note) does not address the

architectural issues of writing a driver but it does focus on

the details of using an SCC to send and receive LLAP

frames. However, some of the problems of transmitting

and receiving LLAP frames are discussed, using sample

code written for Zilog’s Z80181 Emulation Adapter Board.

Also, the problems of sending sync pulses, timing

transmissions and determining that a frame has been

received properly will be discussed.

GENERAL DESCRIPTION

The LocalTalk Link Access Protocol (LLAP) is the ISO-OSI

link layer protocol of the AppleTalk network system using

LocalTalk. Along with ELAP (the corresponding Ethernet

link layer protocol) and TLAP (the Token Ring link layer

protocol), it provides the foundations upon which the other

protocols rest. The LLAP protocol supports the node-to-

node transmission of packets used by DDP and RTMP to

route packets around the internetwork; DDP, in turn,

supports the name binding functions of NBP, the reliable

frame delivery of ATP, and the rest of the AppleTalk

protocol stack.

The LLAP provides the basic transmission of packets from

one node to another on the same network. LLAP accepts

packets of data from clients residing on a particular node

and encapsulates that data into its proper LLAP data

packet. The encapsulation includes source and

destination addresses for proper delivery. LLAP ensures

that any damaged packet is discarded and rejected by the

destination node. The LLAP makes no effort to deliver

damaged packets.

Carrier Sense Multiple Access with Collision

Avoidance

A majority of the difficult timing and all of the hardware

interface problems crop up in the LLAP driver. These

problems are so difficult that it makes sense to start writing

such a driver by writing experimental routines that transmit

and receive frames. This App Note addresses the

intricacies of the interframe and interdialog timings before

trying to engineer code that will truly be a driver. Also,

some of the experimental routines to run on the Z80181

Emulation Adapter Board will be explained.

It is LLAP’s responsibility to provide proper link access

management to ensure fair access to the link by all nodes

on that network. The access discipline that governs this is

known as Carrier Sense Multiple Access with Collision

Avoidance (CSMA/CA). A node wishing to gain access to

the link must first sense that the link is not in use by any

other node (carrier sense); if the link has activity, then the

node wishing to transmit must defer transmission. The

ability of LLAP to allow multiple access to the link also

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Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

GENERAL DESCRIPTION (Continued)

leaves room for possible collisions with other data packets.

LLAP attempts to minimize this probability (collision

avoidance).

External/Status interrupt can be generated. This is

important because the node wishing to use the bus can

simply wait for this interrupt before preparing to transmit

it’s packet.

Two techniques are used by LLAP in its implementations

of CSMA/CA. LLAP outlines this procedure but falls short

in endorsing which hardware to use. (The SCC is, of

course, used by Apple.) The first technique takes

advantage of the distinctive 01111110 flag bytes that

encapsulate the data packet (note that this implies that

SDLC is used). LLAP stipulates that a minimum of two

flags precede each of these data packets. The leading flag

characters provide byte synchronization and give a clue to

any listener that some other node is using the link at a

particular time (use the Hunt bit in RR0 if the SCC is used).

LLAP uses a second technique in its carrier sensing. LLAP

requires that a synchronization pulse for an idle period of

at least two bit times be transmitted prior to sending the

RTS handshaking frame (Figure 1). This synchronization

is obtained by first enabling the hardware line so that an

edge is detected by all the receivers on the network. This

initial edge is perceived as the beginning of the clocking

period. It is soon followed by an idle period (a period with

no carrier) of at least two bit times. All the receivers on the

network see this idle period and assume that the clock has

been lost (missing clock bit set on RR10 ). This method is

much more immediate than the byte flag synchronization

method and provides a quicker way of determining

whether the link is in use. Unfortunately, an interrupt is not

generated by this missing clock and, therefore, polling

must be implemented.

In SDLC mode, the receiver automatically synchronizes on

the flag byte and resets the Hunt bit to zero. The SCC has

some latency in detecting these flag bytes due to the

shifter, etc. This is not ideal because the node needing to

transmit may determine that the link is free, when in fact

the flag bytes are still being shifted into its receiver (i.e., the

link is not idle at all).

The Z80181 code used for polling the missing clock bit is

approximately fifty clock cycles which at 10 MHz is about

5 µsec or about one bit time. This is still relatively quicker

than the time required for the SCC to reset the Hunt bit (the

flag character takes at least eight bit times for it to be

shifted through the buffer before the Hunt bit is reset to

zero). Synchronization pulses can be sent before every

frame but because of the time constraints associated with

the interframe gaps it makes sense to send such pulses

only before the lapENQ and lapRTS frames.

A closing flag is also needed to fully encapsulate the data

packet. LLAP requires that 12 to 18 ones be sent after this

closing flag. The LocalTalk hardware (i.e., the SCC)

interprets this as an abort sequence and causes the

node’s hardware to lose byte sync; this then confirms that

the current sender’s transmission is over. In SDLC mode,

seven or more contiguous 1’s in the receive data stream

forces the receiver into Hunt (Hunt bit set) and an

2 Bit Times (Min)

RTS

1 Bit Time (Min)

Partial Flag

Flag

LLAP Packet

CRC

Flag

12-18 1's

TxD

Possible Partial Flag

TxUnderrun Int.

Figure 1. CSMA/CA Synchronization Pulse Timing Diagram

6-132

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Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

The source node uses the physical layer to detect the

presence or the absence of data packets on the link. The

Dynamic Node ID

LLAP requires the use of an 8-bit node identifier number

(node ID) for each node on the link. Apple had decided that

all LLAP nodes must have a dynamically assigned node

ID. A node would assign itself its unique address upon

activation. It is then up to that particular node to ascertain

that the address it had chosen is unique. A node randomly

chooses an 8-bit address (for example, the refresh register

value on the Z80181 is added to a randomly chosen value

on the receive buffer to obtain a pseudo random 8-bit

address).

node will wait until the line is no longer busy before

attempting to send its packets. If the node senses that the

line is indeed busy, then this node must defer. When the

node senses that the line is idle, then the node waits the

minimum IDG plus some randomly generated time before

sending the packet (the line must remain idle throughout

this period before attempting to send the packet). The

initial packets to be sent are handshaking packets. The

first packet sent by the source node to its destination node

is the RTS packet. The receiver of this RTS packet must

return a CTS packet within the allowable maximum IFG.

The source node then starts transmitting the rest of its data

packet upon receiving this CTS.

1

The node then sends out an LLAP Enquiry control packet

to all the other nodes and waits for the prescribed

interframe gap of 200 µsec. If another node is already

using this node ID, then that node must respond within 200

µsec with a LLAP Acknowledgment control packet. The

new node must then rebroadcast a new guess for its node

ID. If a LLAP Acknowledgment packet is not received

within 200 µsec then the new node assumes that the

address is indeed unique. The new node must rebroadcast

the LLAP enquiry packet several more times to account for

cases when the packet could have been lost or when the

guessed node ID is busy and could have missed the

Enquiry packet.

Collisions are more likely to occur during the handshaking

phase of the dialog. The randomly generated time that is

added to the IDG tends to help spread out the use of the

link among all the transmitters. A successful RTS to CTS

handshake signifies that a collision did not take place. An

RTS packet that collides with another frame has corrupt

data that shows up as a CRC error on the receiving or the

destination node. Upon receiving this, the destination node

infers that a collision must have taken place and abstains

from sending its CTS packet. The source or the

transmitting node sees that the CTS packet was not

received during the IFG and also infers that a collision did

take place. The sending node then backs off and retries.

LLAP Packet

LLAP packets are made up of three header bytes

(destination ID, source ID and LLAP type) and 0 to 600

bytes of variable length data. The LLAP type indicates the

type of packet that is being sent. 80H to FFH are reserved

as LLAP control packets. The four LLAP control packets

that are currently being used are: The lapENQ, which is

used as enquiry packet for dynamic node assignments;

the lapACK, which is the acknowledgment to the lapENQ;

the lapRTS, which is the request to send packet that

notifies the destination of a pending transmission; and the

lapCTS, which is the clear-to-send packet in response to

the RTS packet. Control packets do not contain data fields.

The LLAP keeps two history bytes that log the number of

deferrals and collisions during a dialog. These history

bytes help determine the randomly generated time that is

added to the IDG. The randomly generated time is

readjusted according to the traffic conditions that are

present on the link. If collisions or deferrals have just

occurred on the most recently sent packets, then it can be

assumed that the link has heavier than usual traffic. Here,

the randomly generated number should be a larger

number in order to help spread out the transmission

attempts. Similarly, if the traffic is not so great, then the

randomly generated number should be smaller, thus

reducing the dispersion of the transmission attempts.

LLAP Packet Transmission

LLAP distinguishes between two types of transmissions: a

directed packet is sent from the source node to a specific

destination node through a directed transmission dialog; a

broadcast packet is sent from the source node to all nodes

on the link (destination ID is FFH) through a broadcast

transmission dialog. All dialogs must be separated by a

minimum Inter Dialog Gap (IDG) of 400 µsec. Frames

within these dialogs must be separated from each other

with a maximum Inter Frame Gap (IFG) of 200 µsec.

LocalTalk Physical Layer

LocalTalk uses the SDLC format and the FM0 bit encoding

technique. The RS-422 signalling standard for

transmission and reception was chosen over the RS-232

because a higher data rate over a longer physical distance

is required. LocalTalk requires signals at 230.4 Kbits per

second over a distance of 300 meters.

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Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

HARDWARE CONFIGURATION

As shown in Figure 2, the hardware used to implement this

LLAP driver consists of the Z80181 (an integration of the

Z80180 compatible MPU core with one channel of a

Z85C30 SCC, Z80 CTC, two 8-bit general-purpose parallel

ports and two chip select signals) operating at 10 MHz, a

3.6864 MHz clock source and an RS-422 line driver with

tri-state.

used as transmitter clock. This 230.4 kHz signal is also

used by one of the Z80181’s counter/timer trigger inputs

(Z80 CTC’s channel 1) which is used to count the number

of elapsed bit times. In counter mode, each active edge to

the CTC’s CLK/TRG1 input causes the downcounter of the

CTC to be decremented. The /TRxC pin is programmed as

BRG output and is connected to the CLK/TRG1 input

through an external wire.

The SCC’s clocking scheme decouples the micro-

processor’s clock from the communication clock (Figure

3). The DPLL uses the /RTxC pin as its source. The /RTxC

also drives the Baud Rate Generator which divides its

input by sixteen. The resulting 230.4 kHz signal is then

The /RTS signal is used to tri-state RS-422 to allow other

node transmitters to drive the line. This signal is asserted

and deasserted through bit1 of the SCC’s Write Register 5.

3.6864 MHz

/RTxC

/RTS

TxD

SCC/2

/TRxC

RxD

To Line

Z80181

RS-422 Drivers

From Line

230.4 kHz

Z80180

CLK/TRIG1

CTC

GLU

Addr

Decode

Logic

PIA2

PIA1

PCLK = 10 MHz

Figure 2. Driver Hardware Conﬁguration

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Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

DPLL

Rx

1

Rx

Tx

/RTxC

7.37 MHz

1/2

3.6864 MHz

= 16x230.4 kHz

Receiver

RxDPLL Out

BRG

/16

BRG Out

/RTxC

/TRxC

Tx

Transmitter

230.4 kHz

Figure 3. SCC Clocking Scheme

Listing 1 (Reference Appendix A for Listings 1 through 4)

shows the assembler code for this SCC initialization. Note

that the SCC is treated as a peripheral by the Z80181’s

MPU. For example, an I/O write to the scc_cont (address

e8H) or to the scc_data (address e9H) is a write to the

SCC’s control and data registers, respectively. As shown

in Listing 1, the SCC is initialized by issuing I/O writes to

the pointer and then to the control registers in an

alternating fashion. It is therefore very important that all

interrupts are disabled during this initialization routine.

Since SDLC is bit-oriented, the transmitter and receiver

are both programmed for 8 bits per character as required

by LLAP. Address filtering is implemented by setting the

Address Search Mode bit 2 on WR3. Setting this bit

causes messages with addresses not matching the

address programmed in WR6 and not matching the

broadcast address to be rejected. Values in WR10 presets

the CRCs to ones, sets the encoding to FM0 mode and

makes certain that transmission of flags occur during idle

and underrun conditions. WR11 is set so that the receive

clock is sourced by the DPLL output; the transmit clock is

sourced by the Baud Rate Generator output; /TRxC’s

output is from the BRG. The input to the BRG is from the

/RTxC.

The SCC is initially reset through software before

proceeding to program the other write registers. A NOP is

sufficient to provide the four PCLKs required by the SCC

recovery time after a soft reset. The SCC is programmed

for SDLC mode. The receive, transmit and external

interrupts are all initially disabled during this initialization.

Each of these interrupt sources are enabled at their proper

times in the main program. The SCC is programmed to

include status information in the vector that it places on the

bus in response to an interrupt acknowledge cycle (see

Listing 4 of the SCC interrupt vector table for all the

possible sources).

The BRG’s time constant is loaded in WR13 and WR12 so

that the /RTxC’s 3.6864 MHz signal is divided by 16 in

order to obtain a 230.4 kHz signal for the transmitter clock.

WR14 makes certain that the DPLL is disabled before

choosing the clock source and operating mode. The DPLL

is enabled by issuing the Enter Search Mode in WR14.

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Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

TRANSMITTING A LLAP FRAME

Listing 2 shows the assembler code for subroutine txenq,

which sends an lapENQ frame on the line once the system

has determined that the line is quiet. Note that this routine

can easily be generalized to send any frame.

After the first data byte is transmitted, the txenq routine

sets the SCC to mark on idle so that the abort is sent when

the frame is over. This operation can be done any time

after the first data character has been placed in the

transmit buffer and before the trailing flag is shifted out.

Txenq asserts this mark on idle command after the first

character is placed in the transmit buffer so that LLAP has

control and that no issues of latency may arise (particularly

in designs using interrupt or DMA).

The first responsibility of txenq is to send the sync pulse

required by the CSMA/CA protocol. To do this, txenq sets

the /RTS pin active low, enabling the transmitter drivers,

and then sets it high again to disable them. In order to

satisfy the requirements of the CSMA/CA protocol, the

transmitter drivers must remain off for at least one bit time

(4.3 µsec) to guarantee that all the receivers see at least

one transition. Our routine satisfies this requirement

because the two ld instructions (7 T states each), the two

nop instructions (4 T states each) and the two “out”

instructions (11 T states each) required to set the /RTS line

high, take more than 4.3 µsec to execute on the 10 MHz

Z80181. The transmitter drivers must then remain off for at

least two bit times in order to ensure that all receivers lose

clock; again, the routine depends upon the time required

to execute the instructions before we turn the transmitter

drivers on again.

After the last data byte is written to the SCC, the transmit

routine must wait while the last data byte (the one that the

SCC had just sent to shifter), the two CRC bytes, one flag

byte and 12 to 18 bit times of marking are transmitted. This

total of 44 to 50 bit times is again timed by bittime. When

bittime indicates that enough time has elapsed, the

transmitter drivers are turned off.

Since our hardware includes connecting the output of the

baud rate generator to the input of counter/timer 1 on the

Z80181, that counter timer counts the bit times. The bit

time routine feeds an appropriate count value into the

counter and enables an interrupt routine to receive control

when the count expires. The interrupt routine ctc1int,

shown in Listing 4, sets the timeflag which the transmit

routine polls.

After sending the sync pulse and waiting the required

period of silence, txenq turns on the transmitter drivers to

send the frame. Now, the routine must wait while the SCC

sends out the leading flags. This takes 16 bit times, and

since the SCC does not tell when this has happened, the

transmit routine has no choice but to time this. Our routine

does this by calling bit time, which is discussed below.

Note that the call to bittime, the interrupt routine, the polling

code and the length of time it takes to write to the SCC

registers after a polling loop is exited, all take up a time that

can be a significant number of bits. In order to do these

timings accurately, calculate the number of PCLK cycles

required to execute these pieces of code and to adjust the

counter value that bittime requires. This adjustment is

dependent on the hardware configuration and on the exact

implementation details of the code.

When the two flags have been transmitted, the first data

byte is written to the data register of the SCC. Thereafter,

the routine polls the SCC status register, and when that

register shows the transmit buffer register is empty, the

routine sends the next data character. This polling method

can obviously be replaced by an interrupt routine that is

entered when the transmit buffer is empty or by setting up

the Z80181’s DMA to send characters on demand to the

SCC.

Note, incidentally, that software must put the entire frame

into the transmit register, including the addresses. The

SCC does not generate addresses even when set in WR6.

RECEIVING LLAP FRAMES

In the experiments, the interrupt routines were used to

receive characters and to handle special conditions when

the frame is complete. Listing 3 shows the interrupt

handlers that are entered when the SCC receives a

character and when the SCC interrupts for a special

condition (typically, end of frame). As with transmission, it

is obvious that we could receive characters by polling the

SCC (using up all available CPU cycles) or by using DMA

(using up very few). It is estimated that the recint routine

uses up about 1/3 of the available 34 µsec (4.3 µsec x 8-

bit times) cycles on a 10 MHz processor.

The recint routine moves each character as it is received

from the SCC to a memory buffer and increments the

buffer pointer. The frame’s data length is checked to make

certain that the maximum allowable frame size is not

exceeded.

The spcond interrupt handler checks the status of the SCC

to find out what has happened. The presence on an

overrun condition or a CRC error is flagged as a receive

frame error.

6-136

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

The second routine decrements the receiver buffer

interframe gap, which is 200 µsecs. This difficulty is even

greater than it might appear. The 200 µsec gap starts

when the frame is received; it ends when the leading flags

and destination address of the response are sent. Start

sending the response soon enough to allow sending two

leading flags (plus a possible leading flag fragment) and

the first data character, and to allow for the 3-bit delay in

the SCC shifter. Therefore, start sending early enough to

transmit 35 bits before the interframe gap expires, or about

70 µsecs after you receive the frame.

address by two to account for the two CRC bytes that are

read from the SCC before the special condition interrupt

occurs. Note that the SCC does not filter these CRC bytes,

nor does it filter the address byte. Everything received after

the leading flags and before the trailing flags appears in

the receive buffer.

1

One difficulty that arises in LLAP that was not addressed

here is that the receipt of a frame very often creates an

obligation to send a frame back to the sender within the

CONCLUSIONS

The problems of sending the sync pulses, the timing of

transmission packets, and the problems associated with

the reception of packets as defined by LLAP are handled

by the Z80181 and its peripherals. It was demonstrated

that LLAP frames can be transmitted and received by

using the straight forward polling method and by using

interrupt routines. In a much busier environment where the

processor cannot strictly be an LLAP engine, other

methods such as using DMA in a fully interrupt driven

environment must be used. It was also demonstrated that

severe CPU overhead is used in setting up the sync

pulses, timing out delays, etc., before each LLAP frame. A

modified SCC that transmits and receives special LLAP

frames helps in off loading some of this overhead, hence

freeing the CPU to do other tasks.

6-137

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

APPENDIX A

Listing 1- Asembler Code for SCC Initialization

LISTING 1

475

;***************************************

476

477

;subroutine to initialize scc registers

;***************************************

000001e2

478 initscc:

479

480

481

482

000001e2 f3

000001e3 f5

000001e4 c5

000001e5 e5

di

;disable int while programming scc

push

af

bc

hl

483

000001e6 3e09

000001e8 d3e8

000001ea 3e80

000001ec d3e8

000001ee 00

484

485

486

487

ld

out

ld

out

nop

a,09h

(scc_cont),a

a,80h

;WR9

;point to scc register

;channel reset

;scc register value

;delay needed after scc reset

(scc_cont),a

488

489

490

000001ef 21Wwww

000001f2

000001f2 7e

491

492 scc1:

493

494

495

496

497

498

ld

hl,scctable

;fetch start of scc init table

ld

cp

jp

out

inc

ld

a,(hl)

0ffh

z,ﬁnscc

(scc_cont),a

hl

;fetch register pointer value

;if reg a =0ffh then initscc ﬁnished

000001f3 feff

000001f5 caWwww

000001f8 d3e8

000001fa 23

000001fb 7e

a,(hl)

000001fc d3e8

000001fe 23

000001ff c3R000+01f2,

499

500

501

out

inc

jp

(scc_cont),a

hl

scc1

;loop back

502

00000202

00000202 04

00000203 20

503 scctable:

504

505

db

04h

00100000b

;WR4

;sdlc uses 1x,sdlc mode,no parity

506

00000204 01

00000205 00

507

508

db

01h

00h

;WR1

;nothing,rx,tx and ext int disabled

509

00000206 02

00000207 00

510

511

db

02h

00h

;WR2

;vector base is 00h

512

00000208 03

00000209 cc

513

514

515

516

db

03h

0cch

;WR3

;rx 8b/char,rx crc enabled,address

;search mode for adlc address ﬁltering

;rx disabled.

517

0000020a 05

0000020b 60

518

519

db

05h

60h

;WR5

;tx 8b/char, set rts to disable drivers

520

0000020c 06

0000020d 00

521

522

db

06h

00h

;WR6

;address ﬁeld=’myaddress’ in main pgm

523

0000020e 07

0000020f 7e

524

525

db

07h

7eh

;WR7

;ﬂag pattern

526

00000210 09

00000211 01

527

528

529

530

db

09h

01h

;WR9

;stat low, vis therefore vector returned

;is a variable depending on the source

;of the interrupt.

531

6-138

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

00000212 0a

00000213 e0

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580 ﬁnscc:

581

582

583

584

585

db

0ah

0e0h

;WR10

;crc preset to one,fm0, ﬂag idle/undr

00000214 0b

00000215 f6

db

0bh

0f6h

;WR11

1

;rtxc=xtal,rxc=dpll,txc=brg,trxc=brg out

00000216 0c

00000217 06

db

0ch

06h

;WR12

;brg tc low,for 230.4kbps using rtxc=3.68MHz

00000218 0d

00000219 00

db

0dh

00h

;WR13

;brg tc high

0000021a 0e

0000021b 60

db

0eh

60h

;WR14

;disable dpll

;no local loop back,brg source=rtxc

0000021c 0e

0000021d c0

db

0eh

0c0h

;WR14

;select fm mode

;no local loop back,brg source=rtxc

0000021e 0e

0000021f a0

db

0eh

0a0h

;WR14

;dpll source=rtxc,

;no local loop back,brg source=rtxc

00000220 0e

00000221 20

db

0eh

20h

;WR14

;enter search mode

;no local loopback

00000222 0e

00000223 01

db

0eh

01h

;WR14

;null,no local loopback,enable the brg

00000224 03

00000225 cc

db

03h

0cch

;WR3

;rx 8b/c,enable rx crc,addrs src,rx disable

00000226 0f

00000227 00

db

0fh

00h

;WR15

;ext/stat not used

;WR0

;reset ext/stat once

;reset ext/stat twice

00000228 10

00000229 10

db

10h

0000022a 01

0000022b 00

db

01h

00h

;WR1

;disable all int sources

0000022c 09

0000022d 09

0000022e ff

db

09h

0ffh

;WR9

;enable int

;ﬁnished

0000022f

0000022f e1

00000230 c1

00000231 f1

00000232 c9

pop

ret

hl

bc

af

;

6-139

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

LISTING 2

600

601

602

603 txenq:

604

605

606

607

608

609

610

611

612

613

614

615

616

617

618

619

620

621

622

623

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

640

641

642

643

644

645

646

647

648

649

650

651

652

653 csloop:

654

655

656

657

658

659

;*************************************************

;Subroutine to transmit the llapenq packet

;*************************************************

00000244

00000244 f5

00000245 c5

00000246 e5

push

af

bc

hl

;save status and a reg

;save

;

00000247 f3

di

;make sure that

;no interrupt routine

;nor should interrupt

;occur during

;this subroutine.

00000248 3e03

0000024a d3e8

0000024c 3ecc

0000024e d3e8

ld

out

ld

a,03h

(scc_cont),a

a,0cch

;WR3

out

(scc_cont),a

;8b/char,rx crc

;enable,addrs src

;and rx disabled

00000250 3e0a

00000252 d3e8

00000254 3ee0

00000256 d3e8

ld

out

ld

a,0ah

;select WR10

;idle with ﬂags

(scc_cont),a

a,11100000b

(scc_cont),a

out

;****enable transmitter *****

;select WR5

00000258 3e05

0000025a d3e8

0000025c 3e68

0000025e d3e8

ld

out

ld

a,05h

(scc_cont),a

a,01101000b

(scc_cont),a

;enable tx

out

;

;****enable rs-422 driver *****

;select WR5

00000260 3e05

00000262 d3e8

00000264 3e6a

00000266 d3e8

00000268 00

ld

out

ld

a,05h

(scc_cont),a

a,01101010b

(scc_cont),a

nop

;enable tx,

;reset rts

out

00000269 00

nop

;nop’s needed to complete 4.3 usec

;for 1 bit time enable of transmitter.

;total delay=2*(7+11+4) T states at 10 MHZ

;

;****disable rs-422 driver for 2 bit times*****

;select WR5

0000026a 3e05

0000026c d3e8

0000026e 3e68

00000270 d3e8

ld

out

ld

a,05h

(scc_cont),a

a,01101000b

(scc_cont),a

;enable tx, set rts

out

;

00000272 3e80

00000274 d3e8

00000276 0601

00000278

ld

out

ld

a,10000000b

(scc_cont),a

b,01h

;reset txcrc

;delay count

00000278 10fe

djnz

ld

csloop

;loop needed

;to complete

;8.6 usec min.

;or 2 bit times.

;****enable rs-422 driver for llap transmission*****

;select WR5

0000027a 3e05

6-140

a,05h

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

0000027c d3e8

0000027e 3e6b

660

661

662

663

664

665

666

667

668

669

670

671

672

673

674

675

676

677

678

679

680

681

out

ld

(scc_cont),a

a,01101011b

;sdlc crc,

;txcrc enable,

;reset rts

1

00000280 d3e8

out

(scc_cont),a

;

;**start counting out 2 ﬂag character times **

;

;count 16 bit times

;from the rs-422 enable

;for 2 ﬂags.

;btdelay=subr delay+ctc1int+polling=8bits

;16 bit times-btdelay=16-8=08h

;

00000282 0e08

00000284 cdWwww

ld

call

c,08h

bittime

;bittime delay

;is stored in reg.c

;and bit1 of timﬂg

;will indicate

;count termination.

00000287682 l6:

00000287 3aWwww

0000028a cb4f

;timer ﬂag

;

;if bit1=1 then

;count terminated

683

684

685

686

687

688

689

690

691

692

693

694

695

696

697

698

699

700

701

702

703

704

705

706

707

708

709

710

711

712 txq2:

713

714

715

716

ld

bit

a,(timﬂg)

1,a

0000028c 28f9

0000028e cb8f

00000290 32Wwww

jr

res

ld

z,l6

1,a

(timﬂg),a

;

;reset timﬂg bit1

;update timﬂg

;

00000293 3e03

00000295 d3e5

ld

out

a,03h

(ctc1_cont),a

;disable int,

;software reset

;to kill the counter1

;2+1 bytes to transmitted

;point to txlapenq buffer

;send 1st byte

;

;and send it

;point to the next byte

;

00000297 0602

00000299 21Wwww

ld

b,02h

hl,txlapenq

0000029c 7e

0000029d d3e9

0000029f 23

ld

out

inc

a,(hl)

(scc_data),a

hl

000002a0 3ec0

000002a2 d3e8

ld

out

a,0c0h

(scc_cont),a

;reset eom latch command

;

000002a4 f3

000002a5 3e0a

000002a7 d3e8

di

ld

out

;disable all int

;select WR10

a,0ah

(scc_cont),a

;idle with 1’s

;at the end of the frame

000002a9 3ee8

000002ab d3e8

ld

out

a,11101000b

(scc_cont),a

;

000002ad 3e00

000002af d3e8

000002b1 dbe8

000002b3 cb57

000002b5 28f6

000002b7717 txq1:

000002b7 7e

ld

out

in

bit

jr

a,00h

(scc_cont),a

a,(scc_cont)

2,a

;rr0

;read rr0

;read tx buffer empty

;loop if zero

z,txq2

718

719

720

721

ld

out

inc

a,(hl)

(scc_data),a

hl

;

000002b8 d3e9

000002ba 23

;and send it

;point to the next byte

6-141

UM010901-0601

000002bb 10f0

722

723

724

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

djnz

txq2

;loop until all

;bytes have been

;transmitted.

000002bd 3e28

000002bf d3e8

ld

out

a,028h

(scc_cont),a

;reset tx int pending

;note:tx buffer

;empty happens as tx

;shifter is loaded.

;

;count= last byte+

;crc+ﬂag+12bit times-btdelay

;btdelay=subr delay+ctc1int+polling=8bits

;8+16+8+12-8=36=24h

000002c1 0e24

000002c3 cdWwww

ld

call

c,24h

bittime

;bittime delay

;is stored in reg.c

;

000002c6741 l7:

000002c6 3aWwww

000002c9 cb4f

000002cb 28f9

000002cd cb8f

;timer ﬂag

;

;if bit1=1 then count ﬁnish

;

;reset timﬂg bit1

;update timﬂg

;

;disable int,software reset

;to kill counter

;****disable rs-422 driver after 12 to 18 1’s*****

;select WR5

742

743

744

745

746

747

748

749

750

751

752

753

754

755

756

757

758

759

760

761

762

763

764

765

766

767

768

769

770

771

772

773

774

775

776

777

778

779

780

781

782

783

ld

bit

jr

res

ld

a,(timﬂg)

1,a

z,l7

1,a

(timﬂg),a

000002cf 32Wwww

000002d2 3e03

000002d4 d3e5

ld

out

a,03h

(ctc1_cont),a

000002d6 3e05

000002d8 d3e8

000002da 3e60

000002dc d3e8

ld

out

ld

a,05h

(scc_cont),a

a,01100000b

(scc_cont),a

;disable tx, set rts

;WR3

out

000002de 3e03

000002e0 d3e8

000002e2 3ecd

000002e4 d3e8

ld

out

ld

a,03h

(scc_cont),a

a,0cdh

out

(scc_cont),a

;8b/char,rx crc enabled,

;address search and rx enabled

;*************************************

;count for the interframe gap

;of 200 usec or 46 bit times.

;btdelay=subr delay+ctc1int+polling=8bits

;46 - btdelay=46-8=26h

;note that timﬂg will be polled in

;the main routine.

;

000002e6 0e26

000002e8 cdWwww

ld

call

c,26h

bittime

;

;bittime delay is stored in reg.c

;*************************************

;restore

;restore status and a reg

000002eb e1

000002ec c1

000002ed f1

000002ee c9

pop

pop bc

pop

hl

af

ret

13-142

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

784

785

;subroutine to time out bit time 4.3 usec per bit

;register c contains the number of bits to be

counted down

786

;**********************************************

1

000002ef

787 bittime:

788

789

790

791

792

793

794

795

796

797

798

799

800

801

802

803

804

805

806

807

808

809

000002ef f5

000002f0 c5

000002f1 e5

push

af

bc

hl

;save status and a reg

;save

;

000002f2 3ed2

000002f4 d3e5

ld

out

a,0d2h

(ctc1_cont),a

;ctc1 int vector

000002f6 3edf

000002f8 d3e5

ld

out

a,11011111b

(ctc1_cont),a

;

;enable int

;select counter mode

;clk/trg edge starts with rising edg

;time constant follows

;software reset

;reg c contains the number of bits

;load the number of bits to be counted

;**

;restore

;restate status and a reg

000002fa 79

000002fb d3e5

ld

out

a,c

(ctc1_cont),a

000002fd e1

000002fe c1

000002ff f1

00000300 fb

00000301 c9

pop

ei

hl

bc

af

ret

6-143

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

LISTING 3

1131

1132

1133

1134

1135

1136

1137recint:

1138

1139

1140

1141

1142

1143

1144

1145

1146

1147

1148

1149

;******************************

;receive int service routine.

;******************************

;save received character in receiver buffer

;to by rxpointer

0000044d

0000044d f5

0000044e d5

0000044f e5

00000450 dbe9

00000452 2aWwww

00000455 77

push

in

ld

inc

ld

xor

sbc

jp

af

de

hl

;save af

a,(scc_data)

hl,(rxpointer)

(hl),a

;read scc data

;

;save it

;update pointer

00000456 23

hl

00000457 22Www

0000045a ed5bWwww

0000045e af

0000045f ed52

00000461 c2Wwww

(rxpointer),hl

de,(rxbufend)

a

hl,de

nz,recexit

;

;end of rx buffer

;reset cy

;

;if not zero,then receive

byte length is ok

00000464 21Wwww

00000467 cbc6

1150

1151

1152

ld

set

hl,recerrﬂg

0,(hl)

;

;set bit0=1 maxfrmﬂg to indicate error

;because of max frame

size exceeded.

00000469

1153recexit:

1154

1155

1156

1157

00000469 3e38

0000046b d3e8

0000046d e1

0000046e d1

0000046f f1

ld

a,038h

out

pop

ei

(scc_cont),a

hl

de

af

;reset highest ius

1158

;restore af

;enable int

;return from int

00000470 fb

00000471 c9

1159

1160

ret

1161

1162

;note ret and not reti is used for scc

;interrupts on the z80181.

1163

1164

1165

1166

1167;

1168;

1169;

1170;

1171

;*********************************************

;special receive interrupt service routine

;*********************************************

“parity is special condition” bit is off.

special conditions are eof or rx overrun error.

crc error ﬂag is valid only if eof is valid.

if frame is ok then recerrﬂg bit1=0, otherwise

00000472

1172 spcond:

1173

1174

00000472 f5

00000473 c5

00000474 e5

push

af

bc

hl;

;save af reg

;

1175

1176

00000475 3e01

00000477 d3e8

00000479 dbe8

0000047b e660

0000047d caWwww

1177

1178

1179

1180

ld

out

in

and

jp

a,01h

(scc_cont),a

a,(scc_cont)

01100000b

z,ok

;read rr1

;check bit6 (crc) or bit5 (overrun)

;

1181

1182

;

00000480 21Wwww

00000483 cbce

00000485 c3Wwww

1183

1184

1185

ld

set

jp

hl,recerrﬂg

1,(hl)

crc_exit

;fetch receive error ﬂag

;set bit1=1 for frame not ok

6-144

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

00000488

1186

ok:

00000488 21Wwww

0000048b cb8

1187

1188

ld

res

hl,recerrﬂg

1,(hl)

;fetch receive error ﬂag

;set bit1=0 for frame ok

1189

1190

1191 crc_exit:

1192

1193

1194

1195

1196

1

0000048d

0000048d dbe9

0000048f 2aWwww

00000492 2b

00000493 2b

00000494 22Wwww

in

ld

dec

ld

a,(scc_data)

hl,(rxpointer)

hl

;read 2nd crc (debug only) and

;load pointer

;adjust rx buff ptr for crc1

;adjust rx buff ptr for crc2

;

hl

(rxpointer),hl

1197

00000497

00000497 3e38

00000499 d3e8

1198 spexit:

1199

1200

ld

a,038h

out

(scc_cont),a

;reset highest ius

1201

0000049b e1

0000049c c1

0000049d f1

0000049e fb

0000049f c9

1202

1203

1204

1205

pop

ei

hl

bc

af

;restore hl

;restore be

;restore af

;enable int

;return from int

1206

ret

1207

6-145

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

LISTING 4

1306

1307

1308

1309

1310 ctc1int:

1311

1312

1313

1314

1315

1316

1317

1318

1319

1320

1321

1322

1323

1324

1325

1326

1327

1328

1329

1330

1331

1332

1333

1334

1335

1336

1337

1338 sccvect:

1339

1340

1341

1342

1343

1344

1345

1346

1347

1348

1349

1350

1351 temp:

1352

1353

1354

1355

1356

1357

1358

1359

1360

1361

1362

1363

1364

;****************************************

;ctc1 timer int handler

;****************************************

00000509

;ctc1 is programmed in counter mode.

;external trigger edges is provided by

;/trxc pin at intervals of 4.3 usec.

;bit1 of timﬂg is set when count is terminated.

00000509 f5

0000050a c5

0000050b e5

push

af

bc

hl

;** update the timing ﬂag **

0000050c 21Wwww

0000050f 7e

ld

hl,timﬂg

a,(hl)

1,a

(hl),a

hl

;get recent timﬂg

;bit1=1 after count is over

;update the timﬂg

00000510 cbcf

00000512 77

00000513 e1

00000514 c1

00000515 f1

set

ld

pop

ei

bc

af

00000516 fb

00000517 ed4d

reti

;**********************************

;interrupt vector table for the scc

;**********************************

;the status of the interrupt source will affect

;the interrupt vector. The interrupt handler’s

;address are set in a block, as below.

00000a00

org

sdlc + 0a00h

if

scc_a

8

00000a00

.block

endif

dw

;reserve vector for other ch

00000a08 R000+03e9,

00000a0a R000+04c8,

00000a0c R000+0433,

00000a0e R000+0454,

txint

ext_stat

recint

;tx int

;ext/stat int

;rx char int

;sp rec cond int

dw

spcond

if

not scc_a

8

00000a10

00000a18

.block

endif

;reserve vector for other ch

.block

1

;**********************************

;interrupt vector table for the ctc

;**********************************

00000ad0

00000ad0 R000+04d8,

00000ad2

org

dw

org

dw

0ad0h

ctc0int

0ad2h

ctc1int

;reserved for ctc0 int routine

;reserved for ctc1 int routine

00000ad2 R000+0509,

;************************

;receive buffer area

;************************

6-146

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

00001000

1365

org

1000h

length

1366 rx_buff: .block

1367

1388

1389

1390

1391

1

;************************

;transmitter buffer area

;************************

0000b000

1392

1398

1399

1400

1401

org

0b000h

;

;********************************

;transmit llap enq packet (3bytes)

;********************************

;broadcast id

0000b258 ff

0000b259

1402 txlapenq:db

0ffh

1

1403

.block

;guess at myaddress

myaddress

1404

1405

0000b25a 81

db

81h

;llap enq type

;

6-147

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

APPENDIX B

12 to 18 1’s at the end of an LLAP frame

6-148

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

1

CSMA/CA before an LLAP frame

6-149

UM010901-0601

Application Note

Technical Considerations When Implementing LocalTalk Link Access Protocol

An LLAP Frame

6-150

UM010901-0601

APPLICATION NOTE

1

ON-CHIP OSCILLATOR DESIGN

14

esign and build reliable, cost-effective, on-chip oscillator circuits that are trouble free.

PUTTING OSCILLATOR THEORY INTO A PRACTICAL DESIGN MAKES FOR A

MORE DEPENDABLE CHIP.

D

INTRODUCTION

This Application Note (App Note) is written for designers

using Zilog Integrated Circuits with on-chip oscillators;

circuits in which the amplifier portion of a feedback

oscillator is contained on the IC. This App Note covers

common theory of oscillators, and requirements of the

circuitry (both internal and external to the IC) which comes

from the theory for crystal and ceramic resonator based

circuits.

1. Providing designers with greater understanding of how

oscillators work and how to design them to avoid

problems.

2. To eliminate field failures and other complications

resulting from an unawareness of critical on-chip

oscillator design constraints and requirements.

Problem Background

Purpose and Benefits

Inadequate understanding of the theory and practice of

oscillator circuit design, especially concerning oscillator

startup, has resulted in an unreliable design and

subsequent field problems (See on page 10 for reference

materials and acknowledgments).

The purposes and benefits of this App Note include:

OSCILLATOR THEORY OF OPERATION

The circuit under discussion is called the Pierce Oscillator

(Figures 1, 2). The configuration used is in all Zilog on-chip

oscillators. Advantages of this circuit are low power

consumption, low cost, large output signal, low power level

drawback is the need for high gain in the amplifier to

compensate for feedback path losses.

in the crystal, stability with respect to V and temperature,

and low impedances (not disturbed by stray effects). One

CC

V

i

o

A

B

Figure 1. Basic Circuit and Loop Gain

6-151

UM010901-0601

Application Note

On-Chip Oscillator Design

OSCILLATOR THEORY OF OPERATION (Continued)

Additionally, these gain and phase characteristics of both

the amplifier and the feedback element vary with

frequency. Thus, the above relationships must apply at the

frequency of interest. Also, in this circuit the amplifier is an

active element and the feedback element is passive. Thus,

by definition, the gain of the amplifier at frequency must be

greater than unity, if the loop gain is to be unity.

IC

A

The described oscillator amplifies its own noise at startup

until it settles at the frequency which satisfies the

gain/phase requirement AB = 1. This means loop gain

equals one, and loop phase equals zero (360 degrees). To

do this, the loop gain at points around the frequency of

oscillation must be greater than one. This achieves an

average loop gain of one at the operating frequency.

XTAL

C1

C2

The amplifier portion of the oscillator provides gain > 1 plus

180 degrees of phase shift. The feedback element

provides the additional 180 degrees of phase shift without

attenuating the loop gain to < 1. To do this the feedback

element is inductive, i.e., it must have a positive reactance

at the frequency of operation. The feedback elements

discussed are quartz crystals and ceramic resonators.

Figure 2. Zilog Pierce Oscillator

Pierce Oscillator (Feedback Type)

The basic circuit and loop gain is shown in Figure 1. The

concept is straightforward; gain of the amplifier is

A = Vo/Vi. The gain of the passive feedback element is

B = Vi/Vo. Combining these equations gives the equality

AB = 1. Therefore, the total gain around the loop is unity.

Also, since the gain factors A and B are complex numbers,

they have phase characteristics. It is clear that the total

phase shift around the loop is forced to zero (i.e., 360

Quartz Crystals

A quartz crystal is a piezoelectric device; one which

transforms electrical energy to mechanical energy and

vice versa. The transformation occurs at the resonant

frequency of the crystal. This happens when the applied

AC electric field is sympathetic in frequency with the

mechanical resonance of the slice of quartz. Since this

characteristic can be made very accurate, quartz crystals

are normally used where frequency stability is critical.

Typical frequency tolerance is .005 to 0.3%.

degrees), since V must be in phase with itself. In this

IN

circuit, the amplifier ideally provides 180 degrees of phase

shift (since it is an inverter). Hence, the feedback element

is forced to provide the other 180 degrees of phase shift.

The advantage of a quartz crystal in this application is its

wide range of positive reactance values (i.e., it looks

inductive) over a narrow range of frequencies (Figure 3).

6-152

UM010901-0601

Application Note

On-Chip Oscillator Design

Z

1

Region of Parallel

Operation

INDUCTIVE

0

fs fp*

2

CAPACITIVE

* fs - fp is very small (approximately 300 parts per million)

Figure 3. Series vs. Parallel Resonance

However, there are several ranges of frequencies where

Fs = 1/(2π x sqrt of LC),

the reactance is positive; these are the fundamental

(desired frequency of operation), and the third and fifth

mechanical overtones (approximately 3 and 5 times the

fundamental frequency). Since the desired frequency

range in this application is always the fundamental, the

overtones must be suppressed. This is done by reducing

the loop gain at these frequencies. Usually, the amplifier’s

gain roll off, in combination with the crystal parasitics and

load capacitors, is sufficient to reduce gain and prevent

oscillation at the overtone frequencies.

where Xc and Xl are equal.

Thus, they cancel each other and the crystal is then R

shunted by Cs with zero phase shift.

The parallel resonant frequency is given by:

Fp = 1/[2π x sqrt of L (C Ct/C+Ct)],

where: Ct = C + C

L

S

Cs

L

The following parameters are for an equivalent circuit of a

quartz crystal (Figure 4):

L - motional inductance (typ 120 mH @ 4 MHz)

C - motional capacitance (typ .01 pf @ 4 MHz)

R - motional resistance (typ 36 ohm @ 4 MHz)

R

C

Quartz Equivalent Circuit

Cs - shunt capacitance resulting from the sum of the

capacitor formed by the electrodes (with the quartz as a

dielectric) and the parasitics of the contact wires and

holder (typ 3 pf @ 4 MHz).

Symbolic Representation

The series resonant frequency is given by:

Figure 4. Quartz Oscillator

6-153

UM010901-0601

Application Note

On-Chip Oscillator Design

OSCILLATOR THEORY OF OPERATION (Continued)

Series vs. Parallel Resonance. There is very little

Ceramic Resonators

difference between series and parallel resonance

frequencies (Figure 3). series resonant crystal

Ceramic resonators are similar to quartz crystals, but are

used where frequency stability is less critical and low cost

is desired. They operate on the same basic principle as

quartz crystals as they are piezoelectric devices and have

a similar equivalent circuit. The frequency tolerance is

wider (0.3 to 3%), but the ceramic costs less than quartz.

Figure 5 shows reactance vs. frequency and Figure 6

shows the equivalent circuit.

A

(operating at zero phase shift) is desired for non-inverting

amplifiers. A parallel resonant crystal (operating at or near

180 degrees of phase shift) is desired for inverting amps.

Figure 3 shows that the difference between these two

operating modes is small. Actually, all crystals have

operating points in both serial and parallel modes. A series

resonant circuit will NOT have load caps C1 and C2. A

data sheet for a crystal designed for series operation does

not have a load cap spec. A parallel resonant crystal data

sheet specifies a load cap value which is the series

combination of C1 and C2. For this App Note discussion,

since all the circuits of interest are inverting amplifier

based, only the parallel mode of operation is considered.

Typical values of parameters are L = .092 mH, C = 4.6 pf,

R = 7 ohms and Cs = 40 pf, all at 8 MHz. Generally,

ceramic resonators tend to start up faster but have looser

frequency tolerance than quartz. This means that external

circuit parameters are more critical with resonators.

Impedance100000

(Ohm

10000

1000

100

10

1

0

2000

4000

6000

8000

10000

Frequency (KHz)

Figure 5. Ceramic Resonator Reactance

6-154

UM010901-0601

Application Note

On-Chip Oscillator Design

Power

Supply

1

RTxCB (SCC)

EXTAL (Z180)

SYNCB (SCC)

Vcc

Gnd

XTAL (Z180)

I.C.

Under Test

(All Unused

470 pf

22 pf

Probe (in)

Inputs: 10kΩ To Vcc)

Frequency

Generator

1V P-P/Sine

Probe

(out)

Figure 6. Gain Measurement

Open Loop Gain vs. Frequency over lot, VCC, Process

Split, and Temp. Closed loop gain must be adequate to

start the oscillator and keep it running at the desired

frequency. This means that the amplifier open loop gain

must be equal to one plus the gain required to overcome

the losses in the feedback path, across the frequency band

and up to the frequency of operation. This is over full

Load Capacitors

The effects/purposes of the load caps are:

Cap C2 combined with the amp output resistance provides

a small phase shift. It also provides some attenuation of

overtones.

process, lot, V , and temperature ranges. Therefore,

Cap C1 combined with the crystal resistance provides

additional phase shift.

CC

measuring the open loop gain is not sufficient; the losses

in the feedback path (crystal and load caps) must be

factored in.

These two phase shifts place the crystal in the parallel

resonant region of Figure 3.

Open Loop Phase vs. Frequency. Amplifier phase shift at

and near the frequency of interest must be 180 degrees plus

some, minus zero. The parallel configuration allows for

some phase delay in the amplifier. The crystal adjusts to this

by moving slightly down the reactance curve (Figure 3).

Crystal manufacturers specify a load capacitance number.

This number is the load seen by the crystal which is the

series combination of C1 and C2, including all parasitics

(PCB and holder). This load is specified for crystals meant

to be used in a parallel resonant configuration. The effect

on startup time; if C1 and C2 increase, startup time

increases to the point at which the oscillator will not start.

Hence, for fast and reliable startup, over manufacture of

large quantities, the load caps should be sized as low as

possible without resulting in overtone operation.

Internal Bias. Internal to the IC, there is a resistor placed

from output to input of the amplifier. The purpose of this

feedback is to bias the amplifier in its linear region and to

provide the startup transition. Typical values are 1M to

20M ohms.

Amplifier Characteristics

The following text discusses open loop gain vs. frequency,

open loop phase vs. frequency, and internal bias.

6-155

UM010901-0601

Application Note

On-Chip Oscillator Design

PRACTICE: CIRCUIT ELEMENT AND LAY OUT CONSIDERATIONS

The discussion now applies prior theory to the practical

application.

Gain Measurement Circuit. The gain of the amplifier can

be measured using the circuits of Figures 6 & 7. This may

be necessary to verify adequate gain at the frequency of

interest and in determining design margin.

Amplifier and Feedback Resistor

The elements of the circuit, internal to the IC, include the

amplifier, feedback resistor, and output resistance. The

amplifier is modeled as a transconductance amplifier with

Gain Requirement vs. Temperature, Frequency and

Supply Voltage. The gain to start and sustain oscillation

(Figure 8) must comply with:

a gain specified as I

/V (amps per volt).

OUT IN

2 2

gm > 4π f Rq C

C

t x M

IN OUT

Transconductance/Gain. The loop gain AB = gm x Z1,

where gm is amplifier transconductance (gain) in

amps/volt and Z1 is the load seen by the output. AB must

be greater than unity at and about the frequency of

operation to sustain oscillation.

where:

M is a quartz form factor = (1 + C

/C + C

/C )

OUT IN

OUT OUT 2

Output Impedance. The output impedance limits power to

the XTAL and provides small phase shift with load cap C2.

IC Under Test

33Ω

DC Bias

V

b

V

in

out

I

= (V

out

– V ) /33)

out

b

Figure 7. Transconductance (gm) Measurement

Amplifier

*

VIN

OSC IN

VOUT

OSC OUT

Quartz

Rq, f

COUT

CIN

**

*

Inside chip, feedback resistor biases the amplifier in the high gm region.

**_{External components typically: CIN = COUT = 30 to 50 pf (add 10 pf pin cap).}

Figure 8. Quartz Oscillator Conﬁguration

6-156

UM010901-0601

Application Note

On-Chip Oscillator Design

Frequency Tolerance (initial temperature and aging).

Initial tolerance is typically ±.01%. Temperature tolerance

is typically ±.005% over the temp range (-30 to +100

degrees C). Aging tolerance is also given, typically

±.005%.

Load Capacitors

In the selection of load caps it is understood that parasitics

are always included.

1

Upper Limits. If the load caps are too large, the oscillator

will not start because the loop gain is too low at the

operating frequency. This is due to the impedance of the

load capacitors. Larger load caps produce a longer

startup.

Holder. Typical holder part numbers are HC6, 18,

25, 33, 44.

Shunt Capacitance. (Cs) typically <7 pf.

Lower Limits. If the load caps are too small, either the

oscillator will not start (due to inadequate phase shift

around the loop), or it will run at a 3rd, 5th, or 7th overtone

frequency (due to inadequate suppression of higher

overtones).

Mode. Typically the mode (fundamental, 3rd or 5th

overtone) is specified as well as the loading configuration

(series vs. parallel).

The ceramic resonator equivalent circuit is the same as

shown in Figure 4. The values differ from those specified

in the theory section. Note that the ratio of L/C is much

lower than with quartz crystals. This gives a lower Q which

allows a faster startup and looser frequency tolerance

(typically ±0.9% over time and temperature) than quartz.

Capacitor Type and Tolerance. Ceramic caps of ±10%

tolerance should be adequate for most applications.

Ceramic vs. Quartz. Manufacturers of ceramic resonators

generally specify larger load cap values than quartz crystals.

Quartz C is typically 15 to 30 pF and ceramic typically 100 pF.

Layout

Summary. For reliable and fast startup, capacitors should

be as small as possible without resulting in overtone

operation. The selection of these capacitors is critical and

all of the factors covered in this note should be considered.

The following text explains trace layout as it affects the

various stray capacitance parameters (Figure 9).

Traces and Placement. Traces connecting crystal, caps,

and the IC oscillator pins should be as short and wide as

possible (this helps reduce parasitic inductance and

resistance). Therefore, the components (caps and crystal)

should be placed as close to the oscillator pins of the IC as

possible.

Feedback Element

The following text describes the specific parameters of a

typical crystal:

Drive Level. There is no problem at frequencies greater

Grounding/Guarding. The traces from the oscillator pins

of the IC should be guarded from all other traces (clock,

than 1 MHz and V

= 5V since high frequency AT cut

CC

crystals are designed for relatively high drive levels (5-10

mw max).

V

, address/data lines) to reduce crosstalk. This is

CC

usually accomplished by keeping other traces away from

the oscillator circuit and by placing a ground ring around

the traces/components (Figure 9).

A typical calculation for the approximate power dissipated

in a crystal is:

Measurement and Observation

P = 2R (π x f x C x V

)

CC 2

Connection of a scope to either of the circuit nodes is likely

to affect operation because the scope adds 3-30 pF of

capacitance and 1M-10M ohms of resistance to the circuit.

Where. R = crystal resistance of 40 ohms, C = C1 + Co =

20 pF. The calculation gives a power dissipation of 2 mW

at 16 MHz.

Indications of an Unreliable Design

Series Resistance. Lower series resistance gives better

performance but costs more. Higher R results in more

power dissipation and longer startup, but can be

compensated by reduced C1 and C2. This value ranges

from 200 ohms at 1 MHz down to 15 ohms at 20 MHz.

There are two major indicators which are used in working

designs to determine their reliability over full lot and

temperature variations. They are:

Start Up Time. If start up time is excessive, or varies

widely from unit to unit, there is probably a gain problem.

C1/C2 needs to be reduced; the amplifier gain is not

adequate at frequency, or crystal Rs is too large.

Frequency. The frequency of oscillation in parallel

resonant circuits is mostly determined by the crystal

(99.5%). The external components have a negligible effect

(0.5%) on frequency. The external components (C1,C2)

and layout are chosen primarily for good startup and

reliability reasons.

6-157

UM010901-0601

Application Note

On-Chip Oscillator Design

PRACTICE: CIRCUIT ELEMENT AND LAY OUT CONSIDERATIONS (Continued)

Output Level. The signal at the amplifier output should

loop gain is effectively reduced to unity and constant

swing from ground to V . This indicates there is adequate

gain in the amplifier. As the oscillator starts up, the signal

amplitude grows until clipping occurs, at which point, the

oscillation is achieved. A signal of less than 2.5 Vp-p is an

indication that low gain may be a problem. Either C1/C2

should be made smaller or a low R crystal should be used.

CC

Signal Line

XTAL

Layout Should

Avoid High

Lighted Areas

20 mm

max

2

3

64

C

L

Z80180

GND

20 mm max

EXTAL

L

64

1

CLK

Clock Generator Circuit

2

3

Signals A B

Z80180

(Parallel Traces

Must Be Avoided)

Signal C

Board Design Example

(Top View)

2

3

64

To prevent induced noice, the crystal and load

capacitors should be physically located as

close to the LSI as possible.

●

Z80180

● Signal lines should not run parallel to the clock

oscillator inputs. In particullar, the clock input

circuitry and the system clock output (pin 64)

should be separated as much as possible.

V

power lines should be separated from the

●

cc

clock oscillator input circuitry.

● Resistivity between XTAL or EXTAL and the

other pin should be greater than 10 MΩ

Figure 9. Circuit Board Design Rules

6-158

UM010901-0601

Application Note

On-Chip Oscillator Design

SUMMARY

Understanding the Theory of Operation of oscillators,

combined with practical applications, should give

designers enough information to design reliable oscillator

circuits. Proper selection of crystals and load capacitors,

along with good layout practices, results in a cost effective,

trouble free design.Reference the following text for Zilog

products with on-chip oscillators and their general/

specific requirements.

1

ZILOG PRODUCT USING ON-CHIP OSCILLATORS

®

Zilog products that have on-chip oscillators:

Z8000 : 8581

Communications Products: SCC , ISCC , ESCC

™

®

Z8 Family: All

®

Z80 : C01, C11, C13, C15, C50, C90, 180, 181, 280

ZILOG CHIP PARAMETERS

The following are some recommendations on

Z8000 Family (8581 only)

values/parameters of components for use with Zilog on-

chip oscillators. These are only recommendations; no

guarantees are made by performance of components

outside of Zilog ICs. Finally, the values/parameters chosen

depend on the application. This App Note is meant as a

guideline to making these decisions. Selection of optimal

General Requirements:

Crystal cut: AT cut, parallel resonant, fundamental mode.

Crystal Co: < 7 pF for all frequencies.

Crystal Rs: < 150 ohms for all frequencies.

Load capacitance: 10 to 33 pF.

components is always

cost/performance tradeoffs.

a

function of desired

Z80 Family

General Requirements:

Note: All load capacitance specs include stray

capacitance.

Crystal cut: AT cut, parallel resonant, fundamental mode.

Crystal Co: < 7 pF for all frequencies.

Z8 Family

Crystal Rs: < 60 ohms for all frequencies.

Load capacitance: 10 to 22 pF.

General Requirements:

Specific Requirements:

Crystal Cut: AT cut, parallel resonant, fundamental mode

Crystal Co: < 7 pF for all frequencies.

Crystal Rs: < 100 ohms for all frequencies.

Load Capacitance: 10 to 22 pf, 15 pF typical.

84C01: C1 = 22 pF, C2 = 33 pF (typ); f = DC to 10 MHz.

84C90: DC to 8 MHz.

84C50: same as 84C01.

84C11/13/15: C1 = C2 = 20 -33 pf; f = 6 -10 MHz

80180: f = 12, 16, 20 MHz (Fxtal = 2 x sys. clock).

80280: f = 20 MHz (Fxtal = 2 x Fsysclk).

80181: TBD.

Specific Requirements:

8604: xtal or ceramic, f = 1 - 8 MHz.

8600/10: f = 8 MHz.

8601/03/11/13: f = 12.5 MHz.

8602: xtal or ceramic, f = 4 MHz.

8680/81/82/84/91: f = 8, 12, 16, MHz.

8671: f = 8 MHz.

8612: f = 12, 16 MHz.

86C08/E08: f = 8, 12 MHz.

86C09/19: xtal/resonator, f = 8 MHz, C = 47 pf max.

86C00/10/20/30: f = 8, 12, 16 MHz

86C11/21/91/40/90: f = 12, 16, 20 MHz.

86C27/97: f = 4, 8 MHz.

Communications Family

General Requirements:

Crystal cut: AT cut, parallel resonant, fundamental mode.

Crystal Co: < 7 pF for all frequencies.

Crystal Rs: < 150 ohms for all frequencies.

Load capacitance: 20 to 33 pF.

Frequency: cannot exceed PCLK.

Specific Requirements:

86C12: f = 12, 16 MHz.

Super8 (all): f = 1 - 20 MHz.

8530/85C30/SCC: f = 1 - 6 MHz (10 MHz SCC), 1 - 8.5

MHz (8 MHz SCC).

85130/ESCC (16/20 MHz), f = 1 - 16.384 MHz.

16C35/ISCC: f = 1 -10 MHz.

6-159

UM010901-0601

REFERENCES MATERIALS AND ACKNOWLEDGEMENTS

Intel Corp., Application Note AP-155, “Oscillators for Micro

Controllers”, order #230659-001, by Tom Williamson, Dec.

1986.

Zilog, Inc., Steve German; Figures 4 and 8.

Zilog, Inc., Application Note, “Design Considerations

Using Quartz Crystals with Zilog Components” - Oct. 1988.

Motorola 68HC11 Reference Manual.

Data Sheets; CTS Corp. Knights Div., Crystal Oscillators.

National Semiconductor Corp., App Notes 326 and 400.

14-160

UM010901-0601

APPLICATION NOTE

INTERFACING THE ISCC™ TO THE 68000 AND 8086

INTRODUCTION

The ISCC™ uses its flexible bus to interface with a variety

of microprocessors and microcontrollers; included are the

68000 and 8086.

including the bus types of the 680X0 and the 8086 families

of microprocessors.

This Application Note presents the details of BIU operation

for both slave peripheral and DMA modes. Included are

application examples of interconnecting an ISCC to a

68000 and a 8086 (These examples are currently under

test).

The Z16C35 ISCC is a Superintegration form of the

85C30/80C30 Serial Communications Controller (SCC).

Super integration includes four DMA channels, one for

each receiver and transmitter and a flexible Bus Interface

Unit (BIU). The BIU supports a wide variety of buses

ISCC BUS INTERFACE UNIT (BIU)

The following subsections describe and illustrate the

functions and parameters of the ISCC Bus Interface Unit.

registers access through an internal pointer which first

loads with the register address. Loading of the pointer is

done as a data write. In either case, there are some

external addressing signals.

Overview

The ISCC™ contains a flexible bus interface that is directly

compatible with a variety of microprocessors and

microcontrollers. The bus interface unit adds to the chip by

allowing ease of connection to several standard bus

configurations; among others are the 68000 and the 8086

family microprocessors. This compatibility is achieved by

initializing the ISCC after a reset to the desired bus

configuration.

Chip Enable (CE) allows external selection through the

decode of upper order address bits like accessing

separate chips. A separate input (not part of the AD15-

AD0 bus connection) selects between the internal SCC

and DMA sections of the chip. This input is A0/SCC/DMA

and provides direct transfers to the appropriate chip

subsystem; either multiplexed or non-multiplexed bus

mode.

The device also configures to work with a variety of other

8- or 16-bit bus systems and is used with address/data

multiplexed or non-multiplexed buses. In addition, the

wait/ready handshake, the interrupt acknowledge, and the

bus high byte/low byte selection are all programmable.

Separate read/write, data strobe, write, read, and address

strobe signals are available for direct system interface with

a minimum of external logic.

A second separate input (not part of the AD15-AD0 bus

connection) provides for a selection between the internal

SCC; both channels A and B (Table A-1). This input is

A1/A/B and provides direct transfers to the appropriate

SCC channel when A0/SCC/DMA selects the SCC; either

multiplexed or non-multiplexed bus mode. Note that these

two signals, A1/A/B and A0/SCC/DMA, are inputs when

Modes Description

There are basically two bus modes of operation:

multiplexed and non-multiplexed. In the multiplexed bus

mode, the ISCC internal registers are directly accessible

as separate registers with their own unique hardware

addresses. By contrast, in the non-multiplexed mode, all

6-1

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

ISCC BUS INTERFACE UNIT (BIU) (Continued)

the ISCC is a slave peripheral; they become outputs when

the ISCC is a bus master during DMA operations.

When the ISCC starts for non-multiplexed operation,

register addressing for the DMA section is (except for

CSAR) accomplished as follows. It is completely

independent of the SCC section register addressing.

Programming the write registers requires two write

operations and reading the read registers requires both a

write and a read operation. The first write is to the

Command Status Address Register (CSAR) which

contains five bits that point to the selected register (CSAR

bits 4-0). The second write is the actual control word for the

selected register. If the second operation is a read, the

selected register is accessed. The pointer bits

automatically clear after the second read or write operation

so CSAR addresses again. When in the non-multiplexed

mode, all registers in the DMA section of the ISCC are

accessed.

Table 1. Accessing the ISCC Registers

A0/SCC/DMA

A1/A/B

ACCESS

1

0

1

0

x

SCC Channel A

SCC Channel B

DMA

The following discussions assume knowledge of the SCC

Serial Communications Controller operations and refer to

internal register designations. For a detailed explanation,

refer to the SCC Technical Manual.

Non-Multiplexed Bus Operation

When the ISCC initializes for non-multiplexed operation,

Write Register 0 (WR0) takes on the form of WR0 in the

Z8530, Write Register Bit Functions (Figure A-1). Register

addressing for the SCC section is (except for WR0 and

RR0) accomplished as follows. Programming the write

registers requires two write operations. Reading the read

registers requires both a write and a read operation.

Multiplexed Bus Operation

When the ISCC initializes for multiplexed bus operation, all

registers in the SCC section are directly addressable with

the register address occupying AD5 through AD1 or AD4

through AD0 (Shift Left/Shift Right modes).

The Shift Left/Shift Right modes for the address decoding

of the internal registers (multiplexed bus) are separately

programmable for the SCC and DMA sections. For the

SCC section, the programming and operation is the same

as the SCC; programming occurs through Write Register 0

(WR0), bits 1 and 0 , and Write Register Bit Functions

(Figure A-2). The programming of the Shift Left/Shift Right

modes for the DMA section occurs in the BCR, bit 0. In this

case, the shift function is similar to the SCC section; with

Left Shift, the internal register addresses decode from bits

AD5 through AD1. In Right Shift, the internal register

addresses decode from bits AD4 through AD0.

The first write is to WR0 which contains three bits that point

to the selected register (note the point high command).

The second write is the actual control word for the selected

register. If the second operation is a read, the selected

register is accessed. When in the non-multiplexed mode,

all registers in the SCC section of the ISCC, including the

data registers, access this way.

The pointer register automatically clears after the second

read or write operation so WR0 (or RR0) addresses again.

There is no direct access to the data registers. They are

addressed through the pointer (this is in contrast to the

Z8530 which allows direct addressing of the data registers

through the C/D pin).

During multiplexed bus mode selection, Write Register 0

(WR0) becomes WR0 in the Z8030, Write Register Bit

Functions (Figure A-2).

6-2

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

Write Register 0 (non-multiplexed bus mode)

D7 D6

ster 0 (multiplexed bus mode)

5 D4 D3 D2 D1 D0

D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register 0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

Register 7

Register 8

Register 9

Register 10

Register 11

Register 12

Register 13

Register 14

Register 15

0

1

0

1

0

1

Null Code

Select Shift Left Mode

Select Shift Right Mode

*

0

1

0

1

0

1

0

1

0

1

0

1

Null Code

Reset Ext/Status Interrupts

Send Abort

Enable Int on Next Rx Character

Reset Tx Int Pending

Error Reset

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Null Code

Point High

Reset Highest IUS

Reset Ext/Status Interrupts

Send Abort (SDLC)

Enable Int on Next Rx Character

Reset Tx Int Pending

Error Reset

Null Code

Reset Rx CRC Checker

Reset Tx CRC Generator

Reset Tx Underrun/EOM Latch

Reset Highest IUS

0

1

0

1

0

1

Null Code

Reset Rx CRC Checker

Reset Tx CRC Generator

Reset Tx Underrun/EOM Latch

nnel Only

Figure 2. Write Register 0 Bit Functions

(Multiplexed Bus Mode)

* With Point High Command

Figure 1. Write Register 0 Bit Functions

(Non-Multiplexed Bus Mode)

BUS DATA TRANSFERS

ISCC^™DMA Bus Transfers

All data transfers to and from the ISCC™ are done in bytes

regardless of whether data occupies the lower or upper

byte of the 16-bit bus. Bus transfers as a slave peripheral

are done differently from bus transfers when the ISCC is

the bus master during DMA transactions. The ISCC is

fundamentally an 8-bit peripheral but supports 16-bit

buses in the DMA mode. Slave peripheral and DMA

transactions appear in the next sections.

During DMA transfers, when the ISCC is bus master, only

byte data transfers occur. However, data transfers to or

from the ISCC on the upper 8 bits of the bus or on the lower

8 bits of the bus. Moreover, odd or even byte transfers

activate on the lower or upper 8 bits of the bus. This is

programmable and explained next.

During DMA transfers to memory from the ISCC, only byte

data transfers occur. Data appears on the lower 8 bits and

replicates on the upper 8 bits of the bus. Thus, the data is

written to an odd or even byte of the system memory by

address decoding and strobe generation.

Data Bus Transfers as a Slave Peripheral

When accessed as a peripheral device (when the ISCC is

not a bus master performing DMA transfers), only 8 bits

transfer. During ISCC register read, the byte data present

on the lower 8 bits of the bus is replicated on the upper 8

bits of the bus. Data is accepted by the ISCC only on the

lower 8 bits of the bus.

During DMA transfers to the ISCC from memory, byte data

only transfers. Normally, data appears only on the lower 8

bits of the bus. However, the byte swapping feature

6-3

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

BUS DATA TRANSFERS (Continued)

determines which byte of the bus data is accepted. The

byte swapping feature activates by programming the Byte

Swap Enable bit to a 1 in the BCR. The odd/even byte

transfer selection occurs by programming the Byte Swap

Select bit in the BCR. If Byte Swap Select is a 1, then even

address bytes (transfers where the DMA address has A0

= 0) are accepted on the lower 8 bits of the bus. Odd

address bytes (transfers where the DMA address has A0

= 1) are accepted on the upper 8 bits of the bus. If Byte

Swap Select is a 0, then even address bytes (transfers

where the DMA address has A0 = 0) are accepted on the

upper 8 bits of the bus. Odd address bytes (transfers

where the DMA address has A0 =1) are accepted on the

lower 8 bits of the bus.

The ISCC can return an interrupt vector that encodes with

the type of interrupt pending enabled during this

acknowledge cycle. The ISCC may request an interrupt

but not return an interrupt vector [note that the no vector

bit(s) in the SCC section (WR9 bit 1) and in the DMA

section (ICR bit 5) individually control whether or not an

interrupt vector returns by these cores]. The interrupt

vector can program to include a status field showing the

internal ISCC source of the interrupt. During the interrupt

acknowledge cycle, the ISCC returns the interrupt vector

when INTACK, RD or DS go active and IEI is high (if the

ISCC is not programmed for the no vector option).

During the programmed pulsed acknowledge type

(whether single or double), INTACK is the strobe for the

interrupt vector. Thus when INTACK goes active, the ISCC

drives the bus and presents the interrupt vector to the

CPU. When the status acknowledge type programs, the

ISCC drives the bus with the interrupt vector when RD or

DS are active.

Bus Interface Handshaking

The ISCC™ supports data transfers by either a data strobe

(DS) combined with a read/write (R/W) status line, or

separate read (RD) and write (WR) strobes. These

transactions activate via chip enable (CE).

WAITRDY programs to function either as a WAIT signal or

a READY signal using the BCR write. When programmed

as a wait signal, it supports the READY function of 8X86

family microprocessors. When programmed as a ready

signal, it supports the DTACK function of 680x0 family

microprocessors.

ISCC programming generates interrupts upon the

occurrence of certain internal events. The ISCC internally

prioritizes its own interrupts, therefore, the ISCC presents

one interrupt to the processor even though lower priority

internal interrupts may be pending. Interrupts are

individually enabled or disabled. Refer to the sections on

the SCC core.

The WAIT/RDY signal functions as an output when the

ISCC is not a bus master. In this case, this signal serves

to indicate when the data is available during a read cycle,

when the device is ready to receive data during a write

cycle, and when a valid vector is available during an

interrupt acknowledge cycle.

Interrupt Acknowledge (INTACK) is an input to the ISCC

showing that an interrupt acknowledge cycle is

progressing. INTACK is programmed to accept a status

acknowledge, a single pulse acknowledge, or a double

pulse acknowledge. This programming activates in the

BCR. The double pulse acknowledge is compatible with

8X86 family microprocessors and the status acknowledge

is compatible with 68000 family microprocessors.

When the ISCC is the bus master (DMA section has taken

control of the bus), the WAIT/RDY signal functions as a

WAIT or RDY input. Slow memories and peripheral

devices use WAIT to extend the data strobe (/DS) during

bus transfers. Similarly, memories and peripheral devices

use RDY to indicate valid output or that it is ready to latch

input data.

During an interrupt acknowledge cycle, the SCC and DMA

interrupt priority daisy chain internally resolves. Thus, the

highest priority internal interrupt is presented to the CPU.

6-4

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

CONFIGURING THE BUS

The bus configuration programming is done in two

separate steps (actually it is one operation), to enable the

write to the Bus Configuration Register (BCR). The first

operation that accesses the ISCC after a device reset must

be a write to the BCR since this is the only time that the

BCR is accessible. Before and during the write, various

external signals are sampled to program bus configuration

parameters. During this write, the AØ/SCC//DMA pin must

be Low.

Bits 1 and 2 of the BCR control the interrupt acknowledge

type as shown in the Table A-3.

Table 41. BCR Control of Interrupt Acknowledge

BCR bit 2 BCR bit 1 Interrupt Acknowledge

0

1

0

1

Status Acknowledge

Pulsed Acknowledge (single)

Reserved (action not deﬁned)

Double Pulsed Acknowledge

Address strobe programs multiplexed/non-multiplexed

selection. In a non-multiplexed bus environment, address

strobe (as an input) is not used but tied high through a

suitable pull-up resistor. Thus, no address strobe is

present before the BCR write. Then, when write to the

BCR takes place, the non-multiplexed mode is

programmed because there is no address strobe before

this first write to the device. Note that address strobe

becomes an output during DMA operations so it is not tied

The Status Acknowledge remains active throughout the

interrupt cycle and is directly compatible with the 680x0

family interrupt handshaking. The Status Acknowledge

signal latches with the rising edge of AS for multiplexed

bus operation. It latches by the falling edge of the strobe

(RD or DS) for non-multiplexed bus operation. The Pulsed

Acknowledges are timed to be active during a specified

period in the interrupt cycle. The Double Pulsed

Acknowledge is directly compatible with the 8x86 family

interrupt handshaking. Refer to the timing diagrams in the

ISCC Product Specification for details on the Acknowledge

signal operation.

directly to V

CC.

During the write operation to the BCR, the A1/A/B input is

sampled to select the function of the WAIT/RDY pin (Table

A-2). When the BCR Write is to the SCC Channel A

(A1/A//B High during the BCR write), the WAIT/RDY signal

functions as a wait. When the BCR Write is to Channel B

(A1/A//B Low during the BCR write), the WAIT/RDY signal

functions as a ready.

Reserve bits 3, 4, and 5 of the BCR program as zeros. Bits

6 and 7 of the BCR control the byte swap feature (Table A-

4). Byte swap is applicable only in DMA transfers when the

ISCC is the bus master and only affects ISCC data

acceptance (transfers from memory to the ISCC).l

Table 40. Signals Sampled During the BCR Write

Table 42. Byte Swap Contro

Enable (BCR bit

A1/A//B

WAIT/RDY Function

1

0

WAIT (8086 RDY compatible)

READY (68000 DTACK compatible)

7)

DMA Data Read by the ISCC

0

1

lower 8 bits of bus only

upper or lower 8 bits of bus

This programming affects the function of the WAIT/RDY

signal both as an input, when the ISCC is bus master

during DMA operations, and as an output when the ISCC

is a bus slave.

Swap

Select*

A0

DMA Data read by the ISCC

With this programming, the ISCC is immediately

configured to function successfully on this first and

subsequent bus transactions. The remaining bus

configuration options are programmed by the value written

to the BCR.

0

1

0

1

upper 8 bits of bus

lower 8 bits of bus

upper 8 bits of bus

0

1

* BCR bit 6

Bit 0 of the BCR controls the Shift Left/Shift Right address

decoding modes for the DMA section. In this case, the shift

function is similar to the SCC section. During Left Shift, the

internal register addresses decode from bits AD5 through

AD1. During Right Shift, the internal register addresses

are decode from bits AD4 through AD0. This function is

only applicable in the multiplexed bus mode.

6-5

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

APPLICATIONS EXAMPLES

The following application examples explain and illustrate

the methods of interfacing the ISCC to a Motorola 68000

and an Intel 8086.

performs bus arbitration for multiple bus master requests

and generates bus grant acknowledge (BGACK) which

controls certain bus drive signal sources.

When the ISCC becomes the bus master, a 32-bit address

generation by the DMA section is output on the ISCC

address/data bus. The lower 16 bits of this address store

in an external latch by AS (Address Strobe). Also, the

upper 16 bits of this address store in an external latch by

UAS (Upper Address Strobe). With BGACK low (active)

and with the processor address lines tri-stated, the latch

outputs drive the system address bus.

68000 Interface to the ISCC

Figure A-3 shows a connection of the ISCC to a 68000

microprocessor. The 68000 data bus connects directly, or

through bus transceivers, to the ISCC address/data bus.

R/W and RESET also directly connect. In this example, the

ISCC is on the lower half of the bus; DS of the ISCC

connects to LDS of the 68000. The processor address

lines decode to produce a chip enable for the ISCC. In

addition, processor addresses A1 and A2 connect to

A0/SCC/DMA and A1/A/B, respectively, through a tri-state

driver.

AS is pulled high by an external resistor. This pull-up

insures an inactive AS (at a logic high level) when the

ISCC is not driving this signal. Therefore, on power up or

after a RESET, AS is inactive and programs the non-

multiplexed bus mode on BCR write.

The driver is normally ON (enabled) but turns OFF by

BGACK to grant the bus to ISCC for DMA transfers. This

is done since the A0/SCC/DMA and A1/A/B pins become

outputs during DMA transfers and should not drive the

system address bus. RD and WR tie high through

independent pull-ups. They are not used in this application

but become active outputs during DMA transfers and are

In this application, the outputs of the address latches are

connected to the address bus so that A1 through A23 of

the ISCC drives the system address bus (the ISCC

provides a total of 32 address lines). A0 from the address

latch is diverted to logic which generates UDS and LDS

bus signals from the ISCC data strobe (DS). UDS is

generated when A0 is low and LDS is generated when A0

is high. The lower and upper data strobes are applied to

the system bus through tri-state drivers which are enabled

only when BGACK is active. Bus direction is now

controlled by the ISCC R/W signal which is now an output.

not tied directly to V

.

CC

Although not shown in Table A-5, the A0/SCC/DMA and

A1/A/B pins may be decoded during DMA transfers to

identify the active DMA channel.

Table 43. DMA A/B Channel Decode

For initialization, the BCR write (the first write to the ISCC

after RESET) is done with A2 = 0 (A1/A/B ISCC input at

logic low). This selects the ready option of the WAIT/RDY

signal to conform to the 68000 bus style. The AS signal

programming of the non-multiplexed bus has already been

discussed. The BCR is written with C0H to enable byte

swapping. It also selects the sense of byte swapping with

respect to A0 appropriate to this bus style and selects the

STATUS type of interrupt acknowledge.

A1/A/B

A0/SCC/DMA DMA Channel

1

0

1

0

1

0

Receiver Channel A

Transmitter Channel A

Receiver Channel B

Transmitter Channel B

External logic can use this information to abort a DMA in

progress.

For normal slave device bus interaction, a DTACK is

generated. WAIT/RDY is programed for ready operation

and INTACK programs for the status type. WAIT/RDY

generates a DTACK for normal data transfers and interrupt

responses. Additional logic may be required when other

interrupt sources are present.

8086 Interface with the ISCC

Figure A-4 shows the connection of the ISCC to an 8086

microprocessor and companion clock state generator. In

this application, the ISCC connects for multiplexed

address access to the internal ISCC registers. AD15

through AD0 of the 8086 connect directly, or through a bus

transceiver, to the corresponding AD15 through AD0

address/data ISCC bus pins. RD and WR are directly

compatible and tie together to form the read and write bus

signals.

During DMA transfers, the ISCC becomes bus master.

Becoming bus master is done through the BUSREQ

output and BUSACK input signals of the ISCC. They

connect to an external bus arbitration circuit. This circuit

6-6

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

Vcc

/RESET

/UDS

/RESET

/DS

/UDS

/LDS

Vcc

/RD

/WR

/BGACK

/DTACK

D15-0

WAIT/RDY

AD15-AD0

/BGACK

/OE

A23-16

A0

Q

D

A23-1

Latch

Vcc

A15-1

Q

D

Latch

Vcc

68000

16C35

/AS

/UAS

A2

A1

A1/A/B

Address

Decode

A0/SCC/DMA

/BGACK

/CS

R//W

FC2

FC1

FC0

R//W

/INTACK

/INT

/IPL2

/IPL1

/IPL0

Interrupt

Priority

/BGACK

BG

/BUSREQ

/BUSACK

Bus

Arbitration

Logic

/BR

Figure 3. ISCC Interface to a 68000 Microprocessor

6-7

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

APPLICATIONS EXAMPLES (Continued)

/RESET

/RD

RESET

/RD

/WR

ALE

/AS

AD15-AD0

A1/A/B

AD15-AD0

A7

System Address

Bus Lower

A0/SCC/DMA

A6

Order Bits

D

Q

Latch

A0

/BHE

Chip

Select

Decode

/CS

8086

16C35

/UAS

Q

A19-A16

D

Q

D

Latch

/OE

Latch

/OE

System

Address

Bus Upper

Order Bits

R/W

/DS

Vcc

HOLD

BUS Arbitration and Timing

Synchronization

/BUSREQ

/BUSACK

/INT

*/RD//GT or

HLDA

/INTR

/INTA

RDY

/INTACK

RDY Timing

Synchronizer

WAIT/RDY

* maximum mode

Figure 4. ISCC Interface to an Intel 8086 Microprocessor

6-8

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

When the ISCC becomes a bus master during DMA

operations, RD and WR of the 8086 are tri-stated which

allows the corresponding ISCC signals to control the bus

transactions. The sense of RESET reverses, so the ISCC

RESET signal inverts from the reset applied to the 8086

from the clock state generator.

The ALE signal of the 8086 applies to AS of the ISCC

through an inverting tri-state buffer. The buffer disables

when the ISCC becomes a bus master during DMA

transactions. This prevents conflicts since ALE remains

active even when the 8086 is in the HOLD mode during

DMA transfers. Now, the ISCC AS is an active output. The

address strobe for the demultiplexing latch of addresses

A0 through A15 connects on the ISCC side of the ALE tri-

state buffer. This allows the latch to serve two functions; to

hold either the 8086 or the ISCC address when it is bus

master.

RD/WR and DS of the ISCC are inactive in this application

and tie high. They tie high through independent pull-ups

since these signals become active when the ISCC is bus

master during DMA transactions.

Assuming other devices in the system, the ISCC chip

enable input (CE) activates from a decode of the address.

In this example, the ISCC internally decodes addresses

A1 through A5 and uses A6 and A7, externally. Thus, the

address decode circuitry decodes address lines A0 and A8

and above. The decode of A0 for chip enable places the

ISCC as an 8-bit peripheral on the lower byte of the bus.

A0 and the upper level address lines (including A6 and A7)

demultiplex from the 8086 address/data bus through a

latch strobed by ALE.

After reset, ALE is active and the tri-state buffer enabled.

This supplies address strobes to the ISCC. The presence

of one of these address strobes, before writing to the BCR,

programs the ISCC to the multiplexed bus mode of

operation. The ISCC chip enable (CE) can be inactive and

still recognize an address strobe (AS) before the BCR

write (Figure 4 shows open latches when the input strobe

is low).

When the ISCC is bus master during DMA transactions,

BHE generates from A0. This is done from the output of

the lower order address latch through an inverting tri-state

driver. This driver enables only when the ISCC is the bus

master. Whole word transfers are not done by the ISCC

DMA, thus, BHE generated for the ISCC is always the

inverse of A0.

The demultiplexed addresses A6 and A7 connect to

A0/SCC/DMA and A1/A/B, respectively, of the ISCC to

control selection of the DMA and SCC channels A and B.

This connects through the tri-state drivers. They enable

when the 8086 is the bus master and disable when the

ISCC is bus master. This prevents the ISCC from

improperly driving the system address bus since

A0/SCC/DMA and A1/A/B become active outputs when

the ISCC is the bus master.

The upper bus system address lines demultiplex from the

8086 and the ISCC in separate latches. Like the 68000

example, high order address lines from the ISCC latch via

UAS (upper address strobe). The separate latches drive

the same upper order address lines. A16 from the ISCC

connects to the corresponding A16 address bus line as

derived from the 8086. The output of the two latches

alternately enable depending upon bus mastership.

The address map for the ISCC appears in Table A-6 for

this application.

Table 44. ISCC Address Map

A0 A1-A5 A6

A7 Registers Addressed

The diagram shows INT from the ISCC connected to the

8086 INTR input via an inverter since these signals are of

opposite sense. In actual practice, the ISCC interrupt

request is first processed by an interrupt priority circuit.

INTA (Interrupt Acknowledge) of the 8086 connects

directly to the INTACK input of the ISCC. Conforming to

the 8086 style of interrupt acknowledge, the ISCC is

programed to the Double Pulse Interrupt Acknowledge

type. When this selection occurs, the ISCC responds to

two interrupt acknowledge pulses. The first pulse is

recognized but no action follows. The second pulse

causes the ISCC to go active on the data bus and return

the interrupt vector to the CPU. This action also takes

place with the Single Pulse Interrupt Acknowledge type

selection, except that the bus goes active with the first and

only interrupt acknowledge pulse.

1

0

x

-

x

0

1

x

1

ISCC not enabled

DMA Registers per A1 - A5

SCC Core Channel A

Registers

0

-

1

0

SCC Core Channel B

Registers

Since A0 specifies the lower byte of the bus and includes

the chip enable decode, the internal ISCC register

addresses decode without A0. Thus, Table 6 implies that

the Left Shift address decode selection is made for both

the SCC and DMA sections of the ISCC. The left shift

selection is the default selection after reset. Left/Right Shift

selection programming is discussed later.

6-9

UM010901-0601

Application Note

Interfacing the ISCC™ to the 68000 and 8086

To start, the BCR write (first write to the ISCC after

RESET) is done with A7 = 1 (A1/A/B ISCC input at logic

high). This selects the wait option of the WAIT/RDY signal

to conform to the 8086 bus style. The AS signal

programming of the multiplexed bus was covered earlier.

The BCR is written with 86H to enable byte swapping,

select the sense of the byte swapping with respect to A0

(appropriate to this bus style), and select the Double Pulse

type of interrupt acknowledge.

master. Therefore, there is a requirement for a bus

arbitration circuit.

The

minimum

mode

connection

is

relatively

straightforward. The maximum mode configuration

requires a translation of the ISCC BUSREQ and BUSACK

signals into/from the 8086 RQ/GT timed pulse style of

handshake. Refer to the information on the 8086 for

detailed application information.

The ISCC™ WAIT/RDY output is compatible with the 8086

clock generator RDY input except that one edge of the

signal must be synchronous with the 8086 clock. The

synchronization occurs through external circuitry. Refer to

the information on the 8086 for detailed application

information.

When the ISCC™ begins DMA transfers, it communicates

requests for the bus through BUSREQ and BUSACK. The

8086 receives and grants bus requests through HOLD and

HLDA in the minimum mode and through RQ/GT in the

maximum mode. Depending upon the system

requirements, there could be more than one potential bus

6-10

UM010901-0601

APPLICATION NOTES

ZILOG SCC

Z8030/Z8530

QUESTIONS AND ANSWERS

This document addresses the most commonly asked questions about Zilog’s SCC.

These questions fall into the following five categories:

■

Hard ware Considerations

Interrupt s and Polling

Asychronous mode

■

Sychronous Mode

■

Miscellaneous Questions

HARDWARE CONSIDERATIONS

This section includes questions and answers on the hard-

ware interface, the clocks, the FIFO, special modes (Local

Loopback, DPLL, Manchester), and internal timing consid-

eration.

Q. Do you have to write to the pointer with the Z8530

to access WR0 or RR0?

A. No. Both registers are accessed automatically without

first writing to the pointer.

Q. Does /CE (/CS) have to be High during an interrupt

acknowledge cycle?

A. No.

Hardware (Includes DMA Interface)

Q. What is the SCC transistor count?

A. Approximately 6000 gates, or 18,000 transistors.

Q. Does the SCC support full duplex DMA?

A. The SCC allows full duplex DMA transfers by using the

DTR/REQ and W/REQ as two separate DMA control

lines for transmit request and receive request on each

channel.

Q. What is the difference between the Z8030 and the

Z8530?

A. The Z8030 and Z8530 are packaged from the same

die. The multiplexed bus (Z8030) or non-multiplexed

bus (Z8530) version of the chip is selected at packag-

ing time by an internal bonding option.

Q. When using full duplex DMA, how do you program

W/REQ?

A. W/REQ should be programmed for receive and

DTR/REQ pin should be programmed for transmit.

Q. Can /AS be active only when the Z8030 is being ac-

cessed and High all other times?

A. Since the interrupt pending bits (IPs) are updated on

address strobes, interrupts will not occur unless /AS is

continuous.

Q. Can both channels make simultaneous DMA

requests?

A. Yes.

Q. How do /WR and /CE interact on the Z8530?

A. /WR and /CE are ANDed to enable a transparent latch.

Data is latched on the falling edge when both /CE and

/WR go Low.

Q. Do you have to reset the SCC in hardware?

A. No. A software reset is the same as a hardware reset,

(WR9 CO). It also does not matter whether the Z8030

is in shift right or shift left mode because the address

is the same in either.

Q. How many register pointers does the Z8530 have?

A. The SCC has only one register pointer for both chan-

nels. The SIO (Z844X) has two, one for each channel.

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HARDWARE CONSIDERATIONS (Continued)

Q. Do you need to clear the reset bit in WR0 after a

software reset?

Q. Why does the SCC initialization require that the

External Status Interrupts be reset twice?

A. The reset is clocked with PCLK; so it must be active

during reset.

A. Because of the possibility of noise causing an interrupt

pending bit (IP) to be set. The second reset guarantees

that the latch is clear. If the latch is closed high and the

external signal is low, the first reset will open the latch

at the high-to-low transition causing an interrupt.

Q. How long after a hardware reset should you wait

before programming the SCC.

A. Four PCLKs.

Clocks

Q. Does PCLK have to have a 50% duty cycle?

A. The duty cycle doesn’t have to be 50% as long as the

minimum specification is met.

For PCLK = 3.6864 MHz

For PCLK = 3.9936 MHz

Bit Rate

TC

Error

Bit Rate

TC

Error

38400

19200

9600

7200

4800

3600

2400

1200

46

94

-

19200

9600

7200

4800

3600

2400

2000

1800

1200

600

102

206

-

Q. Can the SCC PCLK be stretched?

A. Yes, as long as the pertinent specification is met. How-

ever, this could cause a problem if PCLK is used to

generate the bit rate.

190

254

382

510

766

1534

275

12%

414

-

553

.06%

830

-

Q. The bit rate generator is driven from what sourc-

996

.04%

es?

A. It may be driven from the RTxC pin or PCLK, or from a

crystal.

1107

1662

3326

6654

13310

.03%

-

Q. How do you connect a bit rate crystal to the SCC?

A. A crystal can be connected between RTxC and SYNC

to supply the clock if the SCC is programmed for

WR11 D7-1.

300

150

134.5

110

14844 .0007%

18151 .0015%

Q. What is the crystal specification?

A. It is a fundamental, parallel resonant crystal. For fur-

ther details see the “Design Considerations Using

Quartz Crystals with Zilog’s Components” Application

Note.

75

26622

39934

-

50

Q. Why are there different Clock factors?

A. These clock factors enable the SCC to sample the

center of the data cell. In the 16x mode, the SCC di-

vides the bit cell into 16 counts and samples on count

8. Clock factors are generally only used with Asyn-

chronous modes.

Q. Can RTxC on both channels be driven from the

same crystal.

A. No. A separate crystal should be used for each chan-

nel. The crystal should be connected between

/SYNC and RTxC of the respective channels. The al-

ternate solution may be to use crystal on one channel

and reflect the clock out of the TRxC output and feed

it into another channel.

Q. How is the error in the receive/transmit clock

reduced?

A. The ideal way to reduce this error is by adjusting the

crystal frequency such that only an integer value of TC

is yielded when the equation is used.

Q. How do you select a crystal frequency?

A. Time constant: (Clock Frequency/2 x Bit rate x clock

factor) - 2. Two examples are given below:

Q. What are the maximum transfer rates?

A. The following table shows the PCLK rates (in bps).

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4 MHz

6 MHz

8 MHz

10 MHz

16 MHz

20 MHz

Asynchronous mode:

External clock

6x mode (no BRG)

BRG

250K

375K

500K

635K

1M

1.25M

16x mode (TX + 0)

62.5K

93.75K

125K

156.5K

250K

312.5K

Synchronous mode:

Using external clock

1M

250K

1.5M

375K

2M

500K

250K

125K

62.5K

2.5M

625K

4M

1M

5M

1.25M

Using DPLL, FM encoding

Using DPLL, MRZ/NRZI encoding

Using DPLL, FM, BRG

125K

187.5K

93.75K

46.88K

312.5K

156.25K

78.125K

500K

250K

125K

625K

62.5K

32.25K

312.5K

156.25K

Using DPLL, NRZ/NRZI, BRG

Q. Can the maximum transfer rate using an external

clock be achieved?

A. Yes, but it is not trivial. In order to achieve the maximum

rate on transmit, the SCC should have a dedicated pro-

cessor or DMA. For example, at a 1 MHz rate, a byte

must be loaded into the SCC every 8 microseconds. To

achieve the maximum rate on receive, requires that the

receive clock and the SCC PCLK be synchronized.

(RTxC to PCLK setup time at maximum rate in the

Product Specification.) It is probably easier to use a

slightly faster PCLK SCC, or back off slightly from the

maximum rate.

FIFO

Q. How do you avoid an overrun in the received

FIFO?

Q. When the FIFO gets locked due to an error condi-

tion, can it still receive?

A. The receive buffer must be read before the recently re-

ceived data character on the serial input is shifted into

the receive data FIFO. This FIFO is three bytes deep.

Thus, if the buffer is not read, the fifth character just ar-

rived causes an overrun condition. There is no bit that

can be set or reset to disable the buffering.

A. The SCC continues to receive until an overrun occurs.

Q. Assuming that there are characters available in

the FIFO, what happens to them if the receiver

goes into the hunt mode?

A. They will remain in the FIFO until they are either read

by the CPU or DMA, or until the channel is reset.

Q. What happens when you read an empty FIFO?

A. You read the last character in the buffer.

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SPECIAL MODES

(LOCAL, LOOPBACK, DPLL, MANCHESTER)

Q

How are the Local, Loopback, and Auto Echo

modes implemented?

Q. Can you receive and transmit between two chan-

nels on the same SCC using the DPLL to generate

both the transmit and receive clocks?

A. The TxD and RxD pins are connected through drivers.

If both modes are simultaneously enabled, then Auto

Echo overrides.

A. To transmit and receive using the same clock, you

need to divide the transmit clock by 16 or 32 to be the

same rate for transmitting and receiving, because the

DPLL requires a divide-by-16 or -32 on the receiver,

depending on the encoding. An external divide-by-16

or -32 is required, and can be connected by outpouring

the bit rate generator on the /TRxC pin, through the ex-

ternal divide circuit, and back in the /RTxC pin as an

input to the transmitter.

Q. Can the SCC transmit when the Auto Echo mode is

enabled?

A. No, the transmitter is logically disconnected from the

TxD pin.

Q. Can the Digital Phase Lock Loop (DPLL) be used

with NRZ?

A. The DPLL simply generates the receive clock which is

the same for both NRZ and NRZI.

Q. How fast will Manchester be decoded?

A. The SCC can decode Manchester data by using the

DPLL in the FM mode and programming the receiver

for NRZ data. Hence, the 125K bit/s is the maximum

rate for decoding at 8MHz SCC. A circuit for encoding

Manchester is available from Zilog.

Q. Do you have to use the DPLL with NRZI and FM en-

coding?

A. If the DPLL is not used, a properly phased external

clock must be supplied.

Q. When will the Time Constant be loaded into the

BRG counter?

A. After a S/W reset or a Zero Count is reached.

Q. What is the error tolerance for the DPLL?

A. The DPLL can only tolerate a + or - 1/32 deviation in

frequency, or about 3%.

Q. How to run NRZ data using the DPLL?

A. Use NRZI for DPLL (WR14) but set to NRZ (WR10).

INTERNAL TIMING

Q. When does data transfer from the transmit buffer

to the shift register?

Q. Does Valid Access Recovery Time apply to all suc-

cessive accesses to the SCC?

A. About 3 PCLK’s after the last bit is shifted out.

A. Any access to the SCC requires that the recovery time

be observed before a new access. This includes read-

ing several bytes from the receive FIFO, accessing

separate bytes on two different channels, etc. When

using DMA or block transfer methods, the recovery

time must be considered.

Q. How long does it take for a write operation to get

to the transmit buffer?

A. It takes about 5 PCLK’s for the data to get to the buffer.

Q. What is Valid Access Recovery Time?

A. Since WR/ and RD/ (AS/ and DS/ on the Z8030) have

no phase relationship with PCLK, the circuitry generat-

ing these internal control signals must provide time for

metastable conditions to disappear. This gives rise to

a recovery time related to PCLK.

Q. Do the DMA request and wait lines on the SCC take

the Valid Access Recovery time into account be-

fore they make a request?

A. No, they are not that intelligent. The user must take

this into account, and program the DMA accordingly.

For example, by inserting wait states during the mem-

ory access between SCC accesses, which will length-

en the time in between SCC accesses, or by requiring

the DMA to release the bus between accesses to the

SCC, to prevent simultaneous data requests from two

channels from violating the recovery time.

Q. How long is Valid Access Recovery Time?

A. On the NMOS SCC, the recovery time is 4 PCLK’s,

while on the CMOS SCC, the recovery time is 3-3.5

PCLK’s.

Q. Why does the Z8030 require that the PCLK be “at

least 90% of the CPU clock frequency for Z8000?“

A. If the clocks are within 90%, then the setup and hold

times will be met. Otherwise, the setup and hold times

must be met by the user.

Q. What happens if Valid Access Recovery Time is

violated?

A. Invalid data can result.

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Q. Does Valid Access Recovery Time affect the inter-

rupt acknowledge cycle?

A. No. The interrupt vector is put on the bus by the SCC

during the interrupt acknowledge cycle, but does not

require any recovery time.

Q. Why can some systems violate the recovery time

by 1 or 2 PCLK’s without affecting the data to the

SCC?

A. This violation may or may not matter to the SCC. This

phase relationship between PCLK, /RD, /WR, (/AS,

/DS for Z8030) can by ASYNC. The SCC requires

some time internally to synchronize these signals. The

electrical specs for the SCC indicate a recovery time,

which is the worst case maximum.

INTERRUPT CONSIDERATIONS

Q. What conditions must exist for the SCC to gener-

ate an interrupt request?

nal/status interrupt IP is cleared by the command Re-

set Ext/Status Interrupts.

A. Interrupts must be enabled (MIE = 1 and IE = 1). The

Interrupt Enable Input (IEI) must be high. The interrupt

pending bit (IP) must be set and its interrupt under ser-

vice bit (IUS) must be reset. No interrupt acknowledge

cycle may be active.

Q. Can the IP bits be set while the SCC is servicing

other interrupts?

A. Yes. If the interrupting condition has a higher priority

than the interrupt currently being serviced, it causes

another interrupt, thus nesting the interrupt services.

Q. How can the /INTACK signal be synchronized with

PCLK?

A. /INTACK needs to be synchronized with PCLK. This

can be accomplished by changing /INTACK only on

the falling edge of PCLK by using a D flip-flop that is

clocked with the inverted PCLK.

Q. Can the IUS bits be accessed?

A. No. They are not accessible.

Q. When do IUS bits get set?

A. The IUS bits are set during an interrupt acknowledge

cycle on the falling edge or /RD or /DS.

Q. Is /CE required during an Interrupt Acknowledge

cycle?

A. No.

Q. How do you reset interrupts on the SCC?

A. The interrupt under service bit (IUS) can be reset by

the command “Reset Highest IUS” or 38 Hex to WR0.

Reset Highest IUS should be the last command issued

in the interrupt service routine.

Q. How long does /INT stay active low when request-

ing an interrupt?

A. If the SCC is operated in a polled mode, the /INT will

remain active until the IP bit is reset. For an interrupt

acknowledge cycle, the /INT will go inactive shortly af-

ter the falling edge of /RD or /DS when the IUS bit is

set.

Q. Why is the interrupt daisy chain settle time re-

quired?

A. This mechanism allows the peripheral with the highest

priority interrupt pending in the hardware interrupt dai-

sy chain to have its interrupt serviced.

Q. Can you use the SCC without a hardware interrupt

acknowledge?

Q. Is there still a settle time if the peripherals are not

chained?

A. Even if only one SCC is used, there still is a minimum

daisy-chain settle time due to the internal chain.

A. Yes. If you are not using the hardware daisy chain, you

don’t need to give an interrupt acknowledge. Tie the

intack pin high, enable interrupts, and on responding

to an interrupt, check RR3 for the cause, and special

receive conditions if you are in receive mode. The in-

ternal daisy-chain settling time must still be met. (IEI to

IEO delay time specification.)

Q. How should the vectors be read when utilizing the

/INTACK?

A. /INTACK should be tied to 5 volts through a register.

Erroneous reads can result from a floating INTACK.

The interrupt vectors can be read after an interrupt

from RR2.

Q. How do you acknowledge an interrupt without a

hardware interrupt acknowledge?

A. Reset the responsible interrupt pending bit (IP). The

/INT line follows the IP bit.

Q. How is the vector register different from the other

registers?

A. The vector register is shared between both channels.

The Write register can be accessed from either chan-

nel. Reading “Read Register 2” on Channel A (RR2A)

returns the unmodified vector, and RR2B returns the

Q. When are the IP bits cleared?

A. A transmitter empty IP is cleared by writing to the

data register. A receive character available IP is

cleared by reading the data register. The exter-

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INTERRUPT CONSIDERATIONS (Continued)

modified vector that includes status. The vector in-

cludes the status bit (VIS, WR9) and determines which

vector register is put out on the bus during an interrupt

cycle.

Q. How do you poll the bits in RR3A?

A. Enable interrupts in WR1 and disable MIE before polling.

Q. What happens when the SCC is programmed to in-

terrupt on transmit buffer empty and also to re-

quest DMA activity on transmit buffer empty?

A. This would not be a wise thing to do. The interrupt

would occur but the DMA could gain control of the bus

and remove the interrupting condition before the inter-

rupt acknowledge could take place. When the CPU re-

covers control of the bus and starts the interrupt

acknowledge cycle, bus confusion results because the

peripheral no longer has a reason to interrupt.

Q. How do you poll the external/status interupt IP bit?

A. Set the IE bits in WR15 so the conditions are latched

and set ext/status master interrupt enable bit in WR1.

To guarantee the current status, the processor should

issue a Reset External/Status interrupts command in

WR0 to open the latches before reading the register.

For further details see the SCC Technical Manual,

section 3.4.7.

Q. When should the status in RR1 be checked?

A. Always read RR1 before reading the data.

Q. Will IP bit (s) for external status be cleared by the

Reset Ext/Status Interrupt?

A. Yes.

Q. What conditions cause the transmit IP to be set?

A. Either the buffer is empty, or the flag after CRC is be-

ing loaded.

Q. How do you tell if you have a Zero Count (ZC) in-

terrupt?

A. This bit is not latched like the other external IP bits. If

an external interrupt occurs and none of the other IP

bits have changed since the last ext/status interrupt,

then the ZC condition caused it. A ZC interrupt will not

be generated if there are other ext/status (IP) pending.

The ZC stays active for each time only when the count

reached zero, approximately two PCLK time periods.

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ASYNCHRONOUS MODE

Q. Can the Sync Character Load Inhibit function strip

characters in Asynchronous mode if not disabled?

A. Yes. If not disabled it will strip any characters which

match the value in the sync character register. Always

disable this function in asynchronous mode (WR3, bit

D1).

Q. In the Auto Enable mode, what happens when

CTS/ goes inactive (high) in the middle of transfer-

ring a byte?

A. If the Auto Enable mode is selected, the CTS/ pin is an

enable for the transmitter. So, when CTS/ is inactive,

transmit stops immediately.

Q. What controls the DTR/WREQ pin?

Q. Can X1 clock mode really be used for the Async

operation?

A. X1 mode cannot be used unless the receive and trans-

mit clocks are synchronized. Using a synchronous mo-

dem is one way of satisfying this requirement.

A. The DTR pin follows the D7 bit in WR5 (inverse) as a

Data Terminal Ready pin, or it is a DMA request line

(WREQ). The bit can be set or reset by writing to WR5.

Q. How is the Asynchronous mode selected?

A. The Asyn mode is selected by programming the num-

ber of stop bits in write register 4.

Q. When does the FIFO buffer lock on an error

condition?

A. The receive data FIFO gets locked only in cases where

the following receiver interrupt modes are selected:

Q. How are receiver breaks handled?

A. The SCC should monitor the break condition and wait

for it to terminate. When the break condition stops, the

single NULL character in the receive buffer should be

read and discarded.

–

Receive Interrupt on Special Condition only

Receive Interrupt on First Character or Special

Condition

Q. Where can you get the DTR input if the DTR/REQ

pin is being used for DMA?

A. The SYNC can be used as an input if operating in the

Async mode. It will cause an interrupt on both transi-

tions.

In both of these modes, the Special Condition interrupt

occurs after the character with the special condition

has been read. The error status has to be valid when

read in the service routine. The Special Condition

locks the FIFO and guarantees that the DMA will not

transfer any characters until the Special Condition has

been serviced.

Q. When a special condition occurs due to a parity

error, will a receive interrupt for that byte still be

generated?

A. No. In the case of Receive interrupt on Special Condi-

tion Only mode, the interrupt will not occur until after

the character with the special condition is read. In the

case of Receive Interrupt on All Characters or Special

Condition Only mode, the interrupt is generated on ev-

ery character whether or not it has a special condition.

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SYNCHRONOUS MODES

(SDLC, HDLC, BYSYNC, AND MONOSYNC MODES INCLUDED)

Q. For what are the cyclical redundancy check (CRC)

residue codes used?

A. The residue codes provide a secondary method to

check the reception of the message.

Q. If the SCC is idling flags, and a byte of data is

loaded into the transmit buffer, what will be

transmitted?

A. Data takes priority over flags and will be loaded in the

shift register and transmitted.

Q. Why is the second byte of the CRC incorrect when

read from the receiving SCC?

A. The second byte of the CRC actually consists of the

last two bits of the first byte or CRC, and the first six

bits of the second byte of CRC.

Q. Since data is preferred, can this cause a problem?

A. This allows you to append on the end of a message, but

it can cause problems with DMA. A character could be

transmitted without an opening flag. To make sure that

a flag has been transmitted, watch for the W/REQ line

to toggle when the flag is loaded into the shift register.

Q. How does the SCC send CRC?

A. The SCC can be programmed to automatically send the

CRC. First, write the first byte of the message to be

sent. This guarantees the transmitter is full. Then reset

the Transmit Underrun/EOM latch (WR0 10). Write the

rest of the data frame. When the transmit buffer under-

runs, the CRC is sent. The following table describes the

action taken by the SCC for the bit-oriented protocols:

Q. Can you gate data by stretching the receive clock?

A. You can hold the clock until you have valid data. There

are no maximum specs on the RxC period, and the

edges are used to sample the data. If there are no edg-

es, no data is sampled.

Q. How do you synchronize the DPLL in SDLC mode?

A. There are two methods to synchronize the DPLL. Sup-

ply at least 16 transitions at the beginning of each

message so the DPLL has time to make adjustments,

or use the DPLL search mode in WR14 to cause the

SCC to synchronize on first transition. The first edge

must be guaranteed to be a cell boundary.

Tx Underrun

EOM Latch Bit

Abort/Flag

Bit

Action Upon

Tx Underrun

Comment

0

1

0

X

Sends CRC +

Flags

Valid Frame

Sends Abort + Aborted

Flags

Frame

Sends Flags

Software

CRC

Q. In SDLC, is the flag and address stripped-off?

A. No, only the flag is stripped. The address will be the

1st character received.

The SCC sets the Tx Underrun/EOM latch when the CRC

or Abort is loaded into the shift register for transmission.

This event causes an interrupt (if enabled).

®

Q. Does IBM SDLC specify parity?

A. No.

Q. In SDLC, when do you reset the CRC generator

and checker?

Q. Can the SCC include parity in SDLC mode?

A. Yes. It is appended at the end of the character.

A. The Reset TxCRC Generator command should be is-

sued when the transmitter is enabled and idling

(WR0). This needs to be done only once at initializa-

tion time for SDLC mode.

Q. How does the SCC operate in transparent mode?

A. The transparentness, as defined by IBM SNA, should

be provided by the software. The SCC does not per-

form any automatic insertion and deletion of link con-

trol nor does it automatically exclude the characters

from the CRC calculation. This also applies to other

high level protocols.

Q. How can you make sure that a flag is transmitted

after CRC?

A. Use the external status end of message (EOM) inter-

rupt to start the CRC transmission, then enable the

transmit buffer empty interrupt. When you get the in-

terrupt, it means that the buffer is empty, a flag is load-

ed in the shift register, and you can send the next

packet of information.

Q. When does the Abort function take effect?

A. The abort takes place immediately by inserting eight

consecutive 1’s.

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Q. Can the SCC detect multiple aborts?

Q. How can you determine when the flag has been

completely sent?

A. The SCC searched for seven consecutive 1’s on the

receive data line for the abort detection. This condition

may be allowed to cause an external status interrupt.

After these seven 1’s are received, the receiver auto-

matically enters Hunt mode, where it looks for flags.

So, even if more than seven 1’s are received in case

of multiple aborts, only the first sequence of 1’s is sig-

nificant.

A. There are several ways to determine if the flag has

been completely sent. This allows the transmitter to be

shut off, or in half duplex the line can be turned around.

This requires a little work by the user because the SCC

does not know when the last flag bit has been shifted

our. The following are some suggestions:

–

Once the flag is loaded into the transmit shift

register, start an external clock. Use the baud rate

generator as the counter.

Q. How do you send an end of poll (EOP) flag in SDLC

loop mode?

A. To send the EOP message, simply toggle the bit which

idles flags or ones to mark flags, then mark ones. This

produces a zero and more than seven 1’s; an EOP

condition.

–

Tie the transmit line into DCD or an available input

pin, and watch for a zero, or end of flag. If you are

running half-duplex, use the local loopback mode

and watch for the flag to end.

Q. When the SCC is programmed for 6 bit sync, how

–

Allow an abort, although this destroys the last

character. Be sure to send a dummy character -

then idle flags after the abort latch is set.

are bits sent?

A. Six bits are sent. The 12-bit sync character sends 12

bits.

Q. How do the DMA W/REQ lines operate?

A. DMA request lines follow the state of the transmit buff-

er.

Q. Do sync patterns (or flags) in data transmissions

get stripped and still cause interrupts?

A. All leading sync patterns (and all flags) are automati-

cally stripped if the Sync Character Load Inhibit fea-

ture is programmed. Any data stripped from the

transmission stream cannot cause a receive character

available interrupt but may cause other interrupts

(such as External/Status for Sync/Hunt and special re-

ceive condition for EOM).

Q. How does the SCC handle messages less than

four bytes in length?

A. A 4-byte message consists of an address, control

word, no data, and 2 bytes of CRC. SDLC defines

messages of less than 4-bytes as an error. It is not de-

fined how the SCC will react, however, as tested by a

SCC user, 4-, 3-, and 2-byte messages cause an inter-

rupt on end of frame, but a 1 byte message does not

cause an interrupt.

Q. How are the sync characters sent at the beginning

of a Bisync frame?

A. Load the transmit buffer with the first byte and the sync

characters are automatically sent out.

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MISCELLANEOUS QUESTIONS

Q. Can the SCC support MARK and SPACE parity in

async?

A. The SCC can transmit-end the equivalent of MARK par-

ity by setting WR4 to select two STOP bits. The receiv-

er always checks for only one STOP bit; therefore, the

receiver does not verify the MARK parity bit.

Q. When is EOM and EOF asserted?

A. EOM is asserted when it detects depletion of data in

the Tx buffer; EOF is asserted when it detects a clos-

ing flag.

Q. After powering up the SCC, are the reset values in

the write and read registers guaranteed?

The SCC (and products using the SCC cell) does notsup-

port SPAC parity for transmitting or receiving. The

Zilog USC Family of serial datacom controllers do sup-

port odd, even, mark, & space parity types.

A. No. You must perform a hardware or software reset.

Q. Can you read the status of a write register, such as

the MIE bit in WR9?

A. No, in order to retain the status of a write register, you

must keep its status in a separate memory for later

use. However, the only exception is that WR15 is a

mirror image of RR15. Also, the ESCC has a new fea-

ture to allow the user to read some of the write regis-

ters (see the ESCC Product Specification or Technical

Manual for more details).

Q. Since both D7 and D1 bits in RR0 are not latched,

it is possible that the receiver detected an Abort

condition, set D7 to 1, initiated an external/status

interrupt and before the processor entered the ser-

vice routine, termination of the abort was detect-

ed, which reset the Break Abort bit . Currently in

the TM (page 7-20), the description for Bit1: Zero

Count states if the interrupt service routine does

not see any changes in the External/Status condi-

tions, it should assume that a zero count transition

occurred when in fact, an Abort condition oc-

curred and was missed. What could be done to

correct this and not miss the fact that an Abort oc-

curred?

A. Very few people actually use the Zero Count interrupt.

This interrupt is generated TWICE during each bit time

and is usually used to count a specific number of bits

that are sent or received. If this interrupt is not used by

your customer, then what is said in the TM about the

Zero Count is true for the Abort Condition. If no other

changes occurred in the external/status conditions

and the Zero Count is not used, then the source of the

interrupt was the Abort condition.

Q. Is there a signal to indicate that a closing SDLC

flag is completely shifted out of the TxD pin? This

is needed to indicate that the frame is completely

free of the output to allow carrier cut off without

disrupting the CRC or closing flag.

A. No, the only way to find this timing is to count the num-

ber of clocks from Tx Underrun Interrupt to the closing

flag. The ESCC contains the feature by deasserting

the /RTS pin after the closing flag. Upgrade to the ES-

CC!

Q. Does the SCC detect a loss of the receive clock

signal?

A. No, if the clock stops, the SCC senses that the bit time

is very long. Use a watch-dog timer to detect a loss in

the receive clock signal.

Q. Is there any harm in grounding the “NO CON-

NECT” (NC) pins in the PLCC package (pin

#17,18,28,36)?

A. These NC pins are not physically connected inside the

die. Therefore, it is safe to tie them to ground.

Q. Can the SCC resynchronize independent clocks

(at the same frequency, but could be out of phase),

one for Rx data and one for Tx data?

A. No, the two clocks are independent of each other.

However, the SCC provides a special transmitter-to-

receiver synchronization function that may be used to

guarantee that the character boundaries for the re-

ceived and transmitted data are the same.

Q. Can the SCC be used as a shift register in one of

the synchronous modes with only data sent to the

Tx register with no CRC and no sync characters?

A. CRC is optional in Mono-, Bi-, and External Sync

Modes only. The sync characters can be stripped out

via software.

7-10

UM010901-0601

USER’S MANUAL

™

ZILOG ESCC

CONTROLLER

QUESTIONS AND ANSWERS

PRODUCT DESCRIPTION

Q. Which of the following is the major factor in differ-

entiating the ESCC from the USC Family?

a. The ESCC has less communications channels

than the USC

c. The ESCC is limited in operation to less than

5 Mbps, but the USC Family can operate up to

10 Mbps

d. The USC supports the T1 data rate, not the ESCC

b. The protocols supported by ESCC and USC are

different

A. (c) Most ESCC and USC Family members have two

channels and protocols. Support by the SCC is a

subset of ESCC. Both ESCC and USC can sup-

port T1 data rates so (a), (b), (d) are not correct.

Q. Which of the following is not an improvement from

the SCC to the ESCC?

The ESCC has 4 bytes of Tx FIFO and 8 bytes of Rx FIFO,

while the SCC has 1 byte for the Tx and 3 bytes for the Rx.

a. The ESCC has deeper FIFOs

The ESCC has many new SDLC enhancements, such as

automatic EOM reset, automatic opening flag generation,

etc.

b. The ESCC has new SDLC enhancements

c. The ESCC has added new READ Registers

d. The ESCC has added new WRITE Registers

The ESCC has added WR7' as a new WRITE Register to

configure the new options, therefore, (a), (b), (d) are all dif-

ferences between the SCC and ESCC.

A. (c) No new READ register addressing is added in the

ESCC although we allowed some Write Registers

to become readable through the existing READ

Register.

7-11

UM010901-0601

SCC™/ESCC™ User’s Manual

™

Zilog ESCC Controller

APPLICATIONS

Q. Which of the following is a benefit from deeper

FIFOs offered by the ESCC?

Q. Which of the following is an applications support

the tool for ESCC:

a. More CPU bandwidths available for other system

tasks

a. Sealevel Board

b. (Electronic Programmers Manual

b. Can support faster data rates on each channel

c. Can support more channels for the same CPU

d. All of the above

c. Application

Note

“Boost

Your

System

Performance Using the Zilog ESCC”“

d. All of the above

A. (d) (a), (b) and (c) are consequences of reduction in in-

terrupt frequency that allows more horsepower to be

delivered from the CPU.

A. (d)

Q. Which of the following is a target application for

the ESCC?

Q. Which of the following CRC polynomials is sup-

a. AppleTalk-LocalTalk Peripherals

ported in ESCC?

a. CRC-16

b. X.25 Packet Switches

c. SNA connectivity products

d. All of the above

b. CRC-32

c. (CRC-CCITT

A. (d) ESCC could support the data rate and protocol re-

quired in the above applications.

d. (a) and (c)

e. (b) and (c)

A. (d) CRC-32 is not supported in ESCC.

Q. How long does it usually take for the customer to

migrate from SCC to ESCC in order to take the ad-

vantage of the FIFO?

a. Less than 3 month

b. About 6 month

c. About a year

A. (a) Since the ESCC is a drop-in replacement to the

SCC and using the deeper FIFO only requires minimal

efforts.

7-12

UM010901-0601


型号：	Z85230
厂家：	ZILOG, INC.
描述：	The Zilog SCC Serial Communication Controller 在Zilog公司SCC串行通信控制器通信控制器
文件：	总317页 (文件大小：3115K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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