Z85C3010NEC [ZILOG]
CMOS SCC SERIAL COMMUNICATIONS CONTROLLER; 鳞状细胞癌的CMOS串行通信控制器
| 型号： | Z85C3010NEC |
| 厂家： | 
ZILOG, INC. |
| 描述： | CMOS SCC SERIAL COMMUNICATIONS CONTROLLER |
| 文件： | 总96页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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)LJXUHꢀꢆꢅꢍ 5HDGꢀ5HJLVWHUꢀ%LWꢀ)XQFWLRQVꢀꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢉꢎ
)LJXUHꢀꢃꢋꢍ ꢀ5HDGꢀ5HJLVWHUꢀ%LWꢀ)XQFWLRQVꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢉꢌ
)LJXUHꢀꢃꢆꢍ 5HDGꢀ&\FOHꢀ7LPLQJꢀ ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢉꢅ
)LJXUHꢀꢃꢃꢍ :ULWHꢀ&\FOHꢀ7LPLQJꢀ ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢁꢋ
)LJXUHꢀꢃꢂꢍ ,QWHUUXSWꢀ$FNQRZOHGJHꢀ&\FOHꢀ7LPLQJꢀ ꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢁꢆ
)LJXUHꢀꢃꢉꢍ 5HDGꢀ&\FOHꢀ7LPLQJꢀ ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢁꢃ
)LJXUHꢀꢃꢁꢍ :ULWHꢀ&\FOHꢀ7LPLQJꢀ ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢁꢂ
)LJXUHꢀꢃꢇꢍ ,QWHUUXSWꢀ$FNQRZOHGJHꢀ&\FOHꢀ7LPLQJꢀ ꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢁꢉ
)LJXUHꢀꢃꢎꢍ 6WDQGDUGꢀ7HVWꢀ/RDGꢀ ꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢁꢇ
)LJXUHꢀꢃꢌꢍ 2SHQꢈ'UDLQꢀ7HVWꢀ/RDG ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍ ꢀꢁꢇ
)LJXUHꢀꢃꢅꢍ =ꢌꢁ&ꢂꢋꢀ5HDGꢏ:ULWHꢀ7LPLQJꢀ'LDJUDPꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢇꢋ
)LJXUHꢀꢂꢋꢍ =ꢌꢁ&ꢂꢋꢀ,QWHUUXSWꢀ$FNQRZOHGJHꢀ7LPLQJꢀ'LDJUDPꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢇꢆ
)LJXUHꢀꢂꢆꢍ ꢀ=ꢌꢁ&ꢂꢋꢀ&\FOHꢀ7LPLQJꢀ'LDJUDPꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢇꢆ
)LJXUHꢀꢂꢃꢍ ꢀ=ꢌꢁ&ꢂꢋꢀ5HVHWꢀ7LPLQJꢀ'LDJUDPꢀ ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢇꢃ
)LJXUHꢀꢂꢂꢍ ꢀ=ꢌꢁ&ꢂꢋꢀ*HQHUDOꢀ7LPLQJꢀ'LDJUDPꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢇꢎ
)LJXUHꢀꢂꢉꢍ ꢀ=ꢌꢁ&ꢂꢋꢀ6\VWHPꢀ7LPLQJꢀ'LDJUDPꢀꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢎꢋ
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)LJXUHꢀꢂꢁꢍ ꢀ=ꢌꢋ&ꢂꢋꢀ5HDGꢏ:ULWHꢀ7LPLQJꢀ'LDJUDPꢀꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢎꢂ
)LJXUHꢀꢂꢇꢍ ꢀ=ꢌꢋ&ꢂꢋꢀ,QWHUUXSWꢀ$FNQRZOHGJHꢀ7LPLQJꢀ'LDJUDPꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍ ꢀꢎꢉ
)LJXUHꢀꢂꢎꢍ ꢀ=ꢌꢋ&ꢂꢋꢀ5HVHWꢀ7LPLQJꢀ'LDJUDPꢀ ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢎꢉ
)LJXUHꢀꢂꢌꢍ =ꢌꢋ&ꢂꢋꢀ*HQHUDOꢀ7LPLQJꢀ'LDJUDPꢀꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢎꢅ
)LJXUHꢀꢂꢅꢍ ꢀ=ꢌꢋ&ꢂꢋꢀ6\VWHPꢀ7LPLQJꢀ'LDJUDPꢀꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢌꢃ
)LJXUHꢀꢉꢋꢍ ꢉꢋꢈ3LQꢀ',3ꢀ3DFNDJHꢀ'LDJUDPꢀꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢌꢂ
)LJXUHꢀꢉꢆꢍ ꢉꢉꢈ3LQꢀ3/&&ꢀ3DFNDJHꢀ'LDJUDPꢀ ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢌꢉ
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/LVWꢅRIꢅ7DEOHV
7DEOHꢀꢆꢍ 6&&ꢀ5HDGꢀ5HJLVWHUꢀ)XQFWLRQVꢀ ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢃꢋ
7DEOHꢀꢃꢍ 6&&ꢀ:ULWHꢀ5HJLVWHUꢀ)XQFWLRQVꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢃꢋ
7DEOHꢀꢂꢍ &DSDFLWDQFHꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢁꢎ
7DEOHꢀꢉꢍ =ꢌꢋ&ꢂꢋꢏ=ꢌꢁ&ꢂꢋꢀ'&ꢀ&KDUDFWHULVWLFV ꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍ ꢀꢁꢌ
7DEOHꢀꢁꢍ =ꢌꢁ&ꢂꢋꢀ5HDGꢏ:ULWHꢀ7LPLQJꢀ ꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢇꢃ
7DEOHꢀꢇꢍ =ꢌꢁ&ꢂꢋꢀ*HQHUDOꢀ7LPLQJꢀ7DEOH ꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍ ꢀꢇꢌ
7DEOHꢀꢎꢍ =ꢌꢁ&ꢂꢋꢀ6\VWHPꢀ7LPLQJꢀ7DEOHꢀ ꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀꢍꢀ ꢎꢆ
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Write Register 1
Write Register 0 (non-multiplexed bus mode)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Ext Int Enable
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
Tx Int Enable
Parity is Special Condition
Rx Int Disable
0
1
0
1
0
0
1
1
Rx Int on First Character or Special Condition
Int on all Rx Characters or Special Condition
Rx Int on Special Condition Only
WAIT/DMA Request on
Receive /Transmit
*
WAIT/DMA Request Function
WAIT/DMA Request
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Code
Point High
Write Register 2
Reset Ext/Status Interrupts
D7 D6 D5 D4 D3 D2 D1 D0
Send Abort (SDLC)
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
V0
V1
V2
V3
V4
Reset Highest IUS
0
0
1
1
0
1
0
1
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
Interrupt
Vector
* With Point High Command
V5
V6
Write Register 0 (multiplexed bus mode)
D7 D6 D5 D4 D3 D2 D1 D0
V7
Write Register 3
D7 D6 D5 D4 D3 D2 D1 D0
Null Code
0
1
0
1
0
0
1
1
Null Code
Select Shift Left Mode
Select Shift Right Mode
*
Rx Enable
Sync Character Load Inhibit
Address Search Mode (SDLC)
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Code
Null Code
Rx CRC Enable
Enter Hunt Mode
Reset Ext/Status Interrupts
Send Abort
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Auto Enables
Reset Highest IUS
0
0
1
1
0
1
0
1
Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 Bits/Character
0
1
0
1
Null Code
0
0
1
1
Reset Rx CRC Checker
Reset Tx CRC Checker
Reset Tx Underrun/EOM Latch
* B Channel Only
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Write Register 4
Write Register 5
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable
Tx CRC Enable
Parity EVEN/ODD
RTS
SDLC/CRC-16
Tx Enable
Send Break
0
1
0
1
Sync Modes Enable
0
0
1
1
1 Stop Bit/Character
1 1/2 Stop Bits/Character
2 Stop Bits/Character
0
1
0
1
0
0
1
Tx 5 Bits (or Less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
0
1
0
1
0
0
1
1
1
DTR
0
1
0
1
X1 Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode
0
0
1
1
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Write Register 6
D7 D6 D5 D4 D3 D2 D1 D0
Sync6 Sync5 Sync4
Sync7
Sync3
Sync3
Sync3
1
ADR3
x
Sync1 Sync0 Monosync, 8 Bits
Sync2
Sync2
Sync2
1
ADR2
x
Sync4
Sync4
Sync0
ADR4
Monosync, 6 Bits
Sync1 Sync0 Sync5
Sync7 Sync6 Sync5
Sync3 Sync2 Sync1
ADR7 ADR6 ADR5
Sync1 Sync0
Sync1
Sync0 Bisync, 16 Bits
1
ADR1
x
1
Bisync, 12 Bits
ADR0 SDLC
ADR6 ADR5 ADR4
ADR7
x
SDLC (Address Range)
Write Register 7
D7 D6 D5 D4 D3 D2 D1 D0
Sync5
Sync3
Sync13
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
Sync7 Sync6
Sync5 Sync4
Sync15 Sync14
Sync4
Sync2
Sync12
Sync8
1
Sync1
x
Sync9
Sync5
1
Sync2
Sync3
Sync0
x
Sync8
Sync4
0
Sync1 Sync0
Sync11 Sync10
Sync7 Sync6
Sync11
Sync10 Sync9
0
1
1
1
1
WR 7’ Prime (85C30 only)
D7 D6 D5 D4 D3 D2 D1 D0
Auto Tx Flag
Auto EOM Reset
Auto RTS Deactivation
Force TxD High
DTR/REQ Fast Mode
Complete CRC Reception
Extended Read Enable
Reserved (Program as 0)
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Write Register 9
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
VIS
TC0
TC1
TC2
NV
DLC
MIE
TC3
TC4
TC5
TC6
Lower Byte of
Time Constant
Status High/Status Low
Software INTACK Enable
No Reset
0
1
0
1
0
0
1
1
TC7
Channel Reset B
Channel Reset A
Force Hardware Reset
Write Register 13
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
TC8
TC9
6-Bit/8-Bit Sync
Loop Mode
TC10
TC11
TC12
TC13
TC14
Upper Byte of
Time Constant
Abort/Flag on Underrun
Mark/Flag Idle
Go Active on Poll
TC15
0
1
0
1
NRZ
NRZI
FM1 (Transition = 1)
FM1 (Transition = 0)
0
0
1
1
Write Register 14
D7 D6 D5 D4 D3 D2 D1 D0
CRC Preset I/O
BR Generator Enable
BR Generator Source
DTR/Request Function
Auto Echo
Write Register 11
D7 D6 D5 D4 D3 D2 D1 D0
Local Loopback
TRxC Out = Xtal Output
TRxC Out = Transmit Clock
TRxC Out = BR Generator Output
TRxC Out = DPLL Output
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Command
Enter Search Mode
Reset Missing Clock
Disable DPLL
TRxC O/I
Set Source = BR Generator
Set Source = RTxC
Set FM Mode
Set NRZI Mode
0
0
1
1
0
1
0
1
Transmit Clock = RTxC Pin
Transmit Clock = TRxC Pin
Transmit Clock = BR Generator Output
Transmit Clock = DPLL Output
Write Register 15
0
1
0
1
Receive Clock = RTxC Pin
Receive Clock = TRxC Pin
Receive Clock = BR Generator Output
Receive Clock = DPLL Output
0
0
1
1
D7 D6 D5 D4 D3 D2 D1 D0
0
RTxC Xtal/No Xtal
Zero Count IE
SDLC FIFO Enable
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
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Read Register 3
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 0
D7 D6 D5 D4 D3 D2 D1 D0
Channel B Ext/Status IP
Rx Character Available
Zero Count
Channel B Tx IP
Channel B Rx IP
Channel A Ext/Status IP
Channel A Tx IP
Channel A Rx IP
0
Tx Buffer Empty
DCD
*
Sync/Hunt
CTS
Tx Underrun/EOM
0
Break/Abort
* Always 0 in B Channel
Read Register 1
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 10
D7 D6 D5 D4 D3 D2 D1 D0
All Sent
Residue Code 2
Residue Code 1
Residue Code 0
Parity Error
0
On Loop
0
0
Rx Overrun Error
CRC/Framing Error
Loop Sending
0
End of Frame (SDLC)
Two Clocks Missing
One Clocks Missing
Read Register 2
Read Register 12
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
V0
V1
V2
TC0
TC1
TC2
V3
Interrupt
Vector *
TC3
V4
V5
V6
Lower Byte
of Time Constant
TC4
TC5
TC6
V7
TC7
* Modified in B Channel
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Read Register 13
Read Register 15
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
TC8
0
TC9
Zero Count IE
0
TC10
TC11
DCD IE
Upper Byte
of Time Constant
TC12
TC13
TC14
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
TC15
Break/Abort IE
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Address Valid
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Data Valid
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相关型号：
Z85C3010PEG
IC 2 CHANNEL(S), 4.1M bps, MULTI PROTOCOL CONTROLLER, PDIP40, PLASTIC, DIP-40, Serial IO/Communication Controller
ZILOG
Z85C3010PSC/PEC
IC 2 CHANNEL(S), 4.1M bps, MULTI PROTOCOL CONTROLLER, PDIP40, PLASTIC, DIP-40, Serial IO/Communication Controller
ZILOG
Z85C3010PSG
IC 2 CHANNEL(S), 4.1M bps, MULTI PROTOCOL CONTROLLER, PDIP40, PLASTIC, DIP-40, Serial IO/Communication Controller
ZILOG
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