Z86C40 [ZILOG]
CMOS Z8 CONSUMER CONTROLLER PROCESSOR; CMOS Z8消费者控制器处理器
| 型号： | Z86C40 |
| 厂家： | 
ZILOG, INC. |
| 描述： | CMOS Z8 CONSUMER CONTROLLER PROCESSOR |
| 文件： | 总17页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CP96DZ82900
ZILOG
PRELIMINARY
CUSTOMER PROCUREMENT SPECIFICATION
Z86C30/C31/C32/C40
CMOS Z8® CONSUMER
CONTROLLER PROCESSOR
FEATURES
■ 32 Input/Output Lines (C40)
ROM
(KB)
4
2
2
4
RAM*
(Byte)
237
125
237
Speed
(MHz)
16
12
12
24 Input/Output Lines (C3X)
Part
Z86C30
Z86C31
Z86C32
Z86C40
■ Vectored, Prioritized Interrupts with
Programmable Polarity
236
16
■ Two Analog Comparators
* General-Purpose
■ Two Programmable 8-Bit Counter/Timers,
■ 28-Pin DIP, 28-Pin SOIC, 28-Pin PLCC Packages
(Z86C3X)
Each with Two 6-Bit Programmable Prescaler
40-Pin DIP, 44-Pin PLCC/QFP Packages (Z86C40)
■ Watch-Dog Timer/Power-On Reset
■ 3.0V to 5.5V Operating Range
■ Low-Power Consumption
■ On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock
■ RAM and ROM Protect
■ –40°C to +105°C Operating Range
■ Expanded Register File (ERF)
GENERAL DESCRIPTION
The Z86C3X/C40 Consumer Controller Processors
(CCP) are members of the Z8® single-chip microcontroller
family offering a unique register-to-register architecture
thatavoidsaccumulatorbottlenecksandoffersfastexecu-
tion of code.
Two on-chip counter/timers, with a large number of select-
able modes, offload the system of administering real-time
tasks such as counting/timing and I/O data communica-
tions.
With ROM/ROMless selectivity, the Z86C40 provides both
external memory and pre-programmed ROM, which
enables these Z8 microcontrollers to be used in high-
volume applications, or where code flexibility is required.
Three address spaces (Program Memory, Register File,
and Expanded Register File [ERF]), support a wide range
of memory configurations. Through the ERF, the designer
has access to three additional control registers that pro-
vide extra peripheral devices, I/O ports, and
register addresses. The rest of the ERF is not physically
implemented and is open for future expansion.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
For applications demanding powerful I/O capabilities, the
Z86C3X/C40's dedicated input and output lines are
grouped into three and four ports, respectively, and are
configurable under software control to provide timing,
status signals, or parallel I/O.
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
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Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
GENERAL DESCRIPTION (Continued)
Vcc
GND
Output Input
/AS /DS R//W /RESET
XTAL
(Only on Z86C40)
Machine Timing
&
Port 3
Instruction Control
RESET
WDT, POR
Counter/
Timers (2)
ALU
FLAGS
Prg. Memory
4K
Interrupt
Control
Register
Pointer
Two Analog
Program
Counter
Comparators
Register File
Port 0
Port 1
8
Port 2
4
4
I/O
Address or I/O
(Nibble Programmable)
Address/Data or I/O
(Byte Programmable)
(Bit Programmable)
(Only on Z86C40)
Functional Block Diagram
2
CP96DZ82900
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
PIN DESCRIPTION
28-Pin DIP/SOIC/PLCC Pin Identification
P25
P26
P27
P04
P05
P06
P07
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P24
P23
Pin # Symbol Function
Direction
1-3
4-7
8
P27-25
P07-04
VCC
Port 2, Pins 5,6,7
Port 0, Pins 4,5,6,7 In/Output
Power Supply
In/Output
P22
P21
P20
9
XTAL2
Crystal Oscillator
Output
10
XTAL1
Crystal Oscillator
Port 3, Pins 1,2,3
Port 3, Pins 4,5
Port 3, Pin 7
Input
P03
11-13 P33-31
14-15 P35-4
16
17
Fixed Input
Fixed Output
Fixed Output
Fixed Output
Z86C30
Z86C31
Z86C32
GND
P37
P36
VCC
P02
P01
Port 3, Pin 6
XTAL2
18
P30
Port 3, Pin 0
Port 0, Pins 0,1,2
Ground, V
Fixed Input
In/Output
P00
P30
P36
P37
P35
10
11
XTAL1
P31
19-21 P02-00
22
23
GND
P03
Port 0, PinS3S
In/Output
P32
12
13
14
24-28 P24-20
Port 2, Pins 0,1,2,3,4 In/Output
P33
P34
P04
P27
P26
P25
P24
P23
P22
28-Pin DIP Configuration
4
26
1
5
25
PX0X5X
P06
P07
VDD
XT2
XT1
P31
XPX21X
P20
P03
VSS
P02
P01
P00
Z86C30
Z86C31
Z86C32
P24
P23
P22
P21
P20
P03
VSS
P02
1
2
3
4
5
6
7
8
P25
P26
P27
P04
28
27
26
25
24
23
22
21
19
18
11
12
P05
P06
P34
P35
P37
P36
P30
P32
P33
P07
VDD
XTAL2
XTAL1
P31
Z86C30
Z86C31
Z86C32
28-Pin PLCC Configuration
20
19
18
17
9
P01
P00
P30
10
11
12
P32
P33
P34
P36
P37
P35
13
14
16
15
28-Pin SOIC Configuration
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Z86C30/C31/C32/C40
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ZILOG
PIN DESCRIPTION (Continued)
1
2
3
4
5
6
7
8
9
R//W
P25
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
/DS
P24
P23
P22
P21
P20
P03
P13
P12
GND
P02
P11
P26
P27
P04
P05
P06
P14
P15
Z86C40
P07
10
11
VCC
P16
12
13
14
15
16
17
18
19
20
P17
P10
P01
P00
P30
P36
P37
P35
/RESET
XTAL2
XTAL1
P31
P32
P33
P34
/AS
40-Pin DIP Assignments
40-Pin Dual-In-Line Package Pin Identification
Pin # Symbol Function
Direction
Pin # Symbol Function
Direction
1
R//W
Read/Write
Output
22
23
24
25
P35
P37
P36
P30
Port 3, Pin 5
Port 3, Pin 7
Port 3, Pin 6
Port 3, Pin 0
Output
Output
Output
Input
2-4
5-7
8-9
P25-27
P04-06
P14-15
Port 2, Pins 5,6,7
Port 0, Pins 4,5,6
Port 1, Pins 4,5
In/Output
In/Output
In/Output
10
11
P07
VCC
Port 0, Pin 7
Power Supply
Port 1, Pins 6,7
In/Output
26-27 P00-01
28-29 P10-11
Port 0, Pin 0,1
Port 1, Pin 0,1
Port 0, Pin 2
In/Output
In/Output
In/Output
12-13 P16-17
14
In/Output
30
31
P02
GND
XTAL2
Crystal, Oscillator Clock Output
Ground, GND
15
XTAL1
Crystal, Oscillator Clock Input
32-33 P12-13
34 P03
35-39 P20-24
40 /DS
Port 1, Pin 2,3
Port 0, Pin 3
Port 2, Pin 0,1,2,3,4
Data Strobe
In/Output
In/Output
In/Output
Output
16-18 P31-33
Port 3, Pins 1,2,3
Port 3, Pin 4
Input
19
20
21
P34
/AS
Output
Output
Input
Address Strobe
/RESET Reset
4
CP96DZ82900
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
PIN DESCRIPTION (Continued)
6
5
4
3
2
1
44 43 42 41 40
P21
P22
P23
P24
/DS
39
38
37
36
35
34
33
32
31
30
29
P30
7
8
P36
9
P37
10
11
12
13
14
15
16
17
P35
/RESET
R//RL
/AS
N/C
R//W
P25
P26
P27
P04
Z86C40
P34
P33
P32
P31
18 19 20 21 22 23 24 25 26 27 28
44-Pin PLCC Pin Assignments
44-Pin PLCC Pin Identification
Pin # Symbol Function
Direction
Pin # Symbol Function
Direction
1-2
3-4
5
GND
P12-13
P03
Ground, GND
Port 1, Pins 2,3
Port 0, Pin 3
Port 2, Pins 0,1,2,3,4
Data Strobe
28 XTAL1 Crystal, Oscillator Clock Input
In/Output
In/Output
In/Output
Output
29-31 P31-33
Port 3, Pins 1,2,3
Port 3, Pin 4
Input
Output
Output
32
33
34
P34
6-10 P20-24
11
/AS
Address Strobe
/DS
R//RL
ROM/ROMless Control Input
12
13
N/C
R//W
Not Connected
Read/Write
Port 2, Pins 5,6,7
Port 0, Pins 4,5,6
Port 1, Pins 4,5
35
36
37
38
39
/RESET Reset
Input
Output
P35
P37
P36
P30
Port 3, Pin 5
Output
Output
Output
Input
14-16 P25-27
17-19 P04-06
20-21 P14-15
In/Output
In/Output
In/Output
Port 3, Pin 7
Port 3, Pin 6
Port 3, Pin 0
22
P07
Port 0, Pin 7
Power Supply
Port 1, Pins 6,7
In/Output
40-41 P00-01
42-43 P10-11
Port 0, Pins 0,1
Port 1, Pins 0,1
Port 0, Pin 2
In/Output
In/Output
In/Output
23-24 VCC
25-26 P16-17
In/Output
44
P02
27
XTAL2
Crystal, Oscillator Clock Output
CP96DZ82900
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Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
PIN DESCRIPTION (Continued)
33 32 31 30 29 28 27 26 25 24 23
P21
P22
P23
P24
/DS
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P30
P36
P37
P35
/RESET
R//RL
/AS
N/C
R//W
P25
P26
P27
P04
Z86C40
P34
P33
P32
P31
1
2
3
4
5
6
7
8
9 10 11
44-Pin QFP Pin Assignments
44-Pin QFP Pin Identification
Pin # Symbol Function
Direction
Pin # Symbol Function
Direction
1-2
3-4
5
6-7
8-9
P05-06
P14-15
P07
Port 0, Pins 5,6
Port 1, Pins 4,5
Port 0, Pin 7
Power Supply
Port 1 Pins 6,7
In/Output
In/Output
In/Output
21
22
P36
P30
Port 3, Pin 6
Port 3, Pin 0
Port 0, Pins 0,1
Port 1, Pins 0,1
Port 0, Pin 2
Output
Input
In/Output
In/Output
In/Output
23-24 P00-01
25-26 P10-11
27
V
PC1C6-17
In/Output
P02
10
11
XTAL2
XTAL1
Crystal, Oscillator Clock Output
Crystal, Oscillator Clock Input
28-29 GND
30-31 P12-13
Ground, GND
Port 1, Pins 2,3
Port 0, Pin 3
Port 2, Pins 0,1,2,3,4
Data Strobe
In/Output
In/Output
In/Output
Output
12-14 P31-33
15
16
Port 3, Pins 1,2,3
Port 3, Pin 4
Input
Output
Output
32
P03
P34
/AS
33-37 P20-24
Address Strobe
38
/DS
17
18
19
20
R//RL
/RESET Reset
P35
P37
ROM/ROMless Control Input
39
40
N/C
R//W
Not Connected
Read/Write
Port 2, Pins 5,6,7
Port 0, Pin 4
Input
Output
In/Output
In/Output
Port 3, Pin 5
Port 3, Pin 7
Output
Output
41-43 P25-27
44 P04
6
CP96DZ82900
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to VSS [Note 1]
Voltage on VDD Pin with Respect to VSS
Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2]
Total Power Dissipation
Maximum Allowable Current out of VSS
Maximum Allowable Current into VDD
Maximum Allowable Current into an Input Pin [Note 3]
Maximum Allowable Current into an Open-Drain Pin [Note 4]
Maximum Allowable Output Current Sinked by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
–40
–65
–0.6
–0.3
–0.6
+105
+150
+7
C
C
V
V
V
+7
VDD+1
1.21
220
W
mA
mA
µA
µA
mA
mA
180
–600
–600
+600
+600
25
25
Notes:
[1] This applies to all pins except XTAL pins and where otherwise noted.
[2] There is no input protection diode from pin to VDD
.
[3] This excludes XTAL pins.
[4] Device pin is not at an output Low state.
Notice:
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the
operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an
extended period may affect device reliability.
Total power dissipation should not exceed 1.21 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [ I – (sum of IOH) ]
+ sum DoDf [ (VDD – V ) x IOH
]
+ sum of (V0L x I0L) OH
STANDARD TEST CONDITIONS
From Output
Under Test
The characteristics listed below apply for standard test
conditionsasnoted.AllvoltagesarereferencedtoGround.
Positive current flows into the referenced pin (Test Load).
150 pF
Test Load Diagram
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND.
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
0
0
0
12 pF
12 pF
12 pF
CP96DZ82900
7
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
DC ELECTRICAL CHARACTERISTICS
TA = 0°C
to +70°C
Typical [1]
@
VCC
Sym Parameter
Note [3]
Min
Max
25°C
Units
Conditions
Notes
V
Clock Input High Voltage 3.0V
0.7 V
V +0.3
1.3
2.5
V
V
Driven by External Clock Generator
Driven by External Clock Generator
CH
CC
CC
5.5V
0.7 V
V +0.3
CC
CC
V
Clock Input Low Voltage 3.0V
GND-0.3 0.2 V
0.7
1.5
1.3
2.5
V
V
V
V
Driven by External Clock Generator
Driven by External Clock Generator
CL
CC
5.5V
3.0V
5.5V
GND-0.3 0.2 V
CC
V
Input High Voltage
Input Low Voltage
0.7 V
V +0.3
CC
IH
CC
0.7 V
V +0.3
CC
CC
V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
GND-0.3 0.2 V
0.7
1.5
3.1
4.8
3.1
4.8
V
V
V
V
V
V
IL
CC
GND-0.3 0.2 V
CC
V
Output High Voltge
Low EMI Mode
V –0.4
IOH = – 0.5 mA
IOH = – 0.5 mA
IOH = – 2.0 mA
IOH = – 2.0 mA
OH
CC
V –0.4
CC
V
Output High Voltage
V –0.4
[8]
[8]
OH1
CC
V –0.4
CC
V
Output Low Voltage
Low EMI Mode
Output Low Voltage
3.0V
5.5V
3.0V
5.0V
3.0V
5.5V
0.6
0.4
0.6
0.4
1.2
1.2
0.3
0.2
0.2
0.1
0.5
0.5
V
V
V
V
V
V
IOL = 1.0 mA
IOL = 1.0 mA
IOL = + 4.0 mA
IOL = + 4.0 mA
IOL = + 6 mA
OL
V
[8]
[8]
[8]
[8]
OL1
V
Output Low Voltage
OL2
IOL = + 12 mA
V
Reset Input High Voltage 3.0V
.8 V
V
V
1.5
2.1
1.1
1.7
0.3
0.2
V
V
[7]
[7]
[7]
[7]
[7]
[7]
RH
CC
CC
5.5V
Reset Input Low Voltage 3.0V
5.5V
Reset Outut Low Voltage 3.0V
5.5V
.8 V
CC
V
GND–0.3 0.2CVC
RL
CC
GND–0.3 0.2 V
V
0.6CC
0.6
V
V
IOL = +1.0 mA
IOL = +1.0 mA
OLR
V
Comparator Input Offset 3.0V
25
25
10
10
mV
mV
V
V
µA
µA
OFFSET
Voltage
5.5V
3.0V
5.5V
3.0V
5.5V
V
Input Common Mode
Voltage Range
Input Leakage
GND-0.3 V –1.0V
GND-0.3 V –1.0V
[10]
[10]
ICR
CC
CC
I
–1
–1
2
2
0.064
0.064
V = OV, V
CC
IL
IN
V = OV, V
IN
CC
IOL
Output Leakage
3.0V
5.5V
3.0V
5.5V
–1
–1
–20
–20
2
2
–130
–180
0.114
0.114
–62
µA
µA
µA
µA
V = OV, V
IN
CC
V = OV, V
IN
CC
I
Reset Input Current
IR
–112
ICC
Supply Current
3.0V
5.5V
3.0V
5.5V
20
25
15
20
7
20
5
mA
mA
mA
mA
@ 16 MHz
@ 16 MHz
@ 12 MHz
@ 12 MHz
[4,5]
[4,5]
[4,5]
[4,5]
15
8
CP96DZ82900
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
DC ELECTRICAL CHARACTERISTICS (Continued)
TA = 0°C
to +70°C
Typical [1]
VCC
@
Sym Parameter
Note [3]
Min
Max
25°C
Units
Conditions
Notes
ICC1
Standby Current
(Halt Mode)
3.0V
5.5V
3.0V
5.5V
4.5
8
4
2.0
3.7
1.5
3.2
mA
mA
mA
mA
V = 0V, V @ 16 MHz
[4,5]
[4,5]
[4,5]
[4,5]
IN
CC
V = 0V, V @ 16 MHz
IN
CC
V = 0V, V @ 12 MHz
IN CC
6
V = 0V, V @ 12 MHz
IN CC
3.0V
5.5V
3.0V
5.5V
3.4
7.0
3
1.5
2.9
1.2
2.5
mA
mA
mA
mA
Clock Divide by 16 @ 16 MHz
Clock Divide by 16 @ 16 MHz
Clock Divide by 16 @ 12 MHz
Clock Divide by 16 @ 12 MHz
[4,5]
[4,5]
[4,5]
[4,5]
5
ICC2
Standby Current
(Stop Mode)
3.0V
5.5V
3.0V
5.5V
8
2
µA
µA
µA
µA
V = OV, V
[6,11]
[6,11]
[6,11]
[6,11]
IN
CC
WDT is not Running
V = OV, V
10
4
IN
CC
WDT is not Running
V = OV, V
500
800
310
600
IN
CC
WDT is Running
V = OV, V
IN
CC
WDT is Running
IALL
Auto Latch
3.0V
0.7
8
2.4
µA
OV < V < V
[9]
IN
CC
Low Current
5.5V
3.0V
1.4
–0.6
15
–5
4.7
–1.8
µA
µA
OV < V < V
[9]
[9]
IN
CC
IALH
Auto Latch
OV < V < V
IN
CC
High Current
5.5V
–1
–8
–3.8
µA
OV < V < V
[9]
IN
CC
T
Power On Reset
3.0V
5.5V
3
2.0
2.05
24
13
2.95
10
4
2.6
mS
mS
V
POR
V
Low Voltage Protection
6 MHz max INT CLK Freq.
[7]
LV
Note:
[1] Typicals are at VCC = 5.0V and 3.3V.
[2] GND = 0V.
[3] The VCC voltage spec. of 3.0V guarantees 3.3V ± 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V ± 0.5V.
[4] All outputs unloaded, I/O pins floating, inputs at rail.
[5] CL1= CL2 = 10 pF.
[6] Same as note [4] except inputs at VCC
[7] Z86C40 only.
.
[8] STD Mode (not Low-EMI Mode).
[9] Auto Latch (mask option) selected.
[10] For analog comparator inputs when analog comparators are enabled.
[11] Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating.
CP96DZ82900
9
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
DC ELECTRICAL CHARACTERISTICS
TA=–40°C
to 105°C
Typical [1]
@
VCC
Sym Parameter
Note [3]
Min
Max
25°C
Units
Conditions
Notes
V
Clock Input High Voltage 3.0V
5.5V
0.7 V
V +0.3
1.3
2.5
V
V
Driven by External Clock Generator
Driven by External Clock Generator
CH
CC
CC
0.7 V
V +0.3
CC
CC
V
Clock Input Low Voltage 3.0V
5.5V
GND-0.3
GND-0.3
0.2 V
0.7
1.5
1.3
2.5
V
V
V
V
Driven by External Clock Generator
Driven by External Clock Generator
CL
CC
0.2 V
CC
V
Input High Voltage
3.0V
5.5V
0.7 V
V +0.3
IH
CC
CC
0.7 V
V +0.3
CC
CC
V
Input Low Voltage
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
GND-0.3
GND-0.3
0.2 V
0.7
1.5
3.1
4.8
3.1
4.8
V
V
V
V
V
V
IL
CC
0.2 V
CC
V
Output High Voltage
Low EMI Mode
Output High Voltage
V –0.4
IOH = – 0.5 mA
IOH = – 0.5 mA
IOH = – 2.0 mA
IOH = – 2.0 mA
OH
CC
V –0.4
CC
V
V –0.4
[8]
[8]
OH1
CC
V –0.4
CC
V
Output Low Voltage
Low EMI Mode
Output Low Voltage
3.0V
5.5V
3.0V
5.0V
3.0V
5.5V
0.6
0.4
0.6
0.4
1.2
1.2
0.3
0.2
0.2
0.1
0.5
0.5
V
V
V
V
V
V
IOL = 1.0 mA
IOL = 1.0 mA
IOL = + 4.0 mA
IOL = + 4.0 mA
IOL = + 6 mA
OL
V
[8]
[8]
[8]
[8]
OL1
V
Output Low Voltage
OL2
IOL = + 12 mA
V
Reset Input High Voltage 3.0V
.8 V
V
1.5
2.1
1.1
1.7
0.4
0.3
V
V
[7]
[7]
[7]
[7]
[7]
[7]
RH
CC
CC
5.5V
Reset Input Low Voltage 3.0V
5.5V
Reset Output Low Voltage 3.0V
5.5V
.8 V
V
CC
V
GND–0.3
GND–0.3
0.2CVC
RL
CC
0.2 V
0.6CC
0.6
V
V
V
IOL = + 1.0 mA
IOL = + 1.0 mA
OLR
V
Comparator Input Offset 3.0V
25
25
10
10
mV
mV
V
V
µA
µA
OFFSET
Voltage
5.5V
3.0V
5.5V
3.0V
5.5V
V
Input Common Mode
Voltage Range
Input Leakage
GND–0.3 V –1.5V
GND–0.3 V –1.5V
[10]
[10]
ICR
CC
CC
I
–1
–1
2
2
<1
<1
V = OV, V
CC
IL
IN
V = OV, V
IN
CC
IOL
Output Leakage
3.0V
5.5V
3.0V
5.5V
–1
–1
–18
–18
2
2
–130
–180
<1
<1
–62
–112
µA
µA
µA
µA
V = OV, V
IN
CC
V = OV, V
IN
CC
I
Reset Input Current
IR
ICC
Supply Current
3.0V
5.5V
3.0V
5.5V
20
25
15
20
7
20
5
mA
mA
mA
mA
@ 16 MHz
@ 16 MHz
@ 12 MHz
@ 12 MHz
[4,5]
[4,5]
[4,5]
[4,5]
15
10
CP96DZ82900
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
DC ELECTRICAL CHARACTERISTICS (Continued)
TA = –40°C
to 105°C
Typical [1]
@
VCC
Sym Parameter
Note [3]
Min
Max
25°C
Units
Conditions
Notes
ICC1
Standby Current
(Halt Mode)
3.0V
5.5V
3.0V
5.5V
4.5
8
4
2.0
3.7
1.5
3.2
mA
mA
mA
mA
V = 0V, V @ 16 MHz
[4,5]
[4,5]
[4,5]
[4,5]
IN
CC
V = 0V, V @ 16 MHz
IN
CC
V = 0V, V @ 12 MHz
V IN= 0V, V CC@ 12 MHz
6
IN
CC
3.0V
5.5V
3.0V
5.5V
3.4
7.0
3
1.5
2.9
1.2
2.5
mA
mA
mA
mA
Clock Divide by 16 @ 16 MHz
Clock Divide by 16 @ 16 MHz
Clock Divide by 16 @ 12 MHz
Clock Divide by 16 @ 12 MHz
[4,5]
[4,5]
[4,5]
[4,5]
5
ICC2
Standby Current
(Stop Mode)
3.0V
5.5V
3.0V
5.5V
8
2
µA
µA
µA
µA
V = OV, V
[6,11]
[6,11]
[6,11]
[6,11]
IN
CC
WDT is not Running
V = OV, V
10
4
IN
CC
WDT is not Running
V = OV, V
600
1000
310
600
IN
CC
WDT is Running
V = OV, V
IN
CC
WDT is Running
IALL
Auto Latch Low Current 3.0V
5.5V
0.7
1.4
–0.6
–1.0
10
20
–7
2.4
4.7
–1.8
–3.8
µA
µA
µA
µA
OV < V < V
[9]
[9]
[9]
[9]
IN
CC
OV < V < V
IN
CC
IALH Auto Latch High Current 3.0V
5.5V
OV < V < V
IN
CC
–10
OV < V < V
IN
CC
T
Power On Reset
3.0V
5.5V
3.0
2.0
1.8
25
14
3.3
7
4
2.6
mS
mS
V
POR
V
Low Voltage Protection
4 MHz max INT CLK Freq.
LV
Note:
[1] Typicals are at VCC = 5.0V and 3.3V.
[2] GND=0V.
[3] The VCC voltage spec. of 3.0V guarantees 3.3V ± 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V ± 0.5V.
[4] All outputs unloaded, I/O pins floating, inputs at rail.
[5] CL1= CL2 = 100pF.
[6] Same as note [4] except inputs at VCC
[[7] Z86C40 only.
.
[8] STD Mode (not Low EMI Mode).
[9] Auto Latch (mask option) selected.
[10] For analog comparator inputs when analog comparators are enabled.
[11] Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating.
[7] Z86C40 only.
CP96DZ82900
11
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Diagram (Z86C40 Only)
R//W, /DM
13
19
12
Port 0
16
20
3
18
1
Port 1
/AS
A7 - A0
D7 - D0 IN
2
9
8
11
4
5
6
/DS
(Read)
17
10
Port1
A7 - A0
D7 - D0 OUT
14
15
7
/DS
(Write)
External I/O or Memory Read/Write Timing
(Z86C40 Only)
12
CP96DZ82900
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table (Z86C40 Only)
(SCLK/TCLK = XTAL/2)
TA=–40°C to 105°C
Note [3] 12 MHz 16 MHz
Min Max Min Max Min Max Min Max Units Notes
TA = –40°C to +105°C
12 MHz 16 MHz
No Symbol Parameter
VCC
1 TdA(AS) Address Valid to /AS Rise Delay
3.0
5.5
3.0
5.5
35
35
45
45
25
25
35
35
35
35
45
45
25
25
35
35
ns
ns
ns
ns
[2]
[2]
2 TdAS(A) /AS Rise to Address Float Delay
3 TdAS(DR) /AS Rise to Read Data Req’d Valid
3.0
5.5
3.0
5.5
250
250
180
180
250
250
180
180
ns
ns
ns
ns
[1,2]
[2]
4 TwAS
/AS Low Width
55
55
40
40
55
55
40
40
5 TdAS(DS) Address Float to /DS Fall
6 TwDSR /DS (Read) Low Width
3.0
5.5
3.0
5.5
0
0
200
200
0
0
135
135
0
0
200
200
0
0
135
135
ns
ns
ns
ns
[1,2]
7 TwDSW /DS (Write) Low Width
3.0
5.5
3.0
5.5
110
110
80
80
110
110
80
80
ns
ns
ns
ns
[1,2]
[1,2]
8 TdDSR(DR) /DS Fall to Read Data Req’d Valid
150
150
75
75
150
150
75
75
9 ThDR(DS) Read Data to /DS Rise Hold Time
10 TdDS(A) /DS Rise to Address Active Delay
3.00
5.5
3.0
5.5
0
0
45
55
0
0
50
50
0
0
45
55
0
0
50
50
ns
ns
ns
ns
[2]
[2]
11 TdDS(AS) /DS Rise to /AS Fall Delay
12 TdR/W(AS) R//W Valid to /AS Rise Delay
3.0
5.5
3.0
5.5
30
45
45
45
35
35
25
25
30
45
45
45
35
55
25
25
ns
ns
ns
ns
[2]
[2]
13 TdDS(R/W) /DS Rise to R//W Not Valid
3.0
5.5
45
45
55
55
35
35
25
25
45
45
55
55
35
35
25
25
ns
ns
ns
ns
[2]
[2]
14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0
5.5
15 TdDS(DW) /DS Rise to Write Data Not Valid Delay
16 TdA(DR) Address Valid to Read Data Req’d Valid
3.0
5.5
3.0
5.5
45
45
35
35
45
45
35
35
ns
ns
ns
ns
[2]
310
310
230
230
310
310
230
230
[1,2]
17 TdAS(DS) /AS Rise to /DS Fall Delay
18 TdDM(AS) /DM Valid to /AS Fall Delay
19 TdDS(DM) /DS Rise to DM Valid Delay
20 ThDS(AS) /DS Valid to Address Valid Hold Time
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
65
65
35
35
45
45
45
45
45
45
30
30
35
35
35
35
65
65
35
35
45
45
45
45
45
45
30
30
35
35
35
35
ns
ns
ns
ns
ns
ns
ns
ns
[2]
[2]
Standard Test Load
Notes:
All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0,
D0 = 0.
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] The VCC voltage specification of 3.0V guarantees 3.3V± 0.3V, and the
VDD voltage specification of 5.5V guarantees 5.0V ± 0.5V.
CP96DZ82900
13
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
AC ELECTRICAL CHARACTERISTICS
Additional Timing Diagram
3
1
Clock
2
2
3
7
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Additional Timing
14
CP96DZ82900
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table (Divide-By-One Mode)
TA = 0°C to +70°C
TA = 40°C to +105°C
VCC
4 MHz
4 MHz
No Symbol Parameter
Note [6]
Min Max
Min
Max
Units
Notes
1
2
TpC
Input Clock Period
3.0V
5.5V
3.0V
5.5V
250
250
DC
DC
25
250
250
DC
DC
25
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
TrC,TfC
Clock Input Rise & Fall Times
25
25
3
4
TwC
Input Clock Width
3.0V
5.5V
3.0V
5.5V
100
100
100
70
100
100
100
70
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
TwTinL
Timer Input Low Width
5
6
TwTinH
TpTin
Timer Input High Width
Timer Input Period
3.0V
5.5V
3.0V
5.5V
5TpC
5TpC
8TpC
8TpC
5TpC
5TpC
8TpC
8TpC
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
7
TrTin,
TfTin
Timer Input Rise & Fall Timer
Int. Request Low Time
3.0V
5.5V
3.0V
5.5V
100
100
100
100
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,2,7,8]
[1,2,7,8]
8A TwIL
100
70
100
70
8B TwIL
Int. Request Low Time
3.0V
5.5V
3.0V
5.5V
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
[1,3,7,8]
[1,3,7,8]
[1,2,7,8]
[1,2,7,8]
9
TwIH
Int. Request Input High Time
10 Twsm
11 Tost
STOP Mode Recovery Width Spec 3.0V
5.5V
12
12
12
12
ns
ns
[4,8]
[4,8]
[4,8,9]
[4,8,9]
Oscillator Start-up Time
3.0V
5.5V
5TpC
5TpC
5TpC
5TpC
Notes:
[1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
[2] Interrupt request via Port 3 (P31-P33).
[3] Interrupt request via Port 3 (P30).
[4] SMR-D5 = 1, POR STOP Mode Delay is on.
[5] Reg. WDTMR.
[6] The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and
the VDD voltage specification of 5.5V guarantees 5.0V ± 0.5V.
[7] SMR D1 = 0.
[8] Maximum frequency for internal system clock is 4 MHz when
using XTAL divide-by-one mode.
[9] For RC and LC oscillator, and for oscillator driven by clock driver.
CP96DZ82900
15
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table
TA = –40°C to +105°C
TA = 0°C to +70°C
VCC
16 MHz
12 MHz
No Symbol
Parameter
Note [6]
Min
Max
Min
Max
Units
Notes
1
2
TpC
Input Clock Period
3.0V
5.5V
3.0V
5.5V
62.5
62.5
DC
DC
15
83
83
DC
DC
15
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
TrC,TfC
Clock Input Rise & Fall Times
15
15
3
4
TwC
Input Clock Width
3.0V
5.5V
3.0V
5.5V
31
31
100
70
26
26
100
70
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
TwTinL
Timer Input Low Width
5
6
TwTinH
TpTin
Timer Input High Width
Timer Input Period
3.0V
5.5V
3.0V
5.5V
5TpC
5TpC
8TpC
8TpC
5TpC
5TpC
8TpC
8TpC
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
7
TrTin,
TfTin
Timer Input Rise & Fall Timer
Int. Request Low Time
3.0V
5.5V
3.0V
5.5V
100
100
100
100
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,2,7,8]
[1,2,7,8]
8A TwIL
100
70
100
70
8B TwIL
Int. Request Low Time
3.0V
5.5V
3.0V
5.5V
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
[1,3,7,8]
[1,3,7,8]
[1,2,7,8]
[1,2,7,8]
9
TwIH
Int. Request Input High Time
10 Twsm
11 Tost
STOP Mode Recovery Width Spec 3.0V
5.5V
12
12
12
12
ns
ns
[4,8]
[4,8]
[4,8]
[4,8]
Oscillator Start-up Time
3.0V
5.5V
5TpC
5TpC
5TpC
5TpC
12 Twdt
Watch-Dog Timer Delay Time
Before Refresh
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
10
5
10
5.0
20
10
40
20
160
80
ms
ms
ms
ms
ms
ms
ms
ms
D0 = 0 [5,11]
D1 = 0 [5,11]
D0 = 1 [5,11]
D1 = 0 [5,11]
D0 = 0 [5,11]
D1 = 1 [5,11]
D0 = 1 [5,11]
D1 = 1 [5,11]
20
10
40
20
160
80
Notes:
[1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
[2] Interrupt request via Port 3 (P31-P33).
[3] Interrupt request via Port 3 (P30).
[4] SMR-D5 = 1, POR STOP Mode Delay is on.
[5] Reg. WDTMR.
[6] The VCC voltage spec. of 3.0V guarantees 3.3V ± 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V ± 0.5V.
[7] SMR D1 = 0.
[8] Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode.
[9] For RC and LC oscillator, and for oscillator driven by clock driver.
[10] Standard Mode (not Low EMI output ports).
[11] Using internal RC.
16
CP96DZ82900
Z86C30/C31/C32/C40
CP96DZ82900
ZILOG
AC ELECTRICAL CHARACTERISTICS
Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
1
2
3
/DAV
Delayed DAV
(Input)
4
5
6
RDY
Delayed RDY
(Output)
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV
Delayed DAV
(Output)
8
9
11
10
RDY
Delayed RDY
(Input)
Output Handshake Timing
©1997byZilog, Inc. Allrightsreserved. Nopartofthisdocument
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
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provisions appearing in Zilog, Inc. Terms and Conditions of Sale
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Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
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CP96DZ82900
17
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